ISL6744AABZ

DATASHEET ISL6744A FN6554 Rev.1.00 Aug 25, 2017 Intermediate Bus PWM Controller The ISL6744A is a low cost, primary side, double-ended controller intended for applications using full and half-bridge topologies for unregulated DC/DC converters. It is a voltage-mode PWM controller designed for half-bridge and full-bridge power supplies. It provides precise switching frequency control, adjustable soft-start, precise dead time control with dead times as low as 35ns, and overcurrent shutdown. The ISL6744A is identical to the ISL6744, but is optimized for higher noise environments. Low start-up and operating currents allow for easy biasing in both AC/DC and DC/DC applications. This advanced BiCMOS design features low start-up and operating currents, adjustable switching frequency up to 1MHz, 1A FET drivers, and very low propagation delays for a fast response to overcurrent faults. Related Literature • For a full list of related documents, visit our website • ISL6744A product page Features • Precision duty cycle and dead time control • 100µA start-up current • Adjustable delayed overcurrent shutdown and restart • Adjustable oscillator frequency up to 2MHz • 1A MOSFET gate drivers • Adjustable soft-start • Internal over-temperature protection • 35ns control to output propagation delay • Small size and minimal external component count • Input undervoltage protection • Pb-free (RoHS compliant) Applications • Telecom and datacom isolated power • DC transformers • Bus converters FN6554 Rev.1.00 Aug 25, 2017 Page 1 of 27 ISL6744A Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 1.2 1.3 1.4 1.5 2. Internal Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 5 5 6 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 2.3 2.4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 7 7 3. Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 4.2 4.3 4.4 4.5 4.6 4.7 5. Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft-Start Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground Plane Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 11 11 11 11 Typical Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Circuit Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transformer Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOSFET Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Component Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Limit Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 13 16 17 18 19 20 21 6. Component List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8. Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9. About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FN6554 Rev.1.00 Aug 25, 2017 Page 2 of 27 1.1 Overview ISL6744A FN6554 Rev.1.00 Aug 25, 2017 1. Internal Architecture V DD FL V DD VBIAS VBIAS 5.00V + BG OUTA Q T UVLO Q OUTB PWM Toggle Internal OT Shutdown 130 - 150 C V BIAS 70µA GND ON SS VBIAS SS Clamp RTD + 2.0V IRTD + - 4.0V 15µA 3.9V S Q VBIAS R Q 160µA OC Latch ON 2.8V + PE AK + Valley S Q CLK R Q CT 0.8V IDCH= 55 x IRTD + - SS Charged Reset Dominant Q SS LOW Q 50µs Retriggerable One Shot Fault Latch SS Set Dominant S Q S Q IDCH PWM Latch LATCH Set Dominant VBIAS V BIAS UV 4.65V 4.80V  CS 0.6V + - FL R Q R Q ON 0.27V + - + BG OC Detect SS Comparator CT + - Figure 1. Block Diagram SS 1. Overview Page 3 of 27 0.8 Typical Application SP1 VIN+ +12V QR1 L1 C11 QH ISL6744A FN6554 Rev.1.00 Aug 25, 2017 1.2 QR3 C2 T1 L3 R8 C9 C13 R10 TP1 C8 RTN L2 C1 T2 R9 QR4 QR2 QL R2 C14 CR3 R11 C12 CR2 C3 R1 TP2 CR1 C7 U4 ISL6700 VDD HB LO VSS HO HS LI HI R6 R5 TP4 C10 C4 C5 TP5 U1 OUTB OUTA VDD R7 ISL6744A GND VIN- SS CS CT C18 RTD D2 TP6 Q5 C15 C16 D1 R12 C6 1. Overview Page 4 of 27 Figure 2. Typical Application Using ISL6744A - 48V Input DC Transformer, 12V at 8A Output ISL6744A 1.3 1. Overview Ordering Information Part Number (Notes 1, 2, 3) Temp. Range (°C) Part Marking Package (RoHS Compliant) Pkg. Dwg. # ISL6744AAUZ 6744A -40 to +105 8 Ld MSOP M8.118 ISL6744AABZ 6744A ABZ -40 to +105 8 Ld SOIC M8.15 Notes: 1. Add “-T” suffix for 2.5k for tape and reel option. Refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), see the product information page for ISL6744A. For more information on MSL, refer to TB363. 1.4 Pin Configuration ISL6744A (SOIC, MSOP) Top View SS 1 FN6554 Rev.1.00 Aug 25, 2017 8 VDD RTD 2 7 OUTB CS 3 6 OUTA CT 4 5 GND Page 5 of 27 ISL6744A 1.5 1. Overview Pin Descriptions Pin Pin Name Number Description SS 1 Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The value of the capacitor determines the rate of increase of the duty cycle during start-up, controls the overcurrent shutdown delay, and the overcurrent and short-circuit hiccup restart period. RTD 2 Oscillator timing capacitor discharge current control pin. A resistor is connected between this pin and GND. The current flowing through the resistor determines the magnitude of the discharge current. The discharge current is nominally 55x this current. The PWM dead time is determined by the timing capacitor discharge duration. CS 3 The input to the overcurrent protection comparator. The overcurrent comparator threshold is set at 0.600V nominal. The CS pin is shorted to GND at the end of each switching cycle. Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. Exceeding the overcurrent threshold will start a delayed shutdown sequence. When an overcurrent condition is detected, the soft-start charge current source is disabled. The soft-start capacitor begins discharging through a 15µA current source, and if it discharges to less than 3.9V (sustained overcurrent threshold), a shutdown condition occurs and the OUTA and OUTB outputs are forced low. When the soft-start voltage reaches 0.27V (reset threshold) a soft-start cycle begins. If the overcurrent condition ceases, and then an additional 50µs period elapses before the shutdown threshold is reached, no shutdown occurs. The SS charging current is re-enabled and the soft-start voltage is allowed to recover. CT 4 The oscillator timing capacitor is connected between this pin and GND. GND 5 Reference and power ground for all functions on this device. Due to high peak currents and high frequency operation, a low impedance layout is necessary. Ground planes and short traces are highly recommended. Alternate half cycle output stages. Each output is capable of 1A peak current for driving power MOSFETs or MOSFET drivers. Each output provides very low impedance to overshoot and undershoot. OUTA 6 OUTB 7 VDD 8 The power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. The total supply current, IDD, will be dependent on the load applied to outputs OUTA and OUTB. Total IDD current is the sum of the quiescent current and the average output current. Knowing the operating frequency (fSW) and the output loading capacitance charge (Q) per output, the average output current can be calculated from (EQ. 1): I OUT = 2  Q  f SW FN6554 Rev.1.00 Aug 25, 2017 (EQ. 1) Page 6 of 27 ISL6744A 2. 2. Specifications Specifications 2.1 Absolute Maximum Ratings Parameter Minimum Maximum Unit Supply Voltage, VDD -0.3 +20.0 V OUTA, OUTB -0.3 VDD V Signal Pins -0.3 5 V 1 A Peak GATE Current CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. 2.2 Thermal Information JA (°C/W) Thermal Resistance (Typical) (Note 4) 8 Ld MSOP Package 128 8 Ld SOIC Package 98 Note: 4. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. Refer to TB379. Parameter Minimum Maximum Unit Maximum Junction Temperature -55 +150 °C Maximum Storage Temperature Range -65 +150 °C Pb-Free Reflow Profile 2.3 refer to TB493 Recommended Operating Conditions Parameter Minimum Maximum -40 +105 °C 9 16 VDC Temperature Range Supply Voltage Range (Typical) 2.4 Unit Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to Figure 1 on page 3 and Figure 2 on page 4. 9V < VD < 16V, RTD = 51.1kΩ, CT = 470pF, TA = -40°C to +105°C (Note 5), Typical values are at TA = +25°C Parameter Test Conditions Min Typ Max Unit Supply Voltage Start-Up Current, IDD VDD < START threshold - - 175 µA Operating Current, IDD RLOAD, COUTA,B = 0 - 2.89 - mA COUTA,B = 1nF - 5 8.5 mA UVLO START Threshold 5.9 6.3 6.6 V UVLO STOP Threshold 5.3 5.7 6.3 V - 0.6 - V 0.55 0.6 0.65 V - 35 - ns 8 10 - mA Hysteresis Current Sense Current Limit Threshold CS to OUT Delay CS Sink Current FN6554 Rev.1.00 Aug 25, 2017 (Note 6) Page 7 of 27 ISL6744A 2. Specifications Recommended operating conditions unless otherwise noted. Refer to Figure 1 on page 3 and Figure 2 on page 4. 9V < VD < 16V, RTD = 51.1kΩ, CT = 470pF, TA = -40°C to +105°C (Note 5), Typical values are at TA = +25°C (Continued) Parameter Test Conditions Input Bias Current Min Typ Max Unit -1 - 1 µA Pulse Width Modulator Minimum Duty Cycle VERROR < CT offset - - 0 % Maximum Duty Cycle CT = 470pF, RTD = 51.1kΩ - 94 - % CT = 470pF, RTD = 1.1kΩ (Note 6) - 99 - % CT to SS Comparator Input Gain (Note 6) - 1 - V/V SS to SS Comparator Input Gain (Note 6) - 0.8 - V/V Oscillator Charge Current 143 156 170 µA 1.925 2 2.075 V 45 - 65 µA/µA CT Valley Voltage 0.75 0.8 0.85 V CT Peak Voltage 2.70 2.80 2.90 V Charging Current 45 - 68 µA SS Clamp Voltage 3.8 4.0 4.2 V RTD Voltage Discharge Current Gain Soft-Start Overcurrent Shutdown Threshold Voltage (Note 6) Overcurrent Discharge Current Reset Threshold Voltage (Note 6) - 3.9 - V 12 15 23 µA 0.25 0.27 0.30 V Output High Level Output Voltage (VOH) VDD - VOUTA or VOUTB, IOUT = -100mA - 0.5 2.0 V Low Level Output Voltage (VOL) IOUT = 100mA - 0.5 1.0 V Rise Time CGATE = 1nF, VDD = 12V - 17 60 ns Fall Time CGATE = 1nF, VDD = 12V - 20 60 ns Thermal Shutdown (Note 6) - 145 - °C Thermal Shutdown Clear (Note 6) - 130 - °C Hysteresis, Internal Protection (Note 6) - 15 - °C Thermal Protection Notes: 5. Specifications at -40°C and +105°C are established by +25°C test with margin limits. 6. Limits are established by characterization and are not production tested. 7. All voltages measured with respect to GND, unless otherwise specified. FN6554 Rev.1.00 Aug 25, 2017 Page 8 of 27 ISL6744A 3. 3. Typical Performance Curves Typical Performance Curves 1-104 CT = 1000pF 60 CT = 680pF Dead Time (ns) CT Discharge Current Gain 65 55 50 CT = 470pF 1-103 CT = 220pF CT = 100pF 100 45 40 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 10 0.10 10 20 30 40 RTD Current (mA) Figure 3. Oscillator CT Discharge Current Gain 80 90 100 1.03 1.02 Normalized Charging Current 500 Oscillator Frequency (kHz) 70 Figure 4. Dead Time vs Capacitance 600 400 300 200 100 0 100 50 60 RTD (kΩ) 1.01 1.00 0.99 0.98 0.97 0.96 200 300 400 500 600 CT (pF) 700 800 900 0.95 -40 1000 -25 -10 5 20 35 50 65 80 95 110 Temperature (°C) Figure 6. Charge Current vs Temperature Figure 5. Capacitance vs Oscillator Frequency (RTD = 49.9kΩ) 1.07 1.06 Normalized Voltage 1.05 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0 10 20 30 40 50 60 70 80 90 100 RTD (kΩ) Figure 7. Timing Capacitor Voltage vs RTD FN6554 Rev.1.00 Aug 25, 2017 Page 9 of 27 ISL6744A 4. 4. Functional Description Functional Description 4.1 Features The ISL6744A PWM is an excellent choice for low cost bridge topologies for applications requiring accurate frequency and dead time control. It features 1A FET drivers, adjustable soft-start, overcurrent protection, and internal thermal protection, allowing a highly flexible design with minimal external components. 4.2 Oscillator The ISL6744A has an oscillator with a frequency range to 2MHz, programmable using a resistor RTD and capacitor CT. The switching period is the sum of the timing capacitor charge and discharge durations. The charge duration is determined by CT and the internal current source (assumed to be 160µA in the formula). The discharge duration is determined by RTD and CT. 4 T C  1.25 10  C T s (EQ. 2) 1 T D  -----------------------------------------------------------------------------  R TD  C T CTDisch arg eCurrentGain 1 T OSC = T C + T D = -------------f OSC (EQ. 3) s s (EQ. 4) where TC and TD are the approximate charge and discharge times, respectively, TOSC is the oscillator free running period, and fOSC is the oscillator frequency. One output switching cycle requires two oscillator cycles. The actual times are slightly longer than calculated due to internal propagation delays of approximately 5ns per transition. This delay adds directly to the switching duration, and also causes overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. Additionally, if very low charge and discharge currents are used, there will be an increased error due to the input impedance at the CT pin. The above formulas help with frequency estimation. Practically, effects such as stray capacitances that affect the overall CT capacitance, variation in RTD voltage and charge current over-temperature, etc. exist, and are best evaluated in-circuit. (EQ. 2) follows from the basic capacitor current equation: . i = C dV dt In this case, with variation in dV with RTD (Figure 7), and in charge current (Figure 6), results from (EQ. 2) would differ from the calculated frequency. The “Typical Performance Curves” on page 9 can be used as a tool along with the above equations to estimate the operating frequency more accurately. The maximum duty cycle (D) and dead time (DT) can be calculated using (EQ. 5) and (EQ. 6): D = T C  T OSC DT =  1 – D   T OSC FN6554 Rev.1.00 Aug 25, 2017 (EQ. 5) s (EQ. 6) Page 10 of 27 ISL6744A 4.3 4. Functional Description Soft-Start Operation The ISL6744A features a soft-start using an external capacitor in conjunction with an internal current source. Soft-start reduces stresses and surge currents during start-up. The oscillator capacitor signal (CT) is compared to the soft-start voltage (SS) in the SS comparator, which drives the PWM latch. Duty cycle is limited while the SS voltage is less than 3.5V. The output pulse width increases as the soft-start capacitor voltage increases up to 3.5V. This has the effect of increasing the duty cycle from zero to the maximum pulse width during the soft-start period. When the soft-start voltage exceeds 3.5V, soft-start is complete. Soft-start occurs during start-up and after recovery from an overcurrent shutdown. The soft-start voltage is clamped to 4V. Please note the capacitance of the soft-start capacitor, CSS. If CSS ≥ 0.1µF, the user will need to add a resistor in series with the capacitor, 100Ω/µF (100Ω at least; 1k at most). 4.4 Gate Drive The ISL6744A can source and sink 1A peak current, and can also be used in conjunction with a MOSFET driver, such as the ISL6700, for level shifting. To limit the peak current through the IC, place an external resistor between the totem-pole output of the IC (OUTA or OUTB pin) and the gate of the MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET’s input capacitance. 4.5 Overcurrent Operation Overcurrent delayed shutdown is enabled after the soft-start cycle is complete. If an overcurrent condition is detected, the soft-start charging current source is disabled and the soft-start capacitor is allowed to discharge through a 15µA source. At the same time, a 50µs retriggerable one-shot timer is activated. The timer remains active for 50µs after the overcurrent condition ceases. If the soft-start capacitor discharges to 3.9V, the output is disabled. This state continues until the soft-start voltage reaches 270mV, at which time a new soft-start cycle is initiated. If the overcurrent condition stops at least 50µs prior to the soft-start voltage reaching 3.9V, the soft-start charging currents revert to normal operation and the soft-start voltage is allowed to recover. 4.6 Thermal Protection An internal temperature sensor protects the device if the junction temperature exceeds +145°C. There is approximately +15°C of hysteresis. 4.7 Ground Plane Requirements Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. VDD should be bypassed directly to GND with good high frequency capacitance. FN6554 Rev.1.00 Aug 25, 2017 Page 11 of 27 ISL6744A 5. 5. Typical Application Typical Application Figure 2 on page 4 features the ISL6744A in an unregulated half-bridge DC/DC converter configuration, often referred to as a DC transformer or bus converter. The input voltage is 48V ±10% DC. The output is a nominal 12V when the input voltage is at 48V. Since this is an unregulated topology, the output voltage will vary proportionately with the input voltage. Load regulation is a function of resistance between the source and the converter output. The output is rated at 8A. 5.1 Circuit Elements The converter design is comprised of the following functional blocks: Input Filtering: L1, C1, R1 Half-Bridge Capacitors: C2, C3 Isolation Transformer: T1 Primary Snubber: C13, R10 Start Bias Regulator: CR3, R2, R7, C6, Q5, D1 Supply Bypass Components: C15, C4 Main MOSFET Power Switch: QH, QL Current Sense Network: T2, CR1, CR2, R5, R6, R11, C10, C14 Control Circuit: U1, C18, C16, D2 Output Rectification and Filtering: QR1, QR2, QR3, QR4, L2, C9, C8 Secondary Snubber: R8, R9, C11, C12 FET Driver: U4 Bootstrap Components for Driver: CR4, C5 ZVS Resonant Delay (Optional): L3, C7 5.2 Design Specifications The following design requirements were selected for evaluation purposes: Switching Frequency, fSW: 235kHz VIN: 48V ± 10% VOUT: 12V (nominal) IOUT: 8A (steady state) POUT: 100W Efficiency: 95% Ripple: 1% FN6554 Rev.1.00 Aug 25, 2017 Page 12 of 27 ISL6744A 5.3 5. Typical Application Transformer Design The design of a transformer for a half-bridge application is an iterative process. The process requires compromises, and even experienced designers will produce different designs when presented with identical requirements. For clarity, the iterative design process is not presented here. The abbreviated design process is as follows: • Select a core geometry suitable for the application. Constraints of height, footprint, mounting preference, and operating environment will affect the core geometry. • Determine the turns ratio. • Select suitable core material(s). • Select the maximum flux density desired for operation. • Select the core size. Core size is determined by the capability of the core structure to store the required energy, the number of turns that have to be wound, and the wire gauge needed. Often the window area (the space used for the windings) and power loss determine the final core size. • Determine the maximum desired flux density. Depending on the frequency of operation, the core material selected, and the operating environment, the allowed flux density must be determined. The decision of what flux density to allow is often difficult to determine initially. Usually, the highest flux density that produces an acceptable design is used, but often the winding geometry dictates a larger core than is indicated based on flux density alone. • Determine the number of primary turns. • Select the wire gauge for each winding. • Determine the winding order and insulation requirements. • Verify the design. For this application, we have selected a planar structure to achieve a low profile design. A PQ style core was selected because of its round center leg cross section, but many suitable core styles are available. nSR nS nP nS nSR Figure 8. Transformer Schematic Because the converter is operating as an open loop at nearly 100% duty cycle, the turns ratio, N, is the ratio of the input voltage to the output voltage divided by 2. V IN 48 N = ------------------------- = --------------- = 2 V OUT  2 12  2 (EQ. 7) The factor of 2 in the denominator is due to the half-bridge topology. Only half of the input voltage is applied to the primary of the transformer. A PC44HPQ20/6 “E-Core” plus a PC44PQ20/3 “I-Core” from TDK were selected for the transformer core. The ferrite material is PC44. The core parameter of concern for flux density is the effective core cross-sectional area, Ae. For the PQ core pieces selected: Ae = 0.62cm2 or 6.2e -5m2 Using Faraday’s Law, V = N d/dt, the number of primary turns can be determined after the maximum flux density is set. An acceptable Bmax is ultimately determined by the allowable power dissipation in the ferrite material and is influenced by the lossiness of the core, core geometry, operating ambient temperature, and air flow. The TDK datasheet for PC44 material FN6554 Rev.1.00 Aug 25, 2017 Page 13 of 27 ISL6744A 5. Typical Application indicates a core loss factor of ~400mW/cm3 with a ±2000 gauss 100kHz sinusoidal excitation. The application uses a 235kHz square wave excitation, so no direct comparison between the application and the data can be made. Interpolation of the data is required. The core volume is approximately 1.6cm3, so the estimated core loss is: f act 3 mW 200kHz P loss  -----------  cm  --------------- = 0.4  1.6  --------------------- = 1.28 3 f meas 100kHz cm W (EQ. 8) 1.28W of dissipation is significant for a core of this size. Reducing the flux density to 1200 gauss will reduce the dissipation by about the same percentage, or 40%. Evaluate the transformer’s performance in the application to determine acceptable dissipation. From Faraday’s Law and using 1200 gauss peak flux density (B = 2400 gauss or 0.24 tesla): –6 V IN  T ON 53  2  10 N = ------------------------------ = ----------------------------------------------------- = 3.56 –5 2  A e  B 2  6.2  10  0.24 turns (EQ. 9) Rounding up yields four turns for the primary winding. The peak flux density using four turns is ~1100 gauss. From (EQ. 7) on page 13, the number of secondary turns is 2. The volts/turn for this design ranges from 5.4V at VIN = 43V to 6.6V at VIN = 53V. Therefore, the Synchronous Rectifier (SR) windings may be set at 1 turn each with proper FET selection. Selecting 2 turns for the synchronous rectifier windings would also be acceptable, but the gate drive losses would increase. Determine the equivalent wire gauge for the planar structure. Since each secondary winding conducts for only 50% of the period, the RMS current is: I RMS = I OUT  D = 10  0.5 = 7.07 A (EQ. 10) where D is the duty cycle. Since an FR-4 PWB planar winding structure was selected, the width of the copper traces is limited by the window area width, and the number of layers is limited by the window area height. The PQ core selected has a usable window area width of 0.165 inches. Allowing one turn per layer and 0.020 inches clearance at the edges allows a maximum trace width of 0.125 inches. Using 100 circular mils (c.m.)/A as a guideline for current density, and from (EQ. 10), 707c.m. are required for each of the secondary windings (a circular mil is the area of a circle 0.001 inches in diameter). Converting c.m. to square mils yields 555 mils2 (0.785 sq. mils/c.m.). Dividing by the trace width results in a copper thickness of 4.44 mils (0.112mm). Using 1.3 mils/oz. of copper requires a copper weight of 3.4oz. To reduce cost, 3oz. copper was selected. One layer of each secondary winding also contains the synchronous rectifier winding. For this layer, the secondary trace width is reduced by 0.025 inches to 0.100 inches (0.015 inches for the SR winding trace width and 0.010 inches spacing between the SR winding and the secondary winding). FN6554 Rev.1.00 Aug 25, 2017 Page 14 of 27 ISL6744A 5. Typical Application The choice of copper weight may be validated by calculating the DC copper losses of the secondary winding. Ignoring the terminal and lead-in resistance, the resistance of each layer of the secondary may be approximated using (EQ. 11). 2 R = ----------------------- r 2 t  ln  -----  r 1  (EQ. 11) where R = Winding resistance  = Resistivity of copper = 669e-9Ω-inches at +20°C t = Thickness of the copper (3 oz.) = 3.9e-3 inches r2 = Outside radius of the copper trace = 0.324 or 0.299 inches r1 = Inside radius of the copper trace = 0.199 inches The winding without the SR winding on the same layer has a DC resistance of 2.21mΩ. The winding that shares the layer with the SR winding has a DC resistance of 2.65mΩ. With the secondary configured as a 4 turn center tapped winding (2 turns each side of the tap), the total DC power loss for the secondary at +20°C is 486mW. The primary windings have an RMS current of approximately 5A (IOUT x NS/NP at ~ 100% duty cycle). The primary is configured as 2 layers, 2 turns per layer to minimize the winding stack height. Allowing 0.020 inches edge clearance and 0.010 inches between turns yields a trace width of 0.0575 inches. Ignoring the terminal and lead-in resistance, and using (EQ. 11), the inner trace has a resistance of 4.25mΩ, and the outer trace has a resistance of 5.52mΩ. The resistance of the primary then is 19.5mΩ at +20°C. The total DC power loss for the primary at +20°C is 489mW. Improved efficiency and thermal performance can be achieved by selecting heavier copper weight for the windings. Evaluation in the application will determine its need. The order and geometry of the windings affects the AC resistance, winding capacitance, and leakage inductance of the finished transformer. To reduce these effects, interleave the windings. The primary winding is placed between the two secondary windings. The winding layout appears as follows: . Figure 9. Top Layer: 1 Turn Secondary and SR Windings Figure 10. Internal layer 1: 1 Turn Secondary Winding Figure 11. Internal Layer 2: 2 Turns Primary Winding Figure 12. Internal Layer 3: 2 Turns Primary Winding FN6554 Rev.1.00 Aug 25, 2017 Page 15 of 27 ISL6744A 5. Typical Application Figure 13. Internal Layer 4: 1 Turn Secondary Winding Figure 14. Bottom Layer: 1 Turn Secondary and SR Windings 0.689 0.358 0.807 0.639 0.403 0.169 0.000 0.000 0.184 0.479 0.774 1.054 Figure 15. PWB Dimensions 5.4 MOSFET Selection The criteria for selection of the primary side half-bridge FETs and the secondary side synchronous rectifier FETs is largely based on the current and voltage rating of the device. However, do not ignore the FET drain-source capacitance and gate charge. The Zero Voltage Switch (ZVS) transition timing is dependent on the transformer’s leakage inductance and the capacitance at the node between the upper FET source and the lower FET drain. The node capacitance is comprised of the drain-source capacitance of the FETs and the transformer parasitic capacitance. The leakage inductance and capacitance form an LC resonant tank circuit, which determines the duration of the transition. The amount of energy stored in the LC tank circuit determines the transition voltage amplitude. If the leakage inductance energy is too low, ZVS operation is not possible and near or partial ZVS operation occurs. As the leakage energy increases, the voltage amplitude increases until it is clamped by the FET body diode to ground or VIN, depending on which FET conducts. When the leakage energy exceeds the minimum required for ZVS operation, the voltage is clamped until the energy is transferred. This behavior increases the time window for ZVS operation. However, the transition time and the period of time during which the voltage is clamped reduces the effective duty cycle. The gate charge affects the switching speed of the FETs. Higher gate charge translates into higher drive requirements and/or slower switching speeds. The energy required to drive the gates is dissipated as heat. The maximum input voltage, VIN, plus transient voltage, determines the voltage rating required. With a maximum input voltage of 53V for this application, and if we allow a 10% adder for transients, a voltage rating of 60V or higher will suffice. FN6554 Rev.1.00 Aug 25, 2017 Page 16 of 27 ISL6744A 5. Typical Application The RMS current through each primary side FET can be determined from (EQ. 10), substituting 5A of primary current for IOUT (assuming 100% duty cycle). The result is 3.5A RMS. Fairchild FDS3672 FETs, rated at 100V and 7.5A (rDS(ON) = 22mΩ), were selected for the half-bridge switches. The synchronous rectifier FETs must withstand approximately one half of the input voltage, assuming no switching transients are present. This suggests that a device capable of withstanding at least 30V is required. Empirical testing in the circuit revealed switching transients of 20V were present across the device, indicating that a rating of at least 60V is required. The RMS current rating of 7.07A for each SR FET requires a low rDS(ON) to minimize conduction losses, which is difficult to find in a 60V device. It was decided to use two devices in parallel to simplify the thermal design. Two Fairchild FDS5670 devices are used in parallel for a total of four SR FETs. The FDS5670 is rated at 60V and 10A (rDS(ON) = 14mΩ). 5.5 Oscillator Component Selection The desired operating frequency of 235kHz for the converter was established in “Design Specifications” on page 12. The oscillator frequency operates at twice the frequency of the converter because two clock cycles are required for a complete converter period. During each oscillator cycle the timing capacitor, CT, must be charged and discharged. Determining the required discharge time to achieve Zero Voltage Switching (ZVS) is the critical design goal in selecting the timing components. The discharge time sets the dead time between the two outputs, and is the same as ZVS transition time. After the discharge time is determined, the remainder of the period becomes the charge time. The ZVS transition duration is determined by the transformer’s primary leakage inductance, Llk, by the FET Coss, by the transformer’s parasitic winding capacitance, and by any other parasitic elements on the node. The parameters may be determined by measurement, calculation, estimate, or by some combination of these methods.  L lk   2C oss + C xfrmr  t zvs  -------------------------------------------------------------------2 s (EQ. 12) Device output capacitance, Coss, is non-linear with applied voltage. To determine the equivalent discrete capacitance, Cfet, a charge model is used. Using a known current source, the time required to charge the MOSFET drain to the desired operating voltage is determined and the equivalent capacitance is calculated. Ichg  t Cfet = -------------------V F (EQ. 13) After the estimated transition time is determined, it must be verified directly in the application. The transformer leakage inductance was measured at 125nH and the combined capacitance was estimated at 2000pF. Calculations indicate a transition period of ~25ns. Verification of the performance yielded a value of TD closer to 45ns. FN6554 Rev.1.00 Aug 25, 2017 Page 17 of 27 ISL6744A 5. Typical Application The remainder of the switching half-period is the charge time, TC, and can be determined using (EQ. 14) –9 1 1 T C = ------------------- – T D = ---------------------------------- – 45  10 = 2.08 3 2  f SW 2  235  10 s (EQ. 14) where fSW is the converter switching frequency. Using Figure 5 on page 9, the capacitor value appropriate to the desired oscillator operating frequency of 470kHz can be selected. A CT value of 100pF, 150pF, or 220pF is appropriate for this frequency. A value of 150pF was selected. To obtain the proper value for RTD, (EQ. 3) on page 10 is used. Because there is a 10ns propagation delay in the oscillator circuit, it must be included in the calculation. The value of RTD selected is 10kΩ. 5.6 Output Filter Design The output filter inductor and capacitor selection is simple and straightforward. Under steady state operating conditions the voltage across the inductor is very small due to the large duty cycle. Voltage is applied across the inductor only during the switch transition time, which is about 45ns in this application. Ignoring the voltage drop across the SR FETs, the voltage across the inductor during the on time with VIN = 48V is: V IN  N S   1 – D  V L = V S – V OUT = ------------------------------------------------  250 2N P (EQ. 15) mV where VL is the inductor voltage VS is the voltage across the secondary winding VOUT is the output voltage If a current ramp, I, of 5% of the rated output current is allowed, the minimum inductance required is: V L  T ON 0.25  2.08 L  ------------------------- = ----------------------------- = 1.04 I 0.5 H (EQ. 16) An inductor value of 1.5µH, rated for 18A was selected. With a maximum input voltage of 53V, the maximum output voltage is about 13V. The closest higher voltage rated capacitor is 16V. Under steady state operating conditions the ripple current in the capacitor is small, so it would seem appropriate to have a low ripple current rated capacitor. However, a high rated ripple current capacitor was selected based on the nature of the intended load, multiple buck regulators. To minimize the output impedance of the filter, a SANYO OSCON 16SH150M capacitor in parallel with a 22µF ceramic capacitor were selected. FN6554 Rev.1.00 Aug 25, 2017 Page 18 of 27 ISL6744A 5.7 5. Typical Application Current Limit Threshold The current limit threshold is fixed at 0.6V nominal, which is the reference to the overcurrent protection comparator. The current level that corresponds to the overcurrent threshold must be chosen to allow for the dynamic behavior of an open loop converter. In particular, the low inductor ripple current under steady state operation increases significantly as the duty cycle decreases. 14 15 13 12 11 10 10 9 5 8 0.9950 0.9960 0.9970 0.9980 0.9990 1.000 0.986 0.988 Figure 16. Steady State Secondary Winding Voltage and Inductor Current 0.992 0.994 0.996 0.998 1.000 Time (ms) Time (ms) V (L1:1) I (L1) 0.990 V (L1:1) I (L1) Figure 17. Secondary Winding Voltage and Inductor Current During Current Limit Operation Figures 16 and 17 show the behavior of the inductor ripple under steady state and overcurrent conditions. In this example, the peak current limit is set at 11A. The peak current limit causes the duty cycle to decrease, resulting in a reduction of the average current through the inductor. The implication is that the converter can not supply the same output current in current limit that it can supply under steady state conditions. The peak current limit setpoint must take this behavior into consideration. A 5.11Ω current sense resistor was selected for the rectified secondary of current transformer T2 for the ISL6744Eval 1, corresponding to a peak current limit setpoint of about 11A. FN6554 Rev.1.00 Aug 25, 2017 Page 19 of 27 ISL6744A 5.8 5. Typical Application Performance The major performance criteria for the converter are efficiency, and to a lesser extent, load regulation. Efficiency, load regulation, and line regulation performance are demonstrated in Figures 18 through 20. 100 12.50 95 12.25 Output Voltage (V) Efficiency (%) As expected, the output voltage varies considerably with line and load when compared to an equivalent converter with a closed loop feedback. However, for applications where tight regulation is not required, such as those applications that use downstream DC/DC converters, this design approach is acceptable. 90 85 85 11.75 11.50 11.25 75 70 12.00 0 1 2 3 4 5 6 7 8 9 11.00 10 1 0 2 3 4 5 6 7 8 9 10 Load Current (A) Load Current (A) Figure 19. Load Regulation at VIN = 48V Figure 18. Efficiency vs Load VIN = 48V 13.5 Output Voltage (V) 13.0 12.5 12.0 11.5 11.0 10.5 42 43 44 45 46 47 48 49 50 51 52 53 Input Voltage (V) Figure 20. Line Regulation at IOUT = 1A FN6554 Rev.1.00 Aug 25, 2017 Page 20 of 27 ISL6744A 5.9 5. Typical Application Waveforms Typical waveforms can be found in Figures 21 through 25. Figure 21 shows the output voltage ripple and noise at 5A. Figure 21. Output Ripple and Noise - 20MHz BW Figures 22 and 23 show the voltage waveforms at the switching node shared by the upper FET source and the lower FET drain. In particular, Figure 23 shows near ZVS operation at 5A of load when the upper FET is turning off and the lower FET is turning on. ZVS operation occurs completely, implying that all the energy stored in the node capacitance has been recovered. Figure 24 on page 22 shows the switching transition between outputs, OUTA and OUTB during steady state operation. The dead time duration of 46.9ns is clearly shown. A 2.7V zener is added between the VDD pins of ISL6700 and ISL6744, to ensure that the PWM turns on only after the driver has turned on, thereby ensuring the soft-start function. Figure 25 on page 22 shows the soft-start operation. Figure 22. FET Drain-Source Voltage FN6554 Rev.1.00 Aug 25, 2017 Figure 23. FET Drain-Source Voltage Near-ZVS Transition Page 21 of 27 ISL6744A 5. Typical Application Figure 24. OUTA - OUTB Transition FN6554 Rev.1.00 Aug 25, 2017 Figure 25. Output Soft-Start Page 22 of 27 ISL6744A 6. 6. Component List Component List Reference Designator Value Description C1 1.0µF Capacitor, 1812, X7R, 100V, 20% C2, C3 3.3µF Capacitor, 1812, X5R, 50V, 20% C4 1.0µF Capacitor, 0805, X5R, 16V, 10% C5 0.1µF Capacitor, 0603, X7R, 16V, 10% C6, C15 4.7µF Capacitor, 0805, X5R, 10V, 20% C7 Open Capacitor, 0603, Open or Optional Discrete Stray Capacitance C8 22µF Capacitor, 1812, X5R, 16V, 20% C9 150µF Capacitor, Radial, Sanyo 16SH150M C10, C11, C12, C13, C14 1000pF Capacitor, 0603, X7R, 50V, 10% C16 150pF Capacitor, 0603, COG, 16V, 5% C18 0.01µF Capacitor, 0603, X7R, 16V, 10% CR1, CR2 Diode, Schottky, BAT54S, 30V CR3 Diode, Schottky, BAT54, 30V CR4 Diode, Schottky, SMA, 100V, 2.1A D1 Zener, 10V, Zetex BZX84C10ZXCT-ND D2 Zener, 2.7V, BZX84C2V7 L1 190nH Pulse, P2004T L2 1.5µH Bitech, HM73-301R5 L3 Short Jumper or Optional Discrete Leakage Inductance P1, P2, P3, P4 Q5 Keystone, 1514-2 NPN Transistor, ON MJD31C QL, QH FET, Fairchild FDS3672, 100V QR1, QR2, QR3, QR4 FET, Fairchild FDS5670, 60V R1 3.3 R2 3.01k Resistor, 2512, 1% R5 5.11 Resistor, 0603, 1% R6 205 Resistor, 0603, 1% R7 75.0k Resistor, 0805, 1% R8, R9 20.0 Resistor, 0805, 1% R10 18 Resistor, 2512, 1% R11 100 Resistor, 0603, 1% R12 10.0k Resistor, 0603, 1% T1 Custom Midcom 31718 T2 Custom Midcom 31719R TP1, TP2, TP4, TP5, TP6 5002 SP1 Resistor, 2512, 1% Keystone Tektronix Scope Jack, 131-4353-00 U1 Intersil ISL6744AAUZ, MSOP8 U4 Intersil ISL6700IB, SOIC FN6554 Rev.1.00 Aug 25, 2017 Page 23 of 27 ISL6744A 7. 7. Revision History Revision History Rev. Date 1.00 Aug 25, 2017 FN6554 Rev.1.00 Aug 25, 2017 Description Applied new formatting. Added Related Literature section. Updated Ordering information table. Update Absolute Maximum Ratings minimum values for Supply Voltage, OUTA, OUTB, and Signal Pins. Added Note 3. Moved Note 7 to end of EC table. Moved Pin Descriptions to table following Pin Configuration. Updated the Soft-Start Operation section on page 11. Added Revision History and About Intersil sections. Updated POD M8.118 to the latest revision. The updates are as follows: -Updated to new POD template. Added land pattern. -Corrected lead width dimension in side view 1 from “0.25 - 0.036” to “0.25 - 0.36”. Updated POD M8.15 to the latest revision. The updates are as follows: -Changed in Typical Recommended Land Pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) -Changed Note 1 “1982” to “1994” Page 24 of 27 ISL6744A 8. 8. Package Outline Drawing Package Outline Drawing For the most recent package outline drawing, see M8.118. M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 5 3.0±0.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE PLANE TOP VIEW 0.55 ± 0.15 0.25 3°±3° 0.85±010 H DETAIL "X" C SEATING PLANE 0.25 - 0.36 0.08 M C A-B D 0.10 ± 0.05 0.10 C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN FN6554 Rev.1.00 Aug 25, 2017 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. Page 25 of 27 ISL6744A 8. Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 For the most recent package outline drawing, see M8.15. DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN6554 Rev.1.00 Aug 25, 2017 Page 26 of 27 ISL6744A 9. 9. About Intersil About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information page found at www.intersil.com. For a listing of definitions and abbreviations of common terms used in our documents, visit: www.intersil.com/glossary. You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2007-2017. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6554 Rev.1.00 Aug 25, 2017 Page 27 of 27