DATASHEET
ISL68201
FN8696
Rev.5.00
Jul 12, 2018
Single-Phase R4 Digital Hybrid PWM Controller with PMBus/SMBus/I2C and PFM
The ISL68201 is a single-phase, synchronous buck PWM
controller featuring the Renesas proprietary R4™ Technology.
It supports a wide 4.5V to 24V input voltage range and a wide
0.5V to 5.5V output range. Integrated LDOs provide controller
bias voltage, allowing for single supply operation. The
ISL68201 includes a PMBus/SMBus/I2C interface for device
configuration and telemetry (VIN, VOUT, IOUT, and temperature)
and fault reporting.
The Renesas proprietary R4 control scheme has extremely fast
transient performance, accurately regulated frequency control,
and all internal compensation. An efficiency enhancing PFM
mode can be enabled to greatly improve light-load efficiency.
The ISL68201’s serial bus allows for easy R4 loop
optimization, resulting in fast transient performance over a
wide range of applications, including all ceramic output filters.
The ISL68201 has four 8-bit configuration pins, which provide
very flexible configuration options (frequency, VOUT, R4 gain,
etc.) without the need for built-in NVM memory. This results in
a design flow that closely matches traditional analog
controllers, while still offering the design flexibility and feature
set of a digital PMBus/SMBus/I2C interface. The ISL68201
also features remote voltage sensing and completely eliminates
any potential difference between remote and local grounds. This
improves regulation and protection accuracy. A precision enable
input is available to coordinate the start-up of the ISL68201 with
other voltage rails, especially useful for power sequencing.
Applications
• High efficiency and high density POL digital power
• FPGA, ASIC, and memory supplies
• Data center: servers, storage systems
• Wired infrastructure: routers, switches, and optical
networking
Features
• Renesas proprietary R4 Technology
- Linear control loop for optimal transient response
- Variable frequency and duty cycle control during load
transient for fastest possible response
- Inherent voltage feed-forward for wide range input
• Input voltage range: 4.5V to 24V
• Output voltage range: 0.5V to 5.5V
• ±0.5% DAC accuracy with remote sense
• Support all ceramic solutions
• Integrated LDOs for single input rail solution
• SMBus/PMBus/I2C compatible, up to 1.25MHz
• 256 boot-up voltage levels with a configuration pin
• Eight switching frequency options from 300kHz to 1.5MHz
• PFM operation option, compatible with ISL99140 for
improved light-load efficiency
• Start-up into precharged load
• Precision enable input to set higher input UVLO and power
sequence as well as fault reset
• Power-good monitor for soft-start and fault detection
• Comprehensive fault protection for high system reliability
- Over-temperature protection
- Output overcurrent and short-circuit protection
- Output overvoltage and undervoltage protection
- Open remote sense protection
• Compatible with 5V or 3.3V PWM input DrMOS or Smart
Power Stage (SPS)
• Compatible with PowerNavigator software
• Wireless infrastructure: base stations
Related Literature
For a full list of related documents, visit our website
• ISL68201 product page
TABLE 1. SINGLE-PHASE R4 DIGITAL HYBRID PWM CONTROLLER OPTIONS
PART
NUMBER
INTEGRATED
DRIVER
PWM
OUTPUT
PMBus/SMBus/I2C
INTERFACE
ISL68200
Yes
No
Yes
Discrete MOSFETs or Dual Channel MOSFETs
ISL68201
No
Yes
Yes
Renesas Power Stages:
ISL99140, ISL99227, ISL99125B, ISL99135B
Renesas Drivers:
ISL6596, ISL6609, ISL6627, ISL6622, ISL6208
FN8696 Rev.5.00
Jul 12, 2018
COMPATIBLE DEVICES
Page 1 of 33
ISL68201
Table of Contents
Typical Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IC Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resistor Reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot-Up Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Monitoring and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOUT Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGOOD Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PFM Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMBus, PMBus, and I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R4 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
10
12
12
16
18
19
20
21
21
21
26
General Application Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Design and Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulator Design Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
28
29
30
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
FN8696 Rev.5.00
Jul 12, 2018
Page 2 of 33
ISL68201
Typical Applications Circuits
1.0µ F
4.7µ F
VCC
PV C C
7VLD O
4.75 TO 24V
V IN
1.0µ F
2
I C/
S M B us/
PM B us
SA LE R T
ISL99140
SC L
SD A
PG O O D
FC CM
PGOOD
EN
PW M
PW M
LG
LG IN
IO U T
V O UT < 7VLD O
UG
EN
V CC
BOOT
‐ 1.7V
0.5V TO 5.5V
PH A S E
100
10k
N TC
VC C
1.54k
VC C
N TC
4
0.1µ F N CP 18X H 103J03R B
B E TA = 3380
PR O G 1-4
C SE N
C SR TN
VSEN
RGND
GND
FIGURE 1. WIDE RANGE INPUT AND OUTPUT APPLICATIONS
1.0µF
4.7µF
VCC
PVCC
VIN
7VLDO
4.5 TO 5.5V
1.0µF
2
I C/
SMBus/
PMBus
SALERT
ISL99140
SCL
SDA
PGOOD
FCCM
PGOOD
EN
PWM
PWM
PHASE
LG
LGIN
IOUT
‐
V OUT < 7VLDO 1.7V
0.5V TO 2.5V
UG
EN
VCC
BOOT
100
10k
VCC
NTC
1.54k
VCC
NTC
0.1µF
4
PROG1-4
NCP18XH103J03RB
BETA = 3380
CSEN
CSRTN
VSEN
RGND
GND
FIGURE 2. 5V INPUT APPLICATION
FN8696 Rev.5.00
Jul 12, 2018
Page 3 of 33
PROG4
SCL
SDA SALERT
PROG2
ISL68201
FN8696 Rev.5.00
Jul 12, 2018
Block Diagram
PROG3
7VLDO VIN PVCC
POR
VCC
SOFT-START
AND
FAULT LOGIC
SMBus/PMBus/I2C
INTERFACE
EN
OTP
OCP
VIN VOUT IOUT
TEMP
FCCM
DRIVER
FCCM
PGOOD
CIRCUITRY
PGOOD
LGIN
PWM AND PFM
CONTROL
RGND
-
VSEN
INTERNAL
COMPENSATION
+ AMPLIFIER
PVCC
OVERVOLTAGE/
UNDERVOLTAGE
PWM
DRIVER
PWM
GND
5V LDO
R4
MODULATOR
PROG1
VIN
7V LDO
REFERENCE
VOLTAGE
CIRCUITRY
OVERCURRENT (OCP) AND
OVER-TEMPERATURE (OTP)
SWITCHING
FREQUENCY
CURRENT SENSE
AND TEMPERATURE
COMPENSATION
7VLDO
CSEN
CSRTN
NTC
GND
Page 4 of 33
IOUT
FIGURE 3. ISL68201 SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
ISL68201
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP RANGE
(°C)
TAPE AND REEL
(UNITS) (Note 1)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL68201IRZ
ISL 68201I
-40 to +85
-
24 Ld 4x4 QFN
L24.4x4C
ISL68201IRZ-T
ISL 68201I
-40 to +85
6k
24 Ld 4x4 QFN
L24.4x4C
ISL68201IRZ-T7A
ISL 68201I
-40 to +85
250
24 Ld 4x4 QFN
L24.4x4C
ISL68201IRZ-TK
ISL 68201I
-40 to +85
1k
24 Ld 4x4 QFN
L24.4x4C
ISL68201-99125DEMO1Z
16A Demo Board with On-Board Transient
ISL68201-99135DEMO1Z
20A Demo Board with On-Board Transient
ISL68201-99140DEMO1Z
35A Demo Board with On-Board Transient
NOTES:
1. Refer to TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL68201 product information page. For more information about MSL, see TB363.
Pin Configuration
LGIN
PVCC
PWM
GND
FCCM
GND
24 LD 4X4 QFN
TOP VIEW
24
23
22
21
20
19
EN
1
18
PROG1
VIN
2
17
PROG2
7VLDO
3
16
PROG3
VCC
4
15
PROG4
SCL
5
14
IOUT
SALERT
6
13
NTC
7
8
9
10
11
12
SDA
PGOOD
RGND
VSEN
CSRTN
CSEN
GND
(PAD)
Functional Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1
EN
Precision enable input. Pulling EN above the rising threshold voltage initiates the soft-start sequence, while pulling EN below the
failing threshold voltage suspends the Voltage Regulator (VR) operation.
2
VIN
Input voltage pin for the R4 loop and LDOs (5V and 7V). Place a high quality low ESR ceramic capacitor (1.0μF, X7R) in
close proximity to the pin. An external series resistor is not advised.
3
7VLDO
4
VCC
Logic bias supply that should be connected to PVCC rail externally. Place a high quality low ESR ceramic capacitor
(1μF, X7R) from this pin to GND.
5
SCL
Synchronous clock signal input of SMBus/PMBus/I2C.
6
SALERT
7
SDA
FN8696 Rev.5.00
Jul 12, 2018
7V LDO from VIN biases the current sensing amplifier. Place a high quality low ESR ceramic capacitor (1.0μF, X7R, 10V+) in
close proximity to the pin.
Output pin for transferring the active low signal driven asynchronously from the VR controller to the SMBus/PMBus.
I/O pin for transferring data signals between the SMBus/PMBus/I2C host and VR controller.
Page 5 of 33
ISL68201
Functional Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
8
PGOOD
9
RGND
This pin monitors the negative rail of the regulator output. Connect to ground at the point of regulation.
10
VSEN
This pin monitors the positive rail of the regulator output. Connect to the point of regulation.
11
CSRTN
12
CSEN
13
NTC
Input pin for the temperature measurement. Connect this pin through an NTC thermistor (10kΩ, ~ 3380) and a decoupling
capacitor (~0.1μF) to GND, and a resistor (1.54kΩ)to VCC of the controller. The voltage at this pin is inversely proportional to
the VR temperature.
14
IOUT
Output current monitor pin. An external resistor sets the gain and an external capacitor provides the averaging function; an
external pull-up resistor to VCC is recommended to calibrate the no load offset. See “IOUT Calibration” on page 19.
15
PROG4
Programming pin for Modulator (R4) RR impedance and output slew rate during Soft-Start (SS) and Dynamic VID (DVID).
It also sets AV gain multiplier to 1x or 2x and determines the AV gain on PROG3.
16
PROG3
Programming pin for ultrasonic PFM operation, fault behavior, switching frequency, and R4 (AV) control loop gain.
17
PROG2
Programming pin for PWM/PFM mode, temperature compensation, and serial bus (SMBus/PMBus/I2C) address.
18
PROG1
Programming pin for boot-up voltage.
19, 21
GND
Ground pin, connect directly to system ground plane.
20
FCCM
Output signal low to work with DrMOS ISL99140 for diode emulation in PFM mode; signal high for PWM mode.
22
PWM
PWM output and is compatible with 3.3V or 5V PWM input external driver, DrMOS, or Smart Power Stage.
23
PVCC
Output of the 5V LDO and input for the LGATE and UGATE MOSFET driver circuits. Place a high quality low ESR ceramic
capacitor (4.7μF or higher, X7R) in close proximity to the pin.
24
LGIN
Low-side gate signal input to complete the internal FLL loop. A 100Ω series impedance from low-side gate drive signal to
this pin is required.
PAD
GND
Return of logic bias supply VCC. Connect directly to the system ground plane with at least four vias.
FN8696 Rev.5.00
Jul 12, 2018
DESCRIPTION
Power-good, open-drain indicator output.
This pin monitors the negative flow of output current with a series resistor and for overcurrent protection and telemetry.
The series resistor sets the current gain and should be within 40Ωand 3.5kΩ.
This pin monitors the positive flow of output current for overcurrent protection and telemetry.
Page 6 of 33
ISL68201
Absolute Maximum Ratings
Thermal Information
VCC, PVCC, VSEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27V
7VLDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to GND, 7.75V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC + 0.3V
ESD Rating
Human Body Model (Tested per JS-001-2010) . . . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . . . 1kV
Latch-Up (Tested per JESD78D, Class 2, Level A) . . . . ±100mA at +125°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
24 Ld QFN (Notes 4, 5) . . . . . . . . . . . . . . . .
39
2.5
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Wide Range Input Voltage, VIN, Figure 1 . . . . . . . . . . . . . . . . . 4.75V to 24V
5V Application Input Voltage, VIN, VCC, PVCC, Figure 2 . . . . . . 4.5V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
-40°C to +85°C, unless otherwise stated.
All typical specifications TA = +25°C, VCC = 5V. Boldface limits apply across the operating temperature range,
PARAMETER
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
EN = 5V, VCC = 5V, fSW = 500kHz, DAC = 1V
14
16.5
mA
EN = 0V, VCC = 5V
14
16.5
mA
EN = 5V, VCC = 5V, fSW = 500kHz, DAC = 1V
2
SYMBOL
TEST CONDITIONS
VCC AND PVCC
VCC Input Bias Current
PVCC Input Bias Current
IVCC
IPVCC
EN = 0V, VCC = 5V
mA
1.0
mA
4.2
4.35
V
3.95
4.15
V
4.2
4.35
V
3.80
3.95
4.15
V
VCC AND VIN POR THRESHOLD
VCC, PVCC Rising POR Threshold Voltage
VCC, PVCC Falling POR Threshold Voltage
3.80
VIN, 7VLDO Rising POR Threshold Voltage
VIN, 7VLDO Falling POR Threshold Voltage
ENABLE INPUT
EN High Threshold Voltage
VENTHR
0.81
0.84
0.87
V
EN Low Threshold Voltage
VENTHF
0.71
0.76
0.81
V
DAC ACCURACY
DAC Accuracy
(TA = 0°C to +85°C)
DAC Accuracy
(TA = -45°C to +85°C)
2.5V < DAC ≤ 5.5V
-0.5
0.5
%
1.6V < DAC ≤ 2.5V
-0.75
0.75
%
1.2V < DAC ≤ 1.6V
-10
10
mV
0.5V ≤ DAC ≤ 1.2V
-8
8
mV
2.5V < DAC ≤ 5.5V
-0.75
0.75
%
1.6V < DAC ≤ 2.5V
-1.0
1.0
%
1.2V < DAC ≤ 1.6V
-11
11
mV
0.5V ≤ DAC ≤ 1.2V
-9
9
mV
CHANNEL FREQUENCY
300kHz Configuration
PWM mode
260
300
335
kHz
400kHz Configuration
PWM mode
345
400
450
kHz
FN8696 Rev.5.00
Jul 12, 2018
Page 7 of 33
ISL68201
Electrical Specifications
All typical specifications TA = +25°C, VCC = 5V. Boldface limits apply across the operating temperature range,
-40°C to +85°C, unless otherwise stated. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
500kHz Configuration
PWM mode
435
500
562
kHz
600kHz Configuration
PWM mode
510
600
670
kHz
700kHz Configuration
PWM mode
610
700
790
kHz
850kHz Configuration
PWM mode
730
850
950
kHz
1000kHz Configuration
PWM mode
865
1000
1120
kHz
1500kHz Configuration
PWM mode
1320
1500
1660
kHz
0.0616
0.078
0.096
mV/µs
0.13
0.157
0.18
mV/µs
0.25
0.315
0.37
mV/µs
0.53
0.625
0.70
mV/µs
1.05
1.25
1.40
mV/µs
2.10
2.50
2.80
mV/µs
4.20
5.00
5.60
mV/µs
8.60
10.0
10.9
mV/µs
140
200
260
µs
250
µA
SOFT-START AND DYNAMIC VID
Soft-Start and DVID Slew Rate
Soft-Start Delay from Enable High
Excluding 5.5ms POR timeout.
See Figures 21 and 22
REMOTE SENSE
Bias Current of VSEN and RGND Pins
Maximum Differential Input Voltage
6.0
V
POWER-GOOD
PGOOD Pull-Down Impedance
RPG
PGOOD = 5mA sink
PGOOD Leakage Current
IPG
PGOOD = 5V
10
50
Ω
1.0
µA
5.15
V
LDOs
5V LDO Regulation
VIN = 12V, load = 50mA
4.85
5V Dropout
VIN = 4.75V, load = 50mA
4.45
V
125
mA
5V LDO Current Capability
7V LDO Regulation
250µA load
7V Dropout
VIN = 4.75V, 250µA load
7V LDO Current Capability
Not recommended for external use
7.2
5.00
7.4
7.5
V
4.50
V
2
mA
CURRENT SENSE
Average OCP Trip Level
IOC_TRIP
82
Short-Circuit Protection Threshold
100
123
130
µA
% IOCP
Sensed Current Tolerance
74
78
83
µA
Sensed Current Tolerance
35
38
42
µA
Maximum Common-Mode Input Voltage
FN8696 Rev.5.00
Jul 12, 2018
7VLDO = 7.4V
5.7
V
VCC = PVCC = 7VLDO = 4.5V
2.8
V
Page 8 of 33
ISL68201
Electrical Specifications
All typical specifications TA = +25°C, VCC = 5V. Boldface limits apply across the operating temperature range,
-40°C to +85°C, unless otherwise stated. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
68
74
80
% DAC
FAULT PROTECTION
UVP Threshold Voltage
Latch
Start-Up OVP Threshold Voltage
0V ≤ VBOOT ≤ 1.08V
1.10
1.15
1.25
V
1.08V < VBOOT ≤ 1.55V
1.58
1.65
1.75
V
1.55V < VBOOT ≤ 1.85V
1.88
1.95
2.05
V
1.85V < VBOOT ≤ 2.08V
2.09
2.15
2.25
V
2.08V < VBOOT ≤ 2.53V
2.56
2.65
2.75
V
2.53V < VBOOT ≤ 3.33V
3.36
3.45
3.6
V
3.33V < VBOOT ≤ 5.5V
5.52
5.65
5.85
V
Start-Up OVP Hysteresis
100
mV
OVP Rising Threshold Voltage
VOVRTH
0.5 ≤ DAC ≤ 5.5
114
120
127
% DAC
OVP Falling Threshold Voltage
VOVFTH
0.5 ≤ DAC ≤ 5.5
96
100
108
% DAC
Over-Temperature Shutdown Threshold
READ_TEMP = 72h
20
22.31
26
% VCC
Over-Temperature Shutdown Reset Threshold
READ_TEMP = 8Eh
25
27.79
30
% VCC
1
V
SMBus/PMBus/I2C
Signal Input Low Voltage
Signal Input High Voltage
Signal Output Low Voltage
1.6
V
4mA pull-up current
DATE, ALERT # Pull-Down Impedance
11
CLOCK Maximum Speed
V
50
Ω
1.25
MHz
CLOCK Minimum Speed
0.05
Telemetry Update Rate
108
Timeout
PMBus Accessible Timeout from All Rails’ POR
0.4
25
See Figure 21
MHz
µs
30
35
ms
5.5
6.5
ms
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
FN8696 Rev.5.00
Jul 12, 2018
Page 9 of 33
ISL68201
Operation
The following sections provide a detailed description of the
ISL68201 operation.
In addition, based on the ON_OFF_CONFIG [02h] setting, the IC
can be enabled or disabled by the serial bus command
“OPERATION [01h]” and/or EN pin. See Table 11 on page 25 for
more details.
IC Supplies
Resistor Reader
The ISL68201 has four bias pins: VIN, 7VLDO, PVCC, and VCC.
The PVCC and 7VLDO voltage rails are 5V LDO and 7.4V LDO
supplied by VIN, respectively, while the VCC pin needs to connect
to the PVCC rail externally to be biased. For 5V input applications,
all these pins should be tied together and biased by a 5V supply.
Because the VIN pin voltage information is used by the R4
Modulator loop, the user CANNOT bias VIN with a series resistor.
In addition, the VIN pin CANNOT be biased independently from
other rails.
The ISL68201 offers four programming pins to customize their
regulator specifications. The details of these pins are summarized
in Table 2, followed by the detailed description of resistor reader
operation.
Enable and Disable
The IC is disabled until the 7VLDO, PVCC, VCC, VIN, and EN pins
increase above their respective rising threshold voltages and the
typical 5.5ms timeout (worst case = 6.5ms) expires, as shown in
Figures 21 and 22 on page 22. The controller becomes disabled
when the 7VLDO, PVCC, VCC, VIN, or EN pins drop below their
respective falling POR threshold voltages.
The precision threshold EN pin allows the user to set a precision
input UVLO level with an external resistor divider, as shown in
Figure 4. For 5V input applications or wide range input
applications, the EN pin can directly connect to VCC, as shown in
Figure 5. If an external enable control signal is available and is an
open-drain signal, a pull-up impedance (100k or higher) can be
used.
EXTERNAL CIRCUIT
ISL68201
VIN
100k
PIN
BIT
NAME
PROG1 [7:0]
BOOT-UP
VOLTAGE
PROG2 [7:7]
PWM/PFM
[6:5]
DESCRIPTION
Sets output boot-up voltage, 256
different options: 0, 0.5V to 5.5V (see
Table 7)
Enables PFM mode or forced PWM.
Temperature Adjusts NTC temperature compensation:
Compensation OFF, +5, +15, +30°C.
[4:0]
ADDR
Sets serial bus 32 different addresses
(see Table 10).
PROG3 [7:7]
USPFM
Ultrasonic (25kHz clamp) PFM enable
[6:6] Fault Behavior OCP fault behavior:
Latch, infinite 9ms retry
[5:3]
fSW
[2:0]
R4 Gain
PROG4 [7:5]
Sets switching frequency (fSW).
Sets error amplifier gain (AV).
RAMP_RATE
Sets soft-start and DVID ramp rate.
[4:3]
RR
Selects RR impedance for R4 loop.
[2:2]
AVMLTI
Selects AV gain multiplier (1x or 2x)
[1:0]
Not Used
Renesas has developed a high resolution ADC using a technique
with a simple 1%, 100ppm/K or better temperature coefficient
resistor divider. The same type of resistors are preferred so that it
has similar change over temperature. In addition, the divider is
compared to the internal divider off VCC and GND nodes and
therefore must refer to VCC and GND pins, not through any RC
decoupling network.
EN
SOFTSTART
TABLE 2. DEFINITION OF PROG PINS
9.09k
VIN UVLO = 10.08V/9.12V
FIGURE 4. INPUT UVP CONFIGURATION
ISL68201
EXTERNAL CIRCUIT
ISL68201
VCC
REGISTER
TABLE
REN
SOFTSTART
EXTERNAL CIRCUIT
VCC
OPTIONAL
EN
RUP
ADC
RDW
VIN UVLO = 4.20/3.95V
REN is needed ONLY if the user wants to
control the IC with an external enable signal
FIGURE 6. SIMPLIFIED RESISTOR DIVIDER ADC
FIGURE 5. 5V INPUT OR WIDE RANGE INPUT CONFIGURATION
FN8696 Rev.5.00
Jul 12, 2018
Page 10 of 33
ISL68201
The RUP and RDW values for a particular parameter set can be
found using the PowerNavigator GUI. Data for corresponding
registers can be read out using the serial PMBus command (DC
to DF). Note: The case of 10kΩ RUP or RDW is the same as 0kΩ
RUP or RDW.
TABLE 5. PROG 3 RESISTOR READER EXAMPLE
PROG3
(DE)
RUP
(kΩ)
00h
Open
0
Disabled
RDW ULTRASONIC
FAULT
(kΩ)
PFM
BEHAVIOR
R4 GAIN
fSW
(kHz)
1x
2x
Retry
300
42
84
TABLE 3. PROG 1 RESISTOR READER EXAMPLE
20h
Open
21.5
Disabled
Retry
700
42
84
PROG1
(DC)
RUP
(kΩ)
RDW
(kΩ)
VOUT
(V)
40h
Open
34.8
Disabled
Latch
300
42
84
00h
Open
0
0.797
60h
Open
52.3
Disabled
Latch
700
42
84
20h
Open
21.5
0.852
80h
Open
75
Enabled
Retry
300
42
84
40h
Open
34.8
0.898
A0h
Open
105
Enabled
Retry
700
42
84
60h
Open
52.3
0.953
C0h
Open
147
Enabled
Latch
300
42
84
80h
Open
75
1.000
A0h
Open
105
1.047
E0h
Open
499
Enabled
Latch
700
42
84
C0h
Open
147
1.102
1Fh
0
Open
Disabled
Retry
600
1
2
E0h
Open
499
1.203
3Fh
21.5
Open
Disabled
Retry
1500
1
2
1Fh
0
Open
1.352
5Fh
34.8
Open
Disabled
Latch
600
1
2
3Fh
21.5
Open
1.500
7Fh
52.3
Open
Disabled
Latch
1500
1
2
5Fh
34.8
Open
1.797
9Fh
75
Open
Enabled
Retry
600
1
2
7Fh
52.3
Open
2.500
BFh
105
Open
Enabled
Retry
1500
1
2
9Fh
75
Open
3.000
BFh
105
Open
3.297
DFh
147
Open
Enabled
Latch
600
1
2
DFh
147
Open
5.000
FFh
499
Open
Enabled
Latch
1500
1
2
FFh
499
Open
0.000
TABLE 6. PROG 4 RESISTOR READER EXAMPLE
TABLE 4. PROG 2 RESISTOR READER EXAMPLE
PROG2
(DD)
RUP
(kΩ)
RDW
(kΩ)
PWM/PFM
TEMP
COMP
PM_ADDR
(7-BIT)
00h
Open
0
Enabled
30
60h
20h
Open
21.5
Enabled
15
60h
40h
Open
34.8
Enabled
5
60h
60h
Open
52.3
Enabled
OFF
60h
80h
Open
75
Disabled
30
60h
A0h
Open
105
Disabled
15
60h
C0h
Open
147
Disabled
5
60h
E0h
Open
499
Disabled
OFF
60h
1Fh
0
Open
Enabled
30
7F
3Fh
21.5
Open
Enabled
15
7F
5Fh
34.8
Open
Enabled
5
7F
7Fh
52.3
Open
Enabled
OFF
7F
9Fh
75
Open
Disabled
30
7F
BFh
105
Open
Disabled
15
7F
DFh
147
Open
Disabled
5
7F
FFh
499
Open
Disabled
OFF
7F
FN8696 Rev.5.00
Jul 12, 2018
PROG4
(DF
RUP
(kΩ)
RDW
(kΩ)
SS RATE
(mV/µs)
(kΩ
AVMLTI
00h
Open
0
1.25
200
1x
20h
Open
21.5
2.5
200
1x
40h
Open
34.8
5
200
1x
60h
Open
52.3
10
200
1x
80h
Open
75
0.078
200
1x
A0h
Open
105
0.157
200
1x
C0h
Open
147
0.315
200
1x
E0h
Open
499
0.625
200
1x
1Fh
0
Open
1.25
800
2x
3Fh
21.5
Open
2.5
800
2x
5Fh
34.8
Open
5
800
2x
7Fh
52.3
Open
10
800
2x
9Fh
75
Open
0.078
800
2x
BFh
105
Open
0.157
800
2x
DFh
147
Open
0.315
800
2x
FFh
499
Open
0.625
800
2x
RR
Page 11 of 33
ISL68201
Soft-Start
The ISL68201-based regulator has four periods during soft-start,
as shown in Figure 7 on page 12. When the EN pin reaches
above its enable threshold, after a 5.5ms timeout (worst
case = 6.5ms) of bias supplies, the controller begins the first
soft-start ramp after a fixed soft-start delay period tD1 as shown
in Figures 21 and 22 on page 22. The output voltage reaches the
boot-up voltage (VBOOT) at a fixed slew rate in period tD2. Then,
the controller regulates the output voltage at VBOOT for another
period tD3 until SMBus/PMBus/ I2C sends a new VOUT
command. If the VOUT command is valid, the ISL68201 initiates
the ramp until the voltage reaches the new VOUT_COMMAND
voltage in period tD4. The soft-start time is the sum of the four
periods, as shown in Equation 1.
t SS = t D1 + t D2 + t D3 + t D4
(EQ. 1)
tD1 is a fixed delay with a typical value of 200µs. tD3 is determined
by the time to obtain a new valid VOUT_COMMAND voltage from
SMBus/PMBus/I2C bus. If the VOUT_COMMAND is valid before the
output reaches the boot-up voltage, the output turns around to
respond to the new VOUT_COMMAND code.
VBOOT< PRE-CHARGED < OVP
V PRECHARGED V PRECHARGED – V BOOT
t D2 = -------------------------------------------- + ----------------------------------------------------------------------- s
RAMP_RATE
RAMP_RATE
The ISL68201 supports precharged load start-up to the
maximum VOUT of 5.5V with sufficient boot capacitor charge. For
an extended precharged load, the boot capacitor discharges to
“PVCC - VOUT - VD” by the high-side drive circuits’ standby current.
For instance, during an extended 4V precharged load, the boot
capacitor reduces to a less-than-1V boot capacitor voltage, which
is insufficient to power up the VR; in this case, it is recommended
to let the output drop below 2.5V with an external bleed resistor
before issuing another soft-start command.
Boot-Up Voltage Programming
An 8-bit pin PROG1 is dedicated for the boot-up voltage
programmability, which offers 256 options 0V and 0.5V to 5.5V,
as in Table 7. The most popular boot-up voltage levels are placed
on the tie-low spots (0h, 20h, 40h, 60h, 80h, A0h, C0h, E0h) and
the tie-high spots (1Fh, 3Fh, 5Fh, 7Fh, 9Fh, BFh, DFh, FFh) for
easy programming, as summarized in Table 3. A 0V boot-up
voltage is considered as “OFF,” the driver is in tri-state and the
internal DAC sets to 0V.
In addition, if the VOUT_COMMAND (21h) is executed
successfully 5.5ms (typically, worst 6.5ms) after VCC POR and
before Enable, it overrides the boot-up voltage set by the PROG1
pin.
VOUT
VBOOT
PRE-CHARGED 10mV), reduce the
“TCOMP” value. If the IOUT pin voltage decreases over 10mV
as the temperature increases (that is, V1 - V2 > 10mV),
increase the “TCOMP” value. The “TCOMP” value can be
adjusted through the serial bus for easy thermal
compensation optimization.
IOUT Calibration
FIGURE 19. RECOMMENDED PLACEMENT OF NTC
The ISL68201 multiplexes the “TCOMP” value with the NTC
digital signal to obtain the adjustment gain to compensate the
temperature impact on the sensed channel current. The
compensated current signal is used for IOUT and overcurrent
protection functions. Use the TCOMP “OFF” code to disable
thermal compensation when the current sensing element is the
resistor or smart power stage (internally thermal compensated)
that has little thermal drifting.
TABLE 8. TCOMP VALUES
D1h
TCOMP (°C)
D1h
TCOMP (°C)
0h
30
2h
5
1h
15
3h
OFF
The thermal compensation design procedure for inductor current
sensing is summarized as follows:
1. Properly choose the voltage divider for the NTC pin to match
the NTC voltage vs temperature curve with the recommended
curve in Figure 18 on page 18.
The current flowing out of the IOUT pin is equal to the sensed
average current inside ISL68201. A resistor is placed from the
IOUT pin to GND to generate a voltage, which is proportional to
the load current and the resistor value, as shown in Equation 12:
R x xI OCP
2.5Vx -------------------------
2.5VxR ISEN
100A
R IOUT = ---------------------------------- = ----------------------------------------------63.875AxR x
63.875AxR x
2.5VxI OCP
25VxI OCP
= --------------------------------------------- = ----------------------------- k
63.875Ax100A
63.875A
where VIOUT is the voltage at the IOUT pin, RIOUT is the resistor
between the IOUT pin and GND, ILOAD is the total output current
of the converter, RISEN is the sense resistor connected to the
CSRTN pin, and RX is the DC resistance of the current sense
element, either the DCR of the inductor or RSENSE depending on
the sensing method. Scale the RIOUT resistor to ensure that the
voltage at the IOUT pin is typically 2.5V at 63.875A load current.
The IOUT voltage is linearly digitized every 108µs and stored in
the READ_IOUT register (8Ch).
4. Use Equation 9 to calculate the resistance of the NTC, and
find out the corresponding NTC temperature TNTC from the
NTC datasheet or using Equation 10, where is equal to 3380
for recommended NTC.
V TM xR
TM
R NTC at T NTC = ----------------------------V CC – V
(EQ. 9)
TM
T NTC = --------------------------------------------------------------------------------- – 273.15
R NTC at T NTC
ln --------------------------------------------- + ----------------- R NTC at 25C 298.15
FN8696 Rev.5.00
Jul 12, 2018
(EQ. 10)
EXTERNAL CIRCUIT
ISL68201
VCC
2. Operate the actual board under the full load and the desired
airflow condition.
3. After the board reaches the thermal steady state (often takes
15 minutes), record the temperature (TCSC) of the current
sense component (inductor) and the voltage at NTC and VCC
pins.
(EQ. 12)
RIOUT_UP
DIGITIZED
IOUT (8Ch)
IOUT
RIOUT_DW
FIGURE 20. IOUT NO LOAD OFFSET CALIBRATION
Place a small capacitor between IOUT and GND to reduce the
noise impact and provide averaging, > 200µs (typically).
To deal with layout and design variation of different platforms,
the ISL68201 is intentionally trimmed to negative at no load,
thus, an offset can easily be added to calibrate the digitized IOUT
reading (8Ch). Hence, the analog vs digitized current slope is set
Page 19 of 33
ISL68201
by the equivalent impedance of RIOUT_UP//RIOUT_DW = RIOUT
(as in Figure 20); the slope of the ideal curve should set to 1A/A
with 0A offset.
For a precision digital IOUT, follow the fine-tuned procedure below.
Steps 1 to 5 must be completed before Step 6.
1. Properly tune L/DCR or ESL/RSEN matching as shown on
page 17 over the range of temperature operation. +25%
over-matching L/DCR at room temperature is needed for
-40°C operation.
2. Properly complete thermal compensation as shown in
“Thermal Monitoring and Compensation” on page 18.
3. Finalize the RISEN resistor to set OCP for overall operating
conditions and board variations as shown in “Overcurrent and
Short-Circuit Protection” on page 20.
4. Collect no load IOUT current with sufficient prototypes and
determine the mean of no load IOUT current.
5. The pull-up impedance on IOUT pin should be
“VCC/IOUT_NO_LOAD”. For instance, a mean of -2.5µA IOUT at
0A load needs RIOUT_UP = 2MΩ.
6. Start with the value below and then fine-tune the RIOUT_DW
value until the average slope of various boards equals 1A/A.
R IOUT_UP xR IOUT
R IOUT_DW = -------------------------------------------------R IOUT_UP – R IOUT
(EQ. 13)
Fault Protection
The ISL68201 provides high system reliability with many fault
protections, as summarized in Table 9.
TABLE 9. FAULT PROTECTION SUMMARY
FAULT
Input UVLO
Bias UVLO
DESCRIPTION
FAULT ACTION
Shut down and recover
VIN pin UVLO; or set by EN pin
when VIN > UVLO
with an external divider for a
higher level. See Figures 4 and 5.
VCC, PVCC, 7VLDO UVLO
Shut down and recover
when Bias > UVLO
Start-Up OVP Higher than VBOOT. See Electrical Latch OFF, reset by VCC
Specifications on page 7.
or toggling enable
(including EN pin and/
Output OVP Rising = 120%; Falling = 100%
or OPERATION
command based on
Output UVP 74% of VOUT, Latch OFF
the ON_OFF_CONFIG
setting)
Output OCP
Average OCP = 100µA with
128µs blanking time.
Short-Circuit Peak OCP = 130% of Average
Protection
OCP with 50ns filter.
OTP
Latch OFF (reset by VCC
or toggling enable
including EN pin and/
or OPERATION
command based on
the ON_OFF_CONFIG
setting), or retry every
9ms; option is
programmable by
PROG3 or D3[0]
Rising = 22.31%VCC (~+136°C); Shut down above
Falling =27.79%VCC (~+122°C). +136°C and recover
when temperature
drops below +122°C
FN8696 Rev.5.00
Jul 12, 2018
The UVLO and OTP faults respond to the current state with
hysteresis, output OVP and output UVP faults are latch events,
and output OCP and output short-circuit faults can be latch or
retry events depending upon the PROG3 or D3[0] setting. All fault
latch events can be reset by VCC cycling, toggling the Enable pin
and/or the serial bus OPERATION command based on the
ON_OFF_CONFIG setting, while the OCP retry event has a hiccup
time of 9ms and the regulator can be recovered when the fault is
removed.
OVERVOLTAGE PROTECTION
The OVP fault detection circuit triggers after the voltage between
VSEN+ and VSEN- is above the rising overvoltage threshold.
When an OVP fault is declared, the controller latches off and the
PGOOD pin asserts low. The fault remains latched and can be
reset by VCC cycling or toggling EN pin and/or the serial bus
OPERATION command based on the ON_OFF_CONFIG setting.
Although the controller latches off in response to an OVP fault,
the LGATE gate-driver output retains the ability to toggle the lowside MOSFET on and off, in response to the output voltage
transversing the OVP rising and falling thresholds. The LGATE
gate driver turns on the low-side MOSFET to discharge the output
voltage, protecting the load. The LGATE gate driver turns off the
low-side MOSFET when the sensed output voltage is lower than
the falling overvoltage threshold (typically 100%). If the output
voltage rises again, the LGATE driver turns on the low-side MOSFET
again when the output voltage is above the rising overvoltage
threshold (typically 120%). By doing so, the IC protects the load
when there is a consistent overvoltage condition.
In addition to normal operation OVP, 5.5ms (typically, worst
case = 6.5ms) after all rails (VCC, PVCC, 7VLDO, VIN) POR and
before the end of soft-start, the start-up OVP circuits are enabled
to protect against an OVP event, while the OVP level is set higher
than VBOOT. See Electrical Specifications on page 7.
UNDERVOLTAGE PROTECTION
The UVP fault detection circuit triggers when the output voltage is
below the undervoltage threshold (typically 74% of DAC). When a
UVP fault is declared, the controller latches off, forcing the LGATE
and UGATE gate-driver outputs low, and the PGOOD pin asserts
low. The fault remains latched and can be reset by VCC cycling or
toggling the EN pin and/or the serial bus OPERATION command
based on the ON_OFF_CONFIG setting.
OVERCURRENT AND SHORT-CIRCUIT PROTECTION
The average Overcurrent Protection (OCP) is triggered when the
internal current out of the IOUT pin goes above the fault
threshold (typically 100µA) with 128µs blanking time. It also has
a fast (50ns filter) secondary overcurrent protection whose
threshold is +30% above average OCP. This protects inductor
saturation from a short-circuit event and provides a more robust
power train and system protection. When an OCP or short-circuit
fault is declared, the controller latches off, forcing the LGATE and
UGATE gate-driver outputs low, or retries with a hiccup time of
9ms. The fault response is programmable by PROG3 or D3[0].
However, the latched off event can be reset by VCC cycling,
toggling the EN pin, and/or the serial bus OPERATION command
based on the ON_OFF_CONFIG setting.
Page 20 of 33
ISL68201
Equation 14 provides a starting point to set a preliminary OCP
trip point, in which IOCP is the targeted OCP trip point and DI (as
in Equation 15) is the peak-to-peak inductor ripple current.
PFM Mode Operation
I
R x x ----- + I OCP
2
R ISEN2 = ------------------------------------------------------------100Ax 100% + 30%
In PFM mode, programmable by PROG2 or serial bus D0[0:0],
the switching frequency is dramatically reduced to minimize the
switching loss and significantly improve light-load efficiency. The
ISL68201 can enter and exit PFM mode seamlessly as the load
changes. The PFM mode is only compatible with the ISL99140
DrMOS with SMOD input by connecting to ISL68201’s FCCM
output pin. Incompatible power stages should operate in PWM
mode.
R ISEN = MAX (R ISEN1, R ISEN2
SMBus, PMBus, and I2C Operation
To deal with layout and PCB contact impedance variation, follow
the fine-tuning procedure below for a more precise OCP. Steps 1 to
3 must be completed before Step 4.
The ISL68201 features SMBus, PMBus, and I2C with 32
programmable addresses through the PROG2 pin, while
SMBus/PMBus includes an Alert# line (SALERT) and Packet Error
Check (PEC) to ensure data properly transmitted. The telemetry
update rate is 108µs (typically). The supported
SMBus/PMBus/I2C addresses are summarized in Table 10. The
7-bit format address does not include the last bit (write and
read): 40-47h, 60-67h, and 70-7Fh.
R x xI OCP
R ISEN1 = -----------------------100A
(EQ. 14)
1. Properly tune L/DCR or ESL/RSEN matching as shown on
page 17 over the range of temperature operation. +25%
over-matching L/DCR at room temperature is needed for
-40°C operation.
2. Properly complete thermal compensation as shown in
“Thermal Monitoring and Compensation” on page 18.
3. Collect OCP trip points (IOCP_MEASURED) with sufficient
prototypes and determine the mean for overall operating
conditions and board variations.
4. Change RISEN by IOCP_TARGETED/IOCP_MEASURED
percentage to meet the targeted OCP.
Note that if the inductor peak-to-peak current is higher or closer
to 30%, the +30% threshold could be triggered instead of the
average OCP threshold. However, the fine-tuning procedure can
still be used.
OVER-TEMPERATURE PROTECTION
As shown in Figure 16 on page 18, there is a comparator with
hysteresis to compare the NTC pin voltage to the threshold set.
When the NTC pin voltage is lower than 22.31% of the VCC
voltage (typically +136°C), it triggers Over-Temperature
Protection (OTP) and shuts down the ISL68201. When the NTC
pin voltage is above 27.79% of the VCC voltage (typically
+122.4°C), the ISL68201 resumes normal operation. When an
OTP fault is declared, the controller forces the LGATE and UGATE
gate-driver outputs low.
PGOOD Monitor
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. If there is a fault condition of a rail’s
(VCC, PVCC, 7VLDO, or VIN) UVLO, output Overcurrent (OCP),
Overvoltage (OVP), Undervoltage (UVP), or Over-Temperature (OTP),
PGOOD is asserted low. Note that the PGOOD pin is an undefined
impedance with insufficient VCC (typically
VOUT_MAX, or VOUT OPEN SENSE)
Input Voltage (N = - 4, Max = 31.9375V)
VIN (V) = HEX2DEC(88 hex data - E000h) * 0.0625V
Page 25 of 33
ISL68201
TABLE 11. SMBus, PMBus, AND I2C SUPPORTED COMMANDS (Continued)
COMMAND
CODE
ACCESS
WORD
LENGTH
(BYTE)
8Dh[15:0]
R
TWO
98h[7:0]
R
ONE
02h
PMBUS_REVISION
AD[15:0]
BLOCK R
TWO
8201h
IC_DEVICE_ID
AE[15:0]
BLOCK R
TWO
0003h
D0[0:0]
R/W
ONE
PROG2[7:7]
ENABLE_PFM
PFM OPERATION
0h = PFM Enabled (DCM at light load)
1h = PFM Disabled (always CCM mode)
D1[1:0]
R/W
ONE
PROG2[6:5]
TEMP_COMP
Thermal Compensation:
0h = 30°C; 01h = 15°C; 02h = 5°C; 03h = OFF
D2[0:0]
R/W
ONE
PROG3[7:7]
D3[0:0]
R/W
ONE
PROG3[6:6]
OCP_BEHAVIOR
D4[2:0]
R/W
ONE
PROG3[2:0]
AV_GAIN
D5{2:0]
R/W
ONE
PROG4[7:5]
RAMP_RATE
D6[1:0]
R/W
ONE
PROG4[4:3]
SET_RR
DC[7:0]
R
ONE
READ_PROG1
Read PROG1
DD{7:0]
R
ONE
READ_PROG2
Read PROG2
DE[7:0]
R
ONE
READ_PROG3
Read PROG3
DF[7:0]
R
ONE
READ_PROG4
Read PROG4
DEFAULT
VALUE
COMMAND NAME
READ_TEMP
DESCRIPTION
VR Temperature
TEMP (°C) = 1/{ln[Rup*HEX2DEC(8D hex
data)/(511 - HEX2DEC(8D hex data)/RNTC(at +25°C)]/Beta +
1/298.15} -273.15
Indicates PMBus Revision 1.2
ISL68201 Device ID
IC_DEVICE_REVISION ISL68201 Device Revision
ENABLE_ULTRASONIC Ultrasonic PFM Enable
0h = 25kHz Clamp Disabled
1h = 25kHz Clamp Enabled
Set latch or infinite retry for OCP fault:
0h = Retry every 9ms; 01 = Latch-OFF
R4 AV GAIN (PROG4, AV Gain Multiplier = 2x)
0h = 84; 1h = 73; 2h = 61; 3h = 49
4h = 38; 5h = 26; 6h = 14; 7h = 2
R4 AV GAIN (PROG4, AV Gain Multiplier = 1x)
0h = 42; 1h = 36.5; 2h = 30.5; 3h = 29.5
4h = 19; 5h = 13; 6h = 7; 7h = 1
Soft-Start and Margining DVID Rate (mV/µs)
0h = 1.25; 1h = 2.5; 2h = 5; 3h = 10; 4h = 0.078; 5h = 0.157
6h = 0.315; 7h = 0.625;
Set RR
0h = 200k; 01h = 400k; 02h = 600k; 03h = 800k
NOTE: Serial bus communication is valid 5.5m (typically, worst 6.5ms) after VCC, VIN, 7VLDO, and PVCC above POR. The telemetry update rate is 108µs.
R4 Modulator
STABILITY
The R4 modulator is an evolutionary step in R3 technology. Like
R3, the R4 modulator is a linear control loop and variable
frequency control during load transients to eliminate beat
frequency oscillation at the switching frequency and maintains
the benefits of current-mode hysteretic controllers. In addition,
the R4 modulator reduces regulator output impedance and uses
accurate referencing to eliminate the need for a high-gain
voltage amplifier in the compensation loop. The result is a
topology that can be tuned to voltage-mode hysteretic transient
speed while maintaining a linear control model and removes the
need for any compensation. This greatly simplifies the regulator
design for customers and reduces external component cost.
The removal of compensation derives from the R4 modulator’s
lack of need for high DC gain. In traditional architectures, high DC
gain is achieved with an integrator in the voltage loop. The
integrator introduces a pole in the open-loop transfer function at
low frequencies. That, combined with the double-pole from the
output L/C filter, creates a three pole system that must be
compensated to maintain stability.
FN8696 Rev.5.00
Jul 12, 2018
Classic control theory requires a single-pole transition through
unity gain to ensure a stable system. Current-mode architectures
(includes peak, peak-valley, current-mode hysteric, R3, and R4)
generate a zero at or near the L/C resonant point, effectively
canceling one of the system’s poles. The system still contains
two poles, one of which must be canceled with a zero before
unity gain crossover to achieve stability.
Page 26 of 33
ISL68201
COMPENSATION TO COUNTER
INTEGRATOR
FOR HIGH DC GAIN
INTEGRATOR POLE
R4 LOOP GAIN (dB)
L/C DOUBLE-POLE
VOUT
p1
VCOMP
SYSTEM HAS 2 POLES
AND 1 ZERO
p2
VDAC
FIGURE 25. CLASSICAL INTEGRATOR ERROR-AMPLIFIER
CONFIGURATION
Because R4 does not require a high-gain voltage loop, the
integrator can be removed, reducing the number of inherent
poles in the loop to two. The current-mode zero continues to
cancel one of the poles, ensuring a single-pole crossover for a
wide range of output filter choices. The result is a stable system
with no need for compensation components or complex
equations to properly tune the stability.
NO COMPENSATOR IS
NEEDED
ec
/d
B
0d dec
-2
/
B
c
0d
/ de
-2
dB
-40
Figure 25 illustrates the classic integrator configuration for a
voltage loop error amplifier. While the integrator provides the
high DC gain required for accurate regulation in traditional
technologies, it also introduces a low-frequency pole into the
control loop. Figure 26 shows the open-loop response that results
from the addition of an integrating capacitor in the voltage loop.
The compensation components found in Figure 25 are necessary
to achieve stability.
CURRENT-MODE
ZERO
z1
f (Hz)
FIGURE 28. UNCOMPENSATED R4 OPEN-LOOP RESPONSE
TRANSIENT RESPONSE
In addition to requiring a compensation zero, the integrator in
traditional architectures also slows system response to transient
conditions. The change in COMP voltage is slow in response to a
rapid change in output voltage. If the integrating capacitor is
removed, COMP moves as quickly as VOUT, and the modulator
immediately increases or decreases switching frequency to
recover the output voltage.
Figure 27 shows the R4 error amplifier that does not require an
integrator for high DC gain to achieve accurate regulation. The
result to the open loop response can be seen in Figure 28.
IOUT
t
R4
R3
VCOMP
R3 LOOP GAIN (dB)
INTEGRATOR POLE
p1
t
L/C DOUBLE-POLE
VOUT
p2
-20dB CROSSOVER
REQUIRED FOR STABILITY
p3
COMPENSATOR TO
ADD z2 IS NEEDED
CURRENT-MODE
ZERO
z1
0
-2
d
-40
ec
ec
c
de
/d
dB
B/
-60dB/d
f (Hz)
FIGURE 26. UNCOMPENSATED INTEGRATOR OPEN-LOOP RESPONSE
R2
VOUT
VCOMP
R1
+
VDAC
FIGURE 27. NON-INTEGRATED R4 ERROR-AMPLIFIER
CONFIGURATION
FN8696 Rev.5.00
Jul 12, 2018
t
FIGURE 29. R3 vs R4 IDEALIZED TRANSIENT RESPONSE
The dotted red and blue lines in Figure 29 represent the time
delayed behavior of VOUT and VCOMP in response to a load
transient when an integrator is used. The solid red and blue lines
illustrate the increased response of R4 in the absence of the
integrator capacitor.
To optimize transient response and improve phase margin for
very wide range applications, the ISL68201 integrates selectable
AV and RR options that move the DC gain and z1 point, as shown
in Figure 28. However, the defaulted AV gain of 42 and RR of
200kΩ can cover many cases and provides sufficient gain and
phase margin. For some extreme cases, lower AV gain and bigger
RR values are needed to provide a better phase margin and
improve transient ringback. The optimal choice AV and RR can
be obtained by simple monitoring transient response when
adjusting AV and RR values through the serial bus.
Page 27 of 33
ISL68201
General Application Design
Guide
Thus, after the output capacitors are selected, the maximum
allowable ripple voltage, VP-P(MAX), determines the lower limit on
the inductance, as shown in Equation 16.
This design guide provides a high-level explanation of the steps
necessary to design a single-phase buck converter. It is assumed
that the reader is familiar with many of the basic skills and
techniques referenced in the following. In addition to this guide,
complete reference designs that include schematics, bills of
materials, and example board layouts are provided.
Output Filter Design
The output inductors and the output capacitor bank together to
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must provide
the transient energy until the regulator can respond. The output
filter limits the system transient response, because it has a low
bandwidth compared to the switching frequency. The output
capacitor must supply or sink load current while the current in
the output inductors increases or decreases to meet the
demand.
In high-speed converters, the output capacitor bank is usually the
most costly (and often the largest) part of the circuit. Output filter
design begins with minimizing the cost of this part of the circuit.
The critical load parameters in choosing the output capacitors are
the maximum size of the load step, I; the load current slew rate,
di/dt; and the maximum allowable output voltage deviation under
transient loading, VMAX. Capacitors are characterized according
to their capacitance, ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage initially
deviates by an amount approximated by the voltage drop across
the ESL. As the load current increases, the voltage drop across
the ESR increases linearly until the load current reaches its final
value. The capacitors selected must have sufficiently low ESL and
ESR so that the total output voltage deviation is less than the
allowable maximum. Neglecting the contribution of inductor
current and regulator response, the output voltage initially
deviates by an amount, as shown in Equation 15:
I
ESL
1
V I ESR + ---------------- V IN + ----------------- --------------------------L OUT
C OUT 8 N f
(EQ. 15)
SW
V OUT 1 – D
I = --------------------------------------L OUT f
SW
The filter capacitor must have sufficiently low ESL and ESR so
that V < VMAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination with
bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the bulk
capacitors allows them to supply the increased current with less
output voltage deviation. The ESR of the bulk capacitors also
creates the majority of the output voltage ripple. As the bulk
capacitors sink and source the inductor AC ripple current, a
voltage develops across the bulk capacitor ESR equal to
IL(P-P) (ESR).
FN8696 Rev.5.00
Jul 12, 2018
V OUT V IN – V OUT
L OUT ESR -------------------------------------------------------f SW V IN V P-P(MAX)
(EQ. 16)
Because the capacitors are supplying a decreasing portion of the
load current while the regulator recovers from the transient, the
capacitor voltage becomes slightly depleted. The output
inductors must be capable of assuming the entire load current
before the output voltage decreases more than VMAX. This
places an upper limit on inductance.
Equation 17 gives the upper limit on L for cases when the trailing
edge of the current transient causes a greater output to voltage
deviation than the leading edge. Equation 18 addresses the
leading edge. Normally, the trailing edge dictates the selection of
L because duty cycles are usually less than 50%. Nevertheless,
both inequalities should be evaluated, and L should be selected
based on the lower of the two results. In Equations 17 and 18,
L is the per-channel inductance and C is the total output
capacitance.
2 C V OUT
L OUT -------------------------------V MAX – I ESR
I 2
(EQ. 17)
1.25 C- V
L OUT ------------------MAX – I ESR V IN – V OUT
I 2
(EQ. 18)
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper MOSFETs.
Their RMS current capacity must be sufficient to handle the AC
component of the current drawn by the upper MOSFETs, which is
related to duty cycle and the number of active phases. The input
RMS current can be calculated with Equation 19.
I IN RMS =
D
D – D 2 Io 2 + ------ I 2
12
(EQ. 19)
Use Figure 30 on page 29 to determine the input capacitor RMS
current requirement given the duty cycle, maximum sustained
output current (IO), and the ratio of the per-phase peak-to-peak
inductor current (IL(P-P) to IO). Select a bulk capacitor with a ripple
current rating that minimizes the total number of input capacitors
required to support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25 times greater than the
maximum input voltage.
Low capacitance, high-frequency ceramic capacitors are needed
in addition to the bulk capacitors to suppress leading and falling
edge voltage spikes. The result of the high current slew rates
produced by the upper MOSFETs turn on and off requires low ESL
ceramic capacitors, which should be placed as close as possible
to each upper MOSFET drain to minimize board parasitic
impedances and maximize noise suppression.
Page 28 of 33
ISL68201
Tables 12 and 13 provide a design and layout checklist that the
designer can reference.
INPUT-CAPACITOR CURRENT (IRMS/IO)
0.6
TABLE 12. DESIGN AND LAYOUT CHECKLIST
IL(P-P) = 0.75 IO
0.4
IL(P-P) = 0
PIN
NAME
NOISE
SENSITIVITY
EN
YES
There is an internal 1µs filter. Decoupling the
capacitor is NOT needed, but if needed, use a
low time constant one to avoid too large a
shutdown delay.
VIN
YES
Place 16V+ X7R 1µF in close proximity to the
pin and the system ground plane.
7VLDO
YES
Place 10V+ X7R 1µF in close proximity to the
pin and the system ground plane.
VCC
YES
Place X7R 1µF in close proximity to the pin and
the system ground plane.
SCL, SDA
YES
50kHz to 1.25MHz signal when the SMBus,
PMBus, or I2C is sending commands. Pairing
up with SALERT and routing carefully back to
SMBus, PMBus or I2C master. 20 mils spacing
within SDA, SALERT, and SCL; and more than
30 mils to all other signals. Refer to the SMBus,
PMBus or I2C design guidelines and place
proper terminated (pull-up) resistance for
impedance matching. Tie them to GND when
not used.
SALERT
NO
Open-drain and high dv/dt pin during
transitions. Route it in the middle of SDA and
SCL. Tie it to GND when not used.
PGOOD
NO
Open-drain pin. Tie it to GND when not used.
RGND,
VSEN
YES
Differential pair routed to the remote sensing
points with sufficient decoupling ceramics
capacitors and not across or go above/under
any switching nodes (BOOT, PHASE, UGATE,
LGATE) or planes (VIN, PHASE, VOUT) even
though they are not in the same layer. At least
20 mils spacing from other traces. DO NOT
share the same trace with CSRTN.
CSRTN
YES
Connect to the output rail side of the output
inductor or current sensing resistor pin with a
series resistor in close proximity to the pin. The
series resistor sets the current gain and should
be within 40Ωand 3.5kΩ. Decoupling
(~ 0.1µF/X7R) on the output end (not the pin) is
optional and might be required for long sense
trace and a poor layout (see Figures 9 and 10).
CSEN
YES
Connect to the phase node side of the output
inductor or current sensing resistor pin with
L/DCR or ESL/RSEN matching network in close
proximity to CSEN and CSRTN pins.
Differentially routing back to the controller with
at least 20 mils spacing from other traces.
Should NOT cross or go above/under the
switching nodes [BOOT, PHASE, UGATE, LGATE],
and power planes (VIN, PHASE, VOUT) even
though they are not in the same layer.
IL(P-P) = 0.5 IO
0.2
0
0
0.2
0.4
0.6
DUTY CYCLE (VOUT/VIN)
0.8
1.0
FIGURE 30. NORMALIZED INPUT-CAPACITOR RMS CURRENT vs
DUTY CYCLE FOR SINGLE-PHASE CONVERTER
Design and Layout Considerations
To ensure a first pass design, the schematics design must be
done correctly with correct pinout and net names, and the board
must be carefully laid out.
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board or internal layers.
The ground-plane layer should be in between power layers and
the signal layers to provide shielding, often the layer below the
top and the layer above the bottom should be the ground layers.
The two sets of components in a DC/DC converter are the power
components and the small signal components. The power
components are the most critical because they switch large
amounts of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first. These include
MOSFETs, input and output capacitors, and the inductor. Keeping
the distance between the power train and the control IC short
helps keep the gate drive traces short. These drive signals
include the LGATE, UGATE, GND, PHASE, and BOOT.
When placing MOSFETs, keep the source of the upper MOSFETs
and the drain of the lower MOSFETs as close as thermally
possible. Input high-frequency capacitors should be placed close
to the drain of the upper MOSFETs and the source of the lower
MOSFETs. Place the output inductor and output capacitors
between the MOSFETs and the load. Place high frequency output
decoupling capacitors (ceramic) as close as possible to the
decoupling target, making use of the shortest connection paths
to any internal planes. Place the components in such a way that
the area under the IC has less noise traces with high dV/dt and
di/dt, such as gate signals, phase node signals, and VIN plane.
FN8696 Rev.5.00
Jul 12, 2018
DESCRIPTION
Page 29 of 33
ISL68201
TABLE 12. DESIGN AND LAYOUT CHECKLIST (Continued)
PIN
NAME
NOISE
SENSITIVITY
NTC
YES
IOUT
PROG1-4
GND
FCCM
PWM
YES
NO
YES
NO
NO
TABLE 13. TOP LAYOUT TIPS
DESCRIPTION
NUMBER
DESCRIPTION
Place an NTC 10k (Murata, NCP15XH103J03RC,
= 3380) in close proximity to the output
inductor’s output rail, not close to MOSFET side
(see Figure 19); the return trace should be
20 mils away from other traces. Place 1.54kΩ
pull-up and decoupling capacitor (typically
0.1µF) in close proximity to the controller. The
pull-up resistor should be exactly tied to the
same point as VCC pin, not through an RC filter.
If not used, connect this pin to VCC.
1
The layer next to controller (top or bottom) should be a ground
layer. Separate analog ground and power ground with a 0Ω
resistor is highly NOT recommended. Directly connect GND
PAD to low noise area of the system ground with at least four
vias.
2
Never place controller and its external components above or
under VIN plane or any switching nodes.
3
Never share CSRTN and VSEN on the same trace.
4
Place the input rail decoupling ceramic capacitors closely to
the high-side FET on the same layer as possible. Never use
only one via and a trace connect the input rail decoupling
ceramics capacitors; must connect to VIN and GND planes.
5
Place all decoupling capacitors in close proximity to the
controller and the system ground plane.
6
Connect remote sense (VSEN and RGND) to the load and
ceramic decoupling capacitors nodes; never run this pair
above or below switching noise plane.
7
Always double check critical component pinout and their
respective footprints.
Scale R so that the IOUT pin voltage is 2.5V at
63.875A load. Place R and C in general
proximity to the controller. The time constant of
RC should be sufficient as an averaging
function (>200µs) for the digital IOUT. An
external pull-up resistor to VCC placeholder is
recommended to cancel IOUT offset at 0A load.
See “IOUT Calibration” on page 19
The resistor divider must be referenced to VCC
pin and the system ground (GND); they can be
placed anywhere. DO NOT use decoupling
capacitors on these pins.
Directly connect to a low noise area of the
system ground. The GND PAD should use at
least four vias. Separate analog ground and
power ground with a 0Ω resistor is highly NOT
recommended.
DO NOT place it across or under external
components of the controller. Keep it at least
20 mils away from sensitive nodes.
DO NOT place it across or under external
components of the controller. Keep it at least
20 mils away from any other traces.
LGIN
NO
Keep it at least 20 mils away from sensitive
nodes. A series 100Ω resistor to low-side gate
signal is required for noise attenuation.
PVCC
YES
Place X7R 4.7µF in proximity to the PVCC pin
and the system ground plane.
FN8696 Rev.5.00
Jul 12, 2018
Voltage Regulator Design Materials
To support VR design and layout, Renesas also developed a set of
tools and evaluation boards, as listed in Table 14 and Ordering
Information on page 5. Contact the local office or field support
for the latest available information.
TABLE 14. AVAILABLE DESIGN ASSISTANCE MATERIALS
ITEM
1
DESCRIPTION
SMBus/PMBus/I2C communication tool with the
PowerNavigator GUI.
2
Evaluation board schematics in OrCAD format and
layout in Allegro format. See Ordering Information
on page 5 for details.
Page 30 of 33
ISL68201
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
Jul 12, 2018
FN8696.5
Updated Ordering information table by adding tape and reel options to table and updating Note 1.
Updated Equation 10.
Removed About Intersil section and updated disclaimer.
Oct 17, 2017
FN8696.4
Updated Pin 11 and 12 descriptions on page 6.
Sep 25, 2017
FN8696.3
Updated LGIN pin description.
Updated Figure 4, changed “10.2V/9.24V” to “10.08V/9.12V”.
Updated 3Fh RUP value in Table 3.
Replaced entire paragraph on page 11.
Added units to R = 348Ω on page 17 above Figure 11.
On page 28 last sentence in paragraph in left column changed “IC(P-P)” to “IL(P-P)”.
Aug 29, 2017
FN8696.2
For Figures 1 and 2 on page 3, added a resistor to the CSRTN circuit.
On page 1, updated the Related Literature section to current standards.
Added three demonstration boards to the Ordering Information table on page 5.
Removed Table 15 on page 30 because the demonstration board information is in the Ordering Information
section.
Mar 7, 2016
FN8696.1
Removed unreleased parts from Table 1.
Mar 2, 2016
FN8696.0
Initial release
FN8696 Rev.5.00
Jul 12, 2018
CHANGE
Page 31 of 33
ISL68201
Package Outline Drawing
For the most recent package outline drawing, see L24.4x4C.
L24.4x4C
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
4.00
4X 2.5
A
20X 0.50
B
19
PIN 1
INDEX AREA
PIN #1 CORNER
(C 0 . 25)
24
1
18
4.00
2 . 50 ± 0 . 15
13
0.15
(4X)
12
7
0.10 M C A B
0 . 07
24X 0 . 23 +- 0
. 05 4
24X 0 . 4 ± 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0 . 90 ± 0 . 1
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
(
2 . 50 )
( 20X 0 . 5 )
C
0 . 2 REF
5
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8696 Rev.5.00
Jul 12, 2018
Page 32 of 33
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
5.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
you or third parties arising from such alteration, modification, copying or reverse engineering.
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all
liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6.
When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9.
Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2)
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A.
Tel: +1-408-432-8888, Fax: +1-408-434-5351
Renesas Electronics Canada Limited
9251 Yonge Street, Suite 8309 Richmond Hill, Ontario Canada L4C 9T3
Tel: +1-905-237-2004
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
Room 1709 Quantum Plaza, No.27 ZhichunLu, Haidian District, Beijing, 100191 P. R. China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, 200333 P. R. China
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999
Renesas Electronics Hong Kong Limited
Unit 1601-1611, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2265-6688, Fax: +852 2886-9022
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Malaysia Sdn.Bhd.
Unit 1207, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics India Pvt. Ltd.
No.777C, 100 Feet Road, HAL 2nd Stage, Indiranagar, Bangalore 560 038, India
Tel: +91-80-67208700, Fax: +91-80-67208777
Renesas Electronics Korea Co., Ltd.
17F, KAMCO Yangjae Tower, 262, Gangnam-daero, Gangnam-gu, Seoul, 06265 Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5338
© 2018 Renesas Electronics Corporation. All rights reserved.
Colophon 7.0
工商网监
湘ICP备2023018690号
