Datasheet
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
Improved Industry Standard Single-Ended Current Mode PWM Controller
The ISL6840, ISL6841, ISL6842, ISL6843, and
ISL6844 (ISL684x) family of adjustable frequency, low
power, Pulse-Width Modulating (PWM) current mode
controllers is designed for a wide range of power
conversion applications including boost, flyback, and
isolated output configurations. Peak current mode
control effectively handles power transients and
provides inherent overcurrent protection.
This advanced BiCMOS design is pin-compatible with
the industry standard 384x family of controllers and
offers significantly improved performance. Features
include low operating current, 60µA start-up current,
adjustable operating frequency to 2MHz, and high
peak current drive capability with 20ns rise and fall
times.
Part Number
Rising UVLO (V)
MAX. Duty Cycle (%)
ISL6840
7.0
100
ISL6841
7.0
50
ISL6842
14.4
100
ISL6843
8.4
100
ISL6844
14.4
50
Features
• 1A MOSFET gate driver
• 60µA start-up current, 100µA maximum
• 25ns propagation delay current sense to output
• Fast transient response with peak current mode
control
• Adjustable switching frequency to 2MHz
• 20ns rise and fall times with 1nF output load
• Trimmed timing capacitor discharge current for
accurate deadtime/maximum duty cycle control
• High bandwidth error amplifier
• Tight tolerance voltage reference over line, load,
and temperature
• Tight tolerance current limit threshold
• Pb-free available (RoHS compliant)
Applications
• Telecom and datacom power
• Wireless base station power
Related Literature
• File server power
For a full list of related documents, visit our website:
• Industrial power systems
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
device pages
• PC power supplies
• Isolated buck and flyback regulators
• Boost regulators
FN9124 Rev.14.00
Jul.22.19
Page 1 of 17
1.1
Overview
Typical Applications
CR5
+3.3V
T1
VIN+
R3
C21
R21
+ C15
+ C16
+1.8V
C4
CR4
C2
C17
CR2
C5
C22
+
+
C20
C19
RETURN
CR6
R1
36V to 75V
C1
R17
R16
C6
C3
R18
R19
U2
Q1
C14
R4
R22
VIN-
U3
R27
C13
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
FN9124 Rev.14.00
Jul.22.19
1.
R15
R20
U4
R26
COMP
CS
FB
VREF
V DD
OUT
RTCT
GND
ISL684x
R6
R10
CR1
Q3
C12
C8
Figure 1. 48V Input Dual Output Flyback
R13
C11
1. Overview
Page 2 of 17
VR1
C10
CR1
L1
VIN+
+VOUT
+
C2
C3
R4
Q1
RETURN
R5
C9
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
FN9124 Rev.14.00
Jul.22.19
R8
C1
R1
R2
U1
COMP
ISL684x
FB
CS
C4
RTCT
R7
VREF
VIN+
VDD
C8
R6
OUT
GND
R3
C7
C5
C6
VIN-
1. Overview
Page 3 of 17
Figure 2. Boost Converter
Functional Block Diagram
VREF
5.00V
VDD
UVLO
Comparator
Enable
VREF Fault
BG +-
VREF
UV Comparator
4.65V 4.80V
GND
A
2.5V
+
+
-
VDD OK
+
-
VREF
BG
A = 0.5
PWM
Comparator
+
-
CS
100mV
Error
Amplifier
2R
+
-
FB
+
-
1.1V
Clamp
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
FN9124 Rev.14.00
Jul.22.19
1.2
ISL6841/ISL6844
Only
Q
R
T
Q
COMP
OUT
VREF
S Q
R Q
2.6V
0.7V
Reset
Dominant
ON
Oscillator
Comparator
+
RTCT
8.4mA
P/N
-40, -41
-42, -44
-43
UVLO On/Off
7.0/6.6V
14.3/8.8V
8.4/7.2V
Figure 3. Block Diagram
1. Overview
Page 4 of 17
ON
Clock
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
1.3
1. Overview
Ordering Information
Part Number
(Notes 2, 3)
Part Marking
Temp Range
(°C)
Tape and Reel
(Units) (Note 1)
ISL6840IBZ-T
6840 IBZ
-40 to +105
2.5k
ISL6840IRZ-T
40Z
-40 to +105
6k
ISL6840IUZ
6840Z
-40 to +105
-
Package
Pkg. Dwg. #
8 Ld SOIC
M8.15
8 Ld 2x3 DFN
L8.2x3
8 Ld MSOP
M8.118
ISL6840IUZ-T
6840Z
-40 to +105
2.5k
8 Ld MSOP
M8.118
ISL6841IUZ (No longer available,
recommended replacement: ISL8841AAUZ)
6841Z
-40 to +105
-
8 Ld MSOP
M8.118
ISL6841IUZ-T (No longer available,
6841Z
recommended replacement: ISL8841AAUZ-T)
-40 to +105
2.5k
8 Ld MSOP
M8.118
ISL6842IBZ
-40 to +105
-
8 Ld SOIC
M8.15
6842 IBZ
ISL6842IBZ-T
6842 IBZ
-40 to +105
2.5k
8 Ld SOIC
M8.15
ISL6843IBZ
6843 IBZ
-40 to +105
-
8 Ld SOIC
M8.15
ISL6843IBZ-T
6843 IBZ
-40 to +105
2.5k
8 Ld SOIC
M8.15
ISL6843IUZ
6843Z
-40 to +105
-
8 Ld MSOP
M8.118
2.5k
8 Ld MSOP
M8.118
8 Ld SOIC
M8.15
ISL6843IUZ-T
6843Z
-40 to +105
ISL6844IBZ (No longer available,
recommended replacement: ISL8844AABZ)
6844 IBZ
-40 to +105
ISL6841EVAL3Z (No longer available or
supported)
Evaluation Board
Notes:
1. See TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J-STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL6840, ISL6841, ISL6842, ISL6843, and ISL6844 device information pages. For more
information about MSL, see TB363.
1.4
Pin Configurations
8 LD SOIC, MSOP
Top View
COMP 1
8 VREF
FB 2
7 VDD
CS 3
6 OUT
RTCT 4
5 GND
FN9124 Rev.14.00
Jul.22.19
8 Ld DFN
Top View
COMP
1
8
VREF
FB
2
7
VDD
CS
3
6
OUT
RTCT
4
5
GND
Page 5 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
1.5
1. Overview
Pin Descriptions
Pin Number
Pin Name
Description
1
COMP
2
FB
The output voltage feedback is connected to the inverting input of the error amplifier through this pin. The
non-inverting input of the error amplifier is internally tied to a reference voltage.
3
CS
The current sense input to the PWM comparator. The input signal range is nominally 0V to 1.0V and has
an internal offset of 100mV.
4
RTCT
The oscillator timing control pin. The operational frequency and maximum duty cycle are set by
connecting a resistor, RT, between VREF and this pin and a timing capacitor, CT, from this pin to GND.
The oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0MHz. The
charge time, tC, the discharge time, tD, the switching frequency, f, and the maximum duty cycle, Dmax,
can be calculated from Equations 1, 2, 3 and 4:
The error amplifier output and the PWM comparator input. The control loop frequency compensation
network is connected between the COMP and FB pins.
(EQ. 1)
t C 0.583 RT CT
0.0083 RT – 4.3
(EQ. 2) t D – RT CT ln ----------------------------------------------
0.0083 RT – 2.4
(EQ. 3)
f = 1 tC + tD
(EQ. 4)
D = tC f
Figure 7 on page 10 can be used as a guideline in selecting the capacitor and resistor values required for
a given frequency.
5
GND
The power and small signal reference ground for all functions.
6
OUT
The drive output to the power switching device. It is a high current output capable of driving the gate of a
power MOSFET with peak currents of 1.0A.
7
VDD
The power connection for the devices. The total supply current depends on the load applied to OUT. Total
IDD current is the sum of the operating current and the average output current. Knowing the operating
frequency, f, and the MOSFET gate charge, Qg, the average output current can be calculated in
Equation 5:
(EQ. 5)
I OUT = Qg f
To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND
pins as possible.
8
FN9124 Rev.14.00
Jul.22.19
VREF
The 5V reference voltage output. +1.0/-1.5% tolerance over line, load, and operating temperature.
Bypass to GND with a 0.1µF to 3.3µF capacitor to filter this output as needed.
Page 6 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
2.
2. Specifications
Specifications
2.1
Absolute Maximum Ratings
Minimum
Maximum
Unit
Supply Voltage, VDD
Parameter
GND - 0.3
+20.0
V
OUT
GND - 0.3
VDD + 0.3
V
Signal Pins
GND - 0.3
6.0
V
1
A
Peak GATE Current
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely
impact product reliability and result in failures not covered by warranty.
2.2
Thermal Information
θJA (°C/W)
θJC (°C/W)
DFN Package (Notes 5, 7)
Thermal Resistance (Typical)
55
6
SOIC Package (Notes 4, 6)
100
60
MSOP Package (Notes 4, 6)
165
62
Notes:
4. θJA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. For θJC, the “case temp” location is taken at the package top center.
7. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features.
See TB379.
Parameter
Minimum
Maximum
Unit
Maximum Junction Temperature
-55
+150
°C
Maximum Storage Temperature Range
-65
+150
°C
Pb-Free Reflow Profile
2.3
see TB493
Recommended Operation Conditions
Parameter
Minimum
Maximum
Unit
Supply Voltage Range (Typical, Note 8)
ISL6840, ISL6841
7.5
14
V
ISL6843
9
16
V
ISL6842, ISL6844
15
18
V
-40
+105
°C
Temperature Range
ISL684xIx
Note:
8. All voltages are with respect to GND
FN9124 Rev.14.00
Jul.22.19
Page 7 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
2.4
2. Specifications
Electrical Specifications
Recommended operating conditions unless otherwise noted. See Functional Block Diagram and Typical Applications schematics. VDD = 15V
(Note 12), Rt = 10kΩ, Ct = 3.3nF, TA = -40°C to +105°C, Typical values are at TA = +25°C. Boldface limits apply across the operating
temperature range, -40°C to +105°C.
Parameter
Test Conditions
Min
(Note 9)
Typ
Max
(Note 9)
Unit
6.5
7.0
7.5
V
Undervoltage Lockout
START Threshold (ISL6840, ISL6841)
START Threshold (ISL6843)
7.8
8.4
9.0
V
START Threshold (ISL6842, ISL6844)
13.3
14.3
15.3
V
STOP Threshold (ISL6840, ISL6841)
6.1
6.6
6.9
V
STOP Threshold (ISL6843)
6.7
7.2
7.7
V
STOP Threshold (ISL6842, ISL6844)
8.0
8.8
9.6
V
Hysteresis (ISL6840, ISL6841)
0.4
V
Hysteresis (ISL6843)
0.8
V
Hysteresis (ISL6842, ISL6844)
5.4
V
Start-Up Current, IDD
VDD < START threshold
60
100
µA
Operating Current, IDD
(Note 10)
3.3
4.0
mA
Operating Supply Current, ID
Includes 1nF GATE loading
4.1
5.5
mA
5.000
5.050
Reference Voltage
Overall Accuracy
Over line (VDD = 12V to 18V), load, temperature
Long Term Stability
TA = +125°C, 1000 hours (Note 11)
4.925
5
V
mV
Fault Voltage
4.40
4.65
4.85
V
VREF Good Voltage
4.60
4.80
VREF - 0.05
V
Hysteresis
50
165
250
mV
Current Limit, Sourcing
-20
mA
5
mA
Current Limit, Sinking
Current Sense
Input Bias Current
VCS = 1V
1.0
µA
CS Offset Voltage
VCS = 0V (Note 11)
95
100
105
mV
COMP to PWM Comparator Offset Voltage
VCS = 0V (Note 11)
0.80
1.15
1.30
V
0.91
0.97
1.03
V
2.5
3.0
3.5
V/V
25
40
ns
Input Signal, Maximum
Gain, ACS = VCOMP/VCS
0 < VCS < 910mV, VFB = 0V (Note 11)
CS to OUT Delay
(Note 11)
-1.0
Error Amplifier
Open-Loop Voltage Gain
(Note 11)
60
90
dB
Reference Voltage
VFB = VCOMP
2.475
2.514
2.55
V
FB Input Bias Current
VFB = 0V
-1.0
-0.2
1.0
µA
COMP Sink Current
VCOMP = 1.5V, VFB = 2.7V
1.0
mA
COMP Source Current
VCOMP = 1.5V, VFB = 2.3V
-0.4
mA
COMP VOH
VFB = 2.3V
4.80
VREF
V
COMP VOL
VFB = 2.7V
0.4
1.0
V
PSRR
Frequency = 120Hz, VDD = 12V to 18V (Note 11)
60
Frequency Accuracy
Initial, TJ = +25°C
49
Frequency Variation with VDD
T = +25°C (f18V - f12V)/f12V
Temperature Stability
(Note 11)
80
dB
Oscillator
FN9124 Rev.14.00
Jul.22.19
52
55
kHz
0.2
1.0
%
-
5
%
Page 8 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
2. Specifications
Recommended operating conditions unless otherwise noted. See Functional Block Diagram and Typical Applications schematics. VDD = 15V
(Note 12), Rt = 10kΩ, Ct = 3.3nF, TA = -40°C to +105°C, Typical values are at TA = +25°C. Boldface limits apply across the operating
temperature range, -40°C to +105°C. (Continued)
Parameter
Test Conditions
Min
(Note 9)
Typ
Max
(Note 9)
Unit
Amplitude, Peak-to-Peak
1.9
V
RTCT Discharge Voltage
0.7
V
Discharge Current
RTCT = 2.0V
7.2
8.4
9.5
mA
Output
Gate VOH
VDD to OUT, IOUT = -200mA
1.0
2.0
V
Gate VOL
OUT to GND, IOUT = 200mA
1.0
2.0
V
Peak Output Current
COUT = 1nF (Note 11)
1.0
Rise Time
COUT = 1nF (Note 11)
20
40
ns
Fall Time
COUT = 1nF (Note 11)
20
40
ns
A
PWM
Maximum Duty Cycle
Minimum Duty Cycle
ISL6840, ISL6842, ISL6843
94
96
%
ISL6841, ISL6844
47
48
%
ISL6840, ISL6842, ISL6843
0
%
ISL6841, ISL6844
0
%
Notes:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
10. This is the VDD current consumed when the device is active but not switching. Does not include gate drive current.
11. Limits established by characterization and are not production tested.
12. Adjust VDD above the start threshold and then lower to 15V.
FN9124 Rev.14.00
Jul.22.19
Page 9 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
3.
3. Typical Performance Curves
Typical Performance Curves
1.001
1.000
1.01
Normalized VREF
Normalized Frequency
1.02
1.00
0.99
0.98
0.97
-40
0.999
0.998
0.997
0.996
-10
20
50
80
0.995
-40 -25
110
-10
5
Temperature (°C)
Figure 4. Frequency vs Temperature
Frequency (kHZ)
Normalized EA Reference
50
65
80
95 110
103
1.000
0.998
0.996
5
20
35
50
65
80
95
Temperature (°C)
Figure 6. EA Reference vs Temperature
FN9124 Rev.14.00
Jul.22.19
35
Figure 5. Reference Voltage vs Temperature
1.002
0.994
-40 -25 -10
20
Temperature (°C)
110
100pF
100
220pF
330pF
470pF
1.0nF
10
1
2.2nF
3.3nF
4.7nF
10
20
30
40
50 60
RT (kΩ)
70
80
90
100
Figure 7. Resistance for CT Capacitor Values Given
Page 10 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
4.
4.1
4. Functional Description
Functional Description
Features
The ISL684x current mode PWMs make an ideal choice for low-cost flyback and forward topology applications.
With its greatly improved performance over industry standard parts, it is the obvious choice for new designs or
existing designs which require updating.
4.2
Oscillator
The ISL684x family of controllers have a sawtooth oscillator with a programmable frequency range to 2MHz,
which can be programmed with a resistor from VREF and a capacitor to GND on the RTCT pin. (See Figure 7 on
page 10 for the resistor and capacitance required for a given frequency.)
4.3
Soft-Start Operation
Soft-start must be implemented externally. Figure 8 shows one method that clamps the voltage on COMP.
VREF
ISL684x
COMP
GND
Figure 8. Soft-Start
4.4
Gate Drive
The ISL684x family is capable of sourcing and sinking 1A peak current. To limit the peak current through the ICs,
an optional external resistor can be placed between the totem-pole output of the IC (OUT pin) and the gate of the
MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic
inductances in the traces of the board and the FET’s input capacitance.
4.5
Slope Compensation
For applications where the maximum duty cycle is less than 50%, slope compensation can be used to improve
noise immunity, particularly at lighter loads. The amount of slope compensation required for noise immunity is
determined empirically, but is generally about 10% of the full scale current feedback signal. For applications
where the duty cycle is greater than 50%, slope compensation is required to prevent instability. The minimum
amount of slope compensation required corresponds to 1/2 the inductor downslope. Adding excessive slope
compensation, however, results in a control loop that behaves more as a voltage mode controller than as a
current mode controller.
Slope compensation may be added to the CS signal shown in Figure 10 on page 12.
CS Signal (V)
Downslope
Current Sense Signal
Time
Figure 9. Current Sense Downslope
FN9124 Rev.14.00
Jul.22.19
Page 11 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
4. Functional Description
RTCT
ISL684x
VREF
CS
Figure 10. Slope Compensation
4.6
Fault Conditions
A fault condition occurs if VREF falls below 4.65V. When a fault is detected, OUT is disabled. When VREF
exceeds 4.80V, the fault condition clears, and OUT is enabled.
4.7
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. A
unique section of the ground plane must be designated for high di/dt currents associated with the output stage.
Bypass VDD directly to GND with good high-frequency capacitors.
FN9124 Rev.14.00
Jul.22.19
Page 12 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
5.
5. Revision History
Revision History
Rev.
Date
Description
14
Jul.22.19
Applied new formatting and template.
Added Related Literature section
Updated Ordering Information table by adding tape and reel information, removing retired parts, and updating
notes.
Removed Note 2.
Updated Theta JA for DFN package changed from 77 to 55.
Updated Theta JC for SOIC package changed from N/A to 60.
Added Note 8 and updated references.
Removed ISL6843C information from document.
Removed ISL6845 information from document.
Updated the disclaimer.
13
Feb.18.16
-Updated Ordering Information table on page 5
12
Sep.29.15
- Updated Ordering Information Table on page 5.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD L8.2X3 to latest revision changes are as follow:
-Revision 1 to Revision 2 Changes:
Tiebar Note 5 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or
ends).
FN9124 Rev.14.00
Jul.22.19
Page 13 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
6.
6. Package Outline Drawings
Package Outline Drawings
For the most recent package outline drawing, see M8.15.
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL “A”
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
Notes:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
FN9124 Rev.14.00
Jul.22.19
Page 14 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
6. Package Outline Drawings
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
For the most recent package outline drawing, see M8.118.
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
FN9124 Rev.14.00
Jul.22.19
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
Page 15 of 17
ISL6840, ISL6841, ISL6842, ISL6843, ISL6844
6. Package Outline Drawings
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 3/15
2.00
A
For the most recent package outline drawing, see L8.2x3.
2X 1.50
PIN 1
INDEX AREA
6
PIN #1
INDEX AREA
6X 0.50
1
1.80 +0.10/-0.15
3.00
B
(4X)
0.15
8
8X 0.40 ±0.10
TOP VIEW
1.65 +0.10/-0.15
8X 0.25 +0.07/-0.05 4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 ±0.10
0.10 C
(1.65)
(1.50)
(8X 0.60)
C
BASE PLANE
SEATING PLANE
0.08 C
0.05 MAX
SIDE VIEW
(2.80)(1.80)
0.20 REF
C
(6X 0.50)
0.05 MAX
(8X 0.25)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
FN9124 Rev.14.00
Jul.22.19
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7.
Compies to JEDEC MO-229 VCED-2.
Page 16 of 17
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