DATASHEET
ISL78113A
FN8638
Rev 0.00
May 1, 2014
Low Input Voltage and High Efficiency Synchronous Boost Converter with 1.3A
Switch
The ISL78113A provides a tiny and convenient boost power
supply solution to generate a regulated output up to 500mA
from any sub-5V secondary rail found in an automotive
electrical system, including battery powered applications
(NiCd, NiMH, or one-cell Li-Ion/Li-Polymer). It offers an
adjustable output (3.0V to 5.2V) supporting USB-OTG or HDMI
applications. The device is able to supply 500mA from a 3V
input and 5V output, and has a typical 1.3A peak current limit.
Features
• Output disconnect during shutdown preventing output
precharging and uncontrolled short-circuit current
• Input voltage range: 0.8V to 4.7V
• Output current: Up to 500mA (VBAT = 3V, VOUT = 5V)
• Logic control shutdown (IQ < 1µA)
The ISL78113A is a fully integrated, internally compensated,
synchronous converter optimized to maximize efficiency and
reduce the overall solution size and bill of materials. Its high
2MHz switching frequency allows the use of tiny, low-profile
inductors and chip capacitors. It also eliminates potential
interference within the AM radio band and the external EMI
filtering needed for converters switching at lower rates. To
minimize power consumption while off, the device features an
ultra-low current shutdown mode dropping quiescent current
to 50nA typical.
• 2MHz switching frequency
ISL78113A is supplied in an 8 Ld DFN package. The device is
rated to operate over the temperature range of -40°C to
+105°C.
• Automotive camera systems
• Up to 95% efficiency at typical operating conditions
• Fault protection: OVP, OCP, OTP, UVLO
• 2mmx2mm 8 Ld DFN package
• Qualified for automotive operations
Applications
• Automotive head units and infotainment systems: especially
those including portable HDMI and USB-OTG connectivity
100
6.8 µH
VBAT = 3.6V
90
80
VBAT =
0.8V TO 4.7V
SW
7
10µF
2
VOUT =
5.0V/500mA
VOUT
VBAT
10µF
422
5
4
EN
FB
80.6
1
GND
ISL78113AARAZ
FIGURE 1. TYPICAL APPLICATION
FN8638 Rev 0.00
May 1, 2014
70
EFFICIENCY (%)
8
VBAT = 4.2V
VBAT = 3.4V
VBAT = 3V
60
50
VBAT = 2.3V
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
LOAD CURRENT ILOAD (A)
FIGURE 2. EFFICIENCY vs LOAD CURRENT
Page 1 of 12
0.6
ISL78113A
Block Diagram
C1
VOUT
VBAT
7
UVLO
VINT
C2
2
VOLTAGE
SELECTOR
START-UP
N-WELL
SWITCH
GATE
DRIVER
VOUT
SW
L1
8
OVP
AND
ANTI-CROSS
CONDUCTION
ZCD
EN
SW
VOUT
5
OFF ON
CURRENT
SENSE
CONTROL LOGIC
R1
AND
DIGITAL
SOFT-START
CURRENT
LIMIT
SLOPE COMP
FB
4
FAULT
MONITORING
gm
VOLTAGE
CLAMP
2MHz
OSCILLATOR
VINT
REFERENCE
GENERATOR
THERMAL
SHUTDOWN
1
FN8638 Rev 0.00
May 1, 2014
R2
6
Page 2 of 12
ISL78113A
Pin Configuration
ISL78113A
ADJUSTABLE OUTPUT
(8 LD DFN)
TOP VIEW
PGND
1
8
SW
VOUT
2
7
VBAT
NC
3
6
AGND
FB
4
5
EN
Pin Descriptions
PIN
NUMBERS SYMBOL
PIN DESCRIPTION
1
PGND
Power ground.
2
VOUT
Device output.
3
NC
No connection.
4
FB
Feedback pin of the converter. Connect voltage divider resistors between VOUT, FB and GND for desired output.
5
EN
The EN pin is an active-HIGH logic input for enabling the device. When asserted HIGH, the boost function begins. When driven
LOW, the device is completely disabled, and current is blocked from flowing from the SW pin to the output and vice versa. This
pin may be tied either HIGH to enable the device or LOW to disable.
6
AGND
7
VBAT
Device input supply from a battery. Connect a 10µF ceramic capacitor from VBAT to power ground.
8
SW
The SW pin is the switching node of the power converter. Connect one terminal of the inductor to the SW pin and the other to
power input.
EPAD
The exposed pad must be connected to PGND pin for proper electrical performance. Place as many vias as possible under the
pad connecting to the system GND plane for optimal thermal performance.
Analog ground.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL78113AARAZ-T
PART MARKING
AAR
VOUT (V)
TEMP RANGE
(°C)
Adjustable
-40 to +105
PACKAGE
(Pb-free)
8 Ld DFN
PKG.
DWG. #
L8.2x2D
NOTES:
1. Use “-T7A” suffix for 250 pieces tape and reel. Please refer to Tech Brief TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78113A. For more information on MSL please see Tech Brief TB363.
FN8638 Rev 0.00
May 1, 2014
Page 3 of 12
ISL78113A
Absolute Maximum Ratings
Thermal Information
VBAT, EN, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
SW Voltage
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V
Pulse +150°C.
Switching stops. Device automatically restarts when temperature decreases to
+125°C.
Output Overvoltage
Protection
Switching stops until EN pin is toggled or power is cycled.
VOUT > 5.9V
Fault Monitoring
Fault monitoring starts 2ms after start-up. Table 1 shows the
response to different detected faults.
Printed Circuit Board Layout
Recommendations
The ISL78113A is a high frequency switching boost converter.
Accordingly, the converter has fast voltage change and high
switching current that may cause EMI and stability issues if the
layout is not done properly. Therefore, careful layout is critical to
minimize the trace inductance and reduce the area of the power
loop.
Power components such as input capacitor, inductor, and the
output capacitors should be placed as close to the device as
possible. Board traces that carry high switching current should be
routed wide and short. A solid power ground plane is important
for EMI suppression.
The switching node (SW pin) of the converter and the traces
connected to this pin are very noisy. Noise sensitive traces such
as the FB trace should be kept away from the SW node. The
voltage divider should be placed close to the FB pin to prevent
noise pickup. Figure 3 shows the recommended PCB layout.
Output Voltage Setting Resistor Selection
In the 8 Ld DFN package, the heat generated in the device is
mainly dissipated through the thermal pad. Maximizing the
copper area connected to the thermal pad is preferable. It is
recommended to add at least 4 vias within the pad to the GND
plane for the best thermal dissipation.
R 1
V OUT = V FB 1 + -------
R 2
FN8638 Rev 0.00
May 1, 2014
FIGURE 3. RECOMMENDED PCB LAYOUT
For ISL78113A, resistors R1 and R2, shown in the “Block
Diagram” on page 2, set the desired output voltage values. The
output voltage can be calculated using Equation 1:
(EQ. 1)
where VFB is the internal FB reference voltage (0.8V typical). The
current flowing through the divider resistors is calculated as
VOUT /(R1 + R2). The resistance is chosen based on the minimum
expected load for VOUT and the minimum PWM on time (PWM
Low; 42ns typical). This will provide a small constant current that
limits the VOUT and voltage in light load conditions. R1 and R2
should be placed close to the FB pin of the device to prevent
noise pickup.
Page 6 of 12
ISL78113A
Inductor Selection
An inductor with core material suitable for high frequency
applications (e.g., ferrite) is desirable to minimize core loss and
improve efficiency. The inductor should have a low DCR to
reduce copper loss. Moreover, the inductor saturation current
should be higher than the maximum peak current of the device;
i.e., 1.6A.
The device is designed to operate with an inductor value of 2.2µH
to 6.8µH to provide stable operation across the range of load,
input and output voltages. Table 2 shows recommended
inductors.
TABLE 2. INDUCTOR VENDOR INFORMATION
MANUFACTURER
SERIES
WEBSITE
Würth Elektronik
WE-TPC, Type S
www.we-online.com
Capacitor Selection
minimum load required due to these forced PWM pulses is
elaborated in the following.
Figure 4 shows the inductor waveform in the forced PWM
operation at no load. tMIN(ON)_LFET is the time the low-side
MOSFET is forced ON.
During tMIN(ON) time, inductor current is charged with slew rate of
VIN/L. The peak inductor current at the end of tMIN(ON) can be
calculated in Equation 2.
V IN t MIN ON
IL peak = ---------------------------------------L
(EQ. 2)
After tMIN(ON) time, low-side MOSFET is turned off, inductor
current is free-wheeling through the high-side MOSFET from VIN
to VOUT until the inductor current ramps down to 0 and the
high-side MOSFET is turned off. The duration of this free-wheeling
period (tFW) can be calculated in Equation 3.
IL peak L
t FW = -------------------------------V OUT – V IN
INPUT CAPACITOR
A minimum of a 10µF ceramic capacitor is recommended to
provide stable operation under typical operating conditions. For
input voltage less than 1.0V application, an additional 2.2µF
ceramic capacitor is recommended for better noise filtering and
EMI suppression. The input capacitor should be placed close to
the input pin, GND pin, and the non-switching terminal of the
inductor.
OUTPUT CAPACITOR
For the output capacitor, a ceramic capacitor with small ESR is
recommended to minimize output voltage ripple. A typical 10µF
should be used to provide stable operation at different typical
operating conditions. The output capacitor should be placed
close to the output pin and GND pin of the device. Table 3 shows
the recommended capacitors.
TABLE 3. CAPACITOR VENDOR INFORMATION
MANUFACTURER
SERIES
WEBSITE
AVX
X7R
www.avx.com
Murata
X7R
www.murata.com
Taiyo Yuden
X7R
www.t-yuden.com
TDK
X7R
www.tdk.com
(EQ. 3)
During this free-wheeling period, the charge to the output is
shown as Q in Figure 4 on page 8, which can be calculated as
shown by Equation 4.
(EQ. 4)
Q = 0.5 IL peak t FW
The ISL78113A outputs charge of Q to the output every switching
cycle, therefore the average current to due to the tMIN(ON) pulses
can be calculated as shown by Equation 5.
(EQ. 5)
I OUT AVG = Q F SW
where FSW is the switching frequency.
Summarizing from Equations 2 through 5, the average current
charged to the output due to the tMIN(ON) pulses can be
calculated by Equation 6.
2
0.5 F SW V IN t MIN ON
I OUT AVG = --------------------------------------------------------------------------------L V OUT – V IN
(EQ. 6)
Forced PWM Operation
The part has forced PWM operation. During a no-load condition
the low-side FET is forced ON for a short pulse with minimum
ON-time (42ns typical) in every cycle and does not allow for pulse
skipping. The part is also implemented with diode emulation
mode to turn off the upper side MOSFET when inductor current
drops to 0 and prevents any negative inductor current. Therefore
in no load to light load (less than several mA) conditions, the
output voltage is pushed higher than regulation point, which may
be out of the user’s output voltage specifications.
This issue can be resolved by adding a small load (several mA) to
keep the output in regulation. The procedure to calculate the
FN8638 Rev 0.00
May 1, 2014
Page 7 of 12
ISL78113A
ILPEAK = VIN/L* tMIN(ON)
SR = (VOUT - VIN)
SR = VIN /L
Q = 0.5 * ILPEAK * tFW
Q
IL
IOUT(AVG) = Q*FSW
IOUT(AVG) = 0.5 * (VIN/L*
tMIN(ON)
tMIN(ON))2*L/(VOUT
Q
- VIN) * FSW
tFW
tFW = ILPEAK * L/(VOUT - VIN)
1/FSW
FIGURE 4. AVERAGE OUTPUT CURRENT DUE TO FORCED PWM PULSES AT NO LOAD CONDITION
Minimum Load Required in Forced PWM
Mode
An example of the typical conditions are listed as follows:
In a no load condition, in order to maintain the output voltage in
regulation, a small load has to be added in the output to absorb
the output current due to forced PWM pulses. Equation 6 can be
used to calculate the minimum required load in worst cases.
• VOUT TYP = 5V
The worst cases refer to FSW, VIN, tMIN(ON), L, VOUT in Equation 6.
• Use the maximum VIN for the worst case.
• Specify the allowed maximum Vout voltage VIN(MAX) and use it
in the worst case calculation, basically the target is to have the
minimum load keeping the VOUT below the maximum
acceptable voltage.
• Use the maximum switching frequency of 2.23MHz specified
in the “Electrical Specifications” table on page 4. Maximum
frequency is the worst case since it delivered most pulses with
fixed charges to the output.
• Use the minimum inductor value considering inductance
variations (normally -20% of nominal value). For the inductor
selection, note the higher the inductance, the less the required
minimum load.
• VIN TYP = 3V
• FSW TYP = 2MHz
• LNOMINAL = 6.8µH
To calculate the minimum required load, the worst conditions we
can use are,
• VIN(MAX) = 3.6V (specified in customer system)
• VOUT(MAX) = 5.25V (specified in customer system)
• FSW = 2.23MHz
• LMIN = (-20%) LNOMINAL = 5.44µH
Using the above worst case parameters in Equation 6, the
calculated output current (IOUT(AVG)) is 3.87mA, which is the
minimum required load to be added in the output to absorb the
output current due to forced PWM pulses. Extra margin can be
added depending on the system worst case condition.
• Use the maximum tMIN(ON) time of 49ns specified in the
“Electrical Specifications” table on page 4. Maximum tMIN(ON)
time is the worst case since it cause higher inductor peak
current and higher charge to the output.
FN8638 Rev 0.00
May 1, 2014
Page 8 of 12
ISL78113A
Typical Characteristics
VIN = 3.4V, VOUT = 5V, L = 6.8µH, COUT = 10µF, R1 = 422Ω, R2 = 80.6Ω; unless otherwise noted.
Typical values are at TA = +25°C.
1.2
1.0
0.8
VOUT = 5.0V
1.0
0.4
0.8
VOUT = 4.0V
VOUT (%)
IOUT (A)
0.6
0.6
0.4
0.2
ILOAD = 1mA
0
-0.2
-0.4
ILOAD = 150mA
-0.6
0.2
-0.8
0
0.8
1.3
1.8
2.3
2.8
3.3
VBAT (V)
3.8
4.3
4.8
-1.0
0
1
2
3
4
VBAT (V)
FIGURE 5. MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE
FIGURE 6. LINE REGULATION, VOUT = 5V
ILOAD = 20mA
ILOAD = 50mA
VOUT WITH 5.0V OFFSET (10mV/DIV)
VOUT WITH 5.0V OFFSET (10mV/DIV)
SW (5V/DIV)
SW (5V/DIV)
INDUCTOR CURRENT (100mA/DIV)
INDUCTOR CURRENT (100mA/DIV)
1µs/DIV
1µs/DIV
FIGURE 7. OUTPUT RIPPLE VOLTAGE (ILOAD = 20mA)
FIGURE 8. OUTPUT RIPPLE VOLTAGE (ILOAD = 50mA)
ILOAD = 150mA
VOUT WITH 5.0V OFFSET (20mV/DIV)
ILOAD = 250mA
VOUT WITH 5.0V OFFSET (50mV/DIV)
SW (5V/DIV)
SW (5V/DIV)
INDUCTOR CURRENT (200mA/DIV)
INDUCTOR CURRENT (200mA/DIV)
1µs/DIV
FIGURE 9. OUTPUT RIPPLE VOLTAGE (ILOAD = 150mA)
FN8638 Rev 0.00
May 1, 2014
1µs/DIV
FIGURE 10. OUTPUT RIPPLE VOLTAGE (ILOAD = 250mA)
Page 9 of 12
5
ISL78113A
Typical Characteristics
VIN = 3.4V, VOUT = 5V, L = 6.8µH, COUT = 10µF, R1 = 422Ω, R2 = 80.6Ω; unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
EN (2V/DIV)
EN (2V/DIV)
VOUT (2V/DIV)
VOUT (2V/DIV)
INDUCTOR CURRENT (500mA/DIV)
INDUCTOR CURRENT (1A/DIV)
SW (5V/DIV)
SW (5V/DIV)
200µs/DIV
100µs/DIV
FIGURE 11. START-UP AFTER ENABLE (ILOAD = 250mA)
FIGURE 12. START-UP AFTER ENABLE (ILOAD = 50mA)
VOUT With 5V OFFSET
VOUT With 5V OFFSET
VOUT (50mV/DIV)
VOUT (100mV/DIV)
ILOAD (100mA/DIV)
ILOAD (200mA/DIV)
SW (5V/DIV)
1ms/DIV
1ms/DIV
FIGURE 13. LOAD TRANSIENT RESPONSE (20mA TO 150mA)
FIGURE 14. LOAD TRANSIENT RESPONSE (20mA TO 250mA)
0.5
VOUT WITH 5.0V OFFSET
0
VBAT = 4.2V
-0.5
VOUT (%)
VOUT (200mV/DIV)
VBAT = 3V
-1.0
VBAT = 3.6V
-1.5
-2.0
VBAT = 3.4V
-2.5
-3.0
ILOAD (200mA/DIV)
1ms/DIV
FIGURE 15. LOAD TRANSIENT RESPONSE (100mA TO 500mA)
FN8638 Rev 0.00
May 1, 2014
0
0.2
0.4
ILOAD (A)
0.6
FIGURE 16. LOAD REGULATION
Page 10 of 12
0.8
ISL78113A
Typical Characteristics
VIN = 3.4V, VOUT = 5V, L = 6.8µH, COUT = 10µF, R1 = 422Ω, R2 = 80.6Ω; unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
100
VBAT = 3.6V
90
80
VBAT = 4.2V
EFFICIENCY (%)
70
60
VBAT = 3.4V
VBAT = 2.3V
VBAT = 3V
50
40
30
20
R1 = 121k
10
0
0
R2 = 22.1k
0.1
0.2
0.3
0.4
LOAD CURRENT ILOAD (A)
0.5
0.6
FIGURE 17. EFFICIENCY vs LOAD CURRENT
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
May 1, 2014
FN8638.0
CHANGE
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2014. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8638 Rev 0.00
May 1, 2014
Page 11 of 12
ISL78113A
Package Outline Drawing
L8.2x2D
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH EXPOSED PAD
Rev 0, 3/11
2.00
6
PIN 1
INDEX AREA
6
PIN #1
INDEX AREA
A
B
8
1
2.00
6x 0.50
(4X)
1.55±0.10
0.15
0.10M C A B 0.22
4
TOP VIEW
( 8x0.30 )
0.90±0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0.10 C
0.90±0.10
BASE PLANE
0 . 00 MIN.
0 . 05 MAX.
SEATING PLANE
0.08 C
SIDE VIEW
0 . 2 REF
C
DETAIL "X"
( 8x0.20 )
PACKAGE
OUTLINE
( 8x0.30 )
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
( 6x0.50 )
1.55
2.00
between 0.15mm and 0.30mm from the terminal tip.
( 8x0.22 )
0.90
2.00
TYPICAL RECOMMENDED LAND PATTERN
FN8638 Rev 0.00
May 1, 2014
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Page 12 of 12
