ISL78234AARZ-T

DATASHEET ISL78233, ISL78234 FN8359 Rev.10.00 Jan 12, 2021 3A and 4A Compact Synchronous Buck Regulators The ISL78233 and ISL78234 are highly efficient, monolithic, synchronous step-down DC/DC converters that can deliver 3A (ISL78233), or 4A (ISL78234) of continuous output current from a 2.7V to 5.5V input supply. The devices use current mode control architecture to deliver a very low duty cycle operation at high frequency with fast transient response and excellent loop stability. The ISL78233 and ISL78234 integrate a very low ON-resistance P-channel (35mΩ) high-side FET and N-channel (11mΩ) low-side FET to maximize efficiency and minimize external component count. The 100% duty-cycle operation allows less than 200mV dropout voltage at 4A output current. The operation frequency of the Pulse-Width Modulator (PWM) is adjustable from 500kHz to 4MHz. The default switching frequency of 2MHz is set by connecting the FS pin high. The ISL78233 and ISL78234 can be configured for discontinuous or forced continuous operation at light load. Forced continuous operation reduces noise and RF interference, while discontinuous mode provides higher efficiency by reducing switching losses at light loads. Features • 2.7V to 5.5V input voltage range • Very low ON-resistance FETs - P-channel 35mΩ and N-channel 11mΩ typical values • High efficiency synchronous buck regulator with up to 95% efficiency • -1.2%/1% reference accuracy over temperature/load/line • Complete BOM with as few as 3 external parts • Internal soft-start - 1ms or adjustable • Soft-stop output discharge during disable • Adjustable frequency from 500kHz to 4MHz - default at 2MHz • External synchronization up to 4MHz • Over-temperature, overcurrent, overvoltage, and negative overcurrent protection Fault protection is provided by internal Hiccup mode current limiting during short-circuit and overcurrent conditions. Other protection, such as overvoltage and over-temperature are also integrated into the device. A power-good output voltage monitor indicates when the output is in regulation. The ISL78233 and ISL78234 offer a 1ms Power-Good (PG) timer at power-up. When in shutdown, the ISL78233 and ISL78234 discharge the output capacitor through an internal soft-stop switch. Other features include internal fixed or adjustable soft-start and internal/external compensation. • Shared common device pinout allows simplified output power upgrades over time • Tiny 3mmx3mm TQFN package • AEC-Q100 qualified Applications • DC/DC POL modules • μC/µP, FPGA, and DSP power • Video processor/SOC power The ISL78233 and ISL78234 are available in a 3mmx3mm 16 Ld Thin Quad Flat (TQFN) Pb-free package and in a 5mmx5mm 16 Ld Wettable Flank Quad Flat No-Lead (WFQFN) package with an exposed pad for improved thermal performance. The ISL78233 and ISL78234 are rated to operate across the temperature range of -40°C to +125°C. • Li-ion battery powered devices • Automotive infotainment power Related Literature For a full list of related documents, visit our website: • ISL78233, ISL78234 device pages 100 3.3VOUT EFFICIENCY (%) 90 80 1.2VOUT 1.5VOUT 1.8VOUT 70 2.5VOUT 60 50 40 0.0 0.5 1.0 1.5 2.0 2.5 OUTPUT LOAD (A) 3.0 3.5 4.0 FIGURE 1. EFFICIENCY vs LOAD (2MHz 5VIN PFM, TA = +25°C) FN8359 Rev.10.00 Jan 12, 2021 Page 1 of 20 ISL78233, ISL78234 Typical Application Diagram 13 14 PHASE PG SGND R3 100k: FB *C3 IS OPTIONAL. IT IS RECOMMENDED TO PUT A PLACEHOLDER FOR IT AND CHECK LOOP ANALYSIS BEFORE USE. EN 5 C3* 22pF PAD SYNC EN 4 PGND R2 200k : 17 3 PG VOUT GND VDD COMP 2 8 R1 100k: +1.8V/4A 1.0μH C2 2x22μF PGND ISL78233, ISL78234 SS C1 2x22μF VIN 7 1 FS GND +2.7V …+5.5V 6 VIN PHASE 15 VIN PHASE 16 L1 FIGURE 2. TYPICAL APPLICATION DIAGRAM TABLE 1. COMPONENT SELECTION TABLE VOUT 1.2V 1.5V 1.8V 2.5V 3.3V 3.6V C1 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF C2 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF 2 x 22µF C3 22pF 22pF 22pF 22pF 22pF 22pF L1 0.33-0.68µH 0.33-0.68µH 0.33-0.68µH 0.47-0.78µH 0.47-0.78µH 0.47-0.78µH R2 100kΩ 150kΩ 200kΩ 316kΩ 450kΩ 500kΩ R3 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ 100kΩ FN8359 Rev.10.00 Jan 12, 2021 Page 2 of 20 ISL78233, ISL78234 COMP SS SHUTDOWN FS SYNC 55pF Soft SOFTSTART SHUTDOWN VDD 100kΩ + BANDGAP VREF + EN + COMP - EAMP - VIN OSCILLATOR PWM/PFM LOGIC CONTROLLER PROTECTION HS DRIVER 3pF + P PHASE LS DRIVER N PGND FB 6kΩ SLOPE Slope COMP 0.8V + CSA - + OV + OCP - 0.85*VREF PG + UV ISET THRESHOLD + SKIP - 1ms DELAY NEG CURRENT SENSING SGND ZERO-CROSS SENSING 0.5V SCP + 100Ω SHUTDOWN FIGURE 3. FUNCTIONAL BLOCK DIAGRAM Ordering Information PART NUMBER (Note 4) PART MARKING OUTPUT VOLTAGE (V) TEMP. RANGE TAPE AND REEL (°C) (UNITS) (Note 1) PACKAGE (RoHS Compliant) PKG. DWG. # ISL78233ARZ (Note 2) 8233 Adjustable -40 to +125 - 16 Ld 3x3 TQFN L16.3x3D ISL78233ARZ-T (Note 2) 8233 Adjustable -40 to +125 6k 16 Ld 3x3 TQFN L16.3x3D ISL78233ARZ-T7A (Note 2) 8233 Adjustable -40 to +125 250 16 Ld 3x3 TQFN L16.3x3D ISL78233AARZ (Note 3) 78233A ARZ Adjustable -40 to +125 - 16 Ld 5x5mm WFQFN L16.5x5D ISL78233AARZ-T (Note 3) 78233A ARZ Adjustable -40 to +125 6k 16 Ld 5x5mm WFQFN L16.5x5D ISL78233AARZ-T7A (Note 3) 78233A ARZ Adjustable -40 to +125 250 16 Ld 5x5mm WFQFN L16.5x5D ISL78233BARZ (Note 2) 8233B Adjustable -40 to +125 - 16 Ld 3x3 TQFN L16.3x3D ISL78233BARZ-T (Note 2) 8233B Adjustable -40 to +125 6k 16 Ld 3x3 TQFN L16.3x3D ISL78233BARZ-T7A (Note 2) 8233B Adjustable -40 to +125 250 16 Ld 3x3 TQFN L16.3x3D ISL78234ARZ (Note 2) 8234 Adjustable -40 to +125 - 16 Ld 3x3 TQFN L16.3x3D FN8359 Rev.10.00 Jan 12, 2021 Page 3 of 20 ISL78233, ISL78234 Ordering Information PART NUMBER (Note 4) PART MARKING OUTPUT VOLTAGE (V) TEMP. RANGE TAPE AND REEL (°C) (UNITS) (Note 1) PACKAGE (RoHS Compliant) PKG. DWG. # ISL78234ARZ-T (Note 2) 8234 Adjustable -40 to +125 6k 16 Ld 3x3 TQFN L16.3x3D ISL78234ARZ-T7A (Note 2) 8234 Adjustable -40 to +125 250 16 Ld 3x3 TQFN L16.3x3D ISL78234AARZ (Note 3) 78234A ARZ Adjustable -40 to +125 - 16 Ld 5x5mm WFQFN L16.5x5D ISL78234AARZ-T (Note 3) 78234A ARZ Adjustable -40 to +125 6k 16 Ld 5x5mm WFQFN L16.5x5D ISL78234AARZ-T7A (Note 3) 78234A ARZ Adjustable -40 to +125 250 16 Ld 5x5mm WFQFN L16.5x5D ISL78233EVAL1Z 3x3mm TQFN Evaluation Board ISL78234EVAL1Z 3x3mm TQFN Evaluation Board ISL78233EVAL2Z 5x5mm WFQFN Evaluation Board ISL78234EVAL2Z 5x5mm WFQFN Evaluation Board NOTES: 1. See TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), see the ISL78233, ISL78234 device information pages. For more information about MSL, see TB363. TABLE 2. KEY DIFFERENCE BETWEEN FAMILY OF PARTS PART NUMBER IOUT MAX (A) ISL78233 3 ISL78234 4 ISL78235 5 Pin Configuration FN8359 Rev.10.00 Jan 12, 2021 PHASE 15 PHASE 16 PHASE VIN 16 LD TQFN TOP VIEW 14 13 VDD 2 11 PGND PG 3 10 SGND SYNC 4 9 FB 5 6 7 8 COMP PGND SS 12 FS 1 EN VIN Page 4 of 20 ISL78233, ISL78234 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1, 16 VIN Input supply voltage. Place a minimum of two 22µF ceramic capacitors from VIN to PGND as close as possible to the IC for decoupling. 2 VDD Input supply voltage for logic. Connect to the VIN pin. 3 PG Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected between VIN and PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation. 4 SYNC Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM mode. Connect to an external function generator for synchronization with the positive edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case of SYNC pin float. 5 EN Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output capacitor when driven to low. 6 FS This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 2MHz if FS is connected to VIN. 7 SS SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC. 8 COMP 9 FB The feedback network of the regulator, FB, is the negative input to the transconductance error amplifier. COMP is the output of the amplifier if COMP is not tied to VDD. Otherwise, COMP is disconnected through a MOSFET for internal compensation. Must connect COMP to VDD in internal compensation mode. The output voltage is set by an external resistor divider connected to FB. With a properly selected divider, the output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to meet a typical application. Additional external networks across COMP and SGND might be required to improve the loop compensation of the amplifier operation. In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the regulator output voltage. 10 SGND Signal ground 11, 12 PGND Power ground 13, 14, 15 PHASE Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω resistor when the device is disabled. See “Functional Block Diagram” on page 3 for more detail. Exposed Pad - The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many vias as possible under the pad connecting to the SGND plane for optimal thermal performance. FN8359 Rev.10.00 Jan 12, 2021 Page 5 of 20 ISL78233, ISL78234 Absolute Maximum Ratings (Reference to GND) Thermal Information VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms) EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V PHASE DC: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V Pulsed (Note 8): . . . . . . . . . . . . . . . . . . . . . . . . -2V (< 0.6µJ) to 7V (20ms) COMP, SS (Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V ESD Rating Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . . . 5kV Machine Model (Tested per AEC-Q100-003). . . . . . . . . . . . . . . . . . 300V Charge Device Model (Tested per AEC-Q100-011). . . . . . . . . . . . . . . 2kV Latch-Up (Tested per AEC-Q100-004, Class II, Level A) . . . . . . . . . . 100mA Thermal Resistance JA (°C/W) JC (°C/W) 16 Ld TQFN Package (Notes 5, 6) . . . . . . . 43 3.5 16 Ld WFQFN Package (Notes 5, 6) . . . . . 33 3.5 Operating Junction Temperature Range . . . . . . . . . . . . . .-55°C to +125°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range (ISL78233) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A (ISL78234) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 4A Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. 6. JC, case temperature location is at the center of the exposed metal pad on the package underside. 7. COMP is an input and output pin. When the ISL7823x is used with an internal compensation, the COMP pin has a rating similar to VIN. When using the ISL7823x in an external compensation, the ratings are -0.3V to 2.7V. 8. The PHASE pin negative voltage can be less than -2V as long as the energy of the pulse does not exceed 0.6µJ. Electrical Specifications Unless otherwise noted, all parameter limits are established across the recommended operating conditions and the specification limits are measured at the following conditions: TA = -40°C to +125°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNIT 2.5 2.7 V INPUT SUPPLY VIN Undervoltage Lockout Threshold VUVLO Rising, no load Falling, no load Quiescent Supply Current Shutdown Supply Current IVIN ISD 2.2 2.45 V SYNC = GND, no load at the output 45 SYNC = GND, no load at the output and no switches switching 45 60 µA µA SYNC = VIN, FS = 2MHz, no load at the output 19 25 mA SYNC = GND, VIN = 5.5V, EN = low 3.8 10 µA 0.600 0.606 OUTPUT REGULATION Reference Voltage VREF VFB Bias Current IVFB Line Regulation Soft-Start Ramp Time Cycle Soft-Start Charging Current 0.593 0.1 µA VIN = VO + 0.5V to 5.5V (minimal 2.7V) 0.2 %/V SS = SGND ISS V VFB = 0.75V VSS = 0.1V 1 1.7 2.1 ms 2.5 µA OVERCURRENT PROTECTION Current Limit Blanking Time tOCON 17 Clock pulses Overcurrent and Auto Restart Period tOCOFF 8 SS cycle Positive Peak Current Limit IPLIMIT FN8359 Rev.10.00 Jan 12, 2021 ISL78234, TA = +25°C 5.4 ISL78234, TA = -40°C to +125°C 5.2 ISL78233, TA = +25°C 3.9 ISL78233, TA = -40°C to +125°C 3.7 6.7 4.9 8.1 A 9 A 6 A 6.6 A Page 6 of 20 ISL78233, ISL78234 Electrical Specifications Unless otherwise noted, all parameter limits are established across the recommended operating conditions and the specification limits are measured at the following conditions: TA = -40°C to +125°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued) PARAMETER Peak Skip Limit SYMBOL ISKIP TEST CONDITIONS ISL78234, TA = +25°C ISL78234, TA = -40°C to +125°C INLIMIT TYP MAX (Note 9) UNIT 0.9 1.1 1.35 A 1.5 A 0.84 ISL78233, TA = +25°C 0.7 1.2 A ISL78233, TA = -40°C to +125°C 0.6 1.3 A -275 375 mA -1.3 A -0.6 A Zero Cross Threshold Negative Current Limit MIN (Note 9) TA = +25°C -5.1 TA = -40°C to +125°C -6.0 0.9 -2.8 COMPENSATION Error Amplifier Transconductance Transresistance RT COMP = VDD, internal compensation 125 µA/V External compensation 130 µA/V 4A application 0.145 0.2 0.25 Ω VIN = 5V, IO = 200mA 26 35 50 mΩ VIN = 2.7V, IO = 200mA 38 52 78 mΩ VIN = 5V, IO = 200mA 5 11 20 mΩ VIN = 2.7V, IO = 200mA 8 15 31 mΩ PHASE P-Channel MOSFET ON-Resistance N-Channel MOSFET ON-Resistance PHASE Maximum Duty Cycle 100 PHASE Minimum On-Time SYNC = High % 100 ns 2350 kHz OSCILLATOR Nominal Switching Frequency fSW FS = VIN 1700 FS with RS = 402kΩ 420 FS with RS = 42.2kΩ SYNC Logic LOW to HIGH Transition Range 2000 kHz 4200 0.67 SYNC Hysteresis 0.75 kHz 0.84 0.17 SYNC Logic Input Leakage Current VIN = 3.6V 3.7 V V 5 µA 0.3 V 1 2 ms 0.01 0.1 µA PG Output Low Voltage IPG = 1mA Delay Time (Rising Edge) Time from VOUT reached regulation PG Pin Leakage Current PG = VIN 0.5 OVP PG Rising Threshold 0.80 UVP PG Rising Threshold 80 86 V 90 % UVP PG Hysteresis 5.5 % PGOOD Delay Time (Falling Edge) 6.5 µs EN Logic Input Low (Note 10) EN_VIL Logic Input High EN_VIH EN Logic Input Leakage Current 0.4 0.9 V V Pulled up to 3.6V 0.1 1 µA Thermal Shutdown Temperature Rising 150 °C Thermal Shutdown Hysteresis Temperature Falling 25 °C NOTE: 9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 10. EN should be held below the EN_VIL until VIN exceeds VUVLO rising. FN8359 Rev.10.00 Jan 12, 2021 Page 7 of 20 ISL78233, ISL78234 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. 100 100 2.5VOUT 2.5VOUT 90 80 1.5VOUT 1.2VOUT EFFICIENCY (%) EFFICIENCY (%) 90 1.8VOUT 70 60 50 80 1.5VOUT 1.2VOUT 1.8VOUT 70 60 50 40 0.0 0.5 1.0 1.5 2.0 2.5 OUTPUT LOAD (A) 3.0 3.5 40 4.0 0.0 FIGURE 4. EFFICIENCY vs LOAD (2MHz, 3.3VIN PWM) 0.5 1.0 1.5 2.0 2.5 OUTPUT LOAD (A) 3.0 3.5 4.0 FIGURE 5. EFFICIENCY vs LOAD (2MHz, 3.3VIN PFM) 100 100 2.5VOUT 3.3VOUT 90 3.3VOUT 90 1.5VOUT 1.2VOUT EFFICIENCY (%) EFFICIENCY (%) 2.5VOUT 80 1.8VOUT 70 60 50 40 1.2VOUT 1.8VOUT 70 60 50 0.0 0.5 1.0 1.5 2.0 2.5 OUTPUT LOAD (A) 3.0 3.5 40 0.0 4.0 FIGURE 6. EFFICIENCY vs LOAD (2MHz, 5VIN PWM) 1.219 1.515 1.214 1.510 1.209 3.3VIN PFM 1.204 5VIN PFM 1.199 5VIN PWM 1.194 1.189 3.3VIN PWM 1.184 1.179 0.5 1.0 1.5 2.0 2.5 OUTPUT LOAD (A) 3.0 3.5 4.0 FIGURE 7. EFFICIENCY vs LOAD (2MHz, 5VIN PFM) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.5VOUT 80 3.3VIN PFM 1.505 1.500 5VIN PFM 1.495 5VIN PWM 1.490 1.485 3.3VIN PWM 1.480 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT LOAD (A) FIGURE 8. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V) FN8359 Rev.10.00 Jan 12, 2021 4.0 1.475 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT LOAD (A) FIGURE 9. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V) Page 8 of 20 4.0 ISL78233, ISL78234 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = VIN, 1.815 2.505 1.810 2.500 1.805 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) 3.3VIN PFM 1.800 5VIN PFM 1.795 5VIN PWM 1.790 1.785 3.3VIN PWM 1.780 1.775 0.0 0.5 1.0 2.495 3.3VIN PFM 2.490 5VIN PFM 2.485 2.475 3.3VIN PWM 2.470 1.5 2.0 2.5 3.0 3.5 4.0 5VIN PWM 2.480 2.465 0.0 0.5 1.0 1.5 2.5 3.0 3.5 4.0 FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V) FIGURE 10. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V) 3.309 75 PHASE MINIMUM ON-TIME (ns) 3.301 OUTPUT VOLTAGE (V) 2.0 OUTPUT LOAD (A) OUTPUT LOAD (A) 5VIN PWM 3.293 3.285 5VIN PFM 3.277 3.269 3.261 3.253 3.245 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 T = +125°C 70 65 60 T = +25°C 55 T = -40°C 50 3.0 3.5 4.0 OUTPUT LOAD (A) FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V) PHASE 5V/DIV 4.5 VIN (V) 5.5 FIGURE 13. PHASE MINIMUM ON-TIME vs VIN (2MHz) PHASE 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 400µs/DIV FIGURE 14. START-UP AT NO LOAD (PFM) FN8359 Rev.10.00 Jan 12, 2021 5.0 400µs/DIV FIGURE 15. START-UP AT NO LOAD (PWM) Page 9 of 20 6.0 ISL78233, ISL78234 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) PHASE 5V/DIV VOUT 1V/DIV PHASE 5V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 400µs/DIV 400µs/DIV FIGURE 16. SHUTDOWN AT NO LOAD (PFM) FIGURE 17. SHUTDOWN AT NO LOAD (PWM) PHASE 5V/DIV PHASE 5V/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 500µs/DIV FIGURE 18. START-UP AT 4A LOAD (PWM) 500µs/DIV FIGURE 19. SHUTDOWN AT 4A LOAD (PWM) IOUT 2A/DIV IOUT 2A/DIV VOUT 1V/DIV VOUT 1V/DIV VEN 5V/DIV VEN 5V/DIV PG 5V/DIV PG 5V/DIV 500µs/DIV 500µs/DIV FIGURE 20. START-UP AT 4A LOAD (PFM) FIGURE 21. SHUTDOWN AT 4A LOAD (PFM) FN8359 Rev.10.00 Jan 12, 2021 Page 10 of 20 ISL78233, ISL78234 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) PHASE 1V/DIV PHASE 1V/DIV 10ns/DIV 10ns/DIV FIGURE 22. JITTER AT NO LOAD PWM (1MHz) FIGURE 23. JITTER AT FULL LOAD PWM (1MHz) PHASE 5V/DIV PHASE 5V/DIV VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV IL 1A/DIV IL 1A/DIV 500ns/DIV 20ms/DIV FIGURE 24. STEADY STATE AT NO LOAD PWM FIGURE 25. STEADY STATE AT NO LOAD PFM PHASE 5V/DIV VOUT RIPPLE 20mV/DIV IL 2A/DIV 500ns/DIV FIGURE 26. STEADY STATE AT 4A PWM FN8359 Rev.10.00 Jan 12, 2021 Page 11 of 20 ISL78233, ISL78234 Typical Operating Performance Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 4A. (Continued) VOUT RIPPLE 100mV/DIV VOUT RIPPLE 100mV/DIV ILOAD 2A/DIV ILOAD 2A/DIV 200µs/DIV 200µs/DIV FIGURE 27. LOAD TRANSIENTS (PWM) FIGURE 28. LOAD TRANSIENTS (PFM) PHASE 5V/DIV VOUT 1V/DIV IL 2A/DIV IL 5A/DIV VOUT 1V/DIV PG 5V/DIV PG 5V/DIV 4µs/DIV 40µs/DIV FIGURE 29. OUTPUT SHORT-CIRCUIT FIGURE 30. OVERCURRENT PROTECTION PHASE 5V/DIV VOUT 1V/DIV VOUT 2V/DIV IL 5A/DIV PG 2V/DIV PG 5V/DIV 20µs/DIV FIGURE 31. OVERVOLTAGE PROTECTION FN8359 Rev.10.00 Jan 12, 2021 20ms/DIV FIGURE 32. OVER-TEMPERATURE PROTECTION Page 12 of 20 ISL78233, ISL78234 Theory of Operation The ISL78233 and ISL78234 are step-down switching regulators optimized for automotive battery powered applications. The regulator operates at a 2MHz default switching frequency for high efficiency and allow smaller form factor, when FS is connected to VIN. By connecting a resistor from FS to SGND, the operational frequency adjustable range is 500kHz to 4MHz. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The quiescent current when the output is not loaded is typically only 45µA. The supply current is typically only 3.8µA when the regulator is shut down. PWM Control Scheme Pulling the SYNC pin HI (>0.8V) forces the converter into PWM mode, regardless of output current. The ISL78233 and ISL78234 employ the current-mode Pulse-Width Modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 3 on page 3 shows the functional block diagram. The current loop consists of the oscillator, the PWM comparator, current-sensing circuit, and the slope compensation for the current loop stability. The slope compensation is 440mV/Ts, which changes proportionally with frequency. The gain for the current-sensing circuit is typically 200mV/A. The control reference for the current loops comes from the Error Amplifier's (EAMP) output. The PWM operation is initialized by the clock from the oscillator. The P-channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA and the slope compensation reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the PFET and turn on the N-channel MOSFET. The NFET stays on until the end of the PWM cycle. Figure 33 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier’s CSA output. The output voltage is regulated by controlling the VEAMP voltage to the current loop. The bandgap circuit outputs a 0.6V reference voltage to the voltage loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and is discussed separately. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated with the 55pF and 100kΩ RC network. The maximum EAMP voltage output is precisely clamped to 2.5V. FN8359 Rev.10.00 Jan 12, 2021 VEAMP VCSA DUTY CYCLE IL VOUT FIGURE 33. PWM OPERATION WAVEFORMS Skip Mode Pulling the SYNC pin LO (