DATASHEET
ISL78268
FN8657
Rev 3.00
December 12, 2014
55V Synchronous Buck Controller with Integrated 3A Driver
Features
The ISL78268 is a grade 1, automotive, synchronous buck
controller with integrated high/low side MOSFET drivers. It
supports a wide operating input voltage range of 5V to 55V
and up to 60V at VIN when not switching. The integrated driver
offers adaptive dead-time control and is capable of supplying
up to 2A sourcing and 3A sinking current, allowing the
ISL78268 to support power stages designed for a wide range
of loads, from under 1A to over 25A.
• Wide input range 5V to 55V (switching); withstand 60V
(non-switching)
• Integrated 2A sourcing, 3A sinking MOSFET drivers
• Constant current regulation/limiting - dedicated average
current control loop
• Adjustable switching frequency or external synchronization
from 50kHz up to 1.1MHz
ISL78268’s fully synchronous architecture enables power
conversion with very high efficiency and improved thermal
performance over standard buck converters. The ISL78268 also
offers diode emulation mode for improved light load efficiency.
• Low shutdown current, IQ 3.5V
VIL(FALL) < 1.5V
PLL_COMP
RPLLCMP
CPLLCMP2
CPLLCMP1
FIGURE 41. CLOCK GENERATOR AND EXTERNAL CLOCK
SYNCHRONIZATION BLOCK
FN8657 Rev 3.00
December 12, 2014
Page 21 of 34
ISL78268
SYNCHRONIZATION WITH EXTERNAL CLOCK
The ISL78268 contains a PLL circuitry and has frequency
synchronization capability by simply connecting the FSYNC pin to
an external square pulse waveform.
than 0.4V (typ) at the starting of soft-start, the device starts with
normal switching frequency from the beginning.
VCC
5µA
The PLL block detects the rising edge of external clock and
synchronizes it with the rising edge of UG. The delay time of UG
rising from the external clock rising edge is 325ns (typ).
SS
3.4V
CLAMP
CSS
The FSYNC pin has special thresholds to detect the external
clock. The input high level of external clock should be higher than
3.5V and low level should be lower than 1.5V.
SOFT-START
CONTROL
LOGIC
+
-
0.4V
SS_DONE
When continuous external clock pulse is applied while operating
with internal clock which is determined by RFSYNC, this device
synchronizes with the external clock gradually and continues its
switching. However, when the external clock is removed for a certain
period (~6ms), the device will stop its switching and restart from the
initialization/soft-start process after about a 50ms interval.
The PLL is compensated with a series connected resistor and
capacitor (RPLLCMP and CPLLCMP) from the PLL_COMP pin to
GND and a capacitor (CPLLCMP2) from PLL_COMP to GND. For
stable operation, recommended to set RPLLCMP = 3.24kΩ,
CPLLCMP1 = 6.8nF, CPLLCMP2 = 1nF. The typical lock time for this
case will be around 0.8ms.
The CLKOUT pin provides a square pulse waveform at the
switching frequency. The amplitude is GND to VCC with
270ns (typ) pulse width, and the rising edge is 180° shifted from
the rising edge of UG.
Soft-Start
Soft-start is implemented by an internal 5µA current source
charging the soft-start capacitor (CSS) at SS to GND. The voltage
on the SS pin controls the reference voltage for the FB pin during
soft-start. When starting up the system while the output voltage
is remaining (prebiased), a prebias circuit charges the CSS
capacitor to the same voltage as FB voltage before soft-start
begins. This allows more accurate correlation between the
soft-start ramp time and the output voltage.
Assuming no prebiased output condition, the soft-start ramp
time is:
C SS
t SS = V REF ----------5A
(EQ. 2)
Where VREF is the 1.6V reference.
Assuming no load condition, the average inductor current
IL_softstart to charge the output capacitors from 0V to final
regulation voltage within soft-start time tSS can be estimated as:
C OUT
I Lsoftstart = V OUT ------------t SS
(EQ. 3)
If start-up with full load is required, the total inductor average
current at the soft-start period is the sum of full load current and
IL_softstart. Based on this consideration, enough soft-start time
should be set to make sure overcurrent protection is not tripped.
At the beginning of soft-start, if the prebiased VFB voltage is
lower than 0.4V (typ), the device is forced to switch at 50kHz (typ)
with minimum on-time of high-side MOSFET. When VFB reaches
0.4V (typ) or higher, the device operates with normal switching
frequency and on-time. If the prebiased VFB voltage is higher
FN8657 Rev 3.00
December 12, 2014
SS_Prebias
TO PWM CONTROL
& PGOOD CONTROL
+
-
+
0.4V
VOUT
+
FB
+
COMP
Gm
TO PWM COMPARATOR
-
VREF = 1.6V
COMP
FIGURE 42. SOFT-START BLOCK
The soft-start period will be finished when the SS pin voltage
reaches its clamp voltage (3.4V typ) with a 0.5ms (typ) additional
interval. At the end of soft-start period, the pull-down of the
PGOOD pin will be released and this pin will be pulled up by
external resistor, which will be biased to VCC or external logic
supply level.
While in soft-start period, the device operates in Diode Emulation
mode to prevent undesired negative current at inductor from
output. In this period, regardless of the configuration of IMON/DE
pin, i.e., either Forced PWM mode or Diode Emulation mode is
selected, only the high-side MOSFET will be switched and
low-side MOSFET will be kept off.
Bootstrap for High-side NMOS Drive
To turn on the high-side MOSFET properly, the ISL78268 employs
a bootstrap circuit using an external boot capacitor (CBOOT) and
diode (DBT). At the time the high-side MOSFET turns off, to
maintain the current on the inductor, the PH node will go down to
GND level at low-side MOSFET turn on. While in this low-side
MOSFET on period, the diode connected from PVCC to boot
capacitor will be forward biased and charge up the boot
capacitor. When the low-side MOSFET is turned off and the
high-side MOSFET is turned on after dead-time, the PH node goes
up to VIN level and the BOOT pin bias is VIN + PVCC - VF to drive
the high-side driver circuitry.
BOOT REFRESHING
In order to keep sufficient supply voltage for the high-side driver
circuit operation, the ISL78268 has a boot-refreshing circuit.
When the boot capacitor voltage becomes lower than 3.3V (typ),
the low side transistor is forced to turn on with its minimum on
time to charge the boot capacitor. The boot refreshing will occur
at the beginning of soft-start and pulse skipping operation at very
light load conditions.
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ISL78268
Current Sensing
PVCC
BOOT
VIN
-
RC
+
TO BOOT
REFRESH
CONTROL
The ISL78268 has two current sense amplifiers: one for high-side
MOSFET peak current sensing for PWM control and overcurrent
protections, and the other for output inductor current sensing for
average current control and diode emulation timing control.
DBT
LEVEL
SHIFT
3.3V
UG
CBOOT
RSENSE
PH
PVCC
VOUT
L
PWM
SIGNAL
DEAD TIME
CONTROL
LG
TO CURRENT
SENSE AMP
PGND
FIGURE 43. OUTPUT BOOT CONTROL
MINIMUM OFF-TIME CONSIDERATION
To ensure the charging of the boot capacitor, the device has
internally fixed minimum off time (tminoff) for the high-side
MOSFET. Just after the high-side MOSFET turns off, the PH node
goes down to GND level and boot capacitor will be charged from
PVCC via an external diode (Schottky diode is recommended).
However, when an NMOS with large Qg is selected to support
heavy load application, the internally fixed tminoff may not be
enough to charge the boot capacitor sufficiently. For this case, it is
recommended to adjust the switching frequency or input voltage
as the system has sufficient off time of high-side transistor.
PWM Operation
The switching cycle is defined as the time between UG pulse
initiation signals. The cycle time of the pulse initiation signal is
the inversion of the switching frequency set by the resistor
between the FSYNC pin and ground.
The ISL78268 uses peak current mode control. The PWM
operation is initialized by the clock from the oscillator. The
high-side MOSFET is turned on (UG) by the clock at the beginning
of a PWM cycle and the inductor current flows in the high-side
MOSFET and ramps up. When the sum of the current sense
signal (through ISEN1 current sense amplifier) and the slope
compensation signal reaches the error amplifier output voltage,
the PWM comparator is triggered and UG is turned off to shut
down the high-side MOSFET. The high-side MOSFET stays off until
the next clock signal comes for the next cycle.
After the high-side MOSFET is turned off, the low-side MOSFET
turns on with the fixed dead-time. The off timing of low-side
MOSFET is determined by either the next high-side on timing at
next PWM cycle or when the inductor current become zero if the
Diode Emulation mode is selected.
To prevent undesired shoot-through current at external high-side
and low-side MOSFETs, the device has adaptive dead-time
control and internally fixed dead-time. The internally fixed
dead-time is typically 55ns, for both high-side to low side and
low-side to high-side switching transition.
The output voltage is sensed by a resistor divider from VOUT to the
FB pin. The difference between the FB voltage and 1.6V (typ)
reference is amplified and compensated to generate the error
voltage signal at the COMP pin that is used for PWM generation
circuits.
FN8657 Rev 3.00
December 12, 2014
CURRENT SENSE AMPLIFIER 1 (CSA1)
The current-sense amplifier (CSA1) is used to sense the inductor
current in the current-sense resistor placed in series with the
high-side MOSFET. The sensed current information (ISEN1) is
used for peak current mode control and overcurrent protection.
Peak current mode control is implemented using CSA1 in the
PWM control loop as described in “PWM Operation”.
The cycle-by-cycle peak current limit (OC1) is implemented by
comparing ISEN1 with an 70µA threshold. At the peak current
limit comparator threshold, the PWM pulse is terminated.
During an overload condition when ISEN1 reaches 93µA (OC2
threshold), the IC enters into latch-off or hiccup mode, which is
defined by the HIC/LATCH pin configuration. If latch-off mode is
selected, the device stops switching when OC2 is tripped and will
not restart until the EN or VIN is toggled. If Hiccup mode is
selected, the PWM is disabled for 500ms (typ) before beginning
a soft-start cycle. Three consecutive OC2 faults are required to
enter hiccup or latch-off. OC2 hiccup or latch-off is enabled
during soft-start and normal operating modes.
CURRENT SENSE AMPLIFIER 2 (CSA2)
The current-sense amplifier (CSA2) is used to sense the
continuous (not pulsing as in RSEN1) inductor current either by
DCR sensing method or using a sense resistor in series with the
inductor for more accurate sensing. The sensed current signal is
used for three functions:
• Average constant current control
• Diode emulation
• Average OC protection
The ISEN2P voltage is also used to monitor the minimum output
voltage. Under the overload condition (OC1) or under the average
constant current control, if the voltage become lower than about
1.2V (typ), the device stops switching and enters Latch-off/
Hiccup mode.
If these three functions are not required in the application, CSA2
should be connected to VCC (or VIN).
SENSE RESISTOR CURRENT SENSING
A sense resistor can be placed in series with the inductor. As
shown in Figure 44, the ISL78268 senses the voltage across the
sense resistor. CSA1 is used to sense the high-side MOSFET’s
current. The sense resistor is placed between the input
capacitors and the high-side MOSFET.
CSA2 is used to sense the inductor current. A sense resistor is
placed between the inductor and the output capacitors.
The voltage on the ISEN(n)P and ISEN(n)N of the current sense
amplifier are forced to be equal. The voltage across RSET(n) is
equivalent to the voltage drop across the RSEN(n) resistor. The
Page 23 of 34
ISL78268
resulting current into the ISEN(n)P pin is proportional (scaled) to
the current in RSEN(n). Equation 4 is derived as:
R SEN n
----------------------I SEN n = I R
SEN n R SET n
(EQ. 4)
Where RSET(n) is the sum of RSET(n)A and RSET(n)B in Figure 44.
ISEN(n)P and ISEN(n)N have equal bias current (112µA typ)
therefore, the resistors RBIAS(n) and RSET(n) should be matched
to prevent offset.
To prevent noise injection from switching currents, it is
recommended to place a filter capacitor in between the RSET
resistors. Typically, 220pF ceramic capacitor is used when the
RSET(n) is 665Ω.
the voltage across the capacitor VCDCRS is equal to the voltage
drop across the DCR, i.e., proportional to the inductor current.
With the internal current sense amplifier, the capacitor voltage
VCDCRS is replicated across the sense resistor RSET2. Therefore,
the current flow into the ISEN2P pin is also proportional to the
inductor current. Equation 7 shows the relation between sensed
current ISEN2 and inductor current (IL) when DCR sensing is used.
DCR
I SEN2 = I L ---------------R
(EQ. 7)
SET2
VIN
CIN
+
TO
CSA1
RSEN1
-
VIN
ISEN1 + 112µA
CIN
+
RSEN1
-
RSET1A
RBIAS1A
UG
ISEN1P
RSET1B
RBIAS1B
AV = 1
ISEN1
CSA1
+
LG
DCR
ISEN1N
UG
112µA
112µA
L
L
+
RSEN2
-
+
-
IL
-
ISEN2P
-
R
CDCRS SET2
RBIAS2
AV = 1
ISEN2
CSA2
ISEN2N
ISEN2+112µA
VOUT
+
112µA
VOUT
LG
RDCRS
IL
RSET2A
RBIAS2A
ISEN2P
RSET2B
RBIAS2B
COUT
AV = 1
ISL78268 INTERNAL CIRCUITS
FIGURE 45. INDUCTOR DCR CURRENT SENSING
112µA
112µA
112µA
Adjustable Slope Compensation
ISL78268 INTERNAL CIRCUITS
FIGURE 44. SENSE RESISTOR CURRENT SENSING
INDUCTOR DCR SENSING
An inductor has a distributed resistance as measured by the DCR
(Direct Current Resistance) parameter.
The inductor DCR can be modeled as a lumped quantity, as
shown in Figure 45, Equation 5 shows the S-domain equivalent
voltage across the inductor VL.
V L = I L s L + DCR
(EQ. 5)
A simple R-C network across the inductor can extract the DCR
voltage, as shown in Figure 45.
The voltage on the capacitor VCDCRS, can be shown to be
proportional to the channel current IL, see Equation 6.
L
s ----------- + 1 DCR I L
DCR
V CDCRS = -----------------------------------------------------------------------------------1
R DCRS ------------- + s C DCRS + 1
R
(EQ. 6)
SET
If the CDCRS is selected so 2**fSW*CDCRS is much greater than
1/RSET, the 1/RSET will be negligible. Also, if the R-C network
components are selected such that the time constant
(RDCRS*CDCRS) matches the inductor time constant (L/DCR),
FN8657 Rev 3.00
December 12, 2014
112µA
CSA2
ISEN2N
COUT
112µA
112µA
ISEN2
A buck converter operating in peak current mode requires slope
compensation when the duty cycle is larger than 50%. It is
advisable to add slope compensation when the duty cycle is
approximately 30% or more since a transient load step can push
the duty cycle higher than the steady state level. When slope
compensation is too low, the converter can suffer from
subharmonic oscillation, which may result in noise emissions at
half the switching frequency. On the other hand,
overcompensation of the slope may reduce the phase margin.
Therefore, proper design of the slope compensation is needed.
The ISL78268 features adjustable slope compensation by
setting the resistor value RSLOPE from the SLOPE pin to GND.
Figure 46 shows the block diagram related to slope compensation.
For current mode control, in theory we need the compensation
slope mSL to be larger than 50% of the inductor current down
ramp slope mb.
Equation 8 shows the resistor value at SLOPE PIN to create a
compensation ramp.
6
Lx10 xR SET
R SLOPE = --------------------------------------------------
KxV OUT xR SEN x1.5
(EQ. 8)
Where K is the selected gain of compensation slope over
inductor down slope. For example, K = 1 gives the RSLOPE value
generating a compensation slope equal to inductor current down
ramp slope. Theoretically, the K needs to be larger than 0.5 and
in general, more than 1.0 is used in the actual application.
Page 24 of 34
ISL78268
VIN
RSET ISEN1P
-
VRAMP
ISEN1
RSEN
+
RBIAS ISEN1N
RG
VCC
VOUT
ON WHILE
UG ON
ISL1 = n*ISLOPE
ISL
VSL
CSL
ON WHILE
LG ON
ISLOPE
+
Vrefsl = 0.5V
SLOPE
RSLOPE
mb
ISEN1
ISL
mSL
m
ma1
a1==Mam+am+SLmSL
VRAMP
VRAMP = (ISEN1+ISL)*RG
FIGURE 46. SLOPE COMPENSATION BLOCK
Light Load Efficiency Enhancement
For switching mode power supplies, the total loss is related to
both the conduction loss and the switching loss. The conduction
loss dominates at heavy load while the switching loss dominates
at light load condition. The ISL78268 has the option to be set in
cycle-by-cycle Diode Emulation mode and pulse skipping
features to enhance the light load efficiency.
IMON/DE is used to select DE (Diode Emulation) mode. When the
IMON/DE is connected to an external resistor or shorted to GND,
the DE mode is selected. Also, if IMON/DE pin is pulled up to VCC
level, the device operates in Forced PWM mode.
To achieve Diode Emulation mode, the current sense amplifier
CSA2 is used to sense the output inductor current either by DCR
sensing or an accurate current shunt resistor.
DIODE EMULATION AT LIGHT LOAD CONDITION
When DE mode is selected, if the inductor current reaches
discontinuous conduction mode (DCM) operation, the ISL78268
controller will turn off the low-side MOSFET and enter into Diode
Emulation mode.
FN8657 Rev 3.00
December 12, 2014
While in soft-start period until the PGOOD pull-down is released,
the low-side MOSFET is forced off (in either cases of DE mode or
Forced PWM mode is selected).
PULSE SKIPPING AT DEEP LIGHT LOAD CONDITION
If the converter enters Diode Emulation mode and the load is
further reduced, COMP voltage becomes lower than the
minimum threshold and the device skips the pulses to increase
the deep light load efficiency.
Average Constant Current Control
In normal PWM operation, the PWM pulse is terminated when
the sensed peak current reaches the error amplifier control
voltage. But some applications, such as charging a battery, may
desire constant output current control instead of output voltage
control. To support such requirements, ISL78268 provides the
average constant current control loop to control the average
current up to the FB regulated output voltage.
Average Constant Current control operates in the range of
approximately 25% to 100% of targeted output voltage. This is
due to the function described in the soft-start sequence (t6-t7)
when the FB voltage (VFB) is below 0.4V and the device operates
at 50kHz (typ) with minimum high-side MOSFET on time.
ISLOPE
ma
By utilizing the cycle-by-cycle diode emulation scheme, negative
current is prevented and the efficiency is improved from the
smaller RMS current in the power stage.
The IMON/DE pin serves to monitor the average current that is
used for average constant current control and Average
Overcurrent Protection (AVGOCP). The Current Sense Amplifier 2
(CSA2) output current, ISEN2, which is representing the output
current (see Figure 44 for RSEN and RSET positions) is sourcing
out from this pin. Equation 9 describes the relation between
output current (IOUT) and IMON/DE pin current (IIMON). An RC
network should be connected between the IMON/DE pin and
GND, such that the ripple current signal can be filtered out and
converted to a voltage signal to represent the averaged output
current. The time constant of the RC network should be on the
order of 10 to 100 times slower than the voltage loop bandwidth
so that the programmable current limit circuit does not interfere
with the control loop stability. The IMON/DE pin voltage VIMON
can be calculated as Equation 10.
R SEN
– 6
I IMON = I OUT -------------- + 68 10 0.125
R
SET
V IMON = I IMON R IMON
(EQ. 9)
(EQ. 10)
When the IMON/DE pin voltage is at 1.6V (typ), the average
constant output current control loop on the device limits the on
time of high-side MOSFET to keep the output current constant.
While the average constant output current control is working, the
output voltage may become lower than preset output voltage
because of the lowered duty cycle. Equation 11 shows the RIMON
for the desired average output current.
12.8
R IMON = --------------------------------------------------------------R SEN
–6
I OUT -------------- + 68 10
R SET
(EQ. 11)
Page 25 of 34
ISL78268
Fault Monitoring and Protection
OUTPUT OVERVOLTAGE DETECTION/PROTECTION
The ISL78268 actively monitors input/output voltage and current to
detect fault conditions. Fault monitors trigger protective measures
to prevent damage to the load.
The ISL78268 output overvoltage detection circuit is active after
soft-start is completed. The output voltage is monitored at the FB
pin and the output overvoltage trip point is set to 115% (typ) of
the FB reference voltage. If the output overvoltage condition is
longer than 10µs (typ) blanking time, the PGOOD pin is pulled
down and the controller moves into hiccup or latch-off mode.
PGOOD SIGNAL
The Power-Good indicator pin (PGOOD pin) is provided for fault
monitoring. The PGOOD pin is an open-drain logic output to
indicate that the soft-start period is completed and the output
voltage is within the specified range. An external pull-up resistor
(10kΩ to 100kΩ) is required to be connected between PGOOD
pin and VCC or external power supply (5.5V max). This pin is
pulled low during soft-start. The PGOOD pin is released high after
the voltage on SS pin reaches SS clamp voltage (3.4V typ) and
after a 0.5ms (typ) delay. PGOOD will be pulled low with a
10µs (typ) blanking filter when output UV, or OV fault, or VIN OV
fault occurs, or EN is pulled low. The PGOOD will be released high
after the 0.5ms (typ) delay when the above faults are removed.
HICCUP/LATCH-OFF OPERATION
As a response to fault detection, either Hiccup or Latch-off mode can
be selected by the configuration of the HIC/LATCH pin. When the
HIC/LATCH pin is pulled high (VCC), the fault response will be Hiccup
mode. When HIC/LATCH pin is pulled low (GND), the fault response
will be in Latch-off mode.
In Hiccup mode, the device will stop switching when a fault
condition is detected, and restart from soft-start after
500ms (typ). This operation will be repeated until fault conditions
are completely removed.
In Latch-off mode, the device will stop switching when a fault
condition is detected and be kept off even after fault conditions
are removed. Either toggling the EN pin or cycling VIN below the
POR threshold will restart the system.
INPUT OVERVOLTAGE PROTECTION
The recovery from output overvoltage in hiccup or latch-off is the
same as described in “Hiccup/Latch-off Operation”. If the hiccup
mode is selected, the output OV recovery threshold is 112% (typ)
of FB reference voltage.
CYCLE-BY-CYCLE PEAK OVERCURRENT
LIMITING/PROTECTION
ISL78268 features cycle-by-cycle peak overcurrent protections by
sensing the peak current at CSA1. The IC continuously compares
the CSA1 output current (ISEN1 calculated from Equation 4),
which is proportional to the current flowing at Current Sense
Resistor1 (RSEN1) with two overcurrent protection threshold,
70µA for OC1 and 93µA for OC2.
The OC1 and OC2 levels are defined as Equations 12 and 13.
I OC1 = 70 10
–6
I OC2 = 93 10
–6
R SET
-------------R SEN
(EQ. 12)
R SET
-------------R SEN
(EQ. 13)
If ISEN1 reaches OC1 threshold, the high-side MOSFET is turned
off. This reduces the converter duty cycle which decreases the
output voltage.
After OC1 protection has reduced the controller down to
minimum duty cycle, if the output current increases to the OC2
threshold for three consecutive switching cycles, the controller
disables the gate drivers and enters hiccup or latch-off mode.
The ISL78268 features overvoltage (OV) fault protection for the
input supply. When VIN is higher than 58V (typ), the UG and LG
gate drivers are disabled and the PGOOD pin is pulled low. There is
a 10µs (typ) transient filter to prevent noise spikes from triggering
input OV. The input OV response can be selected as latch-off or
hiccup.
The recovery from OC2 in hiccup or latch-off is the same as
described in the “Hiccup/Latch-off Operation”.
The recovery from output overvoltage in hiccup or latch-off is the
same as described in “Hiccup/Latch-off Operation”. If the hiccup
mode is selected, the input OV recovery threshold is below 55V (typ).
When the average constant current control loop is active, the IC
also provides average overcurrent protection.
OUTPUT UNDERVOLTAGE DETECTION
The ISL78268 detects the output undervoltage condition. The
output undervoltage threshold is set at 87.5% (typ) of the 1.6V FB
reference voltage. When the FB voltage is below the undervoltage
threshold for more than 10µs (typ), the PGOOD pin is pulled down.
If the output voltage rises above the undervoltage recovery
threshold of 90.5% (typ) of FB reference voltage, PGOOD is pulled
up after 0.5ms (typ) delay. During an undervoltage condition, the
device continues normal operation unless either OC2, AVGOCP,
Input OVP, or thermal shutdown protection is triggered.
The OC1 cycle-by-cycle current limiting and OC2 protection are
active during soft-start and normal operation period.
AVERAGE OVERCURRENT PROTECTION
When output current increases even the duty cycle becomes
minimum by the average constant current control loop, the
VIMON voltage rises above 1.6V. If VIMON reaches 2V (typ), the
ISL78268 stops gate drivers and enters into the hiccup mode.
This provides additional safety for the voltage regulator.
Equation 14 provides the RIMON value for the desired average
overcurrent protection level IOCPAVG.
16
R IMON = -------------------------------------------------------------------------R SEN
–6
I OCPAVG -------------- + 68 10
R SET
(EQ. 14)
The average overcurrent protection (2V REF at IMON/DE) will not
be asserted until the soft-start period is completed.
FN8657 Rev 3.00
December 12, 2014
Page 26 of 34
ISL78268
NEGATIVE CURRENT LIMIT
When operating in Forced PWM mode operation in light load, the
negative current from the output capacitor to GND flows by the
turn on of the low-side MOSFET. The ISL78268 provides
cycle-by-cycle negative current limit to prevent excess negative
current. Equation 15 shows the peak negative current limit
(INEGLIM) threshold.
I NEGLIM = – 50 10
–6
R SET
-------------R SEN
(EQ. 15)
The maximum LDO current can be supplemented with an
external PNP transistor as shown in Figure 48. The advantage is
that the majority of the power dissipation can be moved from the
ISL78268 to the external transistor. Choose RS to be 68Ω so that
the LDO delivers about 10mA when the external transistor begins
to turn on. The external circuit increases the minimum input
voltage to approximately 6.5V.
VIN
Rs
THERMAL PROTECTION
If the junction temperature reaches +160°C (typ), the ISL78268
switching will be disabled and enter into hiccup or latch-off
mode. When hiccup mode is selected, a 15°C (typ) hysteresis
insures that the device will not restart until the junction
temperature drops below +145°C (typ) in Hiccup mode.
VIN
ISL78268
PVCC
PVCC
Internal 5.2V LDO
The ISL78268 has an internal LDO with input at VIN and a fixed
5.2V/100mA output at PVCC. A 4.7µF, 10V or higher X5R or X7R
rated ceramic capacitor is recommended between PVCC to GND.
The output of this LDO is mainly used as the bias supply of the
internal circuitry. To provide a quiet power rail to the internal
analog circuitry, it is recommended to place RC filter between
PVCC and VCC. A 10Ω resistor between PVCC and VCC and at
least 1µF ceramic capacitor from VCC to GND are recommended.
OUTPUT CURRENT LIMITATION OF INTERNAL LDO
The internal LDO tolerates an input supply range of VIN up to 55V
(60V absolute maximum). However, the power losses at the LDO
need to be considered, especially when the gate drivers are
driving external MOSFETs with a large gate charge. At high VIN,
the LDO has significant power dissipation that may raise the
junction temperature where the thermal shutdown occurs.
Figure 47 shows the relationship between maximum allowed
LDO output current and input voltage. The curves are based on
+39°C/W thermal resistance JA of the package.
ILDO(MAX) (mA)
There are several ways to define the external components and
parameters of buck regulators. This section shows one example
of how to decide the parameters of the external components
based on the typical application schematics shown in Figure 4 on
page 8. In the actual application, the parameters may need to be
adjusted and also a few more additional components may need
to be added for the application specific noise, physical sizes,
thermal, testing and/or other requirements.
Output Voltage Setting
The output voltage (VOUT) of the regulator can be programmed by
an external resistor divider set from VOUT to FB and FB to GND.
VOUT can be defined as:
(EQ. 16)
In the actual application, the resistor value should be decided by
considering the quiescent current requirement and loop
response. Typically, between 10kΩ to 30kΩ will be used for the
RFB0.
TA = +25°C
120
Switching Frequency
100
80
TA = +75°C
60
40
TA= +125°C
20
0
Application Information
R FB1
V out = 1.6 1 + -------------
R
FB0
160
140
FIGURE 48. SUPPLEMENTING LDO CURRENT
5
10
15
20
25
30
35
VIN (V)
40
45
FIGURE 47. POWER DERATING CURVE
FN8657 Rev 3.00
December 12, 2014
50
55
60
Switching frequency may be determined by considering several
requirements such as system level response time, solution size,
EMC/EMI limitation, power dissipation and efficiency, ripple
noise level, minimum and maximum input voltage range, etc.
Higher frequency may improve the transient response and help
to minimize the solution size. However, this may increase the
switching losses and EMC/EMI concerns. Thus, a balance of
these parameters are needed when deciding the switching
frequency.
Once the switching frequency is decided, the frequency setting
resistor (RSYNC) can be determined by Equation 1.
Page 27 of 34
ISL78268
Output Inductor Selection
While the Buck Converter is operating in stable continuous
conduction mode (CCM), the output voltage and on-time of the
high-side transistor is determined by Equation 17:
t ON
V OUT = VIN --------- = VIN D
T
(EQ. 17)
Where T is the switching cycle (1/fSW) and D = tON/T is the
on-duty of the high-side transistor.
Under this CCM condition, the inductor ripple current can be
defined as Equation 18:
VIN – V OUT
V OUT
I L(P-P) = t ON ----------------------------- = t OFF ------------L
L
(EQ. 18)
(EQ. 19)
In general, once the inductor value is determined, the ripple
current varies by the input voltage. At the maximum input
voltage, the on-duty becomes minimum and the ripple current
becomes maximum. So, the minimum inductor value can be
estimated from Equation 20.
VIN max – V out V OUT
L min = -------------------------------------- -------------------f SW IL max VIN max
(EQ. 20)
In DC/DC converter design, this ripple current will be set around
20% to 50% of maximum DC output current. A reasonable
starting point to adjust the inductor value will be around 30% of
the maximum DC output current.
Increasing the value of inductor reduces the ripple current and
thus ripple voltage. However, the large inductance value may
reduce the converter’s response time to a load transient. Also,
this reduces the ramp signal and may cause a noise sensitivity
issue.
Under stable operation, the peak current flow in the inductor will
be the sum of output current and 1/2 of ripple current.
I L(P-P)
I L = --------------- I OUT
2
(EQ. 21)
This peak current at maximum load condition must be lower
than the saturation current rating of the inductor with enough
margin. In the actual design, the largest peak current may be
observed at the start-up or heavy load transient. Therefore, the
inductor’s size needs to be determined with the consideration of
these conditions. In addition, to avoid exceeding the inductor’s
saturation rating, it is recommended to set the OCP trip point
between the maximum peak current and the inductor’s
saturation current rating.
Output Capacitor
To filter the inductor current ripples and to have sufficient
transient response, an output capacitor is required.
The current mode control loop allows the usage of lower ESR
ceramic capacitors and thus enables smaller board layout.
Electrolytic and polymer capacitors may also be used.
FN8657 Rev 3.00
December 12, 2014
The following are equations for the required capacitance value to
meet the desired ripple voltage level. Additional capacitance may
be used to lower the ripple voltage and to improve transient
response.
For the ceramic capacitor (low ESR):
I L
V OUTripple = -----------------------------------8 f SW C OUT
(EQ. 22)
Where IL is the inductor’s peak-to-peak ripple current, fSW is the
switching frequency and COUT is the output capacitor.
From the previous equations, the inductor value will be
determined as Equation 19:
VIN – V OUT V OUT
L = ----------------------------- ------------f SW
VIN
However, additional consideration may be needed to use the
ceramic capacitors. While the ceramic capacitor offers excellent
overall performance and reliability, the actual capacitance may
be considerably lower than the advertised value if used DC
biased condition. The effective capacitance can be easily 50%
lower than that of the rated value.
Required minimum output capacitance based on ripple current
will be:
I L
C OUTmin = --------------------------------------------8 f SW V OUTmin
(EQ. 23)
If using electrolytic capacitors, the ESR will be the dominant
portion of the ripple voltage.
V OUTripple = I L ESR
(EQ. 24)
So, to reduce the ripple voltage, reduce the ripple current with
increasing the inductor value or use multiple capacitors in
parallel to reduce the ESR.
The other factor which may affect the selection of the output
capacitor will be the transient response. To estimate the
capacitance value related to transient response, a good starting
point is to determine the allowable overshoot in VOUT if the load
is suddenly reduced. In this case, energy stored in the inductor
will be transferred to COUT and causing its voltage rise.
Equation 25 determines the required output capacitor value in
order to achieve a desired overshoot level relative to the
regulated voltage.
2
I OUT L
C OUTtran = --------------------------------------------------------------------V OUTmax 2
2
V OUT ------------------------ – 1
Vout
(EQ. 25)
Where VOUTmax/VOUT is the relative maximum overshoot
allowed during the removal of the load.
After calculating the required capacitance for both ripple and
transient needs, choose the larger of the calculated values as the
output capacitance. To keep enough capacitance over the biased
voltage and temperature range, a good quality capacitor such as
X7R or X5R is recommended.
Input Capacitor
Depending upon the system input power rail conditions, the
aluminum electrolytic type capacitor is normally used to provide
the stable input voltage and restrict the switching frequency
pulse current in small areas over the input trace for better EMC
performance. The input capacitor should be able to handle the
RMS current from the switching power devices.
Page 28 of 34
ISL78268
Ceramic capacitors must be used at the VIN pin of the IC and
multiple ceramic capacitors including 1µF and 0.1µF are
recommended.
Place these capacitors as close as possible to the IC.
Power MOSFET
Loop Compensation Design
The ISL78268 uses constant frequency peak current mode
control architecture with a Gm amp as the error amplifier. An
external current sense resistor is required for the peak current
sensing and overcurrent protection. Figures 49 and 50 show the
conceptual schematics and control block diagram, respectively.
The external MOSFETs that are driven by the ISL78268 controller
need to be carefully selected to optimize the design of the
synchronous buck regulator.
Since the ISL78268 input voltage can be up to 55V, the
MOSFET's BVdss rating needs to have enough voltage margin
against input voltage tolerance and PH node voltage transient
during switching.
As the UG and LG gate drivers are 5V output, the MOSFET VGS
need to be in this range.
The MOSFET should have low Total Gate Charge (Qgd), low
ON-resistance (rDS(ON)) at VGS = 4.5V (less than 10mΩ is
recommended) and small gate resistance (Rg >1).
s
1 + ------------
R
Fm
esr
out
G T s = ---------------------------------------------- G v s ------------ ----------------------
R
1 + Fm Gi s Rs
s
1 + -------
s
o
n
Where,
1
o = ------------------------------C OUT R OUT
C OUT
Q p R OUT -----------L
(EQ. 31)
Equation 31 shows that the system is a single order system.
Therefore, a simple Type-2 compensator can be used to stabilize
the system. In the actual application, however, an extra phase
margin will be provided by a Type-3 compensator.
1
n = ------------------------L C OUT
PWM COMPARATOR GAIN Fm
Vo
The PWM comparator gain Fm for peak current mode control is
given by Equation 29.
1
D
Fm = ---------------- = ------------------------------------- m a + m SL T
V ramp
R1
RFB1
(EQ. 29)
C1
FB
Where mSL is the slew rate of the slope compensation and ma is
the inductor current slew rate while high-side MOSFET is on and
given as Equation 30.
+
-
COMP
Gm
Vref
RFB0
RCMP1
ROEA
CCMP2
CCMP1
He1
He2
VIN – V OUT
m a = R S ----------------------------L
(EQ. 30
FIGURE 52. TYPE-3 COMPENSATOR
COMPENSATOR DESIGN
The transfer function at error amplifier and its compensation
network will be expressed as Equation 32.
Where RS is the gain of the current sense amplifier.
Vc
mSL+ma
TOTAL Vramp
g
Vramp
CONVERTED H/S
INDUCTOR CURRENT
m
ma
b
SLOPE COMPENSATION
ADDER
ton
toff
v COMP
H e2 s = ----------------- = g m Z COMP =
v FB
mSL
m
1 + sR CMP C CMP1 R OEA
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
1 + s R CMP C CMP1 + R EOA C CMP1 + C CMP2 + C CMc2 C
R
R
S
CMP1 CMP OUT
If ROEA>>RCMP, CCMP1>>CCMP2, and ROEA = infinite, the
equation can be simplified as shown in Equation 33:
s
1 + ---------1
1 + s R CMP C CMP1
z2
H e2 s = g m ------------------------------------------------------------------------------------------ = ------- -------------------s
s C CMP1 1 + s R CMP C CMP2
s
1 + --------- p2
(EQ. 33)
T
FIGURE 51. CONVERTED SENSE CURRENT WAVEFORM
(EQ. 32)
Where,
gm
1 = -----------------C CMP1
1
z2 = -------------------------------------R CMP C CMP1
1
p2 = -------------------------------------R CMP C CMP2
FN8657 Rev 3.00
December 12, 2014
Page 30 of 34
ISL78268
Current Sense Circuit
The transfer function at the feedback resistor network is:
s
1 + ---------R FB0
z1
H e1 S = ---------------------------------- -------------------R FB0 + R FB1
s
1 + --------- p1
(EQ. 34)
Where,
Layout Consideration
1
z1 = ------------------------------------------C 1 R FB1 + R 1
For DC/DC converter design, the PCB layout is a very important to
ensure the desired performance.
1
p1 = ----------------------------------------------------------------------------------------------------------R FB1 R FB0 + R FB1 R 1 + R FB0 R 1
C 1 ----------------------------------------------------------------------------------------------R FB1 + R FB0
The total transfer function with compensation network and gain
stage will be expressed;
G open s = G T s H e1 s H e2 s
s
------------
R 1 +
o
esr
G open s = ------ ----------------------
R
s
s 1 + -------
o
s
1 + ----------
z1
R FB0
---------------------------------- --------------------
R
s
+ R FB1
1 + ----------
FBO
p1
To set the current sense resistor, the voltage across the current
sense resistor should be limited to less than 0.3V. In a typical
application, it is recommended to set the voltage across the
current sense resistor between 30mV to 100mV for the typical
load current condition.
(EQ. 35)
s
1 + -------- z2
1
------------------------
s
s
1 + ----------
p2
(EQ. 36)
From Equation 36, desired pole and zero locations can be
determined as in Equations 37 through 42.
o
1
f po = ----------- = ----------------------------------------------2
2 C OUT R OUT
(EQ. 37)
z1
1
f z1 = ----------- = ----------------------------------------------------------2
2 C 1 R FB1 + R 1
(EQ. 38)
z2
1
f z2 = ----------- = ----------------------------------------------------2
2 C CMc1 R CMP
(EQ. 39)
R FB1 + R FB2
p1
f p1 = ----------- = ------------------------------------------------------------------------------------------------------------------2
2C 1 R FB1 R FB0 + R FB1 R 1 + R FB0 R 1
(EQ. 40)
p2
1
f p2 = ----------- = -----------------------------------------------------2
2 C CMP2 R CMP
(EQ. 41)
esr
1
f zesr = ------------ = --------------------------------------------2
2 C OUT R esr
(EQ. 42)
1. Place the input ceramic capacitor as close as possible to the
VIN pin and power ground connecting to the power MOSFET.
Keep this loop (input ceramic capacitor, IC VIN pin and
MOSFET) as small as possible to reduce voltage spikes
induced by the trace parasitics.
2. Place the input aluminum capacitor close to IC VIN and
ceramic capacitors.
3. Keep the phase node copper area small but large enough to
handle the load current.
4. Place the output ceramic and aluminum capacitors as close
as possible to the power stage components.
5. Place multiple vias under the thermal pad of the IC. The
thermal pad should be connected to the ground copper plane
with as large an area as possible in multiple layers to
effectively reduce the thermal impedance.
6. Place the 4.7µF decoupling ceramic capacitor at the VCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
7. Keep the bootstrap capacitor as close as possible to the IC.
8. Keep the driver traces as short as possible and try to avoid
using a via in the driver path to achieve the lowest impedance.
9. Place the current sense resistor as close as possible to the IC.
Keep the traces of current sense lines symmetric to each
other to avoid undesired switching noise injections.
In general, set fz2 and fz1 close to the fpo. Set fp2 near the
desired bandwidth. Set fp1 close to fzesr .
VCC Input Filter
To provide a quiet power rail to the internal analog circuitry, it is
recommended to place RC filter between PVCC and VCC. A 10Ω
resistor between PVCC and VCC and at least 1µF ceramic
capacitor from VCC to GND are recommended.
FN8657 Rev 3.00
December 12, 2014
Page 31 of 34
ISL78268
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to
make sure you have the latest Rev.
DATE
REVISION
December 12, 2014
FN8657.3
CHANGE
Functional Pin Description
Page 3, FSYNC description. Changed from: There is a 100ns delay from the FSYNC pin's….
To: There is a 325ns delay from the FSYNC pin's….
Page 4, PVCC description. Changed from: The PVCC operating range is 4V to 5.4V.
To: The PVCC operating range is 4.75V to 5.5V.
VCC description. Changed from: range of 4.7V to 5.5V, To: range of 4.75V to 5.5V,
Typical Application Schematics
Page 7, Left side changed from: HIC/LATCH:Connect to either Vcc for Latch-off mode or GND for Hiccup mode
To: HIC/LATCH:Connect to either Vcc for Hiccup mode or GND for Latch-off mode
Page 8, Left side changed from: HIC/LATCH:Connect to either Vcc for Latch-off mode or GND for Hiccup mode
To: HIC/LATCH:Connect to either Vcc for Hiccup mode or GND for Latch-off mode
Page 9, Left side changed from: HIC/LATCH:Connect to either Vcc for Latch-off mode or GND for Hiccup mode
To: HIC/LATCH: Connect to either Vcc for Hiccup mode or GND for Latch-off mode
Page 10, Electrical specification table, Test condition of Input Voltage range, changed from "For VIN = 5 the
internal ... " to "For VIN = 5V, the internal ..."
Elecrical Spec table, Page 11, Phase Lock Loop Locking Time
Changed in Test Conditions: Cpllcmp2=_nF to: Cpllcmp2=1nF
Page 20, Operation Description, 2nd sentence changed from: "such as input and output overvoltage protection,
output overvoltage protection" to: "input overvoltage protection, output overvoltage protection"
Page 22, SYNCHRONIZATION WITH EXTERNAL CLOCK, 2nd paragaph
Changed from : The delay time of UG rising from the external clock rising edge is 100ns (typ).
To: The delay time of UG rising from the external clock rising edge is 325ns (typ).
Page 25, Figure 46 changed: "ma1 = Ma + mSL" to: "ma1 = ma + mSL"
Page 30, EQ. 30 changed : mn=RS*…… to: ma=RS*……
Figure 51 changed: mb to: ma
August 1, 2014
FN8657.2
On page 1 in the Features section, updated the 5th bullet from “Low shutdown current, IQ
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