DATASHEET
ISL78322
FN7908
Rev 3.00
November 30, 2016
Dual 2A/1.7A, 2.25MHz High-Efficiency, Synchronous Buck Regulator
Features
The ISL78322 is a high-efficiency, dual synchronous step-down
DC/DC regulator that can deliver up to 2A/1.7A continuous
output current per channel. The channels are 180° out-ofphase for input RMS current and EMI reduction. The supply
voltage range of 2.8V to 5.5V allows for the use of a single Li+
cell, three NiMH cells or a regulated 5V input. The current
mode control architecture enables very low duty cycle
operation at high frequency with fast transient response and
excellent loop stability. The ISL78322 operates at 2.25MHz
switching frequency, which allows for the use of small, low cost
inductors and capacitors. Each channel is optimized for
generating an output voltage as low as 0.6V.
• Dual 2A/1.7A high-efficiency, synchronous buck regulator
with up to 97% efficiency
• 2.8V to 5.5V input supply range
• 180° out-of-phase outputs reduce ripple current and EMI
• Start-up with prebiased output prevents negative current
flow in output stage
• External synchronization up to 8MHz
• Negative current detection and protection
• 100% maximum duty cycle for lowest dropout
The ISL78322 has a forced PWM mode that reduces noise and
RF interference.
• Internal current mode compensation
• Peak current limiting, hiccup mode short-circuit protection,
and over-temperature protection
The ISL78322 offers a 1ms Power-Good (PG) signal to monitor
both outputs at power-up. When shut down, ISL78322
discharges the output capacitors. Other features include
internal digital soft-start, enable for power sequence,
overcurrent protection, and thermal shutdown. The ISL78322
is offered in a 4mmx3mm, 12 Lead DFN package with 1mm
maximum height. The complete converter occupies less than
1.8cm2 area.
• Pb-free (RoHs compliant)
• AEC-Q100 qualified component
Applications
• DC/DC POL modules
• µC/µP, FPGA, and DSP power
The ISL78322 is qualified to AEC-Q100 and specified for
operation across the -40°C to +105°C (grade 2) ambient
temperature range.
• Automotive embedded processor power supply systems
Related Literature
• For a full list of related documents, visit our website
- ISL78322 product page
100
EFFICIENCY (%)
90
80
2.5VOUT1 PWM
3.3VOUT2 PWM
70
60
50
2.25MHz 5VIN AT +25°C
40
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
OUTPUT LOAD (A)
FIGURE 1. CHARACTERISTIC CURVE
FN7908 Rev 3.00
November 30, 2016
Page 1 of 17
ISL78322
Typical Applications
L1
1.2µH
OUTPUT1
2.5V/2A
LX1
C2
22µF
C3
10pF
PGND
R2
316k
INPUT 2.8V TO 5.5V
FB1
VIN
R3
100k
EN1
C1
2 x 10µF
ISL78322
L2
1.2µH
EN2
OUTPUT2
1.8V/1.7A
LX2
PG
C4
22µF
PGND
SYNC
R5
200k
C5
10pF
FB2
R6
100k
FIGURE 2. TYPICAL APPLICATION DIAGRAM - DUAL INDEPENDENT OUTPUTS
Ordering Information
PART NUMBER (Notes 1, 2, 3)
PART MARKING
ISL78322ARZ
PACKAGE
(RoHS COMPLIANT)
TEMP. RANGE (°C)
BEKA
-40 to +105
12 Ld 4x3 DFN
PKG.
DWG. #
L12.4x3
NOTES:
1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit tape and reel options. Refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see device information page for ISL78322. For more information on MSL, see techbrief TB363.
TABLE 1. COMPONENT VALUE SELECTION
VOUT
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
C1
2x10µF
2x10µF
2x10µF
2x10µF
2x10µF
2x10µF
C2 (or C4)
22µF
22µF
22µF
22µF
22µF
22µF
C3 (or C5)
10pF
10pF
10pF
10pF
10pF
10pF
L1 (or L2)
1.0~2.2µH
1.0~2.2µH
1.0~2.2µH
1.5~3.3µH
1.5~3.3µH
1.5~4.7µH
R2 (or R5)
33k
100k
150k
200k
316k
450k
R3 (or R6)
100k
100k
100k
100k
100k
100k
In Table 1, the minimum output capacitor value is given for
different output voltages to make sure the whole converter
system is stable. Output capacitance should increase to support
faster load transient requirement.
FN7908 Rev 3.00
November 30, 2016
Page 2 of 17
ISL78322
Block Diagram
SHUTDOWN
VCC SHUTDOWN
27pF
VIN1
250k
BANDGAP 0.6V
+
EN1
SOFTSoft
START
Start
PWM
LOGIC
CONTROLLER
PROTECTION
DRIVER
+
COMP
EAMP
3pF
PGND
SLOPE
COMP
+
+
CSA1
FB1
0.2V
1.6k
SCP
+
+
OCP
+
VIN
LX1
1.25V
OSCILLATOR
0.546V
1M
NEGATIVE
CURRENT LIMIT
PG
1ms
DELAY
ZERO - CROSS
SENSING
THERMAL
SHUT DOWN
SYNC
SHUTDOWN
VCC
SHUTDOWN
SHUTDOWN
VIN2
BANDGAP 0.6V
+
EN2
27pF
250k
SOFTSoft
START
Start
+
COMP
EAMP
PWM
LOGIC
CONTROLLER
PROTECTION
DRIVER
3pF
SLOPE
COMP
0.2V
PGND
+
+
CSA2
FB2
1.6k
LX2
SCP
+
+
OCP
1.1V
+
0.546V
NEGATIVE
CURRENT LIMIT
ZERO- CROSS
SENSING
FIGURE 3. BLOCK DIAGRAM
FN7908 Rev 3.00
November 30, 2016
Page 3 of 17
ISL78322
Pin Configuration
ISL78322
(12 LD DFN)
TOP VIEW
FB1
1
12 FB2
EN1
2
11 EN2
PG
3
VIN1
4
PAD
10 SYNC
9
VIN2
LX1
5
8
LX2
PGND1
6
7
PGND2
Pin Description
PIN
NUMBER
SYMBOL
DESCRIPTION
1
FB1
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output voltage can be set to
any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to
meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor the
Channel 1 regulator output voltage.
2
EN1
Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the VOUT1 and discharge output
capacitor when driven to low. Do not leave this pin floating.
3
PG
1ms timer output. At power-up or EN_ HI, this output is a 1ms delayed power-good signal for both the VOUT1 and VOUT2 voltages.
There is an internal 1MΩ pull-up resistor.
4
VIN1
Input supply voltage for Channel 1. Connect 10µF ceramic capacitor to PGND1.
5
LX1
6
PGND1
Negative supply for Power Stage 1.
7
PGND2
Negative supply for Power Stage 2 and system ground.
8
LX2
Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2.
9
VIN2
Input supply voltage for Channel 2 and to provide logic bias. Make sure that VIN2 is ≥ VIN1. Connect 10µF ceramic capacitor to
PGND2.
10
SYNC
Connect to logic low or ground for forced PWM mode. Connect to an external function generator for synchronization. Negative edge
trigger. Do not leave this pin floating.
11
EN2
Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the VOUT2 and discharge output
capacitor when driven to low. Do not leave this pin floating.
12
FB2
The feedback network of the Channel 2 regulator. FB2 is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB2. With a properly selected divider, the output voltage can be set to
any voltage between the power rail (reduced by converter losses) and the 0.6V reference. There is an internal compensation to
meet a typical application. In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor the
Channel 2 regulator output voltage.
-
Switching node connection for Channel 1. Connect to one terminal of inductor for VOUT1.
EXPOSED The exposed pad must be connected to the PGND1 and PGND2 pins for proper electrical performance. Add as many vias as
PAD
possible for optimal thermal performance.
FN7908 Rev 3.00
November 30, 2016
Page 4 of 17
ISL78322
Absolute Maximum Ratings
Thermal Information
(Reference to GND)
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
4x3 DFN Package (Notes 4, 5) . . . . . . . .
41
3
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)
EN1, EN2, PG, SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VIN + 0.3V
LX1, LX2. . . . . . . . . . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . or 7V (20ms)
FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV
Machine Model(Tested per JESD22-C101E) . . . . . . . . . . . . . . . . . . 250V
Charged Device Model (Tested per AEC-Q100-11) . . . . . . . . . . . . . . . 2kV
Latch-Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V to 5.5V
Load Current Range Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A
Load Current Range Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.7A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions:
TA = -40°C to +105°C, VIN = 2.8V to 5.5V, EN1 = EN2 = VIN, SYNC = 0V, L = 1.2µH, C1 = 2 x 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A.
(Typical values are at TA = +25°C, VIN = 3.6V). Boldface limits apply across the operating temperature range, -40°C to +105°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
2.5
2.8
V
INPUT SUPPLY
VIN Undervoltage Lock-out Threshold
VUVLO
Rising
Falling
2.0
2.4
V
Quiescent Supply Current
IVIN
SYNC = GND, EN1 = EN2 = VIN, fSW = 2.25MHz, no load at
the output
0.86
1.00
mA
Shutdown Supply Current
ISD
VIN = 5.5V, EN1 = EN2 = GND
6.5
12.0
µA
0.600
0.610
OUTPUT REGULATION
FB1, FB2 Regulation Voltage
VFB_
FB1, FB2 Bias Current
IFB_
Output Voltage Accuracy
0.590
VFB = 0.55V
SYNC = VIN, Io = 0A to 2A
Line Regulation
V
0.1
µA
±1.5
%
SYNC = GND, Io = 0A to 2A
±1
%
VIN = VO + 0.5V to 5.5V (minimal 2.8V)
0.2
%/V
1.3
ms
Soft-Start Ramp Time Cycle
OVERCURRENT PROTECTION
Dynamic Current Limit ON-time
tOCON
17
Clock
pulses
Dynamic Current Limit OFF-time
tOCOFF
4
SS cycle
Peak Overcurrent Limit
Negative Current Limit
FN7908 Rev 3.00
November 30, 2016
Ipk1
2.7
3.2
3.6
A
Ipk2
2.3
2.8
3.2
A
Ivalley1
-2.2
-1.6
-1.0
A
Ivalley2
-2.2
-1.6
-1.0
A
Page 5 of 17
ISL78322
Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions:
TA = -40°C to +105°C, VIN = 2.8V to 5.5V, EN1 = EN2 = VIN, SYNC = 0V, L = 1.2µH, C1 = 2 x 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A.
(Typical values are at TA = +25°C, VIN = 3.6V). Boldface limits apply across the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
VIN = 5.5V, IO = 200mA Channel 1
90
115
mΩ
VIN = 5.5V, IO = 200mA Channel 2
100
125
mΩ
VIN = 5.5V, IO = 200mA Channel 1
80
103
mΩ
90
112
mΩ
SYMBOL
TEST CONDITIONS
LX1, LX2
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
VIN = 5.5V, IO = 200mA Channel 2
LX_ Maximum Duty Cycle
PWM Switching Frequency
100
fSW
1.80
2.25
2.70
MHz
8.0
MHz
Synchronization Range
(Note 7)
Channel 1 to Channel 2 Phase Shift
Rising edge to rising edge timing
180
°
LX Minimum On Time
SYNC = High (forced PWM mode)
65
ns
Soft Discharge Resistance
RDIS_
EN = LOW
5.4
80
100
130
Ω
0.4
V
PG
Output Low Voltage
Sinking 1mA, VFB = 0.5V
PG Pin Leakage Current
PG = VIN = 3.6V
0.01
PG Pull-Up Resistor
0.10
1
Internal PGOOD Low Rising Threshold
Percentage of nominal regulation voltage
85
Internal PGOOD Low Falling Threshold
Percentage of nominal regulation voltage
78
Delay Time (Rising Edge)
91
97
85
92
0.76
Internal PGOOD Delay Time
(Falling Edge)
2
µA
MΩ
%
%
ms
4
µs
0.4
V
EN1, EN2, SYNC
Logic Input Low
Logic Input High
Enable Logic Input Leakage Current
1.4
IEN_
V
0.1
1
µA
Thermal Shutdown
150
°C
Thermal Shutdown Hysteresis
25
°C
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. The operational frequency per switching channel will be half of the SYNC frequency.
FN7908 Rev 3.00
November 30, 2016
Page 6 of 17
ISL78322
Typical Operating Performance
100
100
90
90
80
EFFICIENCY (%)
EFFICIENCY (%)
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.8V to
5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A.
1.8VOUT2
1.5VOUT2
2.5VOUT1
70
1.2VOUT1
60
80
1.8VOUT2
70
1.5VOUT1
2.5VOUT1
1.2VOUT1
60
50
50
40
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
OUTPUT LOAD (A)
1.6
1.8
40
0.0
2.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
OUTPUT LOAD (A)
1.6
1.8
2.0
FIGURE 5. EFFICIENCY vs LOAD, 2.25MHz, 5VIN PWM
FIGURE 4. EFFICIENCY vs LOAD, 2.25MHz, 3.3VIN PWM
1.23
0.90
0.75
1.22
3.3VIN PWM
OUTPUT VOLTAGE (V)
POWER DISSIPATION (W)
3.3VOUT2
0.60
0.45
0.30
5 VIN PWM
0.15
1.21
1.20
1.19
5VIN PWM
1.18
3.3V VIN PWM
0.00
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
OUTPUT LOAD (A)
1.6
1.8
1.17
0.0
2.0
2.53
1.53
2.52
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.54
1.52
5VIN PWM
1.50
1.49
0.2
0.4
0.6
0.8
1.0
1.2
1.4
OUTPUT LOAD (A)
1.6
1.8
2.0
FIGURE 8. VOUT REGULATION vs LOAD, 2.25MHz, 1.5V CHANNEL 2
FN7908 Rev 3.00
November 30, 2016
0.6
0.8
1.0
1.2
1.4
OUTPUT LOAD (A)
1.6
1.8
2.0
2.51
2.50
5VIN PWM
2.49
2.48
3.3V VIN PWM
3.3V VIN PWM
1.48
0.0
0.4
FIGURE 7. VOUT REGULATION vs LOAD, 2.25MHz, 1.2V, CHANNEL 1
FIGURE 6. POWER DISSIPATION vs LOAD, 2.25MHz, 1.8V,
CHANNEL 2
1.51
0.2
2.47
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
OUTPUT LOAD (A)
1.6
1.8
2.0
FIGURE 9. VOUT REGULATION vs LOAD, 2.25MHz, 2.5V CHANNEL 1
Page 7 of 17
ISL78322
Typical Operating Performance
1.83
2.54
1.82
2.53
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.8V to
5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Continued)
1.81
1.80
1.79
1.78
1.77
0.0
3.3V VIN PWM
2.52
2.51
2A LOAD
2.50
2.49
5VIN PWM
0.2
0.4
0.6
0A LOAD PWM
0.8
1.0
1.2
1.4
OUTPUT LOAD (A)
1.6
1.8
2.0
FIGURE 10. VOUT REGULATION vs LOAD, 2.25MHz, 1.8V, CHANNEL 2
2.48
2.5
2.8
3.1
3.4
1A LOAD
3.7
4.0
4.3
4.6
INPUT VOLTAGE (V)
4.9
5.2
FIGURE 11. OUTPUT VOLTAGE REGULATION vs VIN 2.5V CHANNEL 1
1.83
OUTPUT VOLTAGE (V)
1.82
1.81
0A LOAD PWM
1.80
1.79
0.8A LOAD
1.78
1.7A LOAD
1.77
2.5
2.8
3.1
3.4
3.7
4.0
4.3
4.6
INPUT VOLTAGE (V)
4.9
5.2
5.5
FIGURE 12. OUTPUT VOLTAGE REGULATION vs VIN 1.8V CHANNEL 2
LX2 2V/DIV
LX1 2V/DIV
VOUT2 RIPPLE 20mV/DIV
VOUT1 RIPPLE 20mV/DIV
IL1 0.2A/DIV
TB = 200ns/DIV
FIGURE 13. STEADY STATE OPERATION AT NO LOAD CHANNEL 1
(PWM)
FN7908 Rev 3.00
November 30, 2016
5.5
IL2 0.2A/DIV
TB = 200ns/DIV
FIGURE 14. STEADY STATE OPERATION AT NO LOAD CHANNEL 2
(PWM)
Page 8 of 17
ISL78322
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.8V to
5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Continued)
LX1 2V/DIV
LX2 2V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT2 RIPPLE 20mV/DIV
IL1 1A/DIV
IL2 1A/DIV
TB = 200ns/DIV
FIGURE 15. STEADY STATE OPERATION AT FULL LOAD CHANNEL 1
TB = 200ns/DIV
FIGURE 16. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 2
VOUT2 RIPPLE 50mV/DIV
VOUT1 RIPPLE 50mV/DIV
PG 5V/DIV
PG 5V/DIV
IL1 1A/DIV
IL2 1A/DIV
TB = 200µs/DIV
TB = 200µs/DIV
FIGURE 17. LOAD TRANSIENT CHANNEL 1 (PWM)
EN1 2V/DIV
FIGURE 18. LOAD TRANSIENT CHANNEL 2 (PWM)
EN2 2V/DIV
VOUT1 1V/DIV
VOUT2 1V/DIV
IL1 0.5A/DIV
IL2 0.5A/DIV
PG 5V/DIV
TB = 500µs/DIV
FIGURE 19. SOFT-START WITH NO LOAD CHANNEL 1 (PWM)
FN7908 Rev 3.00
November 30, 2016
PG 5V/DIV
TB = 500µs/DIV
FIGURE 20. SOFT-START WITH NO LOAD CHANNEL 2 (PWM)
Page 9 of 17
ISL78322
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.8V to
5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Continued)
EN1 2V/DIV
EN2 2V/DIV
VOUT1 1V/DIV
VOUT2 1V/DIV
IL1 1A/DIV
IL2 1A/DIV
PG 5V/DIV
TB = 500µs/DIV
FIGURE 21. SOFT-START AT FULL LOAD CHANNEL 1
PG 5V/DIV
TB = 500µs/DIV
FIGURE 22. SOFT-START AT FULL LOAD CHANNEL 2
EN2 2V/DIV
EN1 2V/DIV
VOUT1 1V/DIV
VOUT2 1V/DIV
IL1 0.2A/DIV
IL2 0.2A/DIV
PG 5V/DIV
PG 5V/DIV
TB = 200µs/DIV
TB = 200µs/DIV
FIGURE 23. SOFT-DISCHARGE SHUTDOWN CHANNEL 1
FIGURE 24. SOFT-DISCHARGE SHUTDOWN CHANNEL 2
LX1 2V/DIV
LX2 2V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT2 RIPPLE 20mV/DIV
IL1 0.2A/DIV
IL2 0.2A/DIV
SYNC 2V/DIV
SYNC 2V/DIV
TB = 100ns/DIV
FIGURE 25. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 8MHz CHANNEL 1
FN7908 Rev 3.00
November 30, 2016
TB = 100ns/DIV
FIGURE 26. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 8MHz CHANNEL 2
Page 10 of 17
ISL78322
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.8V to
5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Continued)
LX1 2V/DIV
LX2 2V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT2 RIPPLE 20mV/DIV
IL1 1A/DIV
IL2 0.5A/DIV
SYNC 2V/DIV
SYNC 2V/DIV
TB = 100ns/DIV
FIGURE 27. STEADY STATE OPERATION AT FULL LOAD WITH
FREQUENCY = 8MHz CHANNEL 1
TB = 100ns/DIV
FIGURE 28. STEADY STATE OPERATION AT FULL LOAD WITH
FREQUENCY = 8MHz CHANNEL 2
PG 1V/DIV
IL1 0.5A/DIV
IL1 0.5A/DIV
PG 1V/DIV
LX1 2V/DIV
VOUT1 2V/DIV
LX1 2V/DIV
VOUT1 2V/DIV
TB = 1µs/DIV
FIGURE 29. VOUT1 HARD SHORT TO VIN NEGATIVE CURRENT
WAVEFORMS AT HIGH LINE CHANNEL 1
PG 1V/DIV
IL2 0.5A/DIV
TB = 1µs/DIV
FIGURE 30. RECOVERY FROM HARD SHORT NEGATIVE CURRENT
WAVEFORMS VOUT1 CHANNEL 1
PG 1V/DIV
IL2 0.5A/DIV
VOUT2 2V/DIV
LX2 2V/DIV
LX2 2V/DIV
VOUT2 2V/DIV
TB = 10µs/DIV
FIGURE 31. VOUT2 HARD SHORT TO VIN NEGATIVE CURRENT
WAVEFORMS AT HIGH LINE CHANNEL 2
FN7908 Rev 3.00
November 30, 2016
TB = 1µs/DIV
FIGURE 32. RECOVERY FROM HARD SHORT NEGATIVE CURRENT
WAVEFORMS VOUT2 CHANNEL 2
Page 11 of 17
ISL78322
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.8V to
5.5V, EN = VIN, L1 = L2 = 1.2µH, C1 = 10µF, C2 = C4 = 22µF, IOUT1 = 0A to 2A, IOUT2 = 0A to 1.7A. (Continued)
LX1 5V/DIV
LX1 5V/DIV
VOUT1 2V/DIV
VOUT1 2V/DIV
IL1 2A/DIV
PG 5V/DIV
IL1 2A/DIV
TB = 5µs/DIV
FIGURE 33. OUTPUT SHORT-CIRCUIT CHANNEL 1
PG 5V/DIV
TB = 1ms/DIV
FIGURE 34. OUTPUT SHORT-CIRCUIT RECOVERY CHANNEL 1
LX2 5V/DIV
LX2 5V/DIV
VOUT2 1V/DIV
VOUT2 1V/DIV
IL2 2A/DIV
IL2 2A/DIV
PG 5V/DIV
TB = 5µs/DIV
FIGURE 35. OUTPUT SHORT-CIRCUIT CHANNEL 2
FN7908 Rev 3.00
November 30, 2016
PG 5V/DIV
TB = 1ms/DIV
FIGURE 36. OUTPUT SHORT-CIRCUIT RECOVERY CHANNEL 2
Page 12 of 17
ISL78322
Theory of Operation
The ISL78322 is a dual 2A/1.7A step-down switching regulator
optimized for battery-powered or mobile applications. The
regulator operates at 2.25MHz fixed switching frequency under
heavy load condition to allow small external inductor and
capacitors to be used for minimal Printed Circuit Board (PCB)
area. At light load, the regulator reduces the switching frequency,
unless forced to the fixed frequency, to minimize the switching
loss and to maximize the battery life. The two channels are 180°
out-of-phase operation. The supply current is typically only 6.5µA
when the regulator is shut down.
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
PWM Control Scheme
Pulling the SYNC pin LOW (
