DATASHEET
ISL8002, ISL8002A, ISL80019, ISL80019A
FN7888
Rev 4.00
July 31, 2014
Compact Synchronous Buck Regulators
Features
The ISL8002, ISL8002A, ISL80019 and ISL80019A are highly
efficient, monolithic, synchronous step-down DC/DC converters
that can deliver up to 2A of continuous output current from a 2.7V
to 5.5V input supply. They use peak current mode control
architecture to allow very low duty cycle operation. They operate
at either 1MHz or 2MHz switching frequency, thereby providing
superior transient response and allowing for the use of small
inductors. They also have excellent stability and provide both
internal and external compensation options.
• VIN range 2.7V to 5.5V
• VOUT range is 0.6V to VIN
• IOUT maximum is 1.5A or 2A (see Table 1 on page 3)
• Switching frequency is 1MHz or 2MHz (see Table 1 on page 3)
• Internal or external compensation option
• Selectable PFM or PWM operation option
The ISL8002, ISL8002A, ISL80019 and ISL80019A integrate
very low rDS(ON) MOSFETs in order to maximize efficiency. In
addition, since the high-side MOSFET is a PMOS, the need for a
Boot capacitor is eliminated, thereby reducing external
component count. They can operate at 100% duty cycle (at 1MHz)
with a dropout of 200mV at 2A output current.
• Overcurrent and short circuit protection
• Over-temperature/thermal protection
• VIN Undervoltage Lockout and VOUT Overvoltage Protection
• Up to 95% peak efficiency
Applications
These devices can be configured for either PFM (discontinuous
conduction) or PWM (continuous conduction) operation at light
load. PFM provides high efficiency by reducing switching losses at
light loads and PWM reduces noise susceptibility and RF
interference.
• General purpose point of load DC/DC
• Set-top boxes and cable modems
• FPGA power
These devices are offered in a space saving 8 pin 2mmx2mm
TDFN lead free package with exposed pad for improved thermal
performance. The complete converter occupies less than
0.10in2 area.
VIN
GND
2
EN
3
PG
4
PHASE 8
• See AN1803, “1.5A/2A Low Quiescent Current High
Efficiency Synchronous Buck Regulator”
100
+1.8V/2A
C5
22μF
C6
22μF
PGND 7
EN
VOUT
PAD
COMP 5
R2
100k 1%
9
VO
R 1 = R 2 ------------ – 1
VFB
FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION
(INTERNAL COMPENSATION OPTION)
FN7888 Rev 4.00
July 31, 2014
90
GND
R1
+0.6V 200k 1%
FB 6
MODE
PG
L1
1.2μH
Related Literature
EFFICIENCY (%)
ISL8002
+2.7V …+5.5V 1
VIN
C1
22μF
• DVD, HDD drives, LCD panels, TV
80
70
60
50
(EQ. 1)
40
0.0
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
0.2
0.4
0.6
0.8 1.0 1.2 1.4
OUTPUT LOAD (A)
1.6
1.8
2.0
FIGURE 2. EFFICIENCY vs LOAD
FSW = 1MHz, VIN = 3.3V, MODE = PFM, TA = +25°C
Page 1 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PFM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short-Circuit Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable, Disable, and Soft-Start Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100% Duty Cycle (1MHz Version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal ShutDown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
18
18
18
18
18
18
18
18
19
19
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
19
19
19
20
21
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FN7888 Rev 4.00
July 31, 2014
Page 2 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
TABLE 1. SUMMARY OF KEY DIFFERENCES
PART#
IOUT (MAX)
(A)
FSW
(MHz)
ISL80019
1.5
1
ISL80019A
1.5
2
ISL8002
2
1
ISL8002A
2
2
VIN RANGE
(V)
VOUT RANGE
(V)
PACKAGE
SIZE
2.7 to 5.5
0.6 to 5.5
8 pin 2mmx2mm TDFN
NOTE: In this datasheet, the parts in the table above are collectively called "device".
TABLE 2. COMPONENT VALUE SELECTION TABLE
VOUT
(V)
C1
(µF)
C5, C6
(µF)
C4
(pF)
L1
(µH)
R1
(kΩ)
R2
(kΩ)
0.8
22
22
22
1.0~2.2
33
100
1.2
22
22
22
1.0~2.2
100
100
1.5
22
22
22
1.0~2.2
150
100
1.8
22
22
22
1.0~3.3
200
100
2.5
22
22
22
1.5~3.3
316
100
3.3
22
22
22
1.5~4.7
450
100
FN7888 Rev 4.00
July 31, 2014
Page 3 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Pin Configuration
ISL8002, ISL8002A, ISL80019, ISL80019A
(8 LD 2x2 TDFN)
TOP VIEW
VIN
1
EN
2
MODE
3
PG
4
THERMAL
PAD
(GND)
PAD
PIN 9
8
PHASE
7
PGND
6
FB
5
COMP
Pin Descriptions
PIN #
PIN NAME
PIN DESCRIPTION
1
VIN
The input supply for the power stage of the PWM regulator and the source for the internal linear regulator that provides
bias for the IC. Place a minimum of 10µF ceramic capacitance from VIN to GND and as close as possible to the IC for
decoupling.
2
EN
Device enable input. When the voltage on this pin rises above 1.4V, the device is enabled. The device is disabled when
the pin is pulled to ground. When the device is disabled, a 100Ω resistor discharges the output through the PHASE pin.
See Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5 for details.
3
MODE
Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM
mode. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case the MODE pin is left
floating, however, it is not recommended to leave this pin floating.
4
PG
Power-good output is pulled to ground during the soft-start interval and also when the output voltage is below regulation
limits. There is an internal 5MΩ internal pull-up resistor on this pin.
5
COMP
COMP is the output of the error amplifier. When COMP is tied high to VIN, compensation is internal. When COMP is
connected with a series resistor and capacitor to GND, compensation is external. See “Loop Compensation Design” on
page 20 for more detail.
6
FB
Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. The output voltage is set by
an external resistor divider connected to FB. In addition, the power-good PWM regulator’s power-good and undervoltage
protection circuits use FB to monitor the output voltage.
7
PGND
Power and analog ground connections. Connect directly to the board GROUND plane.
8
PHASE
Power stage switching node for output voltage regulation. Connect to the output inductor. This pin is discharged by an
100Ω resistor when the device is disabled. See Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5 for details.
9
THERMAL PAD Power ground. This thermal pad provides a return path for the power stage and switching currents, as-well-as a thermal
(T-PAD)
path for removing heat from the IC to the board. Place thermal vias to the PGND plane in this pad.
FN7888 Rev 4.00
July 31, 2014
Page 4 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Functional Block Diagram
COMP
MODE
27pF
SOFTSoft
START
*
SHUTDOWN
200kΩ
+
VREF
BANDGAP
VIN
OSCILLATOR
+
EN
+
EAMP
COMP
-
-
P
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
SHUTDOWN
3pF
PHASE
N
HS DRIVER
+
PGND
FB
SLOPE
Slope
COMP
1.15*VREF
6kΩ
+
-
CSA
OV
+
+
OCP
-
0.85*VREF
+
UV
+
VIN
SKIP
5MΩ
PG
1ms
DELAY
-
NEG CURRENT
SENSING
ZERO-CROSS
SENSING
0.3V
SCP
+
100Ω
SHUTDOWN
* By default, when COMP is tied to VIN, the voltage loop is internally compensated with the 27pF and 200kΩ RC network.
Please see "COMP" pin in the “Pin Descriptions” table on Page 4 for more details.
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
FN7888 Rev 4.00
July 31, 2014
Page 5 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PACKAGE
Tape and Reel
(Pb-Free)
PKG.
DWG. #
TAPE AND REEL
QUANTITY
PART
MARKING
TECHNICAL
SPECIFICATIONS
TEMP. RANGE
(°C)
ISL8002IRZ-T
1000
002
2A, 1MHz
-40 to +85
8 Ld TDFN
L8.2x2C
ISL8002IRZ-T7A
250
002
2A, 1MHz
-40 to +85
8 Ld TDFN
L8.2x2C
ISL8002AIRZ-T
1000
02A
2A, 2MHz
-40 to +85
8 Ld TDFN
L8.2x2C
ISL8002AIRZ-T7A
250
02A
2A, 2MHz
-40 to +85
8 Ld TDFN
L8.2x2C
ISL80019IRZ-T
1000
019
1.5A, 1MHz
-40 to +85
8 Ld TDFN
L8.2x2C
ISL80019IRZ-T7A
250
019
1.5A, 1MHz
-40 to +85
8 Ld TDFN
L8.2x2C
ISL80019AIRZ-T
1000
19A
1.5A, 2MHz
-40 to +85
8 Ld TDFN
L8.2x2C
ISL80019AIRZ-T7A
250
19A
1.5A, 2MHz
-40 to +85
8 Ld TDFN
L8.2x2C
ISL8002FRZ-T
1000
02F
2A, 1MHz
-40 to +125
8 Ld TDFN
L8.2x2C
ISL8002FRZ-T7A
250
02F
2A, 1MHz
-40 to +125
8 Ld TDFN
L8.2x2C
ISL8002AFRZ-T
1000
2AF
2A, 2MHz
-40 to +125
8 Ld TDFN
L8.2x2C
ISL8002AFRZ-T7A
250
2AF
2A, 2MHz
-40 to +125
8 Ld TDFN
L8.2x2C
ISL80019FRZ-T
1000
19F
1.5A, 1MHz
-40 to +125
8 Ld TDFN
L8.2x2C
ISL80019FRZ-T7A
250
19F
1.5A, 1MHz
-40 to +125
8 Ld TDFN
L8.2x2C
ISL80019AFRZ-T
1000
9AF
1.5A, 2MHz
-40 to +125
8 Ld TDFN
L8.2x2C
ISL80019AFRZ-T7A
250
9AF
1.5A, 2MHz
-40 to +125
8 Ld TDFN
L8.2x2C
ISL8002EVAL1Z
Evaluation Board
ISL8002AEVAL1Z
Evaluation Board
ISL80019AEVAL1Z
Evaluation Board
ISL80019EVAL1Z
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8002, ISL8002A, ISL80019, ISL80019A. For more information on
MSL please see techbrief TB363.
FN7888 Rev 4.00
July 31, 2014
Page 6 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Absolute Maximum Ratings
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)
PHASE . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6V (DC) or 7V (20ms)
EN, COMP, PG, MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Thermal Resistance (Typical, Notes 4, 5)
JA (°C/W) JC (°C/W)
2x2 TDFN Package . . . . . . . . . . . . . . . . . . .
71
7
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
TJ = -40°C to +125°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply across the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
2.5
2.7
V
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising, no load
Falling, no load
Quiescent Supply Current
Shut Down Supply Current
IVIN
ISD
2.2
2.4
V
MODE = PFM (GND), FSW = 2MHz, no load at
the output
35
60
µA
MODE = PWM (VIN), FSW = 1MHz, no load at
the output
7
15
mA
MODE = PWM (VIN), FSW = 2MHz, no load at
the output
10
22
mA
MODE = PFM (GND), VIN = 5.5V, EN = low
5
10
µA
0.600
0.605
V
0.605
V
OUTPUT REGULATION
Feedback Voltage
VFB
0.595
TJ = -40°C to +125°C
0.589
VFB = 2.7V. TJ = -40°C to +125°C
-120
50
350
nA
Line Regulation
VIN = VO + 0.5V to 5.5V (minimal 2.7V)
TJ = -40°C to +125°C
-0.2
-0.05
0.1
%/V
Load Regulation
See Note 7
VFB Bias Current
IVFB
Soft-Start Ramp Time Cycle
< -0.2
%/A
1
ms
PROTECTIONS
Positive Peak Current Limit
IPLIMIT
2A application
1.5A application
Peak Skip Limit
ISKIP
Thermal Shutdown
FN7888 Rev 4.00
July 31, 2014
3.5
4
A
2.1
2.5
2.9
A
VIN = 3.6, VOUT = 1.8V (See “Applications
Information” on page 19 for more detail)
Zero Cross Threshold
Negative Current Limit
3
INLIMIT
Temperature rising
450
mA
-170
-70
30
mA
-2.3
-1.5
-1
A
150
°C
Page 7 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Electrical Specifications
TJ = -40°C to +125°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
Thermal Shutdown Hysteresis
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Temperature falling
25
°C
COMP tied VIN
40
µA/V
COMP with RC
120
µA/V
COMPENSATION
Error Amplifier Trans-Conductance
Trans-Resistance
RT
0.24
0.3
0.40
Ω
LX
P-Channel MOSFET ON-Resistance
VIN = 5V, IO = 200mA
N-Channel MOSFET ON-Resistance
VIN = 5V, IO = 200mA
LX Maximum Duty Cycle
LX Minimum On-Time
MODE = PWM (High) 1MHz
117
mΩ
86
mΩ
100
60
80
ns
OSCILLATOR
Nominal Switching Frequency
FSW
ISL8002, ISL80019
850
1000
1150
kHz
ISL8002A, ISL80019A
1700
2000
2300
kHz
0.3
V
2
ms
0.01
0.1
µA
110
115
120
%
80
85
PG
Output Low Voltage
1mA sinking current
Delay Time (Rising Edge)
0.5
PGOOD Delay Time (Falling Edge)
1
15
PG Pin Leakage Current
PG = VIN
OVP PG Rising Threshold
OVP PG Hysteresis
µs
5
UVP PG Rising Threshold
UVP PG Hysteresis
%
90
5
%
%
EN AND MODE LOGIC
Logic Input Low
0.4
Logic Input High
Logic Input Leakage Current
1.4
IMODE
Pulled up to 5.5V
V
V
5.5
8
µA
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Not tested in production. Characterized using evaluation board. Refer to Figures 12 through 14 load regulation diagrams. +105°C TA represents near
worst case operating point.
FN7888 Rev 4.00
July 31, 2014
Page 8 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
100
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves
70
60
50
40
0.0
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
40
0.0
2.0
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
100
70
50
40
0.0
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
0.2
0.4
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
60
40
0.0
2.0
100
90
90
80
80
EFFICIENCY (%)
100
70
50
40
0.0
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.2
0.4
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
FIGURE 8. EFFICIENCY vs LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FN7888 Rev 4.00
July 31, 2014
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
2.0
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
2.0
70
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
60
50
0.6
0.6
FIGURE 7. EFFICIENCY vs LOAD
FSW = 1MHz, VIN = 3.3V, MODE = PWM, TA = +25°C
FIGURE 6. EFFICIENCY vs LOAD
FSW = 1MHz, VIN = 3.3V, MODE = PFM, TA = +25°C
60
0.4
70
50
0.6
0.2
FIGURE 5. EFFICIENCY vs LOAD
FSW = 2MHz, VIN = 3.3V, MODE = PWM, TA = +25°C
100
60
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
60
50
FIGURE 4. EFFICIENCY vs LOAD
FSW = 2MHz, VIN = 3.3V, MODE = PFM, TA = +25°C
EFFICIENCY (%)
70
2.0
40
0.0
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
FIGURE 9. EFFICIENCY vs LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
Page 9 of 23
2.0
ISL8002, ISL8002A, ISL80019, ISL80019A
(Continued)
100
100
90
90
80
80
70
60
50
40
0.0
EFFICIENCY (%)
EFFICIENCY (%)
Typical Performance Curves
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
0.2
0.4
70
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
60
50
0.6
0.8
1.0
1.2
1.4
1.6
1.8
40
0.0
2.0
0.2
0.4
0.6
OUTPUT LOAD (A)
0.1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.4
AVERAGE
HIGH
LOW
-0.5
-0.6
0
1.0
1.5
1.6
1.8
-0.2
-0.3
-0.4
-0.6
2.0
AVERAGE
HIGH
LOW
6 SIGMA
0.5
0
LOAD CURRENT
1.0
1.5
FIGURE 13. LOAD REGULATION, TA = +105°C, 3.3VIN, 0.6VOUT, 1MHz
0.0
LOAD REGULATION (%)
-0.1
-0.2
-0.3
AVERAGE
HIGH
LOW
-0.5
6 SIGMA
-0.6
0
0.5
1.0
1.5
2.0
LOAD CURRENT
FIGURE 14. LOAD REGULATION, TA = +105°, 5.5VIN, 0.6VOUT, 1MHz
FN7888 Rev 4.00
July 31, 2014
2.0
LOAD CURRENT
FIGURE 12. LOAD REGULATION, TA = +105°C, 2.7VIN, 0.6VOUT, 1MHz
-0.4
2.0
-0.1
-0.5
6 SIGMA
0.5
1.4
FIGURE 11. EFFICIENCY vs LOAD
FSW = 1MHz, VIN = 5V, MODE = PWM, TA = +25°C
LOAD REGULATION (%)
LOAD REGULATION (%)
FIGURE 10. EFFICIENCY vs LOAD
FSW = 1MHz, VIN = 5V, MODE = PFM, TA = +25°C
0.8
1.0
1.2
OUTPUT LOAD (A)
Page 10 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Typical Performance Curves
(Continued)
1.230
0.925
OUTPUT VOLTAGE (V)
0.920
0.915
0.910
0.905
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
2.0
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
1.805
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.510
0.2
1.810
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
1.515
1.505
1.500
1.800
1.795
1.790
1.785
1.495
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
1.780
0.0
2.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
OUTPUT LOAD (A)
FIGURE 17. VOUT REGULATION vs LOAD,
FSW = 2MHz, VOUT = 1.5V, TA = +25°C
FIGURE 18. VOUT REGULATION vs LOAD,
FSW = 2MHz, VOUT = 1.8V, TA = +25°C
3.335
2.505
2.495
2.490
2.485
5VIN PFM MODE
5VIN PWM MODE
3.330
OUTPUT VOLTAGE (V)
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
2.500
OUTPUT VOLTAGE (V)
1.210
FIGURE 16. VOUT REGULATION vs LOAD,
FSW = 2MHz, VOUT = 1.2V, TA = +25°C
1.520
3.325
3.320
3.315
3.310
2.480
2.475
0.0
1.215
1.200
0.0
2.0
FIGURE 15. VOUT REGULATION vs LOAD,
FSW = 2MHz, VOUT = 0.9V, TA = +25°C
1.490
0.0
1.220
1.205
0.900
0.895
0.0
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
1.225
OUTPUT VOLTAGE (V)
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
0.2
0.4
0.6
0.8
1.0
1.2
1.4
OUTPUT LOAD (A)
FIGURE 19. VOUT REGULATION vs LOAD,
FSW = 2MHz, VOUT = 2.5V, TA = +25°C
FN7888 Rev 4.00
July 31, 2014
1.6
1.8
2.0
3.305
0.0
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
FIGURE 20. VOUT REGULATION vs LOAD,
FSW = 2MHz, VOUT = 3.3V, TA = +25°C
Page 11 of 23
2.0
ISL8002, ISL8002A, ISL80019, ISL80019A
Typical Performance Curves
(Continued)
LX 5V/DIV
LX 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 1V/DIV
VEN 2V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 21. START-UP AT NO LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FIGURE 22. START-UP AT NO LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
LX 5V/DIV
LX 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 2V/DIV
VEN 2V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 23. SHUTDOWN AT NO LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FIGURE 24. SHUTDOWN AT NO LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
LX 5V/DIV
LX 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 2V/DIV
PG 5V/DIV
VEN 2V/DIV
PG 5V/DIV
1ms/DIV
FIGURE 25. START-UP AT 2A LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
FN7888 Rev 4.00
July 31, 2014
1ms/DIV
FIGURE 26. SHUTDOWN AT 2A LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
Page 12 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Typical Performance Curves
(Continued)
LX 5V/DIV
LX 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 2V/DIV
PG 5V/DIV
VEN 2V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 27. START-UP AT 2A LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FIGURE 28. SHUTDOWN AT 2A LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
VEN 5V/DIV
VEN 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 1A/DIV
PG 5V/DIV
IL 1A/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 29. START-UP AT 1.5A LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
FIGURE 30. SHUTDOWN AT 1.5A LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
VEN 5V/DIV
VEN 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 1A/DIV
PLACEHOLDER
PG 5V/DIV
IL 1A/DIV
PG 5V/DIV
1ms/DIV
FIGURE 31. START-UP AT 1.5A LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FN7888 Rev 4.00
July 31, 2014
1ms/DIV
FIGURE 32. SHUTDOWN AT 1.5A LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
Page 13 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Typical Performance Curves
(Continued)
VIN 5V/DIV
VIN 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 1A/DIV
IL 1A/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 33. START-UP VIN AT 2A LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FIGURE 34. START-UP VIN AT 2A LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
VIN 5V/DIV
VIN 5V/DIV
IL 1A/DIV
IL 1A/DIV
VOUT 1V/DIV
VOUT 1V/DIV
PG 5V/DIV
1ms/DIV
PG 5V/DIV
1ms/DIV
FIGURE 35. SHUTDOWN VIN AT 2A LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FIGURE 36. SHUTDOWN VIN AT 2A LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
LX 5V/DIV
LX 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 37. START-UP VIN AT NO LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FN7888 Rev 4.00
July 31, 2014
500µs/DIV
FIGURE 38. START-UP VIN AT NO LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
Page 14 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Typical Performance Curves
(Continued)
LX 5V/DIV
LX 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
100ms/DIV
50ms/DIV
FIGURE 39. SHUTDOWN VIN AT NO LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FIGURE 40. SHUTDOWN VIN AT NO LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
LX 1V/DIV
10ns/DIV
LX 1V/DIV
10ns/DIV
FIGURE 41. JITTER AT NO LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
FIGURE 42. JITTER AT FULL LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
LX 5V/DIV
LX 5V/DIV
VOUT 20mV/DIV
VOUT 10mV/DIV
IL 0.5A/DIV
IL 0.5A/DIV
50ms/DIV
FIGURE 43. STEADY STATE AT NO LOAD
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FN7888 Rev 4.00
July 31, 2014
500ns/DIV
FIGURE 44. STEADY STATE AT NO LOAD
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
Page 15 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Typical Performance Curves
(Continued)
VOUT RIPPLE 50mV/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
200µs/DIV
IL 1A/DIV
200µs/DIV
FIGURE 45. LOAD TRANSIENT
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FIGURE 46. LOAD TRANSIENT
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
LX 5V/DIV
VOUT 0.5V/DIV
IL 1A/DIV
IL 2A/DIV
VOUT 1V/DIV
PG 5V/DIV
PG 5V/DIV
5µs/DIV
500µs/DIV
FIGURE 47. OUTPUT SHORT-CIRCUIT
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FIGURE 48. OVERCURRENT PROTECTION
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
LX 5V/DIV
LX 5V/DIV
675mA MODE TRANSITION, COMPLETELY
ENTER TO PWM AT 770mA
BACK TO PFM AT 121mA
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 2A/DIV
IL 1A/DIV
2µs/DIV
FIGURE 49. PFM TO PWM TRANSITION
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
FN7888 Rev 4.00
July 31, 2014
2µs/DIV
FIGURE 50. PWM TO PFM TRANSITION
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +25°C
Page 16 of 23
ISL8002, ISL8002A, ISL80019, ISL80019A
Typical Performance Curves
(Continued)
LX 5V/DIV
IL 2A/DIV
VOUT 0.5V/DIV
VOUT 2V/DIV
PG 2V/DIV
PG 5V/DIV
10µs/DIV
FIGURE 51. OVERVOLTAGE PROTECTION
FSW = 2MHz, VIN = 5V, MODE = PFM, TA = +25°C
1ms/DIV
FIGURE 52. OVER-TEMPERATURE PROTECTION
FSW = 2MHz, VIN = 5V, MODE = PWM, TA = +163°C
Theory of Operation
The device is a step-down switching regulator optimized for battery
powered applications. It operates at high switching frequency (1MHz
or 2MHz), which enables the use of smaller inductors resulting in
small form factor, while also providing excellent efficiency. Further,
at light loads while in PFM mode, the regulator reduces the
switching frequency, thereby minimizing the switching loss and
maximizing battery life. The quiescent current when the output is
not loaded is typically only 35µA. The supply current is typically only
5µA when the regulator is shut down.
PWM Control Scheme
Pulling the MODE pin HI (>2.5V) forces the converter into PWM
mode, regardless of output current. The device employs the
current-mode pulse-width modulation (PWM) control scheme for
fast transient response and pulse-by-pulse current limiting. See
“Functional Block Diagram” on page 5. The current loop consists of
the oscillator, the PWM comparator, current sensing circuit and the
slope compensation for the current loop stability. The slope
compensation is 900mV/Ts, which changes with frequency. The
gain for the current sensing circuit is typically 300mV/A. The control
reference for the current loops comes from the error amplifier's
(EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-FET and turn on the N-Channel MOSFET. The N-FET stays on until
the end of the PWM cycle. Figure 53 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate
the sum of the slope compensation ramp and the current-sense
amplifier’s CSA output.
FN7888 Rev 4.00
July 31, 2014
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 53. PWM OPERATION WAVEFORMS
The output voltage is regulated by controlling the VEAMP voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 27pF and 200kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 1.6V.
PFM Mode
Pulling the MODE pin LO (