DATASHEET
ISL8016
FN7616
Rev 1.00
May 5, 2011
6A Low Quiescent Current High Efficiency Synchronous Buck Regulator
The ISL8016 is a high efficiency, monolithic, synchronous
step-down DC/DC converter that can deliver up to 6A
continuous output current from a 2.7V to 5.5V input supply.
The output voltage is adjustable from 0.6V to VIN. With an
adjustable current limit, reverse current protection, pre-bias
start and over temperature protection the ISL8016 offers a
highly robust power solution. It uses current control
architecture to deliver fast transient response and excellent
loop stability.
Features
The ISL8016 integrates a pair of low ON-resistance P-Channel
and N-Channel internal MOSFETs to maximize efficiency and
minimize external component count. 100% duty-cycle
operation allows less than 200mV dropout at 6A output
current. Adjustable frequency and synchronization allow the
ISL8016 to be used in applications requiring low noise.
Paralleling capability with phase interleaving allows the IC to
support >6A output current while offering reduced input and
output noise.
• Current Sharing Capable
The ISL8016 can be configured for discontinuous or forced
continuous operation at light load. Forced continuous operation
reduces noise and RF interference while discontinuous mode
provides high efficiency by reducing switching losses at light
loads.
The ISL8016 is offered in a space saving 20 Ld 3x4 QFN lead
free package with exposed pad lead frames for excellent
thermal performance. The complete converter occupies less
than 0.15in2 area.
Various fixed output voltages are available upon request. See
Ordering Information on page 2 for more detail.
• High Efficiency Synchronous Buck Regulator with up to 97%
Efficiency
• 1% Reference Accuracy Over-Temperature/Load/Line
• Fixed Output Voltage Option
• ±10% Output Voltage Margining
• Adjustable Current Limit
• Start-up with Pre-Biased Output
• Internal Soft-Start - 1ms or Adjustable, Internal/External
Compensation
• Soft-Stop Output Discharge During Disabled
• Adjustable Frequency from 500kHz to 4MHz - Default at
1MHz
• External Synchronization up to 4MHz - Master to Slave Phase
Shifting Capability
• Peak current limiting, Hiccup Mode Short Circuit Protection
and Over-Temperature Protection‘
Applications
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Plug-in DC/DC Modules for Routers and Switchers
• Portable Instruments
• Test and Measurement Systems
• Li-ion Battery Powered Devices
100
EFFICIENCY (%)
95
90
3.3VOUT PFM
85
3.3VOUT PWM
80
75
70
0.0
1.0
2.0
3.0
IOUT (A)
4.0
5.0
6.0
FIGURE 1. EFFICIENCY T = +25°C VIN = 5V
FN7616 Rev 1.00
May 5, 2011
Page 1 of 22
ISL8016
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
OUTPUT VOLTAGE (V)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL8016IRAJZ
016A
Adjustable
-40 to +85
20 Ld 3x4 QFN
L20.3x4
ISL8016IR12Z
016W
1.2V
-40 to +85
20 Ld 3x4 QFN
L20.3x4
ISL8016IR15Z
016B
1.5V
-40 to +85
20 Ld 3x4 QFN
L20.3x4
ISL8016IR18Z
016C
1.8V
-40 to +85
20 Ld 3x4 QFN
L20.3x4
ISL8016IR25Z
016F
2.5V
-40 to +85
20 Ld 3x4 QFN
L20.3x4
ISL8016IR33Z
016N
3.3V
-40 to +85
20 Ld 3x4 QFN
L20.3x4
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8016. For more information on MSL please see techbrief TB363.
Pin Configuration
PGND
PGND
SGND
VFB
ISL8016
(20 LD QFN)
TOP VIEW
20
19
18
17
PGND
1
16
COMP
PHASE
2
15
SS
PHASE
3
14
ISET
PAD
FN7616 Rev 1.00
May 5, 2011
VIN
5
12
FS
VIN
6
11
EN
7
8
9
10
SYNCIN
VSET
SYNCOUT
13
PG
4
VIN
PHASE
Page 2 of 22
ISL8016
Pin Descriptions
PIN
SYMBOL
1, 19, 20
PGND
Power ground.
2, 3, 4
PHASE
Switching node connection. Connect to one terminal of the inductor.
5, 6, 7
VIN
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.
8
PG
Power-good is an open-drain output. Use 10k to 100k pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms from the output reaching regulation.
9
SYNCOUT
This pin outputs a 250µA current source that is turned on at the rising edge of the internal clock or
SYNCIN. When SYNCOUT voltage reaches 1V, a reset circuit will activate and discharge SYNCOUT to 0V.
SYNCOUT is held at 0V in PFM light load to reduce quiescent current.
10
SYNCIN
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1M pull-down resistor to prevent an undefined logic state if SYNCIN
is floating.
11
EN
Regulator enable pin. Enables the output when driven to high. Shuts down the chip and discharges the
output capacitor when driven to low. There is an internal 1M pull-down resistor to prevent an
undefined logic state in case of EN pin float.
12
FS
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
13
VSET
VSET is the output margining setting of the regulators. Connect to SGND for -10%, keep it floating for
no margining, and connect to VIN for +10%.
14
ISET
ISET is the peak output current limit and SKIP current limit setting of the regulators. Connect to SGND
for 2A, to VIN for 4A, and keep it floating for 6A.
15
SS
16, 17
COMP, VFB
18
SGND
Signal ground.
EPAD
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many
vias as possible under the pad connecting to the system GND plane for optimal thermal performance.
FN7616 Rev 1.00
May 5, 2011
DESCRIPTION
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor
from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if the FS resistor is used. If internal compensation is used
(FS = VIN), the comp pin should be tied to SGND. The output voltage is set by an external resistor divider
connected to VFB. With a properly selected divider, the output voltage can be set to any voltage
between VIN and the 0.6V reference. While internal compensation offers a solution for many typical
applications, an external compensation network may offer improved performance for some designs.
In addition to regulation, VFB is also used to determine the state of PG.
Short VFB to OUTPUT when using one of the available fixed VOUT options.
Page 3 of 22
ISL8016
Typical Application Diagrams
INPUT
2.7V TO 5.5V
VIN
EN
C1
2x22µF
PHASE
C2
2x47µF
ISL8016
R1
100k
OUTPUT
1.8V/6A
L
1.0µH
R2
200k
PGND
C3*
10pF
PG
SYNCIN
SYNCOUT
VIN
FS
ISET
VSET
SGND
R3
100k
VFB
COMP
SS
* C3 is optional. Recommend
putting a placeholder for it. Check
loop analysis first before use.
FIGURE 2. TYPICAL APPLICATION DIAGRAM - SINGLE CHIP 6A
TABLE 1. COMPONENT VALUE SELECTION
VOUT
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
3.6V
C1
44µF
44µF
44µF
44µF
44µF
44µF
44µF
C2 (or C8)
2x47µF
2x47µF
2x47µF
2x47µF
2x47µF
2x47µF
2x47µF
C3 (or C5)
10pF
10pF
10pF
10pF
10pF
10pF
10pF
L1 (or L2)
0.47~1µH
0.47~1µH
0.47~1µH
0.68~1.5µH
0.68~1.5µH
1~2.2µH
1~2.2µH
R2 (or R5)
33k
100k
150k
200k
316k
450k
500k
R3 (or R6)
100k
100k
100k
100k
100k
100k
100k
FN7616 Rev 1.00
May 5, 2011
Page 4 of 22
ISL8016
INPUT
2.7V TO 5.5V
VIN
PHASE
C2
2 x 47µF
EN
C1
47µF
R1
100k
PG
SYNCOUT
R4
196k
R3
100k
SGND
ISET
VSET
COMP
SS
VIN
EN
PG
C4
470pF
R3
150k
C6
22nF
C7
47µF
C3*
10pF
VFB
FS
INPUT 2.7V TO 5.5V
R2
200k
ISL8016
(MASTER) PGND
SYNCIN
VIN
OUTPUT
1.8V/12A
L1
1.0µH
PHASE
ISL8016
(SLAVE)
C5
10pF
L2
1.0µH
C8
2 x 47µF
PGND
SYNCOUT
SYNCIN
FS
C13
100pF
R5
249k
ISET
VSET
SS
SGND
VFB
COMP
* C3 is optional. Recommend
putting a placeholder for it. Check
loop analysis first before use.
FIGURE 3. TYPICAL APPLICATION DIAGRAM - MULTI CHIP CONFIGURATION 12A
FN7616 Rev 1.00
May 5, 2011
Page 5 of 22
ISL8016
Block Diagram
COMP
SS
SHUTDOWN
FS
SYNCIN
SYNCOUT
55pF
Soft
SOFT
START
SHUTDOWN
168k
250µA
VDD
+
BANDGAP
VREF
+
EN
+
EAMP
VIN
OSCILLATOR
COMP
-
-
P
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
VSET
3pF
+
PHASE
LS
DRIVER
N
PGND
VFB
SLOPE
Slope
COMP
6k
0.8V
+
-
CSA
-
+
OV
+
OCP
-
0.85*VREF
+
UV
ISET
ISET
THRESHOLD
+
SKIP
-
PG
1ms
DELAY
NEG CURRENT
SENSING
SGND
ZERO-CROSS
SENSING
0.1V
SCP
+
100
SHUTDOWN
FIGURE 4. FUNCTIONAL BLOCK DIAGRAM
FN7616 Rev 1.00
May 5, 2011
Page 6 of 22
ISL8016
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, ISET, PG, SYNCOUT, SYNCIN VFB, VSET . . . . . . . -0.3V to VIN+0.3V
PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1500V
Latch Up (Tested per JESD-78A; Class 2, Level A) . . . . . .100mA @ +85°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
3x4 QFN Package (Notes 4, 5) . . . . . . . . . .
42
5
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 6A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Analog Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions
and the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical
values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
2.5
2.7
V
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising, no load
Falling, no load
Quiescent Supply Current
Shut Down Supply Current
IVIN
ISD
2.2
2.4
V
SYNCIN = GND, no load at the output
70
µA
SYNCIN = GND, no load at the output and no
switches switching
70
90
µA
SYNCIN = VIN, FS = 1MHz, no load at the output
8
15
mA
SYNCIN = GND, VIN = 5.5V, EN = low
5
7
µA
OUTPUT REGULATION
Reference Voltage - ISL8016IRAJZ
VREF
VSET = VIN
0.651
0.660
0.669
V
VSET = FLOAT
0.594
0.600
0.606
V
VSET = SGND
0.531
0.540
0.549
V
Output Voltage - ISL8016IR12Z
VVFB
VSET = FLOAT
1.188
1.200
1.212
V
Output Voltage - ISL8016IR15Z
VVFB
VSET = FLOAT
1.485
1.500
1.515
V
Output Voltage - ISL8016IR18Z
VVFB
VSET = FLOAT
1.782
1.800
1.818
V
Output Voltage - ISL8016IR25Z
VVFB
VSET = FLOAT
2.475
2.500
2.525
V
Output Voltage - ISL8016IR33Z
VVFB
VSET = FLOAT
3.266
3.300
3.333
V
Output Voltage Margining
VVFB
VSET = VIN, Percent of OUTPUT changed
9.5
10
10.5
%
-10.5
-10
-9.5
%
VSET = SGND, Percent of OUTPUT changed
VFB Bias Current - ISL8016IRAJZ
IVFB
VFB = 0.75V
Fixed Output VFB Bias Current - ISL8016IRXXZ
IVFB
VSET = FLOAT, VFB = 10% above OUTPUT
Line Regulation
VIN = VO + 0.5V to 5.5V (minimal 2.7V)
Soft-Start Ramp Time Cycle
SS = SGND
Soft-Start Charging Current
FN7616 Rev 1.00
May 5, 2011
ISS
VSS = 0.1V
1.4
0.1
µA
6
µA
0.2
%/V
1
ms
1.8
2.2
µA
Page 7 of 22
ISL8016
Analog Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions
and the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical
values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
OVERCURRENT PROTECTION
Current Limit Blanking Time
tOCON
17
Clock
pulses
Overcurrent and Auto Restart Period
tOCOFF
8
SS cycle
Positive Peak Current Limit
IPLIMIT
Peak Skip Limit
ISKIP
ISET = FLOAT
7.7
9.5
11.5
A
ISET = VIN
5.5
6.5
8.0
A
ISET = SGND
3
4.0
5
A
ISET = FLOAT
1.6
2
2.4
A
ISET = VIN
1.0
1.35
1.6
A
ISET = SGND
Zero Cross Threshold
Negative Current Limit
0.85
-300
INLIMIT
-4.25
-3
A
300
mA
-1.75
A
COMPENSATION
Error Amplifier Trans-Conductance
Trans-Resistance
FS = VIN
100
µA/V
FS with Resistor
200
µA/V
RT
0.117
0.138
0.16
PHASE
P-Channel MOSFET ON-Resistance
VIN = 5V, IO = 200mA
31
45
m
VIN = 2.7V, IO = 200mA
44
55
m
N-Channel MOSFET ON-Resistance
VIN = 5V, IO = 200mA
19
35
m
VIN = 2.7V, IO = 200mA
25
50
m
PHASE Maximum Duty Cycle
100
PHASE Minimum On-Time
SYNCIN = High
140
ns
OSCILLATOR
Nominal Switching Frequency
Fsw
FS = VIN
800
1000
1200
kHz
FS with RS = 402k
450
525
600
kHz
FS with RS = 42.4k
3300
3900
4500
kHz
0.70
0.75
0.80
V
SYNCIN Logic Low to High Transition Range
SYNCIN Hysteresis
0.15
SYNCIN Logic Input Leakage Current
SYNCOUT Charging Current
VIN = 3.6V
ISO
PWM
210
PFM
V
3.6
5
µA
250
290
µA
0
SYNCOUT Voltage Low
µA
0.3
V
0.3
V
1
2
ms
PG Pin Leakage Current
0.01
0.1
µA
OVP PG Rising Threshold
0.80
PG
Output Low Voltage
Delay Time (Rising Edge)
UVP PG Rising Threshold
FN7616 Rev 1.00
May 5, 2011
0.5
80
85
V
90
%
Page 8 of 22
ISL8016
Analog Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions
and the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical
values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
UVP PG Hysteresis
5
%
PGOOD Delay Time (Falling Edge)
7
µs
ISET, VSET
Logic Input Low
Logic Input Float
0.5
Logic Input High
0.9
Logic Input Leakage Current
0.4
V
0.8
V
V
0.1
1
µA
0.4
V
EN
Logic Input Low
Logic Input High
0.9
V
EN Logic Input Leakage Current
0.1
1
µA
Thermal Shutdown
150
°C
Thermal Shutdown Hysteresis
25
°C
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7616 Rev 1.00
May 5, 2011
Page 9 of 22
ISL8016
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V,
100
100
95
95
2.5VOUT
90
2.5VOUT
85
1.8VOUT
EFFICIENCY (%)
EFFICIENCY (%)
EN = 3.3V, SYNCIN = VIN, L = 1.0µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 6A.
1.5VOUT
80
1.2VOUT
75
90
1.2VOUT
80
75
70
0.0
1.0
2.0
3.0
IOUT (A)
4.0
5.0
70
0.0
6.0
FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3VIN PWM)
0.3
0.6
0.9
IOUT (A)
1.2
1.5
1.8
FIGURE 6. EFFICIENCY vs LOAD (1MHz 3.3VIN PFM)
100
100
3.3VOUT
95
3.3VOUT
95
90
EFFICIENCY (%)
EFFICIENCY (%)
1.5VOUT
1.8VOUT
85
2.5VOUT
1.8VOUT
85
1.5VOUT
1.2VOUT
80
75
90
85
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
80
75
70
0.0
1.0
2.0
3.0
IOUT (A)
4.0
5.0
70
0.0
6.0
FIGURE 7. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
0.3
0.6
0.9
IOUT (A)
1.2
1.5
1.8
FIGURE 8. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
1.8
1.84
1.5
1.83
5VIN PWM MODE
1.82
3.3VIN PWM MODE
0.9
VOUT (V)
PD (W)
1.2
0.6
1.80
0.3
1.79
0
0A LOAD
3A LOAD
1.81
6A LOAD
0.0
1.0
2.0
3.0
IOUT (A)
4.0
5.0
FIGURE 9. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V)
FN7616 Rev 1.00
May 5, 2011
6.0
1.78
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
FIGURE 10. VOUT REGULATION vs VIN (PWM VOUT = 1.8V)
Page 10 of 22
5.5
ISL8016
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V,
1.84
1.24
1.83
1.23
1.82
1.22
1.81
3A LOAD
VOUT (V)
VOUT (V)
EN = 3.3V, SYNCIN = VIN, L = 1.0µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
0A LOAD
3.3VIN PWM MODE
3.3VIN PFM MODE
1.21
1.80
1.20
1.79
1.19 5VIN PWM MODE
5VIN PFM MODE
6A LOAD
1.78
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
1.18
0.0
5.5
FIGURE 11. VOUT REGULATION vs VIN (PFM VOUT = 1.8V)
1.82
5VIN PWM MODE
1.51
VOUT (V)
VOUT (V)
1.52
3.3VIN PFM MODE
1.50
5.0
6.0
3.3VIN PWM MODE
5VIN PWM MODE
3.3VIN PFM MODE
1.81
1.80
5VIN PFM MODE
1.49
1.0
2.0
3.0
IOUT (A)
5VIN PFM MODE
1.79
4.0
5.0
1.78
0.0
6.0
FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V)
1.0
2.0
3.0
IOUT (A)
4.0
5.0
6.0
FIGURE 14. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)
3.37
2.54
3.36
2.53
3.3VIN PWM MODE
5VIN PWM MODE
3.35
5VIN PWM MODE
VOUT (V)
2.52
VOUT (V)
4.0
1.83
3.3VIN PWM MODE
3.3VIN PFM MODE
3.34
3.33
2.50
5VIN PFM MODE
2.49
2.48
0.0
3.0
IOUT (A)
1.84
1.53
2.51
2.0
FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)
1.54
1.48
0.0
1.0
1.0
2.0
3.0
IOUT (A)
3.32
4.0
5.0
FIGURE 15. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V)
FN7616 Rev 1.00
May 5, 2011
5VIN PFM MODE
6.0
3.31
0.0
1.0
2.0
3.0
IOUT (A)
4.0
5.0
FIGURE 16. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)
Page 11 of 22
6.0
ISL8016
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V,
EN = 3.3V, SYNCIN = VIN, L = 1.0µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
PHASE 2V/DIV
PHASE 2V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 1A/DIV
FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PWM)
IL 1A/DIV
FIGURE 18. STEADY STATE OPERATION AT NO LOAD (PFM)
PHASE 2V/DIV
VOUT RIPPLE 50mV/DIV
IL 2A/DIV
IL 2A/DIV
VOUT RIPPLE 20mV/DIV
FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD
FIGURE 20. LOAD TRANSIENT (PWM)
VOUT RIPPLE 50mV/DIV
EN 2V/DIV
IL 52A/DIV
VOUT 1V/DIV
IL 1A/DIV
PG 5V/DIV
FIGURE 21. LOAD TRANSIENT (PFM)
FN7616 Rev 1.00
May 5, 2011
FIGURE 22. SOFT-START WITH NO LOAD (PWM)
Page 12 of 22
ISL8016
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V,
EN = 3.3V, SYNCIN = VIN, L = 1.0µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
EN 2V/DIV
EN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 1A/DIV
IL 1A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 23. SOFT-START AT NO LOAD (PFM)
FIGURE 24. SOFT-START WITH PRE-BIASED 1V
EN 2V/DIV
EN 2V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 1A/DIV
IL 2A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 25. SOFT-START AT FULL LOAD
FIGURE 26. SOFT-DISCHARGE SHUTDOWN
PHASE 5V/DIV
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 2A/DIV
IL 0.5A/DIV
SYNC 5V/DIV
FIGURE 27. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 2MHz
FN7616 Rev 1.00
May 5, 2011
SYNC 5V/DIV
FIGURE 28. STEADY STATE OPERATION AT FULL LOAD WITH
FREQUENCY = 2MHz
Page 13 of 22
ISL8016
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V,
EN = 3.3V, SYNCIN = VIN, L = 1.0µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 6A. (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 2A/DIV
IL 0.2A/DIV
SYNC 5V/DIV
SYNC 5V/DIV
FIGURE 29. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 4MHz
FIGURE 30. STEADY STATE OPERATION AT FULL LOAD (PWM) WITH
FREQUENCY = 4MHz
PHASE 5V/DIV
PHASE 5V/DIV
IL 2A/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 5A/DIV
PG 5V/DIV
FIGURE 31. OUTPUT SHORT CIRCUIT
FN7616 Rev 1.00
May 5, 2011
PG 5V/DIV
FIGURE 32. OUTPUT SHORT CIRCUIT RECOVERY
Page 14 of 22
ISL8016
Theory of Operation
VEAMP
The ISL8016 is a step-down switching regulator optimized for
battery-powered handheld applications. The regulator operates at
1MHz fixed default switching frequency when FS is connected to VIN.
By connecting a resistor from FS to SGND, the operating frequency
may be adjusted from 500kHz to 4MHz. Unless forced, PWM is
chosen (SYNCIN pulled HI), the regulator will allow PFM operation
and reduce switching frequency at light loading to maximize
efficiency. In this condition, no load quiescent is typically 70µA.
VCSA
DUTY
CYCLE
IL
PWM Control Scheme
VOUT
Pulling the SYNCIN high (>0.8V) forces the converter into PWM
mode, regardless of output current. The ISL8016 employs the
current-mode pulse-width modulation (PWM) control scheme for fast
transient response and pulse-by-pulse current limiting. Figure 4
shows the block diagram. The current loop consists of the oscillator,
the PWM comparator, current sensing circuit and the slope
compensation for the current loop stability. The slope compensation
is 360mV/Ts. Current sense resistance, Rt, is typically 0.138V/A. The
control reference for the current loop comes from the error
amplifier's (EAMP) output.
FIGURE 33. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNCIN pin LO (
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