DATASHEET
ISL8018
FN7889
Rev 0.00
September 30, 2015
8A Low Quiescent Current High Efficiency Synchronous Buck Regulator
Features
The ISL8018 is a high efficiency, monolithic, synchronous
step-down DC/DC converter that can deliver up to 8A
continuous output current from a 2.7V to 5.5V input supply.
The output voltage is adjustable from 0.6V to VIN. With an
adjustable current limit, reverse current protection, prebias
start and over-temperature protection, the ISL8018 offers a
highly robust power solution. It uses current control
architecture to deliver fast transient response and excellent
loop stability.
• High efficiency synchronous buck regulator with up to 97%
efficiency
• ±10% output voltage margining
• Adjustable current limit
• Start-up with prebiased output
• Internal soft-start - 1ms or adjustable, internal/external
compensation
The ISL8018 integrates a pair of low ON-resistance P-channel
and N-channel internal MOSFETs to maximize efficiency and
minimize external component count. 100% duty-cycle
operation allows less than 250mV dropout at 8A output
current. Adjustable frequency and synchronization allow the
ISL8018 to be used in applications requiring low noise.
• Soft-stop output discharge during disabled
• Adjustable frequency from 500kHz to 4MHz - default at
1MHz
• External synchronization up to 4MHz - master to slave phase
shifting capability
The ISL8018 can be configured for discontinuous or forced
continuous operation at light load. Forced continuous operation
reduces noise and RF interference while discontinuous mode
provides high efficiency by reducing switching losses at light
loads.
• Peak current limiting, hiccup mode short-circuit protection
and over-temperature protection
Applications
• DC/DC POL modules
The ISL8018 is offered in a space saving 20 Ld 3x4 QFN lead
free package with exposed pad lead frames for excellent
thermal performance. The complete converter occupies less
than 96.8mm2 area.
• µC/µP, FPGA and DSP power
• Plug-in DC/DC modules for routers and switchers
• Portable instruments
See Ordering Information on page 2 for more detail.
• Test and measurement systems
Related Literature
• Li-ion battery powered devices
• UG052 “ISL8018DEMO1Z Demonstration Board User Guide”
• UG053 “ISL8018EVAL3Z Evaluation Board User Guide”
100
95
EFFICIENCY (%)
3.3VOUT PFM
90
3.3VOUT PWM
85
80
75
70
0
1
2
3
4
5
6
7
8
IOUT (A)
FIGURE 1. EFFICIENCY T = +25°C VIN = 5V
FN7889 Rev 0.00
September 30, 2015
Page 1 of 21
ISL8018
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
ISL8018IRAJZ
018A
ISL8018EVAL3Z
Evaluation Board
ISL8018DEMO1Z
Demonstration Board
OUTPUT VOLTAGE
(V)
TEMP. RANGE
(°C)
Adjustable
-40 to +85
PACKAGE
(RoHS Compliant)
20 Ld 3x4 QFN
PKG.
DWG. #
L20.3x4
NOTES:
1. Add “-T” suffix for 6k units or “-T7A” suffix for 250 units Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8018. For more information on MSL please see techbrief TB363.
Pin Configuration
PGND
PGND
SGND
VFB
ISL8018
(20 LD QFN)
TOP VIEW
20
19
18
17
PGND
1
16
COMP
PHASE
2
15
SS
PHASE
3
14
ISET
PAD
FN7889 Rev 0.00
September 30, 2015
VIN
5
12
FS
VIN
6
11
EN
7
8
9
10
SYNCIN
VSET
SYNCOUT
13
PG
4
VIN
PHASE
Page 2 of 21
ISL8018
Pin Descriptions
PIN
SYMBOL
1, 19, 20
PGND
Power ground.
2, 3, 4
PHASE
Switching node connection. Connect to one terminal of the inductor.
5, 6, 7
VIN
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.
8
PG
Power-good is an open-drain output. Use 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms from the output reaching regulation.
9
SYNCOUT
This pin outputs a 250µA current source that is turned on at the rising edge of the internal clock or
SYNCIN. When SYNCOUT voltage reaches 0.8V, a reset circuit will activate and discharge SYNCOUT to
0V. SYNCOUT is held at 0V in PFM light load to reduce quiescent current.
10
SYNCIN
Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state if SYNCIN
is floating.
11
EN
Regulator enable pin. Enables the output when driven to high. Shuts down the chip and discharges the
output capacitor when driven to low.
12
FS
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
13
VSET
VSET is the output margining setting of the regulators. Connect to SGND for -10%, keep it floating for
no margining and connect to VIN for +10%.
14
ISET
ISET is the peak output current limit and skip current limit setting of the regulators. Connect to SGND
for 3A, to VIN for 5A and keep it floating for 8A.
15
SS
16, 17
COMP, VFB
18
SGND
Signal ground.
EPAD
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many
vias as possible under the pad connecting to the system GND plane for optimal thermal performance.
FN7889 Rev 0.00
September 30, 2015
DESCRIPTION
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor
from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if the FS resistor is used. If internal compensation is used
(FS = VIN), the comp pin should be tied to SGND. The output voltage is set by an external resistor divider
connected to VFB. With a properly selected divider, the output voltage can be set to any voltage
between VIN and the 0.6V reference. While internal compensation offers a solution for many typical
applications, an external compensation network may offer improved performance for some designs.
In addition to regulation, VFB is also used to determine the state of PG.
Page 3 of 21
ISL8018
Typical Application Diagrams
INPUT
VIN
EN
C1
2x22µF
OUTPUT
1.8V/8A
L
1µH
2.7V TO 5.5V
PHASE
C2
2x47µF
ISL8018
R1
100k
R2
200k
PGND
C3*
15pF
PG
SYNCIN
SYNCOUT
VIN
FS
ISET
VSET
SGND
R3
100k
VFB
COMP
SS
* C3 is optional. Recommend
putting a placeholder for it. Check
loop analysis first before use.
FIGURE 2. TYPICAL APPLICATION DIAGRAM - SINGLE CHIP 8A
FN7889 Rev 0.00
September 30, 2015
Page 4 of 21
ISL8018
Block Diagram
COMP
SS
SHUTDOWN
FS
SYNCIN
SYNCOUT
55pF
Soft
SOFTSTART
SHUTDOWN
168k
250µA
VDD
+
BANDGAP
VREF
+
EN
+
COMP
-
EAMP
-
VIN
OSCILLATOR
P
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
VSET
3pF
+
PHASE
LS
DRIVER
N
PGND
VFB
SLOPE
Slope
COMP
6k
0.8V
+
-
CSA
-
+
OV
+
OCP
-
0.85*VREF
+
UV
ISET
ISET
THRESHOLD
+
SKIP
-
PG
1ms
DELAY
NEG CURRENT
SENSING
SGND
ZERO-CROSS
SENSING
0.1V
SCP
+
100
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
FN7889 Rev 0.00
September 30, 2015
Page 5 of 21
ISL8018
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, ISET, PG, SYNCOUT, SYNCIN VFB, VSET . . . . . . -0.3V to VIN + 0.3V
PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . .1.5V
Latch-up (Tested per JESD-78A; Class 2, Level A) . . . . . .100mA at +85°C
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
3x4 QFN Package (Notes 4, 5) . . . . . . . . . .
42
5
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 8A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. JC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Analog Specifications All parameter limits are established across the recommended operating conditions and are measured at the
following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
2.5
2.7
V
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising, no load
Falling, no load
Quiescent Supply Current
Shutdown Supply Current
IVIN
ISD
2.2
2.4
V
SYNCIN = GND, no load at the output
70
µA
SYNCIN = GND, no load at the output and no
switches switching
70
95
µA
SYNCIN = VIN, fSW = 1MHz, no load at the
output
8
15
mA
SYNCIN = GND, VIN = 5.5V, EN = low
5
9.5
µA
OUTPUT REGULATION
Reference Voltage
Output Voltage Margining
VREF
VVFB
VSET = VIN
0.651
0.660
0.669
V
VSET = FLOAT
0.594
0.600
0.606
V
VSET = SGND
0.531
0.540
0.549
V
9.5
10
10.5
%
-10.5
-10
-9.5
%
VSET = VIN, percent of output changed
VSET = SGND, percent of output changed
VFB Bias Current
IVFB
VFB = 0.75V
Fixed Output VFB Bias Current
IVFB
0.1
µA
VSET = FLOAT, VFB = 10% above output
6
µA
Line Regulation
VIN = VO + 0.5V to 5.5V (minimal 2.7V)
0.2
%/V
Soft-Start Ramp Time Cycle
SS = SGND
1
ms
Soft-Start Charging Current
ISS
VSS = 0.1V
1.4
1.8
2.2
µA
OVERCURRENT PROTECTION
Current Limit Blanking Time
tOCON
17
Clock
pulses
Overcurrent and Auto Restart Period
tOCOFF
8
SS cycle
FN7889 Rev 0.00
September 30, 2015
Page 6 of 21
ISL8018
Analog Specifications All parameter limits are established across the recommended operating conditions and are measured at the
following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
Positive Peak Current Limit
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
9.7
12.8
15.8
A
6.7
8.8
10.9
A
ISET = SGND
4
5.6
7.2
A
ISET = FLOAT
2.18
2.8
3.78
A
ISET = VIN
1.08
1.66
2.3
A
SYMBOL
TEST CONDITIONS
IPLIMIT ISET = FLOAT
ISET = VIN
Peak Skip Limit
ISKIP
ISET = SGND
Zero Cross Threshold
Negative Current Limit
1.05
-300
INLIMIT
-4.25
-3
A
300
mA
-1.75
A
COMPENSATION
Error Amplifier Transconductance
Transresistance
FS = VIN
100
µA/V
FS with resistor
200
µA/V
0.11
Ω
RT
PHASE
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
VIN = 5V, IO = 200mA
31
45
mΩ
VIN = 2.7V, IO = 200mA
44
55
mΩ
VIN = 5V, IO = 200mA
19
35
mΩ
VIN = 2.7V, IO = 200mA
25
50
mΩ
PHASE Maximum Duty Cycle
100
PHASE Minimum On-Time
SYNCIN = High
%
140
ns
OSCILLATOR
Nominal Switching Frequency
fSW
FS = VIN
800
1000
1200
kHz
FS with RS = 402kΩ
440
520
600
kHz
FS with RS = 42.4kΩ
3200
3700
4200
kHz
0.70
0.75
0.80
V
SYNCIN Logic Low to High Transition Range
SYNCIN Hysteresis
0.15
SYNCIN Logic Input Leakage Current
SYNCOUT Charging Current
VIN = 3.6V
ISO
PWM
210
PFM
V
3.6
5
µA
250
290
µA
0
SYNCOUT Voltage Low
µA
0.3
V
0.3
V
1
2
ms
PG Pin Leakage Current
0.01
0.1
µA
OVP PG Rising Threshold
0.80
PG
Output Low Voltage
Delay Time (Rising Edge)
UVP PG Rising Threshold
0.5
80
85
V
90
%
UVP PG Hysteresis
5
%
PGOOD Delay Time (Falling Edge)
7
µs
FN7889 Rev 0.00
September 30, 2015
Page 7 of 21
ISL8018
Analog Specifications All parameter limits are established across the recommended operating conditions and are measured at the
following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply across
the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
0.4
V
0.8
V
ISET, VSET
Logic Input Low
Logic Input Float
0.5
Logic Input High
0.9
Logic Input Leakage Current
V
0.1
1
µA
0.4
V
EN
Logic Input Low
Logic Input High
0.9
V
EN Logic Input Leakage Current
0.1
1
µA
Thermal Shutdown
150
°C
Thermal Shutdown Hysteresis
25
°C
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7889 Rev 0.00
September 30, 2015
Page 8 of 21
ISL8018
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = 3.3V,
SYNCIN = VIN, L = 1µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 8A.
100
100
2.5VOUT
2.5VOUT
90
90
1.2VOUT
1.5VOUT
EFFICIENCY (%)
EFFICIENCY (%)
1.2VOUT
80
1.8VOUT
70
60
50
40
80
1.5VOUT
70
1.8VOUT
60
50
0
1
2
3
4
5
6
7
40
8
0
1
2
3
4
IOUT (A)
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3VIN PWM)
100
1.2VOUT
8
2.5VOUT
1.2VOUT
1.5VOUT
EFFICIENCY (%)
EFFICIENCY (%)
3.3VOUT
2.5VOUT
1.8VOUT
70
60
1.5VOUT
80
1.8VOUT
70
60
50
50
0
1
2
3
4
5
6
7
40
8
0
1
2
3
4
5
6
7
8
IOUT (A)
IOUT (A)
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
FIGURE 7. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
3.5
1.815
3.0
1.810
1.805
2.5
5VIN PWM MODE
0A LOAD
1.800
2.0
VOUT (V)
PD (W)
7
90
80
3.3VIN PWM MODE
1.5
1.0
1.795
4A LOAD
1.790
1.785
0.5
0
6
FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3VIN PFM)
100
3.3VOUT
90
40
5
IOUT (A)
8A LOAD
1.780
0
1
2
3
4
5
6
7
IOUT (A)
FIGURE 8. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V)
FN7889 Rev 0.00
September 30, 2015
8
1.775
2.5
2.8
3.1
3.4
3.7
4.0
4.3
4.6
4.9
5.2
IOUT (A)
FIGURE 9. VOUT REGULATION vs VIN (PWM VOUT = 1.8V)
Page 9 of 21
5.5
ISL8018
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = 3.3V,
SYNCIN = VIN, L = 1µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 8A. (Continued)
1.847
1.230
0A LOAD
1.839
1.224
1.831
1.823
5VIN PFM MODE
1.212
VOUT (V)
VOUT (V)
3.3VIN PFM MODE
1.218
1.815
4A LOAD
1.807
1.799
1.200
1.791
1.194
1.783
1.188
1.775
2.5
3.3VIN PWM MODE
1.206
5VIN PWM MODE
8A LOAD
2.8
3.1
3.4
3.7
4.0
4.3
4.6
4.9
5.2
1.182
5.5
0
1
2
3
IOUT (A)
FIGURE 10. VOUT REGULATION vs VIN (PFM VOUT = 1.8V)
3.3VIN PFM MODE
1.515
5VIN PFM MODE
7
8
1.822
3.3VIN PFM MODE
1.815
5VIN PFM MODE
1.808
VOUT (V)
VOUT (V)
1.509
3.3VIN PWM MODE
1.503
1.497
1.491
3.3VIN PWM MODE
1.801
1.794
1.787
5VIN PWM MODE
5VIN PWM MODE
1.780
1.485
0
1
2
3
4
5
6
7
1.773
8
0
1
2
3
IOUT (A)
4
5
6
7
8
IOUT (A)
FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V)
FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)
3.36
2.532
3.3VIN PFM MODE
2.524
3.34
3.3VIN PWM MODE
2.500
2.492
2.484
5VIN PWM MODE
3.33
VOUT (V)
2.508
5VIN PFM MODE
3.35
5VIN PFM MODE
2.516
VOUT (V)
6
1.829
1.521
3.32
3.31
3.30
5VIN PWM MODE
3.29
2.476
2.468
5
FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)
1.527
1.479
4
IOUT (A)
0
1
2
3
4
5
6
7
IOUT (A)
FIGURE 14. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V)
FN7889 Rev 0.00
September 30, 2015
8
3.28
0
1
2
3
4
5
6
7
IOUT (A)
FIGURE 15. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)
Page 10 of 21
8
ISL8018
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = 3.3V,
SYNCIN = VIN, L = 1µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 8A. (Continued)
PHASE 2V/DIV
PHASE 2V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 1A/DIV
IL 1A/DIV
500ns/DIV
2µs/DIV
FIGURE 16. STEADY STATE OPERATION AT NO LOAD (PWM)
FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PFM)
PHASE 2V/DIV
VOUT RIPPLE 50mV/DIV
IL 2A/DIV
VOUT RIPPLE 20mV/DIV
IL 2A/DIV
500ns/DIV
1ms/DIV
FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD
FIGURE 19. LOAD TRANSIENT (PWM)
VOUT RIPPLE 50mV/DIV
EN 2V/DIV
VOUT 1V/DIV
IL 2A/DIV
IL 2A/DIV
PG 5V/DIV
1ms/DIV
5ms/DIV
FIGURE 20. LOAD TRANSIENT (PFM)
FIGURE 21. SOFT-START WITH NO LOAD (PWM)
FN7889 Rev 0.00
September 30, 2015
Page 11 of 21
ISL8018
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = 3.3V,
SYNCIN = VIN, L = 1µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 8A. (Continued)
EN 5V/DIV
VOUT 1V/DIV
EN 2V/DIV
VOUT 1V/DIV
IL 2A/DIV
IL 2A/DIV
PG 5V/DIV
PG 5V/DIV
5ms/DIV
5ms/DIV
FIGURE 22. SOFT-START AT NO LOAD (PFM)
FIGURE 23. SOFT-START WITH PREBIASED 1V
EN 2V/DIV
VOUT 1V/DIV
EN 2V/DIV
VOUT 1V/DIV
IL 2A/DIV
PG 5V/DIV
IL 2A/DIV
PG 5V/DIV
5ms/DIV
500µs/DIV
FIGURE 24. SOFT-START AT FULL LOAD
FIGURE 25. SOFT-DISCHARGE SHUTDOWN
PHASE 5V/DIV
PHASE 5V/DIV
IL 2A/DIV
VOUT RIPPLE 20mV/DIV
IL 1A/DIV
SYNC 5V/DIV
200ns/DIV
FIGURE 26. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 2MHz
FN7889 Rev 0.00
September 30, 2015
VOUT RIPPLE 20mV/DIV
SYNC 5V/DIV
200ns/DIV
FIGURE 27. STEADY STATE OPERATION AT FULL LOAD WITH
FREQUENCY = 2MHz
Page 12 of 21
ISL8018
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VIN = 5V, EN = 3.3V,
SYNCIN = VIN, L = 1µH, C1 = 2x22µF, C2 = 4x22µF, VOUT = 1.8V, IOUT = 0A to 8A. (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 2A/DIV
IL 0.2A/DIV
SYNC 5V/DIV
SYNC 5V/DIV
100ns/DIV
100ns/DIV
FIGURE 28. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 4MHz
FIGURE 29. STEADY STATE OPERATION AT FULL LOAD (PWM) WITH
FREQUENCY = 4MHz
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 5A/DIV
IL 5A/DIV
PG 5V/DIV
PG 5V/DIV
10µs/DIV
2ms/DIV
FIGURE 30. OUTPUT SHORT-CIRCUIT
FIGURE 31. OUTPUT SHORT-CIRCUIT RECOVERY
FN7889 Rev 0.00
September 30, 2015
Page 13 of 21
ISL8018
Theory of Operation
with the 55pF and 168kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 2.4V.
The ISL8018 is a step-down switching regulator optimized for
battery-powered handheld applications. The regulator operates at
1MHz fixed default switching frequency when FS is connected to
VIN. By connecting a resistor from FS to SGND, the operating
frequency may be adjusted from 500kHz to 4MHz. Unless forced
and PWM is chosen (SYNCIN pulled HI), the regulator will allow
PFM operation and reduce switching frequency at light loading to
maximize efficiency. In this condition, no load quiescent is typically
70µA.
VEAMP
VCSA
DUTY
CYCLE
IL
PWM Control Scheme
VOUT
Pulling the SYNCIN high (>0.8V) forces the converter into PWM
mode, regardless of output current. The ISL8018 employs the
current-mode Pulse Width Modulation (PWM) control scheme for
fast transient response and pulse-by-pulse current limiting. Figure 3
shows the block diagram. The current loop consists of the oscillator,
the PWM comparator, current sensing circuit and the slope
compensation for the current loop stability. The slope compensation
is 360mV/Ts. Current sense resistance, Rt, is typically 0.11V/A. The
control reference for the current loop comes from the error
amplifier's (EAMP) output.
FIGURE 32. PWM OPERATION WAVEFORMS
Skip Mode
Pulling the SYNCIN pin LO (
