DATASHEET
ISL8025, ISL8025A
FN8357
Rev 1.00
December 19, 2013
Compact Synchronous Buck Regulators
The ISL8025, ISL8025A are highly efficient, monolithic,
synchronous step-down DC/DC converters that can deliver 5A of
continuous output current from a 2.7V to 5.5V input supply. The
devices use current mode control architecture to deliver a very low
duty cycle operation at high frequency with fast transient
response and excellent loop stability.
The ISL8025, ISL8025A integrates a very low ON-resistance
P-Channel (36mΩ) high-side FET and N-Channel (13mΩ)
low-side FET to maximize efficiency and minimize external
component count. The 100% duty-cycle operation allows less
than 180mV dropout voltage at 5A output current. The
operation frequency of the pulse-width modulator (PWM) is
adjustable from 500kHz to 4MHz. The default switching
frequency, which is set by connecting the FS pin high, is 1MHz
for the ISL8025 and 2MHz for the ISL8025A.
The ISL8025, ISL8025A can be configured for discontinuous or
forced continuous operation at light load. Forced continuous
operation reduces noise and RF interference, while
discontinuous mode provides higher efficiency by reducing
switching losses at light loads.
Fault protection is provided by internal hiccup mode current
limiting during short circuit and overcurrent conditions. Other
protection, such as overvoltage and over-temperature, are also
integrated into the device. A power-good output voltage
monitor indicates when the output is in regulation.
Features
• 2.7V to 5.5V input voltage range
• Very low ON-resistance FET’s - P-channel 36mΩ and
N-channel 13mΩ typical values
• High efficiency synchronous buck regulator with up to 95%
efficiency
• Pin-to-pin compatible with ISL8023 and ISL8024
• 0.8% reference accuracy over-temperature/load/line
• Internal soft-start: 1ms or adjustable
• Soft-stop output discharge during disable
• Adjustable frequency from 500kHz to 4MHz - default at
1MHz (ISL8025), 2MHz (ISL8025A)
• External synchronization up to 4MHz
• Over-temperature, overcurrent, overvoltage and negative
overcurrent protection
Applications
•
•
•
•
•
•
DC/DC POL modules
μC/µP, FPGA and DSP power
Plug-in DC/DC modules for routers and switchers
Portable instruments
Test and measurement systems
Li-ion battery powered devices
Related Literature
The ISL8025, ISL8025A offers a 1ms Power-good (PG) timer
at power-up. When in shutdown, the ISL8025, ISL8025A
discharges the output capacitor through an internal soft-stop
switch. Other features include internal fixed or adjustable
soft-start and internal/external compensation.
• See AN1806, “5A Low Quiescent Current High Efficiency
Synchronous Buck Regulator”
The ISL8025, ISL8025A are offered in a space saving 16 Ld
3x3 Pb-free QFN package with an exposed pad for improved
thermal performance and 1mm maximum height. The
complete converter occupies less than 0.22 in2 area.
3 PG
SGND 10
FB 9
SYNC
R2
200k
90
C3*
22pF
R3
100k
+0.6V
80
70
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
60
50
EN
*C3 IS OPTIONAL. IT IS
RECOMMENDED TO PUT A
PLACEHOLDER FOR IT AND CHECK
LOOP ANALYSIS BEFORE USE.
EFFICIENCY (%)
PHASE 13
PHASE 14
PGND 11
5 EN
100
VOUT
GND
2 VDD
4
+1.8V/5A
PGND 12
8 COMP
PAD
PG
ISL8025, ISL8025A
17
R1
100k
VIN
7 SS
GND
1
6 FS
+2.7V …+5.5V
C1
2 x 22µF
VIN
PHASE 15
VIN 16
L1
1.0µH C2
2 x 22µF
R
2
VO
= R ------------ – 1
3 VFB
(EQ. 1)
FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION
(INTERNAL COMPENSATION OPTION)
FN8357 Rev 1.00
December 19, 2013
40
0.0
0.5
1.0
1.5 2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 2. EFFICIENCY vs LOAD
FSW = 1MHz, VIN = 5V, MODE = PFM, TA = +25°C
Page 1 of 22
ISL8025, ISL8025A
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Operating Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Operating Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SKIP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
17
17
17
17
17
17
17
18
18
18
18
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
18
PCB Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
FN8357 Rev 1.00
December 19, 2013
Page 2 of 22
ISL8025, ISL8025A
Pin Configuration
VIN
PHASE
PHASE
PHASE
ISL8025, ISL8025A
(16 LD TQFN)
TOP VIEW
16
15
14
13
12
PGND
11
PGND
PG 3
10
SGND
SYNC 4
9
FB
VIN 1
VDD 2
5
6
7
8
EN
FS
SS
COMP
PAD
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1, 16
VIN
Input supply voltage. Place a minimum of two 22µF ceramic capacitors from VIN to PGND as close as
possible to the IC for decoupling.
2
VDD
Input supply voltage for the logic. Connect VIN pin.
3
PG
Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms upon output reached within regulation.
4
SYNC
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case
of SYNC pin float.
5
EN
Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output
capacitor when driven to low.
6
FS
This pin sets the oscillator switching frequency, using a resistor, RFS, from the FS pin to GND. The
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
if FS is connected to VIN.
7
SS
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor from
SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
8, 9
COMP, FB
The feedback network of the regulator, FB, is the negative input to the transconductance error
amplifier. The output voltage is set by an external resistor divider connected to FB. With a properly
selected divider, the output voltage can be set to any voltage between the power rail (reduced by
converter losses) and the 0.6V reference.
COMP is the output of the amplifier if COMP is not tied to VDD. Otherwise, COMP is disconnected thru
a MOSFET for internal compensation. Must connect COMP to VDD in internal compensation mode to
meet a typical application. Additional external networks across COMP and SGND might be required to
improve the loop compensation of the amplifier operation.
In addition, the regulator power-good and under-voltage protection circuitry use FB to monitor the
regulator output voltage.
10
SGND
Signal ground.
11, 12
PGND
Power ground.
13, 14, 15
PHASE
Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100
resistor when the device is disabled. See“FUNCTIONAL BLOCK DIAGRAM” on page 5 for more detail.
Exposed Pad
-
FN8357 Rev 1.00
December 19, 2013
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as
many vias as possible under the pad connecting to SGND plane for optimal thermal performance.
Page 3 of 22
ISL8025, ISL8025A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
OPERATION FREQUENCY
(MHz)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL8025IRTAJZ
025A
1
-40 to +85
16 Ld 3x3 TQFN
L16.3x3D
ISL8025AIRTAJZ
25AA
2
-40 to +85
16 Ld 3x3 TQFN
L16.3x3D
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8025, ISL8025A. For more information on MSL please see techbrief
TB363.
TABLE 1. SUMMARY OF KEY DIFFERENCES
IOUT
(MAX)
(A)
PART
NUMBER
ISL8025
5
ISL8025A
VIN
RANGE
(V)
VOUT
RANGE
(V)
PART SIZE
(mm)
2.7 to 5.5
0.6 to 5.5
3x3
FSW RANGE
(MHz)
Programmable
0.5MHz to 4MHz
Programmable 1MHz to 4MHz
NOTES:
4. The Evaluation Kit default configuration is VOUT = 1.8V, FSW = 1MHz.
5. VREF is 0.6V.
TABLE 2. ISL8025 COMPONENT SELECTION
VOUT
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
3.6V
C1
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
C2
4 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
C3
22pF
22pF
22pF
22pF
22pF
22pF
22pF
L1
0.47~1µH
0.47~1µH
0.47~1µH
0.68~1.5µH
0.68~1.5µH
1~2.2µH
1~2.2µH
R2
33k
100k
150k
200k
316k
450k
500k
R3
100k
100k
100k
100k
100k
100k
100k
TABLE 3. ISL8025A COMPONENT SELECTION
VOUT
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
3.6V
C1
22µF
22µF
22µF
22µF
22µF
22µF
22µF
C2
3 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
2 x 22µF
C3
22pF
22pF
22pF
22pF
22pF
22pF
22pF
L1
0.22~0.47µH
0.22~0.47µH
0.22~0.47µH
0.33~0.68µH
0.33~0.68µH
0.47~1µH
0.47~1µH
R2
33k
100k
150k
200k
316k
450k
500k
R3
100k
100k
100k
100k
100k
100k
100k
FN8357 Rev 1.00
December 19, 2013
Page 4 of 22
ISL8025, ISL8025A
COMP
SS
SHUTDOWN
FS
SYNC
55pF
Soft
SOFTSTART
SHUTDOWN
VDD
100k
+
BANDGAP VREF
+
EN
+
COMP
-
EAMP
-
VIN
OSCILLATOR
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
3pF
+
P
PHASE
LS
DRIVER
N
PGND
FB
6k
SLOPE
Slope
COMP
0.8V
+
CSA
-
+
OV
0.85*VREF
PG
+
UV
+
OCP
-
+
SKIP
-
ISET
THRESHOLD
1ms
DELAY
NEG CURRENT
SENSING
SGND
ZERO-CROSS
SENSING
0.5V
SCP
+
100
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
FN8357 Rev 1.00
December 19, 2013
Page 5 of 22
ISL8025, ISL8025A
Absolute Maximum Ratings
Thermal Information
(Reference to GND)
Thermal Resistance
JA (°C/W) JC (°C/W)
16 LD TQFN Package (Notes 6, 7) . . . . . . .
47
6.5
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
COMP, SS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 3kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Latch Up (Tested per JESD-78A; Class 2, Level A) . . . . . .100mA @ +85°C
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 5A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. JC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are
at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
2.5
2.7
V
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising, no load
Falling, no load
Quiescent Supply Current
Shutdown Supply Current
IVIN
ISD
2.2
2.4
V
SYNC = GND, no load at the output
50
µA
SYNC = GND, no load at the output and no
switches switching
50
60
µA
SYNC = VIN, FSW = 1MHz, no load at the output
8
15
mA
SYNC = VIN, FSW = 2MHz, no load at the output
16
23
mA
SYNC = GND, VIN = 5.5V, EN = low
5
7
µA
0.600
0.605
V
OUTPUT REGULATION
Reference Voltage
VREF
VFB Bias Current
IVFB
0.595
VFB = 0.75V
0.1
µA
Line Regulation
VIN = VO + 0.5V to 5.5V (minimal 2.7V)
0.2
%/V
Soft-Start Ramp Time Cycle
SS = SGND
1
ms
Soft-Start Charging Current
ISS
VSS = 0.1V
1.45
1.85
2.25
µA
OVERCURRENT PROTECTION
Current Limit Blanking Time
tOCON
17
Clock
pulses
Overcurrent and Auto Restart Period
tOCOFF
8
SS cycle
Positive Peak Current Limit
IPLIMIT
Peak Skip Limit
ISKIP
Zero Cross Threshold
Negative Current Limit
FN8357 Rev 1.00
December 19, 2013
5A application
5A application (See “Application Information”
on page 18 for more detail)
6
7.5
9
A
0.8
1
1.2
A
200
mA
-1.5
A
-200
INLIMIT
-4.5
-3
Page 6 of 22
ISL8025, ISL8025A
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VIN, unless otherwise noted. Typical values are
at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8)
TYP
MAX
(Note 8)
UNITS
COMPENSATION
Error Amplifier Trans-Conductance
Trans-Resistance
RT
Internal compensation
60
µA/V
External compensation
120
µA/V
5A application (test at 3.6V)
0.155
0.175
0.195
Ω
VIN = 5V, IO = 200mA
36
41
mΩ
VIN = 2.7V, IO = 200mA
52
60
mΩ
VIN = 5V, IO = 200mA
13
16
mΩ
VIN = 2.7V, IO = 200mA
17
21
mΩ
PHASE
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
PHASE Maximum Duty Cycle
100
PHASE Minimum On-Time
SYNC = High
140
ns
OSCILLATOR
Nominal Switching Frequency
FSW
FSW = VIN, ISL8025
800
1000
1200
kHz
FSW = VIN, ISL8025A
1600
2000
2400
kHz
FSW with RS = 402kΩ
490
kHz
FSW with RS = 42.2kΩ
4200
kHz
SYNC Logic Low-to-High Transition Range
0.70
SYNC Hysteresis
SYNC Logic Input Leakage Current
0.75
0.80
0.15
VIN = 3.6V
3.6
V
V
5
µA
0.3
V
1
2
ms
0.01
0.1
µA
PG
Output Low Voltage
Delay Time (Rising Edge)
Time from VOUT reached regulation
PG Pin Leakage Current
PG = VIN
0.5
OVP PG Rising Threshold
0.80
UVP PG Rising Threshold
0.48
0.51
V
0.54
V
UVP PG Hysteresis
30
mV
PGOOD Delay Time (Falling Edge)
7.5
µs
EN
Logic Input Low
0.4
Logic Input High
0.9
V
V
EN Logic Input Leakage Current
Pulled up to 5.5V
0.1
1
µA
Thermal Shutdown
Temperature Rising
150
°C
Thermal Shutdown Hysteresis
Temperature Falling
25
°C
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN8357 Rev 1.00
December 19, 2013
Page 7 of 22
ISL8025, ISL8025A
Typical Operating Performance
100
100
90
90
80
80
70
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
60
50
40
0.0
EFFICIENCY (%)
EFFICIENCY (%)
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V,
EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A. Resistor load is used in the test
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
70
60
50
40
0.0
5.0
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
100
70
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
60
50
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
40
0.0
5.0
80
80
EFFICIENCY (%)
EFFICIENCY (%)
90
70
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
60
50
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
FIGURE 8. EFFICIENCY vs LOAD (2MHz 3.3VIN PWM)
FN8357 Rev 1.00
December 19, 2013
3.0
3.5
4.0
4.5
5.0
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 7. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
90
1.5
2.5
50
100
1.0
2.0
60
100
0.5
1.5
70
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
40
0.0
1.0
FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM)
100
0.5
0.5
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM)
40
0.0
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.8VOUT
0.9VOUT
70
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
0.8VOUT
60
50
5.0
40
0.0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 9. EFFICIENCY vs LOAD (2MHz 3.3VIN PFM)
Page 8 of 22
ISL8025, ISL8025A
Typical Operating Performance
100
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V,
EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A. Resistor load is used in the test (Continued)
70
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
60
50
40
0.0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 11. EFFICIENCY vs LOAD (2MHz 5VIN PFM)
0.906
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
0.807
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
0.903
OUTPUT VOLTAGE (V)
0.810
OUTPUT VOLTAGE (V)
60
40
0.0
5.0
0.813
0.804
0.801
0.798
0.795
0.900
0.897
0.894
0.891
0.888
0.885
0.792
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
0.882
0.0
5.0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 0.8V)
FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 0.9V)
1.219
1.515
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
1.209
1.204
1.199
1.194
1.189
1.184
1.179
0.0
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
1.510
OUTPUT VOLTAGE (V)
1.214
OUTPUT VOLTAGE (V)
3.3VOUT
2.5VOUT
1.8VOUT
1.5VOUT
1.2VOUT
0.9VOUT
50
FIGURE 10. EFFICIENCY vs LOAD (2MHz 5VIN PWM)
0.789
0.0
70
1.505
1.500
1.495
1.490
1.485
1.480
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 14. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)
FN8357 Rev 1.00
December 19, 2013
1.475
0.0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 15. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V)
Page 9 of 22
ISL8025, ISL8025A
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V,
EN = VIN, SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A. Resistor load is used in the test (Continued)
1.815
2.505
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
1.805
1.800
1.795
1.790
1.785
1.780
1.775
0.0
5VIN PFM
5VIN PWM
3.3VIN PWM
3.3VIN PFM
2.500
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.810
2.495
2.490
2.485
2.480
2.475
2.470
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
2.465
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT LOAD (A)
FIGURE 16. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)
FIGURE 17. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V)
3.309
5VIN PFM
5VIN PWM
OUTPUT VOLTAGE (V)
3.301
3.293
3.285
3.277
3.269
3.261
3.253
3.245
0.0
0.5
1.0
1.5
2.0 2.5 3.0 3.5
OUTPUT LOAD (A)
4.0
4.5
5.0
FIGURE 18. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)
FN8357 Rev 1.00
December 19, 2013
Page 10 of 22
ISL8025, ISL8025A
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A) Resistor load is used in the test.
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 19. START-UP AT NO LOAD (PFM)
FIGURE 20. START-UP AT NO LOAD (PWM)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 21. SHUTDOWN AT NO LOAD (PFM)
500µs/DIV
FIGURE 22. SHUTDOWN AT NO LOAD (PWM)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 23. START-UP AT 5A LOAD (PWM)
FN8357 Rev 1.00
December 19, 2013
500µs/DIV
FIGURE 24. SHUTDOWN AT 5A LOAD (PWM)
Page 11 of 22
ISL8025, ISL8025A
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A) Resistor load is used in the test. (Continued)
IOUT 2A/DIV
VOUT 1V/DIV
VEN 5V/DIV
PG 5V/DIV
IOUT 2A/DIV
VOUT 1V/DIV
VEN 5V/DIV
PG 5V/DIV
1ms/DIV
200µs/DIV
FIGURE 25. START-UP AT 5A LOAD (PFM)
FIGURE 26. SHUTDOWN AT 5A LOAD (PFM)
IOUT 2A/DIV
IOUT 2A/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 27. START-UP VIN AT 5A LOAD (PFM)
FIGURE 28. START-UP VIN AT 5A LOAD (PWM)
IOUT 2A/DIV
IOUT 2A/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 29. SHUTDOWN VIN AT 5A LOAD (PFM)
FIGURE 30. SHUTDOWN VIN AT 5A LOAD (PWM)
FN8357 Rev 1.00
December 19, 2013
Page 12 of 22
ISL8025, ISL8025A
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A) Resistor load is used in the test. (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 31. START-UP VIN AT NO LOAD (PFM)
FIGURE 32. START-UP VIN AT NO LOAD (PWM)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
2ms/DIV
2ms/DIV
FIGURE 33. SHUTDOWN VIN AT NO LOAD (PFM)
FIGURE 34. SHUTDOWN VIN AT NO LOAD (PWM)
PHASE 1V/DIV
PHASE 1V/DIV
10ns/DIV
10ns/DIV
FIGURE 35. JITTER AT NO LOAD PWM
FIGURE 36. JITTER AT FULL LOAD PWM
FN8357 Rev 1.00
December 19, 2013
Page 13 of 22
ISL8025, ISL8025A
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A) Resistor load is used in the test. (Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL 1A/DIV
IL 1A/DIV
500ns/DIV
20ms/DIV
FIGURE 37. STEADY STATE AT NO LOAD PWM
FIGURE 38. STEADY STATE AT NO LOAD PFM
PHASE 5V/DIV
VOUT RIPPLE 100mV/DIV
VOUT RIPPLE 20mV/DIV
IL 2A/DIV
IL 2A/DIV
500ns/DIV
200µs/DIV
FIGURE 39. STEADY STATE AT 5A PWM
FIGURE 40. LOAD TRANSIENT (PWM)
PHASE 5V/DIV
VOUT RIPPLE 100mV/DIV
IL 2A/DIV
VOUT 1V/DIV
IL 2A/DIV
PG 5V/DIV
200µs/DIV
10µs/DIV
FIGURE 41. LOAD TRANSIENT (PFM)
FIGURE 42. OUTPUT SHORT CIRCUIT
FN8357 Rev 1.00
December 19, 2013
Page 14 of 22
ISL8025, ISL8025A
Typical Operating Performance
Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 5V, EN = VIN,
SYNC = VIN, L = 1.0µH, C1 = 22µF, C2 = 2 x 22µF, IOUT = 0A to 5A) Resistor load is used in the test. (Continued)
PHASE 5V/DIV
VOUT 1V/DIV
500mA MODE TRANSITION,
COMPLETELY ENTER TO PWM AT 590mA
VOUT1 RIPPLE 20mV/DIV
IL 5A/DIV
PG 5V/DIV
IL 1A/DIV
50µs/DIV
2µs/DIV
FIGURE 43. OVERCURRENT PROTECTION
FIGURE 44. PFM TO PWM TRANSITION
PHASE 5V/DIV
PHASE 5V/DIV
Back to PFM at 420mA
VOUT 1V/DIV
VOUT1 RIPPLE 20mV/DIV
IL 2A/DIV
PG 5V/DIV
IL 1A/DIV
2µs/DIV
20µs/DIV
FIGURE 45. PWM TO PFM TRANSITION
FIGURE 46. OVERVOLTAGE PROTECTION
VOUT 1V/DIV
PG 2V/DIV
2ms/DIV
FIGURE 47. OVER-TEMPERATURE PROTECTION
FN8357 Rev 1.00
December 19, 2013
Page 15 of 22
ISL8025, ISL8025A
Theory of Operation
The ISL8025, ISL8025A are step-down switching regulators
optimized for battery-powered applications. The regulators
operate at 1MHz or 2MHz fixed default switching frequency for
high efficiency and allow smaller form factor, when FS is
connected to VIN. By connecting a resistor from FS to SGND, the
operational frequency adjustable range is 500kHz to 4MHz. At
light load, the regulator reduces the switching frequency, unless
forced to the fixed frequency, to minimize the switching loss and
to maximize the battery life. The quiescent current when the
output is not loaded is typically only 50µA. The supply current is
typically only 5µA when the regulator is shut down.
PWM Control Scheme
Pulling the SYNC pin HI (>0.8V) forces the converter into PWM
mode, regardless of output current. The ISL8025, ISL8025A
employs the current-mode pulse-width modulation (PWM) control
scheme for fast transient response and pulse-by-pulse current
limiting. Figure 3 on page 5 shows the Functional Block Diagram.
The current loop consists of the oscillator, the PWM comparator,
current sensing circuit and the slope compensation for the
current loop stability. The slope compensation is 440mV/Ts,
which changes with frequency. The gain for the current sensing
circuit is typically 200mV/A. The control reference for the current
loops comes from the error amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-FET and turn on the N-Channel MOSFET. The N-FET stays on
until the end of the PWM cycle. Figure 48 shows the typical
operating waveforms during the PWM operation. The dotted lines
illustrate the sum of the slope compensation ramp and the
current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the VEAMP voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
with the 55pF and 100kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 1.6V.
FN8357 Rev 1.00
December 19, 2013
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 48. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNC pin LO (
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