Datasheet
ISL81802
80V Dual Synchronous Buck Controller
The ISL81802 is a dual synchronous buck controller
that generates two independent outputs or one output
with two interleaved phases for a wide variety of
applications in industrial and general purpose
segments. With a wide input and output voltage
ranges, the controller is suitable for
telecommunication, data center, and computing
applications.
The ISL81802 uses peak current mode control with
phase interleaving for the two outputs. Each output
has a voltage regulator, current monitor, and average
current regulator to provide independent average
voltage and current control. The internal
Phase-Locked Loop (PLL) oscillator assures an
accurate frequency setting from 100kHz to 1MHz, and
the oscillator can be synchronized to an external clock
signal for frequency synchronization and phase
interleave paralleling applications. This PLL circuit
can output a phase-shift-programmable clock signal
that is expanded to three, four, and six phases with
required interleaving phase shift.
The ISL81802 features programmable soft-start and
accurate threshold enable functions along with a
power-good indicator to simplify power supply rail
sequencing. It also provides full protection features
such as OVP, UVP, OTP, and average and peak
current limit on both outputs to ensure high reliability.
Features
• Wide input voltage range: 4.5V to 80V
• Wide output voltage range: 0.8V to 76V
• Four MOSFET drivers with adaptive shoot-through
protection
• Constant output voltage and output current
feedback loop control
• Light-load efficiency enhancement
○ Low ripple diode emulation and burst mode
operation
• Programmable soft-start
• Supports startup into pre-biased rails
• Programmable frequency: 100kHz to 1MHz
• Supports current sharing with cascade phase
interleaving
• External clock sync
• Clock out with accurate phase angle controlled by
PLL or frequency dithering
• PGOOD indicator
• Output current monitor
• Selectable mode between PWM/DE/Burst
• Accurate EN/UVLO threshold: ±2%
The IC is packaged in a spac- conscious 32 Ld
5mmx5mm TQFN or an easy to assemble
4.4mmx9.7mm 38 Ld HTSSOP package. Both
packages use an EPAD to improve thermal
performance and noise immunity. The full feature
design with low pin count makes the ISL81802 an
ideal solution for quick time to market simple power
supply designs.
• Low shut down current: 5µA
Related Literature
• Server and data center
For a full list of related documents, visit our website:
• ISL81802 device page
R16DS0033EU0101 Rev.1.01
Oct.15.20
• Complete protection: OCP (pulse by pulse and
optional hiccup or constant current mode), OVP,
OTP, and UVP
Applications
• Telecommunication
• Automotive electronics
• Industrial equipment
• Power system
Page 1 of 44
ISL81802
PGND
SGND
CS1+
CS1-
VDD
VIN
EN/UVLO2
EN/UVLO1
VIN
ISL81802 TQFN
VCC5V
VDD
BOOT1
UG1
PLL_COMP
VOUT
CLKOUT/DITHER
PHASE1
RT/SYNC
LG1/PWM_MODE
FB1
EPAD
VDD
COMP1
BOOT2
SS/TRK1
UG2
SS/TRK2/OV
PHASE2
COMP2/CLKEN
EXTBIAS
CS2+
LG2/OC_MODE
CS2-
PGOOD
IMON2
IMON1
FB2/PFMEN
Figure 1. Typical Application Diagram
100
98
Efficiency (%)
96
94
92
90
88
86
Vin = 18V
Vin = 36V
Vin = 60V
84
82
Vin = 24V
Vin = 48V
Vin = 80V
80
0
5
10
15
20
Output Current (A)
Figure 2. Efficiency (VOUT = 12V, CC Mode)
R16DS0033EU0101 Rev.1.01
Oct.15.20
Page 2 of 44
ISL81802
Contents
1.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
1.2
1.3
1.4
1.5
2.
Typical Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
6
7
7
8
Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
2.2
2.3
2.4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
5.
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal 8V Linear Regulator (VDD), External Bias Supply (EXTBIAS), and 5V Linear
Regulator (VCC5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable (EN/UVLO) and Soft-Start Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tracking Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Light-Load Efficiency Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prebiased Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Lock Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Synchronization, Multi-Phase Operation and Dithering . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Operation Current Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
24
26
26
28
30
30
30
31
32
33
34
Protection Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.1
5.2
5.3
5.4
5.5
6.
Input Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC5V Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Temperature Protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
35
35
36
36
Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1
6.2
7.
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
General EPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Component Selection Guideline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1
7.2
7.3
7.4
MOSFET Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
39
41
8.
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
R16DS0033EU0101 Rev.1.01
Oct.15.20
Page 3 of 44
Overview
1.1
ISL81802
Typical Application Schematics
9,1
N
5
N
Q
&
X
& Q
5 N
& S
4
1026
8*
(;7%,$6
9,1
&6
(189/2
,021
)%
&203
X+
3+$6(
6675.
%227
9&&9
/*3:0B02'(
8
1&
3*1'
,6/
576 8.6V, EXTBIAS = 0V, IL = 75mA
7.30
7.8
V
VIN = 4.5V, EXTBIAS > 9.0V, IL = 75mA
(Note 10)
7.30
7.8
V
VVDD = 0V, EXTBIAS = 0V, VIN = 12V
120
mA
VVDD = 4.5V, EXTBIAS = 12V, VIN = 4.5V
140
mA
EXTBIAS Supply
Switch Over Threshold Voltage, Rising
VEXT_THR
EXTBIAS voltage
7.10
7.38
7.55
V
Switch Over Threshold Voltage, Falling
VEXT_THF
EXTBIAS voltage
6.60
6.85
7.10
V
VIN UVLO
VIN Rising UVLO Threshold
VUVLOTHR
VIN Falling UVLO Threshold
VUVLOTHF
VIN voltage, 0mA on VCC5V and VDD
VCC5V Rising POR Threshold
VPORTHR
VCC5V voltage, 0mA on VCC5V and VDD
3.7
4.0
4.3
V
VCC5V Falling POR Threshold
VPORTHF
VCC5V voltage, 0mA on VCC5V and VDD
3.30
3.55
3.75
V
3.5
V
3.3
V
VCC5V Power-On Reset
EN/UVLO Threshold
EN1 Rise Threshold
VEN1SS_THR
VIN > 5.6V
0.75
1.05
1.30
V
EN1 Fall Threshold
VEN1SS_THF
VIN > 5.6V
0.60
0.90
1.10
V
EN1 Hysteresis
VEN1SS_HYST
VIN > 5.6V
70
150
300
mV
R16DS0033EU0101 Rev.1.01
Oct.15.20
Page 12 of 44
ISL81802
2. Specifications
Recommended operating conditions unless otherwise noted. See the Block Diagram and Typical Application Schematics. VIN = 4.5V to 80V,
or VDD = 8V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
Parameter
Symbol
Test Conditions
Min
(Note 6)
Typ
Max
(Note 6) Unit
UVLO1 Rise Threshold
VUVLO1_THR
VIN > 5.6V
1.77
1.80
1.83
V
UVLO1 Hysteresis Current
IUVLO1_HYST
VIN = 12V, EN/UVLO = 1.815V
2.5
4.4
6.0
µA
EN2 Rise Threshold
VEN2SS_THR
VIN > 5.6V
0.75
1.05
1.30
V
EN2 Fall Threshold
VEN2SS_THF
VIN > 5.6V
0.60
0.90
1.10
V
EN2 Hysteresis
VEN2SS_HYST
VIN > 5.6V
70
150
300
mV
UVLO2 Rise Threshold
VUVLO2_THR
VIN > 5.6V
1.77
1.80
1.83
V
UVLO2 Hysteresis Current
IUVLO2_HYST
VIN = 12V, EN/UVLO = 1.815V
2.5
4.4
6.0
µA
Soft-Start Current
SS/TRK1 Soft-Start Charge Current
ISS1
SS/TRK = 0V
2.00
µA
SS/TRK2 Soft-Start Charge Current
ISS2
SS/TRK = 0V
2.00
µA
Default Internal Output Ramping Time1
tSS1_MIN
SS/TRK open
1.7
ms
Default Internal Output Ramping Time2
tSS2_MIN
SS/TRK open
1.7
ms
Default Internal Minimum Soft-Starting
Power-Good Monitors
PGOOD Upper Threshold
VPGOV
107
109
112
%
PGOOD Lower Threshold
VPGUV
87
90
92
%
0.35
V
0
150
nA
5
ms
PGOOD Low Level Voltage
PGOOD Leakage Current
VPGLOW
I_SINK = 2mA
IPGLKG
PGOOD = 5V
PGOOD Timing
VOUT Rising Threshold to PGOOD
Rising (Note 9)
tPGR
1.1
VOUT Falling Threshold to PGOOD
Falling
tPGF
80
µs
VREFV
0.800
V
Reference Section
Internal Voltage Loop Reference
Voltage
Reference Voltage Accuracy
Internal Current Loop Reference
Voltage
TA = 0°C to +85°C
-0.75
+0.75
%
TA = -40°C to +125°C
-1.00
+1.00
%
VREFI
Reference Voltage Accuracy
1.200
V
TA = 0°C to +85°C
-0.75
+0.75
%
TA = -40°C to +125°C
-1.00
+1.00
%
+50
nA
PWM Controller Error Amplifiers
FB_1 Pin Bias Current
IFBOUTLKG1
-50
0
FB_1 Error Amp GM
Gm1
1.75
mS
FB_1 Error Amp Voltage Gain
AV1
82
dB
GBW1
8
MHz
300
µA
FB_1 Error Amp Gain-BW Product
FB_1 Error Amp Output Current
Capability
FB_2 Pin Bias Current
FB_2 Error Amp GM
R16DS0033EU0101 Rev.1.01
Oct.15.20
IFBOUTLKG2
Gm2
-50
0
1.75
+50
nA
mS
Page 13 of 44
ISL81802
2. Specifications
Recommended operating conditions unless otherwise noted. See the Block Diagram and Typical Application Schematics. VIN = 4.5V to 80V,
or VDD = 8V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
Parameter
FB_2 Error Amp Voltage Gain
FB_2 Error Amp Gain-BW Product
Symbol
Test Conditions
Min
(Note 6)
Typ
Max
(Note 6) Unit
AV2
82
dB
GBW2
8
MHz
300
µA
FB_2 Error Amp Output Current
Capability
COMP1 Max High Voltage
VCOMP1_HIGH
FB_OUT = 0V
4.7
V
COMP1 Min Low Voltage
VCOMP1_LOW
FB_OUT = 1V
0.01
V
COMP2 Max High Voltage
VCOMP2_HIGH
FB_OUT = 0V
4.7
V
COMP2 Min Low Voltage
VCOMP2_LOW
FB_OUT = 1V
0.01
V
PWM Regulator
PWM1 Minimum Off-Time
tOFF_MIN1
220
ns
PWM1 Minimum On-Time
tON_MIN1
100
ns
PWM2 Minimum Off-Time
tOFF_MIN2
220
ns
PWM2 Minimum On-Time
tON_MIN2
100
ns
PMW1 Peak-to-Peak Sawtooth
Amplitude
DVRAMP1
VIN = VOUT = 12V, fSW = 300kHz
1.0
V
PMW2 Peak-to-Peak Sawtooth
Amplitude
DVRAMP2
VIN = VOUT = 12V, fSW = 300kHz
1.0
V
PMW1 Ramp Offset
VROFFSET1
0.9
1.1
1.25
V
PMW2 Ramp Offset
VROFFSET2
0.9
1.1
1.25
V
Current Sense, Current Monitors, and Average Current Loop
Current Sense1 Differential Voltage
Range
Current Sense1 Common-Mode
Voltage Range
VCS1+ - VCS1-
-80
+150
mV
CMIRCS1
0
80
V
CS1+ Bias Current
CS1+ = CS1- = 12V
3
µA
CS1- Bias Current
CS1+ = CS1- = 12V
400
µA
IMON1 Offset Current
Current Sense1 Voltage to IMON1
Current Source Gain
ICS1OFFSET
GmCS1
CS1+ = CS1- = 12V
17.0
19.5
21.5
µA
12V common-mode voltage applied to
CS1± pins, 0 to 40mV differential voltage
165
200
235
µS
IMON1 Error Amp GM
Gm3
12
µS
IMON1 Error Amp Voltage Gain
AV3
72
dB
IMON1 Active Range (Note 10)
VIMON1_ACT
VCC5V = 5V
VIMON1_H
VCC5V = 5V
IMON1 Logic High Threshold (Note 10)
0
4.3
V
4.7
V
IMON1 Error Amp Gain-BW Product
GBW3
Current Sense2 Differential Voltage
Range
VCS2+ - VCS2-
-80
+150
mV
CMIRCS2
0
80
V
Current Sense2 Common-Mode
Voltage Range
5
MHz
CS2+ Bias Current
CS2+ = CS2- = 12V
3
µA
CS2- Bias Current
CS2+ = CS2- = 12V
400
µA
IMON2 Offset Current
IMON2 Current
R16DS0033EU0101 Rev.1.01
Oct.15.20
ICS2OFFSET
CS2+ = CS2- = 12V
CS2+ = 12V. CS2- = 11.96V
17.0
19
21
µA
25
27.5
28.5
µA
Page 14 of 44
ISL81802
2. Specifications
Recommended operating conditions unless otherwise noted. See the Block Diagram and Typical Application Schematics. VIN = 4.5V to 80V,
or VDD = 8V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
Parameter
Symbol
Current Sense2 Voltage to IMON2
Current Source Gain
GmCS2
Test Conditions
12V common-mode voltage applied to
CS2± pins, 0mV to 40mV differential
voltage
Min
(Note 6)
Typ
165
205
Max
(Note 6) Unit
235
µS
IMON2 Error Amp GM
Gm4
12
µS
IMON2 Error Amp Voltage Gain
AV4
72
dB
GBW4
5
MHz
IMON2 Error Amp Gain-BW Product
Switching Frequency and Synchronization
Switching Frequency
RT Voltage
SYNC Synchronization Range
fSW
VRT
RT = 144kΩ
220
245
265
kHz
RT = 72kΩ
420
450
485
kHz
RT Open or to VCC5V
90
120
145
kHz
RT = 0V
470
575
650
kHz
RT = 72kΩ
fSYNC
560
140
SYNC Input Logic High
VSYNCH
(Note 10)
SYNC Input Logic Low
VSYNCL
(Note 10)
CLKOUT Output High
VCLKH
ISOURCE = 1mA, VCC5V = 5V
CLKOUT Output Low
VCLKL
ISINK = 1mA
CLKOUT Frequency
fCLK
mV
1000
3.2
kHz
V
0.5
V
Clock Output and Frequency Dither
Dither Mode Setting Current Source
IDITHER_MODE_SO
Dither Mode Setting Threshold Low
VDITHER_MODE_L
Dither Mode Setting Threshold High
VDITHER_MODE_H
RT = 72kΩ
4.55
420
V
450
0.3
V
485
kHz
12
µA
0.26
V
0.34
V
Dither Source Current
IDITHERSO
8
µA
Dither Sink Current
IDITHERSI
10
µA
Dither High Threshold Voltage
VDITHERH
2.2
V
Dither Low Threshold Voltage
VDITHERL
1.05
V
Diode Emulation Mode Detection
LG1/PWM_MODE Current Source
IMODELG1
7.5
LG1/PWM_MODE Threshold Low
VMODETHL
0.26
LG1/PWM_MODE Threshold High
VMODETHH
10
13.0
µA
V
0.34
V
PWM1 Diode Emulation Phase
Threshold (Note 11)
VCROSS1
VIN = 12V
0
mV
PWM2 Diode Emulation Phase
Threshold (Note 12)
VCROSS2
VIN = 12V
0
mV
Diode Emulation Burst Mode
PWM1 Burst Mode Enter Threshold
VIMON1BSTEN
IMON1 pin voltage
0.808
0.835
0.860
V
PWM1 Burst Mode Exit Threshold
VMON1BSTEX
IMON1 pin voltage
0.83
0.88
0.92
V
PWM1 Burst Mode Peak Current Limit
Input Shunt Set Point
VBST-CS1
PWM1 Burst Mode Peak FB1 Voltage
Limit Set Point
VBST-VFB1-UTH
R16DS0033EU0101 Rev.1.01
Oct.15.20
VCS1+ - VCS1- , 12V common-mode voltage
applied to CS± pins
27
mV
0.81
V
Page 15 of 44
ISL81802
2. Specifications
Recommended operating conditions unless otherwise noted. See the Block Diagram and Typical Application Schematics. VIN = 4.5V to 80V,
or VDD = 8V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
Parameter
Symbol
Test Conditions
Min
(Note 6)
Typ
Max
(Note 6) Unit
PWM1 Burst Mode Exit FB1 Voltage
Set Point
VBST-VFB1-LTH
0.78
PWM2 Burst Mode Enter Threshold
VIMON2BSTEN
IMON2 pin voltage
0.808
0.835
0.860
V
PWM2 Burst Mode Exit Threshold
VMON2BSTEX
IMON2 pin voltage
0.83
0.88
0.92
V
27
mV
VBST-VFB2-UTH
0.81
V
VBST-VFB2-LTH
0.78
V
PWM2 Burst Mode Peak Current Limit
Input Shunt Set Point
VBST-CS1
PWM2 Burst Mode Peak FB1 Voltage
Limit Set Point
PWM2 Burst Mode Exit FB1 Voltage
Set Point
VCS2+ - VCS2- , 12V common-mode voltage
applied to CS± pins
V
BSTEN Output Logic High
VBSTEN-OH
No load, VCC5V = 5V
4.9
V
BSTEN Output Logic Low
VBSTEN-OL
Pull-up resistance 100kΩ
0.07
V
BSTEN Input Logic High
VBSTEN-IH
(Note 10)
BSTEN Input Logic Low
VBSTEN-IL
(Note 10)
CLKEN Output Logic High
VCLKEN-OH
No load, VCC5V = 5V
4.9
V
CLKEN Output Logic Low
VCLKEN-OL
Pull-up resistance 100kΩ
0.07
V
CLKEN Input Logic High
VCLKEN-IH
(Note 10)
CLKEN Input Logic Low
VCLKEN-IL
(Note 10)
3.2
V
1
3.2
V
V
1
V
6.6
V
PWM Gate Drivers
Driver 1, 2 BOOT Refresh Trip Voltage
VBOOTRF1,2
BOOT voltage - PHASE voltage
5.2
5.85
Driver 1, 2 Source and Upper Sink
Current
IGSRC1,2
2000
mA
Driver 1, 2 Lower Sink Current
IGSNK1,2
3000
mA
Driver 1, 2 Upper Drive Pull-Up
RUG_UP1,2
2.2
Ω
Driver 1, 2 Upper Drive Pull-Down
RUG_DN1,2
1.7
Ω
Driver 1, 2 Lower Drive Pull-Up
RLG_UP1,2
3
Ω
Driver 1, 2 Lower Drive Pull-Down
RLG_DN
2
Ω
Driver 1, 2 Upper Drive Rise Time
tGR_UP
COUT = 1000pF
10
ns
Driver 1, 2 Upper Drive Fall Time
tGF_UP
COUT = 1000pF
10
ns
Driver 1, 2 Lower Drive Rise Time
tGR_DN
COUT = 1000pF
10
ns
Driver 1, 2 Lower Drive Fall Time
tGF_DN
COUT = 1000pF
10
ns
Driver 1, 2 Dead Time
tD_LU
COUT = 1000pF, LG falling edge 1V to UG
rising edge 1V
25
ns
Driver1, 2 Dead Time
tD_UL
COUT = 1000pF, UG falling edge 1V to LG
rising edge 1V
23
ns
Overvoltage Protection
Output OVP Threshold
VOVTH_OUT
112
OV Pin Output Logic High
VOV-OH
Load resistance 100k, VCC5V = 5V
OV Pin Output Logic Low
VOV-OL
No load
OV Pin Input Logic High
VOV-IH
(Note 10)
OV Pin Input Logic Low
VOV-IL
(Note 10)
R16DS0033EU0101 Rev.1.01
Oct.15.20
114
116
%
4.9
V
0
V
3.2
V
1
V
Page 16 of 44
ISL81802
2. Specifications
Recommended operating conditions unless otherwise noted. See the Block Diagram and Typical Application Schematics. VIN = 4.5V to 80V,
or VDD = 8V ±10%, C_VCC5V = 4.7µF, TA = -40°C to +125°C, Typical values are at TA = +25°C, unless otherwise specified.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
Parameter
Symbol
Test Conditions
Min
(Note 6)
Typ
10.5
Max
(Note 6) Unit
Overcurrent Protection
LG2/OC_MODE Current Source
IMODELG2
7.5
LG2/OC_MODE Threshold Low
VMODETHLOC
0.26
LG2/OC_MODE Threshold High
VMODETHHOC
Pulse-by-Pulse Peak Current Limit
Input Shunt Set Point1
VOCSET-CS1
Hiccup Peak Current Limit Input Shunt
Set Point1
VOCSET-CS1-HIC
Pulse-by-Pulse Negative Peak Current
Limit Output Shunt Set Point1
VOCSET-CS1
Output Constant and Hiccup Current
Limit Set Point1
VIMON1CC
Output Constant and Hiccup Current
Limit Set Point at CS1± Input
VAVOCP_CS1
Pulse-by-Pulse Peak Current Limit
Input Shunt Set Point2
VOCSET-CS2
Hiccup Peak Current Limit Input Shunt
Set Point2
VOCSET-CS2-HIC
Pulse-by-Pulse Negative Peak Current
Limit Output Shunt Set Point2
VOCSET-CS2
Output Constant and Hiccup Current
Limit Set Point2
VIMON2CC
Output Constant and Hiccup Current
Limit Set Point at CS2± Input
VAVOCP_CS2
Hiccup OCP Off-Time
VCS1+ - VCS1-, 12V common-mode voltage
applied to CS± pins
68
13.0
µA
V
82
0.34
V
96
mV
VCS1+ - VCS-1
98
mV
VCS1+ - VCS1-, 12V common-mode voltage
applied to ISEN± pins
-60
mV
IMON1 Pin Voltage
1.18
1.2
1.22
V
VCS1+ - VCS1-, 12V common-mode applied
to CS± pins, RIMON1 = 40.2k, TJ = -40°C to
+125°C
43
51
63
mV
VCS1+ - VCS1-, 12V common-mode applied
to CS± pins, RIMON1 = 40.2k, TJ = -40°C to
+85°C
43
51
65
mV
VCS2+ - VCS2-, 12V common-mode voltage
applied to CS± pins
68
82
96
mV
VCS2+ - VCS2-
98
mV
VCS2+ - VCS2-, 12V common-mode voltage
applied to ISEN± pins
-60
mV
IMON2 pin voltage
1.18
1.2
1.22
V
VCS2+ - VCS2-, 12V common-mode applied
to CS± pins, RIMON2 = 40.2k, TJ = -40°C to
+125°C
44
51
65
mV
VCS2+ - VCS2-, 12V common-mode applied
to CS± pins, RIMON2 = 40.2k, TJ = -40°C to
+85°C
44
51
60
mV
tHICC_OFF
55
ms
Over-Temperature Shutdown
TOT-TH
160
°C
Over-Temperature Hysteresis
TOT-HYS
15
°C
Over-Temperature
Notes:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
7. This is the total shutdown current with VIN = 5.6V and 80V.
8. Operating current is the supply current consumed when the device is active but not switching. It does not include gate drive current.
9. When soft-start time is less than 4.5ms, tPGR increases. With internal soft-start (the fastest soft-start time), tPGR increases close to its max
limit 5ms.
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
11. Threshold voltage at the PHASE1 pin for turning off the buck bottom MOSFET during DE mode.
12. Threshold voltage at the PHASE2 pin for turning off the buck bottom MOSFET during DE mode.
R16DS0033EU0101 Rev.1.01
Oct.15.20
Page 17 of 44
ISL81802
3.
3. Typical Performance Curves
Typical Performance Curves
6
6
5
5
Quiescent Current (mA)
Shutdown Current (µA)
Oscilloscope plots are taken using the ISL81802EVAL1Z and ISL81802EVAL2Z evaluation boards,
4
3
2
1
4
3
2
1
0
0
-50
0
50
100
-50
150
0
Figure 6. Shutdown Current vs Temperature
100
150
Figure 7. Quiescent Current vs Temperature
8.00
9
7.95
8
7.90
7
7.85
6
7.80
VDD (V)
VDD (V)
50
Temperature (°)
Temperature (°)
7.75
7.70
5
4
3
7.65
2
7.60
Vin = 12V, Vextbias = 0V
Vin = 4.5V, Vextbias = 12V
7.55
1
0
20
40
60
Vdd vs Vin
Vdd vs Extbias
0
7.50
80
100
0
120
20
IOUT (mA)
40
60
80
100
VIN, Vextbias (V)
Figure 8. VDD Load Regulation at 12V Input
Figure 9. VDD Line Regulation at 20mA Load
5.20
5.08
5.07
5.15
VCC5V (V)
VCC5V (V)
5.06
5.05
5.04
5.03
5.10
5.05
5.02
5.00
5.01
0
20
40
60
80
100
120
IOUT (mA)
Figure 10. VCC5V Load Regulation at 12VIN
R16DS0033EU0101 Rev.1.01
Oct.15.20
140
0
20
40
60
80
100
VIN (V)
Figure 11. VCC5V Line Regulation at 20mA Load
Page 18 of 44
ISL81802
3. Typical Performance Curves
500
210
450
208
Frequency (kHz)
Switching Frequency (kHz)
Oscilloscope plots are taken using the ISL81802EVAL1Z and ISL81802EVAL2Z evaluation boards, (Continued)
400
350
Rt = 144k
Rt = 72k
300
250
206
204
202
200
200
198
-50
0
50
100
150
0
20
40
Temperature (˚C)
60
80
100
VIN (V)
Figure 12. Switching Frequency vs Temperature
Figure 13. Switching Frequency vs VIN, RT = 169k
0.810
1.205
1.2V Reference Voltage (V)
0.8V Reference Voltage (V)
1.204
0.805
0.800
0.795
0.790
1.203
1.202
1.201
1.200
1.199
1.198
1.197
1.196
1.195
-50
0
50
100
150
-50
0
Temperature (°)
Figure 14. 0.8V Reference Voltage vs Temperature
100
150
Figure 15. 1.2V Reference Voltage vs Temperature
120
1.2
100
1.1
80
1.0
IMON1 (V)
Normalized Output Voltage (%)
50
Temperature (°)
60
0.9
40
0.8
20
0.7
0.6
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Soft-Start Pin Voltage (V)
Figure 16. Normalized Output Voltage vs Voltage on
Soft-Start Pin
R16DS0033EU0101 Rev.1.01
Oct.15.20
0
5
10
15
20
IOUT (A)
Figure 17. Dual-Phase Output Current IOUT (DC) vs
IMON1 Pin Voltage, RS_out = 4mΩ, RIMON1 = 20k
Page 19 of 44
ISL81802
3. Typical Performance Curves
Oscilloscope plots are taken using the ISL81802EVAL1Z and ISL81802EVAL2Z evaluation boards, (Continued)
1.2
100
98
1.1
Efficiency (%)
96
IMON (V)
1.0
0.9
0.8
94
92
90
88
86
Vin = 18V
Vin = 36V
Vin = 60V
84
0.7
IMON1
82
IMON2
0.6
Vin = 24V
Vin = 48V
Vin = 80V
80
0
2
4
6
8
12
10
0
5
IOUT (A)
10
15
20
Output Current (A)
Figure 18. Output Current IOUT (DC) vs IMON Pin Voltage,
RS_OUT = 4mΩ, RIMON = 40.2k
Figure 19. CCM Mode Efficiency
11.970
11.946
Vin = 18V
Vin = 36V
Vin = 60V
11.965
Vin = 24V
Vin = 48V
Vin = 80V
11.944
11.942
11.955
11.940
VOUT (V)
11.960
11.950
11.945
11.938
11.936
11.940
11.934
11.935
11.932
11.930
11.930
0
5
10
15
20
25
0
20
40
60
80
100
VIN (V)
Figure 20. CCM Load Regulation at +25°C
Phase 1
20V
Figure 21. CCM Line Regulation at 20A Load +25°C
Phase 1
20V
Phase 2
20V
Phase 2
20V
IL1 5A
IL1 5A
IL2 5A
IL2 5A
2µs/Div
2µs/Div
Figure 22. Dual-Phase Waveforms, VIN = 48V, IOUT = 0A,
CCM Mode
Figure 23. Dual-Phase Waveforms,
VIN = 48V, IOUT = 20A, CCM Mode
R16DS0033EU0101 Rev.1.01
Oct.15.20
Page 20 of 44
ISL81802
3. Typical Performance Curves
Oscilloscope plots are taken using the ISL81802EVAL1Z and ISL81802EVAL2Z evaluation boards, (Continued)
VOUT 100mV
VOUT 1V
IL1 10A
IL1 10A
IL2 10A
IL2 10A
2ms/Div
Figure 24. Dual-Phase Waveforms, VIN = 48V, IOUT = 0-20A
Dynamic, CCM Mode
20ms/Div
Figure 25. Dual-Phase Waveforms, Burst Mode
Waveforms, VIN = 48V, IOUT = 0.1A
VOUT 5V
VOUT 5V
IL1 5A
IL1 10A
IL2 5A
IL2 10A
4ms/Div
Figure 26. Dual-Phase Waveforms, Start-Up Waveform,
VIN = 48V IO = 0A, CCM
4ms/Div
Figure 27. Dual-Phase Waveforms, Start-Up Waveform,
VIN = 48V IO = 20A, CCM
Phase 1
50V
VOUT 10mV
Phase 2
50V
IL1 5A
IL1 10A
IL2 10A
IL2 5A
400µs/Div
2µs/Div
Figure 28. Dual-Phase Burst Mode VIN = 48V, IOUT = 0A
R16DS0033EU0101 Rev.1.01
Oct.15.20
Figure 29. Dual-Output Waveform, VIN = 48V, VOUT1 = 12V,
VOUT2 = 5V, IOUT1 = 0A, IOUT2 = 0A CCM
Page 21 of 44
ISL81802
3. Typical Performance Curves
Oscilloscope plots are taken using the ISL81802EVAL1Z and ISL81802EVAL2Z evaluation boards, (Continued)
VOUT1 200mV
Phase 1
50V
VOUT2 100mV
Phase 2
50V
IL1 10A
IL1 10A
IL2 10A
IL2 10A
2µs/Div
Figure 30. Dual Output Waveform, VIN = 48V, VOUT1 = 12V,
VOUT2 = 5V, IOUT1 = 10A, IOUT2 = 10A CCM
2ms/Div
Figure 31. Dual Output Waveform, VIN = 48V, VOUT1 = 12V,
VOUT2 = 5V, IOUT1 = 0-10A, IOUT2 = 0-10A, Dynamic, CCM
VOUT1 200mV
VOUT1 200mV
VOUT2 100mV
VOUT2 100mV
IL1 10A
IL1 10A
IL2 10A
IL2 10A
1ms/Div
Figure 32. Dual Output Waveforms, Burst Mode
Waveforms, VIN = 48V, IOUT1 = 0.1A, IOUT2 = 0.1A
R16DS0033EU0101 Rev.1.01
Oct.15.20
1ms/Div
Figure 33. Dual Output Waveforms, Start-Up Waveform,
VIN = 48V, VOUT1 = 12V, VOUT2 = 5V, IOUT1 = 0A, IOUT2 = 0A,
CCM
Page 22 of 44
ISL81802
3. Typical Performance Curves
Oscilloscope plots are taken using the ISL81802EVAL1Z and ISL81802EVAL2Z evaluation boards, (Continued)
Phase 1
20V
VOUT1 200mV
VOUT2 100mV
Phase 2
20V
IL1
20A
IL1 10A
IL2
20A
IL2 10A
1ms/Div
40ms/Div
Figure 34. Dual Output Waveforms, Start-Up Waveform,
VIN = 48V, VOUT1 = 12V, VOUT2 = 5V, IOUT1 = 0A, IOUT2 = 0A,
CCM
Figure 35. Dual-Phase OCP Response, HICCUP Mode,
VIN = 48V, VOUT = 12V
14
12
VOUT (V)
10
8
6
4
2
0
0
5
10
15
20
25
30
IOUT (A)
Figure 36. Constant Voltage (CV) and Constant Current (CC) Operation
R16DS0033EU0101 Rev.1.01
Oct.15.20
Page 23 of 44
ISL81802
4.
4.1
4. Functional Description
Functional Description
General Description
The ISL81802 implements dual-buck, dual-phase, and multi-phase controls with a PWM controller, internal
drivers, references, protection circuits, current and voltage control inputs, PLL clock and sync control logic, and
current monitor outputs. See Figure 5.
The ISL81802 is a peak-current mode controller. The two channels can independently control their outputs and
maintain 180° phase shift between in the two PWM outputs. The controller integrates two control loops to regulate
VOUT and average maximum IOUT in each buck channel.
The driver and protection circuits are also integrated in each buck channel to simplify the end design.
The part has an independent enable/disable pins for each buck channel, which provides a flexible power-up
sequencing and a simple VIN UVP implementation. Each buck channel has its own soft-start control. The soft-start
time is programmable by adjusting the soft-start capacitor on the SS/TRK pin.
4.2
Internal 8V Linear Regulator (VDD), External Bias Supply (EXTBIAS), and 5V
Linear Regulator (VCC5V)
The ISL81802 provides two input pins, VIN and EXTBIAS, and two internal LDOs for the VDD gate driver supply.
A third LDO generates VCC5V from VDD. VCC5V provides power to all internal functional circuits other than the
gate drivers. Bypass the linear regulator’s outputs (VDD) with a 10µF capacitor to the power ground. Also, bypass
the third linear regulator output (VCC5V) with a 10µF capacitor to the signal ground. VCC5V is monitored by a
power-on-reset circuit, which disables all regulators when VCC5V falls below 3.5V.
Both LDOs from VIN and EXTBIAS can source over 75mA for VDD to power the gate drivers. When driving large
FETs at a high switching frequency, little or no regulator current may be available for external loads. The LDO
from VDD to VCC5V can also source over 75mA to supply the IC internal circuit. Although the current consumed
by the internal circuit is low, the current supplied by VCC5V to the external loads is limited by VDD. For example,
a single large FET with 15nC total gate charge requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA).
Also, at higher input voltages with larger FETs, the power dissipation across the internal 8V LDO increases.
Excessive power dissipation across this regulator must be avoided to prevent junction temperature rise. Thermal
protection if triggered if the die temperature increases above +160°C due to excessive power dissipation.
When large MOSFETs or high input voltages are used, an external 8V bias voltage can be applied to the
EXTBIAS pin to alleviate excessive power dissipation. When the voltage at the EXTBIAS pin is higher than typical
7.38V, the LDO from EXTBIAS activates and the LDO from VIN is disconnected. The recommended maximum
voltage at the EXTBIAS pin is 36V. For applications with VOUT significantly lower than VIN, EXTBIAS is usually
back biased by VOUT to reduce the LDO power loss. An external UVLO circuit might be necessary to ensure
smooth soft-starting. Renesas recommends adding a 10µF capacitor on the EXTBIAS pin and using a diode to
connect the EXTBIAS pin to VOUT to prevent the EXTBIAS pin voltage from being pulled low due to a VOUT
short-circuit condition.
The two VDD LDOs have an overcurrent limit for short-circuit protection. The VIN to VDD LDO current limit is set
to typical 120mA. The EXTBIAS to VDD LDO current limit is set to a typical 140mA.
4.3
Enable (EN/UVLO) and Soft-Start Operation
ISL81802 provides an enable pin to each of the two buck channels, EN/UVLO1 and EN/UVLO2. Pulling the pin
high or low can enable or disable the corresponding output. When the voltage of either of the two pins is higher
than 1.3V, the three LDOs are enabled. After the VCC5V reaches the POR threshold, the controller is powered up
to initialize its internal circuit. When EN/UVLO1 or EN/UVLO2 is higher than the 1.8V accurate Undervoltage
Lockout (UVLO) threshold, the soft-start circuitry of the corresponding channel becomes active. An internal 2µA
current source begins charging up the soft-start capacitor connected from the corresponding soft-start pin
SS/TRK1 or SS/TRK2/OV to GND. The voltage error amplifier reference voltage is clamped to the voltage on the
SS/TRK1 or SS/TRK2/OV pin. Therefore, the corresponding output voltage rises from 0V to regulation as the
R16DS0033EU0101 Rev.1.01
Oct.15.20
Page 24 of 44
ISL81802
4. Functional Description
soft-start pin rises from 0V to 0.8V. Charging of the soft-start capacitor continues until the voltage on the soft-start
pin reaches 3V. The soft-start pin can also be used for tracking.
The soft-start time is set by the value of the soft-start capacitor connected from the soft-start pin to GND. Inrush
current during start-up is alleviated by adjusting the soft-start time.
The typical soft-start time is set according to Equation 2:
(EQ. 2)
C SS
t SS = 0.8V -----------
2A
When the soft-start time set by external CSS or tracking is less than 1.7ms, an internal soft-start circuit of 1.7ms
takes over the soft-start.
In dual-phase applications, the internal SS/TRK2 signal is disconnected from SS/TRK2/OV pin and internally
connected to SS/TRK1 pin. The VOUT soft-start is controlled by SS/TRK1 pin with a doubled charge current 4µA.
So the external CSS capacitor needs to be doubled to achieve the same soft-start time.
PGOOD toggles high when the Channel 1 output voltage is in regulation.
Pulling both EN/UVLO1 and EN/UVLO2 pins lower than the EN falling threshold VENSS_THF typical 0.9V, disables
the PWM output and internal LDOs to achieve low standby current. The SS/TRK1 and SS/TRK2/OV are also
discharged to GND by an internal MOSFET with 70Ω rDS(ON) in each of the buck channels. For applications with
more than 1µF capacitor on the soft-start pin, Renesas recommends adding a 100Ω to 1kΩ resistor in series with
the capacitor to share the power loss during the discharge.
With the use of the accurate UVLO threshold, an accurate VIN Undervoltage Protection (UVP) feature is
implemented by feeding the VIN into the EN/UVLO pin using a voltage divider, RUV1 and RUV2, shown in Figure 37.
VIN
RUV1
ISL81802
EN/UVLO
RUV2
Figure 37. VIN Undervoltage Protection
The VIN UVP rising threshold is calculated using Equation 3.
(EQ. 3)
V UVLO _ THR R UV1 + R UV2 – 1.4x10 – 6 R UV1 R UV2
V UVRISE = -------------------------------------------------------------------------------------------------------------------------------------------R UV2
where VUVLO_THR is the EN/UVLO pin UVLO rising threshold, typically 1.8V.
The VIN UVP falling threshold is calculated using Equation 4:
(EQ. 4)
V UVLO _ THR R UV1 + R UV2 – I UVLO _ HYST R UV1 R UV2
V UVFALL = ------------------------------------------------------------------------------------------------------------------------------------------------------R UV2
where IUVLO_HYST is the UVLO hysteresis current, typically 3.4µA.
R16DS0033EU0101 Rev.1.01
Oct.15.20
Page 25 of 44
ISL81802
4.4
4. Functional Description
Tracking Operation
Each of the two ISL81802 buck outputs can track an external supply. To implement tracking, connect a resistive
divider between the external supply output and ground. Connect the center point of the divider to the SS/TRK
(SS/TRK1 for Channel 1 and dual-phase or SS/TRK2/OV for Channel 2) pin of the corresponding buck channel.
The resistive divider ratio sets the ramping ratio between the two voltage rails. To implement coincident tracking,
set the tracking resistive divider ratio the same as the output-resistive divider given by Equation 5. Make sure that
the voltage at SS/TRK is greater than 0.8V when the master rail reaches regulation.
To minimize the impact of the 2µA soft-start current on the tracking function, Renesas recommends using
resistors less than 10kΩ for the tracking resistive divider.
When the SS/TRK pin voltage is pulled down to less than 0.3V by the external tracking source, the prebias startup
DE mode function is enabled again. The output voltage may not be able to be pulled down if the load current is not
high enough.
When Overcurrent Protection (OCP) is triggered, the internal minimum soft-start circuit determines the 55ms OCP
soft-start hiccup off-time.
4.5
Control Loops
The ISL81802 integrates two identical buck controllers that provide two output voltages below the input voltage or
one output voltage using two phases. Peak current mode PWM control algorithm is used in the two controllers.
The Renesas proprietary control architecture uses a current sense resistor in series with the inductor to sense the
inductor current (see Figure 1 and Figure 5). By using an RC network, the inductor current signal can also be
derived from the inductor voltage using DCR sensing. The inductor current is controlled by the voltage on the
COMP pin, which is the lowest output of the error amplifiers Gm1 and Gm3 for Channel 1 or Gm2 and Gm4 for
Channel 2. As the simplest example, when the output is regulated to a constant voltage, the FB1 or FB2 pin
receives the output feedback signal, which is compared to the internal reference by Gm1 or Gm2. Lower output
voltage creates higher COMP voltage which leads to a higher PWM duty cycle to deliver more current to the
output. Conversely, higher output voltage creates lower COMP voltage, which leads to a lower PWM duty cycle to
reduce the current delivered to the output.
The ISL81802 has four error amplifiers (Gm1-4), which can control Channel 1 output voltage (Gm1) and current
(Gm3), and Channel 2 output voltage (Gm2) and current (Gm4). In this architecture, both channels can provide
constant voltage and constant current output.
4.5.1
Output Voltage Regulation Loop
The ISL81802 provides a precision 0.8V internal reference voltage to set the output voltage. Based on this
internal reference, the output voltage is set from 0.8V up to a level determined by the feedback voltage divider, as
shown in Figure 38.
A resistive divider from the output to ground sets the output voltage. Connect the center point of the divider to the
FB_OUT pin. The output voltage value is determined by Equation 5.
(EQ. 5)
R FBO1 + R FBO2
V OUT = 0.8V ---------------------------------------------
R FBO2
where RFBO1 is the top resistor of the feedback divider network and RFBO2 is the bottom resistor connected from
FB_OUT to ground, shown in Figure 38.
R16DS0033EU0101 Rev.1.01
Oct.15.20
Page 26 of 44
ISL81802
4. Functional Description
VOUT
RFBO1
FB_OUT
_
+
+
0.8V
_ REF
RFBO2
COMP
Gm1
RCOMP
CCOMP2
CCOMP1
Figure 38. Output Voltage Regulator
As shown in Figure 38, the RCOMP, CCOMP1, and CCOMP2 network connected on the Gm1 regulator output COMP
pin is needed to compensate the loop for stable operation. The loop stability can be affected by many different
factors such as VIN, VOUT, load current, switching frequency, inductor value, output capacitance, and the
compensation network on COMP pin. For most applications 22nF is a good value for CCOMP1. A larger CCOMP1
makes the loop more stable by giving a larger phase margin, but the loop bandwidth is lower. CCOMP2 is typically
1/10th to 1/30th of CCOMP1 to filter high frequency noise. A good starting value for RCOMP is 10k. Lower RCOMP
improves stability but slows the loop response. Optimize the final compensation network with a bench test.
4.5.2
Output Average Current Monitoring and Regulation Loops
The ISL81802 has two current sense amplifiers, A1 and A2, which monitor the output current of both channels.
Figure 39 A shows the ISL81802 Channel 1 current shunt sense and monitor circuit which is identical to Channel
2. The voltage signal on the current sense resistor RS_OUT1 is sent to the differential input of CS1+/CS1-, after the
RC filters RS1/CS1 and RS2/CS2. It is recommended to use a 1Ω value for RS1 and RS2, and a 10nF value for CS1,
and CS2 to effectively damp the switching noise without significantly delaying the current signal or introducing too
much error by the op amp bias current. The A1 amplifier converts the current sense voltage signal to current
signal ICS1.
(EQ. 6)
I CS1 = I OUT1 R S_OUT1 + V CS1OFFSET Gm CS1
where
• IOUT1 is the Channel 1 inductor current
• VCS1OFFSET is the A1 input offset voltage
• GmCS1 is the gain of A1, typical 200µS
• VCS1OFFSET GmCS1 = ICS1OFFSET.
The typical value of ICS1OFFSET is 20µA.
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Oct.15.20
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ISL81802
4. Functional Description
VIN
VIN
UG1
UG1
Q1
Rs_out
L
VOUT
PH1
LG1
Q2
Rs1
LG1
Rs2
Q1
Rdcr
L
VOUT
PH1
Q2
Rs1
Cs1
Cs1
Cs2
CS1+
CS1+
CS1-
Vcs1_offset
A1
A1
Ics1
Ics1
GM3
GM3
+
1.2V _
+
1.2V _
IMON_OUT1
COMP1
Rim
CS1-
Vcs1_offset
Rim1
Cim2
Cim1
A. IOUT Average Current Loop with Shunt Sense
IMON_OUT1
COMP1
Rim
Rim1
Cim2
Cim1
B. IOUT Average Current Loop with DCR Sense
Figure 39. Output Average Current Monitoring and Regulation Loops
By connecting resistor RIM on the IMON1 pin, the ICS1 current signal is transferred to a voltage signal. The RC
network on the IMON1 pin RIM1/CIM1/CIM2 are needed to remove the AC content in the ICS1 signal and ensure
stable loop operation. The average voltages at the IMON1 pin is regulated to 1.2V by Gm3 for constant current
control.
In dual-phase application, the internal IMON2 signal is disconnected from IMON2 pin and internally connected to
IMON1 pin. The ICS1OFFSET is a doubled current 40µA.
The output constant current loop set point IOUTCC1 is calculated by Equation 7. See VAVOCP_CS1 on page 17 in
the Electrical Specifications table to estimate the set point tolerance.
(EQ. 7)
1.2 – I CS1OFFSET xR IM
I OUTCC1 = ---------------------------------------------------------------R IM xR
xGm
S_OUT1
CS1
Similar to the voltage control loop, the average current loop stability can be affected by many different factors
such as VIN, VOUT, switching frequency, inductor value, output and input capacitance, and the RC network on the
IMON1 pin. Due to the AC content in ICS1, a larger CIM1 is needed. Larger CIM1 can also make the loop more
stable by giving a larger phase margin, but the loop bandwidth is lower. For most applications, 47nF is a good
value for CIM1. CIM2 is typically 1/10th to 1/30th of CIM1 to filter high frequency noise. RIM1 is needed to boost the
phase margin. A good starting value for RIM1 is 5k. Optimize the final compensation network with iSim simulation
and bench testing.
Figure 39 B shows the ISL81802 Channel 1 inductor DCR current sense and monitor circuit. Rdcr1 plays the
same role as RS_OUT1 in the shunt current sense circuit. Renesas recommends keeping Rs1 x Cs1 = L1/Rdcr1.
To minimize the error caused by the A1 input bias current, Renesas recommends keeping Rs1 less than 10k.
4.6
Light-Load Efficiency Enhancement
Set each function of the two ISL81802 channels to DE and Burst mode to improve light-load efficiency. The
LG1/PWM_MODE pin sets the DE or PWM mode operation in the initialization period before soft-start. During the
initialization period, a typical 10µA current source IMODELG1 from the LG1/PWM_MODE pin creates a voltage
drop on the resistor RLG1 connected between the LG1/PWM_MODE pin and GND. When the voltage is lower
than the typical 0.3V, PWM mode is set; otherwise, DE mode is set. Note: DE or PWM mode can only be selected
during the initialization period and cannot be changed after initialization is complete.
R16DS0033EU0101 Rev.1.01
Oct.15.20
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ISL81802
4. Functional Description
To set for DE mode operation, select RLG1 to meet:
(EQ. 8)
R LG1 xI MODELG1 0.34V
When DE mode is set, the Channel 1 and 2 buck sync FET driven by LG1 and LG2 are all running in DE mode.
The inductor current is not allowed to reverse (discontinuous operation) depending on the zero cross detection
reference level VCROSS1 for Channel 1 and VCROSS2 for Channel 2 sync FET. At light load conditions, the
converter goes into diode emulation. When the load current is less than the level set by VIMON1BSTEN or
VIMON2BSTEN typical 0.85V on the IMON1 or IMON2 pin, the Channel 1 or 2 enters Burst mode. Equation 9 sets
the Burst mode operation enter condition for Channel 1 as an example (see Figure 39). Same equation also
applies to Channel 2.
(EQ. 9)
R IM x I CS1OFFSET + I OUT1 xR S_OUT1 xGm CS1 V IMON1BSTEN
where:
• ICSOFFSET is the output current sense op amp internal offset current, typical 20µA
• GmCS is the output current sense op amp Gm, typical 200µS.
The part exits Burst mode when the output current increases to higher than the level set by VIMON1BSTEX or
VIMON2BSTEX typical 0.88V on the IMON1 or IMON2 pin. Equation 10 sets the Burst mode operation exit condition
for Channel 1 as en example. Equation 10 also applies to Channel 2.
(EQ. 10)
R IM x I CS1OFFSET + I OUT1 xR S_OUT1 xGm CS1 v IMON1BSTEX
When the part enters Burst mode, the BSTEN pin goes low. To fully avoid any enter/exit chattering, add a 4-10MΩ
resistor between the BSTEN and IMON_OUT pins to further expand the hysteresis.
In Burst mode, an internal window comparator takes control of the output voltage. The comparator monitors the
FB1 or FB2 pin voltage for Channel 1 or 2. When the FB1 or FB2 pin voltage is higher than 0.81V, the Channel 1
or 2 enters Low Power Off mode. Some unneeded internal circuits are powered off to further reduce power
dissipation. When the FB1 or FB2 pin voltage drops to 0.8V, the Channel 1 or 2 wakes up and runs in a fixed level
peak current mode. The fixed level peak current is set by the level that the input current sense amplifier input
voltage reaches VBST-CS1 or VBST-CS2 for Channel 1 or 2, typical 27mV. The output voltage increases in the
wake-up period. When the output reaches 0.82V again, the controller enters into Low Power Off mode again.
When the load current increases, the Low Power Off mode period decreases. When the off mode period
disappears and the load current further increases but still does not meet the Equation 10 exit condition, the output
voltage drops. When the FB1 or FB2 pin voltage drops to 0.78V, Channel 1 or 2 exits Burst mode and runs in
normal DE PWM mode. The voltage error amplifier takes control of the output voltage regulation.
In Low Power Off mode, the CLKEN pin goes low.
The DE and Burst mode operations also apply to dual-phase and multi-phase applications. By connecting the
BSTEN and CLKEN pins in a multiple chip parallel system, the Burst mode enter/exit and burst on/off control are
all synchronized.
Because VOUT is controlled by a window comparator in Burst mode, higher than normal low-frequency voltage
ripple appears on VOUT, which can generate audible noise if the inductor and output capacitors are not chosen
properly. To avoid these drawbacks, disable the Burst mode by choosing a bigger RIM to set the IMON1 pin
voltage higher than 0.88V at no load condition, shown in Equation 11 for Channel 1. Channel 1 runs in DE mode
only. Pulse Skipping mode can also be implemented to lower the light-load power loss with much lower output
voltage ripple as VOUT1 is always controlled by the regulator Gm1. The same approach also applies to Channel 2
and dual-phase operation.
(EQ. 11)
R IM xI CS1OFFSET v IMON1BSTEX
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Oct.15.20
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ISL81802
4.7
4. Functional Description
Prebiased Power-Up
Each of the two ISL81802 channels can soft-start with a prebiased output by running in forced DE mode during
soft-start. The output voltage is not pulled down during prebiased start-up. The PWM mode is not active until the
soft-start ramp reaches 90% of the output voltage set point times the feedback resistive divider ratio. Forced DE
mode is set again when the SS/TRK pin voltage is pulled to less than 0.3V by either an internal or external circuit.
The overvoltage protection function is still operating during soft-start in DE mode.
4.8
Frequency Selection
Switching frequency selection is a trade-off between efficiency and component size. Low switching frequency
improves efficiency by reducing MOSFET switching loss. To meet the output ripple and load transient
requirements, operation at a low switching frequency requires larger inductance and output capacitance. The
switching frequency of the ISL81802 is set by a resistor connected from the RT/SYNC pin to GND according to
Equation 1.
The frequency setting curve shown in Figure 40 assists in selecting the correct value for RT.
3,000
2,500
fSW (kHz)
2,000
1,500
1,000
500
0
0
50
100
150
200
250
RT (k:)
Figure 40. RT vs Switching Frequency fSW
4.9
Phase Lock Loop (PLL)
The ISL81802 integrates a high-performance PLL. The PLL ensures a wide range of accurate clock frequency
and phase setting. It also makes the internal clock easily synchronized to an external clock with the frequency
either lower or higher than the internal setting.
As shown in Figure 41, an external compensation network of RPLL, CPLL1, and CPLL2 is needed to connect to the
PLL_COMP pin to ensure PLL stable operation. Renesas recommends choosing 2.7kΩ for RPLL, 10nF for CPLL1,
and 820pF for CPLL2. With the recommended compensation network, the PLL stability is ensured in the full clock
frequency range of 100kHz to 1MHz.
ISL81802
PLL_COMP
RPLL
CPLL2
CPLL1
Figure 41. PLL Compensation Network
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Oct.15.20
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ISL81802
4.10
4. Functional Description
Frequency Synchronization, Multi-Phase Operation and Dithering
The RT/SYNC pin can synchronize the ISL81802 to an external clock or the CLKOUT/DITHER pin of another
ISL81802. When the RT/SYNC pin is connected to the CLKOUT/DITHER pin of another ISL81802, the two
controllers operate in cascade synchronization with phase interleaving.
When the RT/SYNC pin is connected to an external clock, the ISL81802 synchronizes to this external clock
frequency. The frequency set by the RT resistor can be either lower or higher than, or equal to the external clock
frequency.
The CLKOUT/DITHER pin outputs a clock signal with approximately 300ns pulse width. The signal frequency is
the same as the frequency set by the resistor from the RT pin to ground or the external sync clock. The signal
rising edge phase angle to the rising edge of the internal clock or the external clock to the RT/SYNC pin can be
set by the EN/UVLO2 pin connection and the voltage applied to the IMON2 pin. The phase interleaving can be
implemented by the cascade connecting of the upstream chip CLKOUT/DITHER pin to the downstream chip
RT/SYNC pin in a parallel system. Table 1 shows the CLKOUT/DITHER phase settings with a different
EN/UVLO2 pin connection and IMON2 pin voltage.
Table 1.
CLKOUT and Channel 2 Phase Shift vs EN/UVLO2 and IMON2 Voltage
CLKOUT Phase Shift (°)
Channel 2 Phase Shift (°)
IMON2 Voltage (V)
EN/UVLO2
90°
180°
0-4.3
Tie to EN/UVLO1
60°
180°
4.7-5
Tie to EN/UVLO1
240°
120°
3-5
Tie to SGND
Notes:
13. CLKOUT Phase Shift: CLKOUT rising edge delay after UG1 rising edge.
14. Channel 2 Phase Shift: UG2 rising edge delay after UG1 rising edge.
When IMON2 pin is actively used as Channel 2 current monitor, the pin max voltage is 1.2V. The ISL81802 is
running in dual-output application.
When IMON2 pin is tied to 5V or externally forced to higher than 3V, the ISL81802 is configured for a dual-phase
application. The IMON2 pin internal Channel 2 current signal is connected to IMON1 pin. IMON1 pin monitors the
sum of the Channel 1 and 2 current. The internal current sharing circuit is also enabled. Meanwhile, SS/TRK2/OV
pin internal SS/TRK2 signal is disconnected from the SS/TRK2/OV pin and connected to the SS/TRK1 pin. The
SS/TRK2/OV pin is connected to OVP signal, which is pulled high by a MOSFET with about 4.5k rDS(ON) when
output over voltage fault is triggered. The COMP2/CLKEN pin internal COMP2 signal is disconnected from the
COMP2/CLKEN pin and connected to the COMP1 pin. The COMP2/CLKEN pin is connected to the CLKEN
signal, which is pulled low by a MOSFET with about 4.5k rDS(ON) during burst mode off time. The FB2/BSTEN pin
internal FB2 signal is disconnected from the FB2/BSTEN pin and connected to the FB1 pin. The FB2/BSTEN pin
is connected to BSTEN signal, which is pulled low by a MOSFET with about 4.5k rDS(ON) when the controller
enters into burst mode.
In multi-chip cascade parallel operation, the CLKOUT/DITHER pin of the upstream chip is connected to the
RT/SYNC pin of the downstream chip. The FB1, COMP1, IMON1, EN/UVLO1, SS/TRK1, FB2/BSTEN,
COMP2/CLKEN, and SS/TRK2/OV pins of all the paralleled chips are tied together to implement current sharing,
synchronized start up, burst mode operation, and OVP protection.
The CLKOUT/DITHER pin provides a dual-function option. When a capacitor CDITHER is connected on the
CLKOUT/DITHER pin, the internal circuit disables the CLKOUT function and enables the DITHER function. When
the CLKOUT/DITHER pin voltage is lower than 1.05V, a typical 8µA current source IDITHERSO charges the
capacitor on the pin. When the capacitor voltage is charged to more than 2.2V, a typical 10µA current source
IDITHERSI discharges the capacitor on the pin. A sawtooth voltage waveform shown in Figure 42 is generated on
the CLKOUT/DITHER pin. The internal clock frequency is modulated by the sawtooth voltage on the
CLKOUT/DITHER pin. The clock frequency dither range is set to typically ±15% of the frequency set by the
resistor on the RT/SYNC pin. The dither function is lost when the chip is synchronized to an external clock.
R16DS0033EU0101 Rev.1.01
Oct.15.20
Page 31 of 44
ISL81802
4. Functional Description
ISL81802
CLKOUT/
DITHER
CDITHER
a. Frequency Dithering Operation
1
FDITHER
2.2V
1.05V
b. CLKOUT/DITHER Pin Voltage Waveform in Dither Operation
Figure 42. Frequency Dithering Operation
The dither frequency FDITHER is calculated using Equation 12. Renesas recommends setting CDITHER between
10nF and 1µF. With CDITHER too low, the part may not be able to set to Dither mode. With a higher CDITHER, the
discharge power loss at disable or power off is higher, leading to a higher thermal stress to the internal discharge
circuit. To avoid low frequency ripple, lower the dither frequency to less than 1/10 of the loop bandwidth.
(EQ. 12)
4.11
3.865x10e – 6
F DITHER = ----------------------------------------C DITHER
Parallel Operation Current Sharing
When ISL81802 is set to dual-phase application, the internal Renesas proprietary instant active current sharing
circuit assures the accurate current sharing between the two phases in steady state and start-up or load transient
conditions. Because the current signal from IMON1 is the sum of the two phases, reduce the resistor between the
IMON1 pin and GND to half of the value in a single-phase application. To assure proper parallel operation,
Renesas recommends selecting between 17k and 23k resistance for the resistor between the IMON1 pin and
GND. The RC network is added on the IMON1 pin to filter the ripple noise in the inductor currents and improve the
control loop stability.
Multiple ISL81802 controlled buck converters can be paralleled to each other in cascade as described in
Frequency Synchronization, Multi-Phase Operation and Dithering. The currents in the paralleled converters can
be shared by connecting the IMON1 pin of each controller together to enable the internal Renesas proprietary
instant active current sharing circuit. The 4-phase ISL81802 controlled buck converter is shown in Figure 43. To
minimize the input current and output voltage ripple, the CLKOUT phase delay of the first ISL81802 controller is
programmed to 90° for a perfect phase interleaving.
R16DS0033EU0101 Rev.1.01
Oct.15.20
Page 32 of 44
ISL81802
4. Functional Description
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