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ISL83070EIBZA

ISL83070EIBZA

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    SOIC14

  • 描述:

    IC TRANSCEIVER FULL 1/1 14SOIC

  • 数据手册
  • 价格&库存
ISL83070EIBZA 数据手册
DATASHEET ISL83070E/71E/72E/73E/75E/76E/77E/78E FN6115 Rev 5.00 October 5, 2012 ±15kV ESD Protected, 3.3V, Full Fail-safe, Low Power, High Speed or Slew Rate Limited, RS-485/RS-422 Transceivers The Intersil ISL8307XE are BiCMOS 3.3V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. These devices have very low bus currents (+125mA/-100mA), so they present a true “1/8 unit load” to the RS-485 bus. This allows up to 256 transceivers on the network without violating the RS-485 specification’s 32 unit load maximum, and without using repeaters. For example, in a remote utility meter reading system, individual meter readings are routed to a concentrator via an RS-485 network, so the high allowed node count minimizes the number of repeaters required. Features Receiver (Rx) inputs feature a “Full Fail-Safe” design, which ensures a logic high Rx output if Rx inputs are floating, shorted, or terminated but undriven. • Single 3.3V Supply Hot Plug circuitry ensures that the Tx and Rx outputs remain in a high impedance state while the power supply stabilizes. The ISL83070E through ISL83075E utilize slew rate limited drivers which reduce EMI, and minimize reflections from improperly terminated transmission lines, or unterminated stubs in multidrop and multipoint applications. Slew rate limited versions also include receiver input filtering to enhance noise immunity in the presence of slow input signals. The ISL83070E, ISL83071E, ISL83073E, ISL83076E, ISL83077E are configured for full duplex (separate Rx input and Tx output pins) applications. The half duplex versions multiplex the Rx inputs and Tx outputs to allow transceivers with output disable functions in 8 lead packages. • Pb-Free (RoHS Compliant) • RS-485 I/O Pin ESD Protection  15kV HBM - Class 3 ESD Level on all Other Pins . . . . . . >7kV HBM • Full Fail-safe (Open, Short, Terminated/Floating) Receivers • Hot Plug - Tx and Rx Outputs Remain Three-state During Power-up (Only Versions with Output Enable Pins) • True 1/8 Unit Load Allows up to 256 Devices on the Bus • High Data Rates . . . . . . . . . . . . . . . . . . . . . . up to 20Mbps • Low Quiescent Supply Current . . . . . . . . . . .800A (Max) - Ultra Low Shutdown Supply Current . . . . . . . . . . .10nA • -7V to +12V Common Mode Input/Output Voltage Range • Half and Full Duplex Pinouts • Three State Rx and Tx Outputs Available • Current Limiting and Thermal Shutdown for driver Overload Protection • Tiny MSOP package offering saves 50% board space Applications • Automated Utility Meter Reading Systems • High Node Count Systems • Field Bus Networks • Security Camera Networks • Building Environmental Control/ Lighting Systems • Industrial/Process Control Networks TABLE 1. SUMMARY OF FEATURES PART NUMBER HALF/FULL DATA RATE DUPLEX (Mbps) SLEW-RATE LIMITED? HOT PLUG? # DEVICES ON BUS RX/TX ENABLE? QUIESCENT ICC (A) LOW POWER SHUTDOWN? PIN COUNT ISL83070E FULL 0.25 YES YES 256 YES 510 YES 14 ISL83071E FULL 0.25 YES NO 256 NO 510 NO 8 ISL83072E HALF 0.25 YES YES 256 YES 510 YES 8 ISL83073E FULL 0.5 YES YES 256 YES 510 YES 14 ISL83075E HALF 0.5 YES YES 256 YES 510 YES 8 ISL83076E FULL 20 NO YES 256 YES 510 YES 14 ISL83077E FULL 20 NO NO 256 NO 510 NO 8 ISL83078E HALF 20 NO YES 256 YES 510 YES 8 FN6115 Rev 5.00 October 5, 2012 Page 1 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Pinouts RO 1 8 VCC VCC 1 RE 2 7 B/Z DE 3 6 A/Y 5 GND DI 4 R D ISL83070E, ISL83073E, ISL83076E (14 LD SOIC) TOP VIEW ISL83071E, ISL83077E (8 LD SOIC) TOP VIEW ISL83072E, ISL83075E, ISL83078E (8 LD MSOP, SOIC) TOP VIEW 8 A RO 2 7 B DI 3 6 Z 5 Y GND 4 R D 14 VCC NC 1 RO 2 13 NC R RE 3 11 B DE 4 DI 5 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL83070EIBZA 83070EIBZ TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # -40 to 85 14 Ld SOIC M14.15 M8.15 ISL83072EIBZA 83072 EIBZ -40 to 85 8 Ld SOIC M8.15 ISL83072EIUZA 3072Z -40 to 85 8 Ld MSOP M8.118 ISL83073EIBZA 83073EIBZ -40 to 85 14 Ld SOIC M14.15 ISL83075EIBZA 83075 EIBZ -40 to 85 8 Ld SOIC GND 6 9 Y GND 7 8 NC TRANSMITTING INPUTS -40 to 85 8 Ld MSOP M8.118 ISL83076EIBZA 83076EIBZ -40 to 85 14 Ld SOIC M14.15 ISL83077EIBZA 83077 EIBZ -40 to 85 8 Ld SOIC M8.15 ISL83078EIBZA 83078 EIBZ -40 to 85 8 Ld SOIC M8.15 -40 to 85 8 Ld MSOP M8.118 NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL83070E, ISL83071E, ISL83072E, ISL83073E, ISL83075E, ISL83076E, ISL83077E, ISL83078E. For more information on MSL please see tech brief TB363. OUTPUTS RE DE DI Z Y X 1 1 0 1 X 1 0 1 0 0 0 X High-Z High-Z 1 0 X High-Z* High-Z* M8.15 ISL83075EIUZA 3075Z FN6115 Rev 5.00 October 5, 2012 10 Z D Truth Tables ISL83071EIBZA 83071 EIBZ -40 to 85 8 Ld SOIC ISL83078EIUZA 3078Z 12 A NOTE: *Shutdown Mode (See Note 10), except for ISL83071E/77E RECEIVING INPUTS RE DE DE Half Duplex Full Duplex OUTPUT A-B RO 0 0 X  -0.05V 1 0 0 X  -0.2V 0 0 0 X Inputs Open/Shorted 1 1 0 0 X High-Z* 1 1 1 X High-Z NOTE: *Shutdown Mode (See Note 10), except for ISL83071E/77E Page 2 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Pin Descriptions PIN FUNCTION RO Receiver output: If A - B  -50mV, RO is high; If A - B  -200mV, RO is low; RO = High if A and B are unconnected (floating) or shorted. RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. If the Rx enable function isn’t required, connect RE directly to GND or through a 1k to 3k resistor to GND. DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high, and are high impedance when DE is low. If the Tx enable function isn’t required, connect DE to VCC through a 1k to 3k resistor. DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. GND Ground connection. A/Y 15kV HBM ESD Protected RS-485/RS-422 level, noninverting receiver input and noninverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. B/Z 15kV HBM ESD Protected RS-485/RS-422 level, Inverting receiver input and inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. A 15kV HBM ESD Protected RS-485/RS-422 level, noninverting receiver input. B 15kV HBM ESD Protected RS-485/RS-422 level, inverting receiver input. Y 15kV HBM ESD Protected RS-485/RS-422 level, noninverting driver output. Z 15kV HBM ESD Protected RS-485/RS-422 level, inverting driver output. VCC System power supply input (3.0V to 3.6V). NC No Connection. FN6115 Rev 5.00 October 5, 2012 Page 3 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Typical Operating Circuits +3.3V +3.3V + 8 0.1µF 0.1µF + 8 VCC 1 RO VCC R D 2 RE B/Z 7 3 DE A/Y 6 4 DI RT RT DI 4 7 B/Z DE 3 6 A/Y RE 2 RO 1 R D GND GND 5 5 ISL83072E, ISL83075E, ISL83078E +3.3V +3.3V + 1 0.1µF 0.1µF + 1 VCC RT A 8 2 RO 3 DI VCC R B 7 RT Z 6 Y 6 Z D 7 B Y 5 D 5 RO 2 R 8 A GND GND 4 4 DI 3 ISL83071E, ISL83077E +3.3V +3.3V + 14 VCC 2 RO R A 12 0.1µF 0.1µF RT + 14 VCC 9 Y B 11 D 10 Z 3 RE DE 4 RE 3 4 DE 5 DI DI 5 RT Z 10 Y 9 D 11 B R 12 A GND RO 2 GND 6, 7 6, 7 ISL83070E, ISL83073E, ISL83076E FN6115 Rev 5.00 October 5, 2012 Page 4 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltages DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V DE, RE (Note 20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Input/Output Voltages A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9V to +13V RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC +0.3V) Short Circuit Duration Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table Thermal Resistance (Typical, Note 4) JA (°C/W) 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 105 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 140 14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 128 Maximum Junction Temperature (Plastic Package) . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications PARAMETER Test Conditions: VCC = 3.0V to 3.6V; Unless Otherwise Specified. Typicals are at VCC = 3.3V, TA = +25°C (Note 5). SYMBOL TEST CONDITIONS TEMP (°C) MIN (Note 19) TYP MAX (Note 19) UNITS DC CHARACTERISTICS Driver Differential VOUT VOD RL = 100 (RS-422) (Figure 1A, Note 16) Full 2 2.3 - V RL = 54 (RS-485) (Figure 1A) Full 1.5 2 VCC V - - VCC No Load Change in Magnitude of Driver Differential VOUT for Complementary Output States Driver Common-Mode VOUT Change in Magnitude of Driver Common-Mode VOUT for Complementary Output States Logic Input High Voltage Logic Input Low Voltage Logic Input Hysteresis RL = 60, -7V  VCM  12V (Figure 1B) Full 1.5 2.2 - V VOD RL = 54 or 100 (Figure 1A) Full - 0.01 0.2 V VOC RL = 54 or 100 (Figure 1A) Full - 2 3 V VOC RL = 54 or 100 (Figure 1A) Full - 0.01 0.2 V VIH DI, DE, RE Full 2 - - V VIL DI, DE, RE Full - - 0.8 V DE, RE, (Note 15) 25 - 100 - mV VHYS Logic Input Current IIN1 DI = DE = RE = 0V or VCC, (Note 18) Full -2 - 2 A Input Current (A, B, A/Y, B/Z) IIN2 DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 80 125 A VIN = -7V Full -100 -50 - A RE = 0V, DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 10 40 A VIN = -7V Full -40 -10 - A VIN = 12V Full - 10 40 A VIN = -7V Full -40 -10 - A DE = VCC, -7V  VY or VZ  12V (Note 7) Full - - 250 mA -7V  VCM  12V Full -200 -125 -50 mV VCM = 0V 25 - 15 - mV Output Leakage Current (Y, Z) (Full Duplex Versions Only, Note 13) IIN3 Output Leakage Current (Y, Z) in Shutdown Mode (Full Duplex, Note 13) IIN4 Driver Short-Circuit Current, VO = High or Low Receiver Differential Threshold Voltage Receiver Input Hysteresis FN6115 Rev 5.00 October 5, 2012 IOSD1 VTH VTH RE = VCC, DE = 0V, VCC = 0V or 3.6V Page 5 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Electrical Specifications Test Conditions: VCC = 3.0V to 3.6V; Unless Otherwise Specified. Typicals are at VCC = 3.3V, TA = +25°C (Note 5). (Continued) PARAMETER Receiver Output High Voltage SYMBOL TEST CONDITIONS TEMP (°C) MIN (Note 19) TYP MAX (Note 19) UNITS VCC - 0.6 - - VOH IO = -4mA, VID = -50mV Full Receiver Output Low Voltage VOL IO = -4mA, VID = -200mV Full - 0.17 0.4 V Three-State (high impedance) Receiver Output Current (Note 13) IOZR 0.4V  VO  2.4V Full -1 0.015 1 A Receiver Input Resistance RIN -7V  VCM  12V Full 96 150 - k 0V  VO  VCC Full 7 30 60 mA Full - 150 - °C DE = VCC, RE = 0V or VCC Full - 510 800 A DE = 0V, RE = 0V Full - 480 700 A DE = 0V, RE = VCC, DI = 0V or VCC Full - 0.01 1 A RS-485 Pins (A, Y, B, Z) Human Body Model (HBM), Pin to GND 25 - 15 - kV All Other Pins HBM, per MIL-STD-883 Method 3015 25  7 - kV VOD = 1.5V, CD = 820pF (Figure 4, Note 17) Full 250 800 - kbps Receiver Short-Circuit Current IOSR Thermal Shutdown Threshold TSD V SUPPLY CURRENT No-Load Supply Current (Note 6) Shutdown Supply Current (Note 13) ICC ISHDN DI = 0V or VCC ESD PERFORMANCE DRIVER SWITCHING CHARACTERISTICS (ISL83070E, ISL83071E, ISL83072E, 250kbps) Maximum Data Rate fMAX Driver Differential Output Delay tDD RDIFF = 54, CD = 50pF (Figure 2) Full 250 1100 1500 ns Driver Differential Output Skew tSKEW RDIFF = 54, CD = 50pF (Figure 2) Full - 6 100 ns tR, tF RDIFF = 54, CD = 50pF (Figure 2) Full 350 960 1600 ns Driver Differential Rise or Fall Time Driver Enable to Output High tZH RL = 500, CL = 50pF, SW = GND (Figure 3), (Notes 8, 13) Full - 26 600 ns Driver Enable to Output Low tZL RL = 500, CL = 50pF, SW = VCC (Figure 3), (Notes 8, 13) Full - 200 600 ns Driver Disable from Output High tHZ RL = 500, CL = 50pF, SW = GND (Figure 3), (Note 13) Full - 28 55 ns Driver Disable from Output Low tLZ RL = 500, CL = 50pF, SW = VCC (Figure 3), (Note 13) Full - 30 55 ns (Notes 10, 13) Full 50 200 600 ns Time to Shutdown tSHDN Driver Enable from Shutdown to Output High tZH(SHDN) RL = 500, CL = 50pF, SW = GND (Figure 3), (Notes 10, 11, 13) Full - 180 700 ns Driver Enable from Shutdown to Output Low tZL(SHDN) RL = 500, CL = 50pF, SW = VCC (Figure 3), (Notes 10, 11, 13) Full - 100 700 ns VOD = 1.5V, CD = 820pF (Figure 4, Note 17) Full 500 1600 - kbps DRIVER SWITCHING CHARACTERISTICS (ISL83073E, ISL83075E, 500kbps) Maximum Data Rate fMAX Driver Differential Output Delay tDD RDIFF = 54, CD = 50pF (Figure 2) Full 180 350 800 ns Driver Differential Output Skew tSKEW RDIFF = 54, CD = 50pF (Figure 2) Full - 1 30 ns tR, tF Driver Differential Rise or Fall Time RDIFF = 54, CD = 50pF (Figure 2) Full 200 380 800 ns Driver Enable to Output High tZH RL = 500, CL = 50pF, SW = GND (Figure 3), (Notes 8, 13) Full - 26 350 ns Driver Enable to Output Low tZL RL = 500, CL = 50pF, SW = VCC (Figure 3), (Notes 8, 13) Full - 100 350 ns FN6115 Rev 5.00 October 5, 2012 Page 6 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Electrical Specifications Test Conditions: VCC = 3.0V to 3.6V; Unless Otherwise Specified. Typicals are at VCC = 3.3V, TA = +25°C (Note 5). (Continued) PARAMETER TEMP (°C) MIN (Note 19) TYP RL = 500, CL = 50pF, SW = GND (Figure 3), (Note 13) Full - 28 55 ns RL = 500, CL = 50pF, SW = VCC (Figure 3), (Note 13) Full - 30 55 ns (Notes 10, 13) Full 50 200 600 ns SYMBOL TEST CONDITIONS Driver Disable from Output High tHZ Driver Disable from Output Low tLZ Time to Shutdown tSHDN MAX (Note 19) UNITS Driver Enable from Shutdown to Output High tZH(SHDN) RL = 500, CL = 50pF, SW = GND (Figure 3), (Notes 10, 11, 13) Full - 180 700 ns Driver Enable from Shutdown to Output Low tZL(SHDN) RL = 500, CL = 50pF, SW = VCC (Figure 3), (Notes 10, 11, 13) Full - 100 700 ns VOD = 1.5V, CD = 350pF (Figure 4, Note 17) Full 20 28 - Mbps DRIVER SWITCHING CHARACTERISTICS (ISL83076E, ISL83077E, ISL83078E, 20Mbps) Maximum Data Rate fMAX Driver Differential Output Delay tDD RDIFF = 54, CD = 50pF (Figure 2) Full - 27 40 ns Driver Differential Output Skew tSKEW RDIFF = 54, CD = 50pF (Figure 2) Full - 1 3 ns Driver Output Skew, Part-to-Part Driver Differential Rise or Fall Time tDSKEW tR, tF RDIFF = 54, CD = 50pF (Figure 2, Note 14) Full - - 11 ns RDIFF = 54, CD = 50pF (Figure 2) Full - 9 15 ns Driver Enable to Output High tZH RL = 500, CL = 50pF, SW = GND (Figure 3), (Notes 8, 13) Full - 17 50 ns Driver Enable to Output Low tZL RL = 500, CL = 50pF, SW = VCC (Figure 3), (Notes 8, 13) Full - 16 40 ns Driver Disable from Output High tHZ RL = 500, CL = 50pF, SW = GND (Figure 3), (Note 13) Full - 25 40 ns Driver Disable from Output Low tLZ RL = 500, CL = 50pF, SW = VCC (Figure 3), (Note 13) Full - 28 50 ns (Notes 10, 13) Full 50 200 600 ns Time to Shutdown tSHDN Driver Enable from Shutdown to Output High tZH(SHDN) RL = 500, CL = 50pF, SW = GND (Figure 3), (Notes 10, 11, 13) Full - 180 700 ns Driver Enable from Shutdown to Output Low tZL(SHDN) RL = 500, CL = 50pF, SW = VCC (Figure 3), (Notes 10, 11, 13) Full - 90 700 ns ISL83070E-75E Full 12 20 - Mbps ISL83076E-78E Full 20 35 - Mbps ISL83070E-75E Full 25 70 120 ns ISL83076E-78E Full 25 33 60 ns (Figure 5) Full - 1.5 4 ns (Figure 5, Note 14) Full - - 15 ns RECEIVER SWITCHING CHARACTERISTICS (All Versions) Maximum Data Rate Receiver Input to Output Delay Receiver Skew | tPLH - tPHL | Receiver Skew, Part-to-Part Receiver Enable to Output High Receiver Enable to Output Low Receiver Disable from Output High FN6115 Rev 5.00 October 5, 2012 fMAX tPLH, tPHL tSKD tRSKEW tZH tZL tHZ VID = 1.5V (Note 17) (Figure 5) RL = 1k, CL = 15pF, SW = GND (Figure 6), (Notes 9, 13) ISL83070E-75E Full 5 15 20 ns ISL83076E-78E Full 5 11 17 ns RL = 1k, CL = 15pF, SW = VCC (Figure 6), (Notes 9, 13) ISL83070E-75E Full 5 15 20 ns ISL83076E-78E Full 5 11 17 ns RL = 1k, CL = 15pF, SW = GND (Figure 6), (Note 13) ISL83070E-75E Full 5 12 20 ns ISL83076E-78E Full 4 7 15 ns Page 7 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Electrical Specifications Test Conditions: VCC = 3.0V to 3.6V; Unless Otherwise Specified. Typicals are at VCC = 3.3V, TA = +25°C (Note 5). (Continued) PARAMETER SYMBOL Receiver Disable from Output Low tLZ Time to Shutdown RL = 1k, CL = 15pF, SW = VCC (Figure 6), (Note 13) tSHDN TEMP (°C) MIN (Note 19) TYP ISL83070E-75E Full 5 13 20 ns ISL83076E-78E Full 4 7 15 ns TEST CONDITIONS (Notes 10, 13) MAX (Note 19) UNITS Full 50 180 600 ns Receiver Enable from Shutdown to Output High tZH(SHDN) RL = 1k, CL = 15pF, SW = GND (Figure 6), (Notes 10, 12, 13) Full - 240 500 ns Receiver Enable from Shutdown to Output Low tZL(SHDN) RL = 1k, CL = 15pF, SW = VCC (Figure 6), (Notes 10, 12, 13) Full - 240 500 ns NOTES: 5. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 6. Supply current specification is valid for loaded drivers when DE = 0V. 7. Applies to peak current. See “Typical Performance Curves” for more information. 8. When testing devices with the shutdown feature, keep RE = 0 to prevent the device from entering SHDN. 9. When testing devices with the shutdown feature, the RE signal high time must be short enough (typically 600ns to ensure that the device enters SHDN. 12. Set the RE signal high time >600ns to ensure that the device enters SHDN. 13. Does not apply to the ISL83071E and ISL83077E. 14. tSKEW is the magnitude of the difference in propagation delays of the specified terminals of two units tested with identical test conditions (VCC, temperature, etc.). Only applies to the ISL83076E - 78E. 15. ISL83070E - ISL83075E only. 16. VCC 3.15V 17. Limits established by characterization and are not production tested. 18. If the Tx or Rx enable function isn’t needed, connect the enable pin to the appropriate supply (see “Pin Descriptions” table) through a 1k to 3k resistor. 19. Parts are 100% tested at +25°C. Full temperature limits are guaranteed by bench and tester characterization. 20. If the DE or RE input voltage exceeds the VCC voltage by more than 500mV, then current will flow into the logic pin. The current is limited by a 340Ω resistor (so ≈13mA with VIN = 5V and VCC = 0V) so no damage will occur if VCC ≤ VIN ≤ 7V for short periods of time. Test Circuits and Waveforms VCC RL/2 DE DI VCC Z DI VOD D 375Ω DE Z VOD D Y Y RL/2 FIGURE 1A. VOD AND VOC VOC RL = 60Ω VCM -7V TO +12V 375Ω FIGURE 1B. VOD WITH COMMON MODE LOAD FIGURE 1. DC DRIVER TEST CIRCUITS FN6115 Rev 5.00 October 5, 2012 Page 8 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Test Circuits and Waveforms (Continued) 3V DI 1.5V 1.5V 0V VCC tPHL tPLH DE Z DI RDIFF D CD Y SIGNAL GENERATOR OUT (Z) VOH OUT (Y) VOL 90% DIFF OUT (Y - Z) +VOD 90% 10% 10% tR -VOD tF SKEW = |tPLH - tPHL| FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES DE Z DI 500Ω VCC D SIGNAL GENERATOR SW Y GND 50pF 3V DE NOTE 10 1.5V 1.5V 0V tZH, tZH(SHDN) PARAMETER OUTPUT RE DI SW tHZ Y/Z X 1/0 GND tLZ Y/Z X 0/1 VCC tZH Y/Z 0 (Note 8) 1/0 GND tZL Y/Z 0 (Note 8) 0/1 VCC tZH(SHDN) Y/Z 1 (Note 11) 1/0 GND tZL(SHDN) Y/Z 1 (Note 11) 0/1 VCC OUTPUT HIGH NOTE 10 tHZ VOH - 0.25V 50% OUT (Y, Z) VOH 0V tZL, tZL(SHDN) tLZ NOTE 10 VCC OUT (Y, Z) 50% OUTPUT LOW FIGURE 3A. TEST CIRCUIT VOL + 0.25V V OL FIGURE 3B. MEASUREMENT POINTS FIGURE 3. DRIVER ENABLE AND DISABLE TIMES (EXCEPT ISL83071E, ISL83077E) VCC DE + Z DI 54Ω D CD Y SIGNAL GENERATOR 3V DI VOD 0V - +VOD DIFF OUT (Y - Z) -VOD FIGURE 4A. TEST CIRCUIT 0V FIGURE 4B. MEASUREMENT POINTS FIGURE 4. DRIVER DATA RATE FN6115 Rev 5.00 October 5, 2012 Page 9 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Test Circuits and Waveforms (Continued) +1.5V RE GND A 15pF B R A 0V 0V RO -1.5V tPLH tPHL VCC SIGNAL GENERATOR 1.5V RO 1.5V 0V FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS FIGURE 5. RECEIVER PROPAGATION DELAY RE GND B A R 1kΩ RO SW SIGNAL GENERATOR NOTE 10 VCC GND RE 3V 1.5V 1.5V 15pF 0V tZH, tZH(SHDN) NOTE 10 PARAMETER DE A OUTPUT HIGH tHZ V VOH - 0.25V OH SW 1.5V RO tHZ X +1.5V GND tLZ X -1.5V VCC tZH (Note 9) 0 +1.5V GND tZL, tZL(SHDN) tZL (Note 9) 0 -1.5V VCC NOTE 10 tZH(SHDN) (Note 12) 0 +1.5V GND RO tZL(SHDN) (Note 12) 0 -1.5V VCC 0V tLZ VCC 1.5V OUTPUT LOW FIGURE 6A. TEST CIRCUIT VOL + 0.25V V OL FIGURE 6B. MEASUREMENT POINTS FIGURE 6. RECEIVER ENABLE AND DISABLE TIMES (EXCEPT ISL83071E, ISL83077E) Application Information Receiver Features RS-485 and RS-422 are differential (balanced) data transmission standards for use in long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 transceivers are also RS-422 compliant. RS-422 is a pointto-multipoint (multidrop) standard, which allows only one driver and up to 10 (assuming one unit load devices) receivers on each bus. RS-485 is a true multipoint standard, which allows up to 32 one unit load devices (any combination of drivers and receivers) on each bus. To allow for multipoint operation, the RS-485 spec requires that drivers must handle bus contention without sustaining any damage. These devices utilize a differential input receiver for maximum noise immunity and common mode rejection. Input sensitivity is better than 200mV, as required by the RS-422 and RS-485 specifications. Another important advantage of RS-485 is the extended common mode range (CMR), which specifies that the driver outputs and receiver inputs withstand signals that range from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000’, so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields. FN6115 Rev 5.00 October 5, 2012 Receiver input resistance of 96k surpasses the RS-422 spec of 4k, and is eight times the RS-485 “Unit Load (UL)” requirement of 12k minimum. Thus, these products are known as “one-eighth UL” transceivers, and there can be up to 256 of these devices on a network while still complying with the RS-485 loading spec. Receiver inputs function with common mode voltages as great as +9V/-7V outside the power supplies (i.e., +12V and -7V), making them ideal for long networks where induced voltages, and ground potential differences, are realistic concerns. All the receivers include a “full fail-safe” function that guarantees a high level receiver output if the receiver inputs are unconnected (floating) or shorted. Fail-safe with shorted inputs is achieved by setting the Rx upper switching point to -50mV, thereby ensuring that the Rx sees 0V differential as a high input level. Page 10 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Receivers easily meet the data rates supported by the corresponding driver, and all receiver outputs (except on the ISL83071E and ISL83077E) are tri-statable via the active low RE input. Driver Features The RS-485, RS-422 driver is a differential output device that delivers at least 1.5V across a 54 load (RS-485), and at least 2V across a 100 load (RS-422). The drivers feature low propagation delay skew to maximize bit width, and to minimize EMI. All drivers are tri-statable via the active high DE input, except on the ISL83071E and ISL83077E. The 250kbps and 500kbps driver outputs are slew rate limited to minimize EMI, and to reduce reflections in unterminated or improperly terminated networks. Outputs of the ISL83076E through ISL83078E drivers are not limited, so faster output transition times allow data rates of at least 20Mbps. Hot Plug Function When a piece of equipment powers up, there is a period of time where the processor or ASIC driving the RS-485 control lines (DE, RE) is unable to ensure that the RS-485 Tx and Rx outputs are kept disabled. If the equipment is connected to the bus, a driver activating prematurely during power up may crash the bus. To avoid this scenario, the ISL8307XE versions with output enable pins incorporate a “Hot Plug” function. During power up, circuitry monitoring VCC ensures that the Tx and Rx outputs remain disabled for a period of time, regardless of the state of DE and RE. This gives the processor/ASIC a chance to stabilize and drive the RS-485 control lines to the proper states. ESD Protection All pins on these devices include class 3 (>7kV) Human Body Model (HBM) ESD protection structures, but the RS-485 pins (driver outputs and receiver inputs) incorporate advanced structures allowing them to survive ESD events in excess of 15kV HBM. The RS-485 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect without allowing any latchup mechanism to activate, and without degrading the RS-485 common mode range of -7V to +12V. This built-in ESD protection eliminates the need for board level protection structures (e.g., transient suppression diodes), and the associated, undesirable capacitive load they present. Data Rate, Cables, and Terminations RS-485, RS-422 are intended for network lengths up to 4000’, but the maximum system data rate decreases as the transmission length increases. Devices operating at 20Mbps are limited to lengths less than 100’, while the 250kbps FN6115 Rev 5.00 October 5, 2012 versions can operate at full data rates with lengths of several thousand feet. Twisted pair is the cable of choice for RS-485, RS-422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in these ICs. Proper termination is imperative, when using the 20Mbps devices, to minimize reflections. Short networks using the 250kbps versions need not be terminated, but, terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-to-multipoint (single driver on bus) networks, the main cable should be terminated in its characteristic impedance (typically 120) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transceiver to the main cable should be kept as short as possible. Built-In Driver Overload Protection As stated previously, the RS-485 spec requires that drivers survive worst case bus contentions undamaged. These devices meet this requirement via driver output short circuit current limits, and on-chip thermal shutdown circuitry. The driver output stages incorporate short circuit current limiting circuitry which ensures that the output current never exceeds the RS-485 spec, even at the common mode voltage range extremes. Additionally, these devices utilize a foldback circuit which reduces the short circuit current, and thus the power dissipation, whenever the contending voltage exceeds either supply. In the event of a major short circuit condition, devices also include a thermal shutdown feature that disables the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically re-enable after the die temperature drops about +15°. If the contention persists, the thermal shutdown/re-enable cycle repeats until the fault is cleared. Receivers stay operational during thermal shutdown. Low Power Shutdown Mode These CMOS transceivers all use a fraction of the power required by their bipolar counterparts, but some also include a shutdown feature that reduces the already low quiescent ICC to a 10nA trickle. These devices enter shutdown whenever the receiver and driver are simultaneously disabled (RE = VCC and DE = GND) for a period of at least 600ns. Disabling both the driver and the receiver for less than 50ns guarantees that the transceiver will not enter shutdown. Note that receiver and driver enable times increase when the transceiver enables from shutdown. Refer to Notes 8 through 12, at the end of the “Electrical Specifications” table on page 8 for more information. Page 11 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Typical Performance Curves VCC = 3.3V, TA = +25°C; Unless Otherwise Specified 2.35 DIFFERENTIAL OUTPUT VOLTAGE (V) DRIVER OUTPUT CURRENT (mA) 120 100 80 60 40 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 DIFFERENTIAL OUTPUT VOLTAGE (V) 2.25 RDIFF = 100Ω 2.20 2.15 2.10 2.05 2.00 RDIFF = 54Ω 1.95 1.90 1.85 -40 3.5 -25 0 50 25 75 85 TEMPERATURE (°C) FIGURE 7. DRIVER OUTPUT CURRENT vs DIFFERENTIAL OUTPUT VOLTAGE FIGURE 8. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs TEMPERATURE 200 0.52 ISL83072/75/78E, DE = VCC, RE = X ISL83076E/77/78E 150 0.51 Y OR Z = LOW 100 ISL83070E THRU ISL83075E 0.50 50 ICC (mA) OUTPUT CURRENT (mA) 2.30 0 0.48 -50 Y OR Z = HIGH -100 -150 ISL83070/73/76E, DE = X, RE = 0V; ISL83071/77E 0.49 ISL83072/75/78E, DE = 0V, RE = 0V 0.47 ISL8307XE -7 -6 -4 -2 0 2 4 6 OUTPUT VOLTAGE (V) 8 10 0.46 -40 12 FIGURE 9. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT VOLTAGE -25 0 25 TEMPERATURE (°C) 50 75 85 FIGURE 10. SUPPLY CURRENT vs TEMPERATURE 8.0 1220 1200 SKEW (ns) PROPAGATION DELAY (ns) 7.5 1180 1160 1140 1120 tPHL 7.0 6.5 6.0 1100 |CROSS PT. OF Y AND Z - CROSS PT. OF Y AND Z| tPLH 1080 -40 -25 0 25 TEMPERATURE (°C) 50 75 85 FIGURE 11. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL83070E, ISL83071E, ISL83072E) FN6115 Rev 5.00 October 5, 2012 5.5 -40 -25 0 25 TEMPERATURE (°C) 50 75 FIGURE 12. DRIVER DIFFERENTIAL SKEW vs TEMPERATURE (ISL83070E, ISL83071E, ISL83072E) Page 12 of 18 85 ISL83070E/71E/72E/73E/75E/76E/77E/78E VCC = 3.3V, TA = +25°C; Unless Otherwise Specified (Continued) 370 1.4 365 1.2 360 1.0 SKEW (ns) PROPAGATION DELAY (ns) Typical Performance Curves 355 350 340 0.6 tPHL 345 0.4 tPLH -40 0 -25 25 TEMPERATURE (°C) 0.8 |CROSS PT. OF Y AND Z - CROSS PT. OF Y AND Z| 50 0.2 -40 85 75 FIGURE 13. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL83073E, ISL83075E) -25 0 25 TEMPERATURE (°C) 50 85 75 FIGURE 14. DRIVER DIFFERENTIAL SKEW vs TEMPERATURE (ISL83073E, ISL83075E) 0.95 32 31 0.90 PROPAGATION DELAY (ns) 30 0.85 29 SKEW (ns) 28 27 tPHL 26 tPLH 25 24 0.65 |CROSS PT. OF Y AND Z - CROSS PT. OF Y AND Z| 0 25 TEMPERATURE (°C) 50 85 75 RDIFF = 54Ω, CD = 50pF DI 5 0 5 RO 0 2.5 B/Z 2.0 1.5 1.0 A/Y 0.5 0 TIME (400ns/DIV) FIGURE 17. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83070E, ISL83071E, ISL83072E) FN6115 Rev 5.00 October 5, 2012 0 25 TEMPERATURE (°C) 50 85 75 FIGURE 16. DRIVER DIFFERENTIAL SKEW vs TEMPERATURE (ISL83076E, ISL83077E, ISL83078E) DRIVER OUTPUT (V) 3.0 DRIVER INPUT (V) FIGURE 15. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL83076E, ISL83077E, ISL83078E) -25 RDIFF = 54Ω, CD = 50pF DI 5 0 5 RO 0 3.0 2.5 A/Y 2.0 1.5 1.0 B/Z 0.5 0 TIME (400ns/DIV) FIGURE 18. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL83070E, ISL83071E, ISL83072E) Page 13 of 18 DRIVER INPUT (V) -25 0.60 -40 RECEIVER OUTPUT (V) 22 -40 RECEIVER OUTPUT (V) 0.75 0.70 23 DRIVER OUTPUT (V) 0.80 ISL83070E/71E/72E/73E/75E/76E/77E/78E 5 RO 0 3.0 2.5 B/Z 2.0 1.5 1.0 A/Y 0.5 0 DI 0 5 RO 0 3.0 2.5 A/Y 2.0 1.5 1.0 B/Z 0.5 0 TIME (200ns/DIV) TIME (200ns/DIV) 0 5 RO 0 3.0 2.5 B/Z 2.0 1.5 1.0 A/Y 0.5 0 TIME (10ns/DIV) FIGURE 21. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83076E, ISL83077E, ISL83078E) FN6115 Rev 5.00 October 5, 2012 RECEIVER OUTPUT (V) 5 DRIVER INPUT (V) DI FIGURE 20. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL83073E, ISL83075E) DRIVER OUTPUT (V) DRIVER OUTPUT (V) RECEIVER OUTPUT (V) FIGURE 19. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83073E, ISL83075E) RDIFF = 54Ω, CD = 50pF 5 DRIVER INPUT (V) 0 RDIFF = 54Ω, CD = 50pF RDIFF = 54Ω, CD = 50pF DI 5 0 5 RO 0 3.0 2.5 A/Y 2.0 1.5 1.0 B/Z 0.5 0 TIME (10ns/DIV) FIGURE 22. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL83076E, ISL83077E, ISL83078E) Page 14 of 18 DRIVER INPUT (V) DI 5 RECEIVER OUTPUT (V) RDIFF = 54Ω, CD = 50pF DRIVER INPUT (V) VCC = 3.3V, TA = +25°C; Unless Otherwise Specified (Continued) DRIVER OUTPUT (V) DRIVER OUTPUT (V) RECEIVER OUTPUT (V) Typical Performance Curves ISL83070E/71E/72E/73E/75E/76E/77E/78E Typical Performance Curves VCC = 3.3V, TA = +25°C; Unless Otherwise Specified (Continued) RECEIVER OUTPUT CURRENT (mA) 35 VOL, +25°C 30 Die Characteristics 25 VOH, +25°C 20 SUBSTRATE POTENTIAL (POWERED UP): VOL, +85°C GND TRANSISTOR COUNT: 15 VOH, +85°C 535 10 PROCESS: 5 0 Si Gate BiCMOS 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 RECEIVER OUTPUT VOLTAGE (V) FIGURE 23. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE © Copyright Intersil Americas LLC 2005-2012. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6115 Rev 5.00 October 5, 2012 Page 15 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 5 3.0±0.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE PLANE TOP VIEW 0.55 ± 0.15 0.25 3°±3° 0.85±010 H DETAIL "X" C SEATING PLANE 0.25 - 0.36 0.08 M C A-B D 0.10 ± 0.05 0.10 C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN FN6115 Rev 5.00 October 5, 2012 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. Page 16 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN6115 Rev 5.00 October 5, 2012 Page 17 of 18 ISL83070E/71E/72E/73E/75E/76E/77E/78E Package Outline Drawing M14.15 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 1, 10/09 8.65 A 3 4 0.10 C A-B 2X 6 14 DETAIL"A" 8 0.22±0.03 D 6.0 3.9 4 0.10 C D 2X 0.20 C 2X 7 PIN NO.1 ID MARK 5 0.31-0.51 B 3 (0.35) x 45° 4° ± 4° 6 0.25 M C A-B D TOP VIEW 0.10 C 1.75 MAX H 1.25 MIN 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.10-0.25 1.27 SIDE VIEW (1.27) DETAIL "A" (0.6) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Datums A and B to be determined at Datum H. (5.40) 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 indentifier may be either a mold or mark feature. (1.50) 6. Does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm total in excess of lead width at maximum condition. 7. Reference to JEDEC MS-012-AB. TYPICAL RECOMMENDED LAND PATTERN FN6115 Rev 5.00 October 5, 2012 Page 18 of 18
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ISL83070EIBZA
  •  国内价格 香港价格
  • 10+8.1463810+0.98812
  • 30+8.1083130+0.98350
  • 125+8.10813125+0.98348
  • 300+8.10795300+0.98346
  • 1250+8.107771250+0.98343

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