ISL83083EIBZ-T

DATASHEET ISL83080E/82E/83E/84E/85E/86E/88E ±15kV ESD, 5V, Full Fail-Safe, 1/8 Unit Load, RS-485/RS-422 Transceivers FN6085 Rev 10.00 February 15, 2016 The ISL8308xE are BiCMOS, ESD protected, 5V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Each driver output, and receiver input, is protected against ±15kV ESD strikes without latch-up, and unlike competitive products, this Intersil family is specified for 10% tolerance supplies (4.5V to 5.5V). Features These devices have very low bus currents (+125µA/-75µA), so they present a true “1/8 unit load” to the RS-485 bus. This allows up to 256 transceivers on the network without violating the RS-485 specification’s 32 unit load maximum, and without using repeaters. For example, in a remote utility meter reading system, individual meter readings are routed to a concentrator via an RS-485 network, so the high allowed node count minimizes the number of repeaters required. Data for all meters is then read out from the concentrator via a single access port, or a wireless link. • Full Fail-Safe (Open, Short, Terminated and Floating) Receivers Receiver (Rx) inputs feature a “Full Fail-Safe” design, which ensures a logic high Rx output if Rx inputs are floating, shorted, or terminated but undriven. The ISL83080E, ISL83082E, ISL83083E, ISL83084E, ISL83085E utilize slew rate limited drivers which reduce EMI, and minimize reflections from improperly terminated transmission lines, or unterminated stubs in multidrop and multipoint applications. Slew rate limited versions also include receiver input filtering to enhance noise immunity in the presence of slow input signals. Hot Plug circuitry ensures that the Tx and Rx outputs remain in a high impedance state until the power supply has stabilized, and the Tx outputs are fully short circuit protected. The ISL83080E, ISL83083E, ISL83084E, ISL83086E are configured for full duplex (separate Rx input and Tx output pins) applications. The half duplex versions multiplex the Rx inputs and Tx outputs to allow transceivers with output disable functions in 8 Ld packages. • Pb-Free Available (RoHS Compliant) • RS-485 I/O Pin ESD Protection . . . . . . . . . . ±15kV HBM Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV • Tiny MSOP Packages Save 50% Board Space • Hot Plug Circuitry (ISL83080E, ISL83082E, ISL83083E, ISL83085E) - Tx and Rx Outputs Remain Three-state During Power-up/Power-down • True 1/8 Unit Load Allows up to 256 Devices on the Bus • Specified for Single 5V, 10% Tolerance, Supplies • High Data Rates . . . . . . . . . . . . . . . . . . . . . up to 10Mbps • Low Quiescent Supply Current . . . . . . . . . . . . . . . 530µA Ultra Low Shutdown Supply Current . . . . . . . . . . . . 70nA • -7V to +12V Common Mode Input Voltage Range • Half and Full Duplex Pinouts • Three-State Rx and Tx Outputs (Except ISL83084E) • Current Limiting and Thermal Shutdown for driver Overload Protection Applications • Automated Utility Meter Reading Systems • High Node Count Systems • Factory Automation • Field Bus Networks • Security Camera Networks • Building Environmental Control Systems • Industrial/Process Control Networks FN6085 Rev 10.00 February 15, 2016 Page 1 of 21 ISL83080E/82E/83E/84E/85E/86E/88E TABLE 1. SUMMARY OF FEATURES HALF/FULL DUPLEX DATA RATE (Mbps) SLEWRATE LIMITED? HOT PLUG # DEVICES ON BUS Rx/Tx ENABLE? QUIESCEN T ICC (µA) LOW POWER SHUTDOWN? PIN COUNT ISL83080E Full 0.115 Yes Yes 256 Yes 530 Yes 10, 14 ISL83082E Half 0.115 Yes Yes 256 Yes 530 Yes 8 ISL83083E Full 0.5 Yes Yes 256 Yes 530 Yes 10, 14 ISL83084E (No longer available or supported) Full 0.5 Yes No 256 No 530 No 8 ISL83085E Half 0.5 Yes Yes 256 Yes 530 Yes 8 ISL83086E Full 10 No No 256 Yes 530 Yes 10, 14 ISL83088E Half 10 No No 256 Yes 530 Yes 8 PART NUMBER Pinouts ISL83084E (8 LD SOIC) TOP VIEW ISL83082E, ISL83085E, ISL83088E (8 LD MSOP, SOIC) TOP VIEW RO 1 R RE 2 DE 3 DI 4 D 8 VCC 7 B/Z 6 A/Y 5 GND ISL83080E, ISL83083E, ISL83086E (10 LD MSOP) TOP VIEW RO 1 RE 2 R DE 3 DI 4 GND 5 FN6085 Rev 10.00 February 15, 2016 D VCC 1 R ED ORT P P SU 8 R EO 7 ABL L I A 6 DI R3AV E D ONG L 5 GND 4 NO RO 2 A B Z Y ISL83080E, ISL83083E, ISL83086E (14 LD SOIC) TOP VIEW 10 VCC NC 1 9 A RO 2 8 B RE 3 7 Z DE 4 6 Y DI 5 14 VCC 13 NC R 12 A 11 B D 10 Z GND 6 9 Y GND 7 8 NC Page 2 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Ordering Information PART NUMBER (Note 1) PART MARKING PACKAGE (RoHS Compliant) TEMP. RANGE (°C) PKG. DWG. # ISL83080EIBZ (Note 2) 83080EIBZ -40 to +85 14 Ld SOIC M14.15 ISL83080EIUZ (Note 2) 3080Z -40 to +85 10 Ld MSOP M10.118 ISL83082EIBZ (Note 2) 83082 EIBZ -40 to +85 8 Ld SOIC M8.15 ISL83082EIUZ (Note 2) 3082Z -40 to +85 8 Ld MSOP M8.118 ISL83083EIBZ (Note 2) 83083EIBZ -40 to +85 14 Ld SOIC M14.15 ISL83083EIUZ (Note 2) 3083Z -40 to +85 10 Ld MSOP M10.118 ISL83084EIBZ (Note 2) (No longer available or supported, Recommended Replacements ISL83080EIBZ or ISL83088EIBZ) 83084 EIBZ -40 to +85 8 Ld SOIC M8.15 ISL83085EIBZ (Note 2) 83085 EIBZ -40 to +85 8 Ld SOIC M8.15 ISL83085EIUZ (Note 2) 3085Z -40 to +85 8 Ld MSOP M8.118 ISL83086EIBZ (Note 2) 83086EIBZ -40 to +85 14 Ld SOIC M14.15 ISL83086EIUZ (Note 2) 3086Z -40 to +85 10 Ld MSOP M10.118 ISL83088EIBZ (Note 2) 83088 EIBZ -40 to +85 8 Ld SOIC M8.15 ISL83088EIUZ (Note 2) 3088Z -40 to +85 8 Ld MSOP M8.118 NOTES: 1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. Truth Tables RECEIVING TRANSMITTING INPUTS INPUTS OUTPUTS RE RE DE DI Z Y X 1 1 0 1 X 1 0 1 0 0 0 X High-Z High-Z 1 0 X High-Z * High-Z* NOTE: *Shutdown Mode (See Notes 10 and 13). OUTPUT DE DE Half Duplex Full Duplex A-B RO 0 0 X  -0.05V 1 0 0 X  -0.2V 0 0 0 X Inputs Open/Shorted 1 1 0 0 X High-Z* 1 1 1 X High-Z NOTE: *Shutdown Mode (See Notes 10 and 13). Pin Descriptions PIN FUNCTION RO Receiver output: If A - B  -50mV, RO is high; If A - B  -200mV, RO is low; RO = High if A and B are unconnected (floating) or shorted. RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. FN6085 Rev 10.00 February 15, 2016 Page 3 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Pin Descriptions (Continued) PIN FUNCTION DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. GND Ground connection. A/Y ±15kV HBM ESD Protected RS-485/RS-422 level, noninverting receiver input and noninverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. B/Z ±15kV HBM ESD Protected RS-485/RS-422 level, Inverting receiver input and inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. A ±15kV HBM ESD Protected RS-485/RS-422 level, noninverting receiver input. B ±15kV HBM ESD Protected RS-485/RS-422 level, inverting receiver input. Y ±15kV HBM ESD Protected RS-485/RS-422 level, noninverting driver output. Z ±15kV HBM ESD Protected RS-485/RS-422 level, inverting driver output. VCC System power supply input (4.5V to 5.5V). NC No Connection. Typical Operating Circuit ISL83082E, ISL83085E, ISL83088E +5V +5V + 8 0.1µF 0.1µF + 8 VCC 1 RO VCC R D 2 RE B/Z 7 3 DE A/Y 6 4 DI FN6085 Rev 10.00 February 15, 2016 RT RT DI 4 7 B/Z DE 3 6 A/Y RE 2 R D GND GND 5 5 RO 1 Page 4 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Typical Operating Circuit (Continued) ISL83080E, ISL83083E, ISL83086E +5V +5V + 14 VCC 2 RO R 0.1µF 0.1µF + 14 RT A 12 VCC 9 Y B 11 10 Z D DI 5 3 RE DE 4 4 DE RE 3 5 DI RT Z 10 11 B Y 9 D GND RO 2 R 12 A GND 6, 7 6, 7 ISL83084E +5V +5V + 1 0.1µF 0.1µF + 1 VCC A 8 2 RO 3 DI FN6085 Rev 10.00 February 15, 2016 VCC R RT B 7 Z 6 Y 5 D RT 5 Y 6 Z D 7 B R 8 A GND GND 4 4 DI 3 RO 2 Page 5 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltages DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V) Input/Output Voltages A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -9V to +13V A, B, Y, Z (Transient Pulse Through 100, Note 14) . . . . . . ±75V RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V) Short Circuit Duration Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table Thermal Resistance (Typical, Note 3) JA (°C/W) 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 105 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 140 10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . 190 14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 128 Maximum Junction Temperature (Plastic Package) . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications PARAMETER Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C (Note 5). TEMP (°C) MIN (Note 4) TYP MAX (Note 4) UNITS Full - - VCC V RL = 100 (RS-422) (Figure 1A) Full 2 2.9 - V RL = 54 (RS-485) (Figure 1A) Full 1.5 2.4 VCC V RL = 60, -7V  VCM  12V (Figure 1B) Full 1.5 2.6 - V VOD RL = 54 or 100 (Figure 1A) Full - 0.01 0.2 V VOC RL = 54 or 100 (Figure 1A) Full - 2.85 3 V VOC RL = 54 or 100 (Figure 1A) Full - 0.01 0.1 V SYMBOL TEST CONDITIONS DC CHARACTERISTICS Driver Differential VOUT (no load) VOD1 Driver Differential VOUT (with load) VOD2 Change in Magnitude of Driver Differential VOUT for Complementary Output States Driver Common-Mode VOUT Change in Magnitude of Driver Common-Mode VOUT for Complementary Output States Logic Input High Voltage VIH DE, DI, RE Full 2 - - V Logic Input Low Voltage VIL DE, DI, RE Full - - 0.8 V 25 - 100 - mV DI Input Hysteresis Voltage VHYS Logic Input Current IIN1 DE, DI, RE Full -2 - 2 µA Input Current (A, B) IIN2 DE = 0V, VCC = 0V or 5.5V VIN = 12V Full - 70 125 µA VIN = -7V Full -75 55 - µA RE = 0V, DE = 0V, VCC = 0V VIN = 12V or 5.5V (Note 13) VIN = -7V Full - 7 125 µA Full -75 11 - µA RE = VCC, DE = 0V, VIN = 12V VCC = 0V or 5.5V (Note 13) VIN = -7V Full - 0 20 µA Full -20 9 - µA DE = VCC, -7V  VY or VZ  12V (Note 7) Full - - 250 mA Output Leakage Current (Y, Z) (Full Duplex Versions Only) IIN3 Output Leakage Current (Y, Z) in Shutdown Mode (Full Duplex) IIN3 Driver Short-Circuit Current, VO = High or Low FN6085 Rev 10.00 February 15, 2016 IOSD1 Page 6 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Electrical Specifications PARAMETER Receiver Differential Threshold Voltage Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C (Note 5). (Continued) TEMP (°C) MIN (Note 4) TYP MAX (Note 4) UNITS -7V  VCM  12V Full -200 -90 -50 mV SYMBOL VTH TEST CONDITIONS Receiver Input Hysteresis VTH VCM = 0V 25 - 20 - mV Receiver Output High Voltage VOH IO = -4mA, VID = -50mV Full VCC - 1 4.6 - V Receiver Output Low Voltage VOL IO = -4mA, VID = -200mV Full - 0.2 0.4 V Three-State (high impedance) Receiver Output Current IOZR 0.4V  VO  2.4V (Note 13) Full -1 0.03 1 µA Receiver Input Resistance RIN -7V  VCM  12V Full 96 160 - k 0V  VO  VCC Full ±7 - ±85 mA Half Duplex Versions, DE = VCC, RE = X, DI = 0V or VCC Full - 560 700 µA All Versions, DE = 0V, RE = 0V, or Full Duplex Versions, DE = VCC, RE = X. DI = 0V or VCC Full - 530 650 µA DE = 0V, RE = VCC, DI = 0V or VCC (Note 13) Full - 0.07 2 µA RS-485 Pins (A, Y, B, Z) Human Body Model (HBM), Pin to GND 25 - ±15 - kV All Other Pins HBM, per MIL-STD-883 Method 3015 25 - ±7 - kV Machine Model 25 - ±250 - V Receiver Short-Circuit Current IOSR SUPPLY CURRENT No-Load Supply Current (Note 6) Shutdown Supply Current ICC ISHDN ESD PERFORMANCE DRIVER SWITCHING CHARACTERISTICS (115kbps Versions; ISL83080E, ISL83082E) Driver Differential Output Delay tPLH, tPHL RDIFF = 54, CL = 100pF (Figure 2) Full 500 780 1300 ns Driver Differential Output Skew tSKEW RDIFF = 54, CL = 100pF (Figure 2) Full - 40 100 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54, CL = 100pF (Figure 2) Full 667 1000 1500 ns Maximum Data Rate fMAX CD = 820pF (Figure 4) (Note 15) Full 115 666 - kbps Driver Enable to Output High tZH RL = 500, CL = 100pF, SW = GND (Figure 3), (Note 8) Full - 278 1500 ns Driver Enable to Output Low tZL RL = 500, CL = 100pF, SW = VCC (Figure 3) (Note 8) Full - 35 1500 ns Driver Disable from Output Low tLZ RL = 500, CL = 15pF, SW = VCC (Figure 3) Full - 67 100 ns Driver Disable from Output High tHZ RL = 500, CL = 15pF, SW = GND (Figure 3) Full - 38 100 ns (Note 10) Full 60 160 600 ns Time to Shutdown tSHDN Driver Enable from Shutdown to Output High tZH(SHDN) RL = 500, CL = 100pF, SW = GND (Figure 3) (Notes 10, 11) Full - 400 2000 ns Driver Enable from Shutdown to Output Low tZL(SHDN) RL = 500, CL = 100pF, SW = VCC (Figure 3) (Notes 10, 11) Full - 155 2000 ns DRIVER SWITCHING CHARACTERISTICS (500kbps Versions; ISL83083E, ISL83084E, ISL83085E) Driver Differential Output Delay tPLH, tPHL RDIFF = 54, CL = 100pF (Figure 2) Full 250 360 1000 ns Driver Differential Output Skew tSKEW RDIFF = 54, CL = 100pF (Figure 2) Full - 20 100 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54, CL = 100pF (Figure 2) Full 200 475 750 ns Maximum Data Rate fMAX CD = 820pF (Figure 4) (Note 15) Full 500 1000 - kbps FN6085 Rev 10.00 February 15, 2016 Page 7 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Electrical Specifications Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C (Note 5). (Continued) TEMP (°C) MIN (Note 4) TYP MAX (Note 4) UNITS RL = 500, CL = 100pF, SW = GND (Figure 3), (Notes 8, 13) Full - 137 1000 ns tZL RL = 500, CL = 100pF, SW = VCC (Figure 3), (Notes 8, 13) Full - 35 1000 ns Driver Disable from Output Low tLZ RL = 500, CL = 15pF, SW = VCC (Figure 3), (Note 13) Full - 65 100 ns Driver Disable from Output High tHZ RL = 500, CL = 15pF, SW = GND (Figure 3), (Note 13) Full - 38 100 ns (Note 10) Full 60 160 600 ns PARAMETER SYMBOL TEST CONDITIONS Driver Enable to Output High tZH Driver Enable to Output Low Time to Shutdown tSHDN Driver Enable from Shutdown to Output High tZH(SHDN) RL = 500, CL = 100pF, SW = GND (Figure 3), (Notes 10, 11, 13) Full - 260 1500 ns Driver Enable from Shutdown to Output Low tZL(SHDN) RL = 500, CL = 100pF, SW = VCC (Figure 3), (Notes 10, 11, 13) Full - 155 1500 ns DRIVER SWITCHING CHARACTERISTICS (10Mbps Versions; ISL83086E, ISL83088E) Driver Differential Output Delay tPLH, tPHL RDIFF = 54, CL = 100pF (Figure 2) Full - 20 60 ns Driver Differential Output Skew tSKEW RDIFF = 54, CL = 100pF (Figure 2) Full - 1 10 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 54, CL = 100pF (Figure 2) Full - 13 25 ns Maximum Data Rate fMAX CD = 470pF (Figure 4) (Note 15) Full 10 15 - Mbps Driver Enable to Output High tZH RL = 500, CL = 100pF, SW = GND (Figure 3), (Note 8) Full - 35 150 ns Driver Enable to Output Low tZL RL = 500, CL = 100pF, SW = VCC (Figure 3), (Note 8) Full - 30 150 ns Driver Disable from Output Low tLZ RL = 500, CL = 15pF, SW = VCC (Figure 3) Full - 66 100 ns Driver Disable from Output High tHZ RL = 500, CL = 15pF, SW = GND (Figure 3) Full - 38 100 ns (Note 10) Full 60 160 600 ns Time to Shutdown tSHDN Driver Enable from Shutdown to Output High tZH(SHDN) RL = 500, CL = 100pF, SW = GND (Figure 3), (Notes 10, 11) Full - 115 250 ns Driver Enable from Shutdown to Output Low tZL(SHDN) RL = 500, CL = 100pF, SW = VCC (Figure 3), (Notes 10, 11) Full - 84 250 ns RECEIVER SWITCHING CHARACTERISTICS (115kbps and 500kbps Versions; ISL83080E THRU ISL83085E) Maximum Data Rate Receiver Input to Output Delay Receiver Skew | tPLH - tPHL | fMAX (Figure 5) (Note 15) Full 0.5 10 - Mbps Full - 100 150 ns (Figure 5) Full - 7 10 ns tPLH, tPHL (Figure 5) tSKD Receiver Enable to Output Low tZL RL = 1k, CL = 15pF, SW = VCC (Figure 6), (Notes 9, 13) Full - 10 50 ns Receiver Enable to Output High tZH RL = 1k, CL = 15pF, SW = GND (Figure 6), (Notes 9, 13) Full - 10 50 ns Receiver Disable from Output Low tLZ RL = 1k, CL = 15pF, SW = VCC (Figure 6), (Note 13) Full - 10 50 ns Receiver Disable from Output High tHZ RL = 1k, CL = 15pF, SW = GND (Figure 6), (Note 13) Full - 10 50 ns (Notes 10, 13) Full 60 160 600 ns Time to Shutdown FN6085 Rev 10.00 February 15, 2016 tSHDN Page 8 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Electrical Specifications PARAMETER Test Conditions: VCC = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at VCC = 5V, TA = +25°C (Note 5). (Continued) SYMBOL TEST CONDITIONS TEMP (°C) MIN (Note 4) TYP MAX (Note 4) UNITS Receiver Enable from Shutdown to Output High tZH(SHDN) RL = 1k, CL = 15pF, SW = GND (Figure 6), (Notes 10, 12, 13) Full - 150 2000 ns Receiver Enable from Shutdown to Output Low tZL(SHDN) RL = 1k, CL = 15pF, SW = VCC (Figure 6), (Notes 10, 12, 13) Full - 150 2000 ns Full 10 15 - Mbps Full - 70 125 ns (Figure 5) Full - 0 10 ns RECEIVER SWITCHING CHARACTERISTICS (10Mbps Versions; ISL83086E, ISL83088E) Maximum Data Rate Receiver Input to Output Delay fMAX (Figure 5) (Note 15) tPLH, tPHL (Figure 5) Receiver Skew | tPLH - tPHL | tSKD Receiver Enable to Output Low tZL RL = 1k, CL = 15pF, SW = VCC (Figure 6) (Note 9) Full - 10 30 ns Receiver Enable to Output High tZH RL = 1k, CL = 15pF, SW = GND (Figure 6) (Note 9) Full - 10 30 ns Receiver Disable from Output Low tLZ RL = 1k, CL = 15pF, SW = VCC (Figure 6) Full - 10 30 ns Receiver Disable from Output High tHZ RL = 1k, CL = 15pF, SW = GND (Figure 6) Full - 10 30 ns (Note 10) Full 60 160 600 ns Time to Shutdown tSHDN Receiver Enable from Shutdown to Output High tZH(SHDN) RL = 1k, CL = 15pF, SW = GND (Figure 6) (Notes 10, 12) Full - 150 2000 ns Receiver Enable from Shutdown to Output Low tZL(SHDN) RL = 1k, CL = 15pF, SW = VCC (Figure 6) (Notes 10, 12) Full - 150 2000 ns NOTES: 4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 5. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 6. Supply current specification is valid for loaded drivers when DE = 0V. 7. Applies to peak current. See “Typical Performance Curves” beginning on page 13 for more information. 8. Keep RE = 0 to prevent the device from entering SHDN. 9. The RE signal high time must be short enough (typically 600ns to ensure that the device enters SHDN. 12. Set the RE signal high time >600ns to ensure that the device enters SHDN. 13. Does not apply to the ISL83084E. 14. Tested according to TIA/EIA-485-A, section 4.2.6 (±75V for 15µs at a 1% duty cycle). 15. Limits established by characterization and are not production tested. FN6085 Rev 10.00 February 15, 2016 Page 9 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Test Circuits and Waveforms VCC RL/2 DE DI Z Z DI VOD D 375 DE VCC VOD D Y VCM RL = 60 -7V TO +12V Y VOC RL/2 375 FIGURE 1A. VOD AND VOC FIGURE 1B. VOD WITH COMMON MODE LOAD FIGURE 1. DC DRIVER TEST CIRCUITS 3V DI 1.5V 1.5V 0V VCC CL = 100pF DE Z DI tPLH tPHL OUT (Z) VOH OUT (Y) VOL RDIFF D Y CL = 100pF SIGNAL GENERATOR 90% DIFF OUT (Y - Z) +VOD 90% 10% 10% tR -VOD tF SKEW = |tPLH - tPHL| FIGURE 2A. TEST CIRCUIT FIGURE 2B. MEASUREMENT POINTS FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES DE Z DI 500 VCC D SIGNAL GENERATOR SW Y GND CL 3V DE NOTE 10 RE DI SW CL (pF) tHZ Y/Z X 1/0 GND 15 tLZ Y/Z X 0/1 VCC 15 tZH Y/Z 0 (Note 8) 1/0 GND 100 tZL Y/Z 0 (Note 8) 0/1 VCC 100 tZH(SHDN) Y/Z 1 (Note 11) 1/0 GND 100 tZL(SHDN) Y/Z 1 (Note 11) 0/1 VCC 100 FIGURE 3A. TEST CIRCUIT 1.5V 0V tZH, tZH(SHDN) NOTES 8, 11 PARAMETER OUTPUT 1.5V OUTPUT HIGH tHZ VOH - 0.5V 2.3V OUT (Y, Z) VOH 0V tZL, tZL(SHDN) tLZ NOTES 8, 11 OUT (Y, Z) VCC 2.3V OUTPUT LOW VOL + 0.5V V OL FIGURE 3B. MEASUREMENT POINTS FIGURE 3. DRIVER ENABLE AND DISABLE TIMES (DOES NOT APPLY TO THE ISL83084E) FN6085 Rev 10.00 February 15, 2016 Page 10 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Test Circuits and Waveforms (Continued) VCC 3V DE Z DI DI + 60 D 0V VOD CD Y - +VOD DIFF OUT (Y - Z) SIGNAL GENERATOR -VOD 0V FIGURE 4B. MEASUREMENT POINTS FIGURE 4A. TEST CIRCUIT FIGURE 4. DRIVER DATA RATE +1.5V RE 15pF B 0V R A A 0V 0V RO -1.5V tPLH tPHL VCC SIGNAL GENERATOR 1.5V RO 1.5V 0V FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS FIGURE 5. RECEIVER PROPAGATION DELAY AND DATA RATE RE NOTE 10 B GND A R 1k RO SIGNAL GENERATOR 15pF VCC SW RE 3V 1.5V GND 1.5V 0V tZH, tZH(SHDN) NOTES 9, 12 PARAMETER DE A SW tHZ 0 +1.5V GND tLZ 0 -1.5V VCC tZH (Note 9) 0 +1.5V GND tZL (Note 9) 0 -1.5V VCC tZH(SHDN) (Note 12) 0 +1.5V GND tZL(SHDN) (Note 12) 0 -1.5V VCC FIGURE 6A. TEST CIRCUIT OUTPUT HIGH tHZ VOH - 0.5V 1.5V RO VOH 0V tZL, tZL(SHDN) tLZ NOTES 9, 12 RO VCC 1.5V OUTPUT LOW VOL + 0.5V V OL FIGURE 6B. MEASUREMENT POINTS FIGURE 6. RECEIVER ENABLE AND DISABLE TIMES (DOES NOT APPLY TO THE ISL83084E) Application Information RS-485 and RS-422 are differential (balanced) data transmission standards for use in long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 transceivers are also RS-422 compliant. RS-422 is a point-to-multipoint (multidrop) standard, which allows only FN6085 Rev 10.00 February 15, 2016 one driver and up to 10 (assuming one unit load devices) receivers on each bus. RS-485 is a true multipoint standard, which allows up to 32 one unit load devices (any combination of drivers and receivers) on each bus. To allow for multipoint operation, the RS-485 specification requires that drivers must handle bus contention without sustaining any damage. Page 11 of 21 ISL83080E/82E/83E/84E/85E/86E/88E power-up and power-down, the Tx and Rx outputs remain disabled, regardless of the state of DE and RE, if VCC is less than ~3.4V. This gives the processor/ASIC a chance to stabilize and drive the RS-485 control lines to the proper states. VCC 3.4V 3.2V These devices utilize a differential input receiver for maximum noise immunity and common mode rejection. Input sensitivity is ±200mV, as required by the RS-422 and RS-485 specifications. Receiver input resistance of 96k surpasses the RS-422 specification of 4k, and is eight times the RS-485 “Unit Load (UL)” requirement of 12k minimum. Thus, these products are known as “one-eighth UL” transceivers, and there can be up to 256 of these devices on a network while still complying with the RS-485 loading specification. Receiver inputs function with common mode voltages as great as ±7V outside the power supplies (i.e., +12V and -7V), making them ideal for long networks where induced voltages are a realistic concern. All the receivers include a “full fail-safe” function that guarantees a high level receiver output if the receiver inputs are unconnected (floating) or shorted. Receivers easily meet the data rates supported by the corresponding driver, and all receiver outputs are three-statable via the active low RE input (except for the ISL83084E). Driver Features The RS-485/RS-422 driver is a differential output device that delivers at least 1.5V across a 54 load (RS-485), and at least 2V across a 100 load (RS-422). The drivers feature low propagation delay skew to maximize bit width, and to minimize EMI. All drivers are three-statable via the active high DE input (except for the ISL83084E). The 115kbps and 500kbps driver outputs are slew rate limited to minimize EMI, and to minimize reflections in unterminated or improperly terminated networks. Outputs of the ISL83086E, ISL83088E drivers are not limited, so faster output transition times allow data rates of at least 10Mbps. Hot Plug Function When a piece of equipment powers up, there is a period of time where the processor or ASIC driving the RS-485 control lines (DE, RE) is unable to ensure that the RS-485 Tx and Rx outputs are kept disabled. If the equipment is connected to the bus, a driver activating prematurely during power-up may crash the bus. To avoid this scenario, the ISL83080, ISL83082, ISL83083, ISL83085 versions incorporate a “Hot Plug” function. Circuitry monitoring VCC ensures that, during FN6085 Rev 10.00 February 15, 2016 DRIVER Y OUTPUT (V) Receiver Features 5.0 VCC (V) DI = VCC 2.5 0 5.0 2.5 RL = 1k A/Y ISL83080E 0 RL = 1k RO ISL83080E 5.0 2.5 0 RECEIVER OUTPUT (V) Another important advantage of RS-485 is the extended common mode range (CMR), which specifies that the driver outputs and receiver inputs withstand signals that range from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000’, so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields. TIME (40µs/DIV) FIGURE 7. HOT PLUG PERFORMANCE (ISL83080E) vs DEVICE WITHOUT HOT PLUG CIRCUITRY (ISL83086E) ESD Protection All pins on these devices include class 3 Human Body Model (HBM) ESD protection structures, but the RS-485 pins (driver outputs and receiver inputs) incorporate advanced structures allowing them to survive ESD events in excess of ±15kV HBM. The RS-485 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect without allowing any latchup mechanism to activate, and without degrading the RS-485 common mode range of -7V to +12V. This built-in ESD protection eliminates the need for board level protection structures (e.g., transient suppression diodes), and the associated, undesirable capacitive load they present. Data Rate, Cables, and Terminations RS-485/RS-422 are intended for network lengths up to 4000’, but the maximum system data rate decreases as the transmission length increases. Devices operating at 10Mbps are limited to lengths less than 100’, while the 115kbps versions can operate at full data rates with lengths of several 1000’. Twisted pair is the cable of choice for RS-485/RS-422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in these ICs. Proper termination is imperative (when using the 10Mbps devices) to minimize reflections. Short networks using the Page 12 of 21 ISL83080E/82E/83E/84E/85E/86E/88E 115kbps versions need not be terminated, but, terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-to-multipoint (single driver on bus) networks, the main cable should be terminated in its characteristic impedance (typically 120) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transceiver to the main cable should be kept as short as possible. Built-In Driver Overload Protection As stated previously, the RS-485 specification requires that drivers survive worst case bus contentions undamaged. These devices meet this requirement via driver output short circuit current limits, and on-chip thermal shutdown circuitry. The driver output stages incorporate short circuit current limiting circuitry which ensures that the output current never exceeds the RS-485 specification, even at the common mode voltage range extremes. Additionally, these devices utilize a foldback circuit which reduces the short circuit current, and thus the power dissipation, whenever the contending voltage exceeds either supply. Typical Performance Curves In the event of a major short circuit condition, devices also include a thermal shutdown feature that disables the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically re-enable after the die temperature drops about +15°C. If the contention persists, the thermal shutdown/re-enable cycle repeats until the fault is cleared. Receivers stay operational during thermal shutdown. Low Power Shutdown Mode These CMOS transceivers all use a fraction of the power required by their bipolar counterparts, but they also include a shutdown feature (except for the ISL83084E) that reduces the already low quiescent ICC to a 70nA trickle. These devices enter shutdown whenever the receiver and driver are simultaneously disabled (RE = VCC and DE = GND) for a period of at least 600ns. Disabling both the driver and the receiver for less than 60ns guarantees that the transceiver will not enter shutdown. Note that receiver and driver enable times increase when the transceiver enables from shutdown. Refer to Notes 8 thru 12, at the end of the “Electrical Specification Table” on page 9, for more information. VCC = 5V, TA = +25°C; Unless Otherwise Specified 3.4 80 DIFFERENTIAL OUTPUT VOLTAGE (V) DRIVER OUTPUT CURRENT (mA) 90 70 60 50 40 30 20 10 0 0 1 2 3 4 DIFFERENTIAL OUTPUT VOLTAGE (V) FIGURE 8. DRIVER OUTPUT CURRENT vs DIFFERENTIAL OUTPUT VOLTAGE FN6085 Rev 10.00 February 15, 2016 5 3.2 RDIFF = 100 3.0 2.8 2.6 RDIFF = 54 2.4 2.2 2.0 -40 -25 0 25 TEMPERATURE (°C) 50 75 FIGURE 9. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs TEMPERATURE Page 13 of 21 85 ISL83080E/82E/83E/84E/85E/86E/88E Typical Performance Curves 200 VCC = 5V, TA = +25°C; Unless Otherwise Specified (Continued) 560 ISL83086E/ISL83088E 150 550 HALF DUPLEX, DE = VCC, RE = X 100 540 ISL83080E thru ISL83085E 50 ICC (µA) OUTPUT CURRENT (mA) Y OR Z = LOW 0 520 HALF DUPLEX, DE = GND, RE = GND FULL DUPLEX, DE = X, RE = GND -50 Y OR Z = HIGH 510 -100 -150 ISL8308xE -7 -6 -4 -2 0 2 4 6 OUTPUT VOLTAGE (V) 8 10 500 -40 12 -25 0 25 50 75 85 TEMPERATURE (°C) FIGURE 10. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT VOLTAGE FIGURE 11. SUPPLY CURRENT vs TEMPERATURE 880 60 860 55 840 50 tPHL 820 SKEW (ns) PROPAGATION DELAY (ns) 530 800 45 40 780 760 tPLH 35 50 30 -40 |CROSS PT. OF Y AND Z - CROSS PT. OF Y AND Z| 740 -40 -25 0 25 75 85 -25 0 25 50 75 85 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 12. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL83080E, ISL83082E) FIGURE 13. DRIVER DIFFERENTIAL SKEW vs TEMPERATURE (ISL83080E, ISL83082E) 27 400 26 25 24 380 tPHL SKEW (ns) PROPAGATION DELAY (ns) 390 370 360 23 22 21 20 19 tPLH 350 18 340 -40 -25 0 25 50 75 85 TEMPERATURE (°C) FIGURE 14. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL83083E, ISL83084E, ISL83085E) FN6085 Rev 10.00 February 15, 2016 17 -40 |CROSS PT. OF Y AND Z - CROSS PT. OF Y AND Z| -25 0 25 50 75 TEMPERATURE (°C) FIGURE 15. DRIVER DIFFERENTIAL SKEW vs TEMPERATURE (ISL83083E, ISL83084E, ISL83085E) Page 14 of 21 85 ISL83080E/82E/83E/84E/85E/86E/88E Typical Performance Curves VCC = 5V, TA = +25°C; Unless Otherwise Specified (Continued) 20 0.70 PROPAGATION DELAY (ns) 19 0.65 tPHL SKEW (ns) 18 tPLH 17 0.60 0.55 16 |CROSS PT. OF Y AND Z - CROSS PT. OF Y AND Z| 0 25 50 75 85 -25 0 TEMPERATURE (°C) 0 5 RO 0 4 3 B/Z 2 A/Y RECEIVER OUTPUT (V) 5 DRIVER INPUT (V) DI 1 0 DI 5 0 3 2 DRIVER OUTPUT (V) 4 B/Z A/Y 1 0 TIME (200ns/DIV) FIGURE 20. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83083E, ISL83084E, ISL83085E) FN6085 Rev 10.00 February 15, 2016 RECEIVER OUTPUT (V) 5 DRIVER INPUT (V) RECEIVER OUTPUT (V) DRIVER OUTPUT (V) RO 5 0 RO 0 4 3 A/Y 2 B/Z 1 0 FIGURE 19. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL83080E, ISL83082E) 0 5 85 TIME (400ns/DIV) FIGURE 18. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83080E, ISL83082E) RDIFF = 54, CL = 100pF 75 RDIFF = 54, CL = 100pF TIME (400ns/DIV) DI 50 FIGURE 17. DRIVER DIFFERENTIAL SKEW vs TEMPERATURE (ISL83086E, ISL83088E) DRIVER OUTPUT (V) DRIVER OUTPUT (V) RECEIVER OUTPUT (V) FIGURE 16. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL83086E, ISL83088E) RDIFF = 54, CL = 100pF 25 TEMPERATURE (°C) DRIVER INPUT (V) -25 0.50 -40 RDIFF = 54, CL = 100pF DI 5 0 RO 0 4 3 A/Y 2 B/Z 5 1 0 TIME (200ns/DIV) FIGURE 21. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL83083E, ISL83084E, ISL83085E) Page 15 of 21 DRIVER INPUT (V) 15 -40 ISL83080E/82E/83E/84E/85E/86E/88E 5 RO 0 3 2 DRIVER OUTPUT (V) 4 B/Z A/Y 1 0 RDIFF = 54, CL = 100pF DI 5 0 RO 0 4 3 2 A/Y B/Z 1 0 TIME (20ns/DIV) TIME (20ns/DIV) FIGURE 23. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL83086E, ISL83088E) FIGURE 22. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83086E, ISL83088E) RECEIVER OUTPUT CURRENT (mA) 40 VOL, +25°C 35 Die Characteristics VOL, +85°C 30 SUBSTRATE POTENTIAL (POWERED UP): GND 25 VOH, +25°C 20 TRANSISTOR COUNT: 525 VOH, +85°C 15 PROCESS: 10 Si Gate BiCMOS 5 0 0 1 2 3 4 5 RECEIVER OUTPUT VOLTAGE (V) FIGURE 24. RECEIVER OUTPUT CURRENT vs RECEIVER OUTPUT VOLTAGE FN6085 Rev 10.00 February 15, 2016 5 Page 16 of 21 DRIVER INPUT (V) 0 RECEIVER OUTPUT (V) DI 5 DRIVER INPUT (V) VCC = 5V, TA = +25°C; Unless Otherwise Specified (Continued) RDIFF = 54, CL = 100pF DRIVER OUTPUT (V) RECEIVER OUTPUT (V) Typical Performance Curves ISL83080E/82E/83E/84E/85E/86E/88E Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE February 15, 2016 FN6085.10 Added Rev History and About Intersil verbiage. Updated “Ordering Information” on page 3. Updated POD M8.118 to current version with following changes: Updated to new Intersil format by adding land pattern and moving dimensions from table onto drawing Corrected lead width dimension in side view 1 from “0.25 - 0.036" to “0.25 - 0.36" Updated POD M10.118 to current version with following change: Updated to new POD template. Added land pattern Updated POD M14.15 to current version with following change: Added land pattern and moved dimensions from table onto drawing. Updated POD M8.15 to current version with following changes: Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern. Changed in Typical Recommended Land Pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) Changed Note 1 “1982” to “1994” About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2004-2016. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6085 Rev 10.00 February 15, 2016 Page 17 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 5 3.0±0.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE PLANE TOP VIEW 0.55 ± 0.15 0.25 3°±3° 0.85±010 H DETAIL "X" C SEATING PLANE 0.25 - 0.36 0.08 M C A-B D 0.10 ± 0.05 0.10 C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN FN6085 Rev 10.00 February 15, 2016 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. Page 18 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Package Outline Drawing M10.118 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 4/12 5 3.0±0.05 A DETAIL "X" D 10 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 0.50 BSC B GAUGE PLANE TOP VIEW 0.55 ± 0.15 0.25 3°±3° 0.85±010 H DETAIL "X" C SEATING PLANE 0.18 - 0.27 0.08 M C A-B D 0.10 ± 0.05 0.10 C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-BA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. (0.50) (0.29) (1.40) 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. TYPICAL RECOMMENDED LAND PATTERN FN6085 Rev 10.00 February 15, 2016 Page 19 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Package Outline Drawing M14.15 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 1, 10/09 8.65 A 3 4 0.10 C A-B 2X 6 14 DETAIL"A" 8 0.22±0.03 D 6.0 3.9 4 0.10 C D 2X 0.20 C 2X 7 PIN NO.1 ID MARK 5 0.31-0.51 B 3 (0.35) x 45° 4° ± 4° 6 0.25 M C A-B D TOP VIEW 0.10 C 1.75 MAX H 1.25 MIN 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.10-0.25 1.27 SIDE VIEW (1.27) DETAIL "A" (0.6) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Datums A and B to be determined at Datum H. (5.40) 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 indentifier may be either a mold or mark feature. (1.50) 6. Does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm total in excess of lead width at maximum condition. 7. Reference to JEDEC MS-012-AB. TYPICAL RECOMMENDED LAND PATTERN FN6085 Rev 10.00 February 15, 2016 Page 20 of 21 ISL83080E/82E/83E/84E/85E/86E/88E Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN6085 Rev 10.00 February 15, 2016 Page 21 of 21