ISL83485IBZ-T

DATASHEET ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 FN6052 Rev.5.00 Nov 21, 2018 3.3V, Low Power, High Speed or Slew Rate Limited, RS-485/RS-422 Transceivers These Renesas RS-485/RS-422 devices are BiCMOS 3.3V powered, single transceivers that meet both the RS-485 and RS-422 standards for balanced communication. Unlike competitive devices, this Renesas family is specified for 10% tolerance supplies (3V to 3.6V). The ISL83483 and ISL83488 use slew rate limited drivers which reduce EMI, and minimize reflections from improperly terminated transmission lines, or unterminated stubs in multidrop and multipoint applications. Features • Operate from a single +3.3V supply (10% tolerance) • Interoperable with 5V logic • High data rates . . . . . . . . . . . . . . . . . . . . . . up to 10Mbps • Single unit load allows up to 32 devices on the bus • Slew rate limited versions for error free data transmission (ISL83483, ISL83488) . . . . . . . . . . . . . . . . .up to 250kbps Data rates up to 10Mbps are achievable by using the ISL83485, ISL83490, or ISL83491, which feature higher slew rates. • Low current Shutdown mode (ISL83483, ISL83485, ISL83491). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15nA Logic inputs (for example, DI and DE) accept signals in excess of 5.5V, making them compatible with 5V logic families. • Three-state Rx and Tx outputs (except ISL83488, ISL83490) Receiver (Rx) inputs feature a “fail-safe if open” design, which ensures a logic high output if Rx inputs are floating. All devices present a “single unit load” to the RS-485 bus, which allows up to 32 transceivers on the network. Driver (Tx) outputs are short-circuit protected, even for voltages exceeding the power supply voltage. Additionally, on-chip thermal shutdown circuitry disables the Tx outputs to prevent damage if power dissipation becomes excessive. The ISL83488, ISL83490, and ISL83491 are configured for full duplex (separate Rx input and Tx output pins) applications. The ISL83488 and ISL83490 are offered in space saving 8 Ld packages for applications not requiring Rx and Tx output disable functions (for example, point-to-point and RS-422). Half duplex configurations (ISL83483, ISL83485) multiplex the Rx inputs and Tx outputs to provide transceivers with Rx and Tx disable functions in 8 Ld packages. • -7V to +12V common-mode input voltage range • 10ns propagation delay, 1ns skew (ISL83485, ISL83490, ISL83491) • Full duplex and half duplex pinouts • Current limiting and thermal shutdown for driver overload protection • Pb-free (RoHS compliant) Applications • Factory automation • Security networks • Building environmental control systems • Industrial/process control networks • Level translators (for example, RS-232 to RS-422) • RS-232 “Extension Cords” Related Literature For a full list of related documents, visit our website: • ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 device pages TABLE 1. SUMMARY OF FEATURES PART NUMBER HALF/FULL DUPLEX DATA RATE (Mbps) SLEW-RATE LIMITED? RECEIVER/DRIVER ENABLE? QUIESCENT ICC (mA) LOW POWER SHUTDOWN? PIN COUNT ISL83483 Half 0.25 Yes Yes 0.65 Yes 8 ISL83485 Half 10 No Yes 0.65 Yes 8 ISL83488 Full 0.25 Yes No 0.65 No 8 ISL83490 Full 10 No No 0.65 No 8 ISL83491 Full 10 No Yes 0.65 Yes 14 FN6052 Rev.5.00 Nov 21, 2018 Page 1 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Ordering Information PART NUMBER (Notes 2, 3) PART MARKING TAPE AND REEL TEMP. RANGE (°C) (UNITS) (Note 1) PACKAGE PKG. DWG. # ISL83483IBZ 83483 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15 ISL83483IBZ-T 83483 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15 ISL83483IBZ-T7A 83483 IBZ -40 to +85 250 8 Ld SOIC (RoHS compliant) M8.15 ISL 83483IP -40 to +85 - 8 Ld PDIP ISL83485IBZ 83485 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15 ISL83485IBZ-T 83485 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15 ISL83485IBZ-T7A 83485 IBZ -40 to +85 250 8 Ld SOIC (RoHS compliant) M8.15 ISL83488IBZ 83488 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15 ISL83483IP (No longer available or supported) E8.3 ISL83488IBZ-T 83488 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15 ISL83490IBZ 83490 IBZ -40 to +85 - 8 Ld SOIC (RoHS compliant) M8.15 ISL83490IBZ-T 83490 IBZ -40 to +85 2.5k 8 Ld SOIC (RoHS compliant) M8.15 ISL83491IBZ 83491IBZ -40 to +85 - 14 Ld SOIC (RoHS compliant) M14.15 ISL83491IBZ-T 83491IBZ -40 to +85 2.5k 14 Ld SOIC (RoHS compliant) M14.15 ISL83491IBZ-T7A 83491IBZ -40 to +85 250 14 Ld SOIC (RoHS compliant) M14.15 ISL83491IP -40 to +85 - ISL83491IP (No longer available, recommended replacement: ISL83491IBZ) 14 Ld PDIP E14.3 NOTES: 1. Refer to TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), refer to the ISL83483, ISL83485, ISL83488, ISL83490, and ISL83491 device pages. For more information about MSL, refer to TB363. FN6052 Rev.5.00 Nov 21, 2018 Page 2 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Pinouts ISL83483, ISL83485 (PDIP, SOIC) TOP VIEW RO 1 ISL83488, ISL83490 (SOIC) TOP VIEW 8 VCC VCC 1 RE 2 7 B/Z RO 2 DE 3 6 A/Y DI 3 5 GND R D DI 4 GND 4 R D ISL83491 (PDIP, SOIC) TOP VIEW 8 A NC 1 7 B RO 2 6 Z RE 3 5 Y DE 4 DI 5 14 VCC 13 VCC R 12 A 11 B D 10 Z GND 6 9 Y GND 7 8 NC NOTE: PDIP packages are no longer supported Truth Tables TRANSMITTING RECEIVING INPUTS OUTPUTS INPUTS RE DE DI Z Y X 1 1 0 1 X 1 0 1 0 0 0 X High-Z High-Z 1 0 X High-Z * High-Z * NOTE: *Shutdown Mode for ISL83483, ISL83485, ISL83491 OUTPUT RE DE Half Duplex DE Full Duplex A-B RO 0 0 X ≥ +0.2V 1 0 0 X ≤ -0.2V 0 0 0 X Inputs Open 1 1 0 0 X High-Z * 1 1 1 X High-Z NOTE: *Shutdown Mode for ISL83483, ISL83485, ISL83491 Pin Descriptions PIN FUNCTION RO Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating). RE Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high. DE Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. DI Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. GND Ground connection. A/Y Noninverting receiver input and noninverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. B/Z Inverting receiver input and inverting driver output. Pin is an input if DE = 0; pin is an output if DE = 1. A Noninverting receiver input. B Inverting receiver input. Y Noninverting driver output. Z Inverting driver output. VCC System power supply input (3V to 3.6V). NC No Connection. FN6052 Rev.5.00 Nov 21, 2018 Page 3 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Typical Operating Circuits For calculating the resistor values refer to TB509, “Detecting Bus Signals Correctly with Failsafe Biased RS-485 Receivers” 3.3V 8 RPU 3.3V 100nF VCC 100nF RB 1 RO 8 RPU VCC RO 1 A/Y 6 6 A/Y 2 RE RE 2 3 DE B/Z 7 RT2 VFS RT1 DE 3 7 B/Z 4 DI DI 4 RB GND GND 5 5 FIGURE 1. ISL83483, ISL83485 3.3V 1 VCC 3.3V 100nF 100nF A 8 2 RO B 7 5 Y 6 Z 1 VCC DI RT Z 6 3 7 B 3 DI RT Y 5 RO 2 8 A GND GND 4 4 FIGURE 2. ISL83488, ISL83490 3.3V 13, 14 R PU VCC 3.3V 100nF 100nF RB RB A 12 2 RO 3 RE B 11 4 DE Z 10 9 Y R PU DI 5 RT 10 Z DE 4 11 B 5 DI RT Y 9 GND 6, 7 13,14 VCC RB RB RE 3 RO 2 12 A GND 6, 7 FIGURE 3. ISL83491 FN6052 Rev.5.00 Nov 21, 2018 Page 4 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltages DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input/Output Voltages A, B, Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC +0.5V) Short-Circuit Duration Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Thermal Resistance (Typical, Note 4) Operating Conditions Temperature Range ISL834xxIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C θJA (°C/W) 8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 170 8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . 140 14 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 130 14 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . 105 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile (SOIC only). . . . . . . . . . . . . . . . . see TB493 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. θJA is measured with the component mounted on a low-effective thermal conductivity test board in free air. See TB379. Electrical Specifications Test conditions: VCC = 3V to 3.6V; unless otherwise specified. Typicals are at VCC = 3.3V, TA = +25°C, Note 5. PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) MIN TYP MAX UNIT Full - - VCC V DC CHARACTERISTICS Driver Differential VOUT (no load) VOD1 Driver Differential VOUT (with load) VOD2 Change in Magnitude of Driver Differential VOUT for Complementary Output States Driver Common-Mode VOUT Change in Magnitude of Driver Common-Mode VOUT for Complementary Output States RL = 100Ω (RS-422) (Figure 4A) Full 2 2.7 - V RL = 54Ω (RS-485) (Figure 4A) Full 1.5 2.3 VCC V RL = 60Ω, -7V ≤ VCM ≤ 12V (Figure 4B) Full 1.5 2.6 - V ΔVOD RL = 54Ω or 100Ω (Figure 4A) Full - 0.01 0.2 V VOC RL = 54Ω or 100Ω (Figure 4A) Full - 1.8 3 V ΔVOC RL = 54Ω or 100Ω (Figure 4A) Full - 0.01 0.2 V Logic Input High Voltage VIH DE, DI, RE Full 2 - - V Logic Input Low Voltage VIL DE, DI, RE Full - - 0.8 V Logic Input Current IIN1 DE, DI Full -2 - 2 µA RE Full -25 - 25 µA VIN = 12V Full - 0.6 1 mA VIN = -7V Full - -0.3 -0.8 mA Input Current (A, B) IIN2 Output Leakage Current (Y, Z) (ISL83491) IIN3 Output Leakage Current (Y, Z) in Shutdown Mode (ISL83491) IIN3 Receiver Differential Threshold Voltage VTH DE = 0V, VCC = 0V or 3.6V RE = 0V, DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 14 20 µA VIN = -7V Full -20 -11 - µA RE = VCC, DE = 0V, VCC = 0V or 3.6V VIN = 12V Full - 0.03 1 µA VIN = -7V Full -1 -0.01 - µA -7V ≤ VCM ≤ 12V Full -0.2 - 0.2 V Receiver Input Hysteresis ΔVTH VCM = 0V +25 - 50 - mV Receiver Output High Voltage VOH IO = -4mA, VID = 200mV Full VCC 0.4 - - V Receiver Output Low Voltage VOL IO = -4mA, VID = 200mV Full - - 0.4 V FN6052 Rev.5.00 Nov 21, 2018 Page 5 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Electrical Specifications Test conditions: VCC = 3V to 3.6V; unless otherwise specified. Typicals are at VCC = 3.3V, TA = +25°C, Note 5. (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP (°C) MIN TYP MAX UNIT Three-State (high impedance) Receiver Output Current IOZR 0.4V ≤ VO ≤ 2.4V Full -1 - 1 µA Receiver Input Resistance RIN -7V ≤ VCM ≤ 12V Full 12 19 - kΩ No-Load Supply Current (Note 6) ICC DI = 0V or VCC DE = VCC, RE = 0V or VCC Full - 0.75 1.2 mA DE = 0V, RE = 0V Full - 0.65 1 mA Shutdown Supply Current (Except ISL83488 and ISL83490) ISHDN DE = 0V, RE = VCC, DI = 0V or VCC Full - 15 100 nA Driver Short-Circuit Current, VO = High or Low IOSD1 DE = VCC, -7V ≤ VY or VZ ≤ 12V (Note 7) Full - - 250 mA Receiver Short-Circuit Current IOSR 0V ≤ VO ≤ VCC Full 8 - 60 mA DRIVER SWITCHING CHARACTERISTICS (ISL83485, ISL83490, ISL83491) Maximum Data Rate Driver Differential Output Delay Driver Differential Rise or Fall Time Driver Input to Output Delay Full 12 15 - Mbps tDD RDIFF = 60Ω, CL = 15pF (Figure 5A) Full 1 10 35 ns tR, tF RDIFF = 60Ω, CL = 15pF (Figure 5A) Full 3 5 20 ns Full 6 10 35 ns fMAX tPLH, tPHL RL = 27Ω, CL = 15pF (Figure 5C) RL = 27Ω, CL = 15pF (Figure 5C) Full - 1 8 ns Driver Enable to Output High (Except ISL83490) tZH RL = 110Ω, CL = 50pF, SW = GND (Figure 6), (Note 8) Full - 45 90 ns Driver Enable to Output Low (Except ISL83490) tZL RL = 110Ω, CL = 50pF, SW = VCC (Figure 6), (Note 8) Full - 45 90 ns Driver Disable from Output High (Except ISL83490) tHZ RL = 110Ω, CL = 50pF, SW = GND (Figure 6) +25 - 65 80 ns Full - - 110 ns Driver Disable from Output Low (Except ISL83490) tLZ RL = 110Ω, CL = 50pF, SW = VCC (Figure 6) +25 - 65 80 ns Full - - 110 ns Driver Output Skew tSKEW Driver Enable from Shutdown to Output High (Except ISL83490) tZH(SHDN) RL = 110Ω, CL = 50pF, SW = GND (Figure 6), (Notes 10, 11) Full - 115 150 ns Driver Enable from Shutdown to Output Low (Except ISL83490) tZL(SHDN) RL = 110Ω, CL = 50pF, SW = VCC (Figure 6), (Notes 10, 11) Full - 115 150 ns Full 250 - - kbps Full 600 930 1400 ns DRIVER SWITCHING CHARACTERISTICS (ISL83483, ISL83488) Maximum Data Rate Driver Differential Output Delay Driver Differential Rise or Fall Time Driver Input to Output Delay Driver Output Skew fMAX tDD RDIFF = 60Ω, CL = 15pF (Figure 5A) tR, tF RDIFF = 60Ω, CL = 15pF (Figure 5A) Full 400 900 1200 ns +25 600 930 1500 ns Full 400 - 1500 ns RL = 27Ω, CL = 15pF (Figure 5C) Full - 140 - ns tPLH, tPHL RL = 27Ω, CL = 15pF (Figure 5C) tSKEW Driver Enable to Output High (Except ISL83488) tZH RL = 110Ω, CL = 50pF, SW = GND (Figure 6), (Note 8) Full - 385 800 ns Driver Enable to Output Low (Except ISL83488) tZL RL = 110Ω, CL = 50pF, SW = VCC (Figure 6), (Note 8) Full - 55 800 ns Driver Disable from Output High (Except ISL83488) tHZ RL = 110Ω, CL = 50pF, SW = GND (Figure 6) +25 - 63 80 ns Full - - 110 ns FN6052 Rev.5.00 Nov 21, 2018 Page 6 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Electrical Specifications Test conditions: VCC = 3V to 3.6V; unless otherwise specified. Typicals are at VCC = 3.3V, TA = +25°C, Note 5. (Continued) PARAMETER Driver Disable from Output Low (Except ISL83488) SYMBOL tLZ TEST CONDITIONS RL = 110Ω, CL = 50pF, SW = VCC (Figure 6) TEMP (°C) MIN TYP +25 - Full - MAX UNIT 70 80 ns - 110 ns Driver Enable from Shutdown to Output High (Except ISL83488) tZH(SHDN) RL = 110Ω, CL = 50pF, SW = GND (Notes 10, 11) Full - 450 2000 ns Driver Enable from Shutdown to Output Low (Except ISL83488) tZL(SHDN) Full - 126 2000 ns Full 25 45 90 ns +25 - 2 10 ns Full - 2 12 ns RL = 110Ω, CL = 50pF, SW = VCC (Figure 6), (Notes 10, 11) RECEIVER SWITCHING CHARACTERISTICS (All Versions) Receiver Input to Output Delay Receiver Skew | tPLH - tPHL | tPLH, tPHL (Figure 7) tSKD (Figure 7) Receiver Enable to Output High (Except ISL83488 and ISL83490) tZH RL = 1kΩ, CL = 15pF, SW = GND (Figure 8), (Note 9) Full - 11 50 ns Receiver Enable to Output Low (Except ISL83488 and ISL83490) tZL RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8), (Note 9) Full - 11 50 ns Receiver Disable from Output High (Except ISL83488 and ISL83490) tHZ RL = 1kΩ, CL = 15pF, SW = GND (Figure 8) Full - 7 45 ns Receiver Disable from Output Low (Except ISL83488 and ISL83490) tLZ RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8) Full - 7 45 ns Time to Shutdown (Except ISL83488 and ISL83490) tSHDN (Note 10) Full 80 190 300 ns Receiver Enable from Shutdown to Output High (Except ISL83488 and ISL83490) tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 8), (Notes 10, 11) Full - 240 600 ns Receiver Enable from Shutdown to Output Low (Except ISL83488 and ISL83490) tZL(SHDN) Full - 240 600 ns RL = 1kΩ, CL = 15pF, SW = VCC (Figure 8), (Notes 10, 11) NOTES: 5. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 6. Supply current specification is valid for loaded drivers when DE = 0V. 7. Applies to peak current. See “Typical Performance Curves” on page 11 for more information. 8. When testing the ISL83483, ISL83485, and ISL83491, keep RE = 0 to prevent the device from entering SHDN. 9. When testing the ISL83483, ISL83485, and ISL83491, the RE signal high time must be short enough (typically 300ns to ensure that the device enters SHDN. 12. Set the RE signal high time >300ns to ensure that the device enters SHDN. FN6052 Rev.5.00 Nov 21, 2018 Page 7 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Test Circuits and Waveforms VCC RL/2 DE VCC Z DI DI VOD D 375Ω DE Z VOD D Y VCM RL = 60Ω -7V to +12V Y VOC RL/2 375Ω FIGURE 4B. VOD WITH COMMON MODE LOAD FIGURE 4A. VOD AND VOC FIGURE 4. DC DRIVER TEST CIRCUITS 3V CL = 15pF DE 3V DI 1.5V 1.5V 0V Z DI tPLH RDIFF = 60Ω D Y CL = 15pF tPHL VOH 50% OUT (Y) 50% SIGNAL GENERATOR VOL tPLH tPHL VOH FIGURE 5A. DIFFERENTIAL TEST CIRCUIT OUT (Z) 50% 50% VOL OUT 3V tDD DE DI Z DIFF OUT (Y - Z) RL = 27Ω VOM D 90% tR Y SIGNAL GENERATOR 50% 10% tDD CL = 15pF VOM = 90% +VOD 50% 10% -VOD tF SKEW = |tPLH (Y or Z) - tPHL (Z or Y)| VOH + VOL 2 FIGURE 5C. SINGLE ENDED TEST CIRCUIT ≈1.5V FIGURE 5B. MEASUREMENT POINTS FIGURE 5. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES FN6052 Rev.5.00 Nov 21, 2018 Page 8 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Test Circuits and Waveforms (Continued) DE Z DI 110Ω VCC D SIGNAL GENERATOR SW Y 3V GND DE Note 10 CL = 50pF 1.5V 1.5V 0V tZH, tZH(SHDN) OUTPUT HIGH Note 10 PARAMETER OUTPUT RE DI SW tHZ Y/Z X 1/0 GND tLZ Y/Z X 0/1 VCC tZH Y/Z 0 (Note 8) 1/0 GND tZL, tZL(SHDN) Note 10 OUT (Y, Z) tZL Y/Z 0 (Note 8) 0/1 VCC tZH(SHDN) Y/Z 1 (Note 11) 1/0 GND tZL(SHDN) Y/Z 1 (Note 11) 0/1 VCC tHZ VOH - 0.25V 50% OUT (Y, Z) VOH 0V tLZ VCC 50% VOL + 0.25V V OUTPUT LOW OL FIGURE 6B. MEASUREMENT POINTS FIGURE 6A. TEST CIRCUIT FIGURE 6. DRIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490) RE GND +1.5V 3V 15pF B R A A RO 1.5V 1.5V 0V tPLH tPHL VCC SIGNAL GENERATOR 50% RO 50% 0V FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS FIGURE 7. RECEIVER PROPAGATION DELAY RE GND B A R 1kΩ RO VCC SW SIGNAL GENERATOR GND Note 10 3V RE 1.5V 15pF 1.5V 0V tZH, tZH(SHDN) Note 10 PARAMETER DE A SW tHZ 0 +1.5V GND tLZ 0 -1.5V VCC tZH (Note 9) 0 +1.5V GND tZL (Note 9) 0 -1.5V VCC tZH(SHDN) (Note 12) 0 +1.5V GND tZL(SHDN) (Note 12) 0 -1.5V FIGURE 8A. TEST CIRCUIT OUTPUT HIGH VCC tHZ VOH - 0.25V 1.5V RO VOH 0V tZL, tZL(SHDN) Note 10 RO tLZ VCC 1.5V VOL + 0.25V V OUTPUT LOW OL FIGURE 8B. MEASUREMENT POINTS FIGURE 8. RECEIVER ENABLE AND DISABLE TIMES (EXCLUDING ISL83488, ISL83490) FN6052 Rev.5.00 Nov 21, 2018 Page 9 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Application Information RS-485 and RS-422 are differential (balanced) data transmission standards for use in long haul or noisy environments. RS-422 is a subset of RS-485, so RS-485 transceivers are also RS-422 compliant. RS-422 is a point-to-multipoint (multidrop) standard, which allows only one driver and up to 10 (assuming one unit load devices) receivers on each bus. RS-485 is a true multipoint standard, which allows up to 32 one unit load devices (any combination of drivers and receivers) on each bus. To allow for multipoint operation, the RS-485 specification requires that drivers must handle bus contention without sustaining any damage. Another important advantage of RS-485 is the extended Common-Mode Range (CMR), which specifies that the driver outputs and receiver inputs withstand signals that range from +12V to -7V. RS-422 and RS-485 are intended for runs as long as 4000’, so the wide CMR is necessary to handle ground potential differences, as well as voltages induced in the cable by external fields. Receiver Features These devices use a differential input receiver for maximum noise immunity and common-mode rejection. Input sensitivity is ±200mV, as required by the RS422 and RS-485 specifications. Receiver input impedance surpasses the RS-422 spec of 4kΩ, and meets the RS-485 “Unit Load” requirement of 12kΩ minimum. Receiver inputs function with common-mode voltages as great as +9V/-7V outside the power supplies (that is, +12V and -7V), making them ideal for long networks where induced voltages are a realistic concern. All the receivers include a “fail-safe if open” function that ensures a high level receiver output if the receiver inputs are unconnected (floating). Receivers easily meet the data rates supported by the corresponding driver. ISL83483, ISL83485, ISL83491 receiver outputs are tri-statable using the active low RE input. Driver Features The RS-485, RS-422 driver is a differential output device that delivers at least 1.5V across a 54Ω load (RS-485), and at least 2V across a 100Ω load (RS-422) even with VCC = 3V. The drivers feature low propagation delay skew to maximize bit width, and to minimize EMI. Drivers of the ISL83483, ISL83485, and ISL83491 are tri-statable using the active high DE input. ISL83483 and ISL83488 driver outputs are slew rate limited to minimize EMI, and to minimize reflections in unterminated or improperly terminated networks. Data rate on these slew rate limited versions is a maximum of 250kbps. Outputs of ISL83485, ISL83490, and ISL83491 drivers are not limited, so FN6052 Rev.5.00 Nov 21, 2018 faster output transition times allow data rates of at least 10Mbps. Data Rate, Cables, and Terminations RS-485 and RS-422 are intended for network lengths up to 4000’, but the maximum system data rate decreases as the transmission length increases. Devices operating at 10Mbps are limited to lengths of a few hundred feet, while the 250kbps versions can operate at full data rates with lengths in excess of 1000’. Twisted pair is the cable of choice for RS-485 and RS-422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common-mode signals, which are effectively rejected by the differential receivers in these ICs. Proper termination is imperative, when using the 10Mbps devices, to minimize reflections. Short networks using the 250kbps versions need not be terminated, but, terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-to-multipoint (single driver on bus) networks, the main cable should be terminated in its characteristic impedance (typically 120Ω) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Multipoint (multi-driver) systems require that the main cable be terminated in its characteristic impedance at both ends. Stubs connecting a transceiver to the main cable should be kept as short as possible. Built-In Driver Overload Protection As stated previously, the RS-485 specification requires that drivers survive worst case bus contentions undamaged. The ISL834xx devices meet this requirement through driver output short-circuit current limits, and on-chip thermal shutdown circuitry. The driver output stages incorporate short-circuit current limiting circuitry, which ensures that the output current never exceeds the RS-485 specification, even at the common-mode voltage range extremes. Additionally, these devices use a foldback circuit which reduces the short-circuit current, and thus the power dissipation, whenever the contending voltage exceeds either supply. In the event of a major short-circuit condition, the ISL834xx devices also include a thermal shutdown feature that disables the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically re-enable after the die temperature drops about 15°. If the contention persists, the thermal shutdown/re-enable cycle repeats until the fault is cleared. Receivers stay operational during thermal shutdown. Page 10 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Low Power Shutdown Mode (ISL83483, ISL83485, ISL83491 Only) These CMOS transceivers all use a fraction of the power required by their bipolar counterparts, but the ISL83483, ISL83485, and ISL83491 include a shutdown feature that reduces the already low quiescent ICC to a 15nA trickle. They enter shutdown whenever the receiver and driver are simultaneously disabled (RE = VCC and DE = GND) for a Typical Performance Curves period of at least 300ns. Disabling both the driver and the receiver for less than 80ns ensures that shutdown is not entered. Note that receiver and driver enable times increase when these devices enable from shutdown. For more information refer to Notes 8 through 12 on page 7 at the end of the Electrical Specification table. VCC = 3.3V, TA = +25°C, ISL83483 thru ISL83491; Unless otherwise specified 2.9 DIFFERENTIAL OUTPUT VOLTAGE (V) DRIVER OUTPUT CURRENT (mA) 110 100 90 80 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 DIFFERENTIAL OUTPUT VOLTAGE (V) 3 2.8 RDIFF = 100Ω 2.7 2.6 2.5 2.4 2.3 RDIFF = 54Ω 2.2 2.1 2 -40 3.5 -25 0 25 50 75 85 TEMPERATURE (°C) FIGURE 9. DRIVER OUTPUT CURRENT vs DIFFERENTIAL OUTPUT VOLTAGE FIGURE 10. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs TEMPERATURE 160 800 140 120 750 80 60 40 ICC (µA) OUTPUT CURRENT (mA) ISL83483/85, DE = VCC, RE = X Y OR Z = LOW 100 20 0 -20 700 Y OR Z = HIGH -40 650 -60 ISL83483/85, DE = RE = GND; ISL83491, DE = X, RE = GND; ISL83488/90 -80 -100 -120 -7 -6 -4 -2 0 2 4 6 OUTPUT VOLTAGE (V) 8 10 12 FIGURE 11. DRIVER OUTPUT CURRENT vs SHORT-CIRCUIT VOLTAGE FN6052 Rev.5.00 Nov 21, 2018 600 -40 -25 0 25 50 75 TEMPERATURE (°C) FIGURE 12. SUPPLY CURRENT vs TEMPERATURE Page 11 of 19 85 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Typical Performance Curves 1200 300 RDIFF = 54Ω tPLHZ RDIFF = 54Ω Figure 5A |tPHLY - tPLHZ| 250 1100 PROPAGATION DELAY (ns) VCC = 3.3V, TA = +25°C, ISL83483 thru ISL83491; Unless otherwise specified (Continued) |tPLHY - tPHLZ| tPLHY 200 SKEW (ns) 1000 tPHLY 900 150 100 tPHLZ 800 50 |CROSS PT. OF Y↑ & Z↓ - CROSS PT. OF Y↓ & Z↑| 700 -40 -25 0 50 25 TEMPERATURE (°C) 0 -40 85 75 FIGURE 13. DRIVER PROPAGATION DELAY vs TEMPERATURE (ISL83483, ISL83488) 4 RDIFF = 54Ω 15 3.5 14 50 85 75 RDIFF = 54Ω Figure 5A |tPHLY - tPLHZ| 3 13 2.5 SKEW (ns) 11 tPHLY 10 2 1.5 |CROSSING PT. OF Y↑ & Z↓ CROSSING PT. OF Y↓ & Z↑| tPHLY 1 tPHLZ -25 0 25 50 |tPLHY - tPHLZ| 0.5 -40 85 75 -25 TEMPERATURE (°C) DI 5 0 5 RO 0 DRIVER OUTPUT (V) 3 2.5 B/Z 2 1.5 1 0.5 A/Y 0 TIME (400ns/DIV) FIGURE 17. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83483, ISL83488) FN6052 Rev.5.00 Nov 21, 2018 50 85 75 FIGURE 16. DRIVER SKEW vs TEMPERATURE (ISL83485, ISL84390, ISL83491) RECEIVER OUTPUT (V) RDIFF = 54Ω, CL = 15pF DRIVER INPUT (V) FIGURE 15. DRIVER PROPAGATION DELAY vs TEMPERATURE (ISL83485, ISL83490, ISL83491) 0 25 TEMPERATURE (°C) RDIFF = 54Ω, CL = 15pF DI 5 0 5 RO 0 3 2.5 2 A/Y 1.5 1 0.5 B/Z 0 TIME (400ns/DIV) FIGURE 18. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL83483, ISL83488) Page 12 of 19 DRIVER INPUT (V) tPLHY 12 8 -40 RECEIVER OUTPUT (V) 25 TEMPERATURE (°C) tPLHZ 9 DRIVER OUTPUT (V) 0 FIGURE 14. DRIVER SKEW vs TEMPERATURE (ISL83483, ISL83488) 16 PROPAGATION DELAY (ns) -25 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 0 5 RO 0 3 2.5 B/Z 2 1.5 1 A/Y 0.5 0 TIME (10ns/DIV) FIGURE 19. DRIVER AND RECEIVER WAVEFORMS, LOW TO HIGH (ISL83485, ISL83490, ISL83491) RDIFF = 54Ω, CL = 15pF DI 0 5 RO 0 3 2.5 2 A/Y 1.5 1 0.5 B/Z 0 TIME (10ns/DIV) FIGURE 20. DRIVER AND RECEIVER WAVEFORMS, HIGH TO LOW (ISL83485, ISL83490, ISL83491) Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 528 PROCESS: Si Gate CMOS FN6052 Rev.5.00 Nov 21, 2018 5 Page 13 of 19 DRIVER INPUT (V) DI 5 RECEIVER OUTPUT (V) RDIFF = 54Ω, CL = 15pF DRIVER INPUT (V) VCC = 3.3V, TA = +25°C, ISL83483 thru ISL83491; Unless otherwise specified (Continued) DRIVER OUTPUT (V) DRIVER OUTPUT (V) RECEIVER OUTPUT (V) Typical Performance Curves ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE Nov 21, 2018 FN6052.5 Updated part marking in the ordering information table to represent what the brand has been on the products. Added PDIP note in the thermal information section and specified the Pb-free reflow note is applicable to SOIC pages only. Updated disclaimer. Jul 27, 2018 FN6052.4 Added Related Literature on page 1. Updated Ordering Information table. Removed Retired parts, added tape and reel quantity column, and added MSL note. Updated Typical Operating Circuits on page 4. Thermal Information on page 5: Removed Maximum Lead Temperature (Soldering 10s)+300°C (SOIC - Lead Tips Only) Added Pb-Free Reflow information Updated POD M8.15 from rev 0 to rev 4. Changes since rev 0: Removed "u" symbol from drawing (overlaps the "a" on Side View). Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern Changed in Typical Recommended Land Pattern the following: 2.41(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) 0.200 to 5.20(0.205) Changed Note 1 "1982" to "1994" Updated POD M14.15 from rev 0 to rev 1. Changes since rev 0: Added land pattern and moved dimensions from table onto drawing Added Revision History. Updated disclaimer. FN6052 Rev.5.00 Nov 21, 2018 Page 14 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 For the most recent package outline drawing, see E8.3. Package Outline Drawings E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- SEATING PLANE A2 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MAX NOTES - 0.210 - 5.33 4 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 D1 0.005 - 0.13 - 5 A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 13. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 10.16 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - 14. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 15. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 16. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 17. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 18. E and eA are measured with the leads constrained to be perpendicular to datum -C- . N 8 8 9 Rev. 0 12/93 19. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 20. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 21. N is the maximum number of terminal positions. 22. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN6052 Rev.5.00 Nov 21, 2018 Page 15 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 For the most recent package outline drawing, see E14.3. N E14.3 (JEDEC MS-001-AA ISSUE D) E1 INDEX AREA 1 2 3 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE N/2 INCHES -B-AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - C L B 0.014 0.022 0.356 0.558 - eA B1 0.045 0.070 1.15 1.77 8 C C 0.008 0.014 eB D 0.735 0.775 18.66 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 0.204 0.355 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 14 2.54 BSC - 7.62 BSC 6 0.430 - 0.150 2.93 14 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). FN6052 Rev.5.00 Nov 21, 2018 Page 16 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 M8.15 For the most recent package outline drawing, see M8.15. 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN6052 Rev.5.00 Nov 21, 2018 Page 17 of 19 ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 M14.15 For the most recent package outline drawing, see M14.15. 14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 1, 10/09 8.65 A 3 4 0.10 C A-B 2X 6 14 DETAIL"A" 8 0.22±0.03 D 6.0 3.9 4 0.10 C D 2X 0.20 C 2X 7 PIN NO.1 ID MARK 5 0.31-0.51 B 3 (0.35) x 45° 4° ± 4° 6 0.25 M C A-B D TOP VIEW 0.10 C 1.75 MAX H 1.25 MIN 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.10-0.25 1.27 SIDE VIEW (1.27) DETAIL "A" (0.6) NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSEY14.5m-1994. 3. Datums A and B to be determined at Datum H. (5.40) 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 indentifier may be either a mold or mark feature. (1.50) 6. Does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm total in excess of lead width at maximum condition. 7. Reference to JEDEC MS-012-AB. TYPICAL RECOMMENDED LAND PATTERN FN6052 Rev.5.00 Nov 21, 2018 Page 18 of 19 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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