ISL84780IVZ-T

ISL84780 NOT RECOMMENDED FOR NEW DESIGNS RECOMMENDED REPLACEMENT PART ISL84781 DATASHEET Ultra Low ON-Resistance, Low Voltage, Single Supply, Quad 2:1 Analog Multiplexer The Intersil ISL84780 device is a low ON-resistance, low voltage, bidirectional, Quad SPDT (Dual DPDT) analog switch designed to operate from a single +1.6V to +3.6V supply. Targeted applications include battery-powered equipment that benefit from low on-resistance, and fast switching speeds (tON = 12ns, tOFF = 8ns). The digital logic input is 1.8V logic-compatible when using a single +3V supply. Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This family of parts may be used to “mux-in” additional functionality while reducing ASIC design risk. The ISL84780 is offered in small form factor packages, alleviating board space limitations. The ISL84780 is a committed Quad SPDT that consists of four normally open (NO) and four normally closed (NC) switches. This configuration can also be used as a diff dual 2to-1 multiplexer/demultiplexer or a quad 2-to1 multiplexer/demultiplexer. The ISL84780 is pin compatible with the MAX4780. TABLE 1. FEATURES AT A GLANCE ISL84780 Number of Switches 4 SW Quad SPDT (Dual DPDT) 3.0V RON 0.36 3.0V tON/tOFF 12ns/8ns 1.8V RON 0.54 1.8V tON/tOFF 19ns/11ns Packages 16Ld 3x3 TQFN, 16Ld TSSOP FN6099 Rev 1.00 December 27, 2004 Features • Pin Compatible Replacement for the MAX4780 • ON Resistance (RON) - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.36 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.54 • RON Matching between Channels . . . . . . . . . . . . . . . . .0.13 • RON Flatness Across Signal Range . . . . . . . . . . . . . . .0.05 • Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V • Low Power Consumption (PD). . . . . . . . . . . . . . . . . . 6kV MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1kV Thermal Resistance (Typical, Note 3) JA (°C/W) 16 Ld 3x3 TQFN Package . . . . . . . . . . . . . . . . . . . . 75 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 3V Supply PARAMETER Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS Full 0 - V+ V 25 - 0.4 0.6  ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, (See Figure 5) RON Matching Between Channels, RON V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at max RON, (Note 9) RON Flatness, RFLAT(ON) V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+ (Note 7) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V COM ON Leakage Current, ICOM(ON) V = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V, or Floating Full - - 0.7  25 - 0.13 0.2  Full - - 0.2  25 - 0.05 0.15  Full - - 0.15  25 -3 - 3 nA Full -20 - 20 nA 25 -4 - 4 nA Full -30 - 30 nA 25 - 12 20 ns Full - - 25 ns 25 - 8 14 ns Full - - 17 ns DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 8) V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 1, Note 8) Break-Before-Make Time Delay, tD V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, (See Figure 3, Note 8) Full 1 3 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) 25 - -97 - pC OFF Isolation RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 4) 25 - 68 - dB Crosstalk (Channel-to-Channel) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, (See Figure 6) 25 - -98 - dB Total Harmonic Distortion f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32 25 - 0.002 - % NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) 25 - 62 - pF COM ON Capacitance, CCOM(ON) 25 - 125 - pF FN6099 Rev 1.00 December 27, 2004 f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) Page 3 of 11 ISL84780 Electrical Specifications - 3V Supply PARAMETER Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (°C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS Full 1.6 - 3.6 V 25 - - 0.05 A Full - - 1.5 A POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+ DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Full - - 0.5 V Input Voltage High, VINH Full 1.4 - - V Full -0.5 - 0.5 A Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ (Note 8) NOTES: 4. VIN = input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Guaranteed not tested. 9. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron value, between NC1 and NC2, NC3 and NC4 or between NO1 and NO2, NO3 and NO4. Electrical Specifications - 1.8V Supply PARAMETER Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4, 6), Unless Otherwise Specified TEST CONDITIONS TEMP (°C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS Full 0 - V+ V 25 - 0.54 0.9  Full - - 1  25 - 19 25 ns Full - - 30 ns 25 - 11 17 ns Full - - 22 ns ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+, See Figure 5 DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF, See Figure 1, Note 8 V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF, See Figure 1, Note 8 Break-Before-Make Time Delay, tD V+ = 2.0V, VNO or VNC = 1.0V, RL =50, CL = 35pF, See Figure 3, Note 8 Full 1 5 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0, See Figure 2 25 - -52 - pC OFF Isolation RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, See Figure 4 25 - 68 - dB Crosstalk (Channel-to-Channel) RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS, See Figure 6 25 - -98 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 62 - pF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 125 - pF Input Voltage Low, VINL Full - - 0.4 V Input Voltage High, VINH Full 1.0 - - V Full -0.05 - 0.05 A COM ON Capacitance, CCOM(ON) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL FN6099 Rev 1.00 December 27, 2004 V+ = 2.0V, VIN = 0V or V+ (Note 8) Page 4 of 11 ISL84780 Test Circuits and Waveforms V+ V+ LOGIC INPUT tr < 5ns tf < 5ns 50% 0V SWITCH INPUT tOFF VOUT NO or NC COM IN SWITCH INPUT VNO VOUT 90% SWITCH OUTPUT C 90% LOGIC INPUT CL 35pF RL 50 GND 0V tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R  ON  FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ SWITCH OUTPUT VOUT RG VOUT V+ LOGIC INPUT ON ON OFF C VG VOUT COM NO or NC GND IN 0V CL LOGIC INPUT Q = VOUT x CL FIGURE 2B. TEST CIRCUIT FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION V+ V+ LOGIC INPUT VNX C NO VOUT COM NC 0V RL 50 IN SWITCH OUTPUT VOUT 90% 0V LOGIC INPUT CL 35pF GND tD CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS FIGURE 3B. TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME FN6099 Rev 1.00 December 27, 2004 Page 5 of 11 ISL84780 Test Circuits and Waveforms (Continued) V+ V+ C C RON = V1/1mA SIGNAL GENERATOR NO or NC NO or NC VNX IN 0V or V+ 1mA COM COM ANALYZER 0V or V+ IN V1 GND GND RL FIGURE 4. OFF ISOLATION TEST CIRCUIT FIGURE 5. RON TEST CIRCUIT V+ C V+ C SIGNAL GENERATOR NO or NC COM 50 NO or NC IN1 IN 0V or V+ COM ANALYZER 0V or V+ IMPEDANCE ANALYZER RL NC or NO GND COM N.C. FIGURE 6. CROSSTALK TEST CIRCUIT GND FIGURE 7. CAPACITANCE TEST CIRCUIT Detailed Description The ISL84780 is a bidirectional, quad single pole/double throw (SPDT) analog switch that offers precise switching capability from a single 1.6V to 3.6V supply with low onresistance (0.36) and high speed operation (tON = 12ns, tOFF = 8ns). The device is especially well suited for portable battery-powered equipment due to its low operating supply voltage (1.6V), low power consumption (5.4W max), low leakage currents (30nA max), and the tiny TQFN and TSSOP packages. The ultra low on-resistance and Ron flatness provide very low insertion loss and distortion to applications that require signal reproduction. Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal FN6099 Rev 1.00 December 27, 2004 voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (See Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (See Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages. Page 6 of 11 ISL84780 High-Frequency Performance OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM GND OPTIONAL PROTECTION DIODE FIGURE 8. OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL84780 construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL84780 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.6V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. In 50 systems, the signal response is reasonably flat even past 30MHz with a -3dB bandwidth of 104MHz (See Figure 15). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from the switch input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 16 details the high Off Isolation and Crosstalk rejection provided by this part. At 100kHz, Off Isolation is about 68dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. Logic-Level Thresholds This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.0V to 3.6V (See Figure 17). At 3.6V the VIH level is about 1.27V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. FN6099 Rev 1.00 December 27, 2004 Page 7 of 11 ISL84780 Typical Performance Curves TA = 25°C, Unless Otherwise Specified 0.55 0.4 ICOM = 100mA 85°C 0.5 V+ = 1.8V 0.35 RON () RON () 0.45 0.4 25°C 0.3 -40°C V+ = 2.7V 0.35 V+ = 3V ICOM = 100mA V+ = 3V 0.3 V+ = 3.6V 0 1 2 3 0.25 4 0 0.5 1 1.5 2 2.5 3 VCOM (V) VCOM (V) FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE 100 0.6 V+ = 1.8V ICOM = 100mA 85°C 0.55 50 25°C V+ = 3V 0.5 0 V+ = 1.8V Q (pC) RON () -40°C 0.45 -50 0.4 -100 0.35 0.3 -150 0 0.5 1 1.5 0 2 0.5 1 FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE 2.5 3 20 40 15 30 tOFF (ns) tON (ns) 2 FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE 50 85°C 25°C 20 1.5 25°C -40°C 0 1 85°C 10 5 -40°C 10 0 1.5 VCOM (V) VCOM (V) 2 2.5 3 V+ (V) 3.5 4 FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE FN6099 Rev 1.00 December 27, 2004 4.5 1 1.5 2 2.5 3 3.5 4 V+ (V) FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE Page 8 of 11 4.5 ISL84780 0 GAIN 0 PHASE 20 40 60 80 RL = 50 VIN = 0.2VP-P to 2VP-P 1 10 100 100 FREQUENCY (MHz) CROSSTALK (dB) -20 -20 20 -30 30 -40 40 -50 50 60 -60 ISOLATION 70 -70 80 -80 CROSSTALK -90 90 100 -100 -110 1k 600 10 V+ = 3V FIGURE 15. FREQUENCY RESPONSE 10k 100k 1M 10M FREQUENCY (Hz) 110 100M 500M FIGURE 16. CROSSTALK AND OFF ISOLATION 1.5 1.4 Die Characteristics 1.3 SUBSTRATE POTENTIAL (POWERED UP): VINH AND VINL (V) 1.2 GND (QFN Paddle Connection: To Ground or Float) 1.1 TRANSISTOR COUNT: VINH 1 228 0.9 0.8 PROCESS: VINL Si Gate CMOS 0.7 0.6 0.5 0.4 0.3 1 1.5 2 2.5 3 3.5 4 4.5 V+ (V) FIGURE 17. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE FN6099 Rev 1.00 December 27, 2004 OFF ISOLATION (dB) -10 V+ = 3V PHASE (DEGREES) NORMALIZED GAIN (dB) Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) Page 9 of 11 ISL84780 Thin Shrink Small Outline Plastic Packages (TSSOP) M16.173 N 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA E 0.25(0.010) M E1 2 INCHES GAUGE PLANE -B1 B M 0.05(0.002) -A- SYMBOL MIN MAX MIN MAX NOTES A - 0.043 - 1.10 - A1 3 L A D -C- e  c 0.10(0.004) C A M 0.05 0.15 - A2 0.033 0.037 0.85 0.95 - b 0.0075 0.012 0.19 0.30 9 c 0.0035 0.008 0.09 0.20 - B S 0.002 D 0.193 0.201 4.90 5.10 3 0.169 0.177 4.30 4.50 4 0.026 BSC E 0.246 L 0.020 N  NOTES: 0.006 E1 e A2 A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE MILLIMETERS 0.65 BSC 0.256 6.25 0.028 0.50 16 0o - 0.70 6 16 8o 0o 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. - 6.50 7 8o Rev. 1 2/02 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) © Copyright Intersil Americas LLC 2004. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6099 Rev 1.00 December 27, 2004 Page 10 of 11 ISL84780 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP) ) 2X A L16.3x3A 0.15 C A D 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE 9 D/2 MILLIMETERS D1 D1/2 2X N 6 INDEX AREA 0.15 C B 1 2 3 E1/2 E/2 E1 0.15 C B A2 0 4X B TOP VIEW A 0.70 0.75 0.80 - - - 0.05 - A2 - - 0.80 9 0.30 5, 8 0.20 REF 0.18 A3 SIDE VIEW 9 5 NX b 4X P D 3.00 BSC - 2.75 BSC 9 1.35 - E1 2.75 BSC 9 1.35 1.65 7, 8, 10 - k 0.20 - - - L 0.30 0.40 0.50 8 2 4 3 NX k Ne 1 2 3 6 INDEX AREA E2/2 NX L N e 9  - - 12 9 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. A1 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. SECTION "C-C" C L 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. L e 0.60 2. N is the number of terminals. NX b 10 - 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 8 BOTTOM VIEW C L 3 - NOTES: 9 CORNER OPTION 4X (Nd-1)Xe REF. 4 P Rev. 0 6/04 (Ne-1)Xe REF. E2 7 FN6099 Rev 1.00 December 27, 2004 1.50 0.50 BSC 16 D2 2 N FOR ODD TERMINAL/SIDE 7, 8, 10 N (DATUM A) C C 1.65 3.00 BSC Nd 7 L1 1.50 E 8 4X P 8 9 0.10 M C A B D2 (DATUM B) A1 0.23 D1 e SEATING PLANE NOTES A E2 0.08 C MAX A1 D2 / / 0.10 C C NOMINAL b 9 0.15 C A MIN A3 E 2X 2X SYMBOL L1 10 L e TERMINAL TIP FOR EVEN TERMINAL/SIDE 9. Features and dimensions A2, A3, D1, E1, P &  are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2 and D2 MAX dimension. Page 11 of 11