DATASHEET
ISL8484
Ultra Low ON-Resistance, +1.65V to +4.5V, Single Supply, Dual SPDT Analog
Switch
The Intersil ISL8484 device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
analog switch designed to operate from a single +1.65V to
+4.5V supply. Targeted applications include battery powered
equipment that benefit from low rON (0.29 and fast
switching speeds (tON = 40ns, tOFF = 20ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
With a supply voltage of 4.2V and logic high voltage of 2.85V
at both logic inputs, the part draws only 12µA max of I+
current.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL8484 is offered in small form factor packages, alleviating
board space limitations.
The ISL8484 is a committed dual single-pole/double-throw
(SPDT) that consist of two normally open (NO) and two
normally closed (NC) switches. This configuration can be
used as a dual 2-to-1 multi-plexer. The ISL8484 is pin
compatible with the MAX4684 and MAX4685.
TABLE 1. FEATURES AT A GLANCE
ISL8484
NUMBER OF SWITCHES
2
SW
SPDT or 2-1 MUX
4.3V rON
0.29
4.3V tON/tOFF
40ns/20ns
3V rON
0.33
3V tON/tOFF
50ns/27ns
1.8V rON
0.55
1.8V tON/tOFF
70ns/54ns
Packages
10 Ld 3x3 Thin DFN, 10 Ld MSOP
FN6128
Rev 5.00
May 12, 2008
Features
• Pin Compatible Replacement for the MAX4684 and
MAX4685
• ON-Resistance (rON)
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.33
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55
• rON Matching Between Channels . . . . . . . . . . . . . . . . .0.06
• rON Flatness Across Signal Range . . . . . . . . . . . . . . . .0.03
• Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (PD) . . . . . . . . . . . . . . .8kV
• Guaranteed Break-Before-Make
• 1.8V Logic Compatible (+3V supply)
• Low I+ Current when VINH is not at the V+ Rail
• Available in 10 Ld 3x3 TDFN and 10 Ld MSOP
• Pb-Free Available (RoHS Compliant)
Applications
• Battery-powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
FN6128 Rev 5.00
May 12, 2008
Page 1 of 13
ISL8484
Pinout
Truth Table
(Note 1)
ISL8484
(10 LD TDFN, MSOP)
TOP VIEW
10 NO2
V+ 1
8 IN2
COM1 3
IN1 4
7 NC2
NC1 5
6 GND
NC1 and NC2
NO1 and NO2
0
ON
OFF
1
OFF
ON
NOTE:
9 COM2
NO1 2
LOGIC
Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
Pin Descriptions
PIN
V+
NOTE:
1. Switches Shown for Logic “0” Input.
FUNCTION
System Power Supply Input (+1.65V to +4.5V)
GND
Ground Connection
INx
Digital Control Input
COMx
Analog Switch Common Pin
NOx
Analog Switch Normally Open Pin
NCx
Analog Switch Normally Closed Pin
Ordering Information
PART NUMBER
PART MARKING
TEMP. RANGE
(°C)
PACKAGE
PKG.
DWG. #
ISL8484IR*
484
-40 to +85
10 Ld 3x3 TDFN
L10.3x3A
ISL8484IU*
8484
-40 to +85
10 Ld MSOP
M10.118
ISL8484IRZ*
(Note)
484Z
-40 to +85
10 Ld 3x3 TDFN
(Pb-free)
L10.3x3A
ISL8484IUZ*
(Note)
8484Z
-40 to +85
10 Ld MSOP
(Pb-free)
M10.118
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN6128 Rev 5.00
May 12, 2008
Page 2 of 13
ISL8484
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Input Voltages
NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 500mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV
Thermal Resistance (Typical)
JA (°C/W)
JC (°C/W)
10 Ld 3x3 TDFN Package (Notes 3, 4)
52
11
10 Ld MSOP Package (Note 5) . . . . . .
140
N/A
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6),
Unless otherwise specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 7, 11)
TYP
MAX
(Notes 7, 11) UNITS
Full
0
-
V+
V
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+
(Figure 5, Note 9)
rON Matching Between Channels,
rON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage
at max RON (Note 9, 10)
rON Flatness, rFLAT(ON)
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+
(Note 8, 9)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or Floating
25
-
0.30
0.5
Full
-
0.35
0.7
25
-
0.06
0.07
Full
-
0.08
0.08
25
-
0.03
0.15
Full
-
0.04
0.15
25
-100
-
100
nA
Full
-195
-
195
nA
25
-100
-
100
nA
Full
-195
-
195
nA
25
-
40
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF
(Figure 1)
Turn-OFF Time, tOFF
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF
(Figure 1)
Full
-
50
-
ns
25
-
20
-
ns
Full
-
30
-
ns
Break-Before-Make Time Delay, tD V+ = 4.5V, VNO or VNC = 3.0V, RL = 50, CL = 35pF
(Figure 3)
Full
-
8
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Figure 2)
25
-
170
-
pC
OFF Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(Figure 4)
25
-
62
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(Figure 6)
25
-
-85
-
dB
FN6128 Rev 5.00
May 12, 2008
Page 3 of 13
ISL8484
Electrical Specifications - 4.3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6),
Unless otherwise specified.
TEMP
(°C)
MIN
(Notes 7, 11)
TYP
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25
-
0.005
-
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7)
25
-
62
-
pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7)
25
-
176
-
pF
Full
1.65
-
4.5
V
25
-
-
0.1
µA
Full
-
-
1
µA
25
-
-
12
µA
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.4
-
-
V
Full
-0.5
-
0.5
µA
PARAMETER
Total Harmonic Distortion
TEST CONDITIONS
MAX
(Notes 7, 11) UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
Positive Supply Current, I+
V+ = +4.5V, VIN = 0V or V+
V+ = +4.2V, VIN = 2.85V
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+ (Note 9)
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6),
Unless otherwise specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 7, 11)
TYP
MAX
(Notes 7, 11) UNITS
Full
0
-
V+
V
25
-
0.35
0.5
Full
-
-
0.7
ANALOG SWITCH CHARACTERISTICS
Analog Signal range, VANALOG
ON-Resistance, rON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(Figure 5)
rON Matching Between Channels,
rON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage
at max RON (Note 10)
rON Flatness, rFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+
(Note 8)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or Floating
25
-
0.06
0.07
Full
-
-
0.08
25
-
0.03
0.15
Full
-
-
0.15
25
-
0.9
-
nA
Full
-
30
-
nA
25
-
0.8
-
nA
Full
-
30
-
nA
25
-
50
-
ns
Full
-
60
-
ns
25
-
27
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF
(Figure 1)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF
(Figure 1)
Full
-
35
-
ns
Break-Before-Make Time Delay, tD
V+ = 3.3V, VNO or VNC = 1.5V, RL = 50, CL = 35pF
(Figure 3)
Full
-
9
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Figure 2)
25
-
94
-
pC
OFF Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(Figure 4)
25
-
62
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(Figure 6)
25
-
-85
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25
-
0.005
-
%
FN6128 Rev 5.00
May 12, 2008
Page 4 of 13
ISL8484
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6),
Unless otherwise specified. (Continued)
TEMP
(°C)
MIN
(Notes 7, 11)
TYP
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7)
25
-
65
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7)
25
-
181
-
pF
25
-
0.01
-
µA
Full
-
0.52
-
µA
PARAMETER
COM ON Capacitance, CCOM(ON)
TEST CONDITIONS
MAX
(Notes 7, 11) UNITS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = +3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
25
-
-
0.5
V
Input Voltage High, VINH
25
1.4
-
-
V
Full
-0.5
-
0.5
µA
Input Current, IINH, IINL
V+ = 3.3V, VIN = 0V or V+ (Note 9)
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 6),
Unless otherwise specified.
TEMP
(°C)
MIN
(Notes 7, 11)
TYP
Full
0
-
V+
V
25
-
0.7
0.8
Full
-
-
0.85
25
-
70
-
ns
Full
-
80
-
ns
25
-
54
-
ns
Full
-
65
-
ns
Full
-
10
-
ns
25
-
42
-
pC
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7)
25
-
70
-
pF
COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V (Figure 7)
25
-
186
-
pF
25
-
-
0.4
V
PARAMETER
TEST CONDITIONS
MAX
(Notes 7, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 1.65V, ICOM = 100mA, VNO or VNC = 0V to V+
(Figure 5)
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF
(Figure 1)
V+ = 1.65V, VNO or VNC = 1.0V, RL = 50, CL = 35pF
(Figure 1)
Break-Before-Make Time Delay, tD V+ = 2.0V, VNO or VNC = 1.0V, RL = 50, CL = 35pF
(Figure 3)
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Figure 2)
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+ (Note 9)
25
1.0
-
-
V
Full
-0.5
-
0.5
µA
NOTES:
6. VIN = input voltage to perform proper function.
7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
8. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
9. Limits established by characterization and are not production tested.
10. RON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2 or between NO1 and NO2.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN6128 Rev 5.00
May 12, 2008
Page 5 of 13
ISL8484
Test Circuits and Waveforms
V+
LOGIC
INPUT
V+
tr < 5ns
tf < 5ns
50%
0V
tOFF
SWITCH
INPUT VNO
SWITCH
INPUT
VOUT
NO OR NC
COM
IN
VOUT
90%
SWITCH
OUTPUT
C
90%
LOGIC
INPUT
CL
35pF
RL
50
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
rL
V OUT = V (NO or NC) -------------------------r L + r ON
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
RG
SWITCH
OUTPUT
VOUT
C
VOUT
COM
NO OR NC
VOUT
VG
GND
IN
CL
V+
LOGIC
INPUT
ON
ON
OFF
LOGIC
INPUT
0V
Q = VOUT x CL
Repeat test for all switches.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
V+
LOGIC
INPUT
VNX
NO
RL
50
IN
SWITCH
OUTPUT
VOUT
90%
0V
LOGIC
INPUT
VOUT
COM
NC
0V
C
CL
35pF
GND
tD
FIGURE 3A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
FN6128 Rev 5.00
May 12, 2008
Page 6 of 13
ISL8484
Test Circuits and Waveforms (Continued)
V+
C
V+
C
SIGNAL
GENERATOR
RON = V1/100mA
NO OR NC
NO OR NC
IN
VNX
0V OR V+
100mA
IN
V1
0V OR V+
COM
ANALYZER
GND
COM
RL
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO OR NC
COM
50
NO OR NC
IN1
IN
0V OR V+
COM
ANALYZER
RL
NC or NO
COM
NC
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL8484 is a bidirectional, dual single pole/double throw
(SPDT) analog switch that offers precise switching capability
from a single 1.65V to 4.5V supply with low on-resistance
(0.29) and high speed operation (tON = 40ns, tOFF = 20ns).
The device is especially well suited for portable
battery-powered equipment due to its low operating supply
voltage (1.65V), low power consumption (4.5µW max), low
leakage currents (195nA max), and the tiny DFN and MSOP
packages. The ultra low on-resistance and rON flatness
provide very low insertion loss and distortion to applications
that require signal reproduction.
External V+ Series Resistor
For improved ESD and latch-up immunity Intersil
recommends adding a 100 resistor in series with the V+
power supply pin of the ISL8484 IC (see Figure 8).
FN6128 Rev 5.00
May 12, 2008
0V OR V+
IMPEDANCE
ANALYZER
GND
Repeat test for all switches.
FIGURE 7. CAPACITANCE TEST CIRCUIT
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from the
V+ power supply to ground. This will result in a significant
amount of current flow in the IC which can potentially create a
latch-up state or permanently damage the IC. The external V+
resistor limits the current during this over-stress situation and
has been found to prevent latch-up or destructive damage for
many overvoltage transient events.
Under normal operation the sub-microamp IDD current of the
IC produces an insignificant voltage drop across the 100
series resistor resulting in no impact to switch operation or
performance.
Page 7 of 13
ISL8484
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the purpose
of using a low rON switch. Connecting Schottky diodes to the
signal pins as shown in Figure 8 will shunt the fault current to
the supply or to ground thereby protecting the switch. These
Schottky diodes must be sized to handle the expected fault
current.
.
V+
OPTIONAL
PROTECTION
RESISTOR
C
100
NO
COM
NC
Power-Supply Considerations
IN
GND
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer to
the “Electrical Specifications” tables, beginning on page 3, and
“Typical Performance Curves”, beginning on page 9, for
details.
OPTIONAL
SCHOTTKY
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNX
OPTIONAL
SCHOTTKY
DIODE
The ISL8484 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins: V+
and GND. V+ and GND drive the internal CMOS switches and
set their analog voltage limits. Unlike switches with a 4V
maximum supply voltage, the ISL8484 5.5V maximum supply
voltage provides plenty of room for the 10% tolerance of 4.3V
supplies, as well as room for overshoot and noise spikes.
VCOM
GND
V+ and GND also power the internal logic and level shiftiers.
The level shiftiers convert the input logic levels to switched V+
and GND signals to drive the analog switch gate terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes negative
in this configuration.
Logic-Level Thresholds
FIGURE 9. OVERVOLTAGE PROTECTION
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 9). To prevent forward biasing these diodes, V+ must be
applied before any input signals, and the input signal voltages
must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at the
logic pin and signal pins from exceeding the maximum ratings
of the switch. The following two methods can be used to
provided additional protection to limit the current in the event
that the voltage at a signal pin or logic pin goes below ground
or above the V+ rail.
Logic inputs can be protected by adding a 1k resistor in
series with the logic input (see Figure 9). The resistor limits the
input current below the threshold that produces permanent
damage, and the sub-microamp input current produces an
insignificant voltage drop during normal operation.
FN6128 Rev 5.00
May 12, 2008
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.7V to 4.5V (see Figure18). At 2.7V the
VIL level is about 0.53V. This is still above the 1.8V CMOS
guaranteed low output maximum level of 0.5V, but noise
margin is reduced.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving the
digital input signals from GND to V+ with a fast transition time
minimizes power dissipation.
The ISL8484 has been designed to minimize the supply
current whenever the digital input voltage is not driven to the
supply rails (0V to V+). For example driving the device with
2.85V logic (0V to 2.85V) while operating with a 4.2V supply
the device draws only 12µA of current
(see Figure17 for VIN = 2.85V).
High-Frequency Performance
In 50 systems, the signal response is reasonably flat even
past 30MHz with a -3dB bandwidth of 120MHz (see Figure 22).
The frequency response is very consistent over a wide V+
range, and for varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off Isolation is
Page 8 of 13
ISL8484
the resistance to this feedthrough, while crosstalk indicates the
amount of feedthrough from one switch to another. Figure 23
details the high off isolation and crosstalk rejection provided by
this part. At 100kHz, off isolation is about 62dB in 50
systems, decreasing approximately 20dB per decade as
frequency increases. Higher load impedances decrease off
isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected between
each analog-signal pin and both V+ and GND. One of these
diodes conducts if any analog signal exceeds V+ or GND.
signal pin are identical and therefore fairly well balanced, they
are reverse biased differently. Each is biased by either V+ or
GND and the analog signal. This means their leakages will
vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the
analog-signal-path leakage current. All analog leakage current
flows between each pin and one of the supply terminals, not to
the other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
Typical Performance Curves TA = +25°C, Unless Otherwise Specified.
0.30
0.35
ICOM = 100mA
ICOM = 100mA
0.34
0.29
0.33
V+ = 2.7V
rON ()
rON ()
0.28
0.27
V+ = 3.9V
0.32
0.31
V+ = 3V
0.3
0.26
0.29
V+ = 4.3V
0.25
V+ = 4.5V
0
1
2
3
4
V+ = 3.3V
0.28
5
0
0.5
1.0
1.5
2.0
VCOM (V)
VCOM (V)
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.35
3.5
V+ = 4.3V
ICOM = 100mA
ICOM = 100mA
0.65
+85°C
V+ = 1.65V
0.30
0.50
rON ()
0.55
rON ()
3.0
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.70
0.60
2.5
V+ = 1.8V
+25°C
0.45
0.25
V+ = 2V
0.40
0.35
-40°C
0.30
0.20
0
0.5
1.0
1.5
VCOM (V)
FIGURE 12. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FN6128 Rev 5.00
May 12, 2008
2.0
0
1.0
2.0
3.0
VCOM (V)
4.0
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
Page 9 of 13
5.0
ISL8484
Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued)
0.40
0.40
V+ = 3.3V
ICOM = 100mA
V+ = 2.7V
ICOM = 100mA
+85°C
0.35
0.30
0.35
rON ()
rON ()
+85°C
+25°C
+25°C
0.30
0.25
-40°C
-40°C
0.20
0
0.5
1.0
1.5
2.0
2.5
3.0
0.25
3.5
0
0.5
1.0
1.5
0.60
3.0
200
V+ = 1.8V
ICOM = 100mA
+85°C
V+ = 4.2V
SWEEPING BOTH LOGIC INPUTS
+25°C
150
0.50
-40°C
0.45
ION (mA)
rON ()
2.5
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 14. ON RESISTANCE vs SWITCH VOLTAGE
0.55
2.0
VCOM (V)
VCOM (V)
0.40
0.35
100
50
0.30
0
0.25
0
0.5
1.0
VCOM (V)
1.5
1
2.0
2
3
4
5
VIN 1 AND 2 (V)
FIGURE 16. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 17. SUPPLY CURRENT vs VLOGIC VOLTAGE
200
1.1
1.0
150
0.9
50
V+ = 4.3V
V+ = 1.8V
0
0.8
VINH
0.7
VINL
0.6
0.5
V+ = 3V
-50
-100
VINH AND VINL (V)
Q (pC)
100
0.4
0
1
2
3
4
VCOM (V)
FIGURE 18. CHARGE INJECTION vs SWITCH VOLTAGE
FN6128 Rev 5.00
May 12, 2008
5
0.3
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V+ (V)
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
Page 10 of 13
ISL8484
250
200
200
150
+85°C
150
tOFF (ns)
tON (ns)
Typical Performance Curves TA = +25°C, Unless Otherwise Specified. (Continued)
+25°C
+85°C
100
+25°C
-40°C
100
50
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
0
1.0
4.5
3.5
4.0
4.5
10
V+ = 4.3V
GAIN
-20
0
PHASE
20
60
80
RL = 50
VIN = 0.2VP-P to 2VP-P
10
PHASE (°)
40
1
2.5
3.0
V+ (V)
-10
V+ = 3V
0
2.0
FIGURE 21. TURN-OFF TIME vs SUPPLY VOLTAGE
100
100
600
FREQUENCY (MHz)
FIGURE 22. FREQUENCY RESPONSE
CROSSTALK (dB)
NORMALIZED GAIN (dB)
FIGURE 20. TURN-ON TIME vs SUPPLY VOLTAGE
1.5
-20
20
-30
30
-40
40
-50
50
ISOLATION
-60
60
-70
70
-80
80
CROSSTALK
-90
90
-100
-110
1k
100
10k
100k
1M
10M
110
100M 500M
FREQUENCY (Hz)
FIGURE 23. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND (DFN Paddle Connection: Tie to GND or Float)
TRANSISTOR COUNT:
114
PROCESS:
Submicron CMOS
FN6128 Rev 5.00
May 12, 2008
OFF ISOLATION (dB)
25
1.0
-40°C
Page 11 of 13
ISL8484
Thin Dual Flat No-Lead Plastic Package (TDFN)
L10.3x3A
2X
0.10 C A
A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
E
B
//
A
C
SEATING
PLANE
D2
(DATUM B)
6
INDEX
AREA
0.10 C
0.08 C
A3
SIDE VIEW
7
8
NOMINAL
MAX
NOTES
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
0.20 REF
b
0.20
-
0.25
0.30
1
5, 8
D
2.95
3.0
3.05
-
D2
2.25
2.30
2.35
7, 8
E
2.95
3.0
3.05
-
E2
1.45
1.50
1.55
7, 8
e
0.50 BSC
-
k
0.25
-
-
-
L
0.25
0.30
0.35
8
N
10
2
Nd
5
3
Rev. 3 3/06
D2/2
NOTES:
2
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
NX k
3. Nd refers to the number of terminals on D.
(DATUM A)
4. All dimensions are in millimeters. Angles are in degrees.
E2
E2/2
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX L
N
8
MIN
A3
6
INDEX
AREA
TOP VIEW
SYMBOL
N-1
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
0.10 M C A B
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
CL
NX (b)
(A1)
L1
5
9 L
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FN6128 Rev 5.00
May 12, 2008
Page 12 of 13
ISL8484
Mini Small Outline Plastic Packages
(MSOP)
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
N
SYMBOL
E1
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X
0.25
(0.010)
R1
R
GAUGE
PLANE
A
4X
A2
A1
b
-H-
0.10 (0.004)
L
L1
SEATING
PLANE
C
-A-
e
D
0.20 (0.008)
C
C
MILLIMETERS
MAX
MIN
0.037
0.043
0.94
1.10
-
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.007
0.011
0.18
0.27
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.020 BSC
0.50 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
L1
0.037 REF
0.95 REF
-
N
10
10
7
R
0.003
-
0.07
-
-
R1
0.003
-
0.07
-
-
5o
15o
5o
15o
-
0o
6o
0o
6o
Rev. 0 12/02
CL
E1
0.20 (0.008)
NOTES
A
a
SIDE VIEW
MAX
A1
e
SEATING
PLANE -C-
MIN
C D
-B-
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material
condition.
Minimum
space LLC 2006-2008. All Rights Reserved.
© Copyright
Intersil
Americas
between protrusion and
lead is
0.07mm
(0.0027
inch).
Alladjacent
trademarks
and
registered
trademarks
are the property of their respective owners.
10. Datums -A -H- .
and - B -
to be determined at Datum plane
11. Controlling dimension: MILLIMETER. For
Converted
inch
dimen- see www.intersil.com/en/products.html
additional
products,
sions are for reference only
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6128 Rev 5.00
May 12, 2008
Page 13 of 13
工商网监
湘ICP备2023018690号
