DATASHEET
ISL85033
Wide VIN Dual Standard Buck Regulator With 3A/3A Continuous Output Current
FN6676
Rev 8.00
February 17, 2015
Features
The ISL85033 is a dual standard buck regulator capable of 3A
per channel continuous output current. With an input range of
4.5V to 28V, it provides a high frequency power solution for a
variety of point of load applications.
• Wide input voltage range from 4.5V to 28V
• Adjustable output voltage with continuous output current up
to 3A
The PWM controller in the ISL85033 drives an internal
switching N-Channel power MOSFET and requires an external
Schottky diode to generate the output voltage. The integrated
power switch is optimized for excellent thermal performance
up to 3A of output current. The PWM regulator switches at a
default frequency of 500kHz and it can be user programmed
or synchronized from 300kHz to 2MHz. The ISL85033 utilizes
peak current mode control to provide flexibility in component
selection and minimize solution size. The protection features
include overcurrent, UVLO and thermal overload protection.
• Current mode control
• Adjustable switching frequency from 300kHz to 2MHz
• Independent power-good detection
• Selectable in-phase or out-of-phase PWM operation
• Independent, sequential, ratiometric or absolute tracking
between outputs
• Internal 2ms soft-start time
• Overcurrent/short circuit protection, thermal overload
protection, UVLO
The ISL85033 is available in a small 4mmx4mm Thin Quad
Flat No-Lead (TQFN) Pb-free package.
• Boot undervoltage detection
Related Literature
• Pb-free (RoHS compliant)
• AN1574 “ISL85033DUALEVAL1Z Wide VIN Dual Standard
Buck Regulator With 3A/3A Output Current”
Applications
• AN1585 “ISL85033EVAL2Z (Small Form) Wide VIN Dual
Standard Buck Regulator With 3A/3A Output Current - Short
Form”
• Set-top boxes
• General purpose point-of-load DC/DC power conversion
• FPGA power and STB power
• AN1584 “ISL85033EVAL2Z (Small Form) Wide VIN Dual
Standard Buck Regulator With 3A/3A Output Current - Long
Form”
• DVD and HDD drives
• AN1605 “ISL85033CRSHEVAL1Z Wide VIN Current sharing
Standard Buck Regulator With 6A Output Current”
• Cable modems
• LCD panels, TV power
100
EFFICIENCY (%)
90
12VOUT 1MHz
80
70
60
50
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT LOAD (A)
FIGURE 1. EFFICIENCY vs LOAD, VIN = 28V, TA = +25°C
FN6676 Rev 8.00
February 17, 2015
Page 1 of 26
ISL85033
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operation Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-on Reset and Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
16
16
Output Tracking and Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Regulator Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT Undervoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
18
18
Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sharing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Theory of Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Comparator Gain Fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Stage Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rectifier Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
18
18
18
18
19
19
19
20
20
20
21
22
22
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FN6676 Rev 8.00
February 17, 2015
Page 2 of 26
ISL85033
Pin Configuration
PGOOD1
FS
NC
SGND
SYNCIN
SYNCOUT
PGOOD2
ISL85033
(28 LD TQFN)
TOP VIEW
28
27
26
25
24
23
22
COMP1
1
21 COMP2
FB1
2
20 FB2
SS1
3
19 SS2
PGND1
4
BOOT1
5
17 BOOT2
PHASE1
6
16 PHASE2
PHASE1
7
15 PHASE2
18 PGND2
9
10
11
12
13
VIN1
EN1
VCC
EN2
VIN2
14
VIN2
8
VIN1
PD
Pin Descriptions
PIN NUMBER
SYMBOL
1, 21
COMP1, COMP2
2, 20
FB1, FB2
Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. COMP is the
output of the error amplifier. The output voltage is set by an external resistor divider connected to FB.
In addition, the PWM regulator’s power-good and undervoltage protection circuits use FB1, FB2 to monitor
the regulator output voltage.
3, 19
SS1, SS2
Soft-start pins for each controller. The SS1, SS2 pins control the soft-start and sequence of their respective
outputs. A single capacitor from the SS pin to ground determines the output ramp rate. See the “Output
Tracking and Sequencing” on page 16 for soft-start and output tracking/sequencing details. If SS pins are
tied to VCC, an internal soft-start of 2ms will be used. Maximum CSS value is 100nF.
4, 18
PGND1, PGND2
Power ground connections. Connect directly to the system GND plane.
5, 17
BOOT1, BOOT2
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the
necessary charge to turn on the internal N-Channel MOSFET. Connect an external capacitor from this pin to
PHASE.
6, 7, 15, 16
PHASE1, PHASE2
Switch node output. It connects the source of the internal power MOSFET with the external output inductor
and with the cathode of the external diode.
8, 9, 13, 14
VIN1, VIN2
The input supply for the power stage of the PWM regulator and the source for the internal linear regulator
that provides bias for the IC. Place a minimum of 10µF ceramic capacitance from each VIN to GND and
close to the IC for decoupling.
10, 12
EN1, EN2
PWM controller’s enable inputs. The PWM controllers are held off when the pin is pulled to ground. When
the voltage on this pin rises above 2V, the PWM controller is enabled. If EN1, EN2 pins are driven by an
external signal, the minimum off-time for EN1, EN2 should be:
EN_T_off s = 10s C SS 2.2nF
where CSS is the soft-start pin capacitor (nF). The ISL85033 does not have debouncing to EN1, EN2 external
signals.
11
VCC
Output of the internal 5V linear regulator. Decouple to PGND with a minimum of 4.7µF ceramic capacitor.
This pin is provided only for internal bias of ISL85033 (not to be loaded with current over 10mA).
FN6676 Rev 8.00
February 17, 2015
PIN DESCRIPTION
COMP1, COMP2 are the output of the error amplifier.
Page 3 of 26
ISL85033
Pin Descriptions (Continued)
PIN NUMBER
SYMBOL
23
SYNCOUT
24
SYNCIN
25
SGND
26
NC
This is a no connection pin.
27
FS
Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for
adjustable frequency from 300kHz to 2MHz.
22, 28
PGOOD2, PGOOD1
PD
FN6676 Rev 8.00
February 17, 2015
PIN DESCRIPTION
Synchronization output. Provides a signal that is the inverse of the SYNCIN signal.
Connect to an external signal for synchronization from 300kHz to 2MHz (negative edge trigger). SYNCIN is
not allowed to be floating.
When SYNCIN = logic 0, PHASE1 and PHASE2 are running at 180° out-of-phase.
When SYNCIN = logic 1, PHASE1 and PHASE2 are running at 0° in-phase.
When SYNCIN = an external clock, PHASE1 and PHASE2 are running at 180° out-of-phase.
External SYNC frequency applied to the SYNCIN pin should be at least 2.4 x the internal switching frequency
setting.
Signal ground connections. The exposed pad must be connected to SGND and soldered to the PCB. All
voltage levels are measured with respect to this pin.
Open-drain power-good output that is pulled to ground when the output voltage is below regulation limits or
during the soft-start interval. There is an internal 5MΩ internal pull-up resistor.
The exposed pad must be connected to the system GND plane with as many vias as possible for proper
electrical and thermal performance.
Page 4 of 26
ISL85033
Typical Application Schematics
R6
8.06k
FB2
COMP2
C4
68pF
VCC
VCC
SS1 3
VCC
PGOOD2
PGOOD1
L2
7µH
VOUT2
3A
C5
470pF
C2
470pF
R8
69.8k
R4
69.8k
21
20
FS 27
SS2 19
C1
68pF
1
2
8/9 VIN1
10µF
22
C72
ISL85033
28
PHASE2
L1
7µH
PHASE1
6/7
C12
10nF
D2
B340B
C71
20µF
VIN2
13/14
15/16
5 BOOT1
C8
10nF
EN1
11
VCC
10 25
SGND
26
NC
12
EN2
23 4/18
SYNCOUT
SYNCIN
24
VOUT1
3A
C9
47µF
D1
B340B
BOOT2 17
PGND1/2
C13
47µF
VOUT1
R1
42.2k
R2
8.06k
FB1
R5
25.5k
COMP1
VOUT2
4.7µF
FIGURE 2. DUAL 3A OUTPUT (VIN RANGE FROM 4.5V TO 28V)
FB2
VOUT1
R5
42.2k
COMP2
C5
1nF
20
SS2
SS1
PHASE2
13/14
3
6/7
15/16
C12
10nF
17
23 4/18
12
26
10
25
C71
20µF
VIN2
C72
VOUT1
6A
PHASE1
BOOT1
C8
10nF
L1
7µH
D1
B340B
C9
47µF
11
VCC
24
SGND
BOOT2
5
SYNCIN
B340B
VIN1
10µF
ISL85033
EN2
D2
FB1
COMP1
19
PGND1/2
L2
7µH
2
8/9
PGOOD2 22
PGOOD1 28
VOUT1
C13
47µF
1
EN1
Css1
47nF
FB2
27
SYNCOUT
Css2
47nF
21
NC
VCC
FS
R8
34k
COMP2
R7
0
FB2
C4
68pF
R6
8.06k
4.7µF
FIGURE 3. SINGLE 6A OUTPUT (VIN RANGE FROM 4.5V TO 28V) CURRENT SHARING
FN6676 Rev 8.00
February 17, 2015
Page 5 of 26
ISL85033
BOOT2
COMP2
FB2
PGOOD2
Functional Block Diagram
VCC
5MΩ
BOOT UV
DETECTION
+
-
VCC
-10%
SOFT-START
CONTROL
VOLTAGE
MONITOR
VIN2
CSA2
+
-
SS2
EA
+
-
COMP2
0.8V
REFERENCE
FAULT
MONITOR
EN2
GATE
DRIVE
CSA2
VIN1
LDO
VCC = 5V
BOOT
REFRESH
CONTROL
SLOPE COMP
POWER-ON
RESET
MONITOR
PHASE2
PGND2
+
CSA2
VIN1
THERMAL
MONITOR
+150°C
SYNCOUT
CSA1
FS
OSCILLATOR
SYNCIN
CSA1
SLOPE COMP
+
VIN1
CSA1
EN1
FAULT
MONITOR
0.8V
REFERENCE
DRIVE
GATE
COMP1
EA
+
MONITOR
VOLTAGE
+
CONTROL
SOFT-START
VCC
5MΩ
-10%
PGND1
BOOT UV
DETECTION
FN6676 Rev 8.00
February 17, 2015
BOOT1
SGND
EPAD GND
COMP1
FB1
PGOOD1
VCC
VCC
BOOT
REFRESH
CONTROL
+
SS1
PHASE1
Page 6 of 26
ISL85033
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL85033IRTZ
850 33IRTZ
ISL85033-12VEVAL3Z
Evaluation Board
ISL85033DUALEVAL1Z
Evaluation Board
ISL85033EVAL2Z
Evaluation Board
ISL85033CRSHEVAL1Z
Evaluation Board
TEMP. RANGE
(°C)
-40 to +85
PACKAGE
(RoHS Compliant)
28 Ld TQFN
PKG.
DWG. #
L28.4x4
NOTES:
1. Add “-T*” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL85033. For more information on MSL please see techbrief TB363.
FN6676 Rev 8.00
February 17, 2015
Page 7 of 26
ISL85033
Absolute Maximum Ratings
Thermal Information
VIN1/2 to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +30V
PHASE1/2 to GND . . . . . . . . . . . . . . . . . . . -7V ( 90%
Floating
High
After VOUT2 > 90%
First
High
High
Same time
as VOUT2
Same time
as VOUT1
Floating Floating
R2
8.06k
NOTE
R1
25.5k
FIGURE 41. ABSOLUTE START-UP
Not
Allowed
C3
C1
22nF
C1
22nF
VOUT1
5.0V
C3
SS2
EN1
ISL85033
VOUT2
EN2
ISL85033
C2
47nF
SS2
C2
22nF
VOUT2
5.0V
VOUT1
SS1
SS1
3.3V
C4
TABLE 1. OUTPUT SEQUENCING
EN2
5.0V
C3
C1
47nF
Figure 42 illustrates output sequencing. When EN1 is high and
EN2 is floating, OUT1 comes up first and OUT2 will not start until
OUT1 > 90% of its regulation point. If EN1 is floating and EN2 is
high, OUT2 comes up first and OUT1 will not start until
OUT2 > 90% of its regulation point. If EN1 = EN2 = high, OUT1
and OUT2 come up at the same time. Please refer to Table 1 for
conditions related to Figure 42 (Output Sequencing).
EN1
VOUT1
SS1
3.3V
C4
3.3V
C4
FIGURE 42. OUTPUT SEQUENCING
Protection Features
FIGURE 39. INDEPENDENT START-UP
VOUT1
SS1
5.0V
C3
C1
22nF
SS2
ISL85033
VOUT2
3.3V
C4
C2
22nF
FIGURE 40. RATIOMETRIC START-UP
The ISL85033 limits the current in all on-chip power devices.
Overcurrent protection limits the current on the two buck
regulators and internal LDO for VCC.
Buck Regulator Overcurrent Protection
During PWM on-time, current through the internal switching
MOSFET is sampled and scaled through an internal pilot device.
The sampled current is compared to a nominal 5A overcurrent
limit. If the sampled current exceeds the overcurrent limit
reference level, an internal overcurrent fault counter is set to 1
and an internal flag is set. The internal power MOSFET is
immediately turned off and will not be turned on again until the
next switching cycle.
The protection circuitry continues to monitor the current and
turns off the internal MOSFET as described. If the overcurrent
condition persists for 17 sequential clock cycles, the overcurrent
fault counter overflows indicating an overcurrent fault condition
exists. The regulator is shutdown and power-good goes low.
The buck controller attempts to recover from the overcurrent
condition after waiting 8 soft-start cycles. The internal
overcurrent flag and counter are reset. A normal soft-start cycle
FN6676 Rev 8.00
February 17, 2015
Page 17 of 26
ISL85033
is attempted and normal operation continues if the fault
condition has cleared. If the overcurrent fault counter overflows
during soft-start, the converter shuts down and this hiccup mode
operation repeats.
Thermal Overload Protection
Thermal overload protection limits maximum junction
temperature in the ISL85033. When the junction temperature
(TJ) exceeds +150°C, a thermal sensor sends a signal to the fault
monitor.
The fault monitor commands the buck regulator to shutdown.
When the junction temperature has decreased by 20°C, the
regulator will attempt a normal soft-start sequence and return to
normal operation. For continuous operation, the +125°C
junction temperature rating should not be exceeded.
BOOT Undervoltage Protection
If the BOOT capacitor voltage falls below 2.5V, the BOOT
undervoltage protection circuit will pull the phase pin low through
a 1Ω switch for 400ns to recharge the capacitor. This operation
may arise during long periods of no switching as in no load
situations.
Application Guidelines
Operating Frequency
The ISL85033 operates at a default switching frequency of
500kHz if FS is tied to VCC. Tie a resistor from FS to GND to
program the switching frequency from 300kHz to 2MHz, as
shown in Equation 4. [Minimum on-time of 150ns (typical) in
conjunction with the input and output voltage should be
considered when selecting the maximum operating frequency].
(EQ. 4)
R FS k = 122k t – 0.17s
Where t is the switching period in µs.
RFS (kΩ)
300
200
Synchronization Control
The frequency of operation can be synchronized up to 2MHz by
an external signal applied to the SYNCIN pin. The falling edge on
the SYNCIN triggers the rising edge of PHASE1/2. The switching
frequency for each output is half of the SYNCIN frequency.
Output Inductor Selection
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% of
total load current. The inductor value can then be calculated
using Equation 5:
V IN – V OUT V OUT
L = -------------------------------- ---------------f SW I
V IN
(EQ. 5)
Increasing the value of inductance reduces the ripple current and
thus ripple voltage. However, the larger inductance value may
reduce the converter’s response time to a load transient. The
inductor current rating should be such that it will not saturate in
overcurrent conditions.
Buck Regulator Output Capacitor Selection
An output capacitor is required to filter the inductor current. The
Output ripple voltage and transient response are 2 critical factors
when considering output capacitance choice. The current mode
control loop allows the usage of low ESR ceramic capacitors and
thus smaller board layout. Electrolytic and polymer capacitors
may also be used.
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings and with no DC
bias. In the DC/DC converter application, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
manufacturers data sheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so that this effect can be easily accommodated. The effects of
AC voltage are not frequently published, but an assumption of
~20% further reduction will generally suffice. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
100
For the ceramic capacitors (low ESR):
0
500
750
1000
1250
1500
fSW (kHz)
FIGURE 43. RFS SELECTION vs fSW
1750
2000
I
V OUTripple = ------------------------------------8 f SW C OUT
(EQ. 6)
Where I is the inductor’s peak-to-peak ripple current, fSW is the
switching frequency and COUT is the output capacitor.
If using electrolytic capacitors then:
V OUTripple = I*ESR
FN6676 Rev 8.00
February 17, 2015
(EQ. 7)
Page 18 of 26
ISL85033
Regarding transient response needs, a good starting point is to
determine the allowable overshoot in VOUT if the load is suddenly
removed. In this case, energy stored in the inductor will be
transferred to COUT causing its voltage to rise. After calculating
capacitance required for both ripple and transient needs, choose
the larger of the calculated values. Equation 8 determines the
required output capacitor value in order to achieve a desired
overshoot relative to the regulated voltage.
I OUT 2 * L
C OUT = -------------------------------------------------------------------------------------------V OUT 2 * V OUTMAX V OUT 2 – 1
I RMS
------------ =
Io
D – D2
(EQ. 10)
Where D = VO/VIN
The input ripple current is graphically represented in Figure 45.
0.6
0.5
(EQ. 8)
Where VOUTMAX/VOUT is the relative maximum overshoot
allowed during the removal of the load. For an overshoot of 5%,
the equation becomes Equation 9:
I OUT 2 * L
C OUT = ----------------------------------------------------V OUT 2 * 1.05 2 – 1
IRMS/IO
0.4
0.3
0.2
(EQ. 9)
0.1
Figure 44 shows the relationship of COUT and % overshoot at three
different output voltages. L is assumed to be 7µH and IOUT is 3A.
0
0
0.2
0.4
0.6
DUTY CYCLE (D)
0.8
FIGURE 45. IRMS/IO vs DUTY CYCLE
A minimum of 10µF ceramic capacitance is required on each VIN
pin. The capacitors must be as close to the IC as physically
possible. Additional capacitance may be used.
COUT (µF)
80
60
Loop Compensation Design
3.3VOUT
40
20
The ISL85033 uses a constant frequency current mode control
architecture to achieve simplified loop compensation and fast
loop transient response.
5VOUT
12VOUT
0
1.02
1.04
1.06
1.08
1.10
VOUTMAX/VOUT
FIGURE 44. COUT vs OVERSHOOT VOUTMAX/VOUT
Current Sharing Configuration
In current sharing configuration, FB1 is connected to FB2, EN1 to
EN2, COMP1 to COMP2 and VOUT1 to VOUT2 as shown in Figure 3
on page 5. As a result, the equivalent gm doubles its single
channel value. Since the two channels are out-of-phase, the
frequency will be 2x the channel switching frequency. Ripple
current cancellation will reduce the ripple current seen by the
output capacitors and thus lower the ripple voltage. This results
in the ability to use less capacitance than would be required by a
single phase design of similar rating. Ripple current cancellation
also reduces the ripple current seen at the input capacitors.
Input Capacitor Selection
To reduce the resulting input voltage ripple and to minimize EMI
by forcing the very high frequency switching current into a tight
local loop, an input capacitor is required. The input capacitor
must have adequate ripple current rating, which can be
approximated by Equation 10. If capacitors other than MLCC are
used, attention must be paid to ripple and surge current ratings.
The compensator schematic is shown in Figure 47. As mentioned
in the COUT selection, ISL85033 allows the usage of low ESR
output capacitor. Choice of the loop bandwidth fc is somewhat
arbitrary but should not exceed 1/4 of the switching frequency.
As a starting point, the lower of 100kHz or 1/6 of the switching
frequency is reasonable. The following equations determine
initial component values for the compensation, allowing the
designer to make the selection with minimal effort. Further detail
is provided in “Theory of Compensation” on page 20 to allow fine
tuning of the compensator.
Compensation resistor R1 is given by Equation 11:
2f c V o C o R T
R 1 = ----------------------------------g m V FB
(EQ. 11)
Which, when applied to the ISL85033 becomes:
R 1 k = 0.008247 f c V o C o
(EQ. 12)
Where Co is the output capacitor value [µF], fc = loop bandwidth
[kHz] and Vo is the output voltage [V].
Compensation capacitors C1 [nF], C2 [pF] are given by
Equation 13:
3
6
C o V o 10
C o R c 10
C 1 = ----------------------------------------- ,C 2 = ----------------------------------------Io R1
R1
(EQ. 13)
Where Io [A] is the output load current, R1 (Ω) and RC (Ω) is the
ESR of the output capacitor Co.
FN6676 Rev 8.00
February 17, 2015
Page 19 of 26
ISL85033
Power Stage Transfer Functions
Example: Vo = 5V, Io = 3A, fSW = 500kHz, fc = 50kHz,
Co = 47µF/Rc = 5mΩ, then the compensation resistance
R1 = 96kΩ.
Transfer function F1(S) from control to output voltage is
calculated in Equation 17:
The compensation capacitors are:
C1 = 815pF, C2 = 2.5pF (There is approximately 3pF parasitic
capacitance from VCOMP to GND; therefore, C2 is optional).
Theory of Compensation
The sensed current signal is injected into the voltage loop to
achieve current mode control to simplify the loop compensation
design. The inductor is not considered as a state variable for
current mode control and the system becomes a single order
system. It is much easier to design a compensator to stabilize the
voltage loop than voltage mode control. Figure 46 shows the
small signal model of the synchronous buck regulator.
+
^i
IN
ILd^
^
VIN
1:D
^
iL
^
VO
L
C
1
1
o
Where esr = --------------- ,Q p R o ------- o = --------------Rc Co
L
LC o
Transfer function F2(S) from control to inductor current is given
by Equation 18:
S
1 + -----ˆI
V IN
z
o
F 2 S = ---= --------------------- --------------------------------------Ro + RL 2
dˆ
S
S
------- + --------------- + 1
2 Q
o p
o
(EQ. 18)
1
+
RT
Rc
Ro
Current loop gain Ti(S) is expressed as Equation 19:
Co
T i S = R T F m F 2 S H e S
Ti(S)
K
Fm
+
(EQ. 17)
Where z = -------------Ro Co
VINd^
d^
S
1 + ----------- esr
vˆ o
F 1 S = -----= V IN --------------------------------------2
dˆ
S
S
------- + --------------- + 1
2 Q
o p
o
(EQ. 19)
The voltage loop gain with open current loop is calculated in
Equation 20:
(EQ. 20)
T v S = KFm F 1 S A v S
The voltage loop gain with current loop closed is given by
Equation 21:
Tv(S)
He(S)
^
VCOMP
-Av(S)
FIGURE 46. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
PWM Comparator Gain Fm
The PWM comparator gain Fm for peak current mode control is
given by Equation 14:
1
dˆ
- = -------------------------------F m = ------------------ˆv
+
S
e S n T s
COMP
(EQ. 14)
Where Se is the slew rate of the slope compensation and Sn is
given by Equation 15.
V IN – V o
S n = R T ----------------------L
(EQ. 15)
Tv S
L v S = -----------------------1 + Ti S
(EQ. 21)
V FB
K = ----------- , V
FB is the feedback voltage of the voltage
Vo
Where
error amplifier. If Ti(S)>>1, then Equation 21 can be simplified as
shown in Equation 22:
S
1 + -----------V FB R o + R L
esr A v S
1
L v S = ----------- --------------------- ---------------------- ---------------- , p --------------Vo
S He S
RT
Ro Co
1 + ------p
(EQ. 22)
Equation 22 shows that the system is a single order system,
which has a single pole located at P before the half switching
frequency. Therefore, a simple type II compensator can be easily
used to stabilize the system.
Where RT is transresistance and is the product of the current
sensing resistance and gain of the current amplifier in current
loop.
CURRENT SAMPLING TRANSFER FUNCTION He(S)
In current loop, the current signal is sampled every switching
cycle. Equation 16 shows the transfer function:
2
S
S
H e S = ------- + --------------- + 1
2 Q
n
n
n
(EQ. 16)
2
Where Qn and n are given by Q n = – --- = n = f S .
FN6676 Rev 8.00
February 17, 2015
Page 20 of 26
ISL85033
Put the compensator zero at 6.6kHz (~1.5x CoRo), and put the
compensator pole at ESR zero, which is 1.45MHz. The
compensator capacitors are:
Vo
R2
C3
V FB
V REF
R3
GM
C1 = 470pF, C2 = 3pF (There is approximately 3pF parasitic
capacitance from VCOMP to GND; therefore, C2 is optional).
V COMP
Figure 48A shows the simulated voltage loop gain. It is shown
that it has 80kHz loop bandwidth with 69° phase margin and
15dB gain margin. Optional addition phase boost can be added
to the overall loop response by using C3.
+
R1
C2
C1
60
45
FIGURE 47. TYPE II COMPENSATOR
30
Figure 47 shows the type II compensator and its transfer function
is expressed as Equation 23:
15
S
S
1 + ------------ 1 + -------------
gm
cz1
cz2
vˆ COMP
- = --------------------- --------------------------------------------------------A v S = ------------------C1 + C2
S
vˆ FB
S 1 + ----------
GAIN (dB)
0
(EQ. 23)
cp
-15
-30
Where:
100
1•103
1•104
1•105
1•106
1•105
1•106
FIGURE 48A.
C1 + C2
1
1
cz1 = --------------- , cz2 = --------------- cp = ----------------------R1 C1 C2
R1 C1
R2 C3
(EQ. 24)
100
The compensator design goal is:
80
High DC gain
1 1- f
Loop bandwidth fc: --4- to ----10 SW
60
Gain margin: >10dB
40
Phase margin: 40°
20
The compensator design procedure is shown in Equation 25:
1
Put compensator zero cz1 = 1to3 --------------R C
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower.
The loop gain Tv(S) at crossover frequency of fc has unity gain.
Therefore, the compensator resistance R1 is determined by
Equation 26:
(EQ. 26)
Where gm is the transconductance of the voltage error amplifier,
typically 200µA/V. Compensator capacitor C1 is then given by
Equation 27:
1
1
C 1 = ----------------- ,C 2 = ------------------------R 1 cz
2R 1 f esr
(EQ. 27)
Example: VIN = 12V, Vo = 5V, Io = 3A, fSW = 500kHz,
Co = 22µF (derated value over voltage, temperature)/5mΩ,
L = 5.6µH, gm = 200µs, RT = 0.21, VFB = 0.8V, Se = 1.1105V/s,
Sn = 3.4105V/s, fc = 80kHz, then compensator resistance
R1 = 72kΩ.
FN6676 Rev 8.00
February 17, 2015
0
(EQ. 25)
o 0
2f c V o C o R T
R 1 = ----------------------------------g m V FB
PHASE (°)
-20
100
1•103
1•104
FIGURE 48B.
Rectifier Selection
Current circulates from ground to the junction of the external
Schottky diode and the inductor when the high-side switch is off.
As a consequence, the polarity of the switching node is negative
with respect to ground. This voltage is approximately -0.5V (a
Schottky diode drop) during the off-time. The rectifier's rated
reverse breakdown voltage must be at least equal to the
maximum input voltage, preferably with a 20% derating factor.
The power dissipation when the Schottky diode conducts is
expressed in Equation 28:
V OUT
P D W = I OUT V D 1 – ----------------
V IN
(EQ. 28)
Where:
The VD is the voltage drop of the Schottky diode. Selection of the
Schottky diode is critical in terms of the high temperature
reverse bias leakage current, which is very dependent on VIN and
exponentially increasing with temperature. Due to the nature of
Page 21 of 26
ISL85033
reverse bias leakage vs temperature, the diode should be
carefully selected to operate in the worst case circuit conditions.
Catastrophic failure is possible if the diode chosen experiences
thermal runaway at elevated temperatures. Refer to Application
Notes for AN1574, AN1605, AN1584 diode selection listed on
page 1.
Power Derating Characteristics
To prevent the ISL85033 from exceeding the maximum junction
temperature, some thermal analysis is required. The
temperature rise is given by Equation 29:
(EQ. 29)
T RISE = PD JA
Where PD is the power dissipated by the regulator and θJA is the
thermal resistance from the junction of the die to the ambient
temperature. The junction temperature, TJ, is given by
Equation 30:
(EQ. 30)
T J = T A + T RISE
Where TA is the ambient temperature. For the QFN package, the
θJA is +38°C/W.
The actual junction temperature should not exceed the absolute
maximum junction temperature of +125°C When considering
the thermal design, (consider the thermal needs of the rectifier
diode).
MAXIMUM AMBIENT
TEMPERATURE (°C)
The ISL85033 delivers full current at ambient temperatures up
to +85°C if the thermal impedance from the thermal pad
maintains the junction temperature below the thermal shutdown
level, depending on the Input Voltage/Output Voltage
combination and the switching frequency. The device power
dissipation must be reduced to maintain the junction
temperature at or below the thermal shutdown level. Figure 49
illustrates the power derating versus ambient temperature for
the ISL85033 evaluation kit. Note that the evaluation kit derating
curve is based on total circuit dissipation, not IC dissipation
alone.
120
110
100
90
80
70
60
50
40
30
20
10
0
0
2
3
4
5
6
7
8
9 10 11
ISL85033EVAL1ZB EVALUATION BOARD
TOTAL POWER DISSIPATION (W)
FIGURE 49. POWER DERATING CURVE
FN6676 Rev 8.00
February 17, 2015
Layout is very important in high frequency switching converter
designs. With power devices switching efficiently between
100kHz and 600kHz, the resulting current transitions from one
device to another cause voltage spikes across the
interconnecting impedances and parasitic circuit elements.
These voltage spikes can degrade efficiency, radiate noise into
the circuit, and lead to device overvoltage stress. Careful
component layout and printed circuit board design minimizes
these voltage spikes.
As an example, consider the turn-off transition of the upper
MOSFET. Prior to turn-off, the MOSFET is carrying the full load
current. During turn-off, current stops flowing in the MOSFET and
is picked up by the Schottky diode. Any parasitic inductance in
the switched current path generates a large voltage spike during
the switching interval. Careful component selection, tight layout
of the critical components and short, wide traces minimizes the
magnitude of voltage spikes.
There are two sets of critical components in the ISL85033
switching converter. The switching components are the most
critical because they switch large amounts of energy and
therefore tend to generate large amounts of noise. Next are the
small signal components which connect to sensitive nodes or
supply critical bypass current and signal coupling.
A multilayer printed circuit board is recommended. Figure 50
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, (usually a middle layer of the PC board) for a ground plane
and make all critical component ground connections with vias to
this layer. Dedicate another solid layer as a power plane and
break this plane into smaller islands of common voltage levels.
Keep the metal runs from the PHASE terminals to the output
inductor short. The power plane should support the input power
and output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the phase nodes. Use the remaining
printed circuit layers for small signal wiring.
In order to dissipate heat generated by the internal LDO and
MOSFET, the ground pad should be connected to the internal
ground plane through at least four vias. This allows the heat to
move away from the IC and also ties the pad to the ground plane
through a low impedance path.
JA = +38°C/W
1
Layout Considerations
12
The switching components should be placed close to the
ISL85033 first. Minimize the length of the connections between
the input capacitors, CIN, and the power switches by placing
them nearby. Position both the ceramic and bulk input capacitors
as close to the upper MOSFET drain as possible. Position the
output inductor and output capacitors between the upper and
Schottky diode and the load.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB pin with
vias tied straight to the ground plane as required.
Page 22 of 26
D1
Cout1
ISL85033
SL85033
.. .. ..
vias
Cin1 Cin2
LX2 trace
L2
D2
Cout2
VOUT2
VOUT2
VIN1
VIN2
VOUT1
Cboot
LX1 trace
Fb2
Cboot
Comp1
Fb1
L1
Comp2
ISL85033
FIGURE 50. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
FN6676 Rev 8.00
February 17, 2015
Page 23 of 26
ISL85033
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
February 17, 2015
April 17, 2014
REVISION
CHANGE
FN6676.8 Page 21, paragraph below Equation 27, changed “Co = 220µF/5mΩ...” to "Co = 22µF (derated value over voltage,
temperature)/5mΩ...
FN6676.7
On page 16 in the "Output Tracking and Sequencing" changed the sentence "Maximum CSS value is 50nF" to "The
maximum CSS value is recommended not to exceed 100nF".
Figure 39 on page 17, changed C1 from 0.1µF to 22nF and C2 from 0.2µF to 47nF.
Figure 40 on page 17, changed the value of both C1 and C2 to 22nF each.
Figure 41 on page 17, changed C1 value to 47nF.
Figure 42 on page 17, changed C1 and C2 value to 22nF each.
On page 18 in the Operating Frequency chapter, after the sentence "Tie a resistor from FS to GND to program the
switching frequency from 300kHz to 2MHz, as shown in Equation 4." Added : "Minimum on-time of 150ns (typical)
in conjunction with input and output voltage should be considered when selecting the maximum operating
frequency".
November 2, 2011
FN6676.6 In the “Pin Descriptions” on page 3, added the following to end of EN1, EN2 description:
"If EN1, EN2 pins are driven by an external signal, the minimum off-time for EN1, EN2 should be:
EN_T_off s = 10s C SS 2.2nF
where CSS is the soft-start pin capacitor (nF). ISL85033 does not have debouncing to EN1, EN2 external signals."
In “Enable and Disable” on page 16, adding the following:
"If EN1, EN2 pins are driven by an external signal, the minimum off-time for EN1, EN2 should be:
EN_T_off s = 10s C SS 2.2nF
where CSS is the soft-start pin capacitor (nF). ISL85033 does not have debouncing to EN1, EN2 external signals."
Adding the following after Equation 3 on page 16:
"Maximum Css value is 50nF".
In the “Pin Descriptions” on page 3, added the following to the end of SS1, SS2 description:
"Maximum Css value is 50nF".
October 7, 2011
FN6676.5 In “Absolute Maximum Ratings” on page 8, changed:
PHASE1/2 to GND . . . . .-0.3V to +33V
to:
PHASE1/2 to GND . . . . .-7V (
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