ISL89163FBECZ

Datasheet ISL89163, ISL89164, ISL89165 High Speed, Dual Channel, 6A, Power MOSFET Driver with Enable Inputs The ISL89163, ISL89164, and ISL89165 are high-speed, 6A, dual channel MOSFET drivers with enable inputs. Precision thresholds on all logic inputs allow the use of external RC circuits to generate accurate and stable time delays on both the main channel inputs, INA and INB, and the enable inputs, ENA and ENB. The precision delays capable of these precise logic thresholds make these parts valuable for dead time control and synchronous rectifiers. Note, the enable and input logic inputs can be interchanged for alternate logic implementations. Three input logic thresholds are available: • 3.3V (CMOS) Features • Dual output, 6A peak currents, can be paralleled • Dual AND-ed input logic, (input and enable) • Typical ON-resistance UVLO, and after a short delay, the outputs begin to respond to the logic inputs. • Synchronous Rectifier (SR) driver • Switch mode power supplies • Motor drives, Class D amplifiers, UPS, inverters • Pulse transformer driver • Clock/line driver Related Literature For a full list of related documents, visit our website: • ISL89163, ISL89164, ISL89165 device pages V DD ENB ENA INA GND INB 1 8 2 7 3 4 EPAD OUTA 6 5 OUTB 4.7µF Option B Thresholds (5.0V) 3.0 Positive Threshold Limits 2.5 2.0 1.5 1.0 0.5 0.0 -40 -25 -10 Figure 1. Typical Application FN7707 Rev.6.00 Jul.9.19 Negative Threshold Limits 5 20 35 50 65 80 Temperature (°C) 95 110 125 Figure 2. Temperature Stable Logic Thresholds Page 1 of 22 ISL89163, ISL89164, ISL89165 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 1.2 1.3 1.4 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 5 5 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 2.2 2.3 2.4 2.5 2.6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Waveforms and Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 7 8 9 3. Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 5.2 5.3 5.4 Precision Thresholds for Time Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Paralleling Outputs to Double the Peak Drive Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation of the Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 15 6. General PCB Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. General EPAD Heatsinking Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9. Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 FN7707 Rev.6.00 Jul.9.19 Page 2 of 22 ISL89163, ISL89164, ISL89165 1. 1. Overview Overview 1.1 Block Diagram VDD For options A and B, the UV comparator holds off the outputs For clarity, only one channel is shown until VDD ~> 3.3VDC. For option C, the UV release is ~> 6.5V Separate FET drives, with non-overlapping outputs, prevent shoot-thru currents in the output CMOS FETs resulting with very low high frequency operating currents. ENx ISL89163 ENx and INx inputs are identical and may be interchanged for alternate logic OUTx INx 10k ISL89164, ISL89165 GND EPAD For proper thermal and electrical performance, the EPAD must be connected to the PCB ground plane. Figure 3. Block Diagram 1.2 Ordering Information Part Number (Notes 2, 3, 4) Part Marking Temp Range (°C) ISL89163FRTAZ 163A -40 to +125 ISL89163FRTAZ-T 163A ISL89163FRTBZ Input Input Tape and Reel Configuration Logic (V) (Units) (Note 1) Non-inverting Package (RoHS Compliant) Pkg. Dwg. # 3.3 - 8 Ld 3x3 TDFN L8.3x3I -40 to +125 3.3 6k 8 Ld 3x3 TDFN L8.3x3I 163B -40 to +125 5.0 - 8 Ld 3x3 TDFN L8.3x3I ISL89163FRTBZ-T 163B -40 to +125 ISL89164FRTAZ 164A -40 to +125 ISL89164FRTAZ-T 164A ISL89164FRTBZ 164B 5.0 6k 8 Ld 3x3 TDFN L8.3x3I 3.3 - 8 Ld 3x3 TDFN L8.3x3I -40 to +125 3.3 6k 8 Ld 3x3 TDFN L8.3x3I -40 to +125 5.0 - 8 Ld 3x3 TDFN L8.3x3I 5.0 6k 8 Ld 3x3 TDFN L8.3x3I 3.3 - 8 Ld 3x3 TDFN L8.3x3I 3.3 6k 8 Ld 3x3 TDFN L8.3x3I 5.0 - 8 Ld 3x3 TDFN L8.3x3I ISL89164FRTBZ-T 164B -40 to +125 ISL89165FRTAZ 165A -40 to +125 ISL89165FRTAZ-T 165A -40 to +125 ISL89165FRTBZ 165B -40 to +125 ISL89165FRTBZ-T 165B -40 to +125 ISL89163FBEAZ 89163 FBEAZ -40 to +125 ISL89163FBEAZ-T 89163 FBEAZ ISL89163FBEBZ 89163 FBEBZ Inverting Inverting + Non-inverting 5.0 6k 8 Ld 3x3 TDFN L8.3x3I 3.3 - 8 Ld EPSOIC M8.15D -40 to +125 3.3 2.5k 8 Ld EPSOIC M8.15D -40 to +125 5.0 - 8 Ld EPSOIC M8.15D 5.0 2.5k 8 Ld EPSOIC M8.15D 3.3 - 8 Ld EPSOIC M8.15D Non-inverting ISL89163FBEBZ-T 89163 FBEBZ -40 to +125 ISL89164FBEAZ 89164 FBEAZ -40 to +125 ISL89164FBEAZ-T 89164 FBEAZ -40 to +125 3.3 2.5k 8 Ld EPSOIC M8.15D ISL89164FBEBZ 89164 FBEBZ -40 to +125 5.0 - 8 Ld EPSOIC M8.15D ISL89164FBEBZ-T 89164 FBEBZ -40 to +125 5.0 2.5k 8 Ld EPSOIC M8.15D FN7707 Rev.6.00 Jul.9.19 Inverting Page 3 of 22 ISL89163, ISL89164, ISL89165 Part Number (Notes 2, 3, 4) 1. Overview Part Marking Temp Range (°C) ISL89165FBEAZ 89165 FBEAZ -40 to +125 ISL89165FBEAZ -T 89165 FBEAZ -40 to +125 ISL89165FBEBZ 89165 FBEBZ -40 to +125 ISL89165FBEBZ-T 89165 FBEBZ -40 to +125 Input Input Tape and Reel Configuration Logic (V) (Units) (Note 1) Inverting + Non-inverting Package (RoHS Compliant) Pkg. Dwg. # 3.3V - 8 Ld EPSOIC M8.15D 3.3V 2.5k 8 Ld EPSOIC M8.15D 5.0V - 8 Ld EPSOIC M8.15D 5.0V 2.5k 8 Ld EPSOIC M8.15D Notes: 1. See TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 3. Input Logic Voltage: A = 3.3V, B = 5.0V. 4. For Moisture Sensitivity Level (MSL), see the ISL89163, ISL89164, ISL89165 device pages. For more information about MSL, see TB363. Table 1. Key Differences Between Family of Parts I/O Pins Part Number ENA ENB INA INB OUTA OUTB ISL89163 NINV NINV NINV NINV NINV NINV ISL89164 NINV NINV INV INV NINV NINV ISL89165 NINV NINV INV NINV NINV NINV Note: INV: Inverting Input, NINV: Non-inverting input. FN7707 Rev.6.00 Jul.9.19 Page 4 of 22 ISL89163, ISL89164, ISL89165 1.3 1. Overview Pin Configurations ISL89163FR, ISL89163FB (8 Ld TDFN, EPSOIC) Top View ENA 1 8 ENB INA 2 GND 3 INB 4 ISL89164FR, ISL89164FB (8 Ld TDFN, EPSOIC) Top View ENA 1 8 ENB 7 OUTA /INA 2 7 OUTA 6 VDD GND 3 6 VDD 5 OUTB /INB 4 5 OUTB ISL89165FR, ISL89165FB (8 Ld TDFN, EPSOIC) Top View ENA 1 8 ENB /INA 2 7 OUTA GND 3 6 VDD INB 4 1.4 5 OUTB Pin Descriptions Description (See Table 2) Pin Number Symbol 1 ENA 2 INA, /INA Channel A enable, 0V to VDD Channel A input, 0V to VDD 3 GND 4 INB, /INB 5 OUTB 6 VDD 7 OUTA Channel A output, 0V to VDD 8 ENB Channel B enable, 0V to VDD EPAD Power Ground, 0V Table 2. Power Ground, 0V Channel B enable, 0V to VDD Channel B output Power input, 4.5V to 16V Truth Table for Logic Polarities ENx OUTx INx ENx OUTx /INx Non-Inverting Inverting UV ENx* INx* OUTx* UV ENx* /INx* OUTx* 0 x x 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 *Substitute A or B for x FN7707 Rev.6.00 Jul.9.19 Page 5 of 22 ISL89163, ISL89164, ISL89165 2. 2.1 2. Specifications Specifications Absolute Maximum Ratings Parameter Minimum Maximum Unit -0.3 18 V Logic Inputs (INA, INB, ENA, ENB) GND - 0.3 VDD + 0.3 V Outputs (OUTA, OUTB) GND - 0.3 VDD + 0.3 V Supply Voltage, VDD Relative to GND 150 Average Output Current (Note 5) ESD Rating Human Body Model Class 2 (Tested per JESD22-A114E) Machine Model Class B (Tested per JESD22-A115-A) Charged Device Model Class IV Latch-Up (Tested per JESD-78B; Class 2, Level A) Output Current mA Value Unit 2 kV 200 V 1 kV 500 mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. Note: 5. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output currents of this driver are self limiting by trans conductance or rDS(ON) and do not required any external components to minimize the peaks. If the output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external means to less than the specified absolute maximum. 2.2 Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 8 Ld TDFN Package (Notes 6, 7) 44 3 8 Ld EPSOIC Package (Notes 6, 7) 42 3 Notes: 6. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379. 7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Parameter Minimum Maximum Unit Max Power Dissipation at +25°C in Free Air 2.27 W Max Power Dissipation at +25°C with Copper Plane 33.3 W Storage Temperature Range -65 +150 °C Maximum Operating Junction Temperature Range -40 +150 °C Pb-Free Reflow Profile FN7707 Rev.6.00 Jul.9.19 see TB493 Page 6 of 22 ISL89163, ISL89164, ISL89165 2.3 2. Specifications Recommended Operating Conditions Parameter Minimum Maximum Unit -40 +125 °C 4.5 16 V Logic Inputs (INA, INB, ENA, ENB) 0 VDD V Outputs (OUTA, OUTB) 0 VDD V 7.5 16 V Logic Inputs (INA, INB, ENA, ENB) 0 VDD V Outputs (OUTA, OUTB) 0 VDD V Junction Temperature Options A and B Supply Voltage, VDD Relative to GND Option C Supply Voltage, VDD Relative to GND 2.4 Electrical Specifications 2.4.1 DC Electrical Specifications VDD = 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply across the operating junction temperature range, -40°C to +125°C. TJ = +25°C Parameters Symbol Test Conditions Min Typ TJ = -40°C to +125°C Min Max (Note 8) Max (Note 8) Unit Power Supply Voltage Range (Option A and B) VDD 4.5 16 V Voltage Range (Option C) VDD 7.5 16 V VDD Quiescent Current IDD ENx = INx = GND 5 mA INA = INB = 1MHz, square wave 25 mA Undervoltage VDD Undervoltage Lockout (Options A and B) (Note 12, Figure 10) VUV ENA = ENB = True INA = INB = True 3.3 V VDD Undervoltage Lockout (Option C) (Note 12, Figure 10) VUV ENA = ENB = True INA = INB = True (Note 9) 6.5 V ~25 mV ~0.95 V Hysteresis (Option A or B) Hysteresis (Option C) Inputs Input Range for INA, INB, ENA, ENB VIN Option A, B, or C Logic 0 Threshold for INA, INB, ENA, ENB (Note 11) VIL Option A, nominally 37% x 3.3V Logic 1 Threshold for INA, INB, ENA, ENB (Note 11) VIH Input Capacitance of INA, INB, ENA, ENB (Note 10) CIN Input Bias Current for INA, INB, ENA, ENB IIN GND VDD V 1.22 1.12 1.32 V Option B, nominally 37% x 5.0V 1.85 1.70 2.00 V Option C, nominally 20% x 12V (Note 9) 2.4 2.00 2.76 V Option A, nominally 63% x 3.3V 2.08 1.98 2.18 V Option B, nominally 63% x 5.0V 3.15 3.00 3.30 V Option C, nominally 80% x 12V (Note 9) 9.6 9.24 9.96 V 2 GND < VIN < VDD pF -10 +10 µA VDD - 0.1 VDD V Outputs High Level Output Voltage FN7707 Rev.6.00 Jul.9.19 VOHA VOHB Page 7 of 22 ISL89163, ISL89164, ISL89165 2. Specifications VDD = 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply across the operating junction temperature range, -40°C to +125°C. (Continued) TJ = +25°C Parameters Symbol Low Level Output Voltage Test Conditions Min Typ TJ = -40°C to +125°C Min Max (Note 8) VOLA VOLB GND Max (Note 8) Unit GND + 0.1 V Peak Output Source Current IO VO (initial) = 0V, CLOAD = 10nF -6 A Peak Output Sink Current IO VO (initial) = 12V, CLOAD = 10nF +6 A Notes: 8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 9. The nominal 20% and 80% thresholds for option C are valid for any value within the specified range of VDD. 10. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input is dominated by the PCB parasitic capacitance. 11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input voltage for the inverted inputs is less than the Logic 0 threshold voltage. 12. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 10 on page 10. 2.5 AC Electrical Specifications VDD = 12V, GND = 0V, No Load on OUTA or OUTB, unless otherwise specified. Boldface limits apply across the operating junction temperature range, -40°C to +125°C. TJ = +25°C Parameters Symbol Test Conditions Min Typ Max TJ = -40°C to +125°C Min Max Unit Output Rise Time (see Figure 5) tR CLOAD = 10nF, 10% to 90% 20 40 ns Output Fall Time (see Figure 5) tF CLOAD = 10nF, 90% to 10% 20 40 ns Output Rising Edge Propagation Delay for Non-Inverting Inputs (Note 13) (see Figure 4) tRDLYn VDD = 12V Options A and B 25 50 ns VDD = 8V Option C 25 50 ns Output Rising Edge Propagation Delay with Inverting Inputs (Note 13) (see Figure 4) tRDLYi Output Falling Edge Propagation Delay with Non-Inverting Inputs (Note 13) (see Figure 4) tFDLYn Output Falling Edge Propagation Delay with Inverting Inputs (Note 13) (see Figure 4) tFDLYi Rising Propagation Matching (see Figure 4) VDD = 12V Options A and B 25 50 ns VDD = 8V Option C 25 50 ns VDD = 12V Options A and B 25 50 ns VDD = 8V Option C 25 50 ns VDD = 12V Options A and B 25 50 ns VDD = 8V Option C 25 50 ns tRM No load