DATASHEET
ISL89410, ISL89411, ISL89412
FN6798
Rev 2.00
October 16, 2015
High Speed, Dual Channel Power MOSFET Drivers
The ISL89410, ISL89411, ISL89412 ICs are similar to the
EL7202, EL7212, EL7222 series but with greater VDD
ratings. These are very high speed matched dual drivers
capable of delivering peak currents of 2.0A into highly
capacitive loads. The high speed performance is achieved
by means of a proprietary “Turbo-Driver” circuit that speeds
up input stages by tapping the wider voltage swing at the
output. Improved speed and drive capability are enhanced
by matched rise and fall delay times. These matched delays
maintain the integrity of input-to-output pulse-widths to
reduce timing errors and clock skew problems. This
improved performance is accompanied by a 10-fold
reduction in supply currents over bipolar drivers, yet without
the delay time problems commonly associated with CMOS
devices. Dynamic switching losses are minimized with
non-overlapped drive techniques.
Pinouts
ISL89410
(8 LD PDIP, SOIC)
TOP VIEW
ISL89411
(8 LD PDIP, SOIC)
TOP VIEW
Features
• Industry Standard Driver Replacement
• Improved Response Times
• Matched Rise and Fall Times
• Reduced Clock Skew
• Low Output Impedance
• Low Input Capacitance
• High Noise Immunity
• Improved Clocking Rate
• Low Supply Current
• Wide Operating Voltage Range
• Pb-Free Available (RoHS compliant)
Applications
• Clock/line Drivers
• CCD Drivers
NC
1
8
NC
NC
1
8
NC
INA
2
7
OUTA
INA
2
7
OUTA
GND
3
6
V+
GND
3
6
V+
• Power MOSFET Drivers
INB
4
5
OUTB
INB
4
5
OUTB
• Switch Mode Power Supplies
INVERTING
DRIVERS
NON-INVERTING
DRIVERS
• Ultra-Sound Transducer Drivers
• Class D Switching Amplifiers
• Ultrasonic and RF Generators
• Pulsed Circuits
Pin Descriptions
ISL89412
(8 LD PDIP, SOIC)
TOP VIEW
SYMBOL
V+
NC
1
8
NC
GND
INA
2
7
OUTA
GND
3
6
v+
INB
4
5
OUTB
INA, INB
COMPLEMENTARY
DRIVERS
PIN DESCRIPTIONS
Power voltage from 4.5V to 18V.
Power voltage return
Logic inputs.
OUTA
OUTA
Non-inverted ouput for ISL89410. Inverted output
for ISL89411 and ISL89412.
OUTB
OUTB
Non-inverted output for ISL89410 and ISL89412.
Inverted output for ISL89411.
NC
These pins must be left unconnected.
Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047
Ordering Information
PART
NUMBER
ISL89410IPZ (Note)
(No longer available, recommended
replacement: ISL89410IBZ)
FN6798 Rev 2.00
October 16, 2015
PART
MARKING
89410 IPZ
TEMP. RANGE
(°C)
-40 to +85
PACKAGE
8 Ld PDIP** (Pb-free)
PKG.
DWG. #
E8.3
Page 1 of 10
ISL89410, ISL89411, ISL89412
Ordering Information
PART
NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
PKG.
DWG. #
ISL89410IBZ (Note)
89410 IBZ
-40 to +85
8 Ld SOIC (Pb-free)
M8.15E
ISL89410IBZ-T13* (Note)
89410 IBZ
-40 to +85
8 Ld SOIC (Tape and Reel)
(Pb-free)
M8.15E
ISL89411IPZ (Note)
ISL 89411IPZ
-40 to +85
8 Ld PDIP** (Pb-free)
E8.3
ISL89411IBZ (Note)
89411 IBZ
-40 to +85
8 Ld SOIC (Pb-free)
M8.15E
ISL89411IBZ-T13* (Note)
89411 IBZ
-40 to +85
8 Ld SOIC (Tape and Reel)
(Pb-free)
M8.15E
ISL89412IPZ (No longer available,
recommended replacement: ISL89412IBZ)
89412 IPZ
-40 to +85
8 Ld PDIP** (Pb-free)
E8.3
ISL89412IBZ (Note)
89412 IBZ
-40 to +85
8 Ld SOIC (Pb-free)
M8.15E
ISL89412IBZ-T13* (Note)
89412 IBZ
-40 to +85
8 Ld SOIC (Tape and Reel)
(Pb-free)
M8.15E
*Please refer to TB347 for details on reel specifications.
**Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN6798 Rev 2.00
October 16, 2015
Page 2 of 10
ISL89410, ISL89411, ISL89412
Absolute Maximum Ratings
Thermal Information
Supply (V+ to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.0V
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+
Combined Peak Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . .4A
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Power Dissipation
8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW
8 Ld PDIP* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through-hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Maximum Recommended Operating Conditions
Recommended Operating V+ Range. . . . . . . . . . . . . . 4.5V to 18.0V
Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
TA = +25°C, V = 18V unless otherwise specified; Parameters with MIN and/or MAX limits are 100% tested
at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested.
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT
VIH
Logic “1” Input Voltage
IIH
Logic “1” Input Current
VIL
Logic “0” Input Voltage
IIL
Logic “0” Input Current
VHVS
Input Hysteresis
2.4
@V+
V
0.1
@0V
0.1
10
µA
0.8
V
10
µA
0.3
V
OUTPUT
ROH
Pull-Up Resistance
IOUT = -100mA
3
6
ROL
Pull-Down Resistance
IOUT = +100mA
4
6
IPK
Peak Output Current
Source
2
IDC
Continuous Output Current
Source/Sink
Power Supply Current
Inputs High/ISL89410
4.5
7.5
mA
Inputs High/ISL89411
1
2.5
mA
2.5
5.0
mA
18
V
MAX
UNITS
Sink
A
2
A
100
mA
POWER SUPPLY
IS
Inputs High/ISL89412
VS
Operating Voltage
AC Electrical Specifications
PARAMETER
4.5
TA = +25°C, V = 18V unless otherwise specified.
DESCRIPTION
TEST CONDITIONS
MIN
TYP
SWITCHING CHARACTERISTICS
tR
Rise Time (Note 1)
tF
Fall Time (Note 1)
CL = 500pF
7.5
CL = 1000pF
10
CL = 500pF
10
CL = 1000pF
13
ns
20
ns
ns
20
ns
tD1
Turn-On Delay Time (Note 1)
See “Timing Table” on page 4
18
25
ns
tD2
Turn-Off Delay Time (Note 1)
See“Timing Table” on page 4
20
25
ns
NOTE:
1. Limits established by characterization and are not production tested.
FN6798 Rev 2.00
October 16, 2015
Page 3 of 10
ISL89410, ISL89411, ISL89412
Timing Table
5V
INPUT 2.5V
0
INVERTED
OUTPUT
90%
10%
90%
NON-INVERTED
OUTPUT
10%
tD1
tD2
tF
tR
tF
tR
Standard Test Configuration
V+
4
6
4.7µF
TAN+
7
2
INPUT
OUTPUT
1000pF
3
Simplified Schematic
V+
+
-
INPUT
+
OUTPUT
VREF
INPUT
BUFFER
FN6798 Rev 2.00
October 16, 2015
REFERENCE
AND LEVEL
SHIFTER
INVERTING
BUFFER
WITH
HYSTERESIS
2ND
INVERTING
BUFFER
SUPER
INVERTER
Page 4 of 10
ISL89410, ISL89411, ISL89412
Typical Performance Curves
FIGURE 1. MAX POWER/DERATING CURVES
FIGURE 3. INPUT CURRENT vs VOLTAGE
FIGURE 2. SWITCH THRESHOLD vs SUPPLY VOLTAGE
FIGURE 4. PEAK DRIVE vs SUPPLY VOLTAGE
ISL89410
ISL89411
ISL89412
FIGURE 5. QUIESCENT SUPPLY CURRENT
FN6798 Rev 2.00
October 16, 2015
Page 5 of 10
ISL89410, ISL89411, ISL89412
Typical Performance Curves
(Continued)
FIGURE 6. “ON” RESISTANCE vs SUPPLY VOLTAGE
FIGURE 7. AVERAGE SUPPLY CURRENT vs VOLTAGE AND
FREQUENCY
FIGURE 8. AVERAGE SUPPLY CURRENT vs CAPACITIVE
LOAD
FIGURE 9. RISE/FALL TIME vs LOAD
FIGURE 10. RISE/FALL TIME vs SUPPLY VOLTAGE
FIGURE 11. PROPAGATION DELAY vs SUPPLY VOLTAGE
FN6798 Rev 2.00
October 16, 2015
Page 6 of 10
ISL89410, ISL89411, ISL89412
Typical Performance Curves
(Continued)
FIGURE 12. RISE/FALL TIME vs TEMPERATURE
FIGURE 13. DELAY vs TEMPERATURE
ISL89411 Macro Model
**** ISL89411 Model ****
*
input
*
|
gnd
*
|
|
Vsupply
*
|
|
| Vout
.subckt M89411 2 3 6 7
V1 12 3 1.6
R1 13 15 1k
R2 14 15 5k
R5 11 12 100
C1 15 3 43.3 pF
D1 14 13 dmod
X1 13 11 2 3 comp1
X2 16 12 15 3 comp1
sp 6 7 16 3 spmod
sn 7 3 16 3 snmod
g1 11 0 13 0 938µ
.model dmod d
.model spmod vswitch ron3 roff2meg von1 voff1.5
.model snmod vswitch ron4 roff2meg von3 voff2
.ends M89411
FN6798 Rev 2.00
October 16, 2015
Page 7 of 10
ISL89410, ISL89411, ISL89412
.subckt comp1 out inp inm vss
e1 out vss table { (v(inp) v(inm))* 5000} (0,0) (3.2,3.2)
Rout out vss 10meg
Rinp inp vss 10meg
Rinm inm vss 10meg
.ends comp1
V+
PARASITIC LEAD
INDUCTANCE
Cq
Application Guidelines
It is important to minimize inductance to the power FET by
keeping the output drive current loop as short as possible.
Also, the decoupling capacitor, Cq, should be a high quality
ceramic capacitor with a Q that should be a least 10x the gate
Q of the power FET. A ground plane under this circuit is also
recommended.
V+
Cq SHOULD BE AS CLOSE AS
POSSIBLE TO THE V+ AND
GND PINS
Cq
GND
FIGURE 15. SUGGESTED CONFIGURATION FOR DRIVING
INDUCTIVE LOADS
Where high supply voltage operation is required (15V to 18V),
input signals with a minimum of 3.3V input drive is suggested
and a minimum rise/fall time of 100ns. This is recommended to
minimize the internal bias current power dissipation.
Excessive power dissipation in the driver can result when
driving highly capacitive FET gates at high frequencies. These
gate power losses are defined by Equation 1:
LOOP AS
SHORT AS
POSSIBLE
GND
FIGURE 14. RECOMMENDED LAYOUT METHODS
In applications where it is difficult to place the driver very close
to the power FET (which may result with excessive parasitic
inductance), it then may be necessary to add an external gate
resistor to dampen the inductive ring. If this resistor must be
too large in value to be effective, then as an alternative,
Schottky diodes can be added to clamp the ring voltage to V+
or GND.
P = 2 Q C V gs f SW
(EQ. 1)
where:
P = Power
Qc = Charge of the Power FET at Vgs
Vgs = Gate drive voltage (V+)
fSW = switching Frequency
Adding a gate resistor to the output of the driver will transfer
some of the driver dissipation to the resistor. Another possible
solution is to lower the gate driver voltage which also lowers
Qc.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
October 16, 2015
FN6798.2
CHANGE
Updated Ordering Information Table on page 1.
Added Revision History and About Intersil sections.
Updated POD MDP0027 to M8.15E.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
FN6798 Rev 2.00
October 16, 2015
Page 8 of 10
ISL89410, ISL89411, ISL89412
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(1.27)
(0.60)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
FN6798 Rev 2.00
October 16, 2015
Page 9 of 10
ISL89410, ISL89411, ISL89412
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AD
E
BASE
PLANE
-C-
SEATING
PLANE
A2
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
5
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eA
0.300 BSC
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
eB
-
L
0.115
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
0.355
10.16
N
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
8
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
8
6
10.92
7
3.81
4
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
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For additional products, see www.intersil.com/en/products.html
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN6798 Rev 2.00
October 16, 2015
Page 10 of 10