ISL9003AIEMZ-T

DATASHEET ISL9003A FN6299 Rev 5.00 July 18, 2014 Low Noise LDO with Low IQ and High PSRR ISL9003A is a high performance single low noise, high PSRR LDO that delivers a continuous 150mA of load current. It has a low standby current and is stable with 1µF of MLCC output capacitance with an ESR of up to 200m. Features The ISL9003A has a very high PSRR of 90dB and output noise is 20µVRMS (typical). When coupled with a no load quiescent current of 31µA (typical), and 0.5µA shutdown current, the ISL9003A is an ideal choice for portable wireless equipment. • Excellent Load Regulation: 90dB at 1kHz • Wide Input Voltage Capability: 2.3V to 6.5V • Extremely Low Quiescent Current: 31µA • Low Dropout Voltage: Typically 200mV at 150mA • Low Output Noise: Typically 20µVRMS at 100µA (1.5V) • Stable with 1µF to 4.7µF Ceramic Capacitors Pinouts ISL9003A (5 LD SC-70) TOP VIEW VIN 1 GND 2 EN 3 • Shutdown Pin Turns Off LDO with 1µA (max) Standby Current • Soft-start Limits Input Current Surge During Enable VO 5 • Current Limit and Overheat Protection • ±1.8% Accuracy Over all Operating Conditions CBYP 4 • 5 Ld SC-70 Package or 6 Ld µTDFN Package • -40°C to +85°C Operating Temperature Range ISL9003A (6 LD 1.6x1.6 ΜTDFN) TOP VIEW VO 1 6 VIN GND 2 5 NC CBYP 3 4 EN FN6299 Rev 5.00 July 18, 2014 • Pb-Free (RoHS compliant) Applications • PDAs, Cell Phones and Smart Phones • Portable Instruments, MP3 Players • Handheld Devices Including Medical Handhelds Page 1 of 12 ISL9003A Ordering Information VO VOLTAGE (V) (Note 2) TEMP. RANGE (°C) ISL9003AIENZ-T (Notes 3, 4) CBK 3.30 -40 to +85 PART NUMBER (Note 1) PART MARKING PACKAGE Pb-Free Tape and Reel 5 Ld SC-70 PKG. DWG. P5.049 ISL9003AIEMZ-T (Notes 3, 4) CBJ 3.00 -40 to +85 5 Ld SC-70 P5.049 ISL9003AIEKZ-T (Notes 3, 4) CCE 2.85 -40 to +85 5 Ld SC-70 P5.049 ISL9003AIEJZ-T (Notes 3, 4) CCD 2.80 -40 to +85 5 Ld SC-70 P5.049 ISL9003AIEHZ-T (Notes 3, 4) CCC 2.75 -40 to +85 5 Ld SC-70 P5.049 ISL9003AIERZ-T (Notes 3, 4) CDZ 2.60 -40 to +85 5 Ld SC-70 P5.049 ISL9003AIEFZ-T (Notes 3, 4) CCB 2.50 -40 to +85 5 Ld SC-70 P5.049 ISL9003AIECZ-T (Notes 3, 4) CBY 1.80 -40 to +85 5 Ld SC-70 P5.049 ISL9003AIEBZ-T (Notes 3, 4) CBW 1.50 -40 to +85 5 Ld SC-70 P5.049 ISL9003AIRUBZ-T (Note 5) L 1.50 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9003AIRUCZ-T (Note 5) G 1.80 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9003AIRUFZ-T (Note 5) F 2.50 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9003AIRURZ-T (Note 5) M2 2.60 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9003AIRUHZ-T (Note 5) H 2.75 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9003AIRUJZ-T (Note 5) J 2.80 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9003AIRUKZ-T (Note 5) K 2.85 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9003AIRUMZ-T (Note 5) M 3.00 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9003AIRUNZ-T (Note 5) N 3.30 -40 to +85 6 Ld µTDFN L6.1.6x1.6A NOTES: 1. Please refer to TB347 for details on reel specifications. 2. For other output voltages, contact Intersil Marketing. 3. The part marking is located on the bottom of the part. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN6299 Rev 5.00 July 18, 2014 Page 2 of 12 ISL9003A Absolute Maximum Ratings Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V VO Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + 0.3V) Thermal Resistance Recommended Operating Conditions Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V JA (°C/W) 231 5 Ld SC-70 Package (Note 6) . . . . . . . . . . . . . . . . . 6 Ld µTDFN Package (Note 7) . . . . . . . . . . . . . . . . 125 Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. Electrical Specifications PARAMETER Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF. SYMBOL TEST CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNITS DC CHARACTERISTICS Supply Voltage VIN Ground Current IDD 2.3 Output Enabled; IO = 0µA; VIN < 4.2V 6.5 V 31 40 µA 57 µA 0.5 1.2 µA Output Enabled; IO = 0µA; Full voltage range Shutdown Current IDDS UVLO Threshold VUV+ 1.9 2.1 2.3 V VUV- 1.6 1.8 2.0 V Regulation Voltage Accuracy Maximum Output Current IMAX Internal Current Limit ILIM Drop-out Voltage (Note 9) Thermal Shutdown Temperature Initial accuracy at VIN = VO + 0.5V, IO = 10mA, TJ = +25°C -0.7 +0.7 % VIN = VO + 0.5V to 6.5V, IO = 10µA to150mA, TJ = +25°C -0.8 +0.8 % VIN = VO + 0.5V to 6.5V, IO = 10µA to 150mA, TJ = -40°C to +125°C -1.8 +1.8 % Continuous 150 175 mA 265 355 mA VDO1 IO = 150mA; VO  2.5V 300 500 mV VDO2 IO = 150mA; 2.5V  VO  2.8V 250 400 mV VDO3 IO = 150mA; 2.8V  VO 200 325 mV TSD+ 140 °C TSD- 110 °C at 1kHz 90 dB at 10kHz 70 dB at 100kHz 50 dB BW = 10Hz to 100kHz, IO = 100µA 20 µVRMS BW = 10Hz to 100kHz, IO = 10mA 30 µVRMS AC CHARACTERISTICS Ripple Rejection (Note 8) Output Noise Voltage (Note 8) FN6299 Rev 5.00 July 18, 2014 IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1µF VO = 1.5V, TA = +25°C, CBYP = 0.1µF Page 3 of 12 ISL9003A Electrical Specifications PARAMETER Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF. (Continued) SYMBOL MIN (Note 10) TEST CONDITIONS MAX (Note 10) UNITS TYP DEVICE START-UP CHARACTERISTICS Device Enable tIme tEN Time from assertion of the EN pin to when the output voltage reaches 95% of the VO(nom). 250 500 µs LDO Soft-start Ramp Rate tSSR Slope of linear portion of LDO output voltage ramp during start-up 30 60 µs/V V EN PIN CHARACTERISTICS Input Low Voltage Input High Voltage VIL -0.3 0.4 VIH 1.4 VIN + 0.3 V 0.1 µA Input Leakage Current IIL, IIH Pin Capacitance CPIN Informative 5 pF NOTES: 8. Limits established by characterization and are not production tested. 9. VO = 0.98*VO(NOM); Valid for VO greater than 1.85V. 10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Typical Performance Curves 0.2 0.8 OUTPUT VOLTAGE, VO (%) 0.6 OUTPUT VOLTAGE CHANGE (%) VO = 3.3V ILOAD = 0mA 0.4 0.2 +25C 0.0 +85C -0.2 -0.4 -40C -0.6 -0.8 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 INPUT VOLTAGE (V) FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) FN6299 Rev 5.00 July 18, 2014 6.6 VO = 3.3V +25°C 0.1 IO = 0mA 0.0 -0.1 IO = 75mA IO = 150mA -0.2 -0.3 -0.4 3.3 3.8 4.3 4.8 5.3 5.8 6.3 INPUT VOLTAGE (V) FIGURE 2. OUTPUT VOLTAGE CHANGE (%) vs INPUT VOLTAGE (3.3V OUTPUT) Page 4 of 12 ISL9003A Typical Performance Curves (Continued) 0.10 1.0 0.06 OUTPUT VOLTAGE (%) OUTPUT VOLTAGE CHANGE (%) 0.6 0.4 0.2 -40°C 0.0 +25°C -0.2 +85°C -0.4 0.04 0.00 -0.08 50 75 100 125 150 IO = 150mA -0.04 -0.8 25 IO = 75mA -0.02 -0.06 0 IO = 0mA 0.02 -0.6 -1.0 VIN = 3.8V VO = 3.3V 0.08 VIN = 3.8V VO = 3.3V 0.8 -0.10 -40 175 -25 0 55 25 85 TEMPERATURE (C) LOAD CURRENT - IO (mA) FIGURE 4. OUTPUT VOLTAGE vs TEMPERATURE FIGURE 3. OUTPUT VOLTAGE vs LOAD CURRENT 2.9 3.4 3.3 2.8 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE, VO (V) 3.2 VO = 3.3V +25°C 3.1 3.0 IO = 0mA 2.9 IO = 75mA 2.8 IO = 150mA 2.7 2.6 2.5 2.7 IO = 0mA 2.6 IO = 75mA IO = 150mA 2.5 VO = 2.8V +25°C 2.4 2.4 2.3 2.6 3.1 3.6 4.1 4.6 5.1 5.6 6.1 2.3 2.5 6.6 3.0 3.5 4.5 5.0 5.5 6.0 6.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) FIGURE 6. DROPOUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT) FIGURE 5. DROPOUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) 250 225 VO = 3.3V 200 200 DROPOUT VOLTAGE, VDO (mV) DROPOUT VOLTAGE, VDO (mV) 4.0 150 VO = 2.8V VO = 3.3V 100 50 +25C +85C 175 150 125 100 -40C 75 50 25 0 0 25 50 75 100 125 OUTPUT LOAD (mA) 150 FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT FN6299 Rev 5.00 July 18, 2014 175 0 0 25 50 75 100 125 150 OUTPUT LOAD (mA) FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT Page 5 of 12 175 ISL9003A Typical Performance Curves (Continued) 140 60 GROUND CURRENT (µA) GROUND CURRENT (µA) 50 +85C 40 +25C 30 20 10 100 80 40 -40C 2.0 3.0 2.5 3.5 4.0 4.5 5.0 5.5 +25C +85C 60 20 VO = 3.3V IO = 0µA 0 1.5 VIN = 3.8V VO = 3.3V 120 6.0 -40C 0 6.5 0 25 50 INPUT VOLTAGE (V) 75 100 125 LOAD CURRENT (mA) 150 175 FIGURE 10. GROUND CURRENT vs LOAD FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE 100 IL = 150mA 3 70 2 60 VO(V) 80 IL = 75mA VIN = 3.8V VO = 3.3V 50 40 30 VIN = 5.0V VO = 3.3V IL = 150mA CL = 1µF 1 0 VEN (V) GROUND CURRENT (µA) 90 5 0 IL = 0mA 20 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE (C) 60 70 80 FIGURE 11. GROUND CURRENT vs TEMPERATURE 90 0 100 300 400 500 600 700 800 900 1000 TIME (µs) FIGURE 12. TURN ON/TURN OFF RESPONSE VO = 3.3V ILOAD = 150mA VO = 2.8V ILOAD = 150mA CLOAD = 1µF CBYP = 0.01µF CLOAD = 1µF CBYP = 0.01µF 4.3V 4.2V 3.6V 3.5V 10mV/DIV 10mV/DIV 400µs/DIV FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT FN6299 Rev 5.00 July 18, 2014 200 400µs/DIV FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT Page 6 of 12 ISL9003A Typical Performance Curves (Continued) 110 100 VO = 3.3V VIN = 3.8V 90 10mA 80 PSRR (dB) ILOAD 100mA 50mA 70 60 50 100µA 40 30 VO (10mV/DIV) 20 VIN = 3.9V VO = 1.8V CBYP = 0.1µF CLOAD = 1µF 10 0.1k 1.0 ms/DIV 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 16. PSRR vs FREQUENCY FIGURE 15. LOAD TRANSIENT RESPONSE SPECTRAL NOISE DENSITY (µV/Hz) 2.000 1.000 10mA 0.100 0.010 VIN = 3.9V VO = 1.8V CBYP = 0.1µF 100µA CIN = 1µF CLOAD = 1µF 0.001 10 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY FN6299 Rev 5.00 July 18, 2014 Page 7 of 12 ISL9003A Pin Description 5 LD SC-70 6 LD µTDFN PIN PIN NUMBER PIN NAME NUMBER DESCRIPTION 1 6 VIN 2 2 GND 3 4 EN 4 3 CBYP 5 1 VO LDO Output. Connect a 1µF capacitor of value to GND. - 5 NC No Connect. Supply Voltage/LDO Input. Connect a 1µF capacitor to GND. GND is the connection to system ground. Connect to PCB Ground plane. Output Enable. When this signal goes high, the LDO is turned on. Reference Bypass Capacitor Pin. Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the desired noise and PSRR performance. Typical Application ISL9003A (SC-70) 1 VIN (2.3V TO 5V) 2 ON 3 ENABLE OFF VIN VO 5 GND EN CBYP 4 C3 C1 VOUT 1 ISL9003A (µTDFN) 6 VIN VO 2 GND 3 C2 FN6299 Rev 5.00 July 18, 2014 C3 VOUT CBYP NC EN C2 C1, C2: 1µF X5R CERAMIC CAPACITOR C3: 0.1µF X5R CERAMIC CAPACITOR VIN (2.3V TO 5V) 5 ON ENABLE 4 OFF C1 C1, C2: 1µF X5R CERAMIC CAPACITOR C3: 0.1µF X5R CERAMIC CAPACITOR Page 8 of 12 ISL9003A Block Diagram VIN VO UVLO CONTROL LOGIC SHORT CIRCUIT, THERMAL PROTECTION, SOFT-START GND + - SD BANDGAP AND TEMPERATURE SENSOR VOLTAGE AND REFERENCE GENERATOR 1.0V 0.94V 0.9V GND CBYP Functional Description The ISL9003A contains all circuitry required to implement a high performance LDO. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9003A adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, and soft-start. Smart Thermal shutdown protects the device against overheating. Soft-start minimizes start-up input current surges without causing excessive device turn-on time. Power Control The ISL9003A has an enable pin, (EN), to control power to the LDO output. When EN is low, the device is in shutdown mode. In this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.3µA. When the EN pin goes high, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least 2.1V (typical). Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry turn-on. Once the references are stable, the LDO powers-up. During operation, whenever the VIN voltage drops below about 1.84V, the ISL9003A immediately disables the LDO output. When VIN rises back above 2.1V (assuming the EN pin is high), the device re-initiates its start-up sequence and LDO operation resumes automatically. Reference Generation current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01µF capacitor connected CBYP implements a 100Hz lowpass filter, and is recommended for most high performance applications. For the lowest noise application, a 0.1µF or greater CBYP capacitor should be used. This filters the reference noise to below the 10Hz to 1kHz frequency band, which is crucial in many noise-sensitive applications. The bandgap generates a zero temperature coefficient (TC) voltage for the regulator reference and other voltage references required for current generation and over-temperature detection. A current generator provides references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination. LDO Regulation and Programmable Output Divider The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9003A provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1µF to 4.7µF output capacitor that has a tolerance better than 20% and ESR less than 200m. The design is performance-optimized for a 1µF capacitor. Unless limited by the application, use of an output capacitor value above 4.7µF is not recommended as LDO performance improvement is minimal. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30µs/V to minimize current surge. The ISL9003A provides short-circuit protection by limiting the output current to about 265mA (typ). The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed FN6299 Rev 5.00 July 18, 2014 Page 9 of 12 ISL9003A The LDO uses an independently trimmed 1V reference as its input. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory. Overheat Detection The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about +140°C, the LDO momentarily shuts down until the die cools sufficiently. In the overheat condition, if the LDO sources more than 50mA it will be shut off. Once the die temperature falls back below about +110°C, the disabled LDO is re-enabled and soft-start automatically takes place. Exposed Thermal Pad The ISL9003A with µTDFN package has an exposed thermal pad at the bottom side of the package. The PCB layout should connect the exposed pad to some copper on the component layer for a good thermal conductivity. Since the copper area on the component layer is limited by the surrounding pins of the package, it is more effective to use some thermal vias to conduct the heat to other copper layers if possible. Electrically the copper and vias connecting to the exposed pad should be isolated from any other pin connection, they are strictly for thermal enhancement purpose. © Copyright Intersil Americas LLC 2006-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6299 Rev 5.00 July 18, 2014 Page 10 of 12 ISL9003A Small Outline Transistor Plastic Packages (SC70-5) P5.049 D VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES 5 SYMBOL 4 E CL 1 2 CL 3 e E1 b CL 0.20 (0.008) M C C CL A A2 SEATING PLANE A1 -C- PLATING b1 0.043 0.80 1.10 - 0.004 0.00 0.10 - A2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L2 c1 NOTES 0.031 0.010 0.018 0.017 Ref. 0.26 0.46 4 0.420 Ref. 0.006 BSC 0o N c MAX 0.000  WITH MIN A L b MILLIMETERS MAX A1 L1 0.10 (0.004) C MIN - 0.15 BSC 8o 0o 5 8o - 5 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 Rev. 3 7/07 NOTES: BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 4X 1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1  L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 4X 1 VIEW C 0.4mm 0.75mm 2.1mm 0.65mm TYPICAL RECOMMENDED LAND PATTERN FN6299 Rev 5.00 July 18, 2014 Page 11 of 12 ISL9003A Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN) A E 6 A B L6.1.6x1.6A 6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE 4 MILLIMETERS D PIN 1 REFERENCE 2X 0.15 C 1 2X 3 0.15 C MIN NOMINAL MAX NOTES A 0.45 0.50 0.55 - A1 - - 0.05 - 0.127 REF A3 A1 TOP VIEW e 1.00 REF 4 6 L CO.2 D2 DAP SIZE 1.30 x 0.76 3 1 b 6X 0.10 M C A B E2 b 0.15 0.20 0.25 - D 1.55 1.60 1.65 4 D2 0.40 0.45 0.50 - E 1.55 1.60 1.65 4 E2 0.95 1.00 1.05 - 0.50 BSC e L 0.25 0.30 0.35 Rev. 1 6/06 1. Dimensions are in mm. Angles in degrees. DETAIL A 0.10 C - NOTES: BOTTOM VIEW 6X SYMBOL 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall not exceed 0.08mm. 3. Warpage shall not exceed 0.10mm. 4. Package length/package width are considered as special characteristics. 0.08 C A3 SIDE VIEW C SEATING PLANE 5. JEDEC Reference MO-229. 6. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 0.127±0.008 0.127 +0.058 -0.008 TERMINAL THICKNESS A1 DETAIL A 0.25 0.50 1.00 0.45 1.00 2.00 0.30 1.25 LAND PATTERN FN6299 Rev 5.00 July 18, 2014 6 Page 12 of 12