ISL9014A
®
Data Sheet
March 11, 2008
Dual LDO with Low Noise, Low IQ, and
High PSRR
ISL9014A is a high performance dual LDO capable of
sourcing 300mA current from both outputs. The device has a
low standby current and high-PSRR and is stable with output
capacitance of 1µF to 10µF with ESR of up to 200m .
A reference bypass pin allows an external capacitor for
adjusting a noise filter for low noise and high PSRR
applications.
The quiescent current is typically only 45µA with both LDOs
enabled and active. Separate enable pins control each
individual LDO output. When both enable pins are low, the
device is in shutdown, typically drawing less than 0.1µA.
Several combinations of voltage outputs are standard.
Output voltage options for each LDO range from 1.5V to
3.3V. Other output voltage options are available on request.
FN6438.1
Features
• Integrates two high performance LDOs
- VO1 - 300mA output
- VO2 - 300mA output
• Excellent transient response to large current steps
• Excellent load regulation: 2.8V
200
325
mV
VO
2.8V
TSD+
145
°C
TSD-
110
°C
@ 1kHz
70
dB
@ 10kHz
55
dB
@ 100kHz
40
dB
AC CHARACTERISTICS
IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1µF
Ripple Rejection
3
FN6438.1
March 11, 2008
ISL9014A
Electrical Specifications
PARAMETER
Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature
range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 1.0V) to 6.5V with a minimum VIN of 2.3V;
CIN = 1µF; CO = 1µF; CBYP = 0.01µF (Continued)
SYMBOL
Output Noise Voltage
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
IO = 100µA, VO = 1.5V, TA = +25°C, CBYP = 0.1µF
BW = 10Hz to 100kHz
30
µVRMS
Time from assertion of the ENx pin to when the output voltage
reaches 95% of the VO(nom)
250
500
µs
Slope of linear portion of LDO output voltage ramp during
start-up
30
60
µs/V
DEVICE START-UP CHARACTERISTICS
Device Enable tIme
tEN
LDO Soft-Start Ramp Rate
tSSR
EN1, EN2 PIN CHARACTERISTICS
Input Low Voltage
VIL
-0.3
0.5
V
Input High Voltage
VIH
1.4
VIN + 0.3
V
0.1
µA
Input Leakage Current
IIL, IIH
Pin Capacitance
CPIN
Informative
5
pF
NOTES:
6. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.
7. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
4
FN6438.1
March 11, 2008
ISL9014A
Typical Performance Curves
0.10
0.8
VO = 3.3V
ILOAD = 0mA
0.6
VIN = 3.8V
VO = 3.3V
0.08
0.06
0.4
0.04
0.2
-40°C
0.02
-40°C
+25°C
-0.2
+25°C
0.00
0.0
-0.02
+85°C
-0.04
+85°C
-0.4
-0.06
-0.6
-0.08
-0.8
3.4
3.8
4.6
4.2
5.0
5.4
5.8
6.2
6.6
-0.10
50
0
150
100
200
250
300
350
400
LOAD CURRENT - IO (mA)
INPUT VOLTAGE (V)
FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE
(3.3V OUTPUT)
FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT
0.10
3.4
VIN = 3.8V
VO = 3.3V
ILOAD = 0mA
0.08
0.06
3.3
0.04
VO = 3.3V
IO = 0mA
3.2
IO = 150mA
0.02
3.1
0.00
IO = 300mA
-0.02
3.0
-0.04
-0.06
2.9
-0.08
-0.10
-40
-25
-10
5
20
50
35
65
TEMPERATURE (°C)
80
95
110
125
2.8
3.1
3.6
4.1
4.6
5.1
5.6
6.1
6.5
INPUT VOLTAGE (V)
FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE
2.9
FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE
(3.3V OUTPUT)
350
VO2 = 2.8V
IO = 0mA
300
2.8
250
2.7
VO = 2.8V
IO = 150mA
200
2.6
VO = 3.3V
150
IO = 300mA
2.5
100
2.4
2.3
50
2.6
3.1
3.6
4.1
4.6
5.1
5.6
INPUT VOLTAGE (V)
FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE
(VO2 = 2.8V)
5
6.1
6.5
0
0
50
100
150
200
250
OUTPUT LOAD (mA)
300
350
400
FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT
FN6438.1
March 11, 2008
ISL9014A
Typical Performance Curves
(Continued)
55
175
VO1 = 3.3V
150
50
+125°C
125
+85°C
+25°C
100
+25°C
45
-40°C
-40°C
40
75
35
50
VO1 = 3.3V
VO2 = 2.8V
30
25
IO (BOTH CHANNELS) = 0µA
0
0
25
50
75
100
125
OUTPUT LOAD (mA)
150
175
200
25
3.0
3.5
4.58
4.0
5.5
5.0
6.0
6.5
INPUT VOLTAGE (V)
FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT
FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE
55
200
180
50
160
140
+85°C
45
120
100
40
+25°C
80
35
-40°C
60
40
VIN = 3.8V
VO1 = 3.3V
VO2 = 2.8V
20
0
0
50
100
150
200
250
300
350
VIN = 3.8V
VO = 3.3V
ILOAD = 0µA
30
BOTH OUTPUTS ON
400
25
-40
-25
-10
5
LOAD CURRENT (mA)
110 125
VIN = 5.0V
VO1 = 3.3V
VO2 = 2.8V
IL1 = 300mA
IL2 = 300mA
CL-1, CL-2 = 1µF
CBYP = 0.01µF
3
2
3
2
95
VO2 (10mV/DIV)
VO1 = 3.3V
VO2 = 2.8V
IL1 = 300mA
IL2 = 300mA
VIN
VO1
4
80
FIGURE 10. GROUND CURRENT vs TEMPERATURE
FIGURE 9. GROUND CURRENT vs LOAD
5
35
65
20
50
TEMPERATURE (°C)
1
VO2
1
0
0
5
0
0
1
2
3
4
5
TIME (s)
6
7
8
FIGURE 11. POWER-UP/POWER-DOWN
6
9
10
0
100
200
300
400
500
600
700
800
900 1000
TIME (µs)
FIGURE 12. TURN-ON/TURN-OFF RESPONSE
FN6438.1
March 11, 2008
Typical Performance Curves
(Continued)
VO = 3.3V
ILOAD = 300mA
VO2 = 2.8V
ILOAD = 300mA
CLOAD = 1µF
CBYP = 0.01µF
CLOAD = 1µF
CBYP = 0.01µF
4.3V
4.2V
3.6V
3.5V
10mV/DIV
10mV/DIV
400µs/DIV
400µs/DIV
FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT
FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT
100
VIN = 3.6V
VO = 1.8V
IO = 10mA
CBYP = 0.1µF
CLOAD = 1µF
90
80
VO (25mV/DIV)
70
VO = 1.8V
VIN = 2.8V
60
50
40
300mA
30
ILOAD
20
100 A
10
0
0.1
100µs/DIV
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 16. PSRR vs FREQUENCY
FIGURE 15. LOAD TRANSIENT RESPONSE
1000
100
10
1
VIN = 3.6V
VO = 1.8V
ILOAD = 10mA
CBYP = 0.1µF
CIN = 1µF
CLOAD = 1µF
0.1
10
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY
7
FN6438.1
March 11, 2008
Pin Description
PIN #
PIN
NAME
1
VIN
Analog I/O
Supply Voltage/LDO Input:
Connect a 1µF capacitor to GND.
2
EN1
Low Voltage Compatible
CMOS Input
LDO-1 Enable.
3
EN2
Low Voltage Compatible
CMOS Input
LDO-2 Enable.
4
CBYP
Analog I/O
Reference Bypass Capacitor Pin:
Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the
desired noise and PSRR performance.
5, 7, 8
NC
NC
No Connection
6
GND
Ground
GND is the connection to system ground. Connect to PCB Ground plane.
9
VO2
Analog I/O
LDO-2 Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
10
VO1
Analog I/O
LDO-1 Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended).
TYPE
DESCRIPTION
Typical Application
ISL9014A
VIN (2.3V to 6.5V)
ENABLE 1
ENABLE 2
1
ON
2
OFF ON
3
OFF
4
5
C1
VIN
EN1
VO1
VO2
EN2
NC
CBYP
NC
NC
GND
10
VOUT 1
9
VOUT 2
8
7
6
C2
C3
C4
C1, C3, C4: 1µF X5R CERAMIC CAPACITOR
C2: 0.1µF X5R CERAMIC CAPACITOR
8
FN6438.1
March 11, 2008
Block Diagram
VIN
IS1
1V
LDO
VREF
VO1
ERROR
TRIM
VO1
AMPLIFIER
QEN1
~1.0V
VO2
LDO-1
LDO-2
EN1
CONTROL
LOGIC
EN2
UVLO
GND
BANDGAP AND
TEMPERATURE
SENSOR
1.00V
CBYP
Functional Description
The ISL9014A contains all circuitry required to implement
two high performance LDO’s. High performance is achieved
through a circuit that delivers fast transient response to
varying load conditions. In a quiescent condition, the
ISL9014A adjusts its biasing to achieve the lowest standby
current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, staged turn-on and soft-start.
Smart Thermal shutdown protects the device against
overheating. Staged turn-on and soft-start minimize start-up
input current surges without causing excessive device
turn-on time.
Power Control
The ISL9014A has two separate enable pins (EN1 and EN2)
to individually control power to each of the LDO outputs.
When both EN1 and EN2 are low, the device is in shutdown
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1 µA.
9
VOLTAGE
REFERENCE
GENERATOR
When one or both of the enable pins are asserted, the
device first polls the output of the UVLO detector to ensure
that VIN voltage is at least about 2.1V. Once verified, the
device initiates a start-up sequence. During the start-up
sequence, trim settings are first read and latched. Then,
sequentially, the bandgap, reference voltage and current
generation circuitry power up. Once the references are
stable, a fast-start circuit quickly charges the external
reference bypass capacitor (connected to the CBYP pin) to
the proper operating voltage. After the bypass capacitor has
been charged, the LDO’s power up.
If EN1 is brought high, and EN2 goes high before the VO1
output stabilizes, the ISL9014A delays the VO2 turn-on until
the VO1 output reaches its target level.
If EN2 is brought high, and EN1 goes high before VO2 starts
its output ramp, then VO1 turns on first and the ISL9014A
delays the VO2 turn-on until the VO1 output reaches its
target level.
FN6438.1
March 11, 2008
If EN2 is brought high, and EN1 goes high after VO2 starts
its output ramp, then the ISL9014A immediately starts to
ramp up the VO1 output.
If both EN1 and EN2 are brought high at the same time, the
VO1 output has priority, and is always powered up first.
During operation, whenever the VIN voltage drops below
about 1.8V, the ISL9014A immediately disables both LDO
outputs. When VIN rises back above 2.1V, the device
re-initiates its start-up sequence and LDO operation will
resume automatically.
Reference Generation
LDO Regulation and Programmable Output Divider
The LDO Regulator is implemented with a high-gain
operational amplifier driving a PMOS pass transistor. The
design of the ISL9014A provides a regulator that has low
quiescent current, fast transient response, and overall
stability across all operating and load current conditions.
LDO stability is guaranteed for a 1µF to 10µF output
capacitor that has a tolerance better than 20% and ESR less
than 200m . The design is performance-optimized for a 1µF
capacitor. Unless limited by the application, use of an output
capacitor value above 4.7µF is not recommended as LDO
performance improvement is minimal.
The reference generation circuitry includes a trimmed
bandgap, a trimmed voltage reference divider, a trimmed
current reference generator, and an RC noise filter. The filter
includes the external capacitor connected to the CBYP pin.
A 0.01µF capacitor connected CBYP implements a 100Hz
lowpass filter, and is recommended for most high
performance applications. For the lowest noise application, a
0.1µF or greater CBYP capacitor should be used. This filters
the reference noise to below the 10Hz to 1kHz frequency
band, which is crucial in many noise-sensitive applications.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30 µs/V to minimize current surge. The
ISL9014A provides short-circuit protection by limiting the
output current to about 475mA.
The bandgap generates a zero temperature coefficient (TC)
voltage for the reference divider. The reference divider
provides the regulation reference and other voltage
references required for current generation and
over-temperature detection.
The bandgap outputs a proportional-to-temperature current
that is indicative of the temperature of the silicon. This
current is compared with references to determine if the
device is in danger of damage due to overheating. When the
die temperature reaches about +145°C, one or both of the
LDO’s momentarily shut down until the die cools sufficiently.
In the overheat condition, only the LDO sourcing more than
50mA will be shut off. This does not affect the operation of
the other LDO. If both LDOs source more than 50mA and an
overheat condition occurs, both LDO outputs are disabled.
Once the die temperature falls back below about +110°C,
the disabled LDO(s) are re-enabled and soft-start
automatically takes place.
The current generator outputs references required for
adaptive biasing as well as references for LDO output
current limit and thermal shutdown determination.
10
Each LDO uses an independently trimmed 1V reference. An
internal resistor divider drops the LDO output voltage down
to 1V. This is compared to the 1V reference for regulation.
The resistor division ratio is programmed in the factory.
Overheat Detection
FN6438.1
March 11, 2008
Dual Flat No-Lead Plastic Package (DFN)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
TOP
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
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FN6438.1
March 11, 2008
