ISL9021IIRZ-T

ISL9021 I GNS DE S T W E N AR FOR MENT PDatasheet D E E EN D LA C O M M ED R EP A C E R D 021 N O T O M M EN ISL9 C E R January 14, 2010 250mA Single LDO with Low IQ, Low Noise and High PSRR LDO FN6867.2 Features The ISL9021 is a single LDO providing high performance low input voltage, high PSRR. It delivers guaranteed continuous 250mA load current and is stable with 1µF to 4.7µF of output capacitance (±30%) with an ESR range of 5mΩ to 400mΩ. • High Performance LDO with 250mA guaranteed continuous output current • Input Voltage Range: 1.5V to 5.5V • Output Voltage Range: 0.9V to 3.3V • High PSRR: 75dB @ 10kHz, 50dB @ 1MHz The input voltage range for the ISL9021 is between 1.5V to 5.5V and the output voltage comes in many fixed voltage options with ±1.8% accuracy over temperature, line and load ranges. Other output voltage within the range of 0.9V to 3.3V may be available upon request. The ISL9021 has typical PSRR of 75dB @ 10kHz and 50dB @ 1MHz. • Low Quiescent Current: 35µA The reverse current protection feature prevents current from flowing back to the power source when the output voltage is pulled higher than the input. • Soft-start Limits Input Current Surge During Enable The ISL9021 is offered in tiny 4-bump 1.155mmx0.975mm WLCSP and 1.6mmx1.6mm 6 Ld µTDFN packages. Pinouts • Dropout Voltage: 1.8V mA 150 250 mV 160 °C 20 °C VIN = 4.5V, VO = 3.3V @ 1kHz 60 dB VIN = 4.5V, VO = 3.3V @ 10kHz 75 dB VIN = 4.5V, VO = 3.3V @ 1MHz 50 dB 8.5*VO µVRMS Thermal Shutdown Hysteresis AC CHARACTERISTICS Ripple Rejection (Note 6) Output Noise Voltage (Note 6) VIN = 4.2V, TA = +25°C, BW = 10Hz to 100kHz, IO = 10mA DEVICE START-UP CHARACTERISTICS Device Enable Time tEN Time from assertion of the EN pin to when the output voltage reaches 95% of the VO (nom) 250 600 µs LDO Soft-start Ramp Rate tSSR Slope of linear portion of LDO output voltage ramp during start-up 30 60 µs/V 0.4 V EN LOGIC CHARACTERISTICS Input Low Voltage VIL Input High Voltage VIH Input Leakage Current IIL, IIH 1.1 V 0.1 µA NOTES: 6. Limits established by characterization and are not production tested. 7. Dropout voltage is measured as VIN - VO, when VO is 4% lower than the value of VO; when VIN = VO + 0.5V. 3 FN6867.2 January 14, 2010 ISL9021 Typical Operating Performance 45 40 T = ROOM TEMP T = +85°C T = +45°C QUIESCENT CURRENT (µA) QUIESCENT CURRENT (µA) 45 35 30 25 T = 0°C 20 T = -25°C 15 T = -40°C 10 5 0 1.5 2.5 3.5 4.5 INPUT VOLTAGE (V) T = +45°C T = -40°C 10 5 1.5 2.5 3.5 4.5 INPUT VOLTAGE (V) 5.5 +25°C +85°C T = 0°C T = -40°C T = -25°C 10 1.80 -40°C 1.75 1.70 0 1.65 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 1.60 0 6.0 50 100 150 Io (mA) 200 250 300 FIGURE 4. LOAD REGULATION vs TEMPERATURE (VOUT = 1.85V) FIGURE 3. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT = 3.3V) 2.00 3.5 1.95 3.4 +25°C +25°C +85°C 3.3 1.85 1.80 +85°C Vo (V) Vo (V) 15 1.85 20 1.75 T = -25°C 1.90 30 1.90 T = 0°C 20 1.95 40 -10 3.5 25 T = +85°C Vo (V) QUIESCENT CURRENT (µA) T = ROOM TEMP 30 FIGURE 2. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT = 1.85V) FIGURE 1. QUIESCENT CURRENT vs INPUT VOLTAGE (VOUT = 0.9V) 50 35 0 5.5 T = +85°C T = +45°C T = ROOM TEMP 40 -40°C 1.70 1.65 3.2 -40°C 3.1 3.0 1.60 2.9 1.55 1.50 2.5 3.5 4.5 5.5 VIN(V) FIGURE 5. LINE REGULATION vs TEMPERATURE (VOUT = 1.85V) 4 6.5 2.8 0 50 100 150 200 250 300 Io (mA) FIGURE 6. LOAD REGULATION vs TEMPERATURE (VOUT = 3.3V) FN6867.2 January 14, 2010 ISL9021 Typical Operating Performance (Continued) 3.50 1.05 3.45 1.00 3.40 0.95 +25°C +85°C 3.30 3.25 3.20 +85°C 0.90 Vo (V) Vo (V) 3.35 +25°C -40°C 0.85 -40°C 0.80 0.75 3.15 3.10 0.70 3.05 0.65 3.00 3.5 4.0 4.5 5.0 5.5 6.0 0.60 0 50 100 150 200 250 300 Io (mA) VIN (V) FIGURE 8. LOAD REGULATION vs TEMPERATURE (VOUT = 0.9V) FIGURE 7. LINE REGULATION vs TEMPERATURE (VOUT = 3.3V) VIN = 2.7V 1.00 VOUT = 1.85V 0.95 COUT = 1µF VOUT +25°C +85°C Vo (V) 0.90 0.85 -40°C 0.80 0.75 IOUT 0.70 3.0 3.5 4.0 4.5 5.0 5.5 6.0 IOUT = 1mA TO 250mA VIN (V) FIGURE 9. LINE REGULATION vs TEMPERATURE (VOUT = 0.9V) FIGURE 10. LOAD TRANSIENT RESPONSE VIN = 2.7V COUT = 4.7µF VOUT = 1.85V VOUT IOUT IOUT = 1mA TO 250mA FIGURE 11. LOAD TRANSIENT RESPONSE 5 FIGURE 12. ENABLE FUNCTION (VIN = 3.6V, VOUT = 1.85V, COUT 1µF) FN6867.2 January 14, 2010 ISL9021 Typical Operating Performance (Continued) -20 -30 VIN = 4.5VDC + 50mVAC COUT = 1µF PSRR (dB) -40 IO = 10mA -50 -60 -70 IO = 0A -80 -90 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 13. POWER SUPPLY REJECTION vs FREQUENCY Pin Descriptions PIN NAME DESCRIPTION VIN IC Supply/LDO Input. Connect a 1µF capacitor to GND. GND System ground pin. EN LDO Enable. When this signal goes high, the LDO is turned on. VO LDO Output. Connect a 1µF to 4.7µF capacitor to GND. E-Pad For µTDFN package option only. Connect it to the system ground. Typical Application ISL9021 VIN (1.5V TO 5.5V) VIN VO EN GND VOUT ON ENABLE OFF C1 C2 C1, C2: 1µF X5R CERAMIC CAPACITOR 6 FN6867.2 January 14, 2010 ISL9021 Block Diagram PASS ELEMENT VIN VOUT EN TEMP SENSOR CONTROL LOGIC VOLTAGE AND REFERENCE GENERATOR SHORT-CIRCUIT PROTECTION THERMAL PROTECTION SOFT-START + BANDGAP GND 7 FN6867.2 January 14, 2010 ISL9021 Functional Description The ISL9021 is a high performance low-dropout regulator (LDO) with 250mA sourcing capability. The extra low ground current makes this part a good choice for handheld product applications. The device also incorporates overcurrent, thermal shutdown, reverse current protections, and soft-start features. Thermal shutdown protects the device against overheating. Soft-start limits the start-up input current surges. In some applications, the output voltage may be externally pulled higher than input, or the input voltage could be connected to ground, or connected to some voltage lower than the output side. The ISL9021 features reverse current protection; that can block the reverse current from output to input. Enable Control The ISL9021 has an enable pin. When EN is low, the IC is in shutdown mode. In this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1µA(typ). Driving this pin high will turn on the device. LDO Protections The ISL9021 offers several protection functions, making it ideal for use in battery-powered applications.The ISL9021 provides short-circuit protection by limiting the output current at current limit of 260mA(min). If the short circuit lasts long enough, the die temperature increases, and the over-temperature protection circuit will shut down the output. When the die temperature reaches about +145°C, thermal protection starts to work with output being loaded with at least 50mA. Once the die temperature drops to about +110°C, the LDO will resume operation beginning with a soft-start. 8 The ISL9021’s reverse current protection is intended to block reverse conduction if output voltage is higher than input voltage. Input and Output Capacitors The ISL9021 provides a linear regulator that has low quiescent current, fast transient response, and overall stable operation across the recommended operating conditions. A ceramic capacitor (X5R or X7R) with a capacitance of 1µF to 4.7µF with an ESR up to 400mΩ is suitable for the ISL9021 to maintain its output stability. The ground connection of the output capacitor should be routed directly to the GND pin of the device, and also placed close to the IC. Similarly for the input capacitor, usually a 1µF ceramic capacitor (X5R or 7R) is suitable for most cases, but if a large, fast rising load transient condition is expected, a higher value input capacitor may be necessary to achieve satisfactory performance. Board Layout Recommendations A good PCB layout is an important step to achieve good performance. It is recommended to design the board with separate ground planes for input and output, and connect both ground planes at the GND pin of the IC. Consideration should be taken when placing the components and routing the trace to minimize the ground impedance, and keep the parasitic inductance low. Usually the input/output capacitors should be placed as close to the IC as possible with a good ground connection. FN6867.2 January 14, 2010 ISL9021 Wafer Level Chip Scale Package (WLCSP 0.4mm Ball Pitch) W2x2.4 2x2 ARRAY 4 BALL WAFER LEVEL CHIP SCALE PACKAGE D E PIN 1 TOP VIEW SYMBOL MILLIMETERS A 0.44 Min, 0.495 Nom, 0.55 Max A1 0.190 ±0.030 A2 0.305 ±0.025 b 0.270 ±0.030 D 1.155 ±0.020 D1 0.400 BASIC E 0.975 ±0.020 E1 0.400 BASIC e 0.400 BASIC SD 0.200 BASIC SE 0.00 BASIC NUMBER OF BUMPS: 4 Rev. 2 6/08 A2 A A1 NOTES: 1. All dimensions are in millimeters. b SIDE VIEW e ( D1 ) 2 SE e ( E1 ) 1 B A b SD BOTTOM VIEW All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN6867.2 January 14, 2010 ISL9021 Package Outline Drawing L6.1.6x1.6 6 LEAD ULTRA THIN DUAL FLAT NO-LEAD COL PLASTIC PACKAGE (UTDFN COL) Rev 1, 11/07 2X 1.00 1.60 A 6 PIN 1 INDEX AREA PIN #1 INDEX AREA 6 B 4X 0.50 1 3 5X 0 . 40 ± 0 . 1 1X 0.5 ±0.1 1.60 (4X) 0.15 4 6 0.10 M C A B TOP VIEW 4 0.25 +0.05 / -0.07 BOTTOM VIEW ( 6X 0 . 25 ) SEE DETAIL "X" ( 1X 0 .70 ) 0 . 55 MAX 0.10 C C BASE PLANE (1.4 ) SIDE VIEW SEATING PLANE 0.08 C 0 . 2 REF C ( 5X 0 . 60 ) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" ( 4X 0 . 5 ) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 10 FN6867.2 January 14, 2010