DATASHEET
ISL90810
FN8234
Rev 3.00
September 10, 2015
Single Digitally Controlled Potentiometer (XDCP™) Low Noise/Low Power/I2C
Bus/256 Taps
The ISL90810 integrates a digitally controlled potentiometer
(XDCP) on a monolithic CMOS integrated circuit.
Features
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
Wiper Register (WR) that can be directly written to and read
by the user. The contents of the WR controls the position of
the wiper. When powered on the ISL90810’s wiper will
always commence at mid-scale (128 tap position).
• I2C serial interface with write/read capability
The DCP can be used as three-terminal potentiometer or as
two-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
• 256 resistor taps - 0.4% resolution
• Power-on preset to mid-scale (128 tap position)
• Wiper resistance: 70 typical @ 3.3V
• Standby current 5µA max
• Power supply: 2.7V to 5.5V
• 50k, 10k total resistance
• 8 Ld MSOP
• Pb-free plus anneal available (RoHS compliant)
Pinout
ISL90810
(8 LD MSOP)
TOP VIEW
NC
1
8
VCC
SCL
2
7
RH
SDA
3
6
RL
GND
4
5
RW
Ordering Information
PART NUMBER
PART MARKING
RTOTAL (k)
TEMP RANGE (°C)
PACKAGE
PKG. DWG#
ISL90810WIU8Z* (Note)
(No longer available,
recommended
replacement:
ISL90810UAU8Z-TK)
DEN
10
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
ISL90810WAU8Z* (Note)
(No longer available,
recommended
replacement:
ISL90810UAU8Z-TK)
810WA
10
-40 to +105
8 Ld MSOP (Pb-free)
M8.118
ISL90810UIU8Z* (Note)
DEM
50
-40 to +85
8 Ld MSOP (Pb-free)
M8.118
ISL90810UAU8Z* (Note)
810UA
50
-40 to +105
8 Ld MSOP (Pb-free)
M8.118
*Add "-TK" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8234 Rev 3.00
September 10, 2015
Page 1 of 12
ISL90810
Block Diagram
VCC
RH
SDA
SCL
I2C AND
WIPER
CONTROL
REGISTER
RL
RW
GND
Equivalent Circuitry
Pin Descriptions
MSOP
PIN
SYMBOL
1
NC
DESCRIPTION
RTOTAL
No connection
2
SCL
I2C interface clock
3
SDA
Serial data I/O for the I2C interface
4
GND
Ground
5
RW
“Wiper” terminal of the DCP
6
RL
“Low” terminal of the DCP
7
RH
“High” terminal of the DCP
8
VCC
Power supply
FN8234 Rev 3.00
September 10, 2015
RH
CH
10pF
CW
CL
RL
10pF
25pF
RW
Page 2 of 12
ISL90810
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at Any Digital Interface Pin
With Respect to VSS . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at Any DCP Pin With
Respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +105°C
ESD
HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV
MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Thermal Resistance (Typical, Note 1)
JA (°C/W)
8 Ld MSOP Package
130
Maximum Junction Temperature (Plastic Package . . . . . . . . +150°C
Recommended Operating Conditions
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Automotive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL
RTOTAL
Over recommended operating conditions unless otherwise stated.
PARAMETER
RH to RL Resistance
TEST CONDITIONS
MIN
W, U versions respectively
CH/CL/CW
ILkgDCP
Wiper resistance
-20
VCC = 3.3V @ +25°C
Wiper current = VCC/RTOTAL
70
Potentiometer Capacitance
(Note 14, Equivalent circuitry)
Leakage on DCP pins (Note 14)
MAX
10, 50
RH to RL Resistance Tolerance
RW
TYP
(Notes 2)
k
+20
%
200
10/10/25
Voltage at pin from GND to VCC
0.1
UNIT
pF
1
µA
1
LSB (Note 3)
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)
INL (Note 7)
Integral Non-Linearity
DNL (Note 6)
Differential Non-Linearity
ZSerror (Note 4) Zero-Scale Error
FSerror (Note 5) Full-Scale Error
-1
Monotonic over all tap positions
W option -0.75
+0.75
LSB (Note 3)
U option
+0.5
LSB (Note 3)
LSB (Note 3)
-0.5
W option
0
1
7
U option
0
0.5
2
W option
-7
-1
0
U option
-2
-0.5
0
TCV (Notes 8, 14) Ratiometric Temperature Coefficient DCP Register set to 80 hex
±4
LSB (Note 3)
ppm/°C
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected)
RINL (Note 12)
Integral Non-Linearity
DCP register set between 20 hex and FF hex.
Monotonic over all tap positions
RDNL (Note 6)
Differential Non-Linearity
DCP register set between 20 hex W option -0.75
and FF hex. Monotonic over all tap
U option -0.5
positions
Roffset (Note 10) Offset
TCR
(Notes 13, 14)
1
MI (Note 9)
+0.75
MI (Note 9)
+0.5
MI (Note 9)
W option
0
1
7
MI (Note 9)
U option
0
0.5
2
MI (Note 9)
Resistance Temperature Coefficient DCP register set between 20 hex and FF hex
FN8234 Rev 3.00
September 10, 2015
-1
±35
ppm/°C
Page 3 of 12
ISL90810
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
ICC1
ISB
ILkgDig
PARAMETER
VCC Supply Current
(Volatile Write/Read)
VCC Current (Standby)
Leakage Current at Pins SDA and
SCL
tDCP (Note 14) DCP Wiper Response Time
Vpor
Power-On Recall Voltage
VCCRamp
VCC Ramp Rate
tD (Note 14)
Power-Up Delay
TYP
(Note 1)
MAX
UNITS
fSCL = 400kHz; SDA = Open; (for I2C, Active,
20
100
µA
VCC = +5.5V, I2C Interface in Standby State,
Temperature range from -40°C to +85°C
2
5
µA
VCC = +5.5V, I2C Interface in Standby State,
Temperature range from -40°C to +105°C
2
8
µA
VCC = +3.6V, I2C Interface in Standby State,
Temperature range from -40°C to +85°C
0.8
2
µA
VCC = +3.6V, I2C Interface in Standby State,
Temperature range from -40°C to +105°C
0.8
5
µA
10
µA
1
µs
TEST CONDITIONS
MIN
Read and Volatile Write States only)
Voltage at pin from GND to VCC
-10
SCL falling edge of last bit of DCP Data Byte to
wiper change
Minimum VCC at which memory recall occurs
1.8
2.6
0.2
VCC above Vpor, to DCP Initial Value Register
recall completed, and I2C Interface in standby state
V
V/ms
3
ms
SERIAL INTERFACE SPECIFICATIONS
VIL
SDA, and SCL Input Buffer LOW
Voltage
-0.3
0.3*VCC
V
VIH
SDA, and SCL Input Buffer HIGH
Voltage
0.7*VCC
VCC+0.3
V
Hysteresis
(Note 14)
SDA and SCL Input Buffer Hysteresis
V
0.05*
VCC
VOL (Note 14) SDA Output Buffer LOW Voltage,
Sinking 4mA
0.4
V
Cpin (Note 14) SDA, and SCL Pin Capacitance
10
pF
SCL Frequency
400
kHz
50
ns
900
ns
fSCL
0
tIN (Note 14)
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
tAA (Note 14)
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until SDA
Valid
exits the 30% to 70% of VCC window.
tBUF (Note 14) Time the Bus Must be Free Before the SDA crossing 70% of VCC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of VCC during
the following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of VCC
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to
SDA entering the 30% to 70% of VCC window.
0
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to
SDA rising edge crossing 30% of VCC.
600
ns
FN8234 Rev 3.00
September 10, 2015
Page 4 of 12
ISL90810
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge. Both
or Volatile Only Write
crossing 70% of VCC.
tHD:STO
tDH (Note 14)
TYP
(Note 1)
MAX
UNITS
600
ns
0
ns
Output Data Hold Time
From SCL falling edge crossing 30% of VCC, until
SDA enters the 30% to 70% of VCC window.
tR (Note 14)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF (Note 14)
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb (Note 14)
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2~2.5k.
For Cb = 40pF, max is about 15~20k
1
Rpu (Note 14) SDA and SCL Bus Pull-Up Resistor
Off-Chip
k
SDA vs SCL Timing
tHIGH
tF
SCL
tLOW
tR
tSU:DAT
tSU:STA
SDA
(INPUT TIMING)
tHD:DAT
tHD:STA
tSU:STO
tAA
tDH
tBUF
SDA
(OUTPUT TIMING)
NOTES:
2. Typical values are for TA = +25°C and 3.3V supply voltage.
3. LSB: [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
4. ZS error = V(RW)0/LSB.
5. FS error = [V(RW)255 – VCC]/LSB.
6. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
7. INL = (V(RW)i – i • LSB – V(RW)0)/LSB, for i = 1 to 255.
Max V RW i – Min V RW i
10 6
8. TC V = ---------------------------------------------------------------------------------------------- ----------------- for i = 16 to 240 decimal, T = -40°C to +105°C. Max( ) is the maximum value of the wiper
Max V RW i + Min V RW i 2 145°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
9. MI = |R255 – R0|/255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively.
Roffset = R0/MI, when measuring between RW and RL.
10. Roffset = R255/MI, when measuring between RW and RH.
11. RDNL = (Ri – Ri-1)/MI, for i = 32 to 255.
12. RINL = [Ri – (MI • i) – R0]/MI, for i = 32 to 255.
6
Max Ri – Min Ri
10
13. TC R = --------------------------------------------------------------- ----------------- for i = 32 to 255, T = -40°C to +105°C. Max( ) is the maximum value of the resistance and Min ( ) is the
Max Ri + Min Ri 2 145°C minimum value of the resistance over the temperature range.
14. This parameter is not 100% tested.
FN8234 Rev 3.00
September 10, 2015
Page 5 of 12
ISL90810
Typical Performance Curves
160
1.8
Vcc = 2.7, T = +85°C
Vcc = 2.7, T = -40°C
1.6
Vcc = 2.7, T = +25°C
1.4
120
100
80
60
40
20
0
1.2
STANDBY ICC (µA)
WIPER RESISTANCE ()
140
Vcc = 5.5, T = -40°C
0
50
1.0
0.8
0.4
0.2
Vcc = 5.5, T = +25°C
150
200
+85°C
0.6
Vcc = 5.5, T = +85°C
100
-40°C
+25°C
0.0
2.7
250
3.2
3.7
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[I(RW) = VCC/Rtotal] FOR 50k (U)
0.2
Vcc = 5.5, T = -40°C
0.15
4.2
4.7
5.2
VCC (V)
TAP POSITION (DECIMAL)
FIGURE 2. STANDBY ICC vs VCC
0.3
Vcc = 2.7, T = -40°C
Vcc = 5.5, T = -40°C
Vcc = 2.7, T = -40°C
Vcc = 2.7, T = +25°C
0.2
Vcc = 5.5, T = +85°C
0.1
0.05
INL (LSB)
DNL (LSB)
0.1
0
-0.05
-0.1
-0.15
Vcc = 5.5, T = +25°C
Vcc = 2.7, T = +85°C
Vcc = 5.5, T = +85°C
-0.2
0
50
100
150
200
0
Vcc = 2.7, T = +25°C
Vcc = 2.7, T = +85°C
-0.1
Vcc = 5.5, T = +25°C
-0.2
-0.3
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
0.4
0
-0.1
-0.2
Vcc = 5.5V
-0.3
FSerror (LSB)
ZSerror (LSB)
0.35
0.3
2.7V
0.25
-0.4
Vcc = 2.7V
-0.5
-0.6
-0.7
0.2
-0.8
5.5V
-0.9
0.15
-40
-20
0
20
40
TEMPERATURE (°C)
FIGURE 5. ZSerror vs TEMPERATURE
FN8234 Rev 3.00
September 10, 2015
60
80
-1
-40
-20
0
20
40
60
TEMPERATURE (°C)
FIGURE 6. FSerror vs TEMPERATURE
Page 6 of 12
80
ISL90810
Typical Performance Curves
(Continued)
0.5
0.3
Vcc = 2.7, T = +25°C
0.4
Vcc = 5.5, T = +25°C
0.2
0.1
INL (LSB)
DNL (LSB)
Vcc = 5.5, T = -40°C
0.2
0.1
0
Vcc = 5.5, T = +85°C
0
-0.1
-0.1
-0.2
Vcc = 5.5, T = +85°C
-0.3
Vcc = 2.7, T = +85°C
Vcc = 2.7, T = -40°C
Vcc = 5.5, T = -40°C
-0.2
-0.3
32
82
132
182
TAP POSITION (DECIMAL)
-0.4 Vcc = 2.7, T = +85°C
Vcc = 5.5, T = +25°C
-0.5
32
82
132
232
Vcc = 2.7, T = -40°C
182
232
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
50k (U)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
50k (U)
1.50
20
1.00
10
0.50
2.7V
TC (ppm/°C)
END TO END RTOTAL CHANGE (%)
Vcc = 2.7, T = +25°C
0.3
5.5V
0.00
-0.50
0
-10
-1.00
-1.50
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
-20
32
82
132
182
232
TAP POSITION (DECIMAL)
FIGURE 9. END TO END RTOTAL % CHANGE vs
TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
35
INPUT
25
TC (ppm/°C)
15
5
OUTPUT
-5
-15
-25
32
Tap Position = Mid Point
RTOTAL = 9.4K
57
82
107
132
157
182
207
232
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FN8234 Rev 3.00
September 10, 2015
FIGURE 12. FREQUENCY RESPONSE (2.2MHz)
Page 7 of 12
ISL90810
Typical Performance Curves
(Continued)
Signal at Wiper (Wiper Unloaded)
SCL
Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)
Wiper Movement Mid Point
From 80h to 7fh
FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)
Principles of Operation
The ISL90810 is an integrated circuit incorporating one DCP
with its associated registers, and an I2C serial interface
providing direct communication between a host and the
potentiometer.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). When the WR of the DCP
contains all zeroes (WR[7:0]: 00h), its wiper terminal (RW) is
closest to its “Low” terminal (RL). When the WR of the DCP
contains all ones (WR[7:0]: FFh), its wiper terminal (RW) is
closest to its “High” terminal (RH). As the value of the WR
increases from all zeroes (0 decimal) to all ones (255
decimal), the wiper moves monotonically from the position
closest to RL to the closest to RH. At the same time, the
resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the ISL90810 is being powered up, The WR is reset to
80h (128 decimal), which locates RW roughly at the center
between RL and RH.
The WR can be read or written to directly using the I2C serial
interface as described in the following sections. The I2C
interface Address Byte has to be set to 00hex to access the
WR.
FN8234 Rev 3.00
September 10, 2015
FIGURE 14. LARGE SIGNAL SETTLING TIME
I2C Serial Interface
The ISL90810 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master always
initiates data transfers and provides the clock for both
transmit and receive operations. Therefore, the ISL90810
operates as a slave device in all applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 15). On power-up of the ISL90810 the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL90810 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 15). A START condition is ignored during the powerup for the device.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 15) A STOP condition at the end of
a read operation, or at the end of a write operation places
the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 16).
Page 8 of 12
ISL90810
The ISL90810 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90810 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 0101000 as the seven
MSBs. The LSB is the Read/Write bit. Its value is “1” for a
Read operation, and “0” for a Write operation (See Table 1)
The address byte is set to 00h and follows the identification
byte. Read and write operations always point to address
00h, indicating the WR for the device.
TABLE 1. IDENTIFICATION BYTE FORMAT
0
1
0
1
0
0
0
R/W
(MSB)
(LSB)
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL90810 responds with an ACK. At this time the device
enters its standby state (See Figure 17).
Data Protection
A valid Identification Byte. Address Byte, and total number of
SCL pulses act as a protection for the registers. During a
Write sequence, the Data Byte is loaded into an internal shift
register as it is received. The Data Byte is transferred to the
Wiper Register (WR) at the falling edge of the SCL pulse
that loads the last bit (LSB) of the Data Byte.
Read Operation
A Read operation consists of a three byte instruction
followed by one Data Byte (See Figure 18). The master
initiates the operation issuing the following sequence: a
START, the identification byte with the R/W bit set to "0", an
Address Byte, a second START, and a second Identification
byte with the R/W bit set to "1". After each of the three bytes,
the ISL90810 responds with an ACK. The the ISL90810
transmits Data Bytes as long as the master responds with an
ACK during the SCL cycle following the eighth bit of each
byte. The master terminates the read operation (issuing a
ACK and a STOP condition) following the last bit of the Data
Byte (See Figure 18).
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
SDA OUTPUT FROM
TRANSMITTER
9
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN8234 Rev 3.00
September 10, 2015
Page 9 of 12
ISL90810
WRITE
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE
ADDRESS
BYTE
0 1 0 1 0 0 0 0
0 0 0 0 0 0 0 0
SIGNALS FROM
THE ISL90810
A
C
K
A
C
K
A
C
K
S
T
O
P
DATA
BYTE
FIGURE 17. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
SIGNALS FROM
THE SLAVE
IDENTIFICATION
BYTE WITH
R/W=0
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W=1
ADDRESS
BYTE
0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0
A
C
K
A S
C T
K O
P
0 1 0 1 0 0 0 1
A
C
K
A
C
K
DATA BYTE
FIGURE 18. READ SEQUENCE
FN8234 Rev 3.00
September 10, 2015
Page 10 of 12
ISL90810
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
September 10, 2015
FN8234.3
CHANGE
Updated the Ordering Information table on page 1.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing M8.118 to the latest revision.
-Revision 2 to Revision 3 changes - Updated to new intersil format by adding land pattern and moving
dimensions from table onto drawing.
-Revision 3 to Revision 4 changes - Corrected lead width dimension typo in side view 1 from "0.25 0.036" to "0.25 - 0.36".
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2005-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8234 Rev 3.00
September 10, 2015
Page 11 of 12
ISL90810
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.55 ± 0.15
0.25
3°±3°
0.85±010
H
DETAIL "X"
C
SEATING PLANE
0.25 - 0.36
0.08 M C A-B D
0.10 ± 0.05
0.10 C
SIDE VIEW 1
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
FN8234 Rev 3.00
September 10, 2015
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
Page 12 of 12
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