DATASHEET
ISL9110, ISL9112
FN7649
Rev.3.00
Jul 26, 2018
1.2A High Efficiency Buck-Boost Regulators
Features
The ISL9110 and ISL9112 are highly-integrated buck-boost
switching regulators that accept input voltages either above or
below the regulated output voltage. Unlike other Buck-Boost
regulators, these regulators automatically transition between
operating modes without significant output disturbance.
• Accepts input voltages above or below regulated output
voltage
• Automatic and seamless transitions between Buck and
Boost modes
Both parts are capable of delivering up to 1.2A output current,
and provide excellent efficiency due to their fully synchronous
4-switch architecture. No-load quiescent current of only 35µA
also optimizes efficiency under light-load conditions. Forced
PWM and/or synchronization to an external clock may also be
selected for noise sensitive applications.
• Input voltage range: 1.8V to 5.5V
• Output current: Up to 1.2A
• High efficiency: Up to 95%
• 35µA quiescent current maximizes light-load efficiency
• 2.5MHz switching frequency minimizes external component
size
The ISL9110 is designed for standalone applications and
supports 3.3V and 5V fixed output voltages or variable output
voltages with an external resistor divider. Output voltages as
low as 1V, or as high as 5.2V are supported using an external
resistor divider.
• Selectable Forced PWM mode and external synchronization
• I2C Interface (ISL9112)
• Fully protected for overcurrent, over-temperature, and
undervoltage
The ISL9112 supports a broader set of programmable features
that may be accessed using an I2C bus interface. With a
programmable output voltage range of 1.9V to 5V, the
ISL9112 is ideal for applications requiring dynamically
changing supply voltages. A programmable slew rate can be
selected to provide smooth transitions between output voltage
settings.
• Small 3mmx3mm TDFN Package
Applications
• Regulated 3.3V from a single Li-ion battery
• Smart phones and tablet computers
The ISL9110 and ISL9112 require only a single inductor and
very few external components. Power supply solution size is
minimized by a tiny 3mmx3mm package and a 2.5MHz
switching frequency, which further reduces the size of external
components.
• Handheld devices
• Point-of-load regulators
Related Literature
For a full list of related documents, visit our website
• ISL9110, ISL9112 product pages
VIN =
1.8V TO 5.5V
6
10
9
8
7
PVIN
95
LX1
L1
2.2µH
LX2
VIN
VOUT
MODE
1
EN
BAT
FB
PG
12
VOUT =
3.3V/1A
C2
10µF
EFFICIENCY (%)
5
C1
10µF
STATUS
OUTPUTS
100
ISL9110IRTNZ
90
VIN = 5V
85
80
VIN = 3V
VIN = 2.5V
75
GND
11
PGND
3
VOUT = 3.3V
70
0.01
0.05
0.25
IOUT (A)
FIGURE 2. EFFICIENCY
FIGURE 1. TYPICAL APPLICATION
FN7649 Rev.3.00
Jul 26, 2018
Page 1 of 21
1.25
ISL9110, ISL9112
Table of Contents
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Analog Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
I2C Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Supply and References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
POR Sequence and Soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short-Circuit Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG Status Output (ISL9110 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BAT Status Output (ISL9110 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ultrasonic Mode (ISL9112 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buck-Boost Conversion Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PFM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation With VIN Close to VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Slew Rate Control (ISL9112 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description (ISL9112) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Serial Interface (ISL9112) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protocol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
12
12
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
14
14
15
16
16
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Programming, Adj. Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feed-Forward Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non-Adjustable Version FB Pin Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PVIN and VOUT Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The TDFN Package Requires Additional PCB Layout Rules for the Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General PowerPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
17
17
17
17
17
17
18
18
18
18
18
19
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FN7649 Rev.3.00
Jul 26, 2018
Page 2 of 21
ISL9110, ISL9112
Block Diagram
LX1
4
5
EN
9
VIN
6
BAT
8
GATE
DRIVERS
AND ANTISHOOT THRU
EN
VREF
THERMAL
SHUTDOWN
MODE/SYNC 10
SCL
7
3
PGND
7
PG
VOUT
CLAMP
PWM
CONTROL
CURRENT
DETECT
EN
2
I C
SDA
VOUT
EN
EN
PVIN
MONITOR
1
SOFT
DISCHARGE
REVERSE
CURRENT
PVIN
LX2
2
8
VOUT
MONITOR
EN
EN
12 FB
EN
OSC
REF
ERROR
AMP
VOLTAGE
PROG.
11
GND
Pin Configurations
ISL9110
(12 LD TDFN)
TOP VIEW
LX2 2
LX1 4
PIN # ISL9110 ISL9112
VOUT
VOUT
2
LX2
LX2
9 EN
3
PGND
PGND
8 BAT
4
LX1
LX1
Inductor connection, input side.
5
PVIN
PVIN
Power input. Range: 1.8V to 5.5V. Connect a
10µF capacitor to PGND.
6
VIN
VIN
Supply input. Range: 1.8V to 5.5V.
7
PG
-
Open-drain output.
Provides output power-good status.
-
SCL
BAT
-
-
SDA
9
EN
EN
10
MODE /
SYNC
11
GND
GND
12
FB
FB
PAD
PAD
PAD
11 GND
ISL9110
PAD
PVIN 5
VIN 6
10 MODE/SYNC
7 PG
ISL9112
(12 LD TDFN)
TOP VIEW
VOUT 1
12 FB
LX2 2
PGND 3
LX1 4
11 GND
ISL9112
PAD
8
10 MODE/SYNC
9 EN
PVIN 5
8 SDA
VIN 6
7 SCL
FN7649 Rev.3.00
Jul 26, 2018
DESCRIPTION
1
12 FB
VOUT 1
PGND 3
Pin Descriptions
Buck/boost output. Connect a 10µF
capacitor to PGND.
Inductor connection, output side.
Power ground for high switching current.
Logic input, I2C clock.
Open drain output.
Provides input-power-good status.
Logic I/O, open drain, I2C data.
Logic input, drive high to enable device.
MODE / Logic input, high for auto PFM mode. Low for
SYNC forced PWM operation.
External clock sync input. Range: 2.75MHz
to 3.25MHz.
Analog ground pin.
Voltage feedback pin.
Exposed pad; connect to PGND.
Page 3 of 21
ISL9110, ISL9112
Ordering Information
PART NUMBER
(Notes 2, 3, 4)
PART
MARKING
VOUT
(V)
HICCUP
MODE
TEMP RANGE
(°C)
TAPE AND REEL
(UNITS) (Note 1)
PKG.
DWG. #
PACKAGE
ISL9110IRTNZ
GASA
3.3
Enabled
-40 to +85
-
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9110IRTNZ-T
GASA
3.3
Enabled
-40 to +85
6k
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9110IRTNZ-T7A
GASA
3.3
Enabled
-40 to +85
250
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9110IRT7Z
GATA
5.0
Enabled
-40 to +85
-
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9110IRT7Z-T
GATA
5.0
Enabled
-40 to +85
6k
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9110IRT7Z-T7A
GATA
5.0
Enabled
-40 to +85
250
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9110IRTAZ
GAUA
ADJ.
Enabled
-40 to +85
-
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9110IRTAZ-T
GAUA
ADJ.
Enabled
-40 to +85
6k
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9110IRTAZ-T7A
GAUA
ADJ.
Enabled
-40 to +85
250
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9112IRTNZ
GAVA
3.3
Enabled
-40 to +85
-
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9112IRTNZ-T
GAVA
3.3
Enabled
-40 to +85
6k
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9112IRTNZ-T7A
GAVA
3.3
Enabled
-40 to +85
250
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9112IRT7Z
GAWA
5.0
Enabled
-40 to +85
-
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9112IRT7Z-T
GAWA
5.0
Enabled
-40 to +85
6k
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9112IRT7Z-T7A
GAWA
5.0
Enabled
-40 to +85
250
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9110BIRTAZ
GBAF
ADJ.
Disabled
-40 to +85
-
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
ISL9110BIRTAZ-T
GBAF
ADJ.
Disabled
-40 to +85
6k
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
NOTES:
1. Refer to TB347 for details about reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see the ISL9110, ISL9112 product information pages. For more information about MSL, see TB363.
4. The ISL9110 and ISL9112 can be special ordered with any output voltage between 1.9V and 5.0V in 100mV steps.
FN7649 Rev.3.00
Jul 26, 2018
Page 4 of 21
ISL9110, ISL9112
Absolute Maximum Ratings
Thermal Information
PVIN, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
LX1, LX2 (Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
FB (Adjustable version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
FB (Fixed VOUT versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
GND, PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 250V
Latch-Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
12 Ld TDFN Package (Notes 5, 6) . . . . . . .
42
5.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.2A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. LX1 and LX2 pins can withstand switching transients of -1.5V for 100ns, and 7V for 20ms.
Analog Specifications
VVIN = VPVIN = VEN = 3.6V, VOUT = 3.3V, L1 = 2.2µH, C1 = C2 = 10µF, TA = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
(Note 8) (Note 9) (Note 8)
UNIT
POWER SUPPLY
Input Voltage Range
VIN Undervoltage Lockout Threshold
VIN
VUVLO
1.8
Rising
Falling
VIN Supply Current
IVIN
PFM mode, no external load on Vout (Note 10)
VIN Supply Current, Shutdown
ISD
EN = GND, VIN = 3.6V
1.725
1.550
5.5
V
1.775
V
1.650
V
35
60
µA
0.05
1.0
µA
OUTPUT VOLTAGE REGULATION
Output Voltage Range
VOUT
Output Voltage Accuracy
ISL9110IRTAZ, IOUT = 100mA
1.00
5.20
V
ISL9112, IOUT = 100mA
1.90
5.00
V
VIN = 3.7V, VOUT = 3.3V, IOUT = 0mA, PWM mode
-2
+2
%
VIN = 3.7V, VOUT = 3.3V, IOUT = 1mA, PFM mode
-3
+4
%
0.81
V
1
µA
FB Pin Voltage Regulation
VFB
For adjustable output version
FB Pin Bias Current
IFB
For adjustable output version
0.79
0.80
Line Regulation, PWM Mode
VOUT / VIN
IOUT = 500mA, VOUT = 3.3V, MODE = GND, VIN step
from 2.3V to 5.5V
±0.005
mV/mV
Load Regulation, PWM Mode
VOUT / IOUT
VIN = 3.7V, VOUT = 3.3V, MODE = GND, IOUT step from
0mA to 500mA
±0.005
mV/mA
Line Regulation, PFM Mode
VOUT / VI
IOUT = 100mA, VOUT = 3.3V, MODE = VIN, VIN step
from 2.3V to 5.5V
±12.5
mV/V
Load Regulation, PFM Mode
VOUT / IOUT
VIN=3.7V, VOUT = 3.3V, MODE = VIN, IOUT step from
0mA to 100mA
±0.4
mV/mA
Output Voltage Clamp
VCLAMP
Output Voltage Clamp Hysteresis
Rising, VIN = 3.6V
5.25
VIN = 3.6V
5.95
400
V
mV
DC/DC SWITCHING SPECIFICATIONS
Oscillator Frequency
FN7649 Rev.3.00
Jul 26, 2018
fSW
2.25
2.50
2.75
MHz
Page 5 of 21
ISL9110, ISL9112
Analog Specifications
VVIN = VPVIN = VEN = 3.6V, VOUT = 3.3V, L1 = 2.2µH, C1 = C2 = 10µF, TA = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
Minimum On Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
(Note 8) (Note 9) (Note 8)
UNIT
80
ns
tONMIN
LX1 Pin Leakage Current
IPFETLEAK
-1
1
µA
LX2 Pin Leakage Current
INFETLEAK
-1
1
µA
SOFT-START and SOFT DISCHARGE
Soft-Start Time
VOUT Soft-Discharge ON-Resistance
tSS
Time from when EN signal asserts to when output
voltage ramp starts.
1
ms
Time from when output voltage ramp starts to when
output voltage reaches 95% of its nominal value
with device operating in Buck mode.
VIN = 4V, VOUT = 3.3V, IO = 200mA
1
ms
Time from when output voltage ramp starts to when
output voltage reaches 95% of its nominal value
with device operating in Boost mode.
VIN = 2V, VOUT = 3.3V, IO = 200mA
2
ms
Ω
RDISCHG
VIN = 3.6V, EN < VIL
120
RDSON_P
VIN = 3.6V, IO = 200mA
0.12
0.17
Ω
VIN = 2.5V, IO = 200mA
0.15
0.23
Ω
VIN = 3.6V, IO = 200mA
0.10
0.15
Ω
VIN = 2.5V, IO = 200mA
0.13
0.23
Ω
2.4
2.8
A
POWER MOSFET
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
P-Channel MOSFET Peak Current Limit
RDSON_N
IPK_LMT
VIN = 3.6V
2.0
PFM/PWM TRANSITION
Load Current Threshold, PFM to PWM
VIN = 3.6V, VOUT = 3.3V
200
mA
Load Current Threshold, PWM to PFM
VIN = 3.6V, VOUT = 3.3V
75
mA
External Synchronization Frequency
Range
2.75
3.25
MHz
Thermal Shutdown
155
°C
Thermal Shutdown Hysteresis
30
°C
BATTERY MONITOR AND POWER GOOD COMPARATORS
Battery Monitor Voltage Threshold
VTBMON
Battery Monitor Voltage Hysteresis
VHBMON
100
mV
tBMON
25
µs
PG Delay Time (Rising)
1
ms
PG Delay Time (Falling)
20
µs
Battery Monitor Debounce Time
Minimum Supply Voltage for Valid PG
Signal
1.85
EN = VIN
2.0
2.15
V
1.2
V
PG Range - Lower (Rising)
PGRNGLR
Percentage of programmed voltage
90
%
PG Range - Lower (Falling)
PGRNGLF
Percentage of programmed voltage
87
%
PG Range - Upper (Rising)
PGRNGUR
Percentage of programmed voltage
112
%
PG Range - Upper (Falling)
PGRNGUF
Percentage of programmed voltage
110
%
Compliance Voltage - PG, BAT
FN7649 Rev.3.00
Jul 26, 2018
VIN = 3.6V, ISINK = 1µ
0.3
Page 6 of 21
V
ISL9110, ISL9112
Analog Specifications
VVIN = VPVIN = VEN = 3.6V, VOUT = 3.3V, L1 = 2.2µH, C1 = C2 = 10µF, TA = +25°C. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
(Note 8) (Note 9) (Note 8)
UNIT
0.05
µA
LOGIC INPUTS
Input Leakage
ILEAK
Input HIGH Voltage
VIH
Input LOW Voltage
VIL
I2C Interface Timing Specification
PARAMETER
SYMBOL
1
V
1.4
0.4
V
For SCL, and SDA pins, unless otherwise noted.
TEST CONDITIONS (Note 11)
MIN
(Note 8)
TYP
MAX
(Note 9) (Note 8)
UNIT
Pin Capacitance
Cpin
15
pF
SCL Frequency
fSCL
400
kHz
Pulse Width Suppression Time at SDA
and SCL Inputs
tsp
Any pulse narrower than the max spec is
suppressed
50
ns
SCL Falling Edge to SDA Output Data Valid
tAA
SCL falling edge crossing VIL, until SDA exits the
VIL to VIH window
900
ns
Time the Bus Must be Free Before the
Start of a New Transmission
tBUF
SDA crossing VIH during a STOP condition, to SDA
crossing VIH during the following START
condition
1300
ns
Clock LOW Time
tLOW
Measured at the VIL crossings
1300
ns
Clock HIGH Time
tHIGH
Measured at the VIH crossings
600
ns
START Condition Set-Up Time
tSU:STA
SCL rising edge to SDA falling edge; both
crossing VIH
600
ns
START Condition Hold Time
tHD:STA
From SDA falling edge crossing VIL to SCL falling
edge crossing VIH
600
ns
Input Data Set-Up Time
tSU:DAT
From SDA exiting the VIL to VIH window, to SCL
rising edge crossing VIL
100
ns
Input Data Hold Time
tHD:DAT
From SCL rising edge crossing VIH to SDA
entering the VIL to VIH window
0
ns
STOP Condition Set-Up Time
tSU:STO
From SCL rising edge crossing VIH, to SDA rising
edge crossing VIL
600
ns
STOP Condition Hold Time for Read, or
Volatile Only Write
tHD:STO
From SDA rising edge to SCL falling edge; both
crossing VIH
1300
ns
0
ns
Output Data Hold Time
tDH
From SCL falling edge crossing VIL, until SDA
enters the VIL to VIH window
SDA and SCL Rise Time
tR
From VIL to VIH
20 + 0.1 x Cb
250
ns
SDA and SCL Fall Time
tF
From VIH to VIL
20 + 0.1 x Cb
250
ns
Capacitive Loading of SDA or SCL
Cb
Total on-chip and off-chip
10
400
pF
SDA and SCL Bus Pull-Up Resistor Off-Chip
Rpu
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2kΩ~2.5kΩ
For Cb = 40pF, max is about 15kΩ~20kΩ
1
kΩ
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Typical values are for TA = +25°C and VIN = 3.6V.
10. Quiescent current measurements are taken when the output is not switching.
11. ISL9112 only. Limits established by characterization and are not production tested.
FN7649 Rev.3.00
Jul 26, 2018
Page 7 of 21
ISL9110, ISL9112
Typical Performance Curves
100
100
VIN = 4V
VIN = 3V
95
VIN = 4.5V
EFFICIENCY (%)
EFFICIENCY (%)
95
90
85
VIN = 2V
80
75
VIN = 5V
90
VIN = 5V
VIN = 4V
85
80
VIN = 2V
VIN = 3V
VIN = 2.5V
75
VIN = 2.5V
VOUT = 2.0V
70
0.01
VIN = 4.5V
0.05
0.25
VOUT = 3.3V
70
0.01
1.25
0.05
FIGURE 3. EFFICIENCY vs OUTPUT CURRENT, VOUT = 2V
100
2.5
VOUT = 2V
2.0
VIN = 4.5V
85
80
IOUT (A)
EFFICIENCY (%)
95
90
VIN = 2V
VIN = 2.5V
VOUT = 4.0V
70
0.01
0.05
0.25
VOUT = 3.3V
1.5
1.0
VOUT = 5V
VIN = 3V
0.5
75
0.0
1.5
1.25
2.0
2.5
FIGURE 5. EFFICIENCY vs OUTPUT CURRENT, VOUT = 4V
4.0
4.5
5.0
5.5
60
QUIESCENT CURRENT (µA)
QUIESCENT CURRENT (mA)
3.5
FIGURE 6. MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE
9
8
+85°C
+25°C
6
5
3.0
VIN (V)
IOUT (A)
7
1.25
FIGURE 4. EFFICIENCY vs OUTPUT CURRENT, VOUT = 3.3V
VIN = 4V
VIN = 5V
0.25
IOUT (A)
IOUT (A)
0°C
-40°C
VOUT = 3.3V
4
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
FIGURE 7. PWM MODE QUIESCENT CURRENT, VOUT = 3.3V,
NO LOAD
FN7649 Rev.3.00
Jul 26, 2018
55
50
+85°C
+25°C
45
40
35
0°C
-40°C
VOUT = 3.3V
30
1.5
2.5
3.5
4.5
VIN (V)
FIGURE 8. PFM MODE QUIESCENT CURRENT, VOUT = 3.3V,
NO LOAD
Page 8 of 21
5.5
ISL9110, ISL9112
Typical Performance Curves
(Continued)
VIN = 4.5V 2.5V
VOUT = 3.3V
IOUT = 500mA
LX1
5V/DIV
VIN = 2.5V 4.5V
VOUT = 3.3V
IOUT = 500mA
LX1
5V/DIV
LX2
5V/DIV
LX2
5V/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
INDUCTOR
CURRENT
0.5A/DIV
INDUCTOR
CURRENT
0.5A/DIV
400µs/DIV
400µs/DIV
FIGURE 9. STEADY STATE TRANSITION FROM BUCK TO BOOST
FIGURE 10. STEADY STATE TRANSITION FROM BOOST TO BUCK
LX1
2V/DIV
VOUT
50mV/DIV
LX2
2V/DIV
VIN
2V/DIV
VOUT
50mV/DIV
INDUCTOR
CURRENT
0.5A/DIV
VIN = 4.5V 2.5V 4.5V
VOUT = 3.3V
IOUT = 400mA
VIN = 3.6V
VOUT = 3.3V
IOUT = 0.6A
50µs/DIV
400ns/DIV
FIGURE 11. STEADY STATE VIN NEAR VOUT
FIGURE 12. INPUT TRANSIENT
LX1
5V/DIV
LX1
5V/DIV
LX2
5V/DIV
LX2
5V/DIV
VOUT
0.1V/DIV
VOUT
0.1V/DIV
INDUCTOR
CURRENT
0.5A/DIV
VIN = 2V
VOUT = 3.3V
IOUT = 0A TO 0.4A
100µs/DIV
FIGURE 13. TRANSIENT LOAD RESPONSE
FN7649 Rev.3.00
Jul 26, 2018
INDUCTOR
CURRENT
0.5A/DIV
VIN = 3.6V
VOUT = 3.3V
IOUT = 0A TO 1A
100µs/DIV
FIGURE 14. TRANSIENT LOAD RESPONSE
Page 9 of 21
ISL9110, ISL9112
Typical Performance Curves
(Continued)
LX1
2V/DIV
LX1
5V/DIV
LX2
2V/DIV
LX2
5V/DIV
VOUT
10mV/DIV
VOUT
10mV/DIV
INDUCTOR
CURRENT
0.5A/DIV
VIN = 2.5V
VOUT = 3.3V
IOUT = 500mA
INDUCTOR
CURRENT
0.5A/DIV
VIN = 4.5V
VOUT = 3.3V
IOUT = 1A
400ns/DIV
400ns/DIV
FIGURE 16. SWITCHING WAVEFORMS, BUCK MODE
0.25
0.25
0.20
0.20
+40°C
0.15
rDS(ON) (Ω)
rDS(ON) (Ω)
FIGURE 15. SWITCHING WAVEFORMS, BOOST MODE
+85°C
0.10
0.00
1.5
2.0
2.5
+85°C
0.15
0.10
-40°C
0°C
-40°C
0.05
+40°C
0.05
0°C
3.0
3.5
4.0
4.5
5.0
0.00
1.5
5.5
2.0
2.5
VIN (V)
0.805
3.285
VOUT (V)
VREF (V)
3.290
0.800
3.275
0.790
-40
I
= 0.4A (PWM)
3.270 OUT
1.5
2.5
40
60
80
TEMPERATURE (°C)
FIGURE 19. VREF vs TEMPERATURE, TA = -40°C TO +85°C
FN7649 Rev.3.00
Jul 26, 2018
4.5
5.0
5.5
100
NO LOAD
(PFM)
IOUT = 0.1A
(PFM)
3.280
0.795
20
4.0
FIGURE 18. PFET RDS(ON) vs INPUT VOLTAGE
0.810
0
3.5
VIN (V)
FIGURE 17. NFET RDS(ON) vs INPUT VOLTAGE
-20
3.0
IOUT = 0.8A (PWM)
IOUT = 1.2A
(PWM)
3.5
4.5
VIN (V)
FIGURE 20. OUTPUT VOLTAGE vs V IN VOLTAGE (VOUT = 3.3V)
Page 10 of 21
5.5
ISL9110, ISL9112
Typical Performance Curves
(Continued)
VIN = 4V
VOUT = 3.3V
LX1 I
= 200mA
2V/DIV OUT
LX1
2V/DIV
LX2
2V/DIV
LX2
2V/DIV
VOUT
2V/DIV
VOUT
2V/DIV
EN
2V/DIV
VIN = 2V
VOUT = 3.3V
IOUT = 200mA
EN
2V/DIV
400µs/DIV
400µs/DIV
FIGURE 21. SOFT-START, VIN = 4V, VOUT = 3.3V
FIGURE 22. SOFT-START, V IN = 2V, VOUT = 3.3V
3.315
3.310
3.310
LOAD CURRENT FALLING
3.300
VOUT (V)
VOUT (V)
3.305
3.305
3.300
3.295
3.285
3.285
3.280
0.0
LOAD CURRENT RISING
3.290
LOAD CURRENT RISING
3.290
3.295
0.1
0.2
0.3
0.4
0.5
LOAD CURRENT FALLING
3.280
0.0
0.1
0.2
IOUT (mA)
0.3
0.4
FIGURE 23. OUTPUT VOLTAGE vs LOAD CURRENT
(VIN = 2.5V, VOUT = 3.3V, AUTO PFM/PWM MODE)
VIN = 3.7V
VOUT = 3.3V
FIGURE 24. OUTPUT VOLTAGE vs LOAD CURRENT
(VIN = 4.5V, VOUT = 3.3V, AUTO PFM/PWM MODE)
SCL
2V/DIV
SDA
2V/DIV
EN
1V/DIV
VOUT
1V/DIV
VOUT
200mV/DIV
4ms/DIV
FIGURE 25. OUTPUT SOFT-DISCHARGE
FN7649 Rev.3.00
Jul 26, 2018
0.5
IOUT (mA)
VIN = 5V
VOUT = 3.0V 4.0V 3.0V
SLEWRATE = 0b111
1ms/DIV
FIGURE 26. DIGITAL SLEW OPERATION (ISL9112)
Page 11 of 21
ISL9110, ISL9112
Functional Description
Functional Overview
Refer to the “Block Diagram” on page 3. The ISL9110 and
ISL9112 implement a complete buck boost switching regulator,
with PWM controller, internal switches, references, protection
circuitry, and control inputs.
The PWM controller automatically switches between Buck and
Boost modes as necessary to maintain a steady output voltage,
with changing input voltages and dynamic external loads.
The ISL9110 provides output power-good and input power-good
open-drain status outputs on Pins 7 and 8. In the ISL9112, these
pins are used for an I2C interface, allowing programmable output
voltage and access to the ultrasonic mode and slew rate limit
control bits.
Internal Supply and References
Referring to the “Block Diagram” on page 3, the ISL9110 and
ISL9112 provide two power input pins. The PVIN pin supplies input
power to the DC/DC converter, while the VIN pin provides operating
voltage source required for stable VREF generation. Separate ground
pins (GND and PGND) are provided to avoid problems caused by
ground shift due to the high switching currents.
Enable Input
A master enable pin EN allows the device to be enabled. Driving
EN low invokes a power-down mode, where most internal device
functions, including input and output power good detection, are
disabled.
Soft Discharge
When the device is disabled by driving EN low, an internal resistor
between VOUT and GND is activated. This internal resistor has
typical 120Ω resistance.
POR Sequence and Soft-Start
Bringing the EN pin high allows the device to power-up. A number
of events occur during the start-up sequence. The internal voltage
reference powers up, and stabilizes. The device then starts
operating. There is a typical 1ms delay between assertion of the
EN pin and the start of switching regulator soft-start ramp.
The soft-start feature minimizes output voltage overshoot and
input inrush currents. During soft-start, the reference voltage is
ramped to provide a ramping VOUT voltage. While output voltage
is lower than approximately 20% of the target output voltage,
switching frequency is reduced to a fraction of the normal
switching frequency to aid in producing low duty cycles necessary
to avoid input inrush current spikes. When the output voltage
exceeds 20% of the target voltage, switching frequency is
increased to its nominal value.
When the target output voltage is higher than the input voltage,
there is a transition from Buck mode to Boost mode during the
soft-start sequence. At the time of this transition, the ramp rate
of the reference voltage is decreased, such that the output
voltage slew rate is decreased. This provides a slower output
voltage slew rate.
FN7649 Rev.3.00
Jul 26, 2018
The VOUT ramp time is not constant for all operating conditions.
Soft-start into Boost mode takes longer than soft-start into Buck
mode. The total soft-start time into Buck mode is typically 2ms,
whereas the typical soft-start time into Boost mode is typically
3ms. Increasing the load current increases these typical
soft-start times.
Overcurrent Protection
When the current in the P-channel MOSFET is sensed to reach
the current limit for 16 consecutive switching cycles, the internal
protection circuit is triggered, and switching is stopped for
approximately 20ms. The device then performs a soft-start cycle.
If the external output overcurrent condition exists after the
soft-start cycle, the device detects 16 consecutive switching
cycles reaching the peak current threshold. The process repeats
as long as the external overcurrent condition is present. This
behavior is called ‘Hiccup mode’.
Short-Circuit Protection
The ISL9110 and ISL9112 provides short-circuit protection by
monitoring the feedback voltage. When feedback voltage is
sensed to be lower than a certain threshold, the PWM oscillator
frequency is reduced in order to protect the device from damage.
The P-channel MOSFET peak current limit remains active during
this state.
Undervoltage Lockout
The Undervoltage Lockout (UVLO) feature prevents abnormal
operation in the event that the supply voltage is too low to ensure
proper operation. When the VIN voltage falls below the UVLO
threshold, the regulator is disabled.
PG Status Output (ISL9110 only)
An open-drain output power-good signal is provided in the
ISL9110. An internal window comparator detects when VOUT is
significantly higher or lower than the target output voltage. The
PG output is driven low when sensed VOUT voltage is outside of
this ‘power-good’ window. When VOUT voltage is inside the
‘power-good’ window, the PG pin goes Hi-Z.
The PG detection circuit detects this condition by monitoring
voltage on the FB pin. Hysteresis is provided for the upper and
lower PG thresholds to avoid oscillation of the PG output.
BAT Status Output (ISL9110 only)
The ISL9110 provides an open-drain input power-good status
output. The BAT status pin is driven low when VIN rises above the
VTBMON threshold. The BAT status output goes Hi-Z when VBAT
falls below the VTBMON threshold. Hysteresis is provided for the
VTBMON threshold to avoid oscillation of the BAT output.
Ultrasonic Mode (ISL9112 only)
The ISL9112 provides an ultrasonic mode that can be enabled
through I2C control by setting the ULTRA bit in the control register.
In ultrasonic mode, the PFM switching frequency is forced to be
above the audio frequency range.
This ultrasonic mode applies only to PFM mode operation. With
the ULTRA bit set to ‘1’, PFM mode switching frequency is forced
well above the audio frequency range (fSW becomes typically
Page 12 of 21
ISL9110, ISL9112
60kHz). This mode of operation, however, reduces the efficiency
at light load.
With Switches B and D closed, output voltage increases as the
inductor current ramps down.
Thermal Shutdown
In most operating conditions, there are multiple PFM pulses to
charge up the output capacitor. These pulses continue until VOUT
has achieved the upper threshold of the PFM hysteretic
controller. Switching then stops, and remains stopped until VOUT
decays to the lower threshold of the hysteretic PFM controller.
A built-in thermal protection feature protects the ISL9110 and
ISL9112 if the die temperature reaches +155°C (typical). At this
die temperature, the regulator is completely shut down. The die
temperature continues to be monitored in this thermal-shutdown
mode. When the die temperature falls to +125°C (typical), the
device resumes normal operation.
When exiting thermal shutdown, the ISL9110 and ISL9112
execute their soft-start sequence.
External Synchronization
Operation With VIN Close to VOUT
When the output voltage is close to the input voltage, the
ISL9110 and ISL9112 rapidly and smoothly switches from Boost
to Buck mode as needed to maintain the regulated output
voltage. This behavior provides excellent efficiency and very low
output voltage ripple.
An external sync feature is provided. Applying a clock signal with
a frequency between 2.75MHz and 3.25MHz at the MODE/SYNC
input forces the ISL9110 and ISL9112 to synchronize to this
external clock. The MODE/SYNC input supports standard logic
levels.
Output Voltage Programming
Buck-Boost Conversion Topology
In the adjustable output voltage version (ISL9110IRTAZ), an
external resistor divider is required to program the output
voltage. The FB pin has very low input leakage current, so it is
possible to use large value resistors (for example, R1 = 1MΩ and
R2 = 324kΩ) in the resistor divider connected to the FB input.
The ISL9110 and ISL9112 operate in either Buck or Boost mode.
When operating in conditions where VIN is close to VOUT, the
ISL9110 alternates between Buck and Boost mode as necessary
to provide a regulated output voltage.
Figure 27 shows a simplified diagram of the internal switches
and external inductor.
L1
LX1
LX2
4
SWITCH A
PVIN
SWITCH D
1
SWITCH B
The ISL9112 is available in a fixed output version only. The
factory programmed output voltage can be changed using the
I2C interface. Details about the ISL9112 programmable VOUT
voltage can be found in “Register Description (ISL9112)” on
page 14.
Digital Slew Rate Control (ISL9112 only)
2
5
The ISL9110 is available in fixed and adjustable output voltage
versions. To use the fixed output version, the VOUT pin must be
connected directly to FB.
VOUT
SWITCH C
FIGURE 27. BUCK BOOST TOPOLOGY
When changing voltages using the I2C interface, the ISL9110 can
be programmed to control the rate of voltage increase or
decrease as it transitions from one voltage setting to the next.
The default configuration disables this digital slew rate feature.
To enable the slew rate feature, an I2C command is sent to the
ISL9112, changing the value of the SLEWRATE bit field to a value
other than 0b000. Details about the digital slew rate settings can
be found in Table 1.
PWM Operation
In buck PWM mode, Switch D is continuously closed, and
Switch C is continuously open. Switches A and B operate as a
synchronous buck converter when in this mode.
TABLE 1. REGISTER ADDRESS 0x01: SLEW RATE CONTROL
BIT
NAME
TYPE
RESET
2:0
SLEWRATE
R/W
000
7:3
Reserved
R/W
00000
In boost PWM mode, Switch A remains closed and Switch B
remains open. Switches C and D operate as a synchronous boost
converter when in this mode.
PFM Operation
During PFM operation in Buck mode, Switch D is continuously
closed, and Switch C is continuously open. Switches A and B
operate in discontinuous mode during PFM operation.
During PFM operation in Boost mode, the ISL9110 and ISL9112
closes Switch A and Switch C to ramp up the current in the
inductor. When inductor current reaches a certain threshold, the
device turns off Switches A and C, then turns on Switches B and D.
FN7649 Rev.3.00
Jul 26, 2018
DESCRIPTION
Slew rate control (typ),
expressed as µs per LSB
change in DCDOUT value:
0b000 = 0µs/LSB
0b001 = 1.5µs/LSB
0b010 = 3.1µs/LSB
0b011 = 6.3µs/LSB
0b100 = 12.5µs/LSB
0b101 = 25µs/LSB
0b110 = 50µs/LSB
0b111 = 100µs /LSB
Page 13 of 21
ISL9110, ISL9112
Register Description (ISL9112)
TABLE 3. DCDOUT[4:0] VALUE vs OUTPUT VOLTAGE (Continued)
The ISL9112 has a two I2C accessible control registers that are
used to set output voltage, operating mode, and digital slew rate.
These registers can be read and written to at any time that the
ISL9112 is enabled. Attempts to communicate with the ISL9112
using its I2C interface when the ISL9112 is disabled (EN = Low)
are not supported.
DCDOUT[4:0]
OUTPUT VOLTAGE
(V)
0b01101
3.2
0b01110
3.3
0b01111
3.4
TABLE 2. REGISTER ADDRESS 0x00: VOLTAGE CONTROL
0b10000
3.5
0b10001
3.6
0b10010
3.7
0b10011
3.8
0b10100
3.9
0b10101
4.0
0b10110
4.1
0b10111
4.2
last programmed DCDOUT and ULTRA
settings; or if no I2C communication has
occurred since POR, the factory
programmed default DCDOUT and ULTRA
settings are used.
1: Device uses the I2C programmed
DCDOUT and ULTRA settings.
0b11000
4.3
0b11001
4.4
0b11010
4.5
0b11011
4.6
0b11100
4.7
Bits DCDOUT[4:0] set the output voltage, as shown in Equation 1
and Table 3. The ISL9112 output voltage range is 1.9V to 5.0V.
0b11101
4.8
0b11110
4.9
(EQ. 1)
0b11111
5.0
BIT
NAME
TYPE RESET
DESCRIPTION
4:0 DCDOUT R/W 00000 VOUT programming. See Table 3.
5
ULTRA
R/W
6 Reserved R/W
7
I2CEN
R/W
0
Ultrasonic mode select. Not applicable in
forced PWM mode:
0: Ultrasonic feature disabled
1: Ultrasonic feature enabled
0
0
I2C programming enable bit:
0: Device ignores I2C command, and uses
V OUT = 1.9V + n 0.1V where n = 0 to 31
The power-up output voltage is at 3.3V for ISL9112IRTNZ and 5V
for ISL9112IRT7Z. To change to other voltages after power-up,
first write the DCDOUT register to match the power-up voltage
while keeping the I2CEN bit = 0, then set the I2CEN bit to 1 and
set the new desired DCDOUT register value.
TABLE 3. DCDOUT[4:0] VALUE vs OUTPUT VOLTAGE
DCDOUT[4:0]
OUTPUT VOLTAGE
(V)
0b00000
1.9
0b00001
2.0
0b00010
2.1
0b00011
2.2
0b00100
2.3
0b00101
2.4
0b00110
2.5
0b00111
2.6
0b01000
2.7
0b01001
2.8
0b01010
2.9
0b01011
3.0
0b01100
3.1
FN7649 Rev.3.00
Jul 26, 2018
I2C Serial Interface (ISL9112)
The ISL9112 supports a bi-directional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL9112 operates as a slave device in all
applications.
All communication over the I2C interface is conducted by sending
the MSB of each byte of data first.
Page 14 of 21
ISL9110, ISL9112
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 28). Upon
power-up of the ISL9112, the SDA pin is in the input mode.
All I2C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
ISL9112 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 28). A START condition is ignored
during the power-up sequence and when EN input is low.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 28). A STOP condition at the end of a write
operation initiates the reconfiguration of the ISL9112’s voltage
feedback loop as necessary to provide the programmed output
voltage.
The ISL9112 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and again after
successful receipt of a Register Address Byte. The ISL9112 also
responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
A valid Identification Byte contains 0b0011100 as the seven
MSBs, corresponding to the ISL9112 I2C Slave Address. The LSB
of the Identification byte is the Read/Write bit. Its value is “1” for
a Read operation, and “0” for a Write operations (see Table 4).
TABLE 4. IDENTIFICATION BYTE FORMAT
0
0
1
1
1
0
(MSB)
0
R/W
(LSB)
An Acknowledge (ACK) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data (see
Figure 29).
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 28. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM
MASTER
1
8
SDA OUTPUT FROM
TRANSMITTER
9
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT
FROM RECEIVER
START
ACK
FIGURE 29. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN7649 Rev.3.00
Jul 26, 2018
Page 15 of 21
ISL9110, ISL9112
Write Operation
transmits the Register Address byte, and the ISL9112 responds
with another ACK.
A Write operation requires a START condition, followed by a valid
Identification Byte (containing the Slave Address with the R/W
bit set to 0), a valid Register Address Byte, a Data Byte, and a
STOP condition. After each of the three bytes, the ISL9112
responds with an ACK. The master then sends a STOP to
complete the command.
The host generates a Repeat START condition, or a STOP
condition followed by a START condition. It then transmits an
Identification byte (containing the Slave Address with the R/W bit
set to 1). The ISL9112 responds with an ACK, indicating it is
ready to begin providing the requested data.
The ISL9112 then transmits the data byte by asserting control of
the SDA pin while the host generates clock pulses on the SCL pin.
When transmission of the data byte is complete, the host
generates a NACK condition followed by a STOP condition. This
completes the I2C Read operation.
STOP conditions that terminate write operations must be sent by
the master after sending at least 1 full data byte and its
associated ACK signal. If a STOP condition is issued in the middle
of a data byte, or before 1 full data byte + ACK is sent, then the
ISL9112 ignores the command, and does not change the output
voltage or other settings.
The ISL9112 register map supports only one register, at register
address 0x00. Attempts to read other register addresses are not
supported, and should not be attempted. Similarly, I2C block reads
and writes are not supported by the ISL9112. The ISL9112 has only
one register to read or write, therefore block reads and writes are
not necessary.
Read Operation
A Read operation is shown in Figure 31. It consists of 4 bytes.
The host generates a START condition, then transmits an
Identification byte (containing the Slave Address with the R/W bit
set to 0). The ISL9112 responds with an ACK. The host then
IS L 9 1 1 2 I 2 C W R IT E P R O T O C O L
1
1
1
0
0
I2C S L A V E
7 -B IT A D D R E S S
0
SYSTEM HOST
A
0
0
R /W
0
0
0
0
0
0
A
R E G IS T E R
A D D R ES S = 0x00
DATA BYTE
WARN
0
A
P
IS L 9 1 1 2
A – ACKNOW LEDGE
N – NOT
ACKNOW LEDGE
S – START
P – STOP
DCDV1
(5 B IT S )
ULTRA
0
I2C_EN
S
FIGURE 30. I2C REGISTER WRITE PROTOCOL
ISL9112 I2 C READ PROTOCOL #1
S
0
0
1
1
1
0
0
0 A
0
0
0
0
0
0
0
0 A
S
0
0
1
1
1
0
0
1 A
DATA BYTE
N
SYSTEM
HOST
P
WARN
R/W
ULTRA
I2 C SLAVE
7-BIT ADDRESS
REGISTER
ADDRESS = 0x00
I2C_EN
ISL9112
R/W
I 2C SLAVE
7-BIT ADDRESS
A – ACKNOWLEDGE
N – NOT
ACKNOWLEDGE
S – START
P – STOP
DCDV1
(5 BITS)
ISL9112 I2 C READ PROTOCOL #2
1
1
1
0
I2 C SLAVE
7-BIT ADDRESS
0
0 A
R/W
0
0
0
0
0
0
0
REGISTER
ADDRESS = 0x00
0 A
P
S
0
0
1
1
1
0
I2 C SLAVE
7-BIT ADDRESS
0
1 A
R/W
DATA BYTE
WARN
0
ULTRA
0
I2C_EN
S
N
P
DCDV1
(5 BITS)
FIGURE 31. I2C REGISTER READ PROTOCOL
FN7649 Rev.3.00
Jul 26, 2018
Page 16 of 21
ISL9110, ISL9112
Applications Information
V IN =
1.8V TO 5.5V
Component Selection
C1
10µF
The ISL9112 and the fixed-output versions of the ISL9110
require only three external power components to implement the
buck boost converter: an inductor, an input capacitor, and an
output capacitor.
C3
0.1µF
2
I C
BUS
ISL9112
5
6
10
9
8
7
PVIN
V IN =
1.8V TO 5.5V
C1
10µF
C3
0.1µF
STATUS
OUTPUTS
ISL9110
5
6
10
9
8
7
PVIN
LX1
VIN
MODE
EN
BAT
PG
LX2
VOUT 1
FB
12
L1
2.2µH
R1
1M
C4
56pF
R2
324k
V OUT =
3.3V/1A
C2
10µF
FB
L1
2.2µH
V OUT =
3.3V/1A
C2
10µF
12
GND PGND
11
3
FIGURE 33. TYPICAL ISL9110IRTNZ APPLICATION
Inductor Selection
Use an inductor with high frequency core material (for example,
ferrite core) to minimize core losses and provide good efficiency.
The inductor must be able to handle the peak switching currents
without saturating.
A 2.2µH inductor with ≥2.4A saturation current rating is
recommended. Select an inductor with low DCR to provide good
efficiency. In applications where radiated noise must be
minimized, a toroidal or shielded inductor can be used.
TABLE 5. INDUCTOR VENDOR INFORMATION
GND PGND
11
LX2
1
VOUT
VIN
MODE
EN
SDA
SCL
The adjustable ISL9110 versions require three additional
components to program the output voltage. Two external
resistors program the output voltage, and a small capacitor is
added to improve stability and response.
An optional input supply filtering capacitor (“C3” in Figure 32)
can be used to reduce the supply noise on the VIN pin, which
provides power to the internal reference. In most applications,
this capacitor is not needed.
LX1
3
MANUFACTURER
FIGURE 32. TYPICAL ISL9110IRTAZ APPLICATION
Output Voltage Programming, Adjustable
Version
SERIES
WEBSITE
Coilcraft
LPS4018
www.coilcraft.com
Murata
LQH44P
www.murata.com
Taiyo Yuden
NRS4018
NRS5012
www.t-yuden.com
Sumida
CDRH3D23/HP
CDRH4D22/HP
www.sumida.com
Setting and controlling the output voltage of the ISL9110IRTAZ
(adjustable output version) can be accomplished by selecting the
external resistor values.
Toko
DEM3518C
www.toko.co.jp
Equation 2 can be used to derive the R1 and R2 resistor values:
PVIN and VOUT Capacitor Selection
R 1
V OUT = 0.8V 1 + -------
R 2
The input and output capacitors should be ceramic X5R type with
low ESL and ESR. The recommended input capacitor value is
10µF. The recommended VOUT capacitor value is 10µF to 22µF.
(EQ. 2)
When designing a PCB, include a GND guard band around the
feedback resistor network to reduce noise and improve accuracy
and stability. Place the resistors R1 and R2 close to the FB pin.
Feed-Forward Capacitor Selection
A small capacitor in parallel with resistor R1 is required to
provide the specified load and line regulation. The suggested
value of this capacitor is 56pF for R1 = 1MΩ. An NPO type
capacitor is recommended.
TABLE 6. CAPACITOR VENDOR INFORMATION
MANUFACTURER
SERIES
WEBSITE
AVX
X5R
www.avx.com
Murata
X5R
www.murata.com
Taiyo Yuden
X5R
www.t-yuden.com
TDK
X5R
www.tdk.com
Non-Adjustable Version FB Pin Connection
The fixed output versions of the ISL9110 and the I2C-adjustable
ISL9112 do not require external resistors or a capacitor on the FB
pin. Simply connect VOUT to FB, as shown in Figure 33.
FN7649 Rev.3.00
Jul 26, 2018
Page 17 of 21
ISL9110, ISL9112
Application Example 1.
Recommended PCB Layout
An application using the fixed-output ISL9110IRTNZ is shown in
Figure 34. This application requires only three external
components.
Correct PCB layout is critical for proper operation of the ISL9110.
Place the input and output capacitors as close to the IC as
possible. Keep the ground connections of the input and output
capacitors as short as possible, and on the component layer to
avoid problems that are caused by high switching currents
flowing through PCB vias.
V IN =
1.8V TO 5.5V
ISL9110IRTNZ
5
C1
10µF
6
10
9
8
7
STATUS
OUTPUTS
PVIN
LX1
VIN
MODE
EN
BAT
PG
GND
11
L1
2.2µH
LX2
1
VOUT
FB
V OUT =
3.3V/1A
C2
10µF
12
PGND
3
FIGURE 34. TYPICAL ISL9110IRTNZ APPLICATION
Application Example 2.
An application requiring VOUT = 3.0V, using the adjustable-output
ISL9110IRTAZ is shown in Figure 35. This application requires six
external components.
VIN =
1.8V TO 5.5V
C1
10µF
STATUS
OUTPUTS
ISL9110IRTAZ
5 PVIN
6
10
9
8
7
LX1
L1
2.2µH
LX2
1
VOUT
VIN
MODE
EN
BAT
PG
FB
R1
1M
12
R2
365k
GND PGND
11
C4
56pF
VOUT =
3.0V/1A
C2
10µF
The TDFN Package Requires Additional PCB
Layout Rules for the Thermal Pad
3
FIGURE 35. TYPICAL ISL9110IRTAZ APPLICATION
Application Example 3.
An application requiring VOUT = 3.3V, using the I2C-controllable
ISL9112IRTNZ is shown in Figure 36. This application requires
three external components. Output voltage can be changed using
I2C control.
VIN =
1.8V TO 5.5V
C1
10µF
I2C
BUS
ISL9112IRTNZ
5 PVIN
6
10
9
8
7
VIN
MODE
EN
SDA
SCL
LX1
LX2
1
VOUT
FB
12
FIGURE 37. RECOMMENDED PCB LAYOUT
L1
2.2µH
VOUT =
3.3V/1A
The thermal pad is electrically connected to the PGND supply. Its
primary function is to provide heat sinking for the IC. However,
because of the connection to PGND, the thermal pad must be
tied to the GND supply to prevent unwanted current flow to the
thermal pad. Maximum AC performance is achieved if the
thermal pad is attached to a dedicated ground layer in a
multi-layered PC board.
The thermal pad requirements are proportional to power
dissipation and ambient temperature. A dedicated layer
eliminates the need for individual thermal pad area. When a
dedicated layer is not possible, an isolated thermal pad on
another layer should be used. Pad area requirements should be
evaluated on a case by case basis.
C2
10µF
GND PGND
11 3
FIGURE 36. TYPICAL ISL9112IRTNZ APPLICATION
FN7649 Rev.3.00
Jul 26, 2018
Page 18 of 21
ISL9110, ISL9112
General PowerPAD Design Considerations
The following is an example of how to use vias to remove heat
from the IC.
Renesas recommends that the thermal pad area is filled with
vias. Fill the thermal pad area with vias that are spaced three
times their radius (typically), center-to-center, from each other.
Keep the vias small but not so small that their inside diameter
prevents solder wicking through the holes during reflow.
It is important that the vias have a low thermal resistance for
efficient heat transfer. Do not use “thermal relief” patterns to
connect the vias to the ground plane. Instead use a solid
connection with no gaps for improved thermal performance.
FIGURE 38. PCB VIA PATTERN
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure
you have the latest revision.
DATE
REVISION
CHANGE
Aug 3, 2018
FN7649.3
Updated Related Literature section.
Moved TOC to page 2.
Updated Ordering information table by adding tape and reel parts, adding unit column, removing evaluation
board part numbers, and updating Note 1.
In “Register Description (ISL9112)” on page 14 updated paragraph under Equation 1.
Removed Products section.
Updated POD L12.3x3C to the latest revision changes are as follows:
Tiebar Note updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
Updated Disclaimer.
Jul 13, 2012
FN7649.2
Corrected Application Note titles in “” on page 1.
On page 3, pin configuration diagrams, changed "MODE" to "MODE/SYNC".
On page 4, added ISL9110BIRTAZ to ordering table.
On page 4, added "Hiccup Mode" column in ordering table.
On page 4, corrected Evaluation Board numbers.
On page 13, corrected "EN/SYNC", to "MODE/SYNC" in “External Synchronization”
August 30, 2011
FN7649.1
Page 4:
Removed "ISL9110EVAL1Z" from “Ordering Information” table
Added "ISL9110IRTAZ-EVAL1Z" to “Ordering Information” table
Added "ISL9110IRTNZ-EVAL1Z" to “Ordering Information” table
Added "ISL9110IRT7Z-EVAL1Z" to “Ordering Information” table
Added "ISL9112IRT7Z-EVAL1Z" to “Ordering Information” table
“Inductor Selection” on page 17:
Corrected "A 10µH inductor.." to "A 2.2µH inductor.."
June 16, 2011
FN7649 Rev.3.00
Jul 26, 2018
FN7649.0
Initial release.
Page 19 of 21
ISL9110, ISL9112
Package Outline Drawing
For the most recent package outline drawing, see L12.3x3C.
L12.3x3C
12 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (0.4mm PITCH)
Rev 1, 4/15
3.00
6
PIN #1
INDEX AREA
A
B
6
PIN 1
INDEX AREA
3.00
0.40
(4X)
2.45±0.1
0.15
12x 0.20
0.10 M C A B
4 0.20 ±0.05
1.70±0.1
TOP VIEW
12x 0.40
BOTTOM VIEW
PACKAGE
OUTLINE
SEE DETAIL "X"
0.10 C C
BASE PLANE
SEATING PLANE
0.08 C
0 . 75
(12 x0.20)
SIDE VIEW
2.45
(10 x0.40)
C
1.70
(12 x0.20)
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
(12 x0.40)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
FN7649 Rev.3.00
Jul 26, 2018
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
Page 20 of 21
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by
you or third parties arising from the use of these circuits, software, or information.
2.
Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or
arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application
examples.
3.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.
4.
You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by
5.
Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the
you or third parties arising from such alteration, modification, copying or reverse engineering.
product’s quality grade, as indicated below.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; industrial robots; etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control (traffic lights); large-scale communication equipment; key financial terminal systems; safety control equipment; etc.
Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are
not intended or authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems; surgical implantations; etc.), or may cause
serious property damage (space system; undersea repeaters; nuclear power control systems; aircraft control systems; key plant systems; military equipment; etc.). Renesas Electronics disclaims any and all
liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or
other Renesas Electronics document.
6.
When using Renesas Electronics products, refer to the latest product information (data sheets, user’s manuals, application notes, “General Notes for Handling and Using Semiconductor Devices” in the
reliability handbook, etc.), and ensure that usage conditions are within the ranges specified by Renesas Electronics with respect to maximum ratings, operating power supply voltage range, heat dissipation
characteristics, installation, etc. Renesas Electronics disclaims any and all liability for any malfunctions, failure or accident arising out of the use of Renesas Electronics products outside of such specified
ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Electronics products, semiconductor products have specific characteristics, such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Unless designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas
Electronics document, Renesas Electronics products are not subject to radiation resistance design. You are responsible for implementing safety measures to guard against the possibility of bodily injury, injury
or damage caused by fire, and/or danger to the public in the event of a failure or malfunction of Renesas Electronics products, such as safety design for hardware and software, including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult
and impractical, you are responsible for evaluating the safety of the final products or systems manufactured by you.
8.
Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. You are responsible for carefully and
sufficiently investigating applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive, and using Renesas Electronics
products in compliance with all these applicable laws and regulations. Renesas Electronics disclaims any and all liability for damages or losses occurring as a result of your noncompliance with applicable
laws and regulations.
9.
Renesas Electronics products and technologies shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations. You shall comply with any applicable export control laws and regulations promulgated and administered by the governments of any countries asserting jurisdiction over the parties or
transactions.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, or any other party who distributes, disposes of, or otherwise sells or transfers the product to a third party, to notify such third
party in advance of the contents and conditions set forth in this document.
11. This document shall not be reprinted, reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products.
(Note 1)
“Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries.
(Note 2)
“Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(Rev.4.0-1 November 2017)
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