ISL9209CIRZ-T

DATASHEET ISL9209C FN6489 Rev 1.00 January 16, 2009 Charging System Safety Circuit The ISL9209C is an integrated circuit (IC) optimized to provide a redundant safety protection to a Li-ion battery from failures of a charging system. The IC monitors the input voltage, the battery voltage, and the charge current. When any of the three parameters exceeds its limit, the IC turns off an internal P-Channel MOSFET to remove the power from the charging system. In addition to the above protected parameters, the IC also monitors its own internal temperature and turns off the P-Channel MOSFET when the temperature exceeds +140°C. Together with the battery charger IC and the protection module in a battery pack, the charging system using the ISL9209C has triple-level protection and is two-fault tolerant. Features The IC is designed to turn on the internal PFET slowly to avoid in-rush current at power-up but will turn off the PFET quickly when the input is overvoltage in order to remove the power before any damage occurs. The ISL9209C has a logic warning output to indicate the fault and an enable input to allow the system to remove the input power. • Thermal Enhanced TDFN Package ISL9209CIRZ* 09CZ -40 to +85 PACKAGE (Pb-free) PKG. DWG. # 12 Ld 4x3 TDFN L12.4x3A NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Typical Application Circuit VIN OUT C1 GND FN6489 Rev 1.00 January 16, 2009 • High Immunity of False Triggering Under Transients • Warning Output to Indicate the Occurrence of Faults • Enable Input • Easy to Use • Pb-Free (RoHS Compliant) Applications • Cell Phones WRN • Portable Instruments • Desktop Chargers Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Technical Brief TB379 “Thermal Characterization of Packaged Semiconductor Devices” • Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN Packages” ISL9209C (12 LD 4x3 TDFN) TOP VIEW ISL6292 BATTERY CHARGER VB EN RILIM • Input Overvoltage Protection in Less Than 1µs Pinout ISL9209C ILIM • User Programmable Overcurrent Protection Threshold • PDAs and Smart Phones TEMP. RANGE (°C) *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications INPUT • High Accuracy Protection Thresholds • Digital Still Cameras Ordering Information PART NUMBER PART (Note) MARKING • Fully Integrated Protection Circuit for Three Protected Variables RVB BATTERY PACK VIN 1 12 NC VIN 2 11 OUT GND 3 10 OUT WRN 4 9 ILIM NC 5 8 VB NC 6 7 EN EPAD Page 1 of 11 ISL9209C ISL9209C Absolute Maximum Ratings (Reference to GND) Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 30V Output and VB Pin (OUT, VB) (Note 1) . . . . . . . . . . . . -0.3V to 7.0V Other Pins (ILIM, WRN, EN) . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V Thermal Resistance (Typical, Notes 2, 3) JA (°C/W) JC (°C/W) 4x3 TDFN Package . . . . . . . . . . . . . . . 41 3.5 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3V to 5.5V Operating Current Range. . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. The maximum voltage rating for the VB pin under continuous operating conditions is 5.5V. All other pins are allowed to operate continuously at the absolute maximum ratings. 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 3. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Typical values are tested at VIN = 5.0V and TA = +25°C, maximum and minimum values are guaranteed over the recommended operating conditions, unless otherwise noted. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 2.40 2.58 2.70 V POWER-ON RESET Rising VIN Threshold VPOR POR Hysteresis - 0.10 - V When Enabled 0.75 0.90 1.10 mA When Disabled 30 60 100 µA 5.65 5.85 6.00 V - 0.06 0.10 V Input OVP Falling Threshold 5.55 - - V Input OVP Propagation Delay - - 1 µs VIN Bias Current IVIN VIN Bias Current PROTECTIONS Input Overvoltage Protection (OVP) VOVP Input OVP Hysteresis 0.93 1.00 1.07 A Overcurrent Protection Blanking Time BtOCP - 170 - µs Battery Overvoltage Protection Threshold VBOVP 4.280 4.340 4.400 V - 0.030 - V 4.225 - - V - 180 - µs Overcurrent Protection IOCP VVB = 3V, RILIM = 25k Battery OVP Threshold Hysteresis Battery OVP Falling Threshold Battery OVP Blanking Time BtBOVP - - 20 nA Over-Temperature Protection Rising Threshold VVB = 4.4V - 140 - °C Over-Temperature Protection Falling Threshold - 90 - °C EN Input Logic HIGH 1.5 - - V EN Input Logic LOW - - 0.4 V k VB Pin Leakage Current LOGIC EN Internal Pull-Down Resistor WRN Output Logic Low Sink 5mA current WRN Output Logic High Leakage Current 100 200 400 - 0.35 0.80 V - - 1 µA - 170 280 m POWER MOSFET ON-Resistance FN6489 Rev 1.00 January 16, 2009 rDS(ON) 4.6V < VIN < 5.5V Page 2 of 11 ISL9209C ISL9209C Pin Descriptions VB (Pin 8) VIN (Pin 1, 2) Battery voltage monitoring input. This pin is connected to the battery pack positive terminal via an isolation resistor. The input power source. The VIN can withstand 30V input. ILIM (Pin 9) GND (Pin 3) Overcurrent protection threshold setting pin. Connect a resistor between this pin and GND to set the OCP threshold. System ground reference. WRN (Pin 4) OUT (Pin 10, 11) WRN is an open-drain logic output that turns LOW when any protection event occurs. Output pin. EPAD NC (Pin 5, 6, 12) The exposed pad at the bottom of the TDFN package for enhancing thermal performance. Must be electrically connected to the GND pin. No connection and must be left floating. EN (Pin 7) Enable input. Pull this pin to low or leave it floating to enable the IC and force it to high to disable the IC. Typical Applications INPUT VIN ISL6292 BATTERY CHARGER OUT C1 PART ISL9209C VB ILIM RVB EN RILIM RILIM 25k RVB 200k to 1M C1 1µF/16V X5R ceramic capacitor BATTERY PACK WRN GND DESCRIPTION Block Diagram INPUT OUT VIN Q1 Q2 R1 POR PRE-REG Pre-reg REF Ref FET DRIVER Driver RILIM CP2 EA CP3 Logic LOGIC 1.2V VB Q4 R4 Q5 WRN ILIM 0.8V CP1 R2 Q3 GND ISL6292 Battery BATTERY CHARGER Charger RVB R3 BUF R5 EN FIGURE 1. BLOCK DIAGRAM FN6489 Rev 1.00 January 16, 2009 Page 3 of 11 ISL9209C ISL9209C Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = +25°C, RILIM = 25.5k, RVB = 200k, Unless Otherwise Noted. VIN VIN(2V/DIV) (2V/div) VIN (1V/DIV) VIN (1V/div) OUT (1V/DIV) OUT (1V/div) Load LOADCurrent CURRENT 200mA/DIV (200mA/div) OUT OUT(2V/DIV) (2V/div) WRN WRN(5V/DIV) (5V/div) TIME: Time:5µs/DIV 5s/div TIME: Time:5ms/DIV 5ms/div FIGURE 2. CAPTURED WAVEFORMS FOR POWER-UP. THE OUTPUT IS LOADED WITH A 10 RESISTOR Time:500ms/DIV 500ms/div TIME: FIGURE 3. CAPTURED WAVEFORMS WHEN THE INPUT VOLTAGE STEPS FROM 5.5V TO 9.5V VIN(2V/DIV) (2V/div) VIN VIN (2V/DIV) VIN (2V/div) OUT (2V/div) OUT (2V/DIV) OUT (2V/DIV) OUT (2V/div) WRN (5V/DIV) WRN (5V/div) WRN (5V/div) WRN (5V/DIV) FIGURE 4. CAPTURED WAVEFORMS WHEN THE INPUT GRADUALLY RISES TO THE INPUT OVERVOLTAGE THRESHOLD VIN(2V/DIV) (2V/div) VIN Time: 5ms/div TIME: 5ms/DIV FIGURE 5. TRANSIENT WHEN THE INPUT VOLTAGE STEPS FROM 6.5V TO 5.5V Time:20s/DIV 20s/div TIME: VIN (1V/div) (1V/DIV) VIN VB(1V/DIV) (1V/div) VB OUT OUT(2V/DIV) (2V/div) ILIM ILIM(1V/DIV) (1V/div) OUT (1V/DIV) OUT (1V/div) WRN (5V/div) WRN (5V/DIV) WRN (5V/DIV) Time:500µs/DIV 500s/div WRN (5V/div) TIME: FIGURE 6. TRANSIENT WAVEFORMS WHEN INPUT STEPS FROM 0V TO 9V FN6489 Rev 1.00 January 16, 2009 FIGURE 7. BATTERY OVERVOLTAGE PROTECTION. THE IC IS LATCHED OFF AFTER 16 COUNTS OF PROTECTION. VB VOLTAGE VARIES BETWEEN 4.3V TO 4.5V Page 4 of 11 ISL9209C ISL9209C Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = +25°C, RILIM = 25.5k, RVB = 200k, Unless Otherwise Noted. (Continued) TIME: 200ms/DIV Time: 200ms/div Time:10ms/DIV 10ms/div TIME: VIN(1V/DIV) (1V/div) VIN VIN (1V/div) VIN (1V/DIV) OUT (1V/DIV) OUT (1V/div) LoadCURRENT Current LOAD (500mA/div) 500mA/DIV Load CURRENT Current LOAD (500mA/div) 500mA/DIV OUT OUT (1V/DIV) (1V/div) WRN (5V/DIV) WRN (5V/div) WRN (5V/DIV) WRN (5V/div) FIGURE 9. ZOOMED-IN VIEW OF FIGURE 8 (BLUE: LOAD CURRENT; PINK: OUT PIN VOLTAGE) 1000 1000 900 900 800 800 700 ENABLED CURRENT (µA) INPUT BIAS CURRENT (µA) FIGURE 8. POWER-UP WAVEFORMS WHEN OUTPUT IS SHORT-CIRCUITED 600 500 400 DISABLED 300 700 600 400 300 200 100 100 0 5 10 15 20 25 30 0 -50 35 30V/ENABLED 500 200 0 4.3V/ENABLED 5V/ENABLED 30V/DISABLED 5V/DISABLED -20 INPUT VOLTAGE (V) 40 70 100 130 TEMPERATURE (°C) FIGURE 10. INPUT BIAS CURRENT vs INPUT VOLTAGE WHEN ENABLED AND DISABLED FIGURE 11. INPUT BIAS CURRENT AT DIFFERENT INPUT VOLTAGES WHEN ENABLED AND DISABLED 2.82 5.86 2.80 5.84 2.78 RISING THRESHOLD 2.76 5.82 2.74 VOVP (V) VPOR (V) 10 4.3V/DISABLED 2.72 2.70 2.68 RISING THRESHOLD 5.80 5.78 FALLING THRESHOLD 5.76 FALLING THRESHOLD 2.66 5.74 2.64 2.62 -50 -20 10 40 70 100 TEMPERATURE (°C) FIGURE 12. VPOR vs TEMPERATURE FN6489 Rev 1.00 January 16, 2009 130 5.72 -50 -20 10 40 70 100 130 TEMPERATURE (°C) FIGURE 13. INPUT OVERVOLTAGE PROTECTION THRESHOLDS vs TEMPERATURE Page 5 of 11 ISL9209C ISL9209C Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = +25°C, RILIM = 25.5k, RVB = 200k, Unless Otherwise Noted. (Continued) 200 1040 CURRENT LIMIT = 1A 1030 195 5V 190 185 4.3V 1010 BtOCP (µs) IOCP (mA) 1020 3V 1000 990 180 175 170 165 160 5.5V 980 155 970 -50 -20 10 40 70 100 150 -50 130 -20 TEMPERATURE (°C) FIGURE 14. OVERCURRENT PROTECTION THRESHOLDS vs TEMPERATURE AT VARIOUS INPUT VOLTAGES 510 100 130 4.370 4.3V RISING MAX 4.360 3V 4.350 505 4.340 5V VB IOCP (mA) 70 4.380 CURRENT 515 LIMIT = 0.5A 495 4.330 4.320 490 5.5V 4.310 485 4.300 480 4.290 475 -50 -20 10 40 70 100 FALLING MIN 4.280 130 -60 -40 -20 TEMPERATURE (°C) FIGURE 16. OVERCURRENT PROTECTION THRESHOLDS vs TEMPERATURE AT VARIOUS INPUT VOLTAGES 100 120 140 3.0 VB PIN LEAKAGE CURRENT (nA) 195 190 185 180 175 170 165 160 155 150 -50 0 20 40 60 80 TEMPERATURE (°C) FIGURE 17. BATTERY VOLTAGE OVP THRESHOLDS vs TEMPERATURE AT VARIOUS INPUT VOLTAGES 200 BtBOVP (µs) 40 FIGURE 15. OVERCURRENT PROTECTION BLANKING TIME vs TEMPERATURE 520 500 10 TEMPERATURE (°C) -20 10 40 70 100 TEMPERATURE (°C) FIGURE 18. BATTERY OVP BLANKING TIME FN6489 Rev 1.00 January 16, 2009 130 TESTED AT 5V 2.5 2.0 1.5 1.0 0.5 0 -50 -20 10 40 70 TEMPERATURE (°C) 100 130 FIGURE 19. VB PIN LEAKAGE CURRENT vs TEMPERATURE Page 6 of 11 ISL9209C ISL9209C Typical Operating Performance The test conditions for the Typical Operating Performance are: VIN = 5V, TA = +25°C, RILIM = 25.5k, RVB = 200k, Unless Otherwise Noted. (Continued) 2.0 EN PIN INTERNAL PULL-DOWN (k) 250 1.8 EN THRESHOLD (V) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -20 10 40 70 100 240 230 220 210 200 190 180 170 160 150 130 -50 -20 10 40 70 100 130 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 20. EN INPUT THRESHOLD vs TEMPERATURE FIGURE 21. EN PIN INTERNAL PULL-DOWN RESISTANCE 0.5 rDS(ON) () 0.4 3V 4.3V 0.3 0.2 5V 0.1 5.5V 0 -50 -20 10 40 70 100 130 TEMPERATURE (°C) FIGURE 22. ON-RESISTANCE vs TEMPERATURE AT DIFFERENT INPUT VOLTAGES Theory of Operation Power-up The ISL9209C is an integrated circuit (IC) optimized to provide a redundant safety protection to a Li-ion battery from charging system failures. The IC monitors the input voltage, the battery voltage, and the charge current. When any of the above three parameters exceeds its limit, the IC turns off an internal P-Channel MOSFET to remove the power from the charging system. In addition to the above protected parameters, the IC also monitors its own internal temperature and turns off the P-Channel MOSFET when the temperature exceeds +140°C. Together with the battery charger IC and the protection module in a battery pack, the charging system has triple-level protection from overcharging the Li-ion battery and is two-fault tolerant. The ISL9209C protects up to 30V input voltage. The ISL9209C has a power-on reset (POR) threshold of 2.6V with a built-in hysteresis of 125mV. Before the input voltage reaches the POR threshold, the internal power PFET is off. Approximately 10ms after the input voltage exceeds the POR threshold, the IC resets itself and begins the softstart. The 10ms delay allows any transients at the input during a hot insertion of the power supply to settle down before the IC starts to operate. The soft-start slowly turns on the power PFET to reduce the in-rush current as well as the input voltage drop during the transition. The power-up behavior is illustrated in Figure 2. FN6489 Rev 1.00 January 16, 2009 Input Overvoltage Protection (OVP) The input voltage is monitored by the comparator CP1 in the “Block Diagram” on page 3 (Figure 1). CP1 has an accurate reference of 1.2V from the bandgap reference. The OVP threshold is set by the resistive divider consisting of R1 and R2. The protection threshold is set to 5.85V. When the input Page 7 of 11 ISL9209C ISL9209C voltage exceeds the threshold, the CP1 outputs a logic signal to turn off the power PFET within 1µs (see Figure 3) to prevent the high input voltage from damaging the electronics in the handheld system. The hysteresis for the input OVP threshold is given in the “Electrical Specifications” table on page 2. When the input overvoltage condition is removed, the ISL9209C re-enables the output by running through the soft-start, as shown in Figure 5. Because of the 10ms delay before the soft-start, the output is never enabled if the input rises above the OVP threshold quickly, as shown in Figure 6. the enable pin is toggled. Figure 8 and Figure 9 illustrate the waveforms during the power-up when the output is short-circuited to ground. Battery Overvoltage Protection External Enable Control The battery voltage OVP is realized with the VB pin. The comparator CP3, as shown in Figure 1, monitors the VB pin and issues an overvoltage signal when the battery voltage exceeds the 4.34V (nominal) battery OVP threshold. The threshold has 30mV built-in hysteresis. The comparator CP3 has a built-in 180µs blanking time to prevent any transient voltage from triggering the OVP. If the OVP situation still exists after the blanking time, the power PFET is turned off. The control logic contains a 4-bit binary counter that if the battery overvoltage event occurs 16 times, the power PFET is turned off permanently, as shown in Figure 7. Recycling the input power or toggling the enable (EN) input will reset the counter and restart the ISL9209C. The ISL9209C offers an enable (EN) input. When the EN pin is pulled to logic HIGH, the protection IC is shut down. The internal control circuit as well as the power PFET are turned off. Both 4-bit binary counters for the battery OVP and the OCP are reset to zero when the IC is re-enabled. The EN pin has an internal 200k pull-down resistor. Leaving the EN pin floating or driving it to below 0.4V enables the IC. The resistor between the VB pin and the battery (RVB) as shown in the “Typical Application Circuit” on page 1, is an important component. This resistor provides a current limit in case the VB pin is shorted to the input voltage under a failure mode. The VB pin leakage current under normal operation is negligible to allow a resistance of 200k to 1M be used. Applications Information Overcurrent Protection (OCP) The current in the power PFET is limited to prevent charging the battery with an excessive current. The current is sensed using the voltage drop across the power FET after the FET is turned on. The reference of the OCP is generated using a sensing FET (Q2), as shown in Figure 1. The current in the sensing FET is forced to the value programmed by the ILIM pin. The size of the power FET (Q1) is 31,250 times the size of the sensing FET. Therefore, when the current in the power FET is 31,250 times the current in the sensing FET, the drain voltage of the power FET falls below that of the sensing FET. The comparator CP2 then outputs a signal to turn off the power FET. The OCP threshold can be calculated using Equation 1: 0.8V 25000 I LIM = ---------------  31250 = ---------------R ILIM R ILIM (EQ. 1) where the 0.8V is the regulated voltage at the ILIM pin. The OCP comparator CP2 has a built-in 170µs delay to prevent false triggering by transient signals. The OCP function also has a 4-bit binary counter that accumulates during an OCP event. When the total count reaches 16, the power PFET is turned off permanently, unless the input power is recycled or FN6489 Rev 1.00 January 16, 2009 Internal Over-Temperature Protection The ISL9209C monitors its own internal temperature to prevent thermal failures. When the internal temperature reaches +140°C, the IC turns off the P-Channel power MOSFET. The IC does not resume operation until the internal temperature drops below +90°C. Warning Indication Output The WRN pin is an open-drain output that indicates a LOW signal when any of the three protection events happens. This allows the microprocessor to give an indication to the user to further enhance the safety of the charging system. The ISL9209C is designed to meet the “Lithium-Safe” criteria when operating together with the ISL6292 family Li-ion battery chargers. The “Lithium-Safe” criteria requires the charger output to fall within the green region shown in Figure 23 under normal operating conditions and NOT to fall in the red region when there is a single fault in the charging system. Taking into account the safety circuit in a Li-ion battery pack, the charging system is allowed to have two faults without creating hazardous conditions for the battery cell. The output of any ISL6292 family chargers, such as the ISL6292C, has a typical I-V curve shown with the blue lines under normal operation, which is within the green region. The function of the ISL9209C is to add a redundant protection layer such that, under any single fault condition, the charging system output does not exceed the I-V limits shown with the red lines. As a result, the charging system adopting the ISL9209C and the ISL6292C chip set can easily pass the “Lithium-Safe” criteria test procedures. The ISL9209C is a simple device that requires only three external components, in addition to the ISL6292 charger circuit, to meet the “Lithium-Safe” criteria, as shown in the “Typical Application Circuit” on page 1. The selection of the current limit resistor RILIM is given in “Overcurrent Protection (OCP)” on page 8. Page 8 of 11 ISL9209C ISL9209C RVB Selection The RVB prevents a large current from the VB pin to the battery terminal, in case the ISL9209C fails. The recommended value should be between 200k to 1M. With 200k resistance, the worst case current flowing from the VB pin to the charger output is: ISL9209C MCU VIO RPU WRN Q4 RWRN  30V – 4.2V    200k = 130A  (EQ. 2) assuming the VB pin voltage is 30V under a failure mode and the battery voltage is 4.2V. Such a small current can be easily absorbed by the bias current of other components in the handheld system. Increasing the RVB value reduces the worst case current, but at the same time increases the error for the 4.34V battery OVP threshold. The error of the battery OVP threshold is the original accuracy at the VB pin given in the “Electrical Specifications” table on page 2 plus the voltage built across the RVB by the VB pin leakage current. The VB pin leakage current is less than 20nA, as given in the Electrical Specifications table. With the 200k resistor, the worst-case additional error is 4mV and with a 1M resistor, the worst-case additional error is 20mV. 1000 CHARGE CURRENT (mA) ISL9209 C LIMITS ISL6292C LIMITS EN Q5 REN R5 FIGURE 24. DIGITAL SIGNAL INTERFACE BETWEEN ISL9209C AND MCU Capacitor Selection The input capacitor (C1 in the “Typical Application Circuit” on page 1) is for decoupling. Higher value reduces the voltage drop or the overshoot during transients. Two scenarios can cause the input voltage overshoot. The first one is when the AC adapter is inserted live (hot insertion) and the second one is when the current in the power PFET of the ISL9209C has a step-down change. Figure 25 shows an equivalent circuit for the ISL9209C input. The cable between the AC/DC converter output and the handheld system input has a parasitic inductor. The parasitic resistor is the lumped sum of various components, such as the cable, the adapter output capacitor ESR, the connector contact resistance, and so on. C1 L R AC/DC 0 1 2 3 4 5 ISL9209C 6 BATTERY VOLTAGE (V) FIGURE 23. LITHIUM-SAFE OPERATING REGIONS Interfacing to MCU The ISL9209C has the enable (EN) and the warning (WRN) digital signals that can be interfaced to a microcontroller unit (MCU). Both signals can be left floating if not used. When interfacing to an MCU, it is highly recommended to insert a resistor between the ISL9209C signal pin and the MCU GPIO pin, as shown in Figure 24. The resistor creates an isolation to limit the current, in case a high voltage shows up at the ISL9209C pins under a failure mode. The recommended resistance ranges from 10k to 100k. The selection of the REN is dependent on the IO voltage (VIO) of the MCU. REN should be selected so that the ISL9209C EN pin voltage is above the disable threshold when the GPIO output of the MCU is high. FN6489 Rev 1.00 January 16, 2009 C2 ADAPTER CABLE HANDHELD SYSTEM FIGURE 25. EQUIVALENT CIRCUIT FOR THE ISL9209C INPUT During the load current step-down transient, the energy stored in the parasitic inductor is used to charge the input decoupling capacitor C2. The ISL9209C is designed to turn off the power PFET slowly during the OCP, the battery OVP event, and when the device is disabled via the EN pin. Because of such design, the input overshoot during those events is not significant. During an input OVP, however, the PFET is turned in less than 1µs and can lead to significant overshoot. Higher capacitance reduces this type of overshoot. The overshoot caused by a hot insertion is not very dependent on the decoupling capacitance value. Especially when ceramic type capacitors are used for decoupling. In theory, the overshoot can rise up to twice of the DC output Page 9 of 11 ISL9209C voltage of the AC adapter. The actual peak voltage is dependent on the damping factor that is mainly determined by the parasitic resistance (R in Figure 25). In practice, the input decoupling capacitor is recommended to use a 16V X5R dielectric ceramic capacitor with a value between 0.1µF to 1µF. The output of the ISL9209C and the input of the charging circuit typically share one decoupling capacitor. The selection of that capacitor is mainly determined by the requirement of the charging circuit. When using the ISL6292 family chargers, a 1µF, 6.3V, X5R capacitor is recommended. Layout Recommendation The ISL9209C uses a thermally enhanced DFN package. The exposed pad under the package should be connected to the ground plane electrically as well as thermally. A grid of 1.0mm to 1.2mm pitch thermal vias in two rows and 4 to 5 vias per row is recommended (refer to the ISL9200EVAL1 evaluation board layout). The vias should be about 0.3mm to 0.33mm in diameter. Use some copper on the component layer if possible to further improve the thermal performance but it is not mandatory. Since the ISL9209C is a protection device, the layout should also pay attention to the spacing between tracks. When the distance between the edges of two tracks is less than 0.76mm, an FMEA (failure mechanism and effect analysis) should be performed to ensure that a short between those two tracks does not lead to the charger output exceeding the “Lithium-Safe” region limits. Intersil will have the FMEA document for the solution using the ISL9209C and the ISL6292C chip set but the layout FMEA should be added as part of the analysis. © Copyright Intersil Americas LLC 2007-2009. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6489 Rev 1.00 January 16, 2009 Page 10 of 11 ISL9209C Thin Dual Flat No-Lead Plastic Package (TDFN) L12.4x3A 12 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-229-WGED-4 ISSUE C) 2X 0.15 C A A D MILLIMETERS 2X 0.15 C B SYMBOL 0.70 A1 - A3 E b 6 INDEX AREA D2 B 0.18 // A SIDE VIEW C SEATING PLANE 0.08 A3 C - - 0.05 - 0.23 0.30 5,8 3.15 3.30 3.40 7,8 3.00 BSC 1.55 e 1.70 1.80 7,8 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 12 2 Nd 6 3 7 NOTES: 8 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. D2/2 1 C NOTES 0.80 Rev. 0 1/06 D2 (DATUM B) 0.10 MAX 0.75 4.00 BSC E E2 NOMINAL 0.20 REF D TOP VIEW 6 INDEX AREA MIN A 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 2 4. All dimensions are in millimeters. Angles are in degrees. NX k 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. E2 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. (DATUM A) E2/2 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW NX (b) 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 5 0.10 M C A B CL (A1) L 5 e SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE FN6489 Rev 1.00 January 16, 2009 Page 11 of 11