ISL94202IRTZ-T7

Datasheet ISL94202 Standalone 3 to 8 Cell Li-Ion Battery Pack Monitor Features The ISL94202 is a battery pack monitor IC that supports from three to eight series connected cells. It provides complete battery monitoring and pack control. The ISL94202 provides automatic shutdown and recovery from out-of-bounds conditions and automatically controls pack cell balancing. • Eight cell voltage monitors support Li-ion CoO2, Li-ion Mn2O4, Li-ion FePO4, and other chemistries • Stand-alone pack control - no MCU needed • Multiple voltage protection options (each programmable to 4.8V; 12-bit digital value) and selectable overcurrent protection levels The ISL94202 is highly configurable as a stand-alone unit, but can be used with an optional external Microcontroller (MCU), which communicates to the ISL94202 through an I2C interface. • Programmable detection/recovery times for overvoltage, undervoltage, overcurrent, and short-circuit conditions The ISL94202 supersedes the ISL94203 for all future designs, as the ISL94202 operates in both parallel and series power FET configurations. • Configuration/calibration registers maintained in EEPROM • Open Wire battery connection detection Applications • Integrated charge/discharge FET drive circuitry with built-in charge pump supports high-side N-channel FETs • Power tools • Battery back-up systems • Light electric vehicles • Portable equipment • Cell balancing uses external FETs with internal state machine or an optional external MCU • Energy storage systems • Enters low power states after periods of inactivity ○ Charge or discharge current detection resumes normal scan rates • Solar farms • Medical equipment • Hospital beds Related Literature • Monitoring equipment For a full list of related documents, visit our website: • Ventilators • ISL94202 device page P+ GND DFET C1 C2 C3 LDMON CHMON VDD VBATT VC8 CB8 VC7 CB7 VC6 CB6 VC5 CB5 VC4 CB4 VC3 CB3 VC2 CB2 VC1 CB1 VC0 VSS CFET PCFET CS2 43V CS1 43V PSD FETSOFF INT RGO CHRG ISL94202 SD EOC SCL SDA TEMPO xT1 xT2 VREF ADDR P- Figure 1. Typical Application Diagram FN8889 Rev.3.00 Oct.14.19 Page 1 of 153 ISL94202 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 1.2 1.3 1.4 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 2.2 2.3 2.4 2.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Symbol Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 13 13 20 3. Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4. System Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 0x00-0x4B Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 0x00-01 CDPW & VCELL OV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1.1 VCELL OV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1.2 0x01.7:4 CDPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 0x02-03 VCELL OVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 0x04-05 LDPW & VCELL UV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3.1 VCELL UV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3.2 0x05.7:4 LDPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 0x06-07 VCELL UVR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5 0x08-09 VCELL OVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.6 0x0A-0B VCELL UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.7 0x0C-0D VCELL EOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.8 0x0E-0F VCELL LVCL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.9 0x10-11 VCELL OV Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.9.1 VCELL OVDTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.9.2 VCELL OVDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.10 0x12-13 VCELL UV Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.10.1 VCELL UVDTU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.10.2 VCELL UVDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.11 0x14-15 OWT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.11.1 OWTU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.11.2 OWT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.12 0x16-17 DOC & DOCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.12.1 0x17.[6:4] DOC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.12.2 0x17.[3:2] DOCTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.12.3 0x16-17 DOCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.12.4 DOCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.13 0x18-19 COC & COCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.13.1 0x19.[6:4] COC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.13.2 0x19.[3:2] COCTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.13.3 0x18-19 COCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.13.4 COCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.14 0x1A-1B DSC & DSCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.14.1 0x1B.[6:4] DSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.14.2 0x1B.[3:2] DSCTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FN8889 Rev.3.00 Oct.14.19 32 35 35 36 36 37 37 37 38 38 39 40 40 41 41 42 42 42 42 43 43 43 43 44 44 44 45 46 46 46 47 47 48 48 48 Page 2 of 153 ISL94202 4.1.14.3 0x1B.[1:0] - 0x1A.[7:0] DSCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.14.4 DSCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.15 0x1C-1D CBMIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.16 0x1E-1F CBMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.17 0x20-21 CBMINDV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.18 0x22-23 CBMAXDV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.19 0x24-25 CBON Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.19.1 0x25.[3:2] CBONU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.19.2 0x24-25 CBON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.20 0x26-27 CBOFF Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.20.1 CBOFFU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.20.2 CBOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.21 0x28-29 CBUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.22 0x2A-2B CBUTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.23 0x2C-2D CBOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.24 0x2E-2F CBOTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.25 0x30-31 COT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.26 0x32-33 COTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.27 0x34-35 CUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.28 0x36-37 CUTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.29 0x38-39 DOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.30 0x3A-3B DOTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.31 0x3C-3D DUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.32 0x3E-3F DUTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.33 0x40-41 IOT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.34 0x42-43 IOTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.35 0x44-45 SLV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.36 0x46-47 WDT & SLT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.36.1 0x47.[7:3] WDT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.36.2 0x47.[2:1] SLTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.36.3 0x47.[0] - 0x46.[7:0] SLT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.37 0x48 Mode Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.37.1 0x48.[3:0] IDLE/DOZE Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.37.2 0x48.[7:4] SLEEP Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.38 0x49 Cell Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.39 0x4A Setup 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.39.1 0x4A.7 CELLF PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.39.2 0x4A.5 XT2M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.39.3 0x4A.4 TGAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.39.4 0x4A.2 PCFETE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.39.5 0x4A.1 DOWD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.39.6 0x4A.0 OWPSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.40 0x4B Setup 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.40.1 0x4B.7 CBDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.40.2 0x4B.6 CBDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.40.3 0x4B.5 DFODUV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.40.4 0x4B.4 CFODOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.40.5 0x4B.3 UVLOPD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.40.6 0x4B.0 CB_EOC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 0x80-89 Other Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 0x4C-4F RSV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 0x50-57 User EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 0x80-89 Operations Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FN8889 Rev.3.00 Oct.14.19 49 49 49 50 50 51 52 52 52 53 53 53 53 54 55 56 56 57 58 58 59 60 61 61 62 63 64 64 65 65 66 66 66 66 67 67 67 68 68 68 68 68 68 69 69 69 69 70 70 70 70 70 70 Page 3 of 153 ISL94202 4.3.1 0x80 Status 0 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1.1 0x80.7 CUTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1.2 0x80.6 COTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1.3 0x80.5 DUTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1.4 0x80.4 DOTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1.5 0x80.3 UVLOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1.6 0x80.2 UVF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1.7 0x80.1 OVLOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1.8 0x80.0 OVF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 0x81 - Status 1 (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.1 0x81.7 VEOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.2 0x81.5 OWF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.3 0x81.4 CELLF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.4 0x81.3 DSCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.5 0x81.2 DOCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.6 0x81.1 COCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.7 0x81.0 IOTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 0x82 - Status 2 (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3.1 0x82.7 LVCHG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3.2 0x82.6 INT_SCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3.3 0x82.5,4 ECC_FAIL & ECC_USED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3.4 0x82.3 DCHING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3.5 0x82.2 CHING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3.6 0x82.1 CH_PRSNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3.7 0x82.0 LD_PRSNT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 0x83 - Status 3 (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4.1 0x83.6 IN_SLEEP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4.2 0x83.5 IN_DOZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4.3 0x83.4 IN_IDLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4.4 0x83.3 CBUV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4.5 0x83.2 CBOV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4.6 0x83.1 CBUTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4.7 0x83.0 CBOTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 0x84 CBFC (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 0x85 Control 0 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6.1 0x85.6 ADCSTRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6.2 0x85.[5:4] CG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6.3 0x85.[3:0] AO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7 0x86 Control 1 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7.1 0x86.7 CLR_LERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7.2 0x86.6 LMON_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7.3 0x86.5 CLR_CERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7.4 0x86.4 CMON_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7.5 0x86.3 PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7.6 0x86.2 PCFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7.7 0x86.1 CFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.7.8 0x86.0 DFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8 0x87 - Control 2 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8.1 0x87.6 µCFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8.2 0x87.5 µCCBAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8.3 0x87.4 µCLMON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8.4 0x87.3 µCCMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8.5 0x87.2 µCSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8.6 0x87.1 OW_STRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.8.7 0x87.0 CBAL_ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9 0x88 - Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FN8889 Rev.3.00 Oct.14.19 71 71 71 72 72 72 72 73 73 73 73 74 74 74 74 75 75 75 76 76 76 76 77 77 77 77 78 78 78 78 78 78 78 78 79 79 79 80 80 80 80 81 81 81 81 81 82 82 82 83 83 83 84 84 84 84 Page 4 of 153 ISL94202 4.3.9.1 0x88.3 PDWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9.2 0x88.2 SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9.3 0x88.1 DOZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.9.4 0x88.0 IDLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.10 0x89 - EEPROM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.10.1 0x89.0 EEEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 0x8A-AB Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Conversion Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1.1 Threshold Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1.2 ADC Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1.3 Cell Voltage Formula . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 0x8A-8B CELMIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 0x8C-8D CELMAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.4 0x8E-8F IPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.5 0x90-9F VCELL1-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.6 0xA0-A1 ITEMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.7 0xA2-A5 XT1-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.8 0xA6-A7 VBATT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.9 0xA8-A9 VRGO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.10 0xAA-AB - ADCV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. 84 85 85 85 85 85 86 87 87 88 89 89 89 90 90 91 91 92 92 93 Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.1 VCn Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.2 CBn Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.3 VSS Pin (18, 28, 29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.4 VREF Pin (19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.5 Thermistor Pins (20-22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.6 ADDR Pin (24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.7 SCL Pin (25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.8 SDAI/O Pins (26, 27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.9 INT Pin (31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.10 PSD Pin (32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.11 FETSOFF Pin (33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.12 SD Pin (34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.13 EOC Pin (35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.14 RGO Pin (36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.15 CHMON Pin (37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.15.1 COC Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.15.1.1 Automatic CHMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.15.1.2 MCU CHMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5.15.2 Charger Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.16 LDMON Pin (38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.16.1 DOC/DSC Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.16.1.1 Automatic LDMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.16.1.2 MCU LDMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.16.2 Load Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.17 Cn Pins (39-41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.18 VDD Pin (43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.19 Power FET Pins (42, 44, 45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.19.1 DFET Pin (42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.19.2 CFET Pin (45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.19.3 PCFET Pin (44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 FN8889 Rev.3.00 Oct.14.19 Page 5 of 153 ISL94202 5.19.4 Automatic FET Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.19.5 MCU FET Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.20 CSI1-2 Pins (47, 48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.21 VBATT Pin (48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1 Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Wake Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 System Scans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Automatic V & I Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Automatic V, I, & T Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 MCU Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 System Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Powerdown State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 NORMAL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 IDLE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 DOZE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.5 SLEEP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.6 Mode Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Cell Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 Automatic CB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 MCU CB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Open Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Cell Fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 OV Detection/Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.1 VEOC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 UV Detection & Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Current Monitoring/Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.1 Overcurrent and Short-Circuit Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.1.1 DOC and DSC Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.1.2 COC Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 Temperature Monitoring/Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.1 Charging Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.2 Discharging Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.3 Internal Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 Operational Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.1 Control/Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.1.1 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.2 Standalone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.3 MCU Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.4 Mixed Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. 109 110 111 113 114 115 116 117 117 118 119 120 120 121 121 121 122 122 123 126 126 129 129 130 130 132 133 134 134 135 135 136 136 137 138 139 139 140 140 Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.1 I2C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.1 I2C Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.2 Clock/Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.3 Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.4 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.6 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.6.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FN8889 Rev.3.00 Oct.14.19 141 141 141 141 142 143 143 143 Page 6 of 153 ISL94202 7.1.6.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.7 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.7.1 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.7.2 Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.7.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.8 EEPROM Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.9 EEPROM Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.10 EEPROM Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.10.1 Prepare the ISL94202. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.10.2 Program EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1.10.3 Verify EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Synchronizing MCU Operations with Internal Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 146 146 146 146 147 148 148 148 149 149 149 8. Reduced Cell Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10. Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 FN8889 Rev.3.00 Oct.14.19 Page 7 of 153 ISL94202 1. 1. Overview Overview 1.1 Block Diagram N-Channel FETs P+ PACK+ VDD +16V 470nF CHMON C3 LDMON C2 DFET VDD C1 O.C. Recovery FET Controls/Charge Pump Wake-Up Circuit VBATT 1kΩ Power-On Reset State Machine VC8 330kΩ 47nF 10kΩ 1kΩ CB8 CB8:1 VC7 330kΩ 47nF 10kΩ EOC EOC/SD Error Conditions (OV, UV, SLP State Machines) VSS SD CB State Machine VSS FETSOFF CB7 1kΩ PSD VC6 330kΩ 47nF 10kΩ INT Registers CB6 Temp/Voltage Monitor ALU VC5 CB5 VC4 1kΩ 47nF 10kΩ 330kΩ CB4 VC3 1kΩ 47nF 10kΩ 330kΩ CB3 VC2 1kΩ 47nF 10kΩ 330kΩ CB2 VC1 1kΩ 47nF 10kΩ CB1 VC0 1kΩ 47nF Timing and Control Scan State Machine LDO RGO REG RGO (OUT) Scan State CB State Overcurrent State EOC/SD/Error State SDAO SDAI I2C SCL ADDR TEMPO Watchdog Timer TEMP 330kΩ Memory Manager OSC MUX 10kΩ 330kΩ MUX 47nF EEPROM Registers 14-BIT ADC MUX 1kΩ Input Buffer/Level Shifter/Open-Wire Detect BAT+ PCFET Current-Sense Gain Amplifier x5/x50/x500 GAIN Overcurrent State Machine 100Ω BAT- CFET CS2 CS1 VDD +16V TEMP VB/16 RGO/2 xT2 xT2 xT1 xT1 iT TGAIN x1/x2 VREF VREF VSS PACK- P- Figure 2. Block Diagram FN8889 Rev.3.00 Oct.14.19 Page 8 of 153 ISL94202 1.2 1. Overview Ordering Information Part Number (Notes 2, 3) Part Marking Temp. Range (°C) Tape and Reel (Units) (Note 1) Package (RoHS Compliant) Pkg. Dwg. # ISL94202IRTZ 94202 IRTZ -40 to +85 - 48 Ld TQFN L48.6x6 ISL94202IRTZ-T 94202 IRTZ -40 to +85 4k 48 Ld TQFN L48.6x6 ISL94202IRTZ-T7 94202 IRTZ -40 to +85 1k 48 Ld TQFN L48.6x6 ISL94202IRTZ-T7A 94202 IRTZ -40 to +85 250 48 Ld TQFN L48.6x6 ISL94202EVKIT1Z Evaluation Kit Notes: 1. See TB347 for details on reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 3. For Moisture Sensitivity Level (MSL), see the ISL94202 device page. For more information on MSL, see TB363. Table 1. Key Differences Between Family of Parts Cells Supported Part Number Pack Voltage (Op) Charge/Discharge FET Min Max Cell (V) (V) Balance IPack Fuel Sense Gauge Min Max ISL94202 3 8 4 36 External High Side ISL94203 3 8 4 36 External ISL94208 4 6 8 27 ISL94212 6 12 6 RAJ240100 3 10 RAJ240090 3 RAJ240080 2 FN8889 Rev.3.00 Oct.14.19 Supply Current (Typ) Internal Daisy ADC Chain Config. Location Normal Sleep Standalone No Both High Side 348µA 13µA State Machine 14b No High Side No Parallel High Side 348µA 13µA State Machine 14b No Internal Low Side No Both Low Side 850µA 2µA No N/A No 60 External No No N/A N/A 3.31mA 12µA No 14b Yes 4 50 Both Low Side Yes Both High Side 50µA 1µA Int MCU 18b No 8 4 50 Both Low Side Yes Both High Side 50µA 1µA Int MCU 18b No 5 4 28 Both Low Side Yes Both High Side 50µA 1µA Int MCU 18b No Page 9 of 153 ISL94202 1.3 1. Overview Pin Configuration 1.4 VBATT CSI1 CSI2 CFET PCFET VDD DFET C1 C2 C3 LDMON CHMON 48 Ld TQFN TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 VC8 1 36 RGO CB8 2 35 EOC VC7 3 34 SD CB7 4 33 FETSOFF VC6 5 32 PSD CB6 6 VC5 7 CB5 8 29 VSS VC4 9 28 VSS CB4 10 27 SDAO VC3 11 26 SDAI CB3 12 25 SCL 31 INT PAD (GND) 17 18 19 20 CB2 VC1 CB1 VC0 VSS VREF XT1 21 22 23 24 ADDR 16 DNC 15 TEMPO 14 XT2 13 VC2 30 DNC Pin Descriptions Pin Number Symbol Description 1, 3, 5, 7, 9, 11, 13, 15, 17 VC[8:0] Battery Cell n voltage sense input. These pins monitor the voltage of the battery pack cells. The voltage is level shifted to a ground reference and is monitored internally by an ADC converter. VCn connects to the positive terminal of a battery cell (CELLN) and VC(n-1) connects to the negative terminal of CELLN. 2, 4, 6, 8, 10, 12, 14, 16 CB[8:1] Cell Balancing FET control output n. An internal drive circuit controls an external FET that is used to divert a portion of the current around a cell while the cell charges or adds to the current pulled from a cell during discharge to perform a cell voltage balancing operation. This function is generally used to reduce the voltage on an individual cell relative to other cells in the pack. The cell balancing FETs are turned on or off by an internal cell balance state machine or an external MCU. 18, 28, 29 VSS 19 VREF 20 XT1 21 XT2 22 TEMPO 23, 30 DNC 24 ADDR 25 SCL FN8889 Rev.3.00 Oct.14.19 Ground. This pin connects to the most negative terminal in the battery string. If separate analog and digital ground planes are used they should be connected together at the VSS pins. Voltage Reference Output. This output is the a 1.8V reference voltage used by the internal circuitry (ADC). This pin should not be loaded as this could cause significant ADC error. The VREF pin should be connected to GND through a 1µF capacitor. Temperature monitor inputs. These pins input the voltage across two external NTC thermistors used to determine the temperature of the cells and or the power FET. Temperature Monitor Output Reference. This pin outputs a voltage to be used in a divider that consists of a fixed resistor and a thermistor. The thermistor is located in close proximity to the cells or a power FET. The TEMPO output is connected internally to the VRGO voltage through a PMOS switch only during a measurement of the temperature, otherwise the TEMPO output is off. Do not connect, pin must be floated. Serial Address. This is an address input for an I2C communication link to allow for two devices on one bus. Serial Clock. This is the clock input for an I2C communication link. Page 10 of 153 ISL94202 Pin Number 1. Overview Symbol Description Serial Data. These are the data lines for an I2C interface. When connected together, they form the standard bidirectional interface for the I2C bus (recommended). 26 SDAI 27 SDAO 31 INT Interrupt. This pin goes active low when there is an external MCU connected to the ISL94202 and MCU communication fails to send a slave byte within a watchdog timer period. This is a CMOS type output. 32 PSD Pack Shutdown. This pin is set high when any cell voltage reaches the OVLO threshold (OVLO flag). Optionally, PSD is also set if there is a voltage differential between any two cells that is greater than a specified limit (CELLF flag) or if there is an open-wire condition. This pin can be used with external circuitry for blowing a fuse in the pack or as an interrupt to an external MCU. 33 FETSOFF FETSOFF. This input allows an external MCU to turn off both Power FET and CB outputs. This pin should be pulled low when inactive or tied to ground if unused. 34 SD Shutdown. This output indicates that the ISL94202 detected a failure condition that would result in the DFET turning off. This could be undervoltage, over-temperature, under-temperature, etc. The SD pin also goes active if there is any charge overcurrent condition. This is an open-drain output. 35 EOC End-of-Charge. This output indicates that the ISL94202 detected a fully charged condition. This is defined by any cell voltage exceeding an EOC voltage (as defined by an EOC value in EEPROM). 36 RGO Regulator Output. This is the 2.5V regulator output. 37 CHMON Charge Monitor. This pin is used to detect a charger connection. When the IC is in the Powerdown State or SLEEP Mode, connecting this pin to the charger wakes up the device. When the IC recovers from a charge overcurrent condition, this pin is used to determine if the charger is removed prior to turning on the power FETs. 38 LDMON Load Monitor. This pin is used to detect a load connection. When the IC is in the SLEEP Mode, connecting this pin to a load wakes up the device. When the IC recovers from a discharge overcurrent or short-circuit condition, this pin is used to determine if the load is removed prior to turning on the power FETs. 39, 40, 41 C[3:1] Charge Pump Capacitors. These external capacitors are used by the charge pump to drive the power FETs. 42 DFET Discharge FET Control. The ISL94202 controls the gate of a Discharge N-channel FET through this pin. The FET is turned on by the ISL94202 if all conditions are acceptable. The ISL94202 turns off the FET if an out-of-bounds condition occurs. The FET can be turned off by an external MCU by writing to the DFET control bit. The DFET output is also turned off by the FETSOFF pin. The FET output cannot be turned on by an external MCU if there are any out-of-bounds conditions. 43 VDD Power Supply. This pin provides the operating voltage for the IC circuitry. 44 PCFET Precharge FET Control. The ISL94202 controls the gate of a Precharge N-channel FET through this pin. The FET is turned on by the ISL94202 under precharge conditions, a trickle charge of the cells at the low end of the charge range. The ISL94202 turns off the FET if an out-of-bounds condition occurs. The FET can be turned off by an external MCU by writing to the PCFET control bit. The PCFET output is also turned off by the FETSOFF pin. The FET output cannot be turned on by an external MCU if there are any out-of-bounds conditions. Either the PCFET or the CFET turn on, but not both. 45 CFET Charge FET Control. The ISL94202 controls the gate of a Charge N-channel FET through this pin. The FET is turned on by the ISL94202 if all conditions are acceptable. The ISL94202 turns off the FET if an out-of-bounds condition occurs. The FET can be turned off by an external MCU by writing to the CFET control bit. The CFET output is also turned off by the FETSOFF pin. The FET output cannot be turned on by an external MCU if there are any out-of-bounds conditions. Either the PCFET or the CFET turn on, but not both. 46 CSI2 47 CSI1 Current-Sense Inputs. These pins connect the ISL94202 current-sense circuit to the external sense resistor to measure the differential voltage. The sense resistor is typically in the range of 0.2mΩ to 5mΩ. 48 VBATT PAD GND FN8889 Rev.3.00 Oct.14.19 Input Level Shifter Supply and Battery Pack Voltage Input. This pin powers the input level shifters and is also used to monitor the voltage of the battery stack. The voltage is internally divided by 32 and connected to an ADC converter through a MUX. Thermal Pad. This pad should connect to ground. Page 11 of 153 ISL94202 2. 2. Specifications Specifications 2.1 Absolute Maximum Ratings Parameter Minimum Maximum (Note 4) Unit VSS - 0.5 VSS+ 45.0 V VCn -0.5 VBATT + 0.5 V VCn - VSS (n = 8) -0.5 45.0 V VCn - VSS (n = 6, 7) -0.5 36.0 V VCn - VSS (n = 4, 5) -0.5 27.0 V VCn - VSS (n = 2, 3) -0.5 17.0 V VCn - VSS (n = 1) -0.5 7.0 V VCn - VSS (n = 0) -0.5 3.0 V VCn - VC(n-1) (n = 2 to 12) -3.0 7.0 V VC1 - VC0 -0.5 7.0 V VCBn - VC(n-1), n = 1 to 5 -0.5 7.0 V VCn - VCBn, n = 6 to 8 -0.5 7.0 V ADDR, xT1, xT2, FETSOFF, PSD, INT -0.5 VRGO +0.5 V SCL, SDAI, SDAO, EOC, SD -0.5 5.5 V VDD - 0.5 VDD + 15.5 (60V max) V -0.5 VDD + 15.0 (60V max) V 25 mA Power Supply Voltage, VDD Cell Voltage (VC, VBATT) Cell Balance Pin Voltages (VCB) Terminal Voltage CFET, PCFET, C1, C2, C3 DFET, CHMON, LDMON Terminal Current RGO Current-Sense Voltage VBATT, CS1, CS2 -0.5 VDD +1.0 V VBATT - CS1, VBATT - CS2 -0.5 +0.5 V CS1 - CS2 -0.5 +0.5 V ESD Rating Value Unit 1.5 kV Charged Device Model (Tested per JS-002-2014) 1 kV Latch-Up (Tested per JESD78E; Class 2, Level A) 100 mA Human Body Model (Tested per JS-001-2014) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Note: 4. Devices are characterized, but not production tested, at Absolute Maximum Voltages. FN8889 Rev.3.00 Oct.14.19 Page 12 of 153 ISL94202 2.2 2. Specifications Thermal Information Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 28 0.75 48 Ld QFN Package (Notes 5, 6) Notes: 5. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. 6. For θJC, the case temperature location is the center of the exposed metal pad on the package underside. Parameter Minimum Maximum Unit 400 mW +125 °C +125 °C Continuous Package Power Dissipation Maximum Junction Temperature Storage Temperature Range -55 Pb-Free Reflow Profile 2.3 see TB493 Recommended Operating Conditions Parameter Minimum Maximum Unit -40 +85 °C VDD 4V 36 V VCn-VC(n-1) Specified Range 2.0 4.3 V VCn-VC(n-1) Extended Range 1.0 4.4 V VCn-VC(n-1) Maximum Range (any cell) 0.5 4.8 V Temperature Range Operating Voltage 2.4 Electrical Specifications VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating temperature range, -40°C to +85°C. Parameter Symbol Test Conditions Min (Note 7) Typ Max (Note 7) Unit VPORR1 VDD minimum voltage at which device operation begins (CFET turns on; CHMON = VDD) 6.0 V VPORR2 CHMON minimum voltage at which device operation begins (CFET turns on; VDD > 6.0V) VDD V Powerdown Condition – Threshold Falling VPORF VDD minimum voltage device remains operational (RGO turns off) 3.0 V 2.5V Regulated Voltage VRGO IRGO = 3mA 1.8V Reference Voltage VREF VBATT Input Current - VBATT IVBATT Power-Up Condition – Threshold Rising (Device becomes operational) Input current; NORMAL/IDLE/DOZE Modes VDD = 33.6V Input current; SLEEP/Powerdown Modes VDD = 33.6V FN8889 Rev.3.00 Oct.14.19 2.4 2.5 2.6 V 1.79 1.8 1.81 V 38 45 µA 1 µA Page 13 of 153 ISL94202 2. Specifications VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating temperature range, -40°C to +85°C. (Continued) Parameter Symbol VDD Supply Current Test Conditions Min (Note 7) Max (Note 7) Unit IVDD1 Device active (NORMAL Mode) (No error conditions) CFET, PCFET, DFET = OFF; VDD = 33.6V 310 370 µA IVDD2 Device active (IDLE Mode) (No error conditions) IDLE = 1 CFET, PCFET, DFET = OFF; VDD = 33.6V 215 275 µA IVDD3 Device active (DOZE Mode) (No error conditions) DOZE = 1 CFET, PCFET, DFET = OFF; VDD = 33.6V 210 265 µA IVDD4 FET drive current (IVDD increase when FETs are on NORMAL/IDLE/DOZE Modes); VDD = 33.6V 215 IVDD5 Device active (SLEEP Mode); SLEEP = 1; VDD = 33.6V 0°C to +60°C Input Bias Current Typ 13 µA 30 µA -40°C to +85°C 50 µA IVDD6 Powerdown PDWN = 1; VDD = 33.6V 1 µA ICS1 VDD = VBATT = VCS1 = VCS2 = 33.6V (NORMAL, IDLE, DOZE) 15 µA 0°C to +60°C 1 µA -40°C to +85°C 3 µA 15 µA 0°C to +60°C 1 µA -40°C to +85°C 3 µA 10 VDD = VBATT = VCS1 = VCS2 = 33.6V (SLEEP, Powerdown) ICS2 VDD = VBATT = VCS1 = VCS2 = 33.6V (NORMAL, IDLE, DOZE) 10 VDD = VBATT = VCS1 = VCS2 = 33.6V (SLEEP, Powerdown) VCn Input Current IVCN Cell input leakage current AO2:AO0 = 0000H (NORMAL/IDLE/DOZE; not sampling cells) -1 1 µA CBn Input Current ICBN Cell Balance pin leakage current (no balance active) -1 1 µA VXT1 External temperature monitoring error. ADC voltage error when monitoring xT1 input. TGain = 0; (xTn = 0.2V to 0.737V) -25 15 mV Temperature Monitor Specifications External Temperature Accuracy Internal Temperature Monitor Output (See: “Temperature Monitoring/Response” on page 135) TINT25 [iTB:iT0]10*1.8/4095/GAIN GAIN = 2 (TGain bit = 0) Temperature = +25°C VINTMON Change in [iTB:iT0]10*1.8/4095/GAIN GAIN = 2 (TGain bit = 0) Temperature = -40°C to +85°C FN8889 Rev.3.00 Oct.14.19 0.276 V 1.0 mV/°C Page 14 of 153 ISL94202 2. Specifications VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating temperature range, -40°C to +85°C. (Continued) Parameter Min (Note 7) Typ Max (Note 7) Unit 3 10 mV VCn -VC(n-1) = 0.1V to 4.7V; 0°C to +60°C 15 mV VCn -VC(n-1) = 0.1V to 4.7V; -40°C to +85°C 30 mV Symbol Test Conditions VADCR Relative cell measurement error (Maximum absolute cell measurement error Minimum absolute cell measurement error) Cell Voltage Monitor Specifications Cell Monitor Voltage Accuracy (Relative) VCn -VC(n-1) = 2.4V to 4.2V; 0°C to +60°C Cell Monitor Voltage Accuracy (Absolute) VBATT Voltage Accuracy VADC VBATT Absolute cell measurement error (Cell measurement error compared with voltage at the cell) VCn - VC(n-1) = 2.4V to 4.2V; 0°C to +60°C -15 15 mV VCn - VC(n-1) = 0.1V to 4.7V; 0°C to +60°C -20 20 mV VCn - VC(n-1) = 0.1V to 4.7V; -40°C to +85°C -30 30 mV 0°C to +60°C -200 200 mV -40°C to +85°C -270 270 mV VBATT - [VBB:VB0]10*32*1.8/4095; Current-Sense Amplifier Specifications Charge Current Threshold VCCTH VCS1-VCS2, CHING set (charging) -100 μV Discharge Current Threshold VDCTH VCS1-VCS2, DCHING set (discharging) 100 μV VIA1 VIA1 = ([ISNSB:ISNS0]10*1.8/4095)/5; CHING bit set; Gain = 5 VCS1 = 26.4V, VCS2 - VCS1 = + 100mV 97 102 107 mV VIA2 VIA2 = ([ISNSB:ISNS0]10*1.8/4095)/5; DCHING bit set; Gain = 5 VCS1 = 26.4V, VCS2 - VCS1 = - 100mV -107 -102 -97 mV VIA3 VIA3 = ([ISNSB:ISNS0]10*1.8/4095)/50; CHING bit set; Gain = 50 VCS1 = 26.4V, VCS2 - VCS1 = + 10mV 8.0 10.0 12.0 mV VIA4 VIA4 = ([ISNSB:ISNS0]10*1.8/4095)/50; DCHING bit set; Gain = 50 VCS1 = 26.4V, VCS2 - VCS1 = - 10mV -12.0 -10.0 -8.0 mV VIA5 VIA3 = ([ISNSB:ISNS0]10*1.8/4095)/500; CHING bit set; Gain = 500 VCS1 = 26.4V, VCS2 - VCS1 = + 1mV 0°C to +60°C 0.5 1.0 1.5 mV -40°C to +85°C 0.4 1.6 mV -0.5 mV -0.4 mV Current-Sense Accuracy VIA6 FN8889 Rev.3.00 Oct.14.19 VIA4 = ([ISNSB:ISNS0]10*1.8/4095)/500; DCHING bit set; Gain = 500 VCS1 = 26.4V, VCS2 - VCS1 = - 1mV 0°C to +60°C -1.5 -40°C to +85°C -1.6 -1.0 Page 15 of 153 ISL94202 2. Specifications VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating temperature range, -40°C to +85°C. (Continued) Parameter Min (Note 7) Typ Max (Note 7) Unit VOCD = 4mV [OCD2:0] = 0,0,0 2.6 4.0 5.4 mV VOCD = 8mV [OCD2:0] = 0,0,1 6.4 8.0 9.6 mV VOCD = 16mV [OCD2:0] = 0,1,0 12.8 16.0 19.2 mV VOCD = 24mV [OCD2:0] = 0,1,1 20 25 30 mV VOCD = 32mV [OCD2:0] = 1,0,0 (default) 26.4 33.0 39.6 mV VOCD = 48mV [OCD2:0] = 1,0,1 42.5 50.0 57.5 mV VOCD = 64mV [OCD2:0] = 1,1,0 60.3 67.0 73.7 mV VOCD = 96mV [OCD2:0] = 1,1,1 90 100 110 mV Symbol Test Conditions Overcurrent/Short-Circuit Protection Specifications Discharge Overcurrent Detection Threshold VOCD 160 ms Discharge Overcurrent Detection Time tOCDT [OCDTA:OCDT0] = 0A0H (160ms) (default) Range: 0ms to 1023ms 1ms/step 0s to 1023s; 1s/step Short-Circuit Detection Threshold VSCD VSCD = 16mV [SCD2:0] = 0,0,0 10.4 16.0 21.6 mV VSCD = 24mV [SCD2:0] = 0,0,1 18 24 30 mV VSCD = 32mV [SCD2:0] = 0,1,0 26 33 40 mV VSCD = 48mV [SCD2:0] = 0,1,1 42 49 56 mV VSCD = 64mV [SCD2:0] = 1,0,0 60 67 74 mV VSCD = 96mV [SCD2:0] = 1,0,1 (default) 90 100 110 mV VSCD = 128mV [SCD2:0] = 1,1,0 127 134 141 mV VSCD = 256mV [SCD2:0] = 1,1,1 249 262 275 mV 200 µs Short-Circuit Current Detection Time tSCT [SCTA:SCT0] = 0C8H (200µs) (default) Range: 0µs to 1023µs; 1µs/step 0ms to 1023ms 1ms/step Charge Overcurrent Detection Threshold VOCC VOCC = 1mV [OCC2:0] = 0,0,0 0.2 1.0 2.1 mV VOCC = 2mV [OCC2:0] = 0,0,1 0.7 2.0 3.3 mV VOCC = 4mV [OCC2:0] = 0,1,0 2.8 4.0 5.2 mV VOCC = 6mV [OCC2:0] = 0,1,1 4.5 6.0 7.5 mV VOCC = 8mV [OCC2:0] = 1,0,0 (default) 6.6 8.0 9.8 mV VOCC = 12mV [OCC2:0] = 1,0,1 9.6 12.0 14.4 mV VOCC = 16mV [OCC2:0] = 1,1,0 14.5 17.0 19.6 mV VOCC = 24mV [OCC2:0] = 1,1,1 22.5 25.0 27.5 mV Overcurrent Charge Detection Time tOCCT 160 [OCCTA:OCCT0] = 0A0H (160ms) (default) Range: 0ms to 1023ms 1ms/step 0s to 1023s; 1s per step ms Charge Monitor Input Threshold (Falling Edge) VCHMON µCCMON bit = 1; CMON_EN bit = 1 8.2 8.9 9.8 V Load Monitor Input Threshold (Rising Edge) VLDMON µCLMON bit = 1; LMON_EN bit = 1 0.45 0.60 0.75 V Load Monitor Output Current ILDMON µCLMON bit = 1; LMON_EN bit = 1 FN8889 Rev.3.00 Oct.14.19 62 µA Page 16 of 153 ISL94202 2. Specifications VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating temperature range, -40°C to +85°C. (Continued) Parameter Min (Note 7) Max (Note 7) Symbol Test Conditions Overvoltage Lockout Threshold (Rising Edge - Any Cell) [VCn-VC(n-1)] VOVLO [OVLOB:OVLO0] = 0E80H (4.35V) (default) Range: 12-bit value (0V to 4.8V) 4.35 V Overvoltage Lockout Recovery Threshold - All Cells VOVLOR Falling edge VOVR V 1.8 V VUVR V Typ Unit Voltage Protection Specifications Undervoltage Lockout Threshold (Falling Edge - Any Cell) [VCn-VC(n-1)] VUVLO [UVLOB:UVLO0] = 0600H (1.8V) (default) Range: 12-bit value (0V to 4.8V) Undervoltage Lockout Recovery Threshold - All Cells VUVLOR Rising edge Overvoltage Lockout Detection Time tOVLO NORMAL Mode 5 consecutive samples over the limit (minimum = 160ms, maximum = 192ms) 176 ms Undervoltage Lockout Detection Time tUVLO NORMAL Mode 5 consecutive samples under the limit (minimum = 160ms, maximum = 192ms) 176 ms Overvoltage Threshold (Rising Edge - Any Cell) [VCn-VC(n-1)] VOV [OVLB:OVL0] = 0E2AH (4.25V) (default) Range: 12-bit value (0V to 4.8V) 4.25 V Overvoltage Recovery Voltage (Falling Edge - All Cells) [VCn-VC(n-1)] VOVR [OVRB:OVR0] = 0DD5H (4.15V) (default) Range: 12-bit value (0V to 4.8V) 4.15 V Overvoltage Detection/Release Time tOVT [OVTA:OVT0] = 201H (1s) (default) Range: 0ms to 1023ms; 1ms/step 0s to 1023s; 1s/step 1 s Undervoltage Threshold (Falling Edge - Any Cell) [VCn-VC(n-1)] VUV [UVLB:UVL0] = 0900H (2.7V) (default) Range: 12-bit value (0V to 4.8V) 2.7 V Undervoltage Recovery Voltage (Rising Edge - All Cells) [VCn-VC(n-1)] VUVR [UVRB:UVR0] = 0A00H (3.0V) (default) Range: 12-bit value (0V to 4.8V) 3.0 V Undervoltage Detection Time tUVT [UVTA:UVT0] = 201H (1s) (default) Range: 0ms to 1023ms; 1ms/step 0s to 1023s; 1s/step 1 s Undervoltage Release Time tUVTR [UVTA:UVT0] = 201H (1s) + 3s (default) Range: (0ms to 1023ms) + 3s; 1ms/step (0s to 1023s) + 3s; 1s/step 3 s SLEEP Level Voltage Threshold (Falling Edge - Any Cell) [VCn-VC(n-1)] VSLV [SLVB:SLV0] = 06AAH (2.0V) (default) Range: 12-bit value (0V to 4.8V) 2.0 V SLEEP Detection Time tSLT [SLTA:SLT0] = 201H (1s) (default) Range: 0ms to 1023ms; 1ms/step 0s to 1023s; 1s/step 1 s Low Voltage Charge Threshold (Falling Edge - Any Cell) [VCn-VC(n-1)] VLVCH [LVCHB:LVCH0] = 07AAH (2.3V) (default) Range: 12-bit value (0V to 4.8V) Precharge if any cell is below this voltage 2.3 V Low Voltage Charge Threshold Hysteresis VLVCHH 117 mV FN8889 Rev.3.00 Oct.14.19 Page 17 of 153 ISL94202 2. Specifications VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating temperature range, -40°C to +85°C. (Continued) Parameter Symbol End-of-Charge Threshold (Rising Edge - Any Cell) [VCn-VC(n-1)] VEOC End-of-Charge Threshold Hysteresis VEOCTH Test Conditions Min (Note 7) [EOCSB:EOCS0] = 0E00H (4.2V) (default) Range: 12-bit value (0V to 4.8V) Typ Max (Note 7) Unit 4.2 V 117 mV SLEEP Mode Timer tSMT [MOD7:MOD0] = 0DH (off) (default) Range: 0s to 255 minutes 90 min Watchdog Timer tWDT [WDT4:WDT0] = 1FH (31s) (default) Range: 0s to 31s 31 s Temperature Protection Specifications Internal Temperature Shutdown Threshold TITSD [IOTB:IOT0] = 02D8H 115 °C Internal Temperature Recovery TITRCV [IOTRB:IOTR0] = 027DH 95 °C External Temperature Output Voltage VTEMPO Voltage output at TEMPO pin (during temperature scan); ITEMPO = 1mA 2.30 2.45 2.60 V External Temperature Limit Threshold (Hot) - xT1 or xT2 Charge, Discharge, Cell Balance (see Figure 39) TXTH xTn Hot threshold. Voltage at VTEMPI, xT1 or xT2 = 04B6H, TGain = 0 ~+55°C; thermistor = 3.535k Detected by COT, DOT, CBOT bits = 1 0.265 V External Temperature Recovery Threshold (Hot) - xT1 or xT2 Charge, Discharge, Cell Balance (see Figure 39) TXTHR xTn Hot recovery voltage at VTEMPI xT1 or xT2 = 053EH, TGain = 0 (~+50°C; thermistor = 4.161k) Detected by COT, DOT, CBOT bits = 0 0.295 V External Temperature Limit Threshold (Cold) - xT1 or xT2 Charge, Discharge, Cell Balance (see Figure 39) TXTC xTn Cold threshold. Voltage at VTEMPI xT1 or xT2 = 0BF2H, TGain = 0 (~ -10°C; thermistor = 42.5k) Detected by CUT, DUT, CBUT bits 0.672 V External Temperature Recovery Threshold (Cold) - xT1 or xT2 Charge, Discharge, Cell Balance (see Figure 39) TXTCH xTn Cold recovery voltage at VTEMPI. xT1 or xT2 = 0A93H, TGain = 0 (~5°C; thermistor = 22.02k) Detected by CUT, DUT, CBUT bits 0.595 V Cell Balance Specifications Cell Balance FET Gate Drive Current Cell Balance Maximum Voltage Threshold (Rising Edge - Any cell) [CELMAX] VCBMX Cell Balance Maximum Threshold Hysteresis VCBMXH Cell Balance Minimum Voltage Threshold (Falling Edge - Any cell) [CELMIN] VCBMN Cell Balance Minimum Threshold Hysteresis VCBMNH Cell Balance Maximum Voltage Delta Threshold (Rising Edge - Any Cell) [VCn-VC(n-1)] VCBDU Cell Balance Maximum Voltage Delta Threshold Hysteresis VCBDUH FN8889 Rev.3.00 Oct.14.19 CB1 to CB5 (current out of pin) 15 25 35 µA CB6 to CB8 (current into pin) 15 25 35 µA [CBVUB:CBVU0] = 0E00H (4.2V) (default) Range: 12-bit value (0V to 4.8V) [CBVLB:CBVL0] = 0A00H (3.0V) (default) Range: 12-bit value (0V to 4.8V) [CBDUB:CBD0] = 06AAH (2.0V) (default) Range: 12-bit value (0V to 4.8V) 4.2 V 117 mV 3.0 V 117 mV 2.0 V 117 mV Page 18 of 153 ISL94202 2. Specifications VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating temperature range, -40°C to +85°C. (Continued) Parameter Min (Note 7) Typ Max (Note 7) Unit CHMON pin rising edge Device wakes up and sets SLEEP flag LOW 7.0 8.0 9.0 V LDMON pin falling edge Device wakes up and sets SLEEP flag LOW 0.15 0.40 0.70 V Symbol Test Conditions Device CHMON Pin Voltage Threshold (Wake on Charge) (Rising Edge) VWKUP1 Device LDMON Pin Voltage Threshold (Wake on Load) (Falling Edge) VWKUP2 Wake-Up Specifications Open-Wire Specifications Open-Wire Current Open-Wire Detection Threshold IOW 1.0 mA VOW1 VCn-VC(n-1); VCn is open. (n = 2, 3, 4, 5, 6, 7, 8). Open-wire detection active on the VCn input. -0.3 V VOW2 VC1-VC0; VC1 is open. Open-wire detection active on the VC1 input. 0.4 V VOW3 VC0-VSS; VC0 is open. Open-wire detection active on the VC0 input. 1.25 V FET Control Specifications DFET Gate Voltage CFET Gate Voltage (ON) PCFET Gate Voltage (ON) VDFET1 (ON) 100µA load; VDD = 36V 47 52 57 V VDFET2 (ON) 100µA load; VDD = 6V 8 9 10 V VDFET3 (OFF) VCFET1 (ON) 100µA load; VDD = 36V 47 52 57 V VCFET2 (ON) 100µA load; VDD = 6V 8 9 10 V VCFET3 (OFF) VPFET1 (ON) 100µA load; VDD = 36V 47 52 57 V VPFET2 (ON) 100µA load; VDD = 6V 8 9 10 V VPFET3 (OFF) 0 V VDD V VDD V FET Turn-Off Current (DFET) IDF(OFF) 14 15 16 mA FET Turn-Off Current (CFET) ICF(OFF) 9 13 17 mA FET Turn-Off Current (PCFET) IPF(OFF) 9 13 17 mA FETSOFF Rising Edge Threshold VFO(IH) FETSOFF rising edge threshold. Turn off FETs 1.8 V FETSOFF Falling Edge Threshold VFO(IL) FETSOFF falling edge threshold. Turn on FETs 1.2 V Serial Interface Characteristics (Note 8) Input Buffer Low Voltage (SCL, SDA) VIL Voltage relative to VSS of the device -0.3 VRGO x 0.3 V Input Buffer High Voltage (SCL, SDAI, SDAO) VIH Voltage relative to VSS of the device VRGO x 0.7 VRGO + 0.1 V VOL IOL = 1mA 0.4 V Output Buffer Low Voltage (SDA) SDA, SCL Input Buffer Hysteresis SCL Clock Frequency I2CHYST SLEEP bit = 0 fSCL 0.05 x VRGO V 400 kHz Pulse Width Suppression Time at SDA and SCL Inputs tIN Any pulse narrower than the maximum spec is suppressed. 50 ns SCL Falling Edge to SDA Output Data Valid tAA From SCL falling crossing VIH (minimum), until SDA exits the VIL (maximum) to VIH (minimum) window 0.9 µs FN8889 Rev.3.00 Oct.14.19 Page 19 of 153 ISL94202 2. Specifications VDD = 26.4V, TA = -40°C to +85°C, unless otherwise specified. Boldface specification limits apply across operating temperature range, -40°C to +85°C. (Continued) Parameter Min (Note 7) Max (Note 7) Symbol Test Conditions Time the Bus Must Be Free Before Start of New Transmission tBUF SDA crossing VIH (minimum) during a STOP condition to SDA crossing VIH (minimum) during the following START condition 1.3 µs Clock Low Time tLOW Measured at the VIL (maximum) crossing 1.3 µs Clock High Time tHIGH Measured at the VIH (minimum) crossing 0.6 µs Start Condition Set-Up Time tSU:STA SCL rising edge to SDA falling edge, both crossing the VIH (minimum) level 0.6 µs Start Condition Hold Time tHD:STA From SDA falling edge crossing VIL (maximum) to SCL falling edge crossing VIH (minimum) 0.6 µs Input Data Set-Up Time tSU:DAT From SDA exiting the VIL (maximum) to VIH (minimum) window to SCL rising edge crossing VIL (minimum) 100 ns Input Data Hold Time tHD:DAT From SCL falling edge crossing VIH (minimum) to SDA entering the VIL (maximum) to VIH (minimum) window Stop Condition Set-Up Time tSU:STO From SCL rising edge crossing VIH (minimum) to SDA rising edge crossing VIL (maximum) 0.6 µs Stop Condition Hold Time tHD:STO From SDA rising edge to SCL falling edge. Both crossing VIH (minimum) 0.6 µs 0 ns Typ 0 0.9 Unit µs Data Output Hold Time tDH From SCL falling edge crossing VIL (maximum) until SDA enters the VIL (maximum) to VIH (minimum) window SDA and SCL Rise Time tR From VIL (maximum) to VIH (minimum) 300 ns SDA and SCL Fall Time tF From VIH (minimum) to VIL (maximum) 300 ns SDA and SCL Bus Pull-Up Resistor Off-Chip ROUT Input Leakage (SCL, SDA) ILI EEPROM Write Cycle Time tWR 1 Maximum is determined by tR and tF For CB = 400pF, maximum is 2kΩ ~ 2.5kΩ For CB = 40pF, maximum is 15kΩ ~ 20kΩ kΩ -10 +25°C 10 µA 30 ms Notes: 7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Device MIN and/or MAX values are based on temperature limits established by characterization and are not production tested. 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. 2.5 Symbol Table Waveform Inputs Outputs Must Be Steady Is Steady Can Change From Low To High Changes From Low To High Can Change From High To Low Changes From High To Low Waveform Inputs Outputs Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line Is High Impedance Figure 3. Symbol Table FN8889 Rev.3.00 Oct.14.19 Page 20 of 153 ISL94202 3. 3. Typical Performance Curves Typical Performance Curves 2.53 2.52 2.51 VRGO (V) 2.50 2.49 2.48 2.47 2.46 2.45 2.44 2.43 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 4. VRGO vs Temperature 1.8005 1.8000 1.7995 VREF (V) 1.7990 1.7985 1.7980 1.7975 1.7970 1.7965 1.7960 1.7955 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 5. VREF vs Temperature 70 60 VDD Current (µA) 50 40 30 20 10 0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 6. VDD Current vs Temperature - SLEEP FN8889 Rev.3.00 Oct.14.19 Page 21 of 153 ISL94202 3. Typical Performance Curves 0.16 0.14 VDD Current (µA) 0.12 0.10 0.08 0.06 0.04 0.02 0.00 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 7. VDD Current vs Temperature - Powerdown 400 350 VDD Current (µA) 300 250 200 150 100 50 0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 8. VDD Current vs Temperature - Normal 300 VDD Current (µA) 250 200 150 100 50 0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 9. VDD Current vs Temperature - Idle FN8889 Rev.3.00 Oct.14.19 Page 22 of 153 ISL94202 3. Typical Performance Curves 300 VDD Current (µA) 250 200 150 100 50 0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 85 95 105 85 95 105 Temperature (°C) Figure 10. VDD Current vs Temperature - Doze 0.06 VBAT Current (µA) 0.05 0.04 0.03 0.02 0.01 0.00 -35 -25 -15 -5 5 15 25 35 45 55 65 75 Temperature (°C) Figure 11. VBAT Current vs Temperature - Sleep 0.030 VBAT Current (µA) 0.025 0.020 0.015 0.010 0.005 0.000 -35 -25 -15 -5 5 15 25 35 45 55 65 75 Temperature (°C) Figure 12. VBAT Current vs Temperature - Powerdown FN8889 Rev.3.00 Oct.14.19 Page 23 of 153 ISL94202 3. Typical Performance Curves 35.5 35.0 VBAT Current (µA) 34.5 34.0 33.5 33.0 32.5 32.0 31.5 31.0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 13. VBAT Current vs Temperature - Normal 230 FET Drive Current (µA) 225 220 215 210 205 200 195 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 CFET DFET VBATT = 36V -300 -320 -340 -360 -380 -400 -420 -440 -460 -480 -500 -520 -540 -560 -580 -600 -620 -640 -660 -680 -700 -720 -740 -760 -780 -800 -820 -840 -860 -880 -900 -920 -940 -960 -980 -1000 -1020 -1040 -1060 -1080 Gate Voltage (V) Figure 14. Power FET Drive Current vs Temperature FET Pin Load Current (µA) Figure 15. FET Gate Voltage vs Load Current FN8889 Rev.3.00 Oct.14.19 Page 24 of 153 ISL94202 3. Typical Performance Curves 2.5 DFET CFET PCFET Power FET current (µA) 2.0 1.5 1.0 0.5 0.0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 95 105 Temperature (°C) Figure 16. Power FET Pin Leakage Current (OFF) vs Temperature 0.40 Open-Wire VC2-8 Threshold (V) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 VC2 VC3 VC4 VC6 VC7 VC8 VC5 0.00 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 17. Open-Wire VC2-8 Threshold vs Temperature 0.434 Open-Wire VC1 Threshold (V) 0.432 0.430 0.428 0.426 0.424 0.422 0.420 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 18. VC1 Open-Wire Threshold vs Temperature FN8889 Rev.3.00 Oct.14.19 Page 25 of 153 ISL94202 3. Typical Performance Curves 1.340 Open-Wire VC0 Threshold (V) 1.335 1.330 1.325 1.320 1.315 1.310 1.305 1.300 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 105 95 Temperature (°C) Figure 19. VC0 Open-Wire Threshold vs Temperature 0.98 Open-Wire 1mA Current (mA) 0.96 0.94 0.92 0.9 0.88 0.86 0.84 VC0 VC1 VC2 VC3 VC4 VC5 VC6 VC7 VC8 0.82 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 75 85 95 105 Temperature (°C) Figure 20. Open-Wire Current vs Temperature 130 Oscillator Frequency (kHz) 128 126 124 122 120 118 116 -35 -25 -15 -5 5 15 25 35 45 55 65 Temperature (°C) Figure 21. OSC Frequency vs Temperature FN8889 Rev.3.00 Oct.14.19 Page 26 of 153 ISL94202 3. Typical Performance Curves 0.6 Load Monitor Wake-Up (V) 0.5 0.4 0.3 0.2 0.1 0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 85 95 105 85 95 Temperature (°C) Figure 22. LDMON Wake-Up Threshold vs Temperature 63 Load Monitor Current (µA) 62 61 60 59 58 57 56 55 -35 -25 -15 -5 5 15 25 35 45 55 65 75 Temperature (°C) Figure 23. LDMON Detection Current vs Temperature 7.90 Charge Monitor Wake-Up (V) 7.85 7.80 7.75 7.70 7.65 7.60 -35 -25 -15 -5 5 15 25 35 45 55 65 75 105 Temperature (°C) Figure 24. CHMON Wake-Up Threshold vs Temperature FN8889 Rev.3.00 Oct.14.19 Page 27 of 153 ISL94202 3. Typical Performance Curves 9.05 Charge Monitor Threshold (V) 9.00 8.95 8.90 8.85 8.80 8.75 8.70 8.65 8.60 8.55 µCCMON = 1, CMON_EN = 1, Falling Edge 8.50 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 25. CHMON Recovery Threshold vs Temperature ISENSE 500X Range ±1mV Value (mV) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 Charge Discharge 0.0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 26. ISENSE Voltage 500x Gain (1mV) vs Temperature ISENSE 50X Range ±10mV Value (mV) 10.2 10.1 10.0 9.9 9.8 9.7 9.6 9.5 Charge Discharge 9.4 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 27. ISENSE Voltage 50x Gain (10mV) vs Temperature FN8889 Rev.3.00 Oct.14.19 Page 28 of 153 ISL94202 3. Typical Performance Curves ISENSE 5X Range ±100mV Value (mV) 102.0 101.5 101.0 100.5 100.0 99.5 99.0 Charge Discharge 98.5 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Discharge Short-Ciruit Threshold (mV) Figure 28. ISENSE Voltage 5x Gain (100mV) vs Temperature 272 256 240 224 208 192 176 160 144 128 112 96 80 64 48 32 16 0 -35 -25 -15 -5 5 15 25 16mv 24mv 32mv 48mv 64mv 96mv 128mv 256mv 35 45 55 65 75 85 95 105 Temperature (°C) Figure 29. Discharge Short-Circuit Threshold vs Temperature 104 Discharge Overcurrent Threshold (mV) 96 88 4mv 8mv 16mv 24mv 80 32mv 48mv 64mv 96mv 72 64 56 48 40 32 24 16 8 0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 30. Discharge Overcurrent Threshold vs Temperature FN8889 Rev.3.00 Oct.14.19 Page 29 of 153 ISL94202 3. Typical Performance Curves 9.5 CS1, CS2 Current (µA) - Normal Mode CS1 CS2 9.0 8.5 8.0 7.5 7.0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 31. CS1 and CS2 Input Current vs Temperature 26 Charge Overcurrent Threshold (mV) 24 22 1mv 2mv 4mv 6mv 20 8mv 12mv 16mv 24mv 18 16 14 12 10 8 6 4 2 0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 32. Charge Overcurrent Threshold vs Temperature 6 2V 2.5V 3V 3.3V 3.6V 4V Cell Match (mV) 5 4 3 2 1 0 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 33. Cell Error vs Temperature FN8889 Rev.3.00 Oct.14.19 Page 30 of 153 ISL94202 3. Typical Performance Curves 27.0 26.5 Cell Balance Current (µA) 26.0 25.5 25.0 24.5 24.0 23.5 23.0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CB8 22.5 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature (°C) Figure 34. Cell Balance FET Drive Current vs Temperature FN8889 Rev.3.00 Oct.14.19 Page 31 of 153 ISL94202 4. 4. System Registers System Registers Customer specific operation of the ISL94202 is accomplished through the use of Control/Status Registers and EEPROM. Each register or EEPROM location contains eight bits, accessible using a 7-bit device address plus an 8th bit that indicates a read or a write, followed by the register address. For details about reading and writing registers, see the specific register descriptions in Table 2 and in “Communication Interface” on page 141. EEPROM programming is covered in “Control/Data Registers” on page 138 and “EEPROM Access” on page 147. The configuration registers are a set of volatile registers that enable customizable operation. These registers are initialized on POR (Power On Reset) by the device from the values stored in the EEPROM. They can be modified through the I2C port by an MCU, unless the device is in SLEEP Mode or Powerdown. A 1 written to a control or configuration bit causes the action to be taken. Status Registers include device measurement results, status bits that indicate operational Modes and fault indicator bits. Status Registers are not initialized from EEPROM. Some status registers are used by an external MCU to override device functionality. A 1 read from a status bit indicates that the condition exists. One status register enables read/write access control of the EEPROM. The EEPROM is a set of non-volatile registers that store configuration parameters (only). Read/write access to these registers is gated by “0x89 EEPROM Enable” on page 85. Operation of the ISL94202 is determined by the settings of the configuration registers and measurement results stored in the status registers. The configuration register value must be changed to affect a change in operation. Changes to the EEPROM can only affect an operational change following a POR. 4.1 0x00-0x4B Configuration Registers Configuration Registers are listed below in Table 2. Each listing includes the register page and address, register name with link for the detailed description, a depiction of the contents with bit names, EEPROM factory default, and the type of register (Read or Read/Write). The ISL94202 is configured for applications by accessing these registers. Each configuration register is mapped to an EEPROM location that shares the same address. Bit “0x89 EEPROM Enable” on page 85 determines which is accessed when reading from or writing to these shared addresses. The ranges and step-sizes listed for threshold registers are the ideal values to be used for calculation purposes. Threshold settings that would require operation outside of the recommended operating conditions are not supported. Reserved bits (RSV) should be ignored when reading registers and must be set to 0 when writing to them. Table 2. Page # Register List Bit Function Register Address (Hex) Register Name 7 6 5 4 3 2 1 0 Factory Default (Hex) Type EEPROM/Configuration Registers 35 36 37 00 VCELL OV LSB VCELL Overvoltage Threshold COV [7:0] 2A R/W 01 CDPW, VCELL OV MSB Charge Detect Pulse-Width CPW3 - CPW0 1E R/W 02 VCELL OVR LSB VCELL Overvoltage Recovery Threshold OVR [7:0] D4 R/W 03 VCELL OVR MSB RSV 0D R/W 04 VCELL UV LSB VCELL Undervoltage Threshold UVL [7:0] FF R/W 05 LDPW, VCELL UV MSB Load Detect Pulse Width LPW3 - LPW0 18 R/W FN8889 Rev.3.00 Oct.14.19 RSV RSV VCELL Overvoltage Threshold COV [B:8] RSV VCELL Overvoltage Recovery Threshold OVR [B:8] VCELL Undervoltage Threshold UVL [B:8] Page 32 of 153 ISL94202 Table 2. 4. System Registers Register List (Continued) Bit Function Factory Default (Hex) Type Page # Register Address (Hex) 38 06 VCELL UVR LSB VCELL Undervoltage Recovery Threshold UVR [7:0] FF R/W 07 VCELL UVR MSB RSV 09 R/W 08 VCELL OVLO LSB VCELL Overvoltage Lockout Threshold OVLO [7:0] 7F R/W 09 VCELL OVLO MSB RSV 0E R/W 0A VCELL UVLO LSB VCELL Undervoltage Lockout Threshold UVLO [7:0] 00 R/W 0B VCELL UVLO MSB RSV 06 R/W 0C VCELL EOC LSB VCELL End-of-Charge Threshold EOC [7:0] FF R/W 0D VCELL EOC MSB RSV 0D R/W 0E VCELL LVCL LSB VCELL Low Voltage Charge Level LVCL [7:0] AA R/W 0F VCELL LVCL MSB RSV 07 R/W 10 VCELL OVDT LSB VCELL Overvoltage Delay Timer OVDT [7:0] 01 R/W 11 VCELL OVDTU, VCELL OVDT MSB RSV 08 R/W 12 VCELL UVDT LSB VCELL Undervoltage Delay Time UVDT [7:0] 13 VCELL UVDTU, VCELL UVDT MSB RSV 14 OWT LSB Open-Wire Timing OWT [7:0] 15 OWTU, OWT MSB RSV 16 DOCT LSB Discharge Overcurrent Timer DOCT [7:0] 17 DOC , DOCTU, DOCT MSB RSV 18 COCT LSB Charge Overcurrent Timer COCT [7:0] 19 COC, COCTU, COCT MSB RSV 1A DSCT LSB Discharge Short-Circuit Timer DSCT [7:0] 1B DSC, DSCTU, DSCT MSB RSV 38 39 40 40 41 42 43 43 46 48 49 50 Register Name 7 6 RSV RSV RSV RSV RSV RSV RSV RSV 5 RSV RSV RSV RSV RSV RSV RSV RSV 4 RSV RSV RSV RSV RSV RSV 3 2 1 0 VCELL Undervoltage Recovery Threshold UVR [B:8] VCELL Overvoltage Lockout Threshold OVLO [B:8] VCELL Undervoltage Lockout Threshold UVLO [B:8] VCELL End-of-Charge Threshold EOC [B:8] VCELL Low Voltage Charge Level LVCL [B:8] VCELL Overvoltage VCELL Delay Timer Unit Overvoltage OVDTU [1:0] Delay Timer OVDT [9:8] RSV VCELL Undervoltage Delay Timer Unit UVDTU [1:0] VCELL Undervoltage Delay Timer UVDT [9:8] RSV RSV OpenWire Timing Unit OWTU Discharge Overcurrent Threshold DOC [2:0] Charge Overcurrent Threshold COC [2:0] Discharge Short-Circuit Threshold DSC [2:0] RSV Discharge Overcurrent Timer Unit DOCTU [1:0] Charge Overcurrent Timer Unit COCTU [1:0] Discharge Short-Circuit Timer Unit DSCTU [1:0] Open-W ire Timing OWT [8] Discharge Overcurrent Timer DOCT [9:8] Charge Overcurrent Timer COCT [9:8] Discharge Short-Circuit Timer DSCT [9:8] 01 R/W 08 R/W 14 R/W 02 R/W A0 R/W 44 R/W A0 R/W 44 R/W C8 R/W 60 R/W 1C CBMIN LSB Cell Balance Minimum Voltage CBMIN [7:0] 55 R/W 1D CBMIN MSB RSV 0A R/W 1E CBMAX LSB Cell Balance Maximum Voltage CBMAX [7:0] 70 R/W 1F CBMAX MSB RSV 0D R/W FN8889 Rev.3.00 Oct.14.19 RSV RSV RSV RSV RSV RSV Cell Balance Minimum Voltage CBMIN [B:8] Cell Balance Maximum Voltage CBMAX [B:8] Page 33 of 153 ISL94202 Table 2. 4. System Registers Register List (Continued) Bit Function Factory Default (Hex) Type Page # Register Address (Hex) 50 20 CBMIND LSB Cell Balance Minimum Delta Voltage CBMIND [7:0] 10 R/W 21 CBMIND MSB RSV 00 R/W 22 CBMAXD LSB Cell Balance Maximum Delta Voltage CBMAXD [7:0] AB R/W 23 CBMAXD MSB RSV 01 R/W 24 CBON LSB Cell Balance On-Time CBON [7:0] 02 R/W 25 CBONU, CBON MSB RSV 08 R/W 26 CBOFF LSB Cell Balance Off-Time CBOFF [7:0] 02 R/W 27 CBOFFU, CBOFF MSB RSV 08 R/W 28 CBUT LSB Cell Balance Under-Temperature Limit CBUT [7:0] F2 R/W 29 CBUT MSB RSV 0B R/W 2A CBUTR LSB Cell Balance Under-Temperature Recovery Level CBUTR [7:0] 93 R/W 2B CBUTR MSB RSV 0A R/W 2C CBOT LSB Cell Balance Over-Temperature Limit CBOT [7:0] B6 R/W 2D CBOT MSB RSV 04 R/W 2E CBOTR LSB Cell Balance Over-Temperature Recovery Level CBOTR [7:0] 3E R/W 2F CBOTR MSB RSV 05 R/W 51 52 53 53 54 55 56 56 57 58 58 59 60 61 Register Name 7 6 RSV RSV RSV RSV RSV RSV RSV RSV 5 RSV RSV RSV RSV RSV RSV RSV RSV 4 RSV RSV RSV RSV RSV RSV RSV RSV 3 2 1 0 Cell Balance Minimum Delta Voltage CBMIND [B:8] Cell Balance Maximum Delta Voltage CBMAXD [B:8] Cell Balance On Time Unit CBONU [1:0] Cell Balance Off Time Unit CBOFFU [1:0] Cell Balance On Time CBON [9:8] Cell Balance Off Time CBOFF [9:8] Cell Balance Under-Temperature Limit CBUT [B:8] Cell Balance Under-Temperature Recovery Level CBUTR [B:8] Cell Balance Over-Temperature Limit CBOT [B:8] Cell Balance Over-Temperature Recovery Level CBOTR [B:8] 30 COT LSB Charge Over-Temperature Limit COT [7:0] B6 R/W 31 COT MSB RSV 04 R/W 32 COTR LSB Charge Over-Temperature Recovery Level COTR [7:0] 3E R/W 33 COTR MSB RSV 05 R/W 34 CUT LSB Charge Under-Temperature Limit CUT [7:0] F2 R/W 35 CUT MSB RSV 0B R/W 36 CUTR LSB Charge Under-Temperature Recovery Level CUTR [7:0] 93 R/W 37 CUTR MSB RSV 0A R/W RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV Charge Over-Temperature Limit COT [B:8] Charge Over-Temperature Recovery Level COTR [B:8] Charge Under-Temperature Limit CUT [B:8] Charge Under-Temperature Recovery Level CUTR [B:8] 38 DOT LSB Discharge Over-Temperature Voltage DOT [7:0] B6 R/W 39 DOT MSB RSV 04 R/W 3A DOTR LSB Discharge Over-Temperature Recovery Level DOTR [7:0] 3E R/W 3B DOTR MSB RSV 05 R/W RSV RSV RSV RSV RSV RSV Discharge Over-Temperature Limit DOT [B:8] Discharge Over-Temperature Recovery Level DOTR [B:8] 3C DUT LSB Discharge Under-Temperature Limit DUT [7:0] F2 R/W 3D DUT MSB RSV 0B R/W FN8889 Rev.3.00 Oct.14.19 RSV RSV RSV Discharge Under-Temperature Limit DUT [B:8] Page 34 of 153 ISL94202 4. System Registers Table 2. Register List (Continued) Bit Function Factory Default (Hex) Type Page # Register Address (Hex) 61 3E DUTR LSB Discharge Under-Temperature Recovery Voltage DUTR [7:0] 93 R/W 3F DUTR MSB RSV 0A R/W 62 63 Register Name 7 6 RSV 5 4 RSV RSV 3 2 1 0 Discharge Under-Temperature Recovery Voltage DUTR [B:8] 40 IOT LSB Internal Over-Temperature Voltage Limit IOT [7:0] 64 R/W 41 IOT MSB RSV 06 R/W RSV RSV RSV Internal Over-temperature voltage Limit IOT [B:8] 42 IOTR LSB Internal Over-Temperature Recovery Voltage IOTR [7:0] 10 R/W 43 IOTR MSB RSV 06 R/W 44 VCELL SLV LSB VCELL SLEEP Level Voltage SLV [7:0] AA R/W 45 VCELL SLV MSB RSV 06 R/W 46 SDT LSB SLEEP Delay Timer SDT [7:0] 0F R/W 47 WDT, SDTU, SDT MSB Watchdog Timer WDT4 - WDT0 FC R/W 66 48 MODE_T SLEEP Mode MOD7 - MOD4 FF R/W 66 49 CELL_S Cell Select (Enable) CELL8 - CELL1 83 R/W 67 4A Setup 0 CFPSD RSV XT2M 68 4B Setup 1 CBDD CBDC DFOUV CFOOV UVLOPD RSV 64 64 4.1.1 RSV RSV RSV RSV RSV RSV Internal Over-temperature Recovery Voltage IOTR [B:8] VCELL SLEEP Level Voltage SLV [B:8] SLEEP Delay Timer SDT [8] SLEEP Delay Timer Unit SDTU[1:0] IDLE/DOZE Mode MOD3 - MOD0 TGain RSV(0) PCFET DOWD OWPSD 00 R/W RSV CBEOC 40 R/W 0x00-01 CDPW & VCELL OV The Charger Detection Pulse Width setting and upper 4 bits of the VCell Overvoltage threshold setting are stored at address 0x01. The lower 8 bits of the VCell Overvoltage threshold setting are stored at address 0x00. Table 3. CDPW & OV Bit Bit Name D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte COV7 COV6 COV5 COV4 COV3 COV2 COV1 COV0 Value 0 0 1 0 1 0 1 0 0x2A CDPW3 CDPW2 CDPW1 CDPW0 COVB COVA COV9 COV8 Value 0 0 0 1 1 1 1 0 0x1E 0x00 Default Bit Name 0x01 Default 4.1.1.1 VCELL OV The VCell Overvoltage threshold sets the upper operational voltage limit for enabled (“0x49 Cell Select” on page 67) cells. Each time a cell voltage is measured it is compared to this threshold. If any cell voltage rises above this threshold for longer than the setting of “0x10-11 VCELL OV Timer” on page 41, CFET is turned OFF and fault bit “0x80.0 OVF” on page 73 is set. This action is also dependent on the setting of register “0x4B.4 CFODOV” on page 69 and bits “0x87.6 µCFET” on page 82. The threshold “0x02-03 VCELL OVR” on page 36 sets the voltage level the cells must drop below before the OV fault clears and allows the CFET to turn back on. The threshold setting is 12-bits split across two 8-bit registers at addresses: • 0x00.[7:0]: Lower 8 bits • 0x01.[3:0]: Upper 4 bits FN8889 Rev.3.00 Oct.14.19 Page 35 of 153 ISL94202 4. System Registers The formula to convert the register decimal value to voltage is: REGval  1.8  8 V CELL OV = ---------------------------------------------4095  3 The default setting results in a threshold voltage of ~4.25V. To set the register decimal value to a desired threshold voltage use: V CELL OV  3  4095 REGval = ------------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. 4.1.1.2 0x01.7:4 CDPW The Charge Detection Pulse Width bits set the length of time the ISL94202 CHMON pin function is enabled. If the pin voltage is above the Charge Monitor Input threshold (“VCHMON” on page 16 or “VWKUP1” on page 19) at the end of the set time, the device assumes a charger is present and reacts accordingly. Each Least Significant Bit (LSB) is 1ms, which provides for a programmable range from 0ms to 15ms. The default setting is 1ms. This setting determines how long the charger connection node is loaded (“ILDMON” on page 16) by the “CHMON Pin (37)” on page 99. If a charger is present, the voltage remains above the threshold and a charger is detected. In the absence of a charger or other device that maintains the voltage under this load current, the voltage drops below the detection threshold and no charger is detected (see “0x82.1 CH_PRSNT” on page 77). 4.1.2 0x02-03 VCELL OVR The 12-bit VCELL Overvoltage Recovery threshold setting is shared between two registers. The upper 4 bits of the setting are stored in the lower 4 bits of 0x03 while the remaining 8 bits of OVR are stored in 0x02 as shown in Table 4. The upper 4 bits of register 0x03 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 4. Bit Bit Name 0x02 Default Bit Name 0x03 Default OVR D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 Value 1 1 0 1 0 1 0 0 0xD4 RSV RSV RSV RSV OVRB OVRA OVR9 OVR8 Value 0 0 0 0 1 1 0 1 0x0D The VCELLOVR setting must be less than the VCELLOV threshold for proper operation. The difference between OV and OVR settings functions as hysteresis. If an overvoltage fault (“0x80.0 OVF” on page 73) is detected, the cell voltages must drop below the OVR threshold for the setting “0x10-11 VCELL OV Timer” on page 41 for the fault bit to clear, then the device enables the power FETs (assuming no faults present). This action is also dependent on the setting of “0x4B.4 CFODOV” on page 69 and bit “0x87.6 µCFET” on page 82. The OVR threshold also sets the recovery voltage to clear and “0x80.1 OVLOF” on page 73 from “0x08-09 VCELL OVLO” on page 38 condition. The formula to convert the register decimal value to voltage is: REGval  1.8  8 V CELL OVR = ---------------------------------------------4095  3 The default results in a threshold setting of ~4.149V. FN8889 Rev.3.00 Oct.14.19 Page 36 of 153 ISL94202 4. System Registers To set the register decimal value to a desired threshold voltage use: V CELL OVR  3  4095 REGval = ----------------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. 4.1.3 0x04-05 LDPW & VCELL UV The Load Detect Pulse Width setting and the upper 4 bits of the VCELL Undervoltage threshold setting are stored at address 0x05 as shown in Table 5. The lower 8 bits of the VCELL Undervoltage threshold setting are stored at address 0x04. Table 5. Bit Bit Name 0x04 Default Bit Name 0x05 Default 4.1.3.1 LDPW & UV D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte UVT7 UVT6 UVT5 UVT4 UVT3 UVT2 UVT1 UVT0 Value 1 1 1 1 1 1 1 1 0xFF LDPW3 LDPW2 LDPW1 LDPW0 UVTB UVTA UVT9 UVT8 Value 0 0 0 1 0 1 1 1 0x18 VCELL UV The VCELL Undervoltage threshold sets the lower operational voltage limit for all cells. Each time a cell voltage is measured it is compared to this threshold. If any cell voltage falls below this threshold voltage for longer than the setting of “0x12-13 VCELL UV Timer” on page 42, DFET is turned OFF and fault bit “0x80.2 UVF” on page 72 is set. This action is also dependent on the setting of register “0x4B.5 DFODUV” on page 69 and bits “0x87.6 µCFET” on page 82. For recovery from this fault see “0x06-07 VCELL UVR” on page 38. The threshold setting is 12-bits split across two 8-bit registers at addresses: • 0x04.[7:0]: Lower 8 bits • 0x05.[3:0]: Upper 4 bits The formula to convert the register decimal value to voltage is: REGval  1.8  8 V CELL UV = ---------------------------------------------4095  3 The default results in a threshold setting of ~2.699V. To set the register decimal value to a desired threshold voltage use: V CELL UV  3  4095 REGval = -----------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. 4.1.3.2 0x05.7:4 LDPW The Load Detection Pulse Width bits set the length of time the ISL94202 LDMON pin function is enabled. If the pin voltage is below the Load Monitor Input threshold (“VLDMON” on page 16 or “VWKUP2” on page 19) at the end of the set time, the device assumes a load is present and reacts accordingly. Each LSB is 1ms, providing for a programmable range from 0ms to 15ms. The default setting is 1ms. This setting determines how long the load connection node is loaded (“ILDMON” on page 16) by the “LDMON Pin (38)” on page 104, if a load is present the voltage drops below the threshold and a load is detected. In the absence of a load the voltage remains above the detection threshold and no load is detected (see “0x82.0 LD_PRSNT” on page 77). FN8889 Rev.3.00 Oct.14.19 Page 37 of 153 ISL94202 4.1.4 4. System Registers 0x06-07 VCELL UVR The VCELL Undervoltage Recovery threshold setting is shared between two registers. The upper 4 bits of the UVR setting are stored in the lower 4 bits of 0x07 while the remaining 8 bits of OVR are stored in 0x06 as shown in Table 6. The upper 4 bits of register 0x07 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 6. UVR Bit Bit Name 0x06 Default Bit Name 0x07 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte UVR7 UVR6 UVR5 UVR4 UVR3 UVR2 UVR1 UVR0 Value 1 1 1 1 1 1 1 1 0xFF RSV RSV RSV RSV UVRB UVRA UVR9 UVR8 Value 0 0 0 0 1 0 0 0 0x09 The VCELLUVR setting must be greater than the VCELLUV threshold for proper operation. The difference between UV and UVR settings functions as hysteresis. If an undervoltage fault (“0x80.2 UVF” on page 72) is detected, the cell voltages must rise above the UVR threshold for the setting “0x12-13 VCELL UV Timer” on page 42 for the fault bit to clear, then the device enables the power FETs (assuming no faults present). This action is also dependent on the setting of “0x4B.5 DFODUV” on page 69 and bit “0x87.6 µCFET” on page 82. The UVR threshold also governs recovery from “0x0A-0B VCELL UVLO” on page 39. The formula to convert the register decimal value to voltage is: REGval  1.8  8 V CELL UVR = ---------------------------------------------4095  3 The default results in a threshold setting of ~3.0V. To set the register decimal value to a desired threshold voltage use: V CELL UVR  3  4095 REGval = ----------------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. 4.1.5 0x08-09 VCELL OVLO The VCELL Overvoltage Lockout threshold setting is shared between two registers. The upper 4 bits of the OVLO setting are stored in the lower 4 bits of 0x09 while the remaining 8 bits of OVLO are stored in 0x08 as shown in Table 7. The upper 4 bits of register 0x09 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 7. Bit Bit Name 0x08 Default Bit Name 0x09 Default OVLO D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte OVLO7 OVLO6 OVLO5 OVLO4 OVLO3 OVLO2 OVLO1 OVLO0 Value 0 1 1 0 1 1 1 1 0x7F RSV RSV RSV RSV OVLOB OVLOA OVLO9 OVLO8 Value 0 0 0 0 1 1 1 0 0x0E If any cell voltage rises above the VCELLOVLO threshold for 5 consecutive measurements, the device enters an Overvoltage Lockout condition. This causes the CFET/PCFET to turn OFF, bit “0x80.1 OVLOF” on page 73 is set, the cell balance FETs are turned OFF, and the “PSD Pin (32)” on page 98 is set to active high. Neither CFET or FN8889 Rev.3.00 Oct.14.19 Page 38 of 153 ISL94202 4. System Registers PCFET can be enabled during an OVLO. The OVLO function can be disabled by setting the OVLO threshold to 0x0FFF. VCELLOVLO must be set greater than VCELLOV for proper operation. Recovery is determined by the setting of “0x02-03 VCELL OVR” on page 36. Typically an Overvoltage Lockout is intended to flag a voltage considered too high to safely discharge. The formula for converting from register digital value to voltage is: REGval  1.8  8 V CELL OVLO = ---------------------------------------------4095  3 The default results in a threshold setting of ~3.0V. To set the register decimal value to a desired threshold voltage use: V CELL OVLO  3  4095 REGval = --------------------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. 4.1.6 0x0A-0B VCELL UVLO The VCELL Undervoltage Lockout threshold setting is shared between two registers. The upper 4 bits of the UVLO setting are stored in the lower 4 bits of 0x0B while the remaining 8 bits of UVLO are stored in 0x0A as shown in Table 8. The upper 4 bits of register 0x0B are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 8. Bit Bit Name 0x0A Default Bit Name 0x0B Default UVLO D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte UVLO7 UVLO6 UVLO5 UVLO4 UVLO3 UVLO2 UVLO1 UVLO0 Value 0 0 0 0 0 0 0 0 0x00 RSV RSV RSV RSV UVLOB UVLOA UVLO9 UVLO8 Value 0 0 0 0 0 1 1 0 0x06 If any cell voltage falls below the VCELLUVLO threshold for 5 consecutive measurements, the device enters an Undervoltage Lockout condition. This causes the DFET to turn OFF, bit “0x80.3 UVLOF” on page 72 is set, and the cell balance FETs are turned OFF. If bit “0x4B.3 UVLOPD” on page 70 is set to 1, a UVLO condition forces the part into the Powerdown State (“System Modes” on page 119). This action occurs regardless of the MCU FET control bits setting (“0x87.6 µCFET” on page 82). The UVLO function can be disabled by setting UVLO to 0x0000. VCELLUVLO must be set below VCELLUV for proper operation. Recovery is determined by the setting of “0x06-07 VCELL UVR” on page 38. Typically an Undervoltage Lockout is intended to flag a voltage considered to low to safely charge. The formula for converting from register digital value to voltage is: REGval  1.8  8V CELL UVLO = --------------------------------------------4095  3 The default results in a threshold setting of ~1.8V. FN8889 Rev.3.00 Oct.14.19 Page 39 of 153 ISL94202 4. System Registers To set the register decimal value to a desired threshold voltage use: V CELL UVLO  3  4095 REGval = --------------------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. 4.1.7 0x0C-0D VCELL EOC The VCELL End-of-Charge threshold (VEOC) setting is shared between two registers. The upper 4 bits of the VEOC setting are stored in the lower 4 bits of 0x0D while the remaining 8 bits of VEOC are stored in 0x0C as shown in Table 9. The upper 4 bits of register 0x0D are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 9. VEOC Bit Bit Name D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 Value 1 1 1 1 1 1 1 1 0xFF RSV RSV RSV RSV EOCB EOCA EOC9 EOC8 Value 0 0 0 0 1 1 0 1 0x0D 0x0C Default Bit Name 0x0D Default If any cell voltage rises above the VCELLEOC threshold, the device enters an End-of-Charge condition. This sets bit “0x81.7 VEOC” on page 73 and the “EOC Pin (35)” on page 99 is pulled low. The EOC output can signal an external MCU or enable an LED circuit to signal a fully charged pack. An VEOC condition also effects cell balancing operation, see “0x4B.0 CB_EOC” on page 70 for more information. The formula for converting from register digital value to voltage is: REGval  1.8  8 V CELL EOC = ---------------------------------------------4095  3 The default results in a threshold setting of ~4.199V. To set the register decimal value to a desired threshold voltage use: V CELL EOC  3  4095 REGval = ----------------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. 4.1.8 0x0E-0F VCELL LVCL The VCELL Low Voltage Charge Level setting is shared between two registers. The upper 4 bits of the LVCL setting are stored in the lower 4 bits of 0x0F while the remaining 8 bits of LVCL are stored in 0x0E as shown in Table 10. The upper 4 bits of register 0x0F are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 10. LVCL Bit Bit Name 0x0E Default Bit Name 0x0F Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte LVCL7 LVCL6 LVCL5 LVCL4 LVCL3 LVCL2 LVCL1 LVCL0 Value 1 0 1 0 1 0 1 0 0xAA RSV RSV RSV RSV LVCLB LVCLA LVCL9 LVCL8 Value 0 0 0 0 0 1 1 1 0x07 FN8889 Rev.3.00 Oct.14.19 Page 40 of 153 ISL94202 4. System Registers If any cell voltage falls below the VCELLLVCL, the device sets bit “0x82.7 LVCHG” on page 76 to 1. If any cell voltage falls below this level and “0x4A.2 PCFETE” on page 68 is set to 1, the device turns on the PCFET output instead of the CFET output to enable initial trickle charging of the cells. After the cell voltages rise above VCELLLVCL, CFET is enabled and PCFET is disabled. To disable the Pre-Charge FET function set bit PCFETE to 0 and set VCELLLVCL to 0x0000. The formula for converting from register digital value to voltage is: REGval  1.8  8 V CELL LVCL = ---------------------------------------------4095  3 The default results in a threshold setting of ~2.3V. To set the register decimal value to a desired threshold voltage use: V CELL LVCL  3  4095 REGval = -------------------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. 4.1.9 0x10-11 VCELL OV Timer The 12-bit VCELL Overvoltage Delay Timer setting is shared between two registers. The upper 4 bits of the OVDT setting are stored in the lower 4 bits of 0x11 while the remaining 8 bits of OVDT are stored in 0x10 as shown in Table 11. The upper 4 bits of register 0x11 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 11. OVDT Bit Bit Name 0x10 Default Bit Name 0x11 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte OVDT7 OVDT6 OVDT5 OVDT4 OVDT3 OVDT2 OVDT1 OVDT0 Value 0 0 0 0 0 0 0 1 0x01 RSV RSV RSV RSV OVDTU1 OVDTU0 OVDT9 OVDT8 Value 0 0 0 0 1 0 0 0 0x08 A VCELLOV condition (“VCELL OV” on page 35) must be present for at least the time specified by this setting for the device to enter an Overvoltage condition. The OVDT 12-bit value is split into a 2-bit unit selection value (“VCELL OVDTU” on page 41) and a 10-bit time value (“VCELL OVDT” on page 42). 4.1.9.1 VCELL OVDTU Bits 0x11.3 OVDTU1 and 0x11.2 OVDTU0 are the unit selection bits for the VCELLOVDT value. The following settings are available: • 00 - µsec • 01 - msec • 10 - sec (default) • 11 - min FN8889 Rev.3.00 Oct.14.19 Page 41 of 153 ISL94202 4. System Registers 4.1.9.2 VCELL OVDT The bits OVDT9 - OVDT0 set the 10-bit number of units value used to time an Overvoltage condition. The valid range is 0 - 1023. The 12-bit Timer setting is split across two 8-bit registers at addresses: • 0x10.[7:0]: Lower 8 bits - OVDT • 0x11.[1:0]: Upper 2 bits - OVDT • 0x11.[3:2]: 2 bit - OVDTU The default Timer is 1s. Multiply the 10-bit number of units value by the unit value to calculate the delay time. 4.1.10 0x12-13 VCELL UV Timer The 12-bit VCELL Undervoltage Delay Timer setting is shared between two registers. The upper 4 bits of the UVDT setting are stored in the lower 4 bits of 0x13 while the remaining 8 bits of UVDT are stored in 0x12 as shown in Table 12. The upper 4 bits of register 0x13 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 12. UVDT Bit Bit Name 0x12 Default Bit Name 0x13 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte UVDT7 UVDT6 UVDT5 UVDT4 UVDT3 UVDT2 UVDT1 UVDT0 Value 0 0 0 0 0 0 0 1 0x01 RSV RSV RSV RSV UVDTU1 UVDTU0 UVDT9 UVDT8 Value 0 0 0 0 1 0 0 0 0x08 A VCELLUV condition (“VCELL UV” on page 37) must be present for at least the time specified by this setting for the device to enter an Undervoltage condition. The UVDT 12-bit value is split into a 2-bit unit selection value (“VCELL UVDTU” on page 42) and a 10-bit time value (“VCELL UVDT” on page 42). 4.1.10.1 VCELL UVDTU Bits 0x13.3 UVDTU1 and 0x13.2 UVDTU0 are the unit selection bits of the UVDT value. The following settings are available: • 00 - µsec • 01 - msec • 10 - sec (default) • 11 - min 4.1.10.2 VCELL UVDT The bits UVDT9 - UVDT0 set the 10-bit number of units value used to time an Undervoltage condition. The valid range is 0 - 1023. The 12-bit Timer setting is split across two 8-bit registers at addresses: • 0x12.[7:0]: Lower 8 bits - UVDT • 0x13.[1:0]: Upper 2 bits - UVDT • 0x13.[3:2]: 2-bit - UVDTU The default Timer is 1s. Multiply the 10-bit number of units value by the unit value to calculate the delay time. FN8889 Rev.3.00 Oct.14.19 Page 42 of 153 ISL94202 4.1.11 4. System Registers 0x14-15 OWT The 10-bit Open-Wire Timing value sets the on-time of the open-wire test pulse and is shared between two registers. The 1-bit unit selector of the OWT setting (OWTU0) is stored in 0x15.[1]. The upper 1 bit of the OWT value is stored in 0x15.[0] and the remaining 8 bits of OWT value are stored in 0x14.[7:0] as shown in Table 13. The upper 6 bits of register 0x15 are reserved and should be ignored on read-back and set to 00 0000 when writing to the register. Table 13. OWT Bit Bit Name D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte OWT7 OWT6 OWT5 OWT4 OWT3 OWT2 OWT1 OWT0 Value 0 0 0 1 0 1 0 0 0x14 RSV RSV RSV RSV RSV RSV OWTU OWT8 Value 0 0 0 0 0 0 1 0 0x02 0x14 Default Bit Name 0x15 Default 4.1.11.1 OWTU Bit 0x15.1 OWTU is the unit selection bit of the OWT value. The following settings are available: • 0 - µsec • 1 - msec (default) 4.1.11.2 OWT The bits OWT8 - OWT0 set the 9-bit number of units value used to set the width of the open-wire pulse (see “Open Wire” on page 126). The valid range is 0 - 511. The 10-bit Timer setting is split across two 8-bit registers at addresses: • 0x14.[7:0]: Lower 8 bits - OWT • 0x15.[0]: Upper 1 bit - OWT • 0x15.[1]: 1-bit - OWTU The default Timer is 20ms. Multiply the 9-bit number of units value by the unit value to calculate the pulse width. 4.1.12 0x16-17 DOC & DOCT The Discharge Overcurrent threshold and its associated timer setting, Discharge Overcurrent Timing, are shared between two registers. These values set the requirements for the device to detect/indicate a Discharge Overcurrent condition. The 3-bit DOC threshold value is stored in 0x17.[6:4]. The 2-bit unit selector for the DOCT (DOCTU) is stored in 0x17.[3:2]. The upper 2-bits of the DOCT value is stored in the lower 2 bits of register 0x17 (0x17.[1:0]) and the lower 8-bits of the DOCT value is stored in register 0x16. This is shown in Table 14. The upper Most Significant Bit (MSB) of register 0x17 is reserved and should be ignored on read-back and set to 0 when writing to the register. Timing regarding a Discharge overcurrent condition and recovery can be seen in Figure 35 on page 45 and is described in detail in “DOCR” on page 45. Table 14. DOC Bit Bit Name 0x16 Default Bit Name 0x17 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte DOCT7 DOCT6 DOCT5 DOCT4 DOCT3 DOCT2 DOCT1 DOCT0 Value 1 0 1 0 0 0 0 0 0xA0 RSV DOC2 DOC1 DOC0 DOCTU1 DOCTU0 DOCT9 DOCT8 Value 0 1 0 0 0 1 0 0 0x44 FN8889 Rev.3.00 Oct.14.19 Page 43 of 153 ISL94202 4. System Registers A Discharge Overcurrent condition exists if the voltage across the external sense resistor exceeds the limits set by the DOC threshold for the time specified by DOCT & DOCTU. In a Discharge Overcurrent condition the DOC fault bit “0x81.2 DOCF” on page 74 and the Load Present bit “0x82.0 LD_PRSNT” on page 77 are both set to 1. If bit “0x87.6 µCFET” on page 82 is set to 0 (default), the Power FETs turn off automatically, otherwise the external MCU is responsible for turning off the Power FETs by clearing register bits “0x86.1 CFET” on page 81 and “0x86.0 DFET” on page 82. 4.1.12.1 0x17.[6:4] DOC The Discharge Overcurrent bits (DOC2 - DOC0) are a 3-bit selector used to set the voltage required across the current sense resistor to trigger a Discharge Overcurrent condition. The possible settings and their corresponding voltages are listed in Table 15. The default DOC threshold is 32mV with a range of 4mV to 96mV. Table 15. DOC Threshold Voltages Equivalent Current (A) DOC Setting Threshold (mV) 0.3mΩ 0.5mΩ 1mΩ 2mΩ 5mΩ 000 4 13.3 8 4 2 0.8 001 8 26.6 16 8 4 1.6 010 16 53.3 32 16 8 3.2 011 24 80 48 24 12 4.8 100 (default) 32 106.7 64 32 16 6.4 101 48 (Note 9) 96 48 24 9.6 110 64 (Note 9) (Note 9) 64 32 12.8 111 96 (Note 9) (Note 9) (Note 9) 48 19.2 Note: 9. These selections may not be reasonable due to sense resistor power dissipation. 4.1.12.2 0x17.[3:2] DOCTU The Discharge Overcurrent Timing Unit selection bits 0x17.3 DOCTU1 and 0x17.2 DOCTU0 set the DOCT time unit value. The following settings are available: • 00 - µsec • 01 - msec (default) • 10 - sec • 11 - min 4.1.12.3 0x16-17 DOCT The Discharge Overcurrent Timing bits DOCT9 - DOCT0 set the 10-bit number of units value used to define a Discharge Overcurrent condition. The valid range is 0 - 1023. The 12-bit Timer setting is split across two 8-bit registers at addresses: • 0x16.[7:0]: Lower 8 bits - DOCT • 0x17.[1:0]: Upper 2 bits - DOCT The default DOC Timer setting is 160ms. Multiply the 10-bit DOCT number of units value by the DOCTU unit value to calculate the delay time that must be exceeded to declare a Discharge Overcurrent condition. The timer selectable range is from 1µs to 1023 minutes. FN8889 Rev.3.00 Oct.14.19 Page 44 of 153 ISL94202 4.1.12.4 4. System Registers DOCR If the ISL94202 detects a DOC (or DSC) condition, the Discharge Overcurrent Recovery process begins. The load monitor circuit is enabled after ~3s and then the LDMON pin injects ~60µA (“ILDMON” on page 16) of current into the load for a duration of “0x05.7:4 LDPW” on page 37 every 256ms (see Figure 35). With a load present the LDMON pin voltage falls below threshold “VLDMON” on page 16 and bit “0x82.0 LD_PRSNT” on page 77 is set to 1. After the load is removed or rises to a sufficiently high resistance, the LDMON pin voltage rises above the threshold, which results in the LD_PRSNT bit clearing to 0. If the µCFET bit is set to 0 and the load monitor detects that the load has been removed (LD_PRSNT = 0), the power FETs are re-enabled (assuming no other faults) and the fault bit “0x81.2 DOCF” on page 74 is cleared. If the µCFET bit is set to 1 and LD_PRSNT along with the DOC fault bit clear, the external MCU must re-enable the FETs using bits “0x86.1 CFET” on page 81 and “0x86.0 DFET” on page 82. An external MCU can also override the load monitoring function by setting the bit “0x87.4 µCLMON” on page 83 to 1 and periodically pulsing the bit “0x86.6 LMON_EN” on page 80. When pulsing the LMON_EN bit, the MCU must also check the status of the LD_PRSNT bit. If the µCLMON bit is set to 1, the external MCU must set the bit “0x86.7 CLR_LERR” on page 80 to 1 to reset the DOC bit. When LD_PRSNT and DOC fault is cleared, the MCU can turn on the power FETs because the load has been removed. For more information on the load monitoring circuit, see “LDMON Pin (38)” on page 104. Example timing of a Discharge Overcurrent condition and Recovery is shown in Figure 35. Load Releases During This Time 256ms VLDMON 3s LDMON Pin Detects 2 LDMON Pulses Above Threshold VSC VOCD VDSENSE tSCD DOC Bit DSC Bit tSCD tOCD 1 0 1 0 2.5V SD Output µC Register 1 Read µC is Optional VDD+15V LDMON Detects Load Release Resets DOC, SCD Bit, Turns on FET µC Register 1 Read LDMON Detects Load Release Resets DOC, SCD Bit, Turns on FET DFET Output ISL94202 Turns on DFET (µCFET Bit = 0) Figure 35. DOC and DSC Recovery FN8889 Rev.3.00 Oct.14.19 Page 45 of 153 ISL94202 4.1.13 4. System Registers 0x18-19 COC & COCT The Charge Overcurrent threshold and its associated timer setting, Charge Overcurrent Timing, are shared between two registers. These values together set the requirements for the device to detect/indicate a Charge Overcurrent condition. The 3-bit COC threshold value is stored in 0x19.[6:4]. The 2-bit unit selector for the COCT (COCTU) is stored in 0x19.[3:2]. The upper 2 bits of the COCT value is stored in the lower 2 bits of register 0x19 (0x19.[1:0]) and the lower 8 bits of the COCT value is stored in register 0x18. This is shown in Table 16. The upper MSB of register 0x19 are reserved and should be ignored on read-back and set to 0 when writing to the register. Timing regarding a Charge Overcurrent condition and recovery can be seen in Figure 35 on page 45 and is described in detail in “COCR” on page 47. Table 16. COC Bit Bit Name 0x18 Default Bit Name 0x19 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte COCT7 COCT6 COCT5 COCT4 COCT3 COCT2 COCT1 COCT0 Value 1 0 1 0 0 0 0 0 0xA0 RSV COC2 COC1 COC0 COCTU1 COCTU0 COCT9 COCT8 Value 0 1 0 0 0 1 0 0 0x44 A Charge Overcurrent condition exists if the voltage across the external current sense resistor exceeds the limits set by COC threshold for the time specified by COCT & COCTU. In a Charge Overcurrent condition the fault bit “0x81.1 COCF” on page 75 and the bit “0x82.1 CH_PRSNT” on page 77 are both set to 1. If bit “0x87.6 µCFET” on page 82 is set to 0 (default), the Power FETs turn off automatically, otherwise the external MCU is responsible for turning off the Power FETs by clearing register bits 0x86.[1] for CFET and 0x86.[0] for DFET. 4.1.13.1 0x19.[6:4] COC The Charge Overcurrent bits (COC2 - COC0) are a 3-bit selector used to set the voltage required across the current sense resistor to trigger a Charge Overcurrent condition. The possible settings and their corresponding voltages are listed in Table 17. The default COC threshold is 8mV, with a range from 1mV to 24mV. Table 17. COC Threshold Voltages Equivalent Current (A) COC Setting Threshold (mV) 0.3mΩ 0.5mΩ 1mΩ 2mΩ 5mΩ 000 1 3.33 2 1 0.5 0.2 001 2 6.67 4 2 1 0.4 010 4 13.33 8 4 2 0.8 011 6 20 12 6 3 1.2 100 (default) 8 26.67 16 8 4 1.6 101 12 40 24 12 6 2.4 110 16 53.33 32 16 8 3.2 111 24 80 48 24 12 4.8 4.1.13.2 0x19.[3:2] COCTU The Charge Overcurrent Timing Unit selection bits 0x19.3 COCTU1 and 0x19.2 COCTU0 and set the COCT time unit value. The following settings are available: • 00 - µsec • 01 - msec (default) • 10 - sec • 11 - min FN8889 Rev.3.00 Oct.14.19 Page 46 of 153 ISL94202 4. System Registers 4.1.13.3 0x18-19 COCT The Charge Overcurrent Timing bits COCT9 - COCT0 set the 10-bit number of units value used to define a Charge Overcurrent condition. The valid range is 0 - 1023. The 12-bit Timer setting is split across two 8-bit registers at addresses: • 0x18.[7:0]: Lower 8 bits - COCT • 0x19.[1:0]: Upper 2 bits - COCT The default COC Timer setting is 160ms. Multiply the 10-bit COCT number of units value by the COCTU unit value to calculate the delay time that must be exceeded to declare a Charge Overcurrent condition. The timer selectable range is from 1µs to 1023 minutes. Charger Releases VCHMON Detects 2 CHMON Pulses Below Threshold CHMON Pin VCSENSE VOCC tOCC 1 0 COC Bit 2.5V SD Output Register 1 Read VDD+15V CFET Output CHMON Detects Charger Release Resets DOC, SCD Bit, Turns on FET ISL94202 Turns on CFET (µCFET Bit = 0) Figure 36. COC Recovery 4.1.13.4 COCR If the ISL94202 detects a Charge Overcurrent (COC) condition, the Charge Overcurrent Recovery process begins. The charger monitor circuit is enabled after ~3s, then the CHMON pin pulls ~60µA (“ILDMON” on page 16) of current from the charger node for a duration of “0x01.7:4 CDPW” on page 36 every 256ms (see Figure 36). With a charger present the CHMON pin voltage is above threshold “VCHMON” on page 16 and bit “0x82.1 CH_PRSNT” on page 77 is set to 1. After the charger is removed, the CHMON pin voltage drops below the threshold, resulting in the CH_PRSNT bit clearing to 0. If the µCFET bit is set to 0 and the charger monitor detects the charger has been removed for 2 consecutive sample periods (CH_PRSNT = 0), the power FETs are re-enabled (assuming no other faults) and the fault bit “0x81.1 COCF” on page 75 is cleared. If the µCFET bit is set to 1, the external MCU must re-enable the FETs using bits “0x86.1 CFET” on page 81 and “0x86.0 DFET” on page 82. An external MCU can override the charger monitoring function by setting the bit “0x87.3 µCCMON” on page 83 to 1 and periodically pulsing the bit “0x86.4 CMON_EN” on page 81. When pulsing the CMON_EN bit, the MCU must also check the status of the CH_PRSNT bit. If the µCCMON bit is set to 1, the external MCU must set the bit “0x86.5 CLR_CERR” on page 81 to 1 to reset the COC bit. When CH_PRSNT and COC fault is cleared, the MCU can turn on the power FETs because the charger has been removed. For more information on the charger detection circuit, see section “CHMON Pin (37)” on page 99. Example timing of a Charge Overcurrent condition and recovery is shown in Figure 36 on page 47. FN8889 Rev.3.00 Oct.14.19 Page 47 of 153 ISL94202 4.1.14 4. System Registers 0x1A-1B DSC & DSCT The Discharge Short-Circuit threshold and its associated timer setting, Discharge Short-Circuit Timing, are shared between two registers. These values set the requirements for the device to detect/indicate a Discharge Short-Circuit condition. The 3-bit DSC threshold value is stored in 0x1B.[6:4]. The 2-bit unit selector for the DSCT (DSCTU) is stored in 0x1B.[3:2]. The upper 2 bits of the DSCT value is stored in the lower 2 bits of register 0x1B (0x1B.[1:0]) and the lower 8 bits of the DSCT value is stored in register 0x1A. This is shown in Table 18. The upper MSB of register 0x1B are reserved and should be ignored on read-back and set to 0 when writing to the register. Timing regarding a Discharge overcurrent condition and recovery can be seen in Figure 35 on page 45 and is described in detail in “DSCR” on page 49. Table 18. DSC Bit Bit Name 0x1A Default Bit Name 0x1B Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte DSCT7 DSCT6 DSCT5 DSCT4 DSCT3 DSCT2 DSCT1 DSCT0 Value 1 1 0 0 1 0 0 0 0xC8 RSV DSC2 DSC1 DSC0 DSCTU1 DSCTU0 DSCT9 DSCT8 Value 0 1 1 0 0 0 0 0 0x60 A Discharge Short-Circuit condition exists if the voltage across the external sense resistor exceeds the limits set by DSC threshold for the time specified by DSCT & DSCTU. In a Discharge Short-Circuit condition the DSC fault bit “0x81.3 DSCF” on page 74 and the LD_PRSNT bit “0x82.0 LD_PRSNT” on page 77 are both set to 1. During a Discharge Short-Circuit Condition the power FETs turn off regardless of the condition of bit “0x87.6 µCFET” on page 82. 4.1.14.1 0x1B.[6:4] DSC The Discharge Short-Circuit bits (DSC2 - DSC0) are a 3-bit selector used to set the voltage required across the current sense resistor to trigger a Discharge Short-Circuit condition. The possible settings and their corresponding voltages are listed in Table 19. The default DSC threshold is 128mV, with a range from 16mV to 256mV. Table 19. DSC Threshold Voltages Equivalent Current (A) DSC Setting Threshold (mV) 0.3mΩ 0.5mΩ 1mΩ 2mΩ 5mΩ 000 16 53.3 32 16 8 3.2 001 24 80 48 24 12 4.8 010 32 106.67 64 32 16 6.4 011 48 160 96 48 24 9.6 100 64 213.33 128 64 32 12.8 101 96 (Note 10) 192 96 48 19.2 110 (default) 128 (Note 10) (Note 10) 128 64 25.6 111 256 (Note 10) (Note 10) (Note 10) 128 51.2 Note: 10. These selections may not be reasonable due to sense resistor power dissipation. 4.1.14.2 0x1B.[3:2] DSCTU The Discharge Short-Circuit Timing Unit selection bits 0x1B.3 DSCTU1 and 0x1B.2 DSCTU0 set the DSCT time unit value. The following settings are available: • 00 - µsec (default) • 01 - msec • 10 - sec • 11 - min FN8889 Rev.3.00 Oct.14.19 Page 48 of 153 ISL94202 4.1.14.3 4. System Registers 0x1B.[1:0] - 0x1A.[7:0] DSCT The Discharge Short-Circuit Timing bits DSCT9 - DSCT0 set the 10-bit number of units value used to define a Discharge Short-Circuit condition. The valid range is 0 - 1023. The 12-bit Timer setting is split across two 8-bit registers at addresses: • 0x1A.[7:0]: Lower 8 bits - DSCT • 0x1B.[1:0]: Upper 2 bits - DSCT The default DSC Timer setting 200µs. Multiply the 10-bit DSCT number of units value by the DSCTU unit value to calculate the delay time that must be exceeded to declare a Discharge Short-Current condition. The timer selectable range is from 1µs to 1023 minutes. 4.1.14.4 DSCR If the ISL94202 detects a DSC (or DOC) condition the Discharge Overcurrent Recovery process begins. The load monitor circuit is enabled after ~3s and the LDMON pin injects ~60µA (“ILDMON” on page 16) of current into the load for a duration of “0x05.7:4 LDPW” on page 37 every 256ms (see Figure 35). With a load present the LDMON pin, voltage falls below threshold “VLDMON” on page 16 and bit “0x82.0 LD_PRSNT” on page 77 is set to 1. After the load is removed or rises to a sufficiently high resistance, the LDMON pin voltage rises above the threshold, resulting in the LD_PRSNT bit clearing to 0. If the µCFET bit is set to 0 and the load monitor detects the load has been removed (LD_PRSNT = 0), the power FETs are re-enabled (assuming no other faults) and the fault bit “0x81.3 DSCF” on page 74 is cleared. If the µCFET bit is set to 1 and LD_PRSNT along with the DSC fault bit clear, the external MCU must re-enable the FETs using bits “0x86.1 CFET” on page 81 and “0x86.0 DFET” on page 82. An external MCU can also override the load monitoring function by setting the bit “0x87.4 µCLMON” on page 83 to 1 and periodically pulsing the bit “0x86.6 LMON_EN” on page 80. When pulsing the LMON_EN bit, the MCU must also check the status of the LD_PRSNT bit. If the µCLMON bit is set to 1, the external MCU must set the bit “0x86.7 CLR_LERR” on page 80 to 1 to reset the DSC bit. When LD_PRSNT and DSC fault is cleared, the MCU can turn on the power FETs because the load has been removed. For more information on the load monitoring circuit, see section “LDMON Pin (38)” on page 104. Example timing of a Discharge Overcurrent condition and Recovery is shown in Figure 35 on page 45. 4.1.15 0x1C-1D CBMIN The 12-bit Cell Balance Minimum voltage threshold setting is shared between two registers. The upper 4 bits of the CBMIN setting are stored in the lower 4 bits of 0x1D while the remaining 8 bits of CBMIN are stored in 0x1C as shown in Table 20. The upper 4 bits of register 0x1D are reserved, it should be ignored on read-back and set to 0000 when writing to the register. Table 20. CBMIN Bit Bit Name 0x1C Default Bit Name 0x1D Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CBMIN7 CBMIN6 CBMIN5 CBMN4 CBMIN3 CBMIN2 CBMIN1 CBMIN0 Value 0 1 0 1 0 1 0 1 0x55 RSV RSV RSV RSV CBMINB CBMINA CBMIN9 CBMIN8 Value 0 0 0 0 1 0 1 0 0x0A Cell Balancing is inhibited and the bit “0x83.3 CBUV” on page 78 is set to 1 if all cell voltages are below this threshold. This is a Cell Balance Undervoltage condition. At least one cell voltage must rise above the CBMIN threshold to recover from a Cell Balance Undervoltage condition and clear the CBUV bit. FN8889 Rev.3.00 Oct.14.19 Page 49 of 153 ISL94202 4. System Registers The formula for converting from register digital value to voltage is: REGval  1.8  8 CBMIN = ---------------------------------------------4095  3 The default results in a threshold setting of ~3.1V. To set the register decimal value to a desired threshold voltage use: CBMIN  3  4095 REGval = -------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. See “Cell Balancing” on page 122 for more information on cell balancing operation. 4.1.16 0x1E-1F CBMAX The 12-bit Cell Balance Maximum voltage threshold setting is shared between two registers. The upper 4 bits of the CBMAX setting are stored in the lower 4 bits of 0x1F while the remaining 8 bits of CBMAX are stored in 0x1E as shown in Table 21. The upper 4 bits of register 0x1F are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 21. CBMAX Bit Bit Name 0x1E Default Bit Name 0x1F Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CBMAX7 CBMAX6 CBMAX5 CBMAX4 CBMAX3 CBMAX2 CBMAX1 CBMAX0 Value 0 1 1 1 0 0 0 0 0x70 RSV RSV RSV RSV CBMAXB CBMAXA CBMAX9 CBMAX8 Value 0 0 0 0 1 1 0 1 0x0D Cell Balancing is inhibited and the bit “0x83.2 CBOV” on page 78 is set to 1 if all cell voltages are above this threshold. This is a Cell Balance Overvoltage condition. At least one cell voltage must drop below the CBMAX threshold to recover from a Cell Balance Overvoltage condition and clear the CBOV bit. The formula for converting from register digital value to voltage is: REGval  1.8  8CBMAX = --------------------------------------------4095  3 The default results in a threshold setting of ~4.03V. To set the register decimal value to a desired threshold voltage use:  3  4095REGval = CBMAX --------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. See “Cell Balancing” on page 122 for more information on cell balancing operation. 4.1.17 0x20-21 CBMINDV The 12-bit Cell Balance Minimum Differential Voltage threshold setting is shared between two registers. The upper 4 bits of the CBMINDV setting are stored in the lower 4 bits of 0x21 while the remaining 8 bits of CBMINDV are stored in 0x20 as shown in Table 22 on page 51. The upper 4 bits of register 0x21 are reserved and should be ignored on read-back and set to 0000 when writing to the register. FN8889 Rev.3.00 Oct.14.19 Page 50 of 153 ISL94202 4. System Registers Table 22. CBMINDV Bit D[7] Bit Name D[6] D[5] D[4] CBMINDV7 CBMINDV6 CBMINDV5 CBMINDV4 0x20 Default Bit Name 0x21 Default D[3] CBMINDV3 0 0 0 1 0 RSV RSV RSV RSV CBMINDVB 0 0 0 0 0 D[2] D[1] D[0] CBMINDV2 CBMINDV1 CBMINDV0 0 0 0 0 Value 0x10 CBMINDVA CBMINDV9 CBMINDV8 0 Byte 0 Value 0x00 If the difference between CELLN and the lowest voltage cell is less than this value, cell balancing for CELLN is disabled. Conversely, if the voltage difference between CELLN and the lowest voltage cell is between CBMINDV and “0x22-23 CBMAXDV” on page 51, cell balancing of CELLN is enabled. Note: Cell balancing for CELLN is not enabled if its voltage is less than CBMIN or greater than CBMAX. The formula for converting from register digital value to voltage is: REGval  1.8  8CBMINDV = --------------------------------------------4095  3 The default results in a threshold setting of ~18.75mV. To set the register decimal value to a desired threshold voltage use:  3  4095REGval = CBMINDV ---------------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Voltage measurement accuracy is specified to ±10mV at room temperature. Setting CBMINDV to less than 10mV can result in cell balance algorithm non-convergence and is not recommended. See “Cell Balancing” on page 122 for more information on cell balancing operation. 4.1.18 0x22-23 CBMAXDV The 12-bit Cell Balance Maximum Differential Voltage threshold setting is shared between two registers. The upper 4 bits of the CBMAXDV setting are stored in the lower 4 bits of 0x23 while the remaining 8 bits of CBMAXDV are stored in 0x22 as shown in Table 23. The upper 4 bits of register 0x23 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 23. CBMAXDV Bit Bit Name 0x22 Default Bit Name 0x23 Default D[7] D[6] CBMAXDV7 CBMAXDV6 D[5] D[4] CBMAXDV 5 CBMAXDV 4 1 0 1 0 RSV RSV RSV RSV 0 0 0 0 D[3] D[2] D[1] D[0] CBMAXDV3 CBMAXDV2 CBMAXDV1 CBMAXDV0 1 0 1 1 CBMAXDVB CBMAXDVA CBMAXDV9 CBMAXDV8 0 0 0 1 Byte Value 0xAB Value 0x01 If the difference between CELLN and the lowest voltage cell is larger than “0x20-21 CBMINDV” on page 50, and the voltage on CELLN is between CBMINDV and CBMAXDV, cell balancing of CELLN is enabled. Note: Cell balancing for CELLN is not enabled if its voltage is less than CBMIN or greater than CBMAX. Conversely, if the difference between CELLN and the lowest voltage cell is larger than CBMAXDV, cell balancing for CELLN is disabled and the fault bit “0x81.4 CELLF” on page 74 is set to 1. This is considered a serious fault leading to the pack being disabled. A CELLF condition triggers the ISL94202 to test for an “Open Wire” on page 126. FN8889 Rev.3.00 Oct.14.19 Page 51 of 153 ISL94202 4. System Registers The formula for converting from register digital value to voltage is: REGval  1.8  8 CBMAXDV = ---------------------------------------------4095  3 The default results in a threshold setting of ~500mV. To set the register decimal value to a desired threshold voltage use: CBMAXDV  3  4095 REGval = ------------------------------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. See “Cell Balancing” on page 122 for more information on cell balancing operation. 4.1.19 0x24-25 CBON Timer The 12-bit Cell Balance On Time value is shared between two registers. The 2-bit unit selector for CBON (CBONU) is stored in 0x25.[3:2]. The upper 2 bits of the CBON value is stored in the lower 2 bits of register 0x25 and the lower 8 bits of the CBON value is stored in register 0x24. This is shown in Table 24. The upper 4 bits of register 0x25 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 24. CBON Bit Bit Name 0x24 Default Bit Name 0x25 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CBON7 CBON6 CBON5 CBON4 CBON3 CBON2 CBON1 CBON0 Value 0 0 0 0 0 0 1 0 0x02 RSV RSV RSV RSV CBONU1 CBONU0 CBON9 CBON8 Value 0 0 0 0 1 0 0 0 0x08 This setting determines how long the cell balancing outputs are turned ON during a cell balancing cycle. See “Cell Balancing” on page 122 for more information on cell balancing operation. 4.1.19.1 0x25.[3:2] CBONU The Cell Balance On-Time Unit selection bits 0x25.3 CBONU1 and 0x25.2 CBONU0 set the CBON time unit value. The following settings are available: • 00 - µsec • 01 - msec • 10 - sec (default) • 11 - min 4.1.19.2 0x24-25 CBON The Cell Balance On-Time bits CBON9 - CBON0 set the 10-bit number of units value used to define the Cell Balance On-Time. The valid range is 0 - 1023. The 12-bit Timer setting is split across two 8-bit registers at addresses: • 0x24.[7:0]: Lower 8 bits - CBON • 0x25.[1:0]: Upper 2 bits - CBON The default CBON period is 2s. Multiply the 10-bit CBON number of units value by the CBONU unit value to calculate the time the CB pins are enabled in each cycle of Cell Balancing. FN8889 Rev.3.00 Oct.14.19 Page 52 of 153 ISL94202 4.1.20 4. System Registers 0x26-27 CBOFF Timer The 12-bit Cell Balance Off-Time value is shared between two registers. The 2-bit unit selector for CBOFF (CBOFFU) is stored in 0x27.[3:2]. The upper 2 bits of the CBOFF value is stored in the lower 2 bits of register 0x27 and the lower 8 bits of the CBOFF value is stored in register 0x26. This is shown in Table 25. The upper 4 bits of register 0x27 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 25. CBOFF Bit Bit Name 0x26 Default Bit Name 0x27 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CBOFF7 CBOFF6 CBOFF5 CBOFF4 CBOFF3 CBOFF2 CBOFF1 CBOFF0 Value 0 0 0 0 0 0 1 0 0x02 RSV RSV RSV RSV CBOFFU1 CBOFFU0 CBOFF9 CBOFF8 Value 0 0 0 0 1 0 0 0 0x08 This setting determines how long the cell balancing outputs are turned OFF following a cell balancing cycle. The CBOFF setting should be long enough to allow the ISL94202 to complete at least two measurement scans after the CB FETs have been turned off and all CB induced transients have settled out. If CBOFF is too short, internal decisions on which cells to balance can be made during a CBON period (or during post CB transients). This can lead to poor results. CBOFF also allows time for the CB FETs to cool. See “Cell Balancing” on page 122 for more information on cell balancing operation. 4.1.20.1 CBOFFU The Cell Balance Off-Time Unit selection bits 0x27.3 CBOFFU1 and 0x27.2 CBOFFU0 set the CBOFF time unit value. The following settings are available: • 00 - µsec • 01 - msec • 10 - sec (default) • 11 - min 4.1.20.2 CBOFF The Cell Balance Off-Time bits CBOFF9 - CBOFF0 set the 10-bit number of units value used to define the Cell Balance Off time. The valid range is 0 - 1023. The 12-bit Timer setting is split across two 8-bit registers at addresses: • 0x26.[7:0]: Lower 8 bits - CBOFF • 0x27.[1:0]: Upper 2 bits - CBOFF The default CBOFF period is 2s. Multiply the 10-bit CBOFF number of units value by the CBOFFU unit value to calculate the time the CB pins are disabled following each cycle of Cell Balancing 4.1.21 0x28-29 CBUT The Cell Balance Under-Temperature threshold setting is shared between two registers. The upper 4 bits of the CBUT setting are stored in the lower 4 bits of 0x29 while the remaining 8 bits of CBUT are stored in 0x28 as shown in Table 26 on page 54. The upper 4 bits of register 0x29 are reserved and should be ignored on read-back and set to 0000 when writing to the register. FN8889 Rev.3.00 Oct.14.19 Page 53 of 153 ISL94202 4. System Registers Table 26. CBUT Bit Bit Name 0x28 Default Bit Name 0x29 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CBUT7 CBUT6 CBUT5 CBUT4 CBUT3 CBUT2 CBUT1 CBUT0 Value 1 1 1 1 0 0 1 0 0xF2 RSV RSV RSV RSV CBUTB CBUTA CBUT9 CBUT8 Value 0 0 0 0 1 0 1 1 0x0B The ISL94202 is designed for use with an NTC thermistor. If the voltage measured at either of the “Thermistor Pins (20-22)” on page 96 is greater than the CBUT threshold, the fault bit “0x83.1 CBUTF” on page 78 is set to 1. Given an NTC thermistor, this means that when the measured temperature at either thermistor input is less than the value represented by this register a fault is declared. Given a CBUT fault, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), cell balancing is disabled, otherwise an external MCU is responsible for ceasing cell balancing (see “MCU CB” on page 126). For recovery from this fault see “0x2A-2B CBUTR” on page 54. The CBUTR setting must be less than the CBUT value. The formula for converting from register digital value to voltage is:  1.8CBUT = REGval -----------------------------------4095 The default results in a threshold setting of ~1.344V (-10°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use:  4095REGval = CBUT -----------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. For more information on cell balancing operation see “Cell Balancing” on page 122. 4.1.22 0x2A-2B CBUTR The Cell Balancing Under-Temperature Recovery threshold setting is shared between two registers. The upper 4 bits of the CBUTR setting are stored in the lower 4 bits of 0x2B while the remaining 8 bits of CBUTR are stored in 0x2A as shown in Table 27. The upper 4 bits of register 0x2B are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 27. CBUTR Bit Bit Name 0x2A Default Bit Name 0x2B Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CBUTR7 CBUTR6 CBUTR5 CBUTR4 CBUTR3 CBUTR2 CBUTR1 CBUTR0 Value 1 0 0 1 0 0 1 1 0x93 RSV RSV RSV RSV CBUTRB CBUTRA CBUTR9 CBUTR8 Value 0 0 0 0 1 0 1 0 0x0A The ISL94202 is designed for use with an NTC thermistor. The CBUTR setting must be less than the CBUT value. If the voltage measured at both of the “Thermistor Pins (20-22)” on page 96 is less than the CBUTR value, and the device previously detected a Cell Balance Under-Temperature condition (“0x28-29 CBUT” on page 53), the fault bit “0x83.1 CBUTF” on page 78 is cleared to 0. Given an NTC thermistor, this means that when the measured temperature at either thermistor input is greater than the value represented by this register the previously existing fault is cleared. FN8889 Rev.3.00 Oct.14.19 Page 54 of 153 ISL94202 4. System Registers When the CBUT fault is cleared, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), cell balancing is re-enabled (subject to meeting all other conditions of cell balancing). Otherwise an external MCU is responsible for restarting cell balancing (see “MCU CB” on page 126). The formula for converting from register digital value to voltage is: REGval  1.8 CBUTR = ------------------------------------4095 The default results in a threshold setting of ~1.19V (+5°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use: CBUTR  4095 REGval = ----------------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see 0x4A.4 TGAIN. For more information on cell balancing operation see “Cell Balancing” on page 122. 4.1.23 0x2C-2D CBOT The Cell Balancing Over-Temperature threshold setting is shared between two registers. The upper 4 bits of the CBOT setting are stored in the lower 4 bits of 0x2D while the remaining 8 bits of CBOT are stored in 0x2C as shown in Table 28. The upper 4 bits of register 0x2D are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 28. CBOT Bit Bit Name 0x2C Default Bit Name 0x2D Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CBOT7 CBOT6 CBOT5 CBOT4 CBOT3 CBOT2 CBOT1 CBOT0 Value 1 0 1 1 0 1 1 0 0xB6 RSV RSV RSV RSV CBOTB CBOTA CBOT9 CBOT8 Value 0 0 0 0 0 1 0 0 0x04 The ISL94202 is designed for use with an NTC thermistor. If the voltage measured at either of the “Thermistor Pins (20-22)” on page 96 is less than the CBOT threshold, the fault bit “0x83.0 CBOTF” on page 78 is set to 1. Given an NTC thermistor, this means that when the measured temperature at either thermistor input is greater than the value represented by this register a fault is declared. Given a CBOT fault, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), cell balancing is disabled, otherwise an external MCU is responsible for ceasing cell balancing (see “MCU CB” on page 126). For recovery from this fault see “0x2E-2F CBOTR” on page 56. The CBOTR setting must be greater than the CBOT value. The formula for converting from register digital value to voltage is: REGval  1.8 CBOT = ------------------------------------4095 The default results in a threshold setting of ~0.53V (+55°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use: CBOT  4095REGval = -----------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. For more information on cell balancing operation see “Cell Balancing” on page 122. FN8889 Rev.3.00 Oct.14.19 Page 55 of 153 ISL94202 4.1.24 4. System Registers 0x2E-2F CBOTR The Cell Balancing Over-Temperature Recovery threshold setting is shared between two registers. The upper 4 bits of the CBOTR setting are stored in the lower 4 bits of 0x2F while the remaining 8 bits of CBOTR are stored in 0x2E as shown in Table 29. The upper 4 bits of register 0x2F are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 29. CBOTR Bit Bit Name D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CBOTR7 CBOTR6 CBOTR5 CBOTR4 CBOTR3 CBOTR2 CBOTR1 CBOTR0 Value 0 0 1 1 1 1 1 0 0x3E RSV RSV RSV RSV CBOTRB CBOTRA CBOTR9 CBOTR8 Value 0 0 0 0 0 1 0 1 0x05 0x2E Default Bit Name 0x2F Default The ISL94202 is designed for use with an NTC thermistor. The CBOTR setting must be greater than the CBOT value. If the voltage measured at both “Thermistor Pins (20-22)” on page 96 is greater than the CBOTR value, and the device previously detected a Cell Balance Over-Temperature condition, the fault bit “0x83.0 CBOTF” on page 78 is cleared to 0. Given an NTC thermistor, this means that when the measured temperature at both thermistor inputs is less than the value represented by this register the previously existing fault is cleared. When the CBOT fault is cleared, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), cell balancing is re-enabled (subject to meeting all other conditions of cell balancing), otherwise an external MCU is responsible for restarting cell balancing (see “MCU CB” on page 126). The formula for converting from register digital value to voltage is: REGval  1.8CBOTR = -----------------------------------4095 The default results in a threshold setting of ~0.59V (+50°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use: CBOTR  4095REGval = ----------------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. For more information on cell balancing operation see “Cell Balancing” on page 122. 4.1.25 0x30-31 COT The Charge Over-Temperature threshold setting is shared between two registers. The upper 4 bits of the COT setting are stored in the lower 4 bits of 0x31 while the remaining 8 bits of COT are stored in 0x30 as shown in Table 30. The upper 4 bits of register 0x31 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 30. COT Bit Bit Name 0x30 Default Bit Name 0x31 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte COT7 COT6 COT5 COT4 COT3 COT2 COT1 COT0 Value 1 0 1 1 0 1 1 0 0xB6 RSV RSV RSV RSV COTB COTA COT9 COT8 Value 0 0 0 0 0 1 0 0 0x04 The ISL94202 is designed for use with an NTC thermistor. FN8889 Rev.3.00 Oct.14.19 Page 56 of 153 ISL94202 4. System Registers If the voltage measured at either of the “Thermistor Pins (20-22)” on page 96 is less than the COT threshold, the fault bit “0x80.6 COTF” on page 71 is set to 1. Given an NTC thermistor, this means that when the measured temperature at either thermistor input is greater than the value represented by this register a fault is declared. Given a COT fault, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default) then CFET/PCFET and cell balancing is disabled automatically, otherwise an external MCU is responsible for shutting off the CFET (“0x86.1 CFET” on page 81) and ceasing cell balancing (see “MCU CB” on page 126). For recovery from this fault see “0x32-33 COTR” on page 57. The COTR setting must be greater than the COT value. The formula for converting from register digital value to voltage is: REGval  1.8 COT = ------------------------------------4095 The default results in a threshold setting of ~0.53V (+55°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use:  4095REGval = COT -------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. 4.1.26 0x32-33 COTR The Charge Over-Temperature Recovery threshold setting is shared between two registers. The upper 4 bits of the COTR setting are stored in the lower 4 bits of 0x33 while the remaining 8 bits of COTR are stored in 0x32 as shown in Table 31. The upper 4 bits of register 0x33 are reserved, it should be ignored on read-back and set to 0000 when writing to the register. Table 31. COTR Bit Bit Name 0x32 Default Bit Name 0x33 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte COTR7 COTR6 COTR5 COTR4 COTR3 COTR2 COTR1 COTR0 Value 0 0 1 1 1 1 1 0 0x3E RSV RSV RSV RSV COTRB COTRA COTR9 COTR8 Value 0 0 0 0 0 1 0 1 0x05 The ISL94202 is designed for use with an NTC thermistor. The COTR setting must be greater than the COT value. If the voltage measured at both “Thermistor Pins (20-22)” on page 96 is greater than the COTR value, and the device previously detected a Charge Over-Temperature condition, the fault bit “0x80.6 COTF” on page 71 is cleared to 0. Given an NTC thermistor, this means that when the measured temperature at both thermistor inputs is less than the value represented by this register the previously existing fault is cleared. When the COT fault is cleared, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), CFET/PCFET and cell balancing are re-enabled (subject to meeting all other conditions), otherwise an external MCU is responsible for enabling CFET (“0x86.1 CFET” on page 81) and restarting cell balancing (see “MCU CB” on page 126). The formula for converting from register digital value to voltage is:  1.8COTR = REGval -----------------------------------4095 The default results in a threshold setting of ~0.59V (+50°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). FN8889 Rev.3.00 Oct.14.19 Page 57 of 153 ISL94202 4. System Registers To set the register decimal value to a desired threshold voltage use: COTR  4095 REGval = ------------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. 4.1.27 0x34-35 CUT The Charge Under-Temperature threshold setting is shared between two registers. The upper 4 bits of the CUT setting are stored in the lower 4 bits of 0x35 while the remaining 8 bits of CUT are stored in 0x34 as shown in Table 32. The upper 4 bits of register 0x35 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 32. CUT Bit Bit Name 0x34 Default Bit Name 0x35 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CUT7 CUT6 CUT5 CUT4 CUT3 CUT2 CUT1 CUT0 Value 1 1 1 1 0 0 1 0 0xF2 RSV RSV RSV RSV CUTB CUTA CUT9 CUT8 Value 0 0 0 0 1 0 1 1 0x0B The ISL94202 is designed for use with an NTC thermistor. If the voltage measured at either of the “Thermistor Pins (20-22)” on page 96 is greater than the CUT threshold, the fault bit “0x80.7 CUTF” on page 71 is set to 1. Given an NTC thermistor, this means that when the measured temperature at either thermistor input is less than the value represented by this register a fault is declared. Given a CUT fault, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), CFET/PCFET is shut off and cell balancing is disabled automatically, otherwise an external MCU is responsible for shutting off the power FET (“0x86.1 CFET” on page 81) and ceasing cell balancing (see “MCU CB” on page 126). For recovery from this fault see “0x36-37 CUTR” on page 58. The CUTR setting must be less than the CUT value. The formula for converting from register digital value to voltage is: REGval  1.8CUT = -----------------------------------4095 The default results in a threshold setting of ~1.344V (-10°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use:  4095REGval = CUT ------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. 4.1.28 0x36-37 CUTR The Charge Under-Temperature Recovery threshold setting is shared between two registers. The upper 4 bits of the CUTR setting are stored in the lower 4 bits of 0x37 while the remaining 8 bits of CUTR are stored in 0x36 as shown in Table 33 on page 59. The upper 4 bits of register 0x37 are reserved, it should be ignored on read-back and set to 0000 when writing to the register. FN8889 Rev.3.00 Oct.14.19 Page 58 of 153 ISL94202 4. System Registers Table 33. CUTR Bit Bit Name D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CUTR7 CUTR6 CUTR5 CUTR4 CUTR3 CUTR2 CUTR1 CUTR0 Value 1 0 0 1 0 0 1 1 0x93 RSV RSV RSV RSV CUTRB CUTRA CUTR9 CUTR8 Value 0 0 0 0 1 0 1 0 0x0A 0x36 Default Bit Name 0x37 Default The ISL94202 is designed for use with an NTC thermistor. The CUTR setting must be less than the CUT value. If the voltage measured at both of the “Thermistor Pins (20-22)” on page 96 is less than the CUTR value, and the device previously detected a Cell Under-Temperature condition (“0x34-35 CUT” on page 58), the fault bit “0x80.7 CUTF” on page 71 is cleared to 0. Given an NTC thermistor, this means that when the measured temperature at both thermistor inputs is greater than the value represented by this register the previously existing fault is cleared. When a CUT fault is cleared, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), CFET/PCFET and cell balancing are re-enabled (subject to meeting all other conditions), otherwise an external MCU is responsible for enabling CFET (“0x86.1 CFET” on page 81) and restarting cell balancing (see “MCU CB” on page 126). The formula for converting from register digital value to voltage is:  1.8CUTR = REGval -----------------------------------4095 The default results in a threshold setting of ~1.19V (+5°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use: CUTR  4095 REGval = ------------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. 4.1.29 0x38-39 DOT The Discharge Over-Temperature threshold Setting is shared between two registers. The upper 4 bits of the DOT setting are stored in the lower 4 bits of 0x39 while the remaining 8 bits of DOT are stored in 0x38 as shown in Table 34. The upper 4 bits of register 0x39 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 34. DOT Bit Bit Name 0x38 Default Bit Name 0x39 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte DOT7 DOT6 DOT5 DOT4 DOT3 DOT2 DOT1 DOT0 Value 1 0 1 1 0 1 1 0 0xB6 RSV RSV RSV RSV DOTB DOTA DOT9 DOT8 Value 0 0 0 0 0 1 0 0 0x04 The ISL94202 is designed for use with an NTC thermistor. If the voltage measured at either of the “Thermistor Pins (20-22)” on page 96 is less than the DOT threshold, the fault bit “0x80.4 DOTF” on page 72 is set to 1. Given an NTC thermistor, this means that when the measured temperature at either thermistor input is greater than the value represented by this register a fault is declared. Given a DOT fault, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), DFET and cell balancing are disabled automatically, otherwise an external MCU is responsible for shutting off DFET (“0x86.0 DFET” on page 82) and ceasing cell balancing (see “MCU CB” on page 126). FN8889 Rev.3.00 Oct.14.19 Page 59 of 153 ISL94202 4. System Registers For recovery from this fault see “0x3A-3B DOTR” on page 60. The DOTR setting must be greater than the DOT value. The formula for converting from register digital value to voltage is: REGval  1.8 DOT = ------------------------------------4095 The default results in a threshold setting of ~0.53V (+55°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use: DOT  4095 REGval = --------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. 4.1.30 0x3A-3B DOTR The Discharge Over-Temperature Recovery threshold setting is shared between two registers. The upper 4 bits of the DOTR setting are stored in the lower 4 bits of 0x3B while the remaining 8 bits of DOTR are stored in 0x3A as shown in Table 35. The upper 4 bits of register 0x3B are reserved, it should be ignored on read-back and set to 0000 when writing to the register. Table 35. DOTR Bit Bit Name 0x3A Default Bit Name 0x3B Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte DOTR7 DOTR6 DOTR5 DOTR4 DOTR3 DOTR2 DOTR1 DOTR0 Value 0 0 1 1 1 1 1 0 0x3E RSV RSV RSV RSV DOTRB DOTRA DOTR9 DOTR8 Value 0 0 0 0 0 1 0 1 0x05 The ISL94202 is designed for use with an NTC thermistor. The DOTR setting must be greater than the DOT value. If the voltage measured at both “Thermistor Pins (20-22)” on page 96 is greater than the DOTR value, and the device previously detected a Discharge Over-Temperature condition, the fault bit “0x80.4 DOTF” on page 72 is cleared to 0. Given an NTC thermistor, this means that when the measured temperature at both thermistor inputs is less than the value represented by this register, the previously existing fault is cleared. When the DOT fault is cleared, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), DFET and cell balancing are re-enabled (subject to meeting all other conditions), otherwise an external MCU is responsible for enabling DFET (“0x86.0 DFET” on page 82) and restarting cell balancing (see “MCU CB” on page 126). The formula for converting from register digital value to voltage is: REGval  1.8DOTR = -----------------------------------4095 The default results in a threshold setting of ~0.59V (+50°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use: DOTR  4095 REGval = ------------------------------------1.8 FN8889 Rev.3.00 Oct.14.19 Page 60 of 153 ISL94202 4. System Registers The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. 4.1.31 0x3C-3D DUT The Discharge Under-Temperature threshold setting is shared between two registers. The upper 4 bits of the DUT setting are stored in the lower 4 bits of 0x3D while the remaining 8 bits of DUT are stored in 0x3C as shown in Table 36. The upper 4 bits of register 0x3D are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 36. DUT Bit Bit Name 0x3C Default Bit Name 0x3D Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte DUT7 DUT6 DUT5 DUT4 DUT3 DUT2 DUT1 DUT0 Value 1 1 1 1 0 0 1 0 0xF2 RSV RSV RSV RSV DUTB DUTA DUT9 DUT8 Value 0 0 0 0 1 0 1 1 0x0B The ISL94202 is designed for use with an NTC thermistor. If the voltage measured at either of the “Thermistor Pins (20-22)” on page 96 is greater than the DUT threshold, the fault bit “0x80.5 DUTF” on page 72 is set to 1. Given an NTC thermistor, this means that when the measured temperature at either thermistor input is less than the value represented by this register a fault is declared. When a DUT fault is cleared, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), DFET is shut off and cell balancing is disabled automatically, otherwise an external MCU is responsible for shutting off the power FET (“0x86.0 DFET” on page 82) and ceasing cell balancing (see “MCU CB” on page 126). For recovery from this fault see “0x3E-3F DUTR” on page 61. The DUTR setting must be less than the DUT value. The formula for converting from register digital value to voltage is: REGval  1.8DUT = -----------------------------------4095 The default results in a threshold setting of ~1.344V (-10°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use: DUT  4095 REGval = -------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. 4.1.32 0x3E-3F DUTR The Discharge Under-Temperature Recovery threshold setting is shared between two registers. The upper 4 bits of the DUTR setting are stored in the lower 4 bits of 0x3F while the remaining 8 bits of DUTR are stored in 0x3E as shown in Table 37 on page 62. The upper 4 bits of register 0x3F are reserved, it should be ignored on readback and set to 0000 when writing to the register. FN8889 Rev.3.00 Oct.14.19 Page 61 of 153 ISL94202 4. System Registers Table 37. DUTR Bit Bit Name D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte DUTR7 DUTR6 DUTR5 DUTR4 DUTR3 DUTR2 DUTR1 DUTR0 Value 1 0 0 1 0 0 1 1 0x93 RSV RSV RSV RSV DUTRB DUTRA DUTR9 DUTR8 Value 0 0 0 0 1 0 1 0 0x0A 0x3E Default Bit Name 0x3F Default The ISL94202 is designed for use with an NTC thermistor. The DUTR setting must be less than the DUT value. If the voltage measured at both of the “Thermistor Pins (20-22)” on page 96 is less than the DUTR value, and the device previously detected a Discharge Under-Temperature condition (“0x3C-3D DUT” on page 61), the fault bit “0x80.5 DUTF” on page 72 is cleared to 0. Given an NTC thermistor, this means that when the measured temperature at both thermistor inputs is greater than the value represented by this register the previously existing fault is cleared. Given a DUT fault, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), DFET and cell balancing are re-enabled (subject to meeting all other conditions of cell balancing), otherwise an external MCU is responsible for enabling DFET (“0x86.0 DFET” on page 82) and restarting cell balancing. (see “MCU CB” on page 126) The formula for converting from register digital value to voltage is: REGval  1.8 DUTR = ------------------------------------4095 The default results in a threshold setting of ~1.19V (+5°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use: DUTR  4095REGval = -----------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. 4.1.33 0x40-41 IOT The Internal Over-Temperature threshold Setting is shared between two registers. The upper 4 bits of the IOT setting are stored in the lower 4 bits of 0x41 while the remaining 8 bits of IOT are stored in 0x40 as shown in Table 38. The upper 4 bits of register 0x41 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 38. IOT Bit Bit Name 0x40 Default Bit Name 0x41 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte IOT7 IOT6 IOT5 IOT4 IOT3 IOT2 IOT1 IOT0 Value 0 1 1 0 0 1 0 0 0x64 RSV RSV RSV RSV IOTB IOTA IOT9 IOT8 Value 0 0 0 0 0 1 1 0 0x06 If the voltage measured by the internal temperature senor is less than IOT threshold then the fault bit “0x81.0 IOTF” on page 75 is set to 1. When the temperature measured by the internal temperature senor is higher than the value represented by this register a fault is declared. Given an IOT fault, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default) then all power FETS are shut off and cell balancing is disabled automatically, otherwise an external MCU is responsible for shutting off the power FETs FN8889 Rev.3.00 Oct.14.19 Page 62 of 153 ISL94202 4. System Registers (“0x86.1 CFET” on page 81, “0x86.0 DFET” on page 82) and ceasing cell balancing (see “MCU CB” on page 126). For recovery from this fault see“0x42-43 IOTR” on page 63. The IOTR setting must be less than the IOT value. The formula for converting from register digital value to voltage (V) is: REGval  1.8 IOT = ------------------------------------4095 The formula for converting from voltage (V) to temperature (C) is: IOT  1000 ICTemp = ------------------------------ – 273.15 1.8527 The default results in a threshold setting of ~0.719V (+115°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use: IOT  4095 REGval = -----------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. 4.1.34 0x42-43 IOTR The Internal Over-Temperature Recovery threshold setting is shared between two registers. The upper 4 bits of the IOTR setting are stored in the lower 4 bits of 0x43 while the remaining 8 bits of IOTR are stored in 0x42 as shown in Table 39. The upper 4 bits of register 0x43 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 39. IOTR Bit Bit Name 0x42 Default Bit Name 0x43 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte IOTR7 IOTR6 IOTR5 IOTR4 IOTR3 IOTR2 IOTR1 IOTR0 Value 0 0 0 1 0 0 0 0 0x10 RSV RSV RSV RSV IOTRB IOTRA IOTR9 IOTR8 Value 0 0 0 0 0 1 1 0 0x06 The IOTR setting must be less than the IOT value. If the internal temperature sensor voltage is less than the value in this register, the fault bit “0x81.0 IOTF” on page 75 is cleared to 0. When the measured temperature is less than the value represented by this register, the previously detected fault is cleared. When a IOT fault is cleared, if bit “0x87.5 µCCBAL” on page 83 is set to 0 (default), both the Discharge & Charge Power FETs and cell balancing are re-enabled (subject to meeting all other conditions), otherwise an external MCU is responsible for enabling the FETs (“0x86.0 DFET” on page 82, “0x86.1 CFET” on page 81) and restarting cell balancing (see “MCU CB” on page 126). The formula for converting from register digital value to voltage (V) is: REGval  1.8 IOTR = ------------------------------------4095 FN8889 Rev.3.00 Oct.14.19 Page 63 of 153 ISL94202 4. System Registers The formula for converting from voltage (V) to temperature (C) is: IOTR  1000 ICTemp = ----------------------------------- – 273.15 1.8527 The default results in a threshold setting of ~0.682V (+95°C; TGAIN = 0, GAIN = 2, per Figure 39 on page 96). To set the register decimal value to a desired threshold voltage use: IOTR  4095 REGval = ----------------------------------1.8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. Also see “0x4A.4 TGAIN” on page 68. 4.1.35 0x44-45 SLV The Sleep Level Voltage threshold setting is shared between two registers. The upper 4 bits of the SLV setting are stored in the lower 4 bits of 0x45 while the remaining 8 bits of SLV are stored in 0x44 as shown in Table 40. The upper 4 bits of register 0x45 are reserved and should be ignored on read-back and set to 0000 when writing to the register. Table 40. SLV Bit Bit Name 0x44 Default Bit Name 0x45 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte SLV7 SLV6 SLV5 SLV4 SLV3 SLV2 SLV1 SLV0 Value 1 0 1 0 1 0 1 0 0xAA RSV RSV RSV RSV SLVB SLVA SLV9 SLV8 Value 0 0 0 0 0 1 1 0 0x06 If the voltage across any cell is below the SLV threshold for the time specified by “0x46-47 WDT & SLT” on page 64, the bit “0x83.6 IN_SLEEP” on page 78 is set to 1 and the device enters SLEEP Mode. The formula for converting from register digital value to voltage is: REGval  1.8  8SLV = --------------------------------------------4095  3 The default results in a threshold setting of 2.0V. To set the register decimal value to a desired threshold voltage use: SLV  3  4095REGVal = ---------------------------------------1.8  8 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. 4.1.36 0x46-47 WDT & SLT The Watchdog Timer and Sleep Delay Timer values are shared between two registers. The WDT value is stored in 0x47.[7:3]. The upper 1-bit of the SLT value is stored in the lower 1 bit of the register (0x47.0) and the lower 8 bits of the SLT value is stored in register 0x46. The 2-bit unit selection for the SLT (SLTU) is stored in 0x47.[2:1]. This is shown in Table 41. FN8889 Rev.3.00 Oct.14.19 Page 64 of 153 ISL94202 4. System Registers Table 41. WDT & SLT Bit Bit Name 0x46 Default Bit Name 0x47 Default 4.1.36.1 D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte SLT7 SLT6 SLT5 SLT4 SLT3 SLT2 SLT1 SLT0 Value 0 0 0 0 1 1 1 1 0x0F WDT4 WDT3 WDT2 WDT1 WDT0 SLTU1 SLTU0 SLT8 Value 1 1 1 1 1 1 0 0 0xFC 0x47.[7:3] WDT The Watchdog Timer prevents an external MCU from initiating an action that it cannot undo through the I2C port, which can result in poor or unexpected operation of the pack. The watchdog timer is normally inactive when the device is operating stand-alone. When the pack is expected to have an MCU along with the ISL94202, the watchdog timer setting controls the maximum allowable time between communications from the external MCU to ISL94202 if any µC override bit has been set to 1. The WDT is activated by setting any µC override bits: • “0x87.6 µCFET” on page 82 • “0x87.5 µCCBAL” on page 83 • “0x87.4 µCLMON” on page 83 • “0x87.3 µCCMON” on page 83 • “0x87.2 µCSCAN” on page 84 If the watchdog timer is allowed to expire, the ISL94202 resets the serial interface, and pulses the INT output (“INT Pin (31)” on page 97) for 1µs at 1Hz to alert the MCU. If the INT is unsuccessful in restarting the communication interface, the part operates normally, except the power FETs and cell balance FETs are forced off on the next I2C transaction. The ISL94202 remains in this condition until I2C communications resume. When I2C communication resumes, the µCSCAN, µCCMON, µCLMON, µCFET, and EEEN bits are automatically reset (cleared) but the µCCBAL bit remains set if previously set. The power FETs and cell balance FETs turn on, if conditions allow. Automatic system scans resume on the next I2C communication. To calculate the setting of the timer multiply the value of register bits 0x47.[7:3] by 1s. The default WDT value is 31s. 4.1.36.2 0x47.[2:1] SLTU The Sleep Level Timer Unit selection bits 0x47.2 SLTU1 and 0x47.1 SLTU0 set the 2-bit SLT time unit value. The following settings are available: • 00 - µsec • 01 - msec • 10 - sec (default) • 11 - min FN8889 Rev.3.00 Oct.14.19 Page 65 of 153 ISL94202 4. System Registers 4.1.36.3 0x47.[0] - 0x46.[7:0] SLT The Sleep Level Timer bits SLT8 - SLT0 set the 9-bit number of units value used to define a Sleep Voltage condition. The valid range is 0 - 511. The 9-bit SLT setting is split across two 8-bit registers at addresses: • 0x47.[0]: Upper 1 bit - SLT • 0x46.[7:0]: lower 8 bits - SLT The default Sleep Level Timer setting is 1s. Multiply the 9-bit SLT number of units value by the SLTU unit value to calculate the length of time a cell voltage must remain below the threshold “0x44-45 SLV” on page 64 before the device transitions to “SLEEP Mode” on page 121. 4.1.37 0x48 Mode Timers The Mode Timer settings are stored at address 0x49. These settings govern the time between Mode transitions if no current flow is detected (see “0x82.2 CHING” on page 77 and “0x82.3 DCHING” on page 76). This register is split into two 4-bit values. The upper 4 bits (0x49.[7:4]) are the SLEEP Mode timer setting. The lower 4 bits (0x49.[3:0]) are the IDLE and DOZE Mode timer setting. This is shown in Table 42. Table 42. MOD Bit Bit Name 0x48 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte MOD7 MOD6 MOD5 MOD4 MOD3 MOD2 MOD1 MOD0 Value 1 1 1 1 1 1 1 1 0xFF One of these two timer settings must be non-zero, setting both to 0 is not supported. If both IDLE/DOZE and SLEEP timers are set to 0, the device immediately goes to sleep if there is no current flow detected. To recover from this condition, apply current to the device or hold the LDMON pin low (or CHMON pin high) and write non-zero values to the registers. 4.1.37.1 0x48.[3:0] IDLE/DOZE Timer This setting controls how long the ISL94202 remains in NORMAL (or IDLE) Mode without detecting a “0x82.2 CHING” on page 77 or “0x82.3 DCHING” on page 76 condition before transitioning to IDLE (or DOZE) Mode. If a CHING or DCHING detection occurs, the device immediately transitions back to NORMAL Mode and the timer is reset to 0. Setting the IDLE/DOZE timer to 0 immediately forces the device into the IDLE (or DOZE) Mode when there is no current flow detected. The timer is inactive if the bit “0x87.2 µCSCAN” on page 84 is set to 1, because the MCU is in charge of device operation. The range of the IDLE and DOZE Mode timer is 0 - 15 minutes set with each LSB being 1 minute increments. The default time is 15 Minutes. • 0x49.[3:0] - 1111 (default) See “System Modes” on page 119 for more information on system Modes. 4.1.37.2 0x48.[7:4] SLEEP Timer The SLEEP Timer setting controls how long the ISL94202 remains in DOZE Mode without detecting a “0x82.2 CHING” on page 77 or “0x82.3 DCHING” on page 76 condition before transitioning to SLEEP Mode. If a CHING or DCHING detection occurs, the device immediately transitions back to NORMAL Mode and the timer is reset to 0. Setting the SLEEP Timer to 0 immediately forces the device into SLEEP Mode if there is no current flow detected while in DOZE Mode. The device appears to have skipped directly from IDLE to SLEEP Mode to the observer. The timer is inactive if the bit “0x87.2 µCSCAN” on page 84 is set to 1, because the MCU is in charge of device operation. FN8889 Rev.3.00 Oct.14.19 Page 66 of 153 ISL94202 4. System Registers The range of the SLEEP Mode timer is 0 - 240 Minutes with each LSB being a 16 minute increment. The default setting is 240 minutes. If the SLEEP timer is set to 0s, the device transitions directly from IDLE to SLEEP Mode (if conditions for SLEEP are met) or NORMAL Mode (if SLEEP conditions are not met) completely bypassing DOZE Mode. • 0x49.[7:4] - 1111 (default). See “System Modes” on page 119 for more information on system Modes. 4.1.38 0x49 Cell Select The Cell Select register as shown in Table 43 contains the cell configuration setting the device uses to determine where cells are present. Cells must be selected for measurement results to be compared to the various thresholds as appropriate. If a cell is present, the bit must be set to 1. This setting also determines which cell connections to test for “Open Wire” on page 126 and cell balancing determination. Table 43. CELL Bit Bit Name 0x49 Default D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CELL8 CELL7 CELL6 CELL5 CELL4 CELL3 CELL2 CELL1 Value 1 0 0 0 0 0 1 1 0x83 ONLY the following combinations are supported: • 1000 0011 - 3 Cells connected (default) • 1100 0011 - 4 Cells connected • 1100 0111 - 5 Cells connected • 1110 0111 - 6 Cells connected • 1110 1111 - 7 Cells connected • 1111 1111 - 8 Cells connected These values are mapped according to the external cell connections of VCn and CBn (“VCn Pins” on page 94 & “CBn Pins” on page 94 respectively) where bit CELLn corresponds to whether or not VCn/CBn is connected to a cell. See “Reduced Cell Count” on page 150 for configuring the VCn/CBn pins in applications with 3 - 8 cells. 4.1.39 0x4A Setup 0 Setup 0 is the first of two registers containing single bit settings that enable/disable specific operations or controls. RSV bits must be written as 0 and ignored on read back. Table 44. Setup 0 Bit Name D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Byte CELLF PSD RSV XT2M TGAIN RSV (0) PCFETE DOWD OWPSD Value 0 0 0 0 0 0 0 0 0x00 0x4A Default 4.1.39.1 0x4A.7 CELLF PSD The Cell Fail Pack Shutdown bit enables or disables the PSD pin function of the ISL94202 upon detecting a CELLF condition and setting flag “0x81.4 CELLF” on page 74. Set this bit to 0 (default) to disable the CELLF connection to the PSD output pin. Set this bit to 1 to activate the PSD output pin when a CELLF condition occurs. See “0x22-23 CBMAXDV” on page 51, “0x81.4 CELLF” on page 74, and “PSD Pin (32)” on page 98 for more information. FN8889 Rev.3.00 Oct.14.19 Page 67 of 153 ISL94202 4.1.39.2 4. System Registers 0x4A.5 XT2M The second External Temperature Monitor bit determines the function of the second thermistor input pin. This input can monitor either a second pack thermistor or a power FET temperature thermistor. Set this bit to 0 (default) if the xT2 pin connects to a thermistor that monitors cell temperature, for normal operation. Set this bit to 1 if the xT2 pin connects to a thermistor that monitors FET temperature. This setting blocks shut off of the cell balance outputs if the xT2 temperature exceeds cell balance temperature limits. See “0x28-29 CBUT” on page 53, “0x2C-2D CBOT” on page 55, and “Thermistor Pins (20-22)” on page 96 for more information. 4.1.39.3 0x4A.4 TGAIN The Temperature Gain bit controls the gain of the temperature measurement circuitry for input pins xT1 and xT2 and internal temperature monitoring. Setting this bit to 0 (default) sets the gain of IOT, xT1, and xT2 voltage measurement to 2. Note: This is the preferred and strongly recommended choice as the device calibrations and specifications are tied to this setting. The temperature response is more linear and covers a wider temperature range before nearing the limits of the ADC reading. Setting this bit to 1 sets the gain of IOT, xT1, and xT2 voltage measurement 1. This setting is not recommended for monitoring external thermistors or device internal temperature (IOT). See “Thermistor Pins (20-22)” on page 96 and “0x40-41 IOT” on page 62 for more information. 4.1.39.4 0x4A.2 PCFETE The Pre-Charge FET Enable bit controls whether or not the pre-charge FET is used when a cell has fallen below the LVCH threshold. Set this bit to 0 (default) if the pre-charge FET is not used. Set this bit to 1 to direct the ISL94202 to enable the pre-charge FET instead of the charge FET when any of the cell voltages are below the threshold “0x0E-0F VCELL LVCL” on page 40. See “Power FET Pins (42, 44, 45)” on page 107 and “PCFET Pin (44)” on page 108 for more information. 4.1.39.5 0x4A.1 DOWD The Disable Open Wire Detection bit controls whether or not an open-wire detection is enabled and executed following detection of a “0x81.4 CELLF” on page 74 condition. Set this bit to 0 (default) to enable an open-wire detection scan following a CELLF detection. Set this bit to 1 to prevent and open-wire detection scan following a CELLF detection. See “0x22-23 CBMAXDV” on page 51 and “Open Wire” on page 126 for more information. 4.1.39.6 0x4A.0 OWPSD The Open Wire Pack Shutdown bit controls whether or not the PSD pin is asserted following an open-wire detection. Set this bit to 0 (default) to prevent the ISL94202 from asserting the PSD pin following an open-wire detection. Set this bit to 1 to force the ISL94202 to assert the PSD pin following an open-wire detection. See “PSD Pin (32)” on page 98 and Open Wire for more information. 4.1.40 0x4B Setup 1 Setup 1 is the second of two registers containing single bit settings that enable/disable specific operations or controls. RSV bits must be written as 0 and ignored on read back. FN8889 Rev.3.00 Oct.14.19 Page 68 of 153 ISL94202 4. System Registers Table 45. Setup 1 Bit Name 0x4B Default 4.1.40.1 D[7] D[6] D[5] D[4] D[3] D[2] D[1] [0] Byte CBDD CBDC DFODUV CFODOV UVLOPD RSV RSV CB_EOC Value 0 1 0 0 0 0 0 0 0x40 0x4B.7 CBDD The Cell Balance During Discharge bit controls whether or not cell balancing is performed during discharge. Status bit “0x82.3 DCHING” on page 76 must be 1 indicating a discharge current detection. Set this bit to 0 (default) to disable cell balancing during discharge. In most cases cell balancing during discharge wastes system power and provides no positive benefits. Set this bit to 1 to allow the ISL94202 to perform cell balancing during discharge. See “Cell Balancing” on page 122 for more information. When both CBDD and CBDC are set to 0 automatic cell balancing is completely disabled. 4.1.40.2 0x4B.6 CBDC The Cell Balance During Charge bit controls whether or not cell balancing is performed during charge. Status bit “0x82.2 CHING” on page 77 must be 1 indicating a charge current detection. Set this bit to 0 to disable cell balancing during charge. Set this bit to 1 (default) to allow the ISL94202 to perform automatic cell balancing during charge. See “Cell Balancing” on page 122 for more information. When both CBDD and CBDC are set to 0 automatic cell balancing is completely disabled. 4.1.40.3 0x4B.5 DFODUV The DFET On During Undervoltage bit controls whether or not DFET stays on during a cell under-voltage condition (“0x80.2 UVF” on page 72). Set this bit 0 (default) in systems using separate (also referred to as parallel) discharge and charge paths. This enables the ISL94202 to automatically turn off DFET in a cell UV condition to prevent further discharge of the cells. Set this bit 1 in systems using a single (also referred to as series) discharge and charge path. This enables the ISL94202 to keep DFET on in a cell UV condition if the device detects a charge current. Status bit “0x82.2 CHING” on page 77 must be 1 indicating a charge current detection, otherwise if discharge current is detected (“0x82.3 DCHING” on page 76) the cell UV forces the DFET off. This setting is intended to minimize DFET power dissipation through the body diode during cell UV when the pack is charging. See “VCELL UV” on page 37 for more information. 4.1.40.4 0x4B.4 CFODOV The CFET On During Overvoltage bit is used to control whether or not CFET stays on during a cell over-voltage condition (“0x80.0 OVF” on page 73). Set this bit 0 (default) in systems using separate (also referred to as parallel) discharge and charge paths. This enables the ISL94202 to automatically turn off CFET in a cell OV condition to prevent further charge of the cells. Set this bit 1 in systems using a single (also referred to as series) discharge and charge path. This enables the ISL94202 to keep CFET on in a cell OV condition if the device detects a discharge current. Status bit “0x82.3 DCHING” on page 76 must be a 1, indicating a discharge current detection, otherwise if charge current is detected (“0x82.2 CHING” on page 77) the cell OV forces the CFET off. This setting is intended to minimize CFET power dissipation through the body diode during cell OV when the pack is discharging. See “VCELL OV” on page 35 for more information. FN8889 Rev.3.00 Oct.14.19 Page 69 of 153 ISL94202 4.1.40.5 4. System Registers 0x4B.3 UVLOPD The Undervoltage Lockout Powerdown bit controls whether or not the device powers down when detection of an undervoltage lockout condition (“0x80.3 UVLOF” on page 72) occurs. The default setting of 0 means the device does not power down when detecting a UVLO condition. Set UVLOPD to 1 to force the device to power down when detecting a UVLO condition. This selection combined with the VCELL UVLO threshold is intended to prevent any further use of the pack. This is not intended as a method to conserve power until a charger is connected. If any cell is below “0x0A-0B VCELL UVLO” on page 39, the device transitions back to power-down following wake-up from a charger connection. See “System Modes” on page 119 and “Mode Exceptions” on page 122 for more information. 4.1.40.6 0x4B.0 CB_EOC The Cell Balance During End-of-Charge bit controls whether cell balancing is performed following an VCELL end-of-charge condition detection (“0x81.7 VEOC” on page 73). The default of 0 disables cell balancing following an VEOC detection if there is no current flowing (“0x82.2 CHING” on page 77 or “0x82.3 DCHING” on page 76). Set this bit to 1 to enable cell balancing after an VEOC detection regardless of current direction. See “0x0C-0D VCELL EOC” on page 40 and “Cell Balancing” on page 122 for more information. 4.2 0x80-89 Other Registers These addresses apply to the EEPROM, the equivalent Configuration Register addresses are not to be accessed. Page # Register Address (Hex) Bit Function Register Name 7 6 5 4 3 2 1 0 RSV RSV RSV RSV RSV RSV RSV Factory Default (Hex) Type N/A N/A N/A R/W RSV RSV Other Registers 70 4C - 4F Reserved RSV 70 50 - 57 User EEPROM User EEPROM 58 - 5F Reserved RSV 4.2.1 RSV RSV RSV RSV RSV RSV RSV 0x4C-4F RSV These registers are reserved and should not be written to or read from. 4.2.2 0x50-57 User EEPROM This is the user EEPROM area. There are no registers associated with this section of the EEPROM. See “Control/Data Registers” on page 138 for details on how to write to this area. 4.3 0x80-89 Operations Registers The ISL94202 Operations Registers provide device/system status information. Some of these registers are writable and allow a level of device/system control. These registers do not map to any EEPROM location so they are not permanently programmable. During Power-On Reset (POR) these registers are set to default the values, which are subsequently updated by the ISL94202 following measurements and changes in status. Some of these register bits enable MCU based systems to override the state machine and control the operation of the ISL94202. FN8889 Rev.3.00 Oct.14.19 Page 70 of 153 ISL94202 4. System Registers Table 46. Operations Registers Page # Bit Function Register Address (Hex) Register Name 7 6 5 4 3 UVLOF 2 1 0 Factory Default (Hex) Type Operations Registers 71 80 Status 0 CUTF COTF DUTF DOTF 73 81 Status 1 VEOC RSV OPENF 75 82 Status 2 LVCHG INT_ SCAN ECC_ FAIL 77 83 Status 3 RSV SLEEP DOZE 78 84 CBFC Cell Balance FET Control CBFC [8:1] 79 85 Control 0 RSV ADC STRT Current Gain CG1 - CG0 80 86 Control 1 CLR_ LERR LMON _EN CLR_ CERR CMON PSD _EN PCFET CFET 82 87 Control 2 RSV µC FET µC CBAL µC LMON µC CMON µC SCAN 84 88 Control 3 RSV RSV RSV RSV PDWN 85 89 EEPROM Enable RSV RSV RSV RSV RSV 4.3.1 UVF OVLOF OVF 00 R CELLF DSCF DOCF COCF IOTF 00 R ECC_ USED DCHIN G CHING CH_ PRSNT LD_ PRSNT 00 R IDLE CBUV CBOV CBOT 00 R 00 R/W 00 R/W DFET 00 RW CBAL_ ON 00 RW SLEEP DOZE IDLE 00 RW RSV EEEN 00 RW CBUT Analog Multiplexer Out AO [3:0] OW_ STRT RSV 0x80 Status 0 (R) This status register is read only. The bits are set by the device as the specific threshold settings they are linked to are exceeded. They are cleared by the device if and when the condition that set them returns to within the related recovery threshold or hysteresis. Table 47. Error Status Register 0 Address - Bits 0x80 - D[7] 0x80 - D[6] 0x80 - D[5] 0x80 - D[4] 0x80 - D[3] 0x80 - D[2] 0x80 - D[1] 0x80 - D[0] Name CUTF COTF DUTF DOTF UVLOF UVF OVLOF OVF Default 0 0 0 0 0 0 0 0 4.3.1.1 0x80.7 CUTF The Charge Under-Temperature Fault bit is set following a Charge Under-Temperature condition detection. If the temperature of the external thermistor connected to “Thermistor Pins (20-22)” on page 96 drops below the “0x3435 CUT” on page 58 temperature threshold, the CUTF bit is set to 1. An NTC thermistor is assumed, which means the voltage on the xTn pin is above the CUT threshold voltage. If a CUTF condition detection occurs during charging (“0x82.2 CHING” on page 77 is set), the ISL94202 forces the CFET off. If the device detects discharge current (“0x82.3 DCHING” on page 76 is set), the “0x3C-3D DUT” on page 61 threshold determines FET status during under temperature conditions. The ISL94202 clears the CUTF bit when it detects the temperature of the external thermistor has risen above the “0x36-37 CUTR” on page 58 threshold (the voltage has dropped below). 4.3.1.2 0x80.6 COTF The Charge Over-Temperature Fault bit is set following a Charge Over-Temperature condition detection. If the temperature of the external thermistor connected to “Thermistor Pins (20-22)” on page 96 rises above the “0x3031 COT” on page 56 temperature threshold, the COTF bit is set to 1. An NTC thermistor is assumed, which means the voltage on the xTn pin is below the COT threshold voltage. If a COTF condition detection occurs during charging (“0x82.2 CHING” on page 77 is set), the ISL94202 forces the CFET off. If the device detects discharge current (“0x82.3 DCHING” on page 76 is set), the “0x38-39 DOT” on page 59 threshold determines FET status during over-temperature conditions. FN8889 Rev.3.00 Oct.14.19 Page 71 of 153 ISL94202 4. System Registers The ISL94202 clears the COTF bit when it detects the temperature of the external thermistor has dropped below the “0x32-33 COTR” on page 57 threshold (the voltage has risen above). 4.3.1.3 0x80.5 DUTF The Discharge Under-Temperature Fault bit is set following a Discharge Under-Temperature condition detection. If the temperature of the external thermistor connected to “Thermistor Pins (20-22)” on page 96 drops below the “0x3C-3D DUT” on page 61 temperature threshold, the DUT bit is set to 1. An NTC thermistor is assumed, which means the voltage on the xTn pin is above the DUT threshold voltage. If a DUTF condition detection occurs during discharging (“0x82.3 DCHING” on page 76 is set), the ISL94202 forces the DFET off. If the device detects charge current (“0x82.2 CHING” on page 77 is set), the “0x34-35 CUT” on page 58 threshold determines FET status during under temperature conditions. The ISL94202 clears the DUT bit when it detects the temperature of the external thermistor has risen above the “0x3E-3F DUTR” on page 61 threshold (the voltage has dropped below). 4.3.1.4 0x80.4 DOTF The Discharge Over-Temperature Fault bit is set following a Discharge Over-Temperature condition detection. If the temperature of the external thermistor connected to “Thermistor Pins (20-22)” on page 96 rises above the “0x38-39 DOT” on page 59 temperature threshold, the DOT bit is set to 1. An NTC thermistor is assumed, which means the voltage on the xTn pin is below the DOT threshold voltage. If a DOTF condition detection occurs during discharging (“0x82.3 DCHING” on page 76 is set), the ISL94202 forces the DFET off. If the device detects charge current (“0x82.2 CHING” on page 77 is set), the “0x30-31 COT” on page 56 threshold determines FET status during over-temperature conditions. The ISL94202 clears the DOT bit when it detects the temperature of the external thermistor has dropped below the “0x3A-3B DOTR” on page 60 threshold (the voltage has risen above). 4.3.1.5 0x80.3 UVLOF The Undervoltage Lockout Fault bit is set when the ISL94202 detects at least one cell voltage is below the threshold “0x0A-0B VCELL UVLO” on page 39 for 5 consecutive sample cycles (measurements). This is an Undervoltage Lockout condition. When the UVLO bit is set, the “SD Pin (34)” on page 99 is driven low. If bit “0x4B.3 UVLOPD” on page 70 is set to 1, the device goes to the “Mode Exceptions” on page 122. A UVLO condition overrides the control bit “0x87.6 µCFET” on page 82 and automatically forces the appropriate power FETs off. The ISL94202 clears the UVLO bit only if it detects the cell voltages have risen above the recovery threshold “0x06-07 VCELL UVR” on page 38. This requires all of the cell voltages to be above the UVR threshold, including when the device wakes from a UVLOPD induced Powerdown (“0x4B.3 UVLOPD” on page 70 is set to 1), otherwise it returns to Powerdown. UVLO detection is disabled by setting the VCELL UVLO threshold to 0V. 4.3.1.6 0x80.2 UVF The Undervoltage Fault bit is set when at least one cell is below threshold “VCELL UV” on page 37 for the time period set by “0x12-13 VCELL UV Timer” on page 42. This is an Undervoltage condition. If bit “0x87.6 µCFET” on page 82 is 0, the ISL94202 also shuts off DFET. From the Undervoltage condition, if the cells recover to above the “0x06-07 VCELL UVR” on page 38 threshold for a time exceeding VCELL UVT plus three seconds, the ISL94202 pulses the LDMON output once every 256ms and looks for the absence of a load. The pulses are of programmable duration (0ms to 15ms) using bits “0x05.7:4 LDPW” on page 37. During the pulse period, a small current (~60µA) is output into the load. If there is no load, the LDMON voltage is higher than the recovery threshold of 0.6V. When the load has been removed and the cells are above the VCELLUVR level, the ISL94202 clears the UV bit and, if µCFET = 0, turns on the discharge FET and resumes normal operation. FN8889 Rev.3.00 Oct.14.19 Page 72 of 153 ISL94202 4. System Registers UV detection is disabled by setting the VCELL UV threshold to 0V. See “UV Detection & Response” on page 130 for more information. 4.3.1.7 0x80.1 OVLOF The Overvoltage Lockout Fault bit is set when the ISL94202 detects at least one cell voltage is above the threshold “0x08-09 VCELL OVLO” on page 38 for five consecutive sample cycles (measurements). This is an Overvoltage Lockout condition. When the OVLO bit is set the “CFET Pin (45)” on page 108 and “CBn Pins” on page 94 are turned off and the “PSD Pin (32)” on page 98 is driven high. The ISL94202 clears the OVLO bit only if it detects the cell voltages have dropped below the recovery threshold “0x02-03 VCELL OVR” on page 36. The OVLO condition can be overridden by setting the OVLO threshold to 0x0FFF or by an external MCU setting the “0x87.2 µCSCAN” on page 84 bit to override the internal automatic scan, then turning on the CFET. However, if the MCU takes permanent control of the scan, it must take over the scan for all cells and all control functions, including comparisons of the cell voltage to OV and UV thresholds, managing time delays, and controlling all cell balance functions. 4.3.1.8 0x80.0 OVF The Overvoltage Fault bit is set when at least one cell is above threshold “VCELL OV” on page 35 for the time period set by “0x10-11 VCELL OV Timer” on page 41. This is an Overvoltage condition. If bit “0x87.6 µCFET” on page 82 is 0, the ISL94202 also shuts off CFET. From the Overvoltage condition, if the cells recover to below the “0x02-03 VCELL OVR” on page 36 threshold for a time exceeding VCELL OVT, the ISL94202 clears the OV bit and, if µCFET = 0, turns on the charge FET and resumes normal operation. OV detection is disabled by setting the VCELL OV threshold to the maximum value (0x0FFF). See “OV Detection/Response” on page 129 for more information. 4.3.2 0x81 - Status 1 (R) This status register is read only. The bits are set by the device as the specific threshold settings they are linked to are exceeded. They are cleared by the device if and when the condition that set them returns to within the related recovery threshold or hysteresis. RSV bit should be ignored on register read. Table 48. Error Status Register 1 Address - Bits 0x81 - D[7] 0x81 - D[6] 0x81 - D[5] 0x81 - D[4] 0x81 - D[3] 0x81 - D[2] 0x81 - D[1] 0x81 - D[0] Name VEOC RSV OWF CELLF DSCF DOCF COCF IOTF Default 0 0 0 0 0 0 0 0 4.3.2.1 0x81.7 VEOC The Voltage End-of-Charge detection bit is set when any cell voltage is above the end-of-charge voltage threshold “0x0C-0D VCELL EOC” on page 40. When this bit sets, the “EOC Pin (35)” on page 99 is pulled low. After this bit is set, it can only be cleared by the device when all cells are below the end-of-charge voltage threshold minus the hysteresis (~117mV, see “VEOCTH” on page 18). This is typically accomplished by enabling “0x4B.0 CB_EOC” on page 70. When the CB_EOC bit is set, balancing occurs while an end-of-charge condition exists (VEOC bit = 1), regardless of current flow. This allows the ISL94202 to drain high voltage cells when charging is complete. This speeds the balancing of the pack, especially when there is a large capacity differential between cells. When the end-of-charge condition clears, the cell balance operation returns to normal programming. VEOC detection does not shut off the CFET, disabling CFET at the end of charge is controlled by the threshold “VCELL OV” on page 35. FN8889 Rev.3.00 Oct.14.19 Page 73 of 153 ISL94202 4. System Registers See “VEOC” on page 130 and “Cell Balancing” on page 122. 4.3.2.2 0x81.5 OWF The Open-Wire Fault bit is set when an open wire is detected on any of the cell voltage measurement pins. When detected, the OWF condition turns off the cell balance and power FETs, but only if bit “0x87.6 µCFET” on page 82 is 0. Setting the µCFET bit = 1 prevents the power FETs from turning off during a CELLF condition. When this bit is set, it can only be cleared if an open wire is not detected during a subsequent open-wire scan. The open-wire detection can be set to force the PSD pin high if bit “0x4A.0 OWPSD” on page 68 is set to 1. An open-wire test can be disabled by setting bit “0x4A.1 DOWD” on page 68 to 1. See “Open Wire” on page 126 for details of operation and “0x14-15 OWT” on page 43 to set the duration of the open-wire test. 4.3.2.3 0x81.4 CELLF The Cell Fail fault bit is set when the difference between the lowest voltage cell (“0x8A-8B CELMIN” on page 89) and highest voltage cell (“0x8C-8D CELMAX” on page 89) exceeds threshold “0x22-23 CBMAXDV” on page 51. When detected, the CELLF condition turns off the cell balance FETs and the power FETs, but only if bit “0x87.6 µCFET” on page 82 is 0. Setting the µCFET bit = 1 prevents the power FETs from turning off during a CELLF condition. The MCU is then responsible for the power FET control When this bit is set, it is cleared only if the difference in cell voltage between the lowest voltage cell and highest voltage cell ceases to exceed the cell balance maximum differential voltage during a subsequent set of cell voltage measurements. An CELLF detection can be set to force the PSD pin high if control bit “0x4A.7 CELLF PSD” on page 67 is set to 1. The CELLF function can be disabled by setting the CBMAXDV value to 0x0FFF. In this case, the voltage differential can never exceed the limit. However, disabling the cell fail condition also disables open-wire detection because “Open Wire” on page 126 is triggered by a CELLF. 4.3.2.4 0x81.3 DSCF The Discharge Short Circuit Fault bit is set when the discharge current induces a voltage across the current sense resistor that exceeds the voltage threshold “0x1B.[6:4] DSC” on page 48 for a time greater than the setting of “0x1B.[3:2] DSCTU” on page 48 and “0x1B.[1:0] - 0x1A.[7:0] DSCT” on page 49. When a discharge short-circuit condition is detected, bit “0x82.0 LD_PRSNT” on page 77 is set to 1 while the load remains attached (see “LDMON Pin (38)” on page 104). The cell balance and power FETs turn off automatically in a short-circuit condition, regardless of the setting of the bit “0x87.6 µCFET” on page 82. When the DSCF bit is set, it is cleared when the device detects that the load has been removed for two consecutive load monitoring scans if “0x87.4 µCLMON” on page 83 is 0 (see “DOC/DSC Recovery” on page 104). If the µCFET bit is 0, the device automatically re-enables the power FETs by setting the DFET and CFET (or PCFET) bits to 1 (assuming all other conditions are within normal ranges). If the µCFET bit is 1, the MCU must test for removal of the fault condition and turn on the power FETs. It does this by taking control of the load monitor circuit (set the µCLMON bit = 1) and periodically pulsing bit “0x86.6 LMON_EN” on page 80. When the MCU detects that LD_PRSNT = 0, it then must set the bit “0x86.7 CLR_LERR” on page 80 to 1 (to clear the error condition and reset the DOC or DSC bit) and sets the DFET and CFET (or PCFET) bits to 1 to turn on the power FETs. 4.3.2.5 0x81.2 DOCF The Discharge Overcurrent Fault bit is set when the discharge current induces a voltage across the current sense resistor that exceeds the voltage threshold “0x17.[6:4] DOC” on page 44 for a time greater than the setting of “0x17.[3:2] DOCTU” on page 44 and “0x16-17 DOCT” on page 44. When a discharge overcurrent condition is detected, bit “0x82.0 LD_PRSNT” on page 77 is set to 1 while the load remains attached (see “LDMON Pin (38)” on page 104). FN8889 Rev.3.00 Oct.14.19 Page 74 of 153 ISL94202 4. System Registers The cell balance and power FETs turn off automatically in an overcurrent condition if bit “0x87.6 µCFET” on page 82 = 0, otherwise the MCU must control the FETs. When the DOCF bit is set, it is cleared when the device detects that the load has been removed for two consecutive load monitoring scans if “0x87.4 µCLMON” on page 83 is 0 (see “DOC/DSC Recovery” on page 104). If the µCFET bit is 0, the device automatically re-enables the power FETs by setting the DFET and CFET (or PCFET) bits to 1 (assuming all other conditions are within normal ranges). If the µCFET bit is 1, the MCU must test for removal of the fault condition and then turn on the power FETs. It does this by taking control of the load monitor circuit (set the µCLMON bit = 1) and periodically pulsing bit “0x86.6 LMON_EN” on page 80. When the MCU detects that LD_PRSNT = 0, it must set the bit “0x86.7 CLR_LERR” on page 80 to 1 (to clear the error condition and reset the DOC or DSC bit) and set the DFET and CFET (or PCFET) bits to 1 to turn on the power FETs. 4.3.2.6 0x81.1 COCF The Charge Overcurrent Fault bit is set when the charge current induces a voltage across the current sense resistor that exceeds the voltage threshold “0x19.[6:4] COC” on page 46 for a time greater than the setting of “0x19.[3:2] COCTU” on page 46 and “0x18-19 COCT” on page 47. When a charge overcurrent condition is detected, bit “0x82.1 CH_PRSNT” on page 77 is set 1 while the charger remains attached (see “CHMON Pin (37)” on page 99). The cell balance and power FETs turn off automatically in an overcurrent condition if bit “0x87.6 µCFET” on page 82 = 0, otherwise the MCU must control the FETs. When the COCF bit is set, it is cleared when the device detects that the charger has been removed for two consecutive load monitoring scans if “0x87.3 µCCMON” on page 83 is 0 (see “COC Recovery” on page 100). If the µCFET bit is 0, the device automatically re-enables the power FETs by setting the DFET and CFET (or PCFET) bits to 1 (assuming all other conditions are within normal ranges). If the µCFET bit is 1, the MCU must test for removal of the fault condition and then turn on the power FETs. It does this by taking control of the charger monitor circuit (set the µCCMON bit = 1) and periodically pulsing bit “0x86.4 CMON_EN” on page 81. When the MCU detects that CH_PRSNT = 0, it must set the bit “0x86.5 CLR_CERR” on page 81 to 1 (to clear the error condition and reset the DOC or DSC bit) and set the DFET and CFET (or PCFET) bits to 1 to turn on the power FETs. 4.3.2.7 0x81.0 IOTF The Internal Over-Temperature Fault bit is set to 1 if the internal temperature of the IC goes above the threshold “0x40-41 IOT” on page 62. When the ISL94202 sets the IOTF bit, it also stops/prevents cell balancing and turns off the power FETs. When IOTF is set, the device continues to prevent turn on of the FETs until the internal temperature drops below the recovery threshold “0x42-43 IOTR” on page 63. Note: If the device wakes from Powerdown or SLEEP Mode with the internal temperature above IOTR it may also prevent turn on of the FETs. 4.3.3 0x82 - Status 2 (R) This status register is read only. The bits are set by the device as the specific threshold settings they are linked to are exceeded. They are cleared by the device if and when the condition that set them returns to within the related recovery threshold or hysteresis. Table 49. Error Status Register 2 Address - Bits 0x82 - D[7] 0x82 - D[6] 0x82 - D[5] 0x82 - D[4] 0x82 - D[3] 0x82 - D[2] 0x82 - D[1] 0x82 - D[0] Name LVCHG INT_SCAN ECC_FAIL ECC_USED DCHING CHING CH_PRSNT LD_PRSNT Default 0 0 0 0 0 0 0 0 FN8889 Rev.3.00 Oct.14.19 Page 75 of 153 ISL94202 4. System Registers 4.3.3.1 0x82.7 LVCHG The Low Voltage Charge bit is set if at least one cell voltage is below the threshold “0x0E-0F VCELL LVCL” on page 40. If LVCHG is 1, the PCFET turns on instead of CFET as long as at least one cell is below the VCELL LVCL setting. When all cells are above the Low Voltage Charge threshold, the PCFET output turns off and the CFET output turns on (when appropriate). See “0x4A.2 PCFETE” on page 68, “0x86.2 PCFET” on page 81, and “0x86.1 CFET” on page 81. 4.3.3.2 0x82.6 INT_SCAN The Internal Scan bit is active low (0) for the duration of an internal measurement scan, otherwise it is 1. This bit allows a MCU to synchronize with the ISL94202 system scan when reading scan data such as voltages and temperatures. If the MCU attempts to read a data register while it is being written the result may be incorrect. See “Wake Up” on page 115. 4.3.3.3 0x82.5,4 ECC_FAIL & ECC_USED The ISL94202 contains an Error Checking/detection/Correction mechanism for EEPROM read operations. When reading a value from the EEPROM, the device checks the data value for an error. Two bits represent the status of the read operation, see Table 50. If there are no errors, the EEPROM value is valid and the ECC_USED and ECC_FAIL bits are set to 0. If there is a 1-bit error, the ISL94202 corrects the error and sets the ECC_USED bit. This is a valid operation and the value read from the EEPROM is correct. During an EEPROM read, if there is an error consisting of two or more bits, the ISL94202 sets the ECC_FAIL bit (ECC_USED = 0). This read contains invalid data. The error correction is also active during the initial power-on recall of the EEPROM values to the configuration registers. The circuit corrects for any 1-bit errors. 2-bit errors are not corrected and the contents of the configuration register maintain the previous value. Internally, the power-on recall circuit uses the ECC_USED and ECC_FAIL bits to determine there is a proper recall before allowing the device operation to start. However, an external MCU cannot use these bits to detect the validity of the registers on power-up or determine the use of the error correction mechanism, because the bits automatically reset on the next valid read. Table 50. ECC_FAIL & ECC_USED 0x82.5 ECC_FAIL 0x82.4 ECC_USED Description 0 0 No Errors Detected. 0 1 1-bit error detected and corrected - Valid read. 1 0 2-bit or more error detected - NOT corrected - Invalid read. 1 1 Invalid. See “Control/Data Registers” on page 138 and “I2C Interface” on page 141. 4.3.3.4 0x82.3 DCHING The Discharging bit is set by the analog current direction detection circuit when the discharge current produces a voltage across the sense resistor greater than the minimum detection threshold voltage of ~100µV (typical, see “VDCTH” on page 15, not programmable) for more than 2ms. For current direction detection, there is a 2ms digital delay for getting into or out of either direction condition (CHING or DCHING). This means that the current detection circuit needs to detect an uninterrupted flow of current out of the pack for more than 2ms to indicate a discharge condition (DCHING). Then, the current detector needs to identify that there is a charge current (CHING) or no current (both CHING and DCHING clear) for a continuous 2ms to remove the discharge condition. FN8889 Rev.3.00 Oct.14.19 Page 76 of 153 ISL94202 4. System Registers The measured value for discharge (or charge) current is stored in registers “0x8E-8F IPACK” on page 90. The current reading should only be considered valid if this bit or “0x82.2 CHING” on page 77 is set, otherwise it should be discarded. When set, this bit indicates current flowing out of the pack. 4.3.3.5 0x82.2 CHING The Charging bit is set by the analog current direction detection circuit when the charge current produces a voltage across the sense resistor more negative than the minimum detection threshold voltage of -100µV (typical, see “VCCTH” on page 15, not programmable) for more than 2ms. For current direction detection, there is a 2ms digital delay for getting into or out of either direction condition (CHING or DCHING). This means that the current detection circuit needs to detect an uninterrupted flow of current out of the pack for more than 2ms to indicate a discharge condition (DCHING). Then, the current detector needs to identify that there is a charge current (CHING) or no current (both CHING and DCHING clear) for a continuous 2ms to remove the discharge condition. The measured value for charge (or discharge) current is stored in registers “0x8E-8F IPACK” on page 90. The current reading should only be considered valid if this bit or “0x82.3 DCHING” on page 76 is set, otherwise it should be discarded. When set, this bit indicates current flowing into the pack. 4.3.3.6 0x82.1 CH_PRSNT The Charger Present bit is set during a COC condition (see “0x18-19 COC & COCT” on page 46 and “0x81.1 COCF” on page 75) while the charger is still attached. If the voltage on the “CHMON Pin (37)” on page 99 falls below the threshold (see “VCHMON” on page 16) and “0x87.3 µCCMON” on page 83 = 0, the CH _PRSNT bit resets automatically. CH _PRSNT remains set as long as the voltage on the CHMON pin is above the threshold. If the voltage on the CHMON pin drops below the threshold and µCCMON = 1, the bit is reset only upon a read of the “0x82 - Status 2 (R)” on page 75 by a MCU. See “COC Recovery” on page 100. A Charger Present detection wakes a device from Powerdown or SLEEP into NORMAL Mode. 4.3.3.7 0x82.0 LD_PRSNT The Load Present bit is set during a DOC or DSC condition (see “0x16-17 DOC & DOCT” on page 43 and “0x1A1B DSC & DSCT” on page 48 respectively) while the load is still attached. If the voltage on the “LDMON Pin (38)” on page 104 pin rises above the threshold (see “VLDMON” on page 16) and “0x87.3 µCCMON” on page 83 = 0, the bit resets automatically. LD_PRSNT remains set as long as the voltage on the LDMON pin is below the threshold. If the voltage on the LDMON pin rises above the threshold and µCLMON = 1, the bit is reset only on a read of the “0x82 - Status 2 (R)” on page 75 by a MCU. See “DOC/DSC Recovery” on page 104. A Load Present detection wakes a device from SLEEP into NORMAL Mode. If the device is in Powerdown, a Load Present detection on wake up can prevent the power FETs from turning on. 4.3.4 0x83 - Status 3 (R) The Status 3 register is read only. The bits are set by the device as the specific threshold settings they are linked to are exceeded. They are cleared by the device if/when the condition that set them returns to within the related recovery threshold or hysteresis. RSV bit should be ignored on register read. FN8889 Rev.3.00 Oct.14.19 Page 77 of 153 ISL94202 4. System Registers Table 51. Error Status Register 3 Address - Bits 0x83 - D[7] 0x83 - D[6] 0x83 - D[5] 0x83 - D[4] 0x83 - D[3] 0x83 - D[2] 0x83 - D[1] 0x83 - D[0] Name RSV IN_SLEEP IN_DOZE IN_IDLE CBUV CBOV CBUTF CBOTF Default 0 0 0 0 0 0 0 0 4.3.4.1 0x83.6 IN_SLEEP The In SLEEP Mode bit is set when the ISL94202 is in “SLEEP Mode” on page 121. The IN_SLEEP bit is cleared on initial power up, by the “CHMON Pin (37)” on page 99 going high or by the “LDMON Pin (38)” on page 104 going low. If bits 0x83.[6:4] are all 0, the device is either in “NORMAL Mode” on page 120 or “Powerdown State” on page 120, the device does not respond in Powerdown and the “RGO Pin (36)” on page 99 is off. 4.3.4.2 0x83.5 IN_DOZE The In DOZE Mode bit is set when the ISL94202 is in “DOZE Mode” on page 121. If bits 0x83.[6:4] are all 0, the device is either in “NORMAL Mode” on page 120 or “Powerdown State” on page 120, the device does not respond in Powerdown and the “RGO Pin (36)” on page 99 is off. 4.3.4.3 0x83.4 IN_IDLE The In IDLE Mode bit is set when the ISL94202 is in “IDLE Mode” on page 121. If bits 0x83.[6:4] are all 0, the device is either in “NORMAL Mode” on page 120 or “Powerdown State” on page 120, the device does not respond in Powerdown and the “RGO Pin (36)” on page 99 is off. 4.3.4.4 0x83.3 CBUV The Cell Balance Undervoltage bit is set during a Cell Balance Undervoltage condition, when all cell voltages are below threshold “0x1C-1D CBMIN” on page 49. At least one cell voltage must rise above the CBMIN threshold to recover from a Cell Balance Undervoltage condition, then the ISL94202 automatically clears the CBUV bit. 4.3.4.5 0x83.2 CBOV The Cell Balance Overvoltage bit is set during a Cell Balance Overvoltage condition, when all cell voltages are above threshold “0x1E-1F CBMAX” on page 50. At least one cell voltage must drop below the CBMAX threshold to recover from a Cell Balance Overvoltage condition, then the ISL94202 automatically clears the CBOV bit. 4.3.4.6 0x83.1 CBUTF The Cell Balance Under-Temperature Fault bit is set during a Cell Balance Under-Temperature condition. This occurs when the external temperature sensing thermistors indicate a battery pack temperature below the threshold defined by register “0x28-29 CBUT” on page 53. When the pack temperature rises above the threshold the ISL94202 automatically clears the CBUTF bit. 4.3.4.7 0x83.0 CBOTF The Cell Balance Over-Temperature Fault bit is set during a Cell Balance Over-Temperature condition. This occurs when the external temperature sensing thermistors indicate a battery pack temperature above the threshold defined by register “0x2C-2D CBOT” on page 55. When the pack temperature drops below the threshold the ISL94202 automatically clears the CBOTF bit. 4.3.5 0x84 CBFC (R/W) The Cell Balance FET Control register is located address 0x84. These bits enable MCU control of cell balancing only if the external MCU overrides the ISL94202 automatic cell balance operation (“0x87.5 µCCBAL” on page 83 = 1). Each CBxON bit (Table 52) controls the corresponding “CBn Pins” on page 94 cell balance FET drive output. FN8889 Rev.3.00 Oct.14.19 Page 78 of 153 ISL94202 4. System Registers Table 52. CBFC Bit Bit Name D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] CB8ON CB7ON CB6ON CB5ON CB4ON CB3ON CB2ON CB1ON 0 0 0 0 0 0 0 0 Default • A value of 0 written to any bit in this register turns OFF the corresponding CBx pin cell balance output (default). • A value of 1 written to any bit in this register turns ON the corresponding CBx pin cell balance output. The following conditions apply (no faults): • Cell Balance pin CBx = ON, if CBAL_ON = 1 and CBxON = 1 (see “0x87.0 CBAL_ON” on page 84) • Cell Balance pin CBx = OFF, if CBAL_ON = 0 or CBxON = 0 If µCCBAL = 0, the ISL94202 performs cell balancing. These bits are also used during automatic cell balancing, but their state is not intended to indicate if/when a CB FET is on. See “CBn Pins” on page 94 for more information on the cell balance FET drive pins and “Cell Balancing” on page 122 for more information on cell balancing operation. 4.3.6 0x85 Control 0 (R/W) Control register 0 enables a MCU or test system to control the ADC conversion, current sense gain and the multiplexer if it overrides scan operation by setting bit “0x87.2 µCSCAN” on page 84 to 1. The RSV bit should be set to 0 on a write and ignored on register read. Table 53. Control Register 0 Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Bit Name RSV ADCSTRT CG1 CG0 AO3 AO2 AO1 AO0 Default 0 0 0 0 0 0 0 0 4.3.6.1 0x85.6 ADCSTRT The ADC conversion start bit is used when an external MCU overrides measurement scan operation. When this bit is set to 1, an AD conversion is started. This bit automatically resets to 0 on execution and it does not indicate when the AD conversion is complete. 4.3.6.2 0x85.[5:4] CG The Current Gain setting bits are used when an external MCU overrides measurement scan operation. These bits set the gain of the amplifier which measures the voltage across the current sense resistor (“CSI1-2 Pins (47, 48)” on page 111). Available settings are shown in Table 54. Table 54. Current Gain Settings CG1 CG0 Current gain 0 0 x50 0 1 x5 1 0 x500 1 1 x500 If the MCU overrides measurement scan operation, the selected gain must be used in the current calculation (“0x8E-8F IPACK” on page 90). See “Current Monitoring/Response” on page 132 for more information. FN8889 Rev.3.00 Oct.14.19 Page 79 of 153 ISL94202 4.3.6.3 4. System Registers 0x85.[3:0] AO The Analog Output selection bits are used when an external MCU overrides measurement scan operation. The AO bits select (Table 55) which ISL94202 voltage sense pins are output from the internal analog MUX. The result is stored in registers “0xAA-AB - ADCV” on page 93 by the ADC when internal scan operation has been overridden. Table 55. Analog MUX Control 4.3.7 AO3 AO2 AO1 AO0 Output 0 0 0 0 OFF (Hi-Z) 0 0 0 1 VC1 0 0 1 0 VC2 0 0 1 1 VC3 0 1 0 0 VC4 0 1 0 1 VC5 0 1 1 0 VC6 0 1 1 1 VC7 1 0 0 0 VC8 1 0 0 1 Pack Current 1 0 1 0 VBAT/16 1 0 1 1 RGO/2 1 1 0 0 xT1 1 1 0 1 xT2 1 1 1 0 iT 1 1 1 1 OFF (Hi-Z) 0x86 Control 1 (R/W) Control register 0 enables a MCU or test system to control Load/Charger detection, power FET operation, and the PSD pin if it overrides automatic device operation by setting bits “0x87.6 µCFET” on page 82, “0x87.4 µCLMON” on page 83, and/or “0x87.3 µCCMON” on page 83 to 1. Table 56. Control Register 1 Address - Bits 0x86 - D[7] 0x86 - D[6] 0x86 - D[5] 0x86 - D[4] 0x86 - D[3] 0x86 - D[2] 0x86 - D[1] 0x86 - D[0] Name CLR_LERR LMON_EN CLR_CERR CMON_EN PSD PCFET CFET DFET Default 0 0 0 0 0 0 0 0 4.3.7.1 0x86.7 CLR_LERR The Clear Load Error bit resets the bit “0x82.0 LD_PRSNT” on page 77 if the MCU has taken control of the load monitor function by setting bit “0x87.4 µCLMON” on page 83 to 1. • Writing a 1 to CLR_LERR resets the LD_PRSNT bit. CLR_LERR automatically resets and is only active when µCLMON = 1. See “LDMON Pin (38)” on page 104 for more information. 4.3.7.2 0x86.6 LMON_EN The Load Monitor Enable bit is used by the MCU to turn the load monitor circuit ON or OFF if it has taken control of the monitor function by setting bit “0x87.4 µCLMON” on page 83 to 1. • Writing a 0 to this bit turns OFF the load monitor circuit (default). FN8889 Rev.3.00 Oct.14.19 Page 80 of 153 ISL94202 4. System Registers • Writing a 1 to this bit turns ON the load monitor circuit. After writing a 1 to this bit, the LDMON recovery circuit is pulsed once and the status of the bit “0x82.0 LD_PRSNT” on page 77 is updated. LMON_EN automatically clears. See “LDMON Pin (38)” on page 104 for more information. 4.3.7.3 0x86.5 CLR_CERR The Clear Charger Error bit resets the bit “0x82.1 CH_PRSNT” on page 77 if the MCU has taken control of the charger monitor function by setting bit “0x87.3 µCCMON” on page 83 to 1. Writing a 1 to CLR_CERR resets the CH_PRSNT bit. This bit automatically resets and is only active when µCCMON = 1. See “CHMON Pin (37)” on page 99 for more information. 4.3.7.4 0x86.4 CMON_EN The Charger Monitor Enable bit is used by the MCU to turn the charger monitor circuit ON or OFF if it has taken control of the monitor function by setting bit “0x87.3 µCCMON” on page 83 to 1. • Writing a 0 to this bit turns OFF the charger monitor circuit (default). • Writing a 1 to this bit turns ON the charger monitor circuit. After writing a 1 to this bit, the CHMON recovery circuit is pulsed once and the status of the bit “0x82.1 CH_PRSNT” on page 77 is updated. CMON_EN automatically clears. See “CHMON Pin (37)” on page 99 for more information. 4.3.7.5 0x86.3 PSD The pack shutdown bit is used by the MCU to assert (set high) the “PSD Pin (32)” on page 98. This output can be used to drive external circuitry to blow a fuse. The ISL94202 digital pins operate relative to the “RGO Pin (36)” on page 99, which provides ~2.5V maximum logic High. • Write a 0 to his register to set the PSD pin low (default). • Write a 1 to this register to set the PSD pin high. This bit is also set in conditions where PSD is asserted automatically by the ISL94202 if enabled by the following bits; “0x4A.7 CELLF PSD” on page 67, “0x4A.0 OWPSD” on page 68 and “0x08-09 VCELL OVLO” on page 38. Follow the links for more information. 4.3.7.6 0x86.2 PCFET The Pre-Charge FET bit is used by the MCU to turn on or off the “PCFET Pin (44)” on page 108. • Writing a 0 to this bit turns PCFET OFF (default). • Writing a 1 to this bit turns PCFET ON. This bit is set to 0 automatically by the ISL94202 in COC, DOC, or DSC conditions, unless the automatic response is disabled by the bit “0x87.6 µCFET” on page 82. If automatic FET control is disabled, a DSC condition still forces the power FETs off because a MCU cannot override the DSC response. Figure 37 on page 82 shows the timing between set/clear of this bit and the PCFET pin. See “0x18-19 COC & COCT” on page 46, “0x16-17 DOC & DOCT” on page 43, and “0x1A-1B DSC & DSCT” on page 48 for more information. 4.3.7.7 0x86.1 CFET The Charge FET bit is used by the MCU to turn on or off the “CFET Pin (45)” on page 108. • Writing a 0 to this bit turns CFET OFF (default). • Writing a 1 to this bit turns CFET ON. FN8889 Rev.3.00 Oct.14.19 Page 81 of 153 ISL94202 4. System Registers This bit is set to 0 automatically by the ISL94202 in a COC or DSC condition, unless the automatic response is disabled by the bit “0x87.6 µCFET” on page 82. If automatic FET control is disabled, a DSC condition still forces the power FETs off because a MCU cannot override DSC response. Figure 37 on page 82 shows the timing relationship between set/clear of this bit and the CFET pin. See “0x18-19 COC & COCT” on page 46 and “0x1A-1B DSC & DSCT” on page 48 for more information. 4.3.7.8 0x86.0 DFET The Discharge FET bit is used by the MCU to turn on or off the “DFET Pin (42)” on page 108. • Writing a 0 to this bit turns DFET OFF (default). • Writing a 1 to this bit turns DFET ON. This bit is set to 0 automatically by the ISL94202 in a DOC or DSC condition, unless the automatic response is disabled by the bit “0x87.6 µCFET” on page 82. If automatic FET control is disabled, a DSC condition still forces the power FETs off because a MCU cannot override DSC response. Figure 37 shows the timing relationship between set/clear of this bit and the DFET pin. See “0x16-17 DOC & DOCT” on page 43 and “0x1A-1B DSC & DSCT” on page 48 for more information. SCL Bit 3 SDA Bit 2 Bit 1 Bit 0 Bit 1 ACK Bit 0 ACK DATA ~1µs (~500µs if Both FETs Off) ~1µs tFTON DFET/CFET Turn On 10% 90% tFTOFF 90% 10% Figure 37. I2C FET Control Timing 4.3.8 0x87 - Control 2 (R/W) Control register 2 enables a MCU or test system to override most of the ISL94202 autonomous operations. The RSV bit should be set to 0 on a write and ignored on register read. Table 57. Control Register 2 Address - Bits 0x87 - D[7] 0x87 - D[6] 0x87 - D[5] 0x87 - D[4] 0x87 - D[3] 0x87 - D[2] 0x87 - D[1] 0x87 - D[0] Name RSV µCFET µCCBAL µCLMON µCCMON µCSCAN OW_STRT CBAL_ON Default 0 0 0 0 0 0 0 0 4.3.8.1 0x87.6 µCFET The MCU FET control bit overrides automatic FET control by the ISL94202. When the MCU sets this bit it is responsible for enabling/disabling the FETs when necessary under most conditions. The exceptions are Short-Circuit Current, Open-Wire, Internal Over-Temperature, OVLO and UVLO faults, plus SLEEP, and FETSOFF (“FETSOFF Pin (33)” on page 98) conditions override the µCFET control bit and automatically force the appropriate power FETs off. • Writing a 0 to bit µCFET means automatic FET control is operational (default). • Writing a 1 to bit µCFET means the FETs are controlled by an external MCU. For more information on the relationship of the µCFET setting and automatic FET control response scenarios also see: Cell Voltages FN8889 Rev.3.00 Oct.14.19 Page 82 of 153 ISL94202 4. System Registers • “0x00-01 CDPW & VCELL OV” on page 35 and “0x02-03 VCELL OVR” on page 36 • “0x04-05 LDPW & VCELL UV” on page 37 and “0x06-07 VCELL UVR” on page 38 • “0x08-09 VCELL OVLO” on page 38 and “0x80.1 OVLOF” on page 73 • “0x0A-0B VCELL UVLO” on page 39 and “0x80.3 UVLOF” on page 72 • “0x0E-0F VCELL LVCL” on page 40 and “0x82.7 LVCHG” on page 76 Pack Current • “0x16-17 DOC & DOCT” on page 43 and “0x81.2 DOCF” on page 74 • “0x18-19 COC & COCT” on page 46 and “0x81.1 COCF” on page 75 • “0x1A-1B DSC & DSCT” on page 48 and “0x81.3 DSCF” on page 74 Temperature • “0x30-31 COT” on page 56, “0x32-33 COTR” on page 57, and “0x80.6 COTF” on page 71 • “0x34-35 CUT” on page 58, “0x36-37 CUTR” on page 58, and “0x80.7 CUTF” on page 71 • “0x38-39 DOT” on page 59, “0x3A-3B DOTR” on page 60, and “0x80.4 DOTF” on page 72 • “0x3C-3D DUT” on page 61, “0x3E-3F DUTR” on page 61, and “0x80.5 DUTF” on page 72 • “0x40-41 IOT” on page 62, “0x42-43 IOTR” on page 63, and “0x81.0 IOTF” on page 75 Open Wire • “0x14-15 OWT” on page 43 and “0x81.5 OWF” on page 74 4.3.8.2 0x87.5 µCCBAL The MCU Cell Balancing bit overrides automatic CB FET control by the ISL94202. When the MCU sets this bit it is responsible for enabling/disabling the CB FETs. See “0x85 Control 0 (R/W)” on page 79 and “0x49 Cell Select” on page 67. • Writing a 0 to this bit means automatic cell balancing by the ISL94202 is enabled (default). • Writing a 1 to this bit means automatic cell balancing by the ISL94202 is disabled. For more information on automatic and MCU enabled cell balancing, see section “Cell Balancing” on page 122. 4.3.8.3 0x87.4 µCLMON The MCU Load Monitoring bit overrides automatic load monitoring control by the ISL94202. • Writing a 0 to this bit means automatic load monitoring by the ISL94202 is enabled (default). • Writing a 1 to this bit means automatic load monitoring by the ISL94202 is disabled. The MCU must trigger load detection using “0x86.6 LMON_EN” on page 80. For more information on operations dependent on load monitoring, see “LDMON Pin (38)” on page 104, “OV Detection/Response” on page 129, “UV Detection & Response” on page 130, and “Current Monitoring/Response” on page 132. 4.3.8.4 0x87.3 µCCMON The MCU Charger Monitoring bit overrides automatic charger monitoring control by the ISL94202. • Writing a 0 to this bit means automatic charger monitoring by the ISL94202 is enabled (default). • Writing a 1 to this bit means automatic charger monitoring by the ISL94202 is disabled. The MCU must trigger load detection using “0x86.4 CMON_EN” on page 81. For more information on operations dependent on charger monitoring, see “CHMON Pin (37)” on page 99, “OV Detection/Response” on page 129, “UV Detection & Response” on page 130, and “Current Monitoring/Response” on page 132. FN8889 Rev.3.00 Oct.14.19 Page 83 of 153 ISL94202 4.3.8.5 4. System Registers 0x87.2 µCSCAN The MCU System Scan bit overrides automatic system measurement scans that are normally based on the device “System Modes” on page 119. This bit is reset if the “0x47.[7:3] WDT” on page 65 expires, system scans only resume on receipt of the next I2C transaction. • Writing a 0 to this bit means the ISL94202 automatically performs the system scan based on the device Mode (default). • Writing a 1 to this bit means the ISL94202 does not perform the system scans automatically. The MCU must trigger the measurements normally executed by the automatic system scans. See “0x85 Control 0 (R/W)” on page 79. See “System Scans” on page 116 for more information. 4.3.8.6 0x87.1 OW_STRT The Open Wire Start bit triggers an open-wire scan. This bit automatically resets when completing the open-wire scan. This bit is only active if “0x4A.1 DOWD” on page 68 is 1 or µCSCAN is 1. • Writing a 0 to this bit does nothing, but reading a 0 means no open-wire scan is being performed (default). • Writing a 1 to this bit initiates an open-wire scan. For more information, see “Open Wire” on page 126. 4.3.8.7 0x87.0 CBAL_ON The Cell Balance on bit turns on selected cell balance pins if the MCU Cell Balancing bit (µCCBAL) is set to 1. This bit is only operational if the µCCBAL bit is 1. • Writing a 0 to this bit disables all CBn outputs (default). • Writing a 1 to this bit enables CBn outputs previously set to 1 in register “0x84 CBFC (R/W)” on page 78 and disables the outputs set to 0. For more information, see “MCU CB” on page 126. 4.3.9 0x88 - Control 3 Control register 3 enables a MCU or test system to override the ISL94202 automatic mode transitions and select a specific mode. When set, the device remains in the selected Mode as automatic mode transitions are blocked. Setting more than one of these bits simultaneously to 1 is not supported. These bits are not intended to indicate device Mode status, see “0x83 - Status 3 (R)” on page 77. The device does not include a bit to indicate “Powerdown State” on page 120 because register access is not possible in Powerdown. Table 58. Control Register 3 Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Bit Name RSV RSV RSV RSV PDWN SLEEP DOZE IDLE 0 0 0 0 0 0 0 0 Default The RSV bits should be set to 0 on a write and ignored on register read. 4.3.9.1 0x88.3 PDWN The Powerdown bit is used by the MCU to force the ISL94202 into the “Mode Exceptions” on page 122. This bit can be used to place the pack in the lowest current state for prolonged storage at the end of battery pack test. The device can only be brought out of Powerdown by a charger connection detection (“Charger Detection” on page 102) as no communications are possible. On wake-up from Powerdown the device loads settings to the registers backed by EEPROM while the other registers are set to default including this bit. • Writing a 0 (default) to this bit is not possible if the device is in “Powerdown State” on page 120, only a CHMON detection (“CHMON Pin (37)” on page 99) wakes the device from Powerdown. FN8889 Rev.3.00 Oct.14.19 Page 84 of 153 ISL94202 4. System Registers • Writing a 1 to this bit puts the device in the Powerdown State. • Reading a 0 from this bit shows the device is not in the Powerdown State, although any response from the device indicates it is not in Powerdown. For more information, see “System Modes” on page 119. 4.3.9.2 0x88.2 SLEEP The SLEEP bit is used by a MCU to force the ISL94202 into “SLEEP Mode” on page 121. • Writing a 1 to this bit puts the device in SLEEP Mode. • Overwriting a 1 with a 0 (default) on this bit enables normal ISL94202 Mode operation. • Reading a 0 from this bit shows the device is not forced into SLEEP Mode by command from the MCU. For more information, see “System Modes” on page 119. 4.3.9.3 0x88.1 DOZE The DOZE bit is used by a MCU to force the ISL94202 into “DOZE Mode” on page 121. • Writing a 1 to this bit puts the device in DOZE Mode. • Overwriting a 1 with a 0 (default) on this bit enables normal ISL94202 Mode operation. • Reading a 0 from this bit shows the device is not forced into DOZE Mode by command from the MCU. For more information, see “System Modes” on page 119. 4.3.9.4 0x88.0 IDLE The IDLE bit is used by a MCU to force the ISL94202 into “IDLE Mode” on page 121. • Writing a 1 to this bit puts the device in IDLE Mode. • Overwriting a 1 with a 0 (default) on this bit enables normal ISL94202 Mode operation. • Reading a 0 from this bit shows the device is not forced into IDLE Mode by command from the MCU. For more information, see “System Modes” on page 119. 4.3.10 0x89 - EEPROM Enable This register contains the bit used for reading from and programming the ISL94202 EEPROM. The RSV bits should be set to 0 on a write and ignored on register read. Table 59. EEPROM Enable Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Bit Name RSV RSV RSV RSV RSV RSV RSV EEEN 0 0 0 0 0 0 0 0 Default 4.3.10.1 0x89.0 EEEN The EEPROM Enable bit determines read/write access to either the control registers or the EEPROM. • Set EEEN = 0 (default) by writing 0x00 to register 0x89 to access the control registers. • Set EEEN = 1 by writing 0x01 to register 0x89 to access the ISL94202 EEPROM. Reading from and writing to control/status registers and reading from EEPROM can be performed using a byte operation (read/write 1 byte) or page operation (read/write 4 bytes). Writing to EEPROM must be performed using a byte operation, and all 4 bytes in the page must be written. For more information, see “Byte Write” on page 143 and “EEPROM Write” on page 148. For more information on programming the EEPROM, see “Control/Data Registers” on page 138. FN8889 Rev.3.00 Oct.14.19 Page 85 of 153 ISL94202 4.4 4. System Registers 0x8A-AB Data Registers The ISL94202 has a 14-bit ADC for voltage measurements. The outputs of most measurements are stored as 12-bits spanning two 8-bit registers to represent the digitized result. When two registers are used, the portion of the result is described in the register map name such as MSB or LSB. Table 60. Data Registers Page # Register Address (Hex) Bit Function Register Name 7 6 5 4 3 2 1 0 Factory Default (Hex) Type N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R N/A R Data Registers 89 89 90 90 91 91 91 91 91 91 91 91 91 92 92 92 93 8A CELMIN LSB Minimum Cell Voltage CELMIN [7:0] 8B CELMIN MSB RSV 8C CELMAX LSB Maximum Cell Voltage CELMAX [7:0] 8D CELMAX MSB RSV 8E IPACK LSB Pack Current IPACK [7:0] 8F IPACK MSB RSV 90 VCELL1 LSB Cell 1 Voltage VCELL1 [7:0] 91 VCELL1 MSB RSV 92 VCELL2 LSB Cell 2 Voltage VCELL2 [7:0] 93 VCELL2 MSB RSV 94 VCELL3 LSB Cell 3 Voltage VCELL3 [7:0] 95 VCELL3 MSB RSV 96 VCELL4 LSB Cell 4 Voltage VCELL4 [7:0] 97 VCELL4 MSB RSV 98 VCELL5 LSB Cell 5 Voltage VCELL5 [7:0] 99 VCELL5 MSB RSV 9A VCELL6 LSB Cell 6 Voltage VCELL6 [7:0] 9B VCELL6 MSB RSV 9C VCELL7 LSB Cell 7 Voltage VCELL7 [7:0] 9D VCELL7 MSB RSV 9E VCELL8 LSB Cell 8 Voltage VCELL8 [7:0] 9F VCELL8 MSB RSV A0 ITEMP LSB Internal Temperature IT [7:0] A1 ITEMP MSB RSV A2 XT1 LSB External Temperature 1 XT1 [7:0] A3 XT1 MSB RSV A4 XT2 LSB External Temperature 2 XT2 [7:0] A5 XT2 MSB RSV A6 VBATT LSB Pack Voltage VBATT [7:0] A7 VBATT MSB RSV A8 VRGO LSB RGO Voltage VRGO [7:0] A9 VRGO MSB RSV AA ADC LSB 14-bit ADC Voltage ADC [7:0] N/A R AB ADC MSB RSV RSV 14-bit ADC Voltage ADC [D:8] N/A R Reserved (RSV) RSV RSV RSV N/A N/A AC - AF FN8889 Rev.3.00 Oct.14.19 RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV RSV Minimum Cell Voltage CELMIN [B:8] Maximum Cell Voltage CELMAX [B:8] Pack Current IPACK [B:8] Cell 1 Voltage VCELL1 [B:8] Cell 2 Voltage VCELL2 [B:8] Cell 3 Voltage VCELL3 [B:8] Cell 4 Voltage VCELL4 [B:8] Cell 5 Voltage VCELL5 [B:8] Cell 6 Voltage VCELL6 [B:8] Cell 7 Voltage VCELL7 [B:8] Cell 8 Voltage VCELL8 [B:8] Internal Temperature IT [B:8] External Temperature 1 XT1 [B:8] External Temperature 2 XT2 [B:8] Pack Voltage VBATT [B:8] RGO Voltage VRGO [B:8] RSV RSV RSV RSV Page 86 of 153 ISL94202 4. System Registers The ranges and step-sizes listed for measurement registers are the ideal values to be used for calculation purposes. The usable measurement range is also limited by the recommended operating conditions and by non-idealities of the measurement channel. Measurement result registers may or may not reach the maximum or minimum for input voltages within the ideal voltage range listed. Formulas used for conversion between voltages and register values include constants. The following section explains the origin of these constants. Not all of these parameters are included in every conversion, see the specific register description for the correct method of conversion for each. 4.4.1 Conversion Constants The ISL94202 has an internal 14-bit ADC and a precision 1.8V voltage reference for measurement of all of the system voltages. The full-scale ADC reading is limited to this 1.8V reference voltage. Each voltage to be measured is level shifted to the input of the ADC. Given a 1.8V full-scale range, most of these voltages must be divided to remain within this range. Given a maximum cell voltage of 4.8V and the 1.8V ADC full-scale voltage, cell voltages must be scaled by 1.8/4.8 or 3/8 to use the entire input range of the ADC. The following are used in the next two subsections as examples of a cell voltage reading conversion from Analog to Digital and Digital to Analog. • Vcell = 3.85V = The actual cell voltage. • Vref = 1.8V = The ADC reference. • Vscale = (3/8) = The ADC reference voltage divided by the full scale voltage (4.8V). • Vshift = Level shifted voltage fed to the ADC. • Ratio = Ratio of the Level shifted voltage to the ADC reference voltage. • HexValue10 = Digitized final ADC output value. 4.4.1.1 Threshold Setting The first example covers the conversion from an analog voltage (Vcell) to its corresponding digital value as if setting a voltage threshold register. 1. Voltage Division First scale the input voltage by multiplying it by the ratio of 3/8. 3 V shift = V cell  --8 3 1.44375 = 3.85  --8 2. Ratio of voltage to Vref Calculate the ratio of the measured voltage to Vref. V shift Ratio = ------------V ref 1.44375 0.8020834 = --------------------1.8 FN8889 Rev.3.00 Oct.14.19 Page 87 of 153 ISL94202 4. System Registers 3. Ratio to 12-bit value Finally convert this ratio to a 12-bit decimal value by multiplying it by the 12-bit maximum value. HexValue 10 = Ratio   2 12 – 1 3285 = 0.8020834  4095 4.4.1.2 ADC Reading The second example covers the conversion from a digital value to a voltage as if reading a voltage measurement result from a data register. 1. 12-bit value to Ratio Take the digitized value and divide it by the maximum digital value possible (rounding has occurred below and was required due to the quantization error inherent to all ADCs). HexValue 10 Ratio = --------------------------------12 2 – 1 3285 0.8020834 = ------------4095 2. Voltage derived from Vref and Ratio Use this value to derive the scaled voltage from the reference voltage. V shift = Ratio  V ref 1.44375 = 0.8020834  1.8 3. Reverse Level Shifted voltage Divide by the scaled ADC input level by the value of the scaler (or multiply by its inverse). Vshift V cell = ---------------3 ---  8 8 3.85 = 1.44375  --3 FN8889 Rev.3.00 Oct.14.19 Page 88 of 153 ISL94202 4.4.1.3 4. System Registers Cell Voltage Formula Putting the information in the above steps together gives the final formulas for conversion between Analog and Digital values for Cell voltages. To calculate a register threshold from a desired voltage setting use: V meas  3  4095 HexValue 10 = --------------------------------------------1.8  8 To calculate a voltage from a measured value or threshold setting use: HexValue 10  1.8  8 V meas = --------------------------------------------------------4095  3 4.4.2 0x8A-8B CELMIN The VCELL Minimum registers store the lowest measured cell voltage from the last cell voltage system scan. The data is split between two registers. The upper 4 bits of the CELMIN result are stored in the lower 4 bits of 0x8B while the remaining 8 bits are stored in 0x8A as shown in Table 61. The upper 4 bits of register 0x8B are reserved and should be ignored on read. Table 61. CELMIN Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0x8A CELMIN7 CELMIN6 CELMIN5 CELMIN4 CELMIN3 CELMIN2 CELMIN1 CELMIN0 0x8B RSV RSV RSV RSV CELMINB CELMINA CELMIN9 CELMIN8 The formula to convert the register decimal value to voltage is: HEXvalue 10  1.8  8 Cell v = ---------------------------------------------------------4095  3 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. For more information on cell measurements, see “VCn Pins” on page 94. 4.4.3 0x8C-8D CELMAX The VCELL Maximum registers store the highest measured cell voltage from the last cell voltage system scan. The data is split between two registers. The upper 4 bits of the CELMAX result are stored in the lower 4 bits of 0x8D while the remaining 8 bits are stored in 0x8C as shown in Table 62. The upper 4 bits of register 0x8D are reserved and should be ignored on read. Table 62. CELMAX Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0x8C CELMAX7 CELMAX6 CELMAX5 CELMAX4 CELMAX3 CELMAX2 CELMAX1 CELMAX0 0x8D RSV RSV RSV RSV CELMAXB CELMAXA CELMAX9 CELMAX8 The formula to convert the register decimal value to voltage is: HEXvalue 10  1.8  8 Cell v = ---------------------------------------------------------4095  3 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. For more information on cell measurements, see “VCn Pins” on page 94. FN8889 Rev.3.00 Oct.14.19 Page 89 of 153 ISL94202 4.4.4 4. System Registers 0x8E-8F IPACK The Pack current measurement result registers store the voltage measured across the current sense resistor from the last system scan. The data is split between two registers. The upper 4 bits of the IPACK result are stored in the lower 4 bits of 0x8F while the remaining 8 bits are stored in 0x8E as shown in Table 63. The upper 4 bits of register 0x8F are reserved and should be ignored on read. Table 63. IPACK Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0x8E IPACK7 IPACK6 IPACK5 IPACK4 IPACK3 IPACK2 IPACK1 IPACK0 0x8F RSV RSV RSV RSV IPACKB IPACKA IPACK9 IPACK8 The value in this register is only valid if either “0x82.2 CHING” on page 77 or “0x82.3 DCHING” on page 76 bit is set. If neither of these bits are set, the value in this register is invalid and must be ignored. The formula to convert the register decimal value to current is: HEXvalue 10  1.8 Current A = --------------------------------------------------------4095  Gain  R sense The equation constants are detailed in “0x8A-AB Data Registers” on page 86 and “0x85.[5:4] CG” on page 79. For more information on IPACK measurements, see “CSI1-2 Pins (47, 48)” on page 111. 4.4.5 0x90-9F VCELL1-8 The VCELL registers store the cell voltage measurement result from the last cell voltage system scan. The data is split between two registers. The upper 4 bits of the VCELL result are stored in the lower 4 bits of 0x9x while the remaining 8 bits are stored in 0x9(x-1) as shown in Table 64. The full set of VCELL registers are listed in Table 2. The upper 4 bits of register 0x9x are reserved and should be ignored on read. Table 64. VCELLx Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0x90 VCELL17 VCELL16 VCELL15 VCELL14 VCELL13 VCELL12 VCELL11 VCELL10 0x91 RSV RSV RSV RSV VCELL1B VCELL1A VCELL19 VCELL18 - - - - - - - - - 0x9E VCELL87 VCELL86 VCELL85 VCELL84 VCELL83 VCELL82 VCELL81 VCELL80 0x9F RSV RSV RSV RSV VCELL8B VCELL8A VCELL89 VCELL88 The cell must be selected (set to 1) in register “0x49 Cell Select” on page 67 for the VCELL data register(s) to update during system scans. If the cell is not enabled, it is not measured and the value in the register is invalid. The formula to convert the register decimal value to cell voltage is: HEXvalue 10  1.8  8 Cell v = ---------------------------------------------------------4095  3 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. For more information on cell measurements, see “VCn Pins” on page 94. FN8889 Rev.3.00 Oct.14.19 Page 90 of 153 ISL94202 4.4.6 4. System Registers 0xA0-A1 ITEMP The ITEMP registers store the internal temperature voltage measurement result from the last system scan. The data is split between two registers. The upper 4 bits of the ITEMP result are stored in the lower 4 bits of 0xA1 while the remaining 8 bits are stored in 0xA0 as shown in Table 65. The upper 4 bits of register 0xA1 are reserved and should be ignored on read. Table 65. ITEMP Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0xA0 IT7 IT6 IT5 IT4 IT3 IT2 IT1 IT0 0xA1 RSV RSV RSV RSV ITB ITA IT9 IT8 The ITEMP voltage is not scaled so the 3/8 factor is not part of the formula to convert the register decimal value to voltage as the following shows: HEXvalue 10  1.8 Temp v = -----------------------------------------------4095 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. The formula for converting from voltage (V) to temperature (C) is:  Temp v   1000 ITemp = ------------------------------------------ – 273.15 1.8527 4.4.7 0xA2-A5 XT1-2 The External Temperature 1 and 2 registers store the voltage measurement results from the last system scan at the device “Thermistor Pins (20-22)” on page 96. The data for each of the two pins is split between two pairs of registers. The upper 4 bits of the xT1 (xT2) result are stored in the lower 4 bits of 0xA3 (0xA5) while the remaining 8 bits are stored in 0xA2 (0xA4) as shown in Table 65. The upper 4 bits of registers 0xA3 and 0xA5 are reserved and should be ignored on read. Table 66. EXT1 Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0xA2 XT17 XT16 XT15 XT14 XT13 XT12 XT11 XT10 0xA3 RSV RSV RSV RSV XT1B XT1A XT19 XT18 0xA4 XT27 XT26 XT25 XT24 XT23 XT22 XT21 XT20 0xA5 RSV RSV RSV RSV XT2B XT2A XT29 XT28 The formula to convert the register decimal value to voltage is: HEXvalue 10  1.8 Temp v = -----------------------------------------------4095 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. The conversion from voltage to temperature is a function of the thermistor and external circuitry used. For more information on external temperature measurement, see “Thermistor Pins (20-22)” on page 96. FN8889 Rev.3.00 Oct.14.19 Page 91 of 153 ISL94202 4.4.8 4. System Registers 0xA6-A7 VBATT The VBATT registers store the voltage measurement results from the last system scan. The data is split between two registers. The upper 4 bits of the VBATT result are stored in the lower 4 bits of 0xA7 while the remaining 8 bits are stored in 0xA6 as shown in Table 67. The upper 4 bits of register 0xA7 are reserved and should be ignored on read. Table 67. VBATT Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0xA6 VBATT7 VBATT6 VBATT5 VBATT4 VBATT3 VBATT2 VBATT1 VBATT0 0xA7 RSV RSV RSV RSV VBATTB VBATTA VBATT9 VBATT8 The VBATT voltage presented to the ADC for measurement is divided by 32 between the “VBATT Pin (48)” on page 113 and VSS. The formula to convert the register decimal value to voltage is: HEXvalue 10  1.8  32 VBATT v = ------------------------------------------------------------4095 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. 4.4.9 0xA8-A9 VRGO The VRGO registers store the voltage measurement results from the last system scan. The data is split between two registers. The upper 4 bits of the VRGO result are stored in the lower 4 bits of 0xA9 while the remaining 8 bits are stored in 0xA8 as shown in Table 67. The upper 4 bits of register 0xA9 are reserved and should be ignored on read. Table 68. VRGO Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0xA8 VRGO7 VRGO6 VRGO5 VRGO4 VRGO3 VRGO2 VRGO1 VRGO0 0xA9 RSV RSV RSV RSV VRGOB VRGOA VRGO9 VRGO8 The VRGO voltage presented to the ADC for measurement is divided by 2 between the “RGO Pin (36)” on page 99 and VSS. The formula to convert the register decimal value to voltage is: HEXvalue 10  1.8  2 VBATT v = ---------------------------------------------------------4095 The equation constants are detailed in “0x8A-AB Data Registers” on page 86. FN8889 Rev.3.00 Oct.14.19 Page 92 of 153 ISL94202 4.4.10 4. System Registers 0xAA-AB - ADCV The 14-bit ADC Voltage register contains a 2’s complement calibrated voltage output from the device ADC. In NORMAL Mode this reading is not usable because it cannot be associated with a specific monitored voltage. If a MCU takes control of scan operation then this reading becomes useful. The data is split between two registers. The upper 6 bits of the ADCV result are stored in the lower 6-bits of 0xAB while the remaining 8 bits are stored in 0xAA as shown in Table 69. The upper 2 bits of register 0xAB are reserved and should be ignored on read. Table 69. ADCV Bit D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 0xAA ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0 0xAB RSV RSV ADCVD ADCVC ADCVB ADCVA ADCV9 ADCV8 To use this register a MCU must take control of the system scan (“0x87.2 µCSCAN” on page 84), use register “0x85.[3:0] AO” on page 80, set the internal multiplexer to select the desired channel, and finally set the bit “0x85.6 ADCSTRT” on page 79 to trigger the ADC. The conversion result is found in this register. The following are the formulas for converting from the register digital value to voltage:  HEXvalue 10 – 16384   1.8 HEXvalue 10  8191  ADC V = ---------------------------------------------------------------------------8191 HEXvalue 10  1.8 HEXvalue 10  8191  ADC V = -----------------------------------------------8191 FN8889 Rev.3.00 Oct.14.19 Page 93 of 153 ISL94202 5. 5.1 5. Pin Function Pin Function VCn Pins Pins VC0 - VC8 are the voltage sense inputs of the ISL94202, which are used by the device in pairs to sense the differential voltage across each cell. Positive pin VCn and negative pin VCn-1 are connected to the ADC through a multiplexer. Each voltage sense input uses an external RC filter to minimize noise and protect against EMI and voltage transients. The filters carry the loop currents produced by EMI and should be placed as close to the battery connector as possible. Connect the ground terminals of the capacitors directly to a solid ground plane. Place any vias in line to the signal inputs so that the inductance of these forms a low pass filter with the grounded capacitors. The filtered battery cell voltages internally connect to the cell voltage monitoring system. The monitoring system contains a multiplexer to select a specific input, and an analog-to-digital converter. These pins should be connected to their respective cells as shown in Figure 38 on page 95 through a 1kΩ resistor, with a 47nF capacitor at the VCn pin to the VSS ground plane (“VSS Pin (18, 28, 29)” on page 95). Renesas recommends that capacitors connected to cells are fail safe or fail open types. See “Reduced Cell Count” on page 150 for configuring the VC pins in applications with less than 8 cells. 5.2 CBn Pins The Cell Balance pins, CB1 - CB8, are the cell balance driver outputs of the ISL94202. A combination of NMOS and PMOS FETs are driven by these pins to enable external cell balancing operation. The ISL94202 cell balancing outputs are current sources/sinks that are switched on and off to balance a cell. The cell balance FETs are driven by a current source (Cells 1-5) or sink (Cells 6-8) of 25µA, the simplified diagram is shown in Figure 38. Cell balancing requires four external components; A cell balance FET, a gate-source resistor (180-330kΩ), an 10kΩ isolation resistor and a cell balance current setting resistor (R2) in series with the FET drain. Use the equation below to calculate the cell balance current: V CELL I CB = ------------------------------------ R 2 + R DSON  Set the gate-source resistor so the voltage does not exceed 7V. A Zener across the gate-source of the FET can be used to protect less robust FETs and the CBn pin from EOS in more severe environments. The gate isolation resistor between the CBn pin and the balance FET gate serves primarily to protect the FET and the CBn pin. It limits the current spike that occurs during FET turn on, which is a function of the gate capacitance. The CB pins can be controlled either externally from a MCU or by the ISL94202 automatically (default). Setting bit “0x87.5 µCCBAL” on page 83 to 1 gives the MCU control of the CB pins. For more information, see “Cell Balancing” on page 122. See “Reduced Cell Count” on page 150 for configuring the CB pins in applications with less than 8 cells. FN8889 Rev.3.00 Oct.14.19 Page 94 of 153 ISL94202 5. Pin Function 47nF 10kΩ CB8 330kΩ 39Ω 1kΩ VC7 39Ω 39Ω 39Ω 39Ω VC6 CB6 CB5 330kΩ 1kΩ VC4 47nF 10kΩ CB4 330kΩ 1kΩ VC3 47nF 10kΩ CB3 330kΩ 1kΩ VC2 47nF 10kΩ CB2 330kΩ 1kΩ VC1 47nF 10kΩ CB1 330kΩ 1kΩ VC0 CB4ON 4M CB3ON 10V CB2ON 10V 10V 10V 10V CB1ON 4M 4M 4M 4M 4M VSS CB8ON CB7ON 25µA 47nF 10V VC5 47nF 10kΩ CB5ON 25µA 39Ω 4M 25µA 330kΩ 1kΩ 39Ω 10V ENABLE 25µA 47nF 10kΩ 4M 25µA 330kΩ 1kΩ 39Ω CB7 10V CBAL_ON 25µA 47nF 10kΩ ISL94202 25µA VC8 25µA 1kΩ CB6ON VSS Figure 38. VCn/CBn and CB Drive Circuitry Note: The internal 10V Zener is selected based on the device ESD diodes. It is not intended to limit the VGS of the external CB FET. It is an internal device that helps protect the pins from ESD/Latch-up/Hot plug, although the primary purpose is ESD protection. 5.3 VSS Pin (18, 28, 29) VSS is the ISL94202 analog ground pin. It must have a solid connection to the ground plane(s). The digital and analog ground planes should connect together as close to the VSS pin Via as possible. The Exposed Pad (EPAD) on the bottom of the ISL94202 must also be tied to analog ground. Multiple Vias are recommended for good thermal conductivity. 5.4 VREF Pin (19) The ISL94202 Reference Voltage pin is connected to the internal 1.8V reference used by the ADC. This pin should not be loaded as this could cause significant ADC error. The VREF pin should be connected to a 1µF capacitor connected to Analog GND. FN8889 Rev.3.00 Oct.14.19 Page 95 of 153 ISL94202 5. Pin Function There is a 6k resistor internal to the ISL94202 between the VREF Buffer and the ADC Reference input. The VREF pin is connected to this node so that the external cap completes the LPF for the ADC Ref input. A 0.5µA current pulled out of the VREF pin causes an error of 3mV on this node. This induces measurement errors on all ADC measurements. WARNING: Any noise on this node directly couples into the ADC and its measurements. With the exception of the external capacitor other connections to this pin are not recommended. 5.5 Thermistor Pins (20-22) The ISL94202 monitors the internal temperature of the device (“0xA0-A1 ITEMP” on page 91) plus two external NTC thermistors (“0xA2-A5 XT1-2” on page 91). Three device pins are used for connections to external temperature measurement circuits; xT1, xT2, and TEMPO. Pin xT1 (20) is dedicated to monitoring the battery pack temperature. Charge and discharge temperature faults are linked to the voltage at this pin. See “0x28-29 CBUT” on page 53 through “0x3E-3F DUTR” on page 61. Pin xT2 (21) is configurable, it can monitor either pack temperature (default setting of “0x4A.5 XT2M” on page 68 to 0) or the temperature of the FETs by setting the bit XT2M to 1. The TEMPO pin (22) supplies the bias voltage to the thermistors during measurement, it achieves this using an internal PMOS switch between RGO and TEMPO pins. The switch to the TEMPO pin is only turned on while temperature measurements are being taken to save power. Typical value is 2.45V (see “VTEMPO” on page 18). When the MCU is in control of the scan (“0x87.2 µCSCAN” on page 84), the TEMPO pin is turned on when the analog MUX (“0x85.[3:0] AO” on page 80) for the ADC is set to read xT1 or xT2. The temperature voltages have two selectable gain settings (“0x4A.4 TGAIN” on page 68) applied to both pins. Setting the TGain bit = 0 (default) sets the gain to 2x, providing for a full scale input voltage = 0.9V. The device is calibrated at the default temperature gain setting of 2x, this is the preferred setting because it produces a more linear temperature response. Using TGain = 1 sets the gain to 1 and is not recommended. The external voltage reading as a function of temperature in the default configurations given in Figure 39 are shown in Table 70. Table 70. xT Pin Voltage vs Temperature and Configuration TGain = 0 TGain = 1 TEMP (°C) RTherm (Ω) RParallel (Ω) xTn (V) TEMP (°C) RTherm (Ω) xTn (V) -40 195652 9514 0.7396 -40 195652 1.7233 0 27219 7313 0.6112 0 27219 0.6078 25 10000 5000 0.4537 25 10000 0.2649 50 4161 2938 0.2887 50 4161 0.1176 80 1669 1430 0.1495 80 1669 0.0486 TEMPO Pin TEMPO Pin 22kΩ 82.5kΩ 22kΩ xT1 Pin xT1 Pin xT2 Pin xT2 Pin 10kΩ 82.5kΩ 10kΩ Thermistors: 10k @ 25°C Murata NCP18XH103F03RB TGAIN = 1 (GAIN = 1) TGAIN = 0 (GAIN = 2) Figure 39. External Temperature Circuits FN8889 Rev.3.00 Oct.14.19 Page 96 of 153 ISL94202 5.6 5. Pin Function ADDR Pin (24) The serial address pin is logically tied to the LSB of the ISL94202 7-bit device “I2C Address” on page 141. If the address pin is tied to “RGO Pin (36)” on page 99, the LSB of the ISL94202 7-bit address is a 1, giving a 7-bit device address of b0101001. If the address pin is tied to digital GND, the LSB of the ISL94202 7-bit address is a 0, giving a 7-bit device address of b0101000. Appending the 8th bit of the address, the read or write bit, provides the address matrix shown in Table 79 on page 141. This pin should not float, either tie it to RGO or digital GND (no resistor is needed). 5.7 SCL Pin (25) The serial clock pin is the I2C clock pin driven by the master for I2C communications. A pull up to RGO of between 4.7kΩ to 10kΩ is recommended. Note: The I2C pins should not be driven externally while the device is in the Powerdown State, this can back-feed into the RGO pin and partially power the device logic into an unknown state. 5.8 SDAI/O Pins (26, 27) The ISL94202 uses a standard I2C interface though it separates the input and output data interfaces onto two pins. Input data is clocked in on SDAI (from MCU to ISL94202), and output data is clocked out on SDAO (from ISL94202 to MCU). These pins should be tied together to form a standard I2C SDA signal. A pull up to RGO of 4.7kΩ to 10kΩ is recommended. Note: The I2C pins should not be driven externally while the device is in the Powerdown State, this can back-feed into the RGO pin and partially power the device logic into an unknown state. 5.9 INT Pin (31) The Interrupt pin is a CMOS type push-pull output that is active low and is used when there is a MCU connected to the ISL94202. This pin is only active if one or more of the MCU override bits are set to 1. The MCU override bits are: • µCFET - “0x87.6 µCFET” on page 82 • µCCBAL - “0x87.5 µCCBAL” on page 83 • µCLMON - “0x87.4 µCLMON” on page 83 • µCCMON - “0x87.3 µCCMON” on page 83 • µCSCAN - “0x87.2 µCSCAN” on page 84 If there is no communication within the watchdog timeout period (see “0x47.[7:3] WDT” on page 65), INT is asserted. If a timeout occurs, all CB outputs and power FETs are turned off (see “CBn Pins” on page 94 and “Power FET Pins (42, 44, 45)” on page 107). The device pulses the INT pin low for 1µs at a rate of 1Hz until the MCU responds. While the MCU does not respond, the part operates normally except no FETs (CB or power) are allowed to turn on. The device remains in this condition until an I2C transaction occurs. When I2C communications resumes, bits µCLMON, µCCMON, µCSCAN, µCFET, and EEEN (“0x89.0 EEEN” on page 85) are cleared. µCCBAL remains set. The system scans resume on the next I2C transaction. The CB outputs and power FETs turn back on, if conditions allow. If the INT pin is unused, it can float as no connections are required. FN8889 Rev.3.00 Oct.14.19 Page 97 of 153 ISL94202 5.10 5. Pin Function PSD Pin (32) The Pack Shutdown pin is an output indicator that the pack has encountered a fatal error. This pin goes active high when any cell voltage reaches the threshold “0x08-09 VCELL OVLO” on page 38. The PSD pin can optionally be configured to operate in two other fail conditions; Cell Fail (“0x4A.7 CELLF PSD” on page 67) and Open-Wire Fail (“0x4A.0 OWPSD” on page 68). The PSD output remains active as long as the fault conditions exist, it is not latched. A momentary fault condition results in a PSD pulse. A continuous fault condition results in a continuous output. This pin is intended to be used with external circuitry to blow a fuse or as an interrupt to a MCU. If the PSD pin is unused, it can float as no connections are required. 5.11 FETSOFF Pin (33) The FETs Off pin is an active high input that allows an external MCU to turn off both the cell balance outputs and the power FETs. This pin should be pulled up to RGO to turn the FETs off. The FETSOFF input is typically used when an external MCU is in control of the system scan and FETs. It provides a second method to quickly shut all FETs off in addition to writing to the FET control registers. The logic circuitry of the FETSOFF input is composed of stacked 5V devices to tolerate a 5V MCU. There is an ESD diode to VRGO that turns on if the pin is pulled high enough above the RGO voltage (Therefore, the Abs Max of RGO + 0.5V). Given the 10k external resistor and a 200Ω internal resistance, if the resistors are pulled up to 5.5V, there is 3V across the resistors and ESD diode. If we assume all of the voltage is across the resistors, the current is 9V. When the voltage at CHMON exceeds the threshold, the current is high enough (>~25µA) for the voltage of D1 and D2 to exceed the threshold of the comparator. The bit CH_PRSNT clears (= 0) if the voltage at CHMON drops below 9V. When the voltage at CHMON is below the threshold, insufficient current flows to fully turn on diodes D1 and D2. This means the voltage at the positive input of the comparator drops below the band-gap voltage reference. 5.15.1.1 Automatic CHMON After detecting a COC condition and “0x87.3 µCCMON” on page 83 is set to 0, the ISL94202 automatically enters recovery and periodically turns on the CHMON recovery circuit. The length of this pulse is set in register “0x01.7:4 CDPW” on page 36. When a charger is not detected (“0x82.1 CH_PRSNT” on page 77 is 0), the device resets the COC bit (“0x81.1 COCF” on page 75) and returns to normal operation. If µCFET bit (“0x87.6 µCFET” on page 82) is 0, the FETs are automatically re-enabled (subject to all other safe operating conditions being met). If µCFET bit is 1, the MCU is responsible for re-enabling the FETs. 5.15.1.2 MCU CHMON After detecting a COC condition and “0x87.3 µCCMON” on page 83 is set to 1, the MCU must perform recovery for the ISL94202 to return to normal operation. The recommended recovery sequence is: 1. Write 1 to CMON_EN (“0x86.4 CMON_EN” on page 81). 2. Wait at least CDPW time (“0x01.7:4 CDPW” on page 36). 3. Read CH_PRSNT (“0x82.1 CH_PRSNT” on page 77). 4. If CH_PRSNT = 1, go back to Step 1. If CH_PRSNT = 0, set CLR_CERR bit (“0x86.5 CLR_CERR” on page 81) to 1 to clear the overcurrent condition fault bit. If µCFET bit (“0x87.6 µCFET” on page 82) is 0, the FETs are automatically re-enabled (subject to all other safe operating conditions being met). If µCFET bit is 1, the MCU is responsible for re-enabling the FETs. FN8889 Rev.3.00 Oct.14.19 Page 101 of 153 ISL94202 5. Pin Function CHMON ISL94202 Trip Requirement: V-CHMON: V > ~9V 210k Otherwise current through D1 & D2 does not produce Vf large enough to trip comparator. CDPW CHMON EN Q1 + VDD 3. 2V D1 CH_PRSNT - V-BG 0.7V + D2 0.7V VSS Figure 43. CHMON Recovery 5.15.2 Charger Detection If the ISL94202 is in the “Powerdown State” on page 120, a charger connection must be used to wake the device up. If in “SLEEP Mode” on page 121, a charger or load connection can be used to wake the device up. When entering SLEEP Mode (via “0x44-45 SLV” on page 64, “0x48.[3:0] IDLE/DOZE Timer” on page 66, or “0x88.2 SLEEP” on page 85), the ISL94202 keeps the wake-up circuit disabled for ~50ms. During this 50ms, the ISL94202 is in SLEEP Mode. After a ~50ms delay, the ISL94202 enables the “Load Detection” on page 105 and charger detection circuits. If a detection is made, the device exits SLEEP to NORMAL Mode. If after the 50ms period there is no load or charger detection, the wakeup circuit stays enabled and the device remains in SLEEP Mode (Figure 46). The circuit does not draw significant current (Figure 44). Note: A load connection to CHMON while in SLEEP Mode also wakes the device. It is important to be aware of the timing and voltage levels. If an application has a particularly large capacitive load with a slow discharge rate, there is a possibility that the voltage seen at the CHMON pin is large enough to prevent SLEEP as the voltage can trigger a false charger detection. Conversely, if the voltage at CHMON drops to ~0V to quickly (~9V (See “0x82.1 CH_PRSNT” on page 77). The load detection voltage is CBMINDV or [CB5ON] CB5 Driver CELL4 Voltage - CELLMIN > CBMINDV or [CB4ON] CB4 Driver CELL3 Voltage - CELLMIN > CBMINDV or [CB3ON] CB3 Driver 4 CELL2 Voltage - CELLMIN > CBMINDV or [CB2ON] CB2 Driver 6 CELL1 Voltage - CELLMIN > CBMINDV or [CB1ON] CB1 Driver CB Off Timer is Counting CBOV Bit CBUV Bit CBERR CBOT Bit CBUT Bit OPEN Bit ENABLE CELLF Bit CASC SD Pin FETSOFF Pin EOC Pin 1 CB_EOC CHING Bit 3 CBDD CBDC Bit DCHING Bit 5 2 7 Figure 62. Cell Balance Operation Table 77. Cell Balance Truth Table CB_EOC Bit EOC Pin CBDC CHING CBDD DCHING Enable 0 x 0 0 0 0 0 1 1 0 0 0 0 0 0 x 0 0 0 1 0 1 1 0 0 0 1 0 0 x 0 0 1 0 0 1 1 0 0 1 0 0 0 x 0 0 1 1 1 1 1 0 0 1 1 1 0 x 0 1 0 0 0 1 1 0 1 0 0 0 0 x 0 1 0 1 0 1 1 0 1 0 1 0 0 x 0 1 1 0 0 1 1 0 1 1 0 0 0 x 0 1 1 1 0 1 1 0 1 1 1 0 0 x 1 0 0 0 0 1 1 1 0 0 0 0 0 x 1 0 0 1 0 1 1 1 0 0 1 0 0 x 1 0 1 0 0 1 1 1 0 1 0 0 FN8889 Rev.3.00 Oct.14.19 Page 125 of 153 ISL94202 6. System Operation Table 77. Cell Balance Truth Table (Continued) CB_EOC Bit EOC Pin CBDC CHING CBDD DCHING Enable 0 x 1 0 1 1 1 1 1 1 0 1 1 1 0 x 1 1 0 0 1 1 1 1 1 0 0 1 0 x 1 1 0 1 0 1 1 1 1 0 1 0 0 x 1 1 1 0 1 1 1 1 1 1 0 1 0 x 1 1 1 1 0 1 1 1 1 1 1 0 1 0 x x x x 1 6.5.2 MCU CB To control the cell balance FETs, the external MCU first needs to set “0x87.5 µCCBAL” on page 83 bit to disable automatic cell balance operation. To turn on the cell balance FETs, the MCU needs to enable each individual cell balance FET output using the cell balance control register (“0x84 CBFC (R/W)” on page 78). In this register, each bit corresponds to a specific cell balance output. With the cell balance outputs selected/enabled, the MCU sets “0x87.0 CBAL_ON” on page 84 to turn on the cell balance output control circuit. To turn the cell balance outputs off, the CBAL_ON bit should be cleared. If the external MCU is performing the system scan, cell voltages should not be measured until the cell balance output FETs are turned off and there has been enough time for the cell voltages to settle. Only then should cell voltages be measured and read for use in determining the next cells to be balanced. 6.6 Open Wire An Open-Wire condition occurs when the series connection between a VCn measurement pin and the cell to be measured is broken. A CELLF condition (see “Cell Fail” on page 129) detection is required to trigger an Open-Wire test. The test is performed on the first scan following the CELLF condition detection and then once every 32 scans while the CELLF condition remains. A CELLF condition is the first indication that an Open-Wire condition may be present. Bit “0x4A.1 DOWD” on page 68 is used to enable or disable the Open-Wire test. The Open-Wire detection mechanism pulls (or pushes) 1mA of current sequentially on each VCn input (“VCn Pins” on page 94) for a period of time specified by register “0x14-15 OWT” on page 43. The pulse is programmable between 1µs and 512ms, the default time is 1ms. During this test, comparators test the voltage at the VCn pin relative to its adjacent cells (VCn-1 & VCn+1). In the absence of a cell and with an external 4.7nF capacitor a 1mA input current changes the voltage at VCn to the open-wire threshold (relative to adjacent cell) within 30µs (signaling a Open-Wire condition). If the cell is present, the voltage change on the VCn input is negligible. Each VCn input has a comparator that detects if the voltage on an input drops more than 0.3V below the voltage of VCn-1 with exceptions to VC0 & VC1. For VC1, the comparator looks to see if the voltage drops 0.4V below VC0. For VC0, the circuit looks to see if the voltage exceeds 1.25V. FN8889 Rev.3.00 Oct.14.19 Page 126 of 153 ISL94202 6. System Operation VCn Cell n Internal 2.5V Supply VC4 VC3 Cell 3 VC2 Control Logic Cell 4 Note: The open-wire test is run only if the device detects the CELLF condition and then once every 32 voltage scans while a CELLF condition exists. Each current source is turned on sequentially. Cell 2 VC1 Cell 1 VC0 Figure 63. Open-Wire Detection FN8889 Rev.3.00 Oct.14.19 Page 127 of 153 ISL94202 6. System Operation Pack VC5 Open Wire Pack Open Wire Cleared Pack Cell Imbalance CELMAX CELMIN CELLF Threshold CBAL FETs Turn Off CELLF Bit 1s (Note 15) No Open-Wire Scans Open-Wire Scan ~160ms (Default) tOW VC8 OW Test ~1ms VC7 OW Test VC6 OW Test VC5 OW Test VC4 OW Test VC3 OW Test VC2 OW Test VC1 OW Test VC6 VC5 VC4 Default = 20ms (Note 12) 1V 32ms (Note 16) VOLTAGE SCAN ~1.7V (Note 13) OPEN BIT Voltage Scan Reports that VC5 = 0V and VC6 = 4.8V Notes: 12. Voltage drop = 1mA * 1kΩ = 1V. 13. Voltage = VF of CB5 Balance FET body diode + (1mA * 1kΩ). 14. OWPSD bit = 0. 15. This time is 8s in IDLE and 16s in DOZE. 16. This 32ms scan rate increases to 256ms in IDLE and 512ms in DOZE. Figure 64. Open-Wire Test Timing With the Open-Wire pulse current setting of 1mA, input resistors of 1kΩ create a voltage drop of 1V. This voltage drop combined with the body diode clamp of the cell balance FET, provides the -1.4V drop to trip an open-wire detection. For this reason and for the increased protection, Renesas recommends not using smaller input series resistors. For example, with a 100Ω input resistor the voltage across the input resistor drops only 0.1V. This would not allow the input open-wire detection hardware to trigger (although the digital detection of an open wire still works, the hardware detection automatically turns off the open-wire current). Input resistors larger than 1kΩ may be desired to increase the input filtering. This is enabled with an increase in the detection time (by changing the OWT value, see “0x14-15 OWT” on page 43.) However, increasing the input resistors affects measurement accuracy. The ISL94202 has up to 2µA variation in the input measurement current. This amounts to about 2mV measurement error with 1k resistors (this error has been factory calibrated out). However, 10kΩ resistors can result in up to 20mV measurement errors. To increase the input filtering, the preferred method is to increase the size of the capacitors. Depending on the selection of the input filter components, the internal open-wire comparators may not detect an open-wire condition. This might happen if the input resistor is small. In this case, the body diode of the cell balance FET may clamp the input before it reaches the open-wire detection threshold. To overcome this limitation and provide a redundant open-wire detection, at the end of the open-wire scan all input voltages are converted to digital values. If any digital value equals 0V (minimum) or 4.8V (maximum), the device sets the OPEN error flag (see “0x81.5 OWF” on page 74) indicating an open-wire failure. When an open-wire condition occurs and the Open-Wire Pack Shutdown bit (“0x4A.0 OWPSD” on page 68) is equal to 0, the ISL94202 turns off all (CB and Power) FETs, but does not set the PSD output. While in this FN8889 Rev.3.00 Oct.14.19 Page 128 of 153 ISL94202 6. System Operation condition, the device continues to operate normally in all other ways (for example, the cells are scanned and the current monitored. As time passes, the device drops into lower power Modes). When an open-wire condition occurs and OWPSD bit is equal to 1, the Open Wire Fault (“0x81.5 OWF” on page 74) is set, the ISL94202 turns off all (CB and Power) FETs, and asserts the “PSD Pin (32)” on page 98. The device can automatically recover from an open-wire condition because the open-wire test is still functional, unless the OWPSD bit equals 1 and the PSD pin blows a fuse in the pack. If the open-wire test finds that the open wire has been cleared, then Open-Wire Fault is reset to 0 and other tests determine whether conditions allow the power FETs to turn back on. The open-wire test hardware has two limitations. First, it depends on the CELLF indicator (“0x81.4 CELLF” on page 74). If the Cell Balance Maximum Voltage Delta (“0x22-23 CBMAXDV” on page 51) value is set too high (FFFh for example), the device may never detect a CELLF condition. The second limitation is that the open-wire test does not happen immediately. A scan must detect a CELLF condition, then the open-wire test occurs on the next scan, 32ms (NORMAL Mode) to 512ms (DOZE Mode) later. 6.7 Cell Fail The Cell Fail (“0x81.4 CELLF” on page 74) condition indicates that the difference between the highest voltage cell and the lowest voltage cell exceeds a programmed threshold (“0x22-23 CBMAXDV” on page 51). When detected, the CELLF condition turns off the cell balance and power FETs, but only if “0x87.6 µCFET” on page 82 = 0. Setting µCFET = 1 prevents the power FETs from turning off during a CELLF condition. The MCU is then responsible for the power FET control. Setting control bit “0x4A.7 CELLF PSD” on page 67 to 1 enables the PSD activation when the ISL94202 detects a Cell Fail condition. When “0x81.4 CELLF” on page 74 = 1 and CELLF_PSD = 1, the power FETs and cell balance FETs turn off, and the PSD output (“PSD Pin (32)” on page 98) goes active. You can use the PSD pin output through additional circuitry to deactivate the pack by blowing a fuse. The PSD pin alone is not capable of blowing a fuse. The CELLF function can be disabled by setting the CBMAXDV value to 0xFFF. In this case, the voltage differential can never exceed the limit. However, disabling the cell fail condition also disables the open-wire detection (see “Open Wire” on page 126). 6.8 OV Detection/Response The device needs to monitor the voltage on each battery cell (“VCn Pins” on page 94). If the voltage of any cell exceeds the cell overvoltage threshold (“VCELL OV” on page 35) for a time exceeding cell overvoltage timer (“0x10-11 VCELL OV Timer” on page 41), the device sets the Overvoltage Fault bit (“0x80.0 OVF” on page 73). Then, if “0x87.6 µCFET” on page 82 = 0, the ISL94202 turns the charge FET OFF by setting “0x86.1 CFET” on page 81 to 0. When the OV fault is set, the pack has entered Overcharge Protection Mode. The status of the discharge FET remains unaffected. The charge FET remains off until the voltage on the overcharged cell drops below “0x02-03 VCELL OVR” on page 36 for the time period set by “0x10-11 VCELL OV Timer” on page 41. Note: The time taken to recover is equal to the time taken to enter the condition because the same timer setting is used. The detection timer and recovery timer are asynchronous to the voltage threshold. As a result, a setting of 1s can result in a delay time of 1s to 2s, depending on when the OV/OVR is detected. The device further continues to monitor the battery cell voltages and is released from Overcharge Protection Mode when [VCn - VC(n-1)]< VOVR for more than the overcharge delay time, for all cells. When the device is released from Overcharge Protection Mode, the charge FET is automatically switched on (if µCFET = 0). When the device returns from Overcharge Protection Mode, the status of the discharge FET remains unaffected. There is also an overvoltage lockout (“0x08-09 VCELL OVLO” on page 38). When this level is reached, an OVLO bit (“0x80.1 OVLOF” on page 73) is set, the PSD output is asserted, and the charge FET or precharge FET is FN8889 Rev.3.00 Oct.14.19 Page 129 of 153 ISL94202 6. System Operation immediately turned off. You can use the PSD pin output through additional circuitry to deactivate the pack by blowing a fuse. The PSD pin alone is not capable of blowing a fuse. If the µCFET bit is 1 during an OV condition, the MCU must control both turn off and turn on of the charge and precharge power FETs. This does not apply to the OVLO condition. If there is discharge current flowing out of the pack, the device includes an option to turn the charge FET back on in an overvoltage condition. This option is set by bit “0x4B.4 CFODOV” on page 69 (CFET ON During Overvoltage). Then, if the discharge current stops and there is still an overcharge condition on the cell, the device again disables the charge FET. Normal Operation Mode Normal Operation Mode Overcharge Protection Mode Overvoltage Lock-out Protection Mode VOVLO VEOC tOV VOV VOVR VCn tOVR Pack CFLG Reset Charge Current Discharge DFLG SET DFET DFLG Reset CFODOV Flag = 1 Allows CFET to Turn on During OV, if Discharging CFET EOC Pin VEOC Bit OV Bit SD Pin PSD Pin OVLO Bit Figure 65. OV Detection/Response 6.8.1 VEOC During charge, if the voltage on any cell exceeds an Voltage End-Of-Charge threshold (“0x0C-0D VCELL EOC” on page 40), the VEOC bit (“0x81.7 VEOC” on page 73) is set and the EOC output (“EOC Pin (35)” on page 99) is pulled low. The VEOC bit and the EOC output resume normal conditions when the voltage on all cells drops back below the [VCELL EOC - 117mV] threshold. VEOC detection does not shut off the CFET, disabling CFET at the end of charge is controlled by the threshold “VCELL OV” on page 35. 6.9 UV Detection & Response If the voltage of any cell falls below the cell undervoltage threshold (“VCELL UV” on page 37) for a time exceeding cell overvoltage timer (“0x12-13 VCELL UV Timer” on page 42), the device sets the Undervoltage Fault bit (“0x80.2 UVF” on page 72). Then, if “0x87.6 µCFET” on page 82 = 0, the ISL94202 turns the discharge FET OFF by setting “0x86.0 DFET” on page 82 to 0. When the UV fault is set, the pack has entered Undercharge Protection mode. The status of the charge FET remains unaffected. FN8889 Rev.3.00 Oct.14.19 Page 130 of 153 ISL94202 6. System Operation While any cell voltage is less than a low voltage charge threshold (“0x0E-0F VCELL LVCL” on page 40) and if the PCFETE bit (“0x4A.2 PCFETE” on page 68) is set, the PCFET output is turned on instead of the CFET output during charging. This enables a precharge condition to limit the charge current to undervoltage cells. From the undervoltage condition, if the cells recover to above “0x06-07 VCELL UVR” on page 38 for a time exceeding “0x12-13 VCELL UV Timer” on page 42 plus three seconds, the ISL94202 pulses the LDMON output once every 256ms and looks for the absence of a load (see “LDMON Pin (38)” on page 104). The pulses are of programmable duration (0ms to 15ms) using the [LPW3:LPW0] bits. During the pulse period, a small current (~60µA) is output into the load. If there is no load, the LDMON voltage is higher than the recovery threshold of 0.6V. When the load has been removed and the cells are above the undervoltage recovery level, the ISL94202 clears the UV bit and, if µCFET = 0, turns on the discharge FET and resumes normal operation. VC VUVR VUV VLVCH VSL tUV +3s VUVLO tUV If Charge Voltage Connected IPACK tUV +3s tUV tSL Charge Discharge DISCHARGE Sampling for Load Release (µCLMON Pulses) LMON_EN Bit (Looking for Tool Trigger Release) (From µC) Microcontroller Only (µCLMON Bit = 1) Load Released LDMON Pin VLDMON (Starts Looking for Charger/Load Connect) CMON_EN Bit VWKUPC Wake Up Charge Connect CHMON Pin VWKUPL LD_PRSNT Bit DFET Remains Set if UVLOPD = 0 and µCFET = 1 DFET On if Charging and DFODUV Bit is Set DFET Bit DFET On if Charging and DFODUV Bit is Set CFET Bit If PCFETE Set, PCFET Turns On Here, Not CFT PCFET Bit IN_SLP Bit UVLO Bit UV Bit (µCFET = 0) Overdischarge Overdischarge Protection Mode Protection Mode Sleep UVLO Set if UVLOPD = 0 If UVLOPD = 1 and µCFET = 0 or 1, Device Powers Down UV Bit (µCFET = 1) Reset When Microcontroller Writes CLR_LERR Bit = 1 Figure 66. UV detection/response The VCELL UV detection and recovery timer is asynchronous to the voltage threshold. As a result, a setting of 1s can result in a delay time of 1s to 2s (and a recovery time of 3s to 4s), depending on when the UV/UVR is detected. If any of the cells drop below a sleep threshold (“0x44-45 SLV” on page 64) for a period of time (“0x47.[2:1] SLTU” on page 65), the ISL94202 turns off both FETs (DFET and CFET = 0) and puts the pack into SLEEP Mode by FN8889 Rev.3.00 Oct.14.19 Page 131 of 153 ISL94202 6. System Operation setting the Sleep bit (“0x83.6 IN_SLEEP” on page 78) to 1. If the µCFET bit is set, the device does not go to sleep. There is also an undervoltage lockout condition. This is detected by comparing the cell voltages to a programmable UVLO threshold (“0x0A-0B VCELL UVLO” on page 39). When any cell voltage drops below the UVLO threshold and remains below the threshold for five voltage scan periods (~160ms), the UVLO bit (“0x80.3 UVLOF” on page 72) is set and the SD output pin goes active. If UVLOPD = 0 and µCFET = 0, the DFET is also turned off. If UVLOPD = 1 (“0x4B.3 UVLOPD” on page 70), the ISL94202 goes into a “Powerdown State” on page 120. If the µCFET bit is set to 1, the MCU must both turn off and turn on the discharge power FETs and control the sleep and power-down conditions. The device includes an option to turn the discharge FET back on in an undervoltage condition, if there is a charge current flowing into the pack (“0x82.2 CHING” on page 77). This option is set by the “0x4B.5 DFODUV” on page 69 (DFET ON During Undervoltage) control bit. Then, if the charge current stops and there is still an undervoltage condition on the cell, the device again disables the discharge FET. 6.10 Current Monitoring/Response The current monitor is an analog detection circuit that tracks the charge current, discharge current, and current direction. The current monitor circuit is on all the time, except in SLEEP and Power-Down Modes (“System Modes” on page 119). The power FETs are off in these two states. The current monitor compares the voltage across the sense resistor to several different thresholds. These are discharge short-circuit (“0x1A-1B DSC & DSCT” on page 48), discharge overcurrent (“0x16-17 DOC & DOCT” on page 43), and charge overcurrent (“0x18-19 COC & COCT” on page 46). If the measured voltage exceeds the specified limit for a specified duration of time, the ISL94202 acts to protect the system. The current monitor also tracks the direction of the current. This is a low-level detection and indicates the presence of a charge or discharge current. If either condition is detected, the ISL94202 sets an appropriate flag (“0x82.2 CHING” on page 77 and “0x82.3 DCHING” on page 76). The current-sense element is on the high-side of the battery pack. The current-sense circuit has a gain x5, x50, or x500. The sense amplifier allows a very wide range of currents to be monitored. The gain settings allow a sense resistor in the range of 0.3mΩ to 5mΩ. A diagram of the current-sense circuit is shown in Figure 67 on page 133. There are two parts of the current-sense circuit. The first part is a digital current monitor circuit. This circuit allows the current to be tracked by an external MCU or computer. The current-sense amplifier gain in this current measurement is set by “0x85.[5:4] CG” on page 79. The 14-bit offset adjusted ADC result of the conversion of the voltage across the current-sense resistor is saved to register “0xAA-AB - ADCV” on page 93, as well as a 12-bit value (“0x8E-8F IPACK” on page 90) that is used for threshold comparisons. The offset adjustment is based on a factory calibration value saved in EEPROM. The digital readouts cover the input voltage ranges shown in Table 78. Table 78. Maximum Current Measurement Range Gain Setting Voltage Range (mV) Current Range (RSENSE = 1mΩ) 5x -250 to 250 -250A to 250A 50x -25 to 25 -25A to 25A 500x -2.5 to 2.5 -2.5A to 2.5A FN8889 Rev.3.00 Oct.14.19 Page 132 of 153 ISL94202 6. System Operation RSENSE CS1 CS2 500Ω 5kΩ 50kΩ + - AO2:0 = 9H Voltage Scan Charge Overcurrent Detect 250kΩ 250kΩ Note: AGC sets gain during overcurrent monitoring. CG bits select gain when ADC measures current. Programmable Detection Time COC [OCCTB:OCC0] GAIN SELECT Programmable Thresholds [OCC2:OCC0] CG1:0 14-Bit ADC Output 14-Bit Value Discharge Overcurrent Detect AGC Register 14-BIT ADC + Address: [8Fh:8Eh] 12 MUX Pack Current Register DOC [OCDTB:OCDT0] Address: [ABh:AAh] 12-Bit Value Programmable Detection Time + - POLARITY CONTROL Discharge Short-Circuit Detect 4 Digital CAL EEPROM CHING AO3:AO0 Voltage Select Bits Programmable Thresholds DCHING Current Direction Detect + 2ms Filter [OCD2:OCD0] Programmable Detection Time DSC [SCTB:SCT0] Programmable Thresholds [DSC2:DSC0] Figure 67. Current sense block diagram The second part is the analog current direction, overcurrent, and short-circuit detect mechanisms. This circuit is on all the time. During the operation of the overcurrent detection circuit, the sense amplifier gain is automatically controlled. For current direction detection, there is a 2ms digital delay for getting into or out of either direction condition, which means that the charge current detection circuit needs to detect an uninterrupted flow of current out of the pack for more than 2ms to indicate a discharge condition. Then, the current detector needs to identify that there is a charge current or no current for a continuous 2ms to remove the discharge condition. The overcurrent and short-circuit detection thresholds are programmable values stored in the EEPROM. The charge and discharge overcurrent conditions and the discharge short-circuit condition need to be continuous for a period of time before an overcurrent condition is detected. For more information on the relevant settings, review the following sections: • Discharge Overcurrent - “0x16-17 DOC & DOCT” on page 43 & “DOCR” on page 45. • Charge Overcurrent - “0x18-19 COC & COCT” on page 46 & “COCR” on page 47. • Discharge Short Circuit - “0x1A-1B DSC & DSCT” on page 48 & “DSCR” on page 49. • Current Direction - “0x82.2 CHING” on page 77 & “0x82.3 DCHING” on page 76. 6.10.1 Overcurrent and Short-Circuit Detection The ISL94202 continually monitors current by mirroring the current across a current-sense resistor (between the CS1 and CS2 pins) to a resistor to ground. • A discharge overcurrent condition exists when the voltage across the external sense resistor exceeds the discharge overcurrent threshold (set by the discharge overcurrent threshold bits) for an overcurrent time delay, set by the discharge overcurrent timeout bits (“0x16-17 DOC & DOCT” on page 43). This condition sets the fault FN8889 Rev.3.00 Oct.14.19 Page 133 of 153 ISL94202 6. System Operation bit “0x81.2 DOCF” on page 74 high. The bit “0x82.0 LD_PRSNT” on page 77 is also set high at this time. If the µCFET bit is 0, the power FETs turn off automatically. If the µCFET bit is 1, the external MCU must control the power FETs (“0x87.6 µCFET” on page 82). • A charge overcurrent condition exists when the voltage across the external sense resistor exceeds the charge overcurrent threshold (set by the charge overcurrent threshold bits) for an overcurrent time delay, set by the discharge overcurrent timeout bits (“0x18-19 COC & COCT” on page 46). This condition sets the fault bit “0x81.1 COCF” on page 75 high. The bit “0x82.1 CH_PRSNT” on page 77 is also set high at this time. If the µCFET bit is 0, the power FETs turn off automatically. If the µCFET bit is 1, the external MCU must control the power FETs. • A discharge short-circuit condition exists when the voltage across the external sense resistor exceeds the discharge short-circuit threshold (set by the discharge short-circuit threshold bits) for an overcurrent time delay, set by the discharge short-circuit timeout bits (“0x1A-1B DSC & DSCT” on page 48). This condition sets the fault bit “0x81.3 DSCF” on page 74 high. The bit “0x82.0 LD_PRSNT” on page 77 is also set high at this time. The power FETs turn off automatically in a shortcircuit condition, regardless of the condition of the µCFET bit. 6.10.1.1 DOC and DSC Response When the ISL94202 enters the discharge overcurrent protection or short-circuit protection mode, the ISL94202 begins a load monitor state. In the load monitor state, the ISL94202 waits three seconds and then periodically checks the load by turning on the “LDMON Pin (38)” on page 104 output for 0 to 15ms every 256ms. Program the pulse duration with the bits “0x05.7:4 LDPW” on page 37. When turned on, the recovery circuit outputs a small current (~60µA) to flow from the device and into the load. With a load present, the voltage on the LDMON pin is low and the LD_PRSNT bit remains set to 1. When the load rises to a sufficiently high resistance, the voltage on the LDMON pin rises above the LDMON threshold and the LD_PRSNT bit is reset. When the load has been released for a sufficiently long period of time (two successive load sample periods), the ISL94202 recognizes that the conditions are OK and resets the bit “0x81.2 DOCF” on page 74 or bit “0x81.3 DSCF” on page 74. If the µCFET bit is 0, the device automatically re-enables the power FETs by setting the DFET and CFET (or PCFET) bits to 1 (assuming all other conditions are within normal ranges). If the µCFET bit is 1, the MCU must turn on the power FETs. An external MCU can override the automatic load monitoring of the device. It does this by taking control of the load monitor circuit (set the bit “0x87.4 µCLMON” on page 83 = 1) and periodically pulsing the bit “0x86.6 LMON_EN” on page 80. When the MCU detects that LD_PRSNT = 0, it sets the bit “0x86.7 CLR_LERR” on page 80 to 1 (to clear the error condition and reset the DOC or DSC bit) and sets the DFET and CFET (or PCFET) bits to 1 to turn on the power FETs. 6.10.1.2 COC Response When the ISL94202 enters the Charge Overcurrent Protection mode, the ISL94202 begins a charger monitor state. In the charger monitor state, the ISL94202 periodically checks the charger connection by turning on the “CHMON Pin (37)” on page 99 output for 0ms to 15ms every 256ms. Program the pulse duration with the bits “0x01.7:4 CDPW” on page 36. When turned on, the recovery circuit checks the voltage on the CHMON pin. With a charger present, the voltage on the CHMON pin is high (>9V) and the CH_PRSNT bit remains set to 1. When the charger connection is removed, the voltage on the CHMON pin falls below the CHMON threshold and the CH_PRSNT bit is reset. When the charger has been released for a sufficiently long period of time (two successive sample periods), the ISL94202 recognizes that the conditions are OK and clears the bit “0x81.1 COCF” on page 75. If the µCFET bit is 0, the device automatically re-enables the power FETs by setting the DFET and CFET (or PCFET) bits to 1 (assuming all other conditions are within normal ranges). If the µCFET bit is 1, the MCU must turn on the power FETs. An external MCU can override the automatic charger monitoring of the device. It does this by taking control of the load monitor circuit (set the bit “0x87.3 µCCMON” on page 83 = 1) and periodically pulsing the bit “0x86.4 CMON_EN” on page 81. When the MCU detects that CH_PRSNT = 0, it sets the bit “0x86.5 CLR_CERR” on FN8889 Rev.3.00 Oct.14.19 Page 134 of 153 ISL94202 6. System Operation page 81 to 1 (to clear the error condition and reset the COC bit) and sets the DFET and CFET (or PCFET) bits to 1 to turn on the power FETs. Normal Operation Mode Overcurrent Protection Mode Normal Operation Mode Sense Current IOCC tOCCT VCHMON Charger Removed Charger Still Connected When µCFET = 0 Sample Rate Set by ISL94202 CHMON Pin When µCFET = 1 and µCCMON = 1 Sample Rate Set by Microcontroller CMON_EN (From µC) COC Bit (µCFET = 0) (Note 18) (Note 17) COC Bit (µCFET = 1) CFET Notes: 17. When µCFET = 1, COC bit is reset when the CLR_CERR is set to 1. 18. When µCFET = 0, COC is reset by the ISL94202 when the condition is released. Figure 68. COC Protection Mode 6.11 Temperature Monitoring/Response As part of the normal voltage scan, the ISL94202 monitors both the temperature of the device (“0xA0-A1 ITEMP” on page 91) and the temperature of two external temperature sensors (see “Thermistor Pins (20-22)” on page 96). External Temperature 2 can be used to monitor the temperature of the FETs, instead of the cells, by setting the bit “0x4A.5 XT2M” on page 68 to 1. The temperature voltages have two selectable gain settings (“0x4A.4 TGAIN” on page 68) applied to both pins. Setting the TGain bit = 0 (default) sets the gain to 2x, providing for a full scale input voltage = 0.9V. The device is calibrated at the default temperature gain setting of 2x, this is the preferred setting because it produces a more linear temperature response. The temperature management state machine is detailed in Figure 69 on page 137. 6.11.1 Charging Temperature There are four relevant temperature thresholds in effect when the ISL94202 detects a charge current (“0x82.2 CHING” on page 77). These thresholds consist of two out of bounds levels and their complementary recovery levels. • When the external temperature on xT1 or xT2 exceeds threshold Charge Over-Temperature (“0x30-31 COT” on page 56), fault bit “0x80.6 COTF” on page 71 is set to 1 and the CFET (“CFET Pin (45)” on page 108) is turned off. If “0x87.6 µCFET” on page 82 = 1, an external MCU must turn off the CFET. • When the external temperature on xT1 and xT2 falls back below threshold Charge Over-Temperature Recovery (“0x32-33 COTR” on page 57) following a COTF condition previously detected, the fault bit COTF clears and the CFET is turned on (if all other safe operating conditions are met). If µCFET = 1, an external MCU must turn on the CFET. FN8889 Rev.3.00 Oct.14.19 Page 135 of 153 ISL94202 6. System Operation • When the external temperature on xT1 or xT2 falls below threshold Charge Under-Temperature (“0x34-35 CUT” on page 58), fault bit “0x80.7 CUTF” on page 71 is set to 1 and the CFET is turned off. If µCFET = 1, an external MCU must turn off the CFET. • When the external temperature on xT1 and xT2 rises back above threshold Charge Under-Temperature Recovery (“0x36-37 CUTR” on page 58) following a CUTF condition previously detected, the fault bit CUTF clears and the CFET is turned on (if all other safe operating conditions are met). If µCFET = 1, an external MCU must turn on the CFET. If “0x4A.2 PCFETE” on page 68 = 1, PCFET (“PCFET Pin (44)” on page 108) follows the state of the CFET pin. 6.11.2 Discharging Temperature There are four relevant temperature thresholds in effect when the ISL94202 detects a discharge current (“0x82.3 DCHING” on page 76). These thresholds consist of two out of bounds levels and their complementary recovery levels. • When the external temperature on xT1 or xT2 exceeds threshold Discharge Over-Temperature (“0x38-39 DOT” on page 59), fault bit “0x80.4 DOTF” on page 72 is set to 1 and the DFET (“DFET Pin (42)” on page 108) is turned off. If “0x87.6 µCFET” on page 82 = 1, an external MCU must turn off the DFET. • When the external temperature on xT1 and xT2 falls back below threshold Discharge Over-Temperature Recovery (“0x3A-3B DOTR” on page 60) following a DOTF condition previously detected, the fault bit DOTF clears and the DFET is turned on (if all other safe operating conditions are met). If µCFET = 1, an external MCU must turn on the DFET. • When the external temperature on xT1 or xT2 falls below threshold Discharge Under-Temperature (“0x3C-3D DUT” on page 61), fault bit “0x80.5 DUTF” on page 72 is set to 1 and the DFET is turned off. If µCFET = 1, an external MCU must turn off the DFET. • When the external temperature on xT1 and xT2 rises back above threshold Discharge Under-Temperature Recovery (“0x3E-3F DUTR” on page 61) following a DUTF condition previously detected, the fault bit DUTF clears and the DFET is turned on (if all other safe operating conditions are met). If µCFET = 1, an external MCU must turn on the DFET. 6.11.3 Internal Temperature There are two internal temperature thresholds independent of current direction. These thresholds consist of an out of bounds level and its complementary recovery level. • Internal over-temperature (“0x40-41 IOT” on page 62) - When the internal temperature exceeds this threshold, bit “0x81.0 IOTF” on page 75 is set to 1 and all power FETs are turned off regardless of the state of “0x87.6 µCFET” on page 82. • Internal over-temperature recovery (“0x42-43 IOTR” on page 63) - When the internal temperature falls below this threshold, bit “0x81.0 IOTF” on page 75 is automatically cleared to 0 and all power FETs are allowed to turn back on. If “0x87.6 µCFET” on page 82 = 1, an external MCU must turn on any FETs. FN8889 Rev.3.00 Oct.14.19 Page 136 of 153 6.12 FN8889 Rev.3.00 Oct.14.19 Charge Shutdown Turn Off CFET µCFET = 0 Discharge Shutdown Turn Off DFET µCFET = 0 µCFET = 1 XT2M = 1 XT2M = 1 Balance Shutdown Turn Off Balancing µCFET = 0 Cell Balance Under-Temp Set CBUT Bit = 1 XT2M = 0 xT2CBOTR xT2 OTR XT2M = 0 Cell Balance Over-Temp OK Set CBOT Bit = 0 Balance Permitted SAMPLE MODE XT2M = 1 xT2 UT xT2>CBUTS xT1>CBUTS XT2M = 0 xT2 OT xT2DUTS xT2CUTS xT2