DATASHEET
ISL94208
FN8306
Rev.2.00
May 1, 2017
4- to 6-Cell Li-ion Battery Management Analog Front-End
The ISL94208 battery management IC is designed for use with a
microcontroller and features an analog front-end with
overcurrent protection for multi-cell Li-ion battery packs. The
ISL94208 supports battery packs consisting of four to six cells in
series and one or more cells in parallel.
Features
• Software selectable overcurrent protection levels and variable
protect detection times
-
Using an internal analog multiplexer, the ISL94208 allows a
separate microcontroller with an A/D converter to monitor each
cell voltage plus internal and external temperature.
The ISL94208 provides integral overcurrent and short-circuit
protection circuitry, an internal 3.3V voltage regulator, internal
cell balancing switches, and drive circuitry for external FET
devices for control of pack charge and discharge.
Related Literature
4 discharge overcurrent thresholds
4 short-circuit thresholds
4 charge overcurrent thresholds
8 overcurrent delay times (charge)
8 overcurrent delay times (discharge)
2 short-circuit delay times (discharge)
• Automatic FET turn-off and cell balance disable on reaching
external (battery) or internal (IC) temperature limit
• Automatic cell balance turn off on IC over-temperature
• For a full list of related documents, visit our website
- ISL94208 product page
• Integrated charge/discharge FET drive circuitry
• Internal cell balancing FETs handle up to 200mA of balancing
current for each cell
• Sleep operation with negative or positive edge wake-up
• threshold.
WKPOL bit = ‘0’, the device wakes up on the falling edge of the WKUP pin. The WKUP bit is HIGH only when the
WKUP pin voltage < threshold.
29
SDA
Serial Data. This is the bidirectional data line for an I2C interface. This pin should be pulled up to 3.3V using a
resistor.
30
SCL
Serial Clock. This is the clock input for an I2C communication link. This pin should be pulled up to 3.3V using a
resistor.
-
PAD
Thermal Pad. Connect to VSS.
Block Diagram
TEMPI TEMP3V
VCELL6
TEMPERATURE
SENSOR
CIRCUITS
VCELL3
VCELL2
CELL
LEVEL
VOLTAGES
SHIFTERS
VSS
6
VCELL0
CB6
CB4
CB3
CB2
CIRCUITS
AO
I2C, CONTROL
LOGIC, REGISTERS,
OSCILLATOR
CELL
BALANCE
RGC
RGO
2
VCELL1
CB5
VCC
OVERCURRENT
CIRCUITS
FET CONTROL
CIRCUITRY
CB1
CFET
DFET
VFET2
VFET1
VMON
CSENSE
ISREF
DSENSE
BACKUP
SUPPLY
POWER
CONTROL
SCL
SDA
WKUP
VBACK
VCELL4
3.3VDC
REGULATOR
MUX
VCELL5
FIGURE 2. BLOCK DIAGRAM
FN8306 Rev.2.00
May 1, 2017
Page 5 of 36
ISL94208
Absolute Maximum Ratings
Thermal Information
(Note 4)
Power Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 36.0V
Cell Voltage, VCELL
VCELLn (n = 5, 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 27.0V
VCELLn (n = 3, 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 18.0V
VCELLn (n = 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 9.0V
VCELLn - VCELLn-1 (n = 1, 2, 3, 4, 5, 6) . . . . . . . . . . . . . . . . . . -0.5V to 5V
VCELL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 5V
VCELL0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 0.5V
Cell Balance, CB
CB6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 36V
CB6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V
CB4, CB5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 27V
CB4, CB5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V
CB2, CB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 18.0V
CB1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
CBn -VCn-1 (n = 1, 2, 3, 4, 5, 6) . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
FET Control
VFET2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to 18V
VFET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to 13V
VFET2-VFET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5V
CFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -18.0V to 18V
CFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-18.0V to VVFET2 + 0.5V
DFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 18V
DFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VVFET2 + 0.5V
Terminal Voltage,
SCL, SDA, CSENSE, DSENSE, TEMPI, RGO, AO, TEMP3V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 to VRGO + 0.5V
ISREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .- 0.5V to VSS + 0.5
VBACK, RGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 to 5V
VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5V to 36V
VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5V to VCC + 0.5V
WKUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .- 0.5V to 27V
WKUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5V to VCC + 0.5V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 250V
Capacitive Discharge Model (Tested per JESD22-C101D). . . . . . . .1.5kV
Latch-Up (Tested per JESD-78D; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
32 Ld QFN (Notes 5, 6) . . . . . . . . . . . . . . . .
30
1.7
Continuous Package Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . .400mW
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions (Note 4)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Voltage:
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 26.4V
SCL, SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3.6V
VBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCELL1 or 2.0V to 4.6V
VCELL1 - VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 4.3V
VCELLn - VCELLn-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 4.3V
VFET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 to 8.6
VFET2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 to 12.9
VFET2 - VFET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V to 4.5V
ISREF - VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1V to 0.1V
(CSENSE - ISREF), (DSENSE - ISREF) . . . . . . . . . . . . . . . . . . . . -0.5V to 1.5V
DFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VFET2
CFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VFET2
WKUP (WKPOL=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VBACK
WKUP (WKPOL=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 27V
VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VCC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. All Absolute Maximum Ratings and Recommended Operating Conditions referenced to VSS, unless otherwise noted.
5. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. JC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
VCC = 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +85°C.
PARAMETER
Power-Up Condition 1
Power-Up Condition 2 Threshold
(Rising)
SYMBOL
VPORVCC
VPOR
TEST CONDITION
MIN
(Note 7)
VCC voltage (Note 8)
VBACK - VSS (rising) (Note 8)
0°C to +60°C
TYP
MAX
(Note 7)
UNIT
4
6.5
V
1.6
2.05
V
1.55
1.95
V
Power-Up Condition 2 Threshold
Hysteresis
VHYS
VBACK - VSS (falling) (Note 8)
0.02
0.1
0.30
V
3.3V Regulated Voltage
VRGO
0µA < IRGC < 350µA
3.0
3.3
3.6
V
FN8306 Rev.2.00
May 1, 2017
Page 6 of 36
ISL94208
Electrical Specifications
VCC = 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
(Note 7)
TYP
0.35
0.50
MAX
(Note 7)
UNIT
3.3VDC Voltage Regulator Control
Current Limit
IRGC
(Control current at output of RGC.
Recommend NPN with gain of 70+)
mA
VCC Supply Current
IVCC1
Power-up defaults, WKUP pin = 0V
300
510
µA
IVCC2
LDMONEN bit = 1, VMON floating,
CFET = 1, DFET=1, WKPOL bit = 1,
VWKUP = 10V, [AO3:AO0] bits = 03H
400
700
µA
IVCC3
Default register settings, except
SLEEP bit = 1. WKUP pin = VCELL1
1
10
µA
0.1
1.5
µA
VFET1 Supply Current
(Normal or Sleep Mode)
IVFET1
VFET2 Supply Current
(Normal or Sleep Mode)
IVFET3
DFET, CFET outputs floating
0.1
1
µA
RGO Supply Current
IRGO1
Power-up defaults, WKUP pin = 0V
300
410
µA
IRGO2
LDMONEN bit = 1, VMON floating,
CFET = 1, DFET=1, WKPOL bit = 1,
VWKUP = 10V, [AO3:AO0] bits = 03H
450
650
µA
IRGO3
Default register settings, except
SLEEP bit = 1. WKUP pin = VCELL1
0.4
1
µA
7
12
µA
VBACK Input Current
(Falling edge wake-up; WKPOL = 0)
(Normal or Sleep Mode)
VBACK Input Current
(Rising edge wake-up; WKPOL = 1)
(Normal Mode)
(Sleep Mode)
VCELL Input Current (Monitoring)
VCELL Input Current Differential
(Monitoring)
VCELL Input Current (Non-Monitoring)
FN8306 Rev.2.00
May 1, 2017
IVBACK01
WKUP ≤ VWKUP2(max)
IVBACK02
VWKUP2(max) < WKUP < 5V
0.5
3
µA
IVBACK11
WKUP < VWKUP1(min) or;
WKUP > VWKUP1(max)
0.5
3
µA
IVBACK12
VWKUP1(min) ≤ WKUP ≤ VWKUP1(max)
120
300
µA
IVBACK13
WKUP ≥ VWKUP1(min)
180
500
µA
IVBACK14
WKUP < VWKUP1(min)
0.5
3
µA
IVCELLA
Sinking current at:
VCELL6 (measure VCELL6 or VCELL5) and
VCELL5 (measure VCELL6 or VCELL5) and
VCELL4 (measure VCELL5)
40
65
µA
IVCELLB
Sinking current at:
VCELL4 (measure VCELL4) and
VCELL3 (measure VCELL4 or VCELL3) and
VCELL2 (measure VCELL3)
30
50
µA
IVCELLC
Sourcing current at:
VCELL2 (measure VCELL2) and
VCELL1 (measure VCELL2)
-40
-20
µA
IVCELLD
Sourcing current at:
VCELL1 (measure VCELL1) and
VCELL0 (measure VCELL1)
-38
-18
µA
IVCELLDIFF Difference in monitoring current between
VCELLn and VCELL(n-1); n = 1, 2, 3, 4
-2
2
µA
Difference in monitoring current between
VCELLn and VCELL(n-1); n = 5, 6
-4
4
µA
VCELLn and VCELL(n-1)
(n = 1, 2, 3, 4, 5, or 6)
n is a non-selected cell
-1
1
µA
IVCELLN
±0.1
Page 7 of 36
ISL94208
Electrical Specifications
VCC = 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
VOCD = 0.10V (OCDV1, OCDV0 = 0, 0)
0.08
0.10
0.12
V
VOCD = 0.12V (OCDV1, OCDV0 = 0, 1)
0.10
0.12
0.14
V
VOCD = 0.14V (OCDV1, OCDV0 = 1, 0)
0.12
0.14
0.16
V
SYMBOL
TEST CONDITION
OVERCURRENT/SHORT-CIRCUIT PROTECTION SPECIFICATIONS
Discharge Overcurrent Detection
Threshold
Sense Voltage Relative To ISREF
(Default Highlighted)
VOCD
Charge Overcurrent Detection
Threshold
Sense Voltage Relative to ISREF
(Default Highlighted)
VOCC
Short Current Detection Threshold
Voltage Relative to ISREF
(Default Highlighted)
VSC
VOCD = 0.16V (OCDV1, OCDV0 = 1, 1)
0.14
0.16
0.18
V
VOCC = 0.10V (OCCV1, OCCV0 = 0, 0)
-0.12
-0.10
-0.07
V
VOCC = 0.12V (OCCV1, OCCV0 = 0, 1)
-0.14
-0.12
-0.09
V
VOCC = 0.14V (OCCV1, OCCV0 = 1, 0)
-0.16
-0.14
-0.11
V
VOCC = 0.16V (OCCV1, OCCV0 = 1, 1)
-0.18
-0.16
-0.13
V
VSC = 0.20V (SCDV1, SCDV0 = 0, 0)
0.15
0.20
0.25
V
VSC = 0.35V (SCDV1, SCDV0 = 0, 1)
0.30
0.35
0.40
V
VSC = 0.65V (SCDV1, SCDV0 = 1, 0)
0.60
0.65
0.70
V
VSC = 1.20V (SCDV1, SCDV0 = 1, 1)
1.10
1.20
1.30
V
1.1
1.45
1.8
V
Load Monitor Input Threshold
(Falling Edge)
VVMON
LDMONEN bit = ‘1’
Load Monitor Input Threshold
(Hysteresis)
VVMONH
LDMONEN bit = ‘1’
0.25
mV
Load Monitor Current
IVMON
V(VMON) between VVMON and V(VCC)
20
40
60
µA
Short-Circuit Time-out
(Default Highlighted)
tSCD
Short-circuit detection delay (SCLONG
bit = ‘0’)
90
190
290
µs
Short-circuit detection delay (SCLONG
bit = ‘1’)
5
10
15
ms
tOCD = 160ms (OCDT1, OCDT0 = 0, 0 and
DTDIV = 0)
80
160
240
ms
tOCD = 320ms (OCDT1, OCDT0 = 0, 1 and
DTDIV = 0)
160
320
480
ms
tOCD = 640ms (OCDT1, OCDT0 = 1, 0 and
DTDIV = 0)
320
640
960
ms
tOCD = 1280ms (OCDT1, OCDT0 = 1, 1 and
DTDIV = 0)
640
1280
1920
ms
tOCD = 2.5ms (OCDT1, OCDT0 = 0, 0 and
DTDIV = 1)
1.25
2.50
3.75
ms
tOCD = 5ms (OCDT1, OCDT0 = 0, 1 and
DTDIV = 1)
2.5
5
7.5
ms
tOCD = 10ms (OCDT1, OCDT0 = 1, 0 and
DTDIV = 1)
5
10
15
ms
tOCD = 20ms (OCDT1, OCDT0 = 1, 1 and
DTDIV = 1)
10
20
30
ms
Over Discharge Current Time-out
(Default Highlighted)
FN8306 Rev.2.00
May 1, 2017
tOCD
Page 8 of 36
ISL94208
Electrical Specifications
VCC = 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
Over Charge Current Time-out
(Default Highlighted)
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
tOCC = 80ms (OCCT1,OCCT0 = 0, 0 and
CTDIV = 0)
40
80
120
ms
tOCC = 160ms (OCCT1, OCCT0 = 0, 1 and
CTDIV = 0)
80
160
240
ms
tOCC = 320ms (OCCT1, OCCT0 = 1, 0 and
CTDIV = 0)
160
320
480
ms
tOCC = 640ms (OCCT1, OCCT0 = 1, 1 and
CTDIV = 0)
320
640
960
ms
tOCC = 2.5ms (OCCT1, OCCT0 = 0, 0 and
CTDIV = 1)
1.25
2.50
3.75
ms
tOCC = 5ms (OCCT1, OCCT0 = 0, 1 and
CTDIV = 1)
2.5
5
7.5
ms
tOCC = 10ms (OCCT1, OCCT0 = 1, 0 and
CTDIV = 1)
5
10
15
ms
tOCC = 20ms (OCCT1, OCCT0 = 1, 1 and
CTDIV = 1)
10
20
30
ms
SYMBOL
tOCC
TEST CONDITION
OVER-TEMPERATURE PROTECTION SPECIFICATIONS
Internal Temperature Shutdown
Threshold
TINTSD
Internal Temperature Hysteresis
THYS
Internal Over-temperature Turn-On
Delay Time
tITD
External Temperature Output Current
IXT
External Temperature Limit Threshold
TXTF
External Temperature Limit Hysteresis
TXTH
Temperature drop needed to restore
operation after over-temperature shutdown
125
°C
20
°C
128
ms
Current output capability at TEMP3V pin
1.2
Voltage at VTEMPI; Relative to
V TEMP3V falling edge
-----------------------------13
-20
0
+20
mV
60
110
160
mV
V TEMP3V
mA
Voltage at VTEMPI relative to -----------------------------13
Delay between activating the external
sensor and the internal over-temperature
detection
1
ms
tXTAON
TEMP3V is ON (3.3V)
5
ms
tXTAOFF
TEMP3V output is off
635
ms
External Temperature Monitor Delay
tXTD
External Temperature Autoscan On
Time
External Temperature Autoscan Off
Time
ANALOG OUTPUT SPECIFICATIONS
Cell Monitor Analog Output Voltage
Accuracy
VAOC
[VCELLN - VCELLN-1]/2 - AO
-15
Cell Monitor Analog Output External
Temperature Accuracy
VAOXT
External temperature monitoring accuracy.
Voltage error at AO when monitoring TEMPI
voltage (measured with TEMPI = 1V)
-10
Internal Temperature Monitor Output
Voltage Slope
VINTMON
Internal Temperature Monitor Output
TINT25
FN8306 Rev.2.00
May 1, 2017
4
30
mV
10
mV
Internal temperature monitor voltage
change
-3.5
mV/°C
Output at +25°C
1.31
V
Page 9 of 36
ISL94208
Electrical Specifications
VCC = 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
AO Output Stabilization Time
SYMBOL
TEST CONDITION
tVSC
From SCL falling edge at data bit 0 of
command to AO output stable within 0.5%
of final value. AO voltage steps from 0V to
2V. (CAO = 10pF). (Note 10)
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
0.1
ms
10
Ω
200
mA
7.0
V
CELL BALANCE SPECIFICATIONS
Cell Balance Transistor rDS(ON)
RCB
Cell Balance Transistor Current
ICB
5
WAKE-UP/SLEEP SPECIFICATIONS
Device WKUP Pin Voltage Threshold
(WKUP Pin Active High - Rising Edge)
VWKUP1
WKUP pin rising edge (WKPOL = 1)
Device wakes up and sets WKUP flag HIGH
Device Wkup Pin Hysteresis
(WKUP Pin Active High)
VWKUP1
WKUP pin falling edge hysteresis
(WKPOL = 1) sets WKUP flag LOW (does not
automatically enter sleep mode)
Input Resistance On WKUP
RWKUP
HYS
Resistance from WKUP pin to VSS
(WKPOL = 1)
Device WKUP Pin Active Voltage
Threshold (WKUP Pin Active
Low-Falling Edge)
VWKUP2
WKUP pin falling edge (WKPOL = 0)
Device wakes up and sets WKUP flag HIGH
Device WKUP Pin Hysteresis
(WKUP Pin Active Low)
VWKUP2
WKUP pin rising edge hysteresis
(WKPOL = 0) sets WKUP flag LOW (does not
automatically enter sleep mode)
Device Wake-up Delay
HYS
tWKUP
Delay after voltage on WKUP pin crosses
the threshold (rising or falling) before
activating the WKUP bit
3.5
5.0
100
mV
250
360
450
kΩ
VBACK - 2.2
VBACK - 1.8
VBACK - 1.4
V
200
20
40
mV
60
ms
5.6
10.8
V
4.4
10.8
V
8.4
14.4
V
6.6
14.4
V
FET CONTROL SPECIFICATIONS
VFET1 Voltage
VVFET1A
VVFET1B
VFET2 Voltage
VVFET2A
VVFET2B
Control Outputs Response Time
(CFET, DFET)
0°C to +85°C
tCO
0°C to +85°C
Bit 0 to start of control signal (DFET)
Bit 1 to start of control signal (CFET)
1.0
µs
CFET Gate Voltage
VCFET
No load on CFET
VFET2- 0.5
VFET2
V
DFET Gate Voltage
VDFET
No load on DFET
VFET2- 0.5
VFET2
V
FET Turn On Current (DFET)
IDF(ON)
DFET voltage = 0 to VFET2 -1.5V
-20°C to +85°C
80
200
450
µA
FET Turn On Current (CFET)
ICF(ON)
CFET voltage = 0 to VFET2 - 1.5V
-20°C to +85°C
80
200
450
µA
100
180
FET Turn Off Current (DFET)
IDF(OFF)
DFET voltage = FET2 to 1V
DFET Resistance to VSS
RDF(OFF)
VDFET < 1V (When turning off the FET)
mA
11
Ω
400
kHz
SERIAL INTERFACE CHARACTERISTICS
SCL Clock Frequency
fSCL
Pulse Width Suppression Time at SDA
and SCL Inputs
tIN
Any pulse narrower than the max spec is
suppressed
50
ns
SCL Falling Edge to SDA Output Data
Valid
tAA
From SCL falling crossing VIH(min), until
SDA exits the VIL(max) to VIH(min) window
0.9
µs
FN8306 Rev.2.00
May 1, 2017
Page 10 of 36
ISL94208
Electrical Specifications
VCC = 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
Time the Bus Must Be Free Before
Start of New Transmission
tBUF
SDA crossing VIH(min) during a STOP
condition to SDA crossing VIH(min) during
the following START condition
1.3
µs
Clock Low Time
tLOW
Measured at the VIL(max) crossing
1.3
µs
tHIGH
Clock High Time
Measured at the VIH(min) crossing
0.6
µs
Start Condition Setup Time
tSU:STA
SCL rising edge to SDA falling edge. Both
crossing the VIH(min) level
0.6
µs
Start Condition Hold Time
tHD:STA
From SDA falling edge crossing VIL(max) to
SCL falling edge crossing VIH(min)
0.6
µs
Input Data Setup Time
tSU:DAT
From SDA exiting the VIL(max) to VIH(min)
window to SCL rising edge crossing VIL(min)
100
ns
Input Data Hold Time
tHD:DAT
From SCL falling edge crossing VIH(min) to
SDA entering the VIL(max) to VIH(min)
window
0
Stop Condition Setup Time
tSU:STO
From SCL rising edge crossing VIH(min) to
SDA rising edge crossing VIL(max)
0.6
µs
Stop Condition Hold Time
tHD:STO
From SDA rising edge to SCL falling edge.
Both crossing VIH(min)
0.6
µs
Data Output Hold Time
tDH
From SCL falling edge crossing VIL(max)
until SDA enters the VIL(max) to VIH(min)
window. (Note 9)
0
ns
SDA and SCL Rise Time
tR
From VIL(max) to VIH(min) (Notes 11, 12)
20 + 0.1 x Cb
300
ns
SDA and SCL Fall Time
tF
From VIH(min) to VIL(max) (Notes 11, 12)
20 + 0.1 x Cb
300
ns
Capacitive Loading of SDA or SCL
Cb
Total on-chip and off-chip (Notes 11, 12)
10
400
pF
SDA and SCL Bus Pull-up Resistor
Off Chip
ROUT
Maximum is determined by tR and tF.
For CB = 400pF, max is about 2kΩ~ 2.5kΩ
For CB = 40pF, max is about 15kΩ to 20kΩ
(Notes 11, 12)
1
0.9
µs
kΩ
Input Leakage Current (SCL, SDA)
ILI
-10
10
µA
Input Buffer Low Voltage (SCL, SDA)
VIL
Voltage relative to VSS of the device
-0.3
VRGO x 0.3
V
Input Buffer High Voltage (SCL, SDA)
VIH
Voltage relative to VSS of the device
VRGO x 0.7
VRGO + 0.1V
V
0.4
V
Output Buffer Low Voltage (SDA)
SDA and SCL Input Buffer Hysteresis
VOL
I2CHYST
IOL = 1mA
Sleep bit = 0
0.05 * VRGO
V
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
8. Power-up of the device requires VBACK and VCC to be above the limits specified.
9. The device provides an internal hold time of at least 300ns for the SDA signal to bridge the unidentified region of the falling edge of SCL.
10. Maximum output capacitance = 15pF.
11. These are I2C specific parameters and are not production tested. However, they are used to set conditions for testing to validate specification.
12. Limits should be considered typical and are not production tested.
FN8306 Rev.2.00
May 1, 2017
Page 11 of 36
ISL94208
Timing Diagrams
50µs
SLEEP BIT
SLEEP BIT
I2C WRITE
(SLEEP BIT)
I2C WRITE
(SLEEP BIT)
1
4V
RGC PIN
1V
AWAKE
** Note 23
§
§
Note 24
101
*
Note 22
SLEEP
ON
RGC PIN
OFF
0
*
Note 22
SLEEP
AWAKE
AWAKE
WKUP PIN NORMALLY ABOVE FALLING EDGE THRESHOLD
1
AWAKE
SLEEP
AWAKE
WKUP PIN NORMALLY BELOW FALLING EDGE THRESHOLD
FIGURE 16. SLEEP/WAKE-UP TIMING (WKPOL BIT = 0)
FN8306 Rev.2.00
May 1, 2017
Page 23 of 36
ISL94208
MAINTAINING THIS CONDITION CAUSES
HIGH CURRENT ON VBACK (~200uA)
tWKUP
Note 21
Note 21
WKUP PIN
tWKUP
tWKUP
RISING
EDGE
WKUP PIN
THRESHOLD
#
tWKUP
100µs
Rising
Edge
Threshold
tWKUP
#
50µs
>50µs
Note 24
§
SLEEP BIT
** Note 23
SLEEP BIT
I2C WRITE
(SLEEP BIT)
§
Note 24
I2C WRITE
(SLEEP BIT)
1
ON
RGC PIN
OFF
** Note 23
101
0
1
ON
RGC PIN
OFF
*
AWAKE
Note 22
SLEEP
AWAKE
*
AWAKE
WKUP PIN NORMALLY BELOW RISING EDGE THRESHOLD
SLEEP
AWAKE
SLEEP
AWAKE
WKUP PIN NORMALLY ABOVE RISING EDGE THRESHOLD
NOTES:
21. # These are Glitches on the WKUP pin that are not long enough to exceed the internal filter and are not detected as valid signals.
22. * These periods are pseudo-sleep. The regulator turns on to power the wake-up circuits, but Wake-up is not complete until the WKUP bit is latched.
23. ** The rising edge of the WKUP bit resets the SLEEP bit, if not already reset.
24. § When the WKUP pin is Active during Awake periods, the device needs a falling edge on the SLEEP bit (while the WKUP pin is above the threshold)
before the SLEEP bit can force sleep. The diagram shows two methods of doing this.
FIGURE 17. SLEEP/WAKEUP TIMING (WKPOL BIT = 1)
Protection Functions
In the default recommended condition, the ISL94208
automatically responds to discharge overcurrent, discharge
short-circuit, charge overcurrent, internal over-temperature, and
external over-temperature conditions. The designer can set
optional over-ride conditions that allow the response to be
dictated by the microcontroller. These are discussed in the
following sections.
Overcurrent Safety Functions
The ISL94208 continually monitors the discharge current by
monitoring the voltage at the CSENSE and DSENSE pins. If that
voltage exceeds a selected value for a time exceeding a selected
delay, then the device enters an overcurrent or short-circuit
protection mode. In these modes, the ISL94208 automatically
turns off both power FETs and hence prevents current from
flowing through the terminals P+ and P-. See Figure 29 on page
32.
The voltage thresholds and the response times of the overcurrent
protection circuits are selectable for discharge overcurrent,
charge overcurrent, and discharge short-circuit conditions. The
specific settings are determined by bits in the Discharge Set
Configuration Register (ADDR:05H) on page 18, and the Charge/
Time Scale Configuration Scale Register (ADDR:06H) on
page 19. In addition, refer to “Registers” on page 15.
FN8306 Rev.2.00
May 1, 2017
In an overcurrent condition, the ISL94208 automatically turns off
the voltage on CFET and DFET pins. The DFET output drives the
discharge FET gate low, turning off the FET quickly. The CFET output
turns off and allows the gate of the charge FET to be pulled low
through a resistor.
By turning off the FETs the ISL94208 prevents damage to the
battery pack caused by excessive current into or out of the cells (as
in the case of a faulty charger or short-circuit condition).
When the ISL94208 detects a discharge overcurrent condition, both
power FETs are turned off and the DOC bit is set. When the FETs are
turned off, the DFET and CFET bits are also reset. The automatic
response to overcurrent during discharge is prevented by setting the
DENOCD bit to ‘1’. The external microcontroller can turn on the FETs
at any time to recover from this condition, but it would usually turn
on the load monitor function first (by setting the LDMONEN bit) and
monitor the LDFAIL bit to detect that the overcurrent condition has
been removed.
When the ISL94208 detects a discharge short-circuit condition, both
power FETs are turned off and DSC bit is set. When the FETs are
turned off, the DFET and CFET bits are also reset. The automatic
response to short-circuit during discharge is prevented by setting the
DENSCD bit to ‘1’. The external microcontroller can turn on the FETs
at any time to recover from this condition, but it would usually turn
on the load monitor function first (by setting the LDMONEN bit) and
monitor the LDFAIL bit to detect that the overcurrent condition has
been removed.
Page 24 of 36
ISL94208
When the ISL94208 detects a charge overcurrent condition, both
power FETs are turned off and COC bit is set. When the FETs are
turned off, the DFET and CFET bits are also reset. The automatic
response to overcurrent during discharge is prevented by setting the
DENOCC bit to ‘1’. The external microcontroller can turn on the FETs
at any time to recover from this condition, but it would usually wait
to do this until the cell voltages are not overcharged and that the
overcurrent condition has been removed (or the microcontroller
could wait until the pack is removed from the charger and then
re-attached).
An alternative method of providing the protection function, if desired
by the designer, is to turn off the automatic safety response. In this
case, the ISL94208 devices still monitor the conditions and set the
status bits, but take no action in overcurrent or short-circuit
conditions. Safety of the pack depends, instead, on the
microcontroller sending commands to the ISL94208 to turn off the
FETs.
To facilitate a microcontroller response to an overcurrent condition,
especially if the microcontroller is in a low power state, a charge
overcurrent flag (COC), a discharge overcurrent flag (DOC), or the
short-circuit flag (DSC) being set causes the ISL94208 TEMP3V
output to turn on and pull high (see Figure 19). This output can be
used as an external interrupt by the microcontroller to wake-up
quickly to handle the overcurrent condition.
P+
VSS
RL
PR1
ISL94208
VMON
VREF
LDFAIL
= 1 if VMON > VVMONH
= 0 if VMON < VVMONH
LDMONEN
VSS
FIGURE 18. LOAD MONITOR CIRCUIT
Load Monitoring
The load monitor function in the ISL94208 (see Figure 18) is
used primarily to detect that the load has been removed
following an overcurrent or short-circuit condition during
discharge. This can be used in a control algorithm to prevent the
FETs from turning on while the overload or short-circuit condition
remains.
The load monitor can also be used by the microcontroller
algorithms after an undervoltage condition on any cells causes
the FETs to turn off. Use of the load monitor prevents the FETs
FN8306 Rev.2.00
May 1, 2017
The load monitor circuit can be turned on or off by the
microcontroller. It is normally turned off to minimize current
consumption. It must be activated by the external microcontroller
for it to operate. The circuit works by internally connecting the
VMON pin to VSS through a resistor. The circuit operates as
shown in Figure 18.
In a typical pack operation, when an overcurrent or short-circuit
event happens, the DFET turns off, opening the battery circuit to
the load. At this time, the RL is small and the load monitor is
initially off. In this condition, the voltage at VMON rises to nearly
the pack voltage.
When the power FETs turn off, the microcontroller activates the
load monitor by setting the LDMONEN bit. This turns on an
internal FET that adds a pull down resistor to the load monitor
circuit. While still in the overload condition the combination of
the load resistor, an external adjustment resistor (R1), and the
internal load monitor resistor form a voltage divider. R1 is chosen
so that when the load is released to a sufficient level, the LDFAIL
condition is reset.
The diode in the VMON circuit is necessary to prevent the VMON
voltage from going negative with respect to VSS when a charger
connects between P+ and P- and the charger voltage is
significantly larger than the battery stack voltage.
OPEN
POWER FETs
from turning on while the load is still present. This minimizes the
possible “on-off-on cycles” that can occur when a load is applied
in a low capacity pack. It can also be part of a system protection
mechanism to prevent the load from turning on automatically.
That is, some action must be taken before the pack is again
turned on.
Over-Temperature Safety Functions
EXTERNAL TEMPERATURE MONITORING
The external temperature is monitored by using a voltage divider
consisting of a fixed resistor and a thermistor. This divider is
powered by the ISL94208 TEMP3V output. This output is
normally controlled so it is on for only short periods to minimize
current consumption.
Without microcontroller intervention, and in the default state, the
ISL94208 provides an automatic temperature scan. This scan
circuit repeatedly turns on TEMP3V output (and the external
temperature monitor) for 5ms out of every 640ms. In this way,
the external temperature is monitored even if the microcontroller
is asleep.
When the TEMP3V output turns on, the ISL94208 waits 1ms for
the temperature reading to stabilize, then compares the external
temperature voltage with an internal voltage divider that is set to
TEMP3V/13. If the thermistor voltage is below the reference
threshold after the delay, an external temperature fail condition
exists. To set the external over-temperature limit, set the value of
RX resistor to 12 times the resistance of the thermistor at the
desired over-temp threshold.
The TEMP3V output pin also turns on when the microcontroller
sets the AO3:AO0 bits to select that the external temperature
voltage. This causes the TEMPI voltage to be placed on AO and
activates (after 1ms) the over-temperature detection. As long as
the AO3:AO0 bits point to the external temperature, the TEMP3V
Page 25 of 36
ISL94208
In the event of an automatic over-temperature condition, cell
balancing is prevented and the FETs are held off until the
temperature drops below the temperature recovery threshold.
During this temperature shutdown period, the microcontroller
can monitor the internal temperature through the analog output
pin (AO), but any writes to the CFET bit, DFET bit, or cell balancing
bits are ignored
Analog Multiplexer Selection
The ISL94208 devices can be used to externally monitor
individual battery cell voltages and temperatures. Each quantity
can be monitored at the analog output pin (AO). The desired
voltage is selected using the I2C interface and the AO3:AO0 bits.
See Figure 20 and Table 6 on page 17. Remember to reset the
AO3:AO0 bits to ‘0000’ after measurements to minimize
unnecessary current draw from the cells.
ATMPOFF
TMP3ON
ISL94208
OSC
RGO
AO3:AO0
TO
µC
DECODE
EXT TEMP
TEMP3V
12R
The automatic response to an internal over-temperature is
prevented by setting the DISITSD bit to ‘1’. The automatic
response to an external over-temperature is prevented by setting
the DISXTSD bit to ‘1’. In either case, it is important for the
microcontroller to monitor the internal and external temperature
to protect the pack and the electronics in an over-temperature
condition.
I2C
DISCHARGE SC
I2C
PROTECTION CIRCUITS
Turning off the FETs in the event of an over-temperature
condition prevents continued discharge or charge of the cells
when they are overheated. Turning off cell balancing in the event
of an over-temperature condition prevents damage to the IC if
too many cells are being balanced, which would cause too much
power dissipation in the ISL94208.
4ms
508ms
AO
MUX
RX
TEMPI
1ms
DELAY
XOT
EXTERNAL
TEMP
MONITOR
Rth
R
By default, when the ISL94208 detects an internal or external
over-temperature condition, the FETs are turned off, the cell
balancing function is disabled, and the IOT bit or XOT bit
(respectively) is set.
A similar operation occurs when monitoring the internal
temperature through the AO output, except there is no external
“calibration” of the voltage associated with the internal
temperature. For the internal temperature monitoring, the
voltage at the output is linear with respect to temperature. See
“Electrical Specifications” on page 6 for information about the
output voltage at +25°C and the output slope relative to
temperature.
CHARGE OC
PROTECTION
The voltage representing the external temperature applied at the
TEMPI terminal is directed to the AO terminal through a MUX, as
selected by the AO control bits (see Figures 19 and 20). The
external temperature voltage is not divided by 2 as are the cell
voltages. Instead it is a direct reflection of the voltage at the
TEMPI pin.
DISCHARGE OC
The microcontroller can override both the automatic temperature
scan and the microcontroller controlled temperature scan by
setting the TEMP3ON configuration bit. This turns on the TEMP3V
output to keep the temperature control voltage on all the time for
a continuous monitoring of an over-temperature condition. This
likely will consume a significant amount of current, so this feature
is usually used for special or test purposes.
Temperature Monitoring
REGISTERS
output remains on. Because of the manual scan of the
temperature, it may be desired to turn off the automatic scan,
although they can be used at the same time without
interference. To turn off the automatic scan, set the ATMPOFF bit.
VSS
TEMP FAIL
INDICATOR
FIGURE 19. EXTERNAL TEMPERATURE MONITORING AND
CONTROL
Voltage Monitoring
Because the voltage on each of the Li-ion Cells is normally higher
than the regulated supply voltage, and because the voltages on
the upper cells are much higher than is tolerated by a
microcontroller, it is necessary to both level shift and divide the
voltage before it can be monitored by the microcontroller or an
external A/D converter. To get into the voltage range required by
the external circuits, the voltage level shifter divides the cell
voltage by 2 and references it to VSS. Therefore, a Li-ion cell with
a voltage of 4.2V becomes a voltage of 2.1V on the AO pin.
FN8306 Rev.2.00
May 1, 2017
Page 26 of 36
ISL94208
Cell Balancing
Overview
A typical ISL94208 Li-ion battery pack consists of four to six cells
in series, with one or more cells in parallel. This combination
gives both the voltage and power necessary for many battery
powered applications. While the series/parallel combination of
Li-ion cells is common, the configuration is not as efficient as it
could be, because any capacity mismatch between
series-connected cells reduces the overall pack capacity. This
mismatch is greater as the number of series cells and the load
current increase. Cell balancing techniques increase the
capacity, and the operating time, of Li-ion battery packs.
Definition of Cell Balancing
Cell balancing is defined as the application of differential
currents to individual cells (or combinations of cells) in a series
string. Without cell balancing, cells in a series string receive
nominally identical currents. A battery pack requires additional
components and circuitry to achieve cell balancing. For the
ISL94208 devices, balancing resistors are the only external
components required.
SCL
SDA
I2C
LEVEL
SHIFT
VCELL7
LEVEL
SHIFT
VCELL6
LEVEL
SHIFT
VCELL2
LEVEL
SHIFT
VCELL1
REGS
AO3:AO0
DECODE
AO
2
MUX
resistor across the specified cell. The maximum current that can
be drawn from (or bypassed around) the cell is 200mA. This
current is set by selecting the value of the external resistor.
Figure 21 shows an example with a 200mA (maximum)
balancing current.
With lower balancing current, more balancing FETs can be turned
on at once, without exceeding the device power dissipation limits
or generating excessive balancing current that will heat the
external resistor.
External VMON/CFET Protection
Mechanisms
When there is a single charge/discharge path, a blocking diode
is recommended in the VMON to Pack- (discharge) path in
ISL94208 solution. See D1 in Figure 22. This diode is to protect
against a negative voltage on the VMON pin that can occur when
the FETs are off and the charger connects to the pack. This diode
is not needed when there is a separate charge and discharge
path, because the voltages on Pack- (discharge) are always
positive.
When the pack is designed with a single set of charge/discharge
FETs, the ISL94208 CFET pin should be protected in the event of
an overcurrent or short-circuit shutdown. When this happens, the
FET opens suddenly. The flyback voltage from the motor windings
could exceed the maximum input voltage on the CFET pin.
Therefore, it is recommended that an additional external series
diode be placed between the CFET pin of the ISL94208 and the
gate of the Charge FET. See Diode D3 in Figure 22. This reduces
the CFET gate voltage, but not significantly.
Finally, to protect the Charge FET itself in the event of a large
negative voltage on the Pack- pin, zener diode D4 is added. A
large negative voltage can occur when the Pack- (discharge) pin
goes significantly negative, while the CFET pin is being internally
clamped. The zener voltage of D4 should be less than the
VGS(max) specification of the FET.
VSS
EXT TEMP.
MUX
VCELL7
TEMPI
21Ω
1W
INT
TEMP
ISL94208
CB7
200mA
FIGURE 20. ANALOG OUTPUT MONITORING DIAGRAM
7 6 5 4 3 2 1
VCELL1
Cell Balance Operation
Cell balancing is accomplished through a microcontroller
algorithm. This algorithm compares the cell voltages (a
representation of the pack capacity) and turns on balancing for
the cells that have the higher voltages. There are many
parameters that should be considered when writing this
algorithm. An example cell balancing algorithm is available in
the ISL94208EVAL1Z evaluation kit.
The microcontroller turns on a specific cell balancing switch by
setting a bit in the Cell Balance Register. Each bit in the register
corresponds to one cell’s balancing control. When the bit is set,
an internal cell balancing FET turns on. This connects an external
FN8306 Rev.2.00
May 1, 2017
21Ω
1W
CELL
BALANCE
CONTROL
(REG 02H)
CB1
VSS
FIGURE 21. CELL BALANCING CONTROL EXAMPLE WITH 200mA
BALANCING CURRENT
Page 27 of 36
ISL94208
PACK+
PACKD1
VMON
10MΩ
ISL94208
D4
1MΩ
D3
CFET
DFET
I2C Interface
Interface Conventions
The device provides an I2C communications interface. The
protocol defines any device that sends data onto the bus as a
transmitter, and the receiving device as the receiver. The device
controlling the transfer is called the Master and the device being
controlled is called the Slave. The Master always initiates data
transfers, and provides the clock for both transmit and receive
operations. Therefore, the ISL94208 devices operate as slaves in
all applications.
When sending or receiving data, the convention is that the Most
Significant Bit (MSB) is sent first. Therefore, the first address bit
sent is bit 7.
Clock and Data
FIGURE 22. USE OF DIODES FOR PROTECTING THE CFET AND
VMON PINS
User Flags
The ISL94208 contains four flags in the register area that the
microcontroller can use for general purpose indicators. These
bits are designated UFLG3, UFLG2, UFLG1, and UFLG0. The
microcontroller can set or reset these bits by writing into the
appropriate register.
The user flag bits are battery backed up (by the VBACK pin
voltage), so the contents remain even after exiting Sleep mode.
However, if the microcontroller sets the POR bit to force a power
on reset, all of the user flags are also reset. In addition, if the
voltage on VBACK ever drops below the POR voltage, the
contents of the user flags (as well as all other register values)
would be lost.
FN8306 Rev.2.00
May 1, 2017
Data states on the SDA line can change only while SCL is LOW.
SDA state changes while SCL HIGH are reserved for indicating
START and STOP conditions. See Figure 23.
Start Condition
All commands are preceded by the START condition, which is a
HIGH-to-LOW transition of SDA when SCL is HIGH. The device
continuously monitors the SDA and SCL lines for the START
condition and does not respond to any command until this
condition has been met. See Figure 24.
Stop Condition
All communications must be terminated by a STOP condition,
which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The
STOP condition is also used to place the device into the Standby
power mode after a Read sequence. A STOP condition is only
issued after the transmitting device has released the bus. See
Figure 24.
Page 28 of 36
ISL94208
Acknowledge (ACK)
.
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either Master
or Slave, releases the bus after transmitting eight bits. During the
ninth clock cycle, the receiver pulls the SDA line LOW to
acknowledge that it received the eight bits of data. See
Figure 25.
The device responds with an Acknowledge after recognition of a
START condition and the correct Slave byte. If a Write operation is
selected, the device responds with an Acknowledge after the
receipt of each subsequent eight bits. The device acknowledges
all incoming data and Address bytes, except for the Slave byte
when the contents do not match the device’s address.
In the Read mode, the device transmits eight bits of data,
releases the SDA line, then monitors the line for an
Acknowledge. If an acknowledge is detected and no STOP
condition is generated by the Master, the device continues
transmitting data. The device terminates further data
transmissions if an acknowledge is not detected. The Master
must then issue a STOP condition to return the device to Standby
mode and place the device into a known state.
SCL
SDA
START
STOP
FIGURE 24. I2C START AND STOP BITS
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 25. ACKNOWLEDGE RESPONSE FROM RECEIVER
SCL
SDA
DATA
STABLE
DATA
CHANGE
DATA
STABLE
FIGURE 23. VALID DATA CHANGES ON I2C BUS
FN8306 Rev.2.00
May 1, 2017
Page 29 of 36
ISL94208
Write Operations
After receiving the Acknowledge after the Data byte, the device
automatically increments the address. So, before sending the
STOP bit, the Master may send additional data to the device
without re-sending the Slave and Register Address bytes. After
writing to address 0AH, the address “wraps around” to address 0.
Do not continue to write to addresses higher than address 08H,
because these addresses access registers that are reserved.
Writing to these locations can result in unexpected device
operation.
For a Write operation, the device requires a Slave byte and a
Register Address byte. The Slave byte specifies the particular device
on the I2C bus that the Master is writing to. The Register Address
specifies one of the registers in that device. After receipt of each
byte, the device responds with an Acknowledge, and awaits the next
eight bits from the Master. After the Acknowledge, following the
transfer of data, the Master terminates the transfer by generating a
STOP condition (see Figure 26).
SIGNALS
FROM THE
MASTER
When receiving data from the Master, the value in the Data byte
is transferred into the register specified by the Register address
byte on the falling edge of the clock following the eighth data bit.
S
T
A
R
T
REGISTER
ADDRESS
S
T
O
P
DATA
01010000
A
C
K
SIGNALS
FROM THE
SLAVE
SDA BUS
SLAVE
BYTE
A
C
K
A
C
K
ISL94208: SLAVE BYTE = 50H
FIGURE 26. WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
Read Sequence
SDA BUS
SIGNALS
FROM THE
SLAVE
RANDOM READ
S
T
A
R
T
SLAVE
BYTE
REGISTER
ADDRESS
S
AT
CO
KP
SLAVE
BYTE
01010001
01010000
A
C
K
A
C
K
A
C
K
DATA
ISL94208: SLAVE BYTE = 010100xH
S
T
A
R
T
CURRENT ADDRESS READ
S
T
A
R
T
S
AT
CO
KP
SLAVE
BYTE
01010001
A
C
K
DATA
FIGURE 27. READ SEQUENCE
FN8306 Rev.2.00
May 1, 2017
Page 30 of 36
ISL94208
Register Protection
The Discharge Set, Charge Set, and Feature Set configuration
registers are write protected on initial power up. To write to these
registers it is necessary to set a bit to enable each one. These
write enable bits are in the Write Enable register (Address 08H).
1. Write the FSETEN bit (Addr 8:bit 7) to ‘1’ to enable changes to
the data in the Feature Set register (Address 7).
2. Write the CHSETEN bit (Addr 8:bit 6) to ‘1’ to enable changes
to the data in the Feature Set register (Address 6).
3. Write the DISSETEN bit (Addr 8:bit 5) to ‘1’ to enable changes
to the data in the Feature Set register (Address 5).
The microcontroller can reset these bits back to zero to prevent
inadvertent writes that change the operation of the pack.
Operation State Machine
Figure 28 shows a device state machine, which illustrates how
the ISL94208 responds to various conditions.
POWER FAILS AND VCC OR VBACK OR BOTH SUPPLIES DO NOT MEET MINIMUM
VOLTAGE REQUIREMENTS
POWER DOWN STATE
I2C INTERFACE IS DISABLED.
BIASING IS DISABLED.
ALL REGISTERS SET TO DEFAULT VALUES
(ALL = ‘0’)
POWER IS APPLIED AND BOTH VCC AND VBACK MEET MINIMUM
VOLTAGE REQUIREMENTS
POWER UP STATE
I2C INTERFACE IS ENABLED.
BIASING IS ENABLED.
VOLTAGE REGULATOR IS ENABLED.
SLEEP BIT
(WKUP NOT ACTIVE)
MAIN OPERATING STATE (AWAKE)
• VOLTAGE REGULATOR IS ON
• LOGIC AND REGISTERS ARE POWERED
BY RGO
• CFET, DFET, AND CELL BALANCING
OUTPUTS ARE ON OR OFF. (REQUIRE AN
EXTERNAL COMMAND TO TURN ON).
• THE OVER-TEMPERATURE PROTECTION
CIRCUIT IS ACTIVE.
• OVERCURRENT PROTECTION (OCP)
CIRCUITS ARE ACTIVE WHEN THE
EITHER OF THE CFET AND DFET
OUTPUTS ARE ENABLED. THE OCP
CIRCUITS ARE OFF WHEN BOTH THE
CFET AND DFET OUTPUTS ARE OFF.
• OVERCURRENT CONDITIONS FORCE
THE POWER FETS TO TURN OFF.
OVER-TEMPERATURE CONDITIONS
FORCE THE POWER FETS AND CELL
BALANCE OUTPUT OFF.
• VOLTAGE AND TEMPERATURE
MONITORING CIRCUITS ARE AWAITING
EXTERNAL CONTROL.
SLEEP BIT
(WKUP ACTIVE)
WKUP GOES ABOVE OR
BELOW THRESHOLD (EDGE
TRIGGERED).
OR, SLEEP BIT IS SET TO ‘0’
SLEEP STATE
• VOLTAGE REGULATOR IS OFF
• BIASING IS OFF
• LOGIC AND REGISTERS ARE POWERED
BY VBACK
• CFET, DFET, AND CELL BALANCING
OUTPUTS ARE OFF.
• CHARGE AND DISCHARGE CURRENT
PROTECTION CIRCUITS ARE OFF.
• VOLTAGE AND TEMPERATURE
MONITORING CIRCUITS ARE OFF.
• I2C COMMUNICATION IS ACTIVE (IF
VBACK VOLTAGE IS HIGH ENOUGH TO
OPERATE WITH THE EXTERNAL
DEVICE).
FIGURE 28. DEVICE OPERATION STATE MACHINE
FN8306 Rev.2.00
May 1, 2017
Page 31 of 36
ISL94208
Application Circuits
The following application circuits are ideas to consider when developing a battery pack implementation. There are many more ways
that the pack can be designed.
Integrated Charge/Discharge Path
P+
VBACK
20Ω
200Ω
20Ω
200Ω
20Ω
200Ω
VFET2
VFET1
VCC
VCELL6
500Ω
200kΩ
WKUP
100kΩ
ISL94208
CB6
VCELL5
2N7002
RGC
CB5
VCELL4
RGO
15V
1µF
CB4
µC
20Ω
200Ω
20Ω
VCELL2
AO
VCELL1
B-
CB1
VMON
VSS
VCC
RESET
SCL
SDA
INT
A/D IN
GP
I/O
OPTIONAL
LEDS/
RESISTORS
CHRG
100Ω
I/O
3.6V
CFET
DFET
VCELL0
ISREF
20Ω
TEMPI
SCL
SDA
CB2
VBACK
200Ω
10µF 10µF10µF
CB3
TEMP3V
DSENSE
200Ω
200Ω
VCELL3
CSENSE
20Ω
200Ω
THERM
200Ω
CHGR Present
240k
27Ω
PACK INTERFACE
NOT NEEDED DURING
DISCHARGE
16V (
