ISL9502
®
Data Sheet
Two-Phase PWM Controller for Graphics
Processor Units (GPU)
Increase in GPU clock frequency is accompanied by
associated increase in the demand for power and transientcurrent slew rate. At the same time, the voltage tolerance
requirement during steady-state and transient operation is
becoming more stringent of advanced GPU. The ISL9502 is
a two-phase PWM controller with embedded gate drivers,
which is tailored to meet the power and dynamic
requirements. The two-phase buck converter uses two
interleaved channels to effectively double the output voltage
ripple frequency and thereby reduce output voltage ripple
amplitude with fewer components, lower component cost,
reduced power dissipation, and smaller real estate area.
The heart of the ISL9502 is the patented R3 (Robust Ripple
Regulator®) modulator. Compared with the traditional multiphase buck regulator, R3 technology has the fastest transient
response. This is due to the R3 modulator commanding
variable switching frequency during a load transient.
July 17, 2006
FN9275.1
Features
• Precision Two-phase Buck PWM controller
- 0.5% System Accuracy Over Temperature
- Active Voltage Positioning Capability
• Internal Gate Driver with 2A Driving Capability
• Superior Load Transient Response
• Dynamic Phase Adding/Dropping
• Voltage Selection Input
- 6-Bit VSEL Input
- 0.500V to 1.500V in 25mV Steps
- Supports VSEL Change On-The-Fly
• Multiple Current-Sensing Schemes Supported
- Lossless Inductor DCR Current Sensing
- Precision Resistive Current Sensing
• Thermal Monitor
• User Programmable Switching Frequency
At heavy load operation of the active mode, ISL9502
commands the two phase continuous conduction mode
(CCM) operation. While the pin SET3 is asserted at the
medium or light load, the ISL9502 smoothly disables one
phase and operates in a one-phase operation. Once in onephase operation, when the GPU further lowers the load
current, the ISL9502 enables diode emulation to maximize
efficiency at light load depending on the logic of SET1 and
SET2.
• Differential Remote GPU Voltage Sensing
A 6-bit digital-to-analog converter (DAC) allows dynamic
adjustment of the output voltage from 0.500V to 1.500V with
25mV step. A 0.5% system accuracy of the core output
voltage over temperature is achieved by the ISL9502.
ISL9502CRZ
(Note)
A unity-gain differential amplifier is provided for remote GPU
die sensing. This allows the voltage on the GPU die to be
accurately measured and regulated. Current sensing can be
realized using either lossless inductor DCR sensing or
precision resistor sensing. A single NTC thermistor network
can thermally compensates the gain and the time constant of
the DCR variations. Droop control, also referred as adaptive
voltage positioning (AVP), is implemented in ISL9502 to
reduce output decoupling capacitors and achieve more costeffective transient-load regulation.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
1
• Static and Dynamic Current Sharing
• Overvoltage, Undervoltage, and Overcurrent Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART
NUMBER
PART
MARKING
TEMP.
(°C)
PACKAGE
PKG.
DWG. #
ISL9502CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Pb-free)
ISL9502CRZ-T ISL9502CRZ -10 to 100 48 Ld 7x7 QFN L48.7x7
(Note)
(Pb-free)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved. R3 Technology™ is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
ISL9502
Pinout
ISL9502 (7x7 QFN)
TOP VIEW
VW
OCSET
SOFT
NTC
VRHOT#
RBIAS
VDD
SET3
PGOOD
9
8
7
6
5
4
3
2
1
COMP 10
13
48
GND
VSEN
14
47
NC
RTN
15
46
SET2
DROOP
16
45
SET1
DFB
17
44
40
39
VSEL1
ISEN2
38
VSEL0
ISEN1
37
42
41
43
VDD
24
VSUM
VSEL4
VIN
20
VSEL2
23
VSEL5
19
GND
22
18
VSEL3
21
VO
GND PAD
(BOTTOM)
VR_ON
GND
36 BOOT1
35 UGATE1
34 PHASE1
33 PGND1
32 LGATE1
31 PVCC
30 LGATE2
29 PGND2
28 PHASE2
27 UGATE2
26 BOOT2
25 NC
FN9275.1
July 17, 2006
2
FB 11
FB2 12
VDIFF
ISL9502
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 -+7V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25V
Boot1,2 and UGATE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30V
ALL Other Pins. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VRHOT# . . . . . . . . . . . . . . -0.3 -+7V
Thermal Resistance (Typical)
θJA°C/W
θJC°C/W
QFN Package (Notes 1, 2). . . . . . . . . .
29
4.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 22V
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . -10°C to 100°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . -10°C to 125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VDD = 5V, TA = -10°C to 100°C, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VR_ON = 3.3V
-
3.1
3.6
mA
VR_ON = 0V
-
-
1
µA
VR_ON = 0V, VIN = 25V,
-
-
1
µA
PORr
VDD Rising
-
4.35
4.5
V
PORf
VDD Falling
3.9
4.1
-
V
No load, closed loop, active mode,
TA = 0°C to 100°C,
VSEL = 0.75-1.5V
-0.5
-
0.5
%
-2
-
2
%
1.45
1.47
1.49
V
1.188
1.2
1.212
V
INPUT POWER SUPPLY
+5V Supply Current
IVDD
Input Supply Current at VIN Pin
IVIN
POR (Power-On Reset) Threshold
SYSTEM AND REFERENCES
System Accuracy
%Error
(Vcc_core)
VSEL = 0.5-0.725V
RBIAS Voltage
RRBIAS
Boot Voltage
VBOOT
Maximum Output Voltage
RRBIAS = 147kΩ
VCC_CORE
(max)
VSEL = [000000]
-
1.5
-
V
VCC_CORE
(min)
VSEL = [101000]
-
0.5
-
V
RFSET = 3.9kΩ, 2 channel operation,
Vcomp = 2V
-
300
-
kHz
200
-
500
kHz
-0.3
-
0.3
mV
-
90
-
dB
CHANNEL FREQUENCY
Nominal Channel Frequency
fSW
Adjustment Range
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain
AV0
Error Amp Gain-Bandwidth Product
Error Amp Slew Rate
FB Input Current
GBW
CL = 20pF
-
18
-
MHz
SR
CL = 20pF
-
5
-
V/µs
-
10
150
nA
IIN(FB)
3
FN9275.1
July 17, 2006
ISL9502
Electrical Specifications
VDD = 5V, TA = -10°C to 100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Imbalance Voltage
-
-
1
mV
Input Bias Current
-
20
-
nA
-46
-41
-36
µA
ISEN
SOFT-START CURRENT
Soft-Start Current
ISS
GATE DRIVER DRIVING CAPABILITY
UGATE Source Resistance
RSRC(UGATE)
500mA Source Current
-
1
1.5
Ω
UGATE Source Current
ISRC(UGATE)
VUGATE_PHASE = 2.5V
-
2
-
A
UGATE Sink Resistance
RSNK(UGATE)
500mA Sink Current
-
1
1.5
Ω
UGATE Sink Current
ISNK(UGATE)
VUGATE_PHASE = 2.5V
-
2
-
A
LGATE Source Resistance
RSRC(LGATE)
500mA Source Current
-
1
1.5
Ω
LGATE Source Current
ISRC(LGATE)
VLGATE = 2.5V
-
2
-
A
LGATE Sink Resistance
RSNK(LGATE)
500mA Sink Current
-
0.5
0.9
Ω
LGATE Sink Current
ISNK(LGATE)
VLGATE = 2.5V
-
4
-
A
-
1.1
-
kΩ
UGATE to PHASE Resistance
Rp(UGATE)
GATE DRIVER SWITCHING TIMING (refer to timing diagram)
UGATE Rise Time
tRU
PVCC = 5V, 3nF Load
-
8.0
-
ns
LGATE Rise Time
tRL
PVCC = 5V, 3nF Load
-
8.0
-
ns
UGATE Fall Time
tFU
PVCC = 5V, 3nF Load
-
8.0
-
ns
LGATE Fall Time
tFL
PVCC = 5V, 3nF Load
-
4.0
-
ns
UGATE Turn-on Propagation Delay
tPDHU
PVCC = 5V, Outputs Unloaded
20
30
44
ns
LGATE Turn-on Propagation Delay
tPDHL
PVCC = 5V, Outputs Unloaded
7
15
30
ns
0.43
0.58
0.67
V
BOOTSTRAP DIODE
Forward Voltage
PVCC = 5V, Forward Bias Current = 2mA
Leakage
VR = 16V
-
-
1
µA
POWER GOOD and PROTECTION MONITOR
PGOOD Low Voltage
VOL
IPGOOD = 4mA
-
0.11
0.4
V
PGOOD Leakage Current
IOH
PGOOD = 3.3V
-1
-
1
µA
Overvoltage Threshold
OVH
VO rising above setpoint > 1ms
160
200
240
mV
OVHS
VO rising above setpoint > 0.5µs
1.675
1.7
1.725
V
Severe Overvoltage Threshold
OCSET Reference Current
I(Rbias) = 10µA
9.8
10
10.2
µA
OC Threshold Offset
DROOP rising above OCSET > 120µs
-3.5
-
3.5
mV
Current Imbalance Threshold
Difference between ISEN1 and ISEN2 > 1ms
-
7.5
-
mV
-360
-300
-240
mV
Undervoltage Threshold
UVf
VO falling below setpoint for > 1ms
LOGIC INPUTS
VR_ON and SET1 Inputs Low
VIL
-
-
1
V
VR_ON and SET1 Inputs High
VIH
2.3
-
-
V
Leakage Current of VR_ON
4
IIL(3.3)
Logic input is low
-1
0
-
µA
IIH(3.3)
Logic input is high at 3.3V
-
0
1
µA
FN9275.1
July 17, 2006
ISL9502
Electrical Specifications
VDD = 5V, TA = -10°C to 100°C, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
Leakage Current of SET1
IIL_SET1
IIH_SET1
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SET1 input is low
-1
0
-
µA
SET1 input is high at 3.3V
-
0.45
1
µA
DAC(VSEL0-VSEL5), SET3 and
SET2 Inputs Low
VIL
-
-
0.3
V
DAC(VSEL0-VSEL5), SET3 and
SET2 Inputs High
VIH
0.7
-
-
V
Leakage Current of DAC(VSEL0VSEL5), SET3 and SET2
IIL
Logic input is low
-1
0
-
µA
IIH
Logic input is high at 1V
-
0.45
1
µA
53
60
67
µA
1.165
1.18
1.2
V
-
5
9
Ω
THERMAL MONITOR
NTC Source Current
NTC = 1.3 V
Over-temperature Threshold
V(NTC) falling
VRHOT# Low Output Resistance
I = 20mA
RHOT
ISL9502 Gate Driver Timing Diagram
PWM
tPDHU
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tPDHL
Functional Pin Description
PGOOD - Power good open-drain output. Will be pulled up
externally by a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
SET3 - Low load current indicator input. When asserted low,
indicates a reduced load-current condition, and product goes
into single phase operation.
OCSET - Over-current set input. A resistor from this pin to
VO sets DROOP voltage limit for OC trip. A 10µA current
source is connected internally to this pin.
VW - A resistor from this pin to COMP programs the
switching frequency (exa. 4.42kΩ ≅ 300kHz).
COMP - This pin is the output of the error amplifier.
VDD - 5V control power supply.
FB - This pin is the inverting input of error amplifier.
RBIAS - 147kΩ resistor to GND sets internal current
reference.
FB2 - There is a switch between FB2 pin and the FB pin.
The switch is closed in single-phase operation and is
opened in two phase operation. The components connecting
to FB2 is to adjust the compensation in single phase
operation to achieve optimum performance if needed.
VRHOT# - Thermal overload output indicator with
open-drain output. Over- temperature pull-down resistance
is 10Ω.
NTC - Thermistor input to VRHOT# circuit and a 60µA
current source is connected internally to this pin.
SOFT - A capacitor from this pin to GND pin sets the
maximum slew rate of the output voltage. The SOFT pin is
the non-inverting input of the error amplifier.
5
VDIFF - This pin is the output of the differential amplifier.
VSEN - Remote core voltage sense input.
RTN - Remote core voltage sense return.
FN9275.1
July 17, 2006
ISL9502
PGND2 - Return path of the lower gate driver for phase 2.
DROOP - Output of the droop amplifier. The voltage level on
this pin is the sum of Vo and the programmed droop voltage
by the external resistors.
LGATE2 - Lower-side MOSFET gate signal for phase 2.
PVCC - 5V power supply for gate drivers.
DFB - Inverting input to droop amplifier.
LGATE1 - Lower-side MOSFET gate signal for phase 1.
VO - An input to the IC that reports the local output voltage.
PGND1 - Return path of the lower gate driver for phase 1.
VSUM - This pin is connected to the summing junction for
current sensing.
PHASE1 - Channel-1 phase. This pin should connect to the
source of upper MOSFET.
VIN - Supply voltage. It is used for input voltage feedforward
to improve the input line transient performance.
UGATE1 - Upper MOSFET gate signal for phase 1.
BOOT1 - Upper gate driver supply voltage for phase 1. An
internal boot strap diode is connected to the PVCC pin.
GND - Signal ground. Connect to local controller ground.
VDD - 5V control power supply.
GND - Signal ground. Connect to local controller ground.
ISEN2 - Individual current sharing sensing for channel 2.
NC - Not connected. Connecting this pin to the ground.
VSEL0, VSEL1, VSEL2, VSEL3, VSEL4, VSEL5 - Voltage
selection input with VSEL0 is the least significant bit (LSB)
and VSEL5 is the most significant bit (MSB).
BOOT2 - Upper gate driver supply voltage for phase 2. An
internal boot strap diode is connected to the PVCC pin.
VR_ON - Digital input enable. A high level logic signal on
this pin enables the regulator.
UGATE2 - Upper MOSFET gate signal for phase 2.
SET1, SET2 - Select power-saving modes.
PHASE2 - Channel-2 phase. This pin should connect to the
source of upper MOSFET.
NC - Not connected.
ISEN1 - Individual current sharing sensing for channel 1.
GND - Signal ground. Connect to local controller ground.
VW
OCSET
SOFT
NTC
VRHOT#
RBIAS
VDD
SET3
PGOOD
9
8
7
6
5
4
3
2
1
COMP 10
FB 11
FB2 12
VDIFF
13
48
GND
VSEN
14
47
NC
RTN
15
46
SET2
DROOP
16
45
SET1
DFB
17
44
VR_ON
VSEL3
GND
40
VSEL2
VDD
39
VSEL1
ISEN2
38
VSEL0
ISEN1
37
42
20
41
43
VIN
24
19
VSEL4
23
VSUM
22
VSEL5
21
VO
18
GND PAD
(BOTTOM)
GND
36 BOOT1
35 UGATE1
34 PHASE1
33 PGND1
32 LGATE1
31 PVCC
30 LGATE2
29 PGND2
28 PHASE2
27 UGATE2
26 BOOT2
25 NC
6
FN9275.1
July 17, 2006
ISL9502
PGND2
LGATE2
PHASE2
UGATE2
BOOT2
PGND1
LGATE1
PHASE1
UGATE1
BOOT1
VRHOT#
NTC
Functional Block Diagram
60µA
PVCC
PVCC
+
PVCC
PVCC
VDD
1.22V
PVCC
PVCC
DRIVER
LOGIC
VIN
VIN
DRIVER
LOGIC
ULTRASONIC
TIMER
FLT
FLT
ISEN2
CURRENT
BALANCE
ISEN1
VSOFT
I_BALF
VIN
GND
VSOFT
VIN
MODULATOR
MODULATOR
OC
OC
CH1
CH2
VW
VDD
PGOOD
Vw
PGOOD
MONITOR
AND LOGIC
CH1
CH2
COMP
Vw
FAULT AND
PGOOD
LOGIC
SINGLE
PHASE
VO
E/A
VIN
FB2
-
+
PHASE
CONTROL
LOGIC
PGOOD
FLT
PHASE
SEQUENCER
FB
SINGLE
PHASE
SOFT
VSOFT
OC
VDIFF
VO
SOFT
+
+
+
+
+
RTN
VO
DROOP
VSEN
VO
DROOP
-
DFB
VSUM
OCSET
+
10µA
SET1
SET2
SET3
VSEL5
VSEL4
VSEL3
VSEL2
VSEL1
VSEL0
1
-
0.5
MODE
CONTROL
DAC
-
1
VR_ON
RBIAS
MODE CHANGE
REQUEST
DACOUT
SINGLE
PHASE
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL9502
7
FN9275.1
July 17, 2006
ISL9502
Typical Performance Curves 300kHz, DCR Sense, 2xIRF7821/2xIRF7832 Per Phase
100
1.16
VIN = 8.0V
VIN = 8.0V
1.14
80
VIN = 12.6V
70
VIN = 19.0V
1.12
60
VOUT (V)
EFFICIENCY (%)
90
50
40
30
VIN = 12.6V
1.10
VIN = 19.0V
1.08
1.06
20
1.04
10
0
0
5
10
15
20
25
30
35
40
45
1.02
50
0
10
20
IOUT (A)
FIGURE 2. 2-PHASE CCM EFFICIENCY, VOUT = 1.15V
40
50
FIGURE 3. 2-PHASE CCM LOAD LINE, VOUT = 1.15V
100
1.16
VIN = 8.0V
90
1.15
80
VIN = 12.6V
70
1.14
VIN = 19.0V
60
VOUT (V)
EFFICIENCY (%)
30
IOUT (A)
50
40
1.13
VIN = 8.0V
VIN = 12.6V
1.12
30
VIN = 19.0V
20
1.11
10
0
0
2
4
6
8
10
12
14
16
18
20
1.10
0
2
4
6
IOUT (A)
8
10
12
14
16
18
20
IOUT (A)
FIGURE 4. 1-PHASE CCM EFFICIENCY, VOUT = 1.15V
FIGURE 5. 1-PHASE CCM LOAD LINE, VOUT = 1.15V
Typical Performance Curves
VOUT
VSOFT
VOUT
VR_ON
VSOFT
VR_ON
CSOFT = 15nF
FIGURE 6. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VSEL = 1V, ILOAD = 10A
8
CSOFT = 15nF
FIGURE 7. SOFT-START WAVEFORM SHOWING SLEW RATE
OF 2.5mV/µs AT VSEL = 1.4375V, ILOAD = 10A
FN9275.1
July 17, 2006
ISL9502
Typical Performance Curves
(Continued)
LINE TRANSIENT
IIN
VIN
VOUT
FIGURE 8. 8V-20V INPUT LINE TRANSIENT RESPONSE,
CIN = 240µF
FIGURE 9. 2 PHASE CURRENT BALANCE, FULL LOAD = 50A
VSEL2
VOUT
VOUT
DYNAMIC VSEL
ACTIVE MODE
LOAD TRANSIENT
PHASE1,
PHASE2
FIGURE 10. LOAD STEP-UP RESPONSE, 35A LOAD STEP @
200A/µs, 2 PHASE CCM
FIGURE 11. VSEL2 CHANGE OF FROM 1.0V TO 1.1V AT
SET1 = 0, SET2 = 1, SET3 = 1
VSEL2
VOUT
VOUT
DYNAMIC VSEL
ACTIVE MODE
LOAD TRANSIENT
FIGURE 12. LOAD DUMP RESPONSE, 35A LOAD STEP @
200A/µs, 2 PHASE CCM
9
PHASE1,
PHASE2
FIGURE 13. VSEL2 CHANGE FROM 1.1V TO 1V AT SET1 = 0,
SET2 = 1, SET3 = 1
FN9275.1
July 17, 2006
ISL9502
Typical Performance Curves
(Continued)
SET3
DROP PHASE IN
CCM MODE
SET3
ADD PHASE IN
CCM MODE
VCORE
VCORE
PHASE1
PHASE1
PHASE2
PHASE2
FIGURE 14. 2-PHASE CCM TO 1-PHASE CCM, AT SET1 = 0,
SET2 = 1, ILOAD = 10A
FIGURE 15. 1-PHASE CCM TO 2-PHASE CCM, AT SET1 = 0,
SET2 = 1
VOUT
PHASE1
PGOOD
PGOOD
VOUT
IL1, IL2
FIGURE 16. OVERCURRENT PROTECTION
FIGURE 17. 1.7V OVERVOLTAGE PROTECTION SHOWS
OUTPUT VOLTAGE PULLED LOW TO 0.9V AND
PWM THREE-STATE
VOUT
IL1, IL2
IIN
FIGURE 18. INRUSH CURRENT AT START-UP, VIN = 8V, VOUT = 1.450V, ILOAD = 10A
10
FN9275.1
July 17, 2006
ISL9502
Simplified Application Circuit for DCR Current Sensing
V +5
VIN
R12
VDD PVCC VIN
VIN
RBIAS
NTC
C7
R13
VRHOT#
C8
VSEL
UGATE1
BOOT1
SOFT
LO
C6
VSELs
PHASE1
R10
SET2
CL
RL
ISL9502
LGATE1
ISEN1
SET1
VO'
R8
PGND2
SET3
VO
VSUM
ISEN1
CO
VIN
VR_ON
VR_ON
C8
PGOOD
GPUGOOD
VSEN
REMOTE
SENSE
UGATE2
RTN
C5
VDIFF
R3
LO
BOOT2
R2
PHASE2
C3
R11
RL
LGATE2
FB
C1
R9
PGND2
R1
ISEN2
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
R6
R4
C4
RN
NTC
NETWORK
CCS
VO'
FIGURE 19. ISL9502 BASED TWO-PHASE BUCK CONVERTER WITH INDUCTOR DCR CURRENT SENSING
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FN9275.1
July 17, 2006
ISL9502
Simplified Application Circuit for Resistive Current Sensing
V +5
VIN
R11
VDD PVCC VIN
VIN
RBIAS
NTC
C7
R12
VRHOT#
C9
VSEL
UGATE1
BOOT1
SOFT
L
RS
C6
VSELs
PHASE1
R10
SET2
SET2
ISL9502
SET1
LGATE1
ISEN1
SET1
VO'
R8
PGND2
SET3
CL
RL
SET3
VO
VSUM
ISEN1
CO
VIN
VR_ON
VR_ON
C8
PGOOD
GPUGOOD
VSEN
REMOTE
SENSE
UGATE2
RTN
RS
C5
VDIFF
R3
L
BOOT2
R2
PHASE2
C3
R11
RL
LGATE2
FB
C1
R9
PGND2
R1
ISEN2
CL
VO'
VSUM
COMP
ISEN2
C2
RFSET
VSUM
VSUM
VW
OCSET
C9
GND
DFB
DROOP VO
R5
CHF
R6
R4
C4
VO'
FIGURE 20. ISL9502 BASED TWO-PHASE BUCK CONVERTER WITH RESISTIVE CURRENT SENSING
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FN9275.1
July 17, 2006
ISL9502
Theory of Operation
The ISL9502 is a two-phase regulator including embedded
gate drivers for reduced system cost and board area. The
regulator provides optimum steady-state and transient
performance for GPU applications up to 60A. System
efficiency is enhanced by idling a phase at low-current and
implementing DCM-mode operation.
The heart of the ISL9502 is the patented R3 (Robust Ripple
Regulator®) modulator. The R3® modulator combines the
best features of fixed frequency PWM and hysteretic PWM
while eliminating many of their shortcomings. The ISL9502
modulator internally synthesizes an analog of the inductor
ripple current and uses hysteretic comparators on those
signals to establish PWM pulse widths. Operating on these
large-amplitude, noise-free synthesized signals allows the
ISL9502 to achieve lower output ripple and lower phase jitter
than either conventional hysteretic or fixed frequency PWM
controllers. Unlike conventional hysteretic converters, the
ISL9502 has an error amplifier that allows the controller to
maintain a 0.5% voltage regulation accuracy throughout the
VSEL range from 0.7V to 1.5V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients results in
increased switching frequency, which gives the R3 regulator
a faster response than conventional fixed frequency PWM
controllers. Transient load current is inherently shared
between active phases due to the use of a common
hysteretic window voltage. Individual average phase
voltages are monitored and controlled to equally share the
static current among the active phases.
VDD
10mV/µs
VR_ON
2mV/µs
VBOOT
100µs
VSEL COMMANDED
VOLTAGE
SOFT & VO
6.8ms
PGOOD
FIGURE 21. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
Static Operation
After the start sequence, the output voltage will be regulated
to the value set by the VSEL inputs per Table 1. The
ISL9502 will control the no-load output voltage to an
accuracy of ±0.5% over the range of 0.75V to 1.5V. The
input of VSELs has to be actively pulled to logic high or logic
low. Floating VSEL pins will leave logic-level vulnerable to
noise-coupling.
TABLE 1. VSEL TABLE
VSEL
VOUT
VSEL
VOUT
000000
1.500
010101
0.975
000001
1.475
010110
0.950
000010
1.450
010111
0.925
000011
1.425
011000
0.900
000100
1.400
011001
0.875
Start-Up Timing
000101
1.375
011010
0.850
With the controller's +5V VDD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. Approximately
100µs later, SOFT and VOUT begin ramping to the boot
voltage of 1.2V. At startup, the regulator always operates in a
2-phase CCM mode, regardless of control signal assertion
levels. During this internal, the SOFT cap is charged by
40µA current source. If the SOFT capacitor is selected to be
20nF, the SOFT ramp will be at 2mV/s for a soft-start time of
600s. Approximately 7ms later, PGOOD is asserted HIGH.
The entire soft-start event is illustrated in Figure 21.
000110
1.350
011011
0.825
000111
1.325
011100
0.800
001000
1.300
011101
0.775
001001
1.275
011110
0.750
001010
1.250
011111
0.725
001011
1.225
100000
0.700
001100
1.200
100001
0.675
001101
1.175
100010
0.650
001110
1.150
100011
0.625
001111
1.125
100100
0.600
010000
1.100
100101
0.575
010001
1.075
100110
0.550
010010
1.050
100111
0.525
010011
1.025
101000
0.500
010100
1.000
The ISL9502 is designed to always start up in 2-phase
mode, then switch to the desired state as dictated by the
states of the pins in Table 2. If a 1-phase design is
implemented, the second phase will try to switch during
start-up even though it is not connected to the system. This
will not affect the start-up performance. After soft-start is
complete, phase 2 will shut down and the controller will run
continuously in 1-phase mode.
A fully-differential amplifier implements core voltage sensing
for precise voltage control at the remote-sense point. The
inputs to the amplifier are the VSEN and RTN pins.
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July 17, 2006
ISL9502
As the load current increases from zero, the output voltage
will droop from the VSEL table value by an amount
proportional to current to achieve active voltage positioning.
The ISL9502 provides for current to be measured using
either resistors in series with the channel inductors as shown
in the application circuit of Figure 2 or using the intrinsic
series resistance of the inductors as shown in the application
circuit of Figure 3. In both cases signals representing the
inductor currents are summed at VSUM, which is the noninverting input to the DROOP amplifier shown in the block
diagram of Figure 1. The voltage at the DROOP pin minus
the output voltage, VO´, is a high-bandwidth analog of the
total inductor current. This voltage is used as an input to a
differential amplifier to achieve active voltage positioning.
This is also the input to the over-current protection circuit.
When using inductor DCR current sensing, a single NTC
element is used to compensate the positive temperature
coefficient of the copper winding, thus maintaining active
voltage positioning.
In addition to monitoring the total current (used for DROOP
and over-current protection), the individual channel average
currents are monitored and used for balancing the load
between channels. The IBAL circuit will adjust the channel
pulse-widths up or down relative to the other channel to
cause the voltages presented at the ISEN pins to be equal.
The ISL9502 controller can be configured for two-channel
operation, with the channels operating 180° apart. The
channel PWM frequency is determined by the value of
RFSET connected to pin VW as shown in Figure 2 and
Figure 3. Input and output ripple frequencies will be the
channel PWM frequency multiplied by the number of active
channels.
High Efficiency Operation Mode
The ISL9502 has several operating modes to optimize
efficiency. These operating modes are established by the
control signal inputs SET1, SET2, and SET3 as shown in
Table 2. At high current levels, the system can operate with
both phases fully active, responding rapidly to transients and
deliver the maximum power to the load. At reduced load
current levels, one of the phases can be idled. This
configuration will minimize switching losses, while still
maintaining transient response capability. At the lowest
current levels, the controller can be configured to operate in
single-phase DCM mode, thus achieving the highest
possible efficiency. In this mode of operation, the lower FET
will be configured to automatically detect and prevent
discharge current flowing from the output capacitor through
the inductors, and the switching frequency will be
proportionately reduced, thus greatly reducing both
conduction and switching losses.
Smooth mode transitions are facilitated by the R3
Technology™, which correctly maintains the internally
synthesized ripple currents throughout mode transitions. The
controller is thus able to deliver the appropriate current to the
load throughout mode transitions. The controller contains
embedded mode-transition algorithms which robustly
maintain voltage-regulation for all control signal input
sequences and durations.
Timing of the mode transitions of ISL9502 has been carefully
designed to work in concert with VSEL changes to minimize
any perturbations to the output voltage. For example,
transitions into single-phase mode will be delayed until any
VSEL induced voltage ramp is complete to allow the
associated output capacitor charging current to be shared by
both inductor paths. While in single-phase automatic-DCM
mode, VSEL changes will initiate an immediate return to
two-phase CCM mode. This ensures that both inductor
paths share the output capacitor charging current and are
fully active for the subsequent load current increases.
The controller contains internal counters which prevent
spurious control signal glitches from resulting in unwanted
mode transitions. Control signals of less than two switching
periods do not result in phase-idling. Signals of less than 7
switching periods do not result in implementation of DCM
mode.
TABLE 2. CONTROL SIGNAL TRUTH TABLES FOR OPERATION MODES OF ISL9502
SET1
SET2
SET3
PHASE OPERATION MODES
0
0
0
1-phase CCM
0
0
1
2-phase CCM
0
1
0
1-phase CCM
0
1
1
2-phase CCM
1
0
0
1-phase diode emulation
1
0
1
1-phase diode emulation
1
1
0
1-phase CCM
1
1
1
2-phase CCM
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July 17, 2006
ISL9502
While transitioning to single-phase operation, the controller
smoothly transitions current from the idling-phase to the
active-phase, and detects the idling-phase zero-current
condition. During transitions into DCM or CCM mode, the
timing is carefully adjusted to eliminate output voltage
excursions. When a phase is added, the current balance
between phases is quickly restored.
While SET3 is high, both phases are switching. If SET3 is
asserted low and either SET2 or SET1 are not asserted, the
controller will transition to CCM operation with only phase 1
switching, and both FET's of phase 2 will be off. The
controller will thus eliminate switching losses associated with
the unneeded channel.
When SET3, SET2, and SET1 are all asserted, the controller
will transition to single-phase DCM mode. In this mode, both
FET's associated with phase 2 will be off, and the ISL9502
will turn-off the lower FET of channel 1 whenever the
channel 1 current decays to zero. As load is further reduced,
the phase 1 channel switching frequency will decrease, thus
maintaining high efficiency.
Protection
The ISL9502 provides overcurrent, overvoltage, undervoltage protection and over-temperature protection as
shown in Table 3.
Overcurrent protection is tied to the voltage droop which is
determined by the resistors selected as described in the
“Component Selection and Application” section. Once a
load-line is selected, large or small, a corresponding
overcurrent set resistor can be chosen. An overcurrent fault
will occur when the load current exceeds the overcurrent
setpoint voltage while the regulator is in a 2-phase mode.
While the regulator is in a 1-phase mode of operation, the
overcurrent setpoint is automatically reduced by half. For
overcurrents less than twice the OCSET level, the over-load
condition must exist for 120µs in order to trip the OC fault
latch. This is shown in Figure 16.
For over-loads exceeding twice the set level, the PWM
outputs will immediately shut off and PGOOD will go low to
maximize protection due to hard shorts.
In addition, excessive phase imbalance, due to gate driver
failure for example, will be detected in two-phase operation
and the controller will be shut-down one millisecond after the
imbalance is detected. A phase current mismatch is
detected when the voltage measured between the ISEN pins
is greater than 7.5mV.
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than VSEL - 300mV for one
millisecond, a fault will be detected and the IC will latch off.
The PWM outputs will turn off and PGOOD will go low. Note
that most practical core regulators will have the overcurrent
set to trip before the -300mV undervoltage limit.
There are two levels of overvoltage protection and response.
For output voltage exceeding the set value by +200mV for
one millisecond, a fault is declared. All of the above faults
have the same action taken; PGOOD is latched low and the
upper and lower power FETs are turned off so that inductor
current will decay through the FET body diodes. This
condition can be reset by bringing VR_ON low or by bringing
VDD below 4V. When these inputs are returned to their high
operating levels, a soft-start will occur.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL9502
FAULT DURATION PRIOR
TO PROTECTION
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120µs
PWM1, PWM2 three-state,
PGOOD latched low
VR_ON toggle or VDD toggle
Severe-Overcurrent fault
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