ISLA112P50IRZ

DATASHEET ISLA112P50 FN7604 Rev.3.0 Jul 6, 2021 12-Bit, 500MSPS A/D Converter The ISLA112P50 is a low-power, high-performance, 500MSPS analog-to-digital converter designed with Renesas’ proprietary FemtoCharge™ technology on a standard CMOS process. The ISLA112P50 is part of a pin-compatible portfolio of 8, 10 and 12-bit A/Ds. This device an upgrade of the KAD551XP-50 product family and is pin similar. The device utilizes two time-interleaved 250MSPS unit A/Ds to achieve the ultimate sample rate of 500MSPS. A single 500MHz conversion clock is presented to the converter, and all interleave clocking is managed internally. The proprietary Interleave Engine (I2E) performs automatic fine correction of offset, gain, and sample time skew mismatches between the unit A/Ds to optimize performance. No external interleaving algorithm is required. A serial peripheral interface (SPI) port allows for extensive configurability of the A/D. The SPI also controls the interleave correction circuitry, allowing the system to issue continuous calibration commands as well as configure many dynamic parameters. CLKP • 90fs Clock Jitter • Automatic Fine Interleave Correction Calibration • Multiple Chip Time Alignment Support via the Synchronous Clock Divider Reset • Programmable Gain, Offset and Skew Control • Over-Range Indicator • Clock Phase Selection • Nap and Sleep Modes • Two’s Complement, Gray Code or Binary Data Format • DDR LVDS-Compatible or LVCMOS Outputs • Programmable Test Patterns and Internal Temperature Sensor Applications • Radar and Electronic/Signal Intelligence • Broadband Communications • High-Performance Data Acquisition OVDD CLOCK MANAGEMENT CLKN • 1.15GHz Analog Input Bandwidth TABLE 1. PIN-COMPATIBLE FAMILY CLKDIVRSTN AV DD CLKDIVRSTP Digital output data is presented in selectable LVDS or CMOS formats. The ISLA112P50 is available in a 72 Ld QFN package with an exposed paddle. Performance is specified over the full industrial temperature range (-40°C to +85°C). Features MODEL RESOLUTION SPEED (MSPS) ISLA112P50 12 500 CLKOUTP ISLA110P50 10 500 CLKOUTN ISLA118P50 8 500 Key Specifications 12 - BIT 250 MSPS ADC SHA D[11:0]P VREF DIGITAL VINP Gain/Offset/Skew Adjustments VINN ERROR I2 E • SNR = 65.8dBFS for fIN = 190MHz (-1dBFS) D[11:0]N • SFDR = 80dBc for fIN = 190MHz (-1dBFS) ORP • Total Power Consumption = 455mW ORN CORRECTION OUTFMT OUTMODE 12 - BIT 250 MSPS ADC VCM SHA VREF + – SDO OGND S DIO CS B SCLK SPI CONTROL RESETN AGND NAPSLP 1.25V FIGURE 1. BLOCK DIAGRAM FN7604 Rev.3.0 Jul 6, 2021 Page 1 of 33 © 2010 Renesas Electronics ISLA112P50 Table of Contents Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .10 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Over-Range Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I2E Requirements and Restrictions . . . . . . . . . . . . . . . . . . .18 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Active Run State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Nyquist Zones. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Configurability and Communication . . . . . . . . . . . . . . . . . . . . 19 Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . .20 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . .22 SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Indexed Device Configuration/Control . . . . . . . . . . . . . . . . . . 23 AC RMS Power Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Address 0x60-0x64: I2E initialization . . . . . . . . . . . . . . . . . . . 25 Device Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 A/D Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . 31 Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FN7604 Rev.3.0 Jul 6, 2021 Page 2 of 33 ISLA112P50 Ordering Information PART NUMBER (Notes 1, 2) PART MARKING ISLA112P50IRZ SPEED (MSPS) PACKAGE DESCRIPTION (RoHS Compliant) PKG. DWG. # CARRIER TYPE TEMP. RANGE 500 72 Ld QFN L72.10x10J Tray -40 to +85°C ISLA112P50 IRZ NOTES: 1. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA112P50. For more information about MSL, see TB363. Pin Configuration AVSS AVDD OUTFMT SDIO SCLK CSB SDO OVSS ORP ORN D11P D11N D10P D10N D9P D9N OVDD OVSS (72 LD QFN) TOP VIEW 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD 1 54 D8P DNC 2 53 D8N RES 3 52 D7P RES 4 51 D7N DNC 5 50 D6P AVDD 6 49 D6N AVSS 7 48 CLKOUTP AVSS 8 47 CLKOUTN VINN 9 46 RLVDS PD r VINP 10 AVSS 11 AVDD 12 DNC 13 DNC 14 al i t n e d nfi VCM 15 DNC 16 DNC 17 45 OVSS 44 D5P on i t ma r o Inf 43 D5N 42 D4P 41 D4N 40 D3P 39 D3N 38 D2P CONNECT THERMAL PAD TO AVSS 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CLKP CLKN OUTMODE NAPSLP AVDD RESETN OVSS OVDD CLKDIVRSTP CLKDIVRSTN DNC DNC D0N D0P D1N D1P OVDD 37 D2N AVDD DNC 18 FIGURE 2. PIN CONFIGURATION FN7604 Rev.3.0 Jul 6, 2021 Page 3 of 33 ISLA112P50 Pin Descriptions PIN NUMBER LVDS [LVCMOS] NAME LVDS [LVCMOS] FUNCTION 1, 6, 12, 19, 24, 71 AVDD 1.8V Analog Supply 2, 5, 13, 14, 16, 17, 18, 30, 31 DNC Do Not Connect 3, 4 RES Reserved. (4.7k pull-up to OVDD is required for each of these pins) 7, 8, 11, 72 AVSS Analog Ground 9, 10 VINN, VINP 15 VCM 20, 21 CLKP, CLKN 22 OUTMODE 23 NAPSLP Tri-Level Power Control (Nap, Sleep modes) 25 RESETN Power On Reset (Active Low) 26, 45, 55, 65 OVSS Output Ground 27, 36, 56 OVDD 1.8V Output Supply 28, 29 CLKDIVRSTP, CLKDIVRSTN 32, 33 D0N, D0P [NC, D0] LVDS Bit 0 (LSB) Output Complement, True [NC, LVCMOS Bit 0] 34, 35 D1N, D1P [NC, D1] LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1] 37, 38 D2N, D2P [NC, D2] LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2] 39, 40 D3N, D3P [NC, D3] LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3] 41, 42 D4N, D4P [NC, D4] LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4] 43, 44 D5N, D5P [NC, D5] LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5] 46 RLVDS 47, 48 CLKOUTN, CLKOUTP [NC, CLKOUT] LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT] 49, 50 D6N, D6P [NC, D6] LVDS Bit 6 Output Complement, True [NC, LVCMOS Bit 6] 51, 52 D7N, D7P [NC, D7] LVDS Bit 7 Output Complement, True [NC, LVCMOS Bit 7] 53, 54 D8N, D8P [NC, D8] LVDS Bit 8 Output Complement, True [NC, LVCMOS Bit 8] 57, 58 D9N, D9P [NC, D9] LVDS Bit 9 Output Complement, True [NC, LVCMOS Bit 9] 59, 60 D10N, D10P [NC, D10] LVDS Bit 10 Output Complement, True [NC, LVCMOS Bit 10] 61, 62 D11N, D11P [NC, D11] LVDS Bit 11(MSB) Output Complement, True [NC, LVCMOS Bit 11] 63, 64 ORN, ORP [NC, OR] 66 SDO SPI Serial Data Output (4.7k pull-up to OVDD is required) 67 CSB SPI Chip Select (active low) 68 SCLK SPI Clock 69 SDIO SPI Serial Data Input/Output 70 OUTFMT PD AVSS Analog Input Negative, Positive Common Mode Output Clock Input True, Complement Tri-Level Output Mode (LVDS, LVCMOS) Sample Clock Synchronous Divider Reset Positive, Negative LVDS Bias Resistor (connect to OVSS with a 10k, 1% resistor) LVDS Over-Range Complement, True [NC, LVCMOS Over-Range] Tri-Level Output Data Format (Two’s Comp., Gray Code, Offset Binary) Exposed Paddle. Analog Ground NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection) FN7604 Rev.3.0 Jul 6, 2021 Page 4 of 33 ISLA112P50 Absolute Maximum Ratings Thermal Information AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 72 Ld QFN (Notes 3, 4, 5) . . . . . . . . . . . . . . 23 0.75 Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See TB379 for details. 4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 5. For solder stencil layout and reflow guidelines, please see TB389. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, FIN = 105MHz, fSAMPLE = 500MSPS, after completion of I2E calibration. ISLA112P50 (Note 6) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.41 1.45 1.52 VP-P DC SPECIFICATIONS (Note 6) Analog Input Full-Scale Analog Input Range VFS Differential Input Resistance RIN Differential CIN Differential 1.9 pF Full Temp 325 ppm/°C Input Capacitance Full Scale Range Temp. Drift AVTC Input Offset Voltage VOS Gain Error Common-Mode Output Voltage  500 -10 EG ±2.0 10 mV 635 mV ±2.0 VCM % 435 535 0.9 V 0.2 1.8 V Clock Inputs Inputs Common Mode Voltage CLKP, CLKN Input Swing Power Requirements 1.8V Analog Supply Voltage AVDD 1.7 1.8 1.9 V 1.8V Digital Supply Voltage OVDD 1.7 1.8 1.9 V 1.8V Analog Supply Current IAVDD 173 186 mA 1.8V Digital Supply Current (Note 7) IOVDD 3mA LVDS, I2E powered down, Notch Filter powered down 87 94 mA 3mA LVDS, I2E On, Notch Filter On 132 mA Power Supply Rejection Ratio PSRR 30MHz, 200mVP-P -36 dB 2mA LVDS, I2E powered down, Notch Filter powered down 455 mW 3mA LVDS, I2E powered down, Notch Filter powered down 468 3mA LVDS, I2E On, Notch Filter powered down 535 mW 3mA LVDS, I2E On, Notch Filter On 549 mW Total Power Dissipation Normal Mode Nap Mode FN7604 Rev.3.0 Jul 6, 2021 PD PD 164 504 179 mW mW Page 5 of 33 ISLA112P50 Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, FIN = 105MHz, fSAMPLE = 500MSPS, after completion of I2E calibration. (Continued) ISLA112P50 (Note 6) PARAMETER Sleep Mode SYMBOL CONDITIONS MIN PD TYP MAX UNITS 28 34 mW Nap Mode Wakeup Time (Note 8) Sample Clock Running 2.75 µs Sleep Mode Wakeup Time (Note 8) Sample Clock Running 1 ms AC SPECIFICATIONS (Note 9) Differential Nonlinearity Integral Nonlinearity DNL -0.8 ±0.3 0.8 INL -2.0 ±0.8 2.0 LSB 80 MSPS Minimum Conversion Rate (Note 10) fS MIN Maximum Conversion Rate fS MAX Signal-to-Noise Ratio (Notes 11, 12) SNR 500 fIN = 10MHz SINAD dBFS 65.9 dBFS fIN = 190MHz 65.8 dBFS fIN = 364MHz 65.2 dBFS fIN = 495MHz 64.9 dBFS fIN = 605MHz 64.4 dBFS fIN = 995MHz 62.6 dBFS ENOB 65.9 dBFS 65.9 dBFS fIN = 190MHz 65.5 dBFS fIN = 364MHz 64.9 dBFS fIN = 495MHz 63.7 dBFS fIN = 605MHz 60.8 dBFS fIN = 995MHz 48.8 dBFS fIN = 10MHz 10.65 Bits fIN = 105MHz Spurious-Free Dynamic Range (Notes 11, 12) SFDR 63.9 fIN = 10MHz fIN = 105MHz Effective Number of Bits (Notes 11, 12) MSPS 65.9 fIN = 105MHz Signal-to-Noise and Distortion (Notes 11, 12) LSB 63.1 10.65 Bits fIN = 190MHz 10.20 10.59 Bits fIN = 364MHz 10.48 Bits fIN = 495MHz 10.29 Bits fIN = 605MHz 9.81 Bits fIN = 995MHz 7.82 Bits fIN = 10MHz 84 dBc 86 dBc fIN = 190MHz 80 dBc fIN = 364MHz 78 dBc fIN = 495MHz 71 dBc fIN = 605MHz 64 dBc fIN = 995MHz 49 dBc fIN = 70MHz 89 dBc 87 dBc fIN = 105MHz 70.0 Intermodulation Distortion IMD Word Error Rate WER 10-12 Full Power Bandwidth FPBW 1.15 fIN = 170MHz GHz I2E SPECIFICATIONS FN7604 Rev.3.0 Jul 6, 2021 Page 6 of 33 ISLA112P50 Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, FIN = 105MHz, fSAMPLE = 500MSPS, after completion of I2E calibration. (Continued) ISLA112P50 (Note 6) PARAMETER SYMBOL Offset Mismatch-Induced Spurious Power I2E Settling Times Minimum Duration of Valid Analog Input (Note 13) CONDITIONS MIN TYP MAX UNITS No I2E Calibration performed -70 dBFS Active Run state enabled -81 dBFS I2Epost_t Calibration settling time for Active Run state 1000 ms tTE Allow one I2E iteration of Offset, Gain and Phase correction 500 µs Largest Interleave Spur Total Interleave Spurious Power Sample Time Mismatch Between Unit A/Ds fIN = 10MHz to 240MHz, Active Run State enabled, in Track Mode -94 dBc fIN = 10MHz to 240MHz, Active Run State enabled and previously settled, in Hold Mode -82 dBc fIN = 260MHz to 490MHz, Active Run State enabled, in Track Mode -89 dBc fIN = 260MHz to 490MHz, Active Run State enabled and previously settled, in Hold Mode -79 dBc Active Run State enabled, in Track Mode, fIN is a broadband signal in the 1st Nyquist zone -90 dBc Active Run State enabled, in Track Mode, fIN is a broadband signal in the 2nd Nyquist zone -85 dBc 30 fs Gain Mismatch Between Unit A/Ds Active Run State enabled, in Track Mode 0.01 % Offset Mismatch Between Unit A/Ds 1 mV NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output. 8. See “Nap/Sleep” for more detail. 9. AC Specifications apply after internal calibration of the A/D is invoked at the given sample rate and temperature. Refer to “Power-On Calibration” and “User Initiated Reset” for more detail. 10. The DLL Range setting must be changed for low speed operation. 11. The offset mismatch-induced spur energy, which occurs at fSAMPLE/2, is not included in any specification unless otherwise noted. 12. This specification only applies when I2E is in Active Run state, and in Track Mode. 13. Limits are specified over the full operating temperature and voltage range and are established by characterization and not production tested. Digital Specifications PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0 1 10 µA -25 -12 -5 µA CMOS INPUTS Input Current High (SDIO, RESETN, CSB, SCLK) IIH VIN = 1.8V Input Current Low (SDIO, RESETN, CSB, SCLK) IIL VIN = 0V Input Voltage High (SDIO, RESETN, CSB, SCLK) VIH Input Voltage Low (SDIO, RESETN, CSB, SCLK) VIL FN7604 Rev.3.0 Jul 6, 2021 1.17 V 0.63 V Page 7 of 33 ISLA112P50 Digital Specifications (Continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Current High (OUTMODE, NAPSLP, OUTFMT) (Note 14) IIH 15 25 40 µA Input Current Low (OUTMODE, NAPSLP, OUTFMT) IIL -40 25 -15 µA Input Capacitance CDI 3 pF LVDS INPUTS (ClkdivrstP, ClkdivrstN) Input Common Mode Range VICM 825 1575 mV Input Differential Swing (peak to peak, single ended) VID 250 450 mV Input Pull-up and Pull-down Resistance RIpu 1 M 620 mVP-P LVDS OUTPUTS Differential Output Voltage (Note 15) Output Offset Voltage VT 3mA Mode VOS_LVDS 3mA Mode 950 965 980 mV Output Rise Time tR 625 ps Output Fall Time tF 625 ps OVDD - 0.1 V CMOS OUTPUTS Voltage Output High VOH IOH = -500µA Voltage Output Low VOL IOL = 1mA OVDD - 0.3 0.1 0.3 V Output Rise Time tR 2 ns Output Fall Time tF 2 ns Timing Diagrams SAMPLE N SAMPLE N INP INP INN INN tA tA CLKN CLKP CLKN CLKP LATENCY t CPD = L CYCLES LATENCY t CPD CLKOUTN CLKOUTP = L CYCLES CLKOUTN CLKOUTP tDC t DC tPD D[11:0]P t PD DATA N-L D[11:0]N DATA N-L+1 DATA N-L+2 FIGURE 3. LVDS TIMING DIAGRAM FN7604 Rev.3.0 Jul 6, 2021 DATA N D[11:0]P D[11:0]N DATA N-L DATA N-L+1 DATA N-L+2 DATA N FIGURE 4. CMOS TIMING DIAGRAM Page 8 of 33 ISLA112P50 Switching Specifications PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS A/D OUTPUT Aperture Delay tA 375 ps RMS Aperture Jitter jA 90 fs Input Clock to Output Clock Propagation Delay AVDD, OVDD = 1.8V, TA = +25°C tCPD 2.6 2.9 3.3 ns AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C tCPD 2.0 2.6 3.6 ns Relative Input Clock to Output Clock Propagation Delay Matching (Note 16) AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C dtCPD -450 450 ps tPD 1.74 2.6 3.83 ns 250 Input Clock to Data Propagation Delay, LVDS Mode Output Clock to Data Propagation Delay tDC -250 0 Synchronous Clock Divider Reset Setup Time (with respect to the positive edge of CLKP) tRSTS 300 75 ps Synchronous Clock Divider Reset Hold Time (with respect to the positive edge of CLKP) tRSTH 450 150 ps Synchronous Clock Divider Reset Recovery Time LVDS or CMOS Mode DLL recovery time after Synchronous Reset tRSTRT Latency (Pipeline Delay) (Note 17) Overvoltage Recovery 52 ps µs L 17 cycles tOVR 1 cycles SPI INTERFACE (Notes 18, 19) SCLK Period CSBto SCLK Setup Time Write Operation t CLK 32 cycles (Note 18) Read Operation tCLK 132 cycles tS 2 cycles Read or Write CSBafter SCLK Hold Time Read or Write tH 11 cycles Data Valid to SCLK Setup Time Write tDSW 2 cycles Data Valid after SCLK Hold Time Write tDHW 8 cycles Data Valid after SCLK Time Read tDVR Data Invalid after SCLK Time Read tDHR 6 cycles Sleep Mode CSBto SCLK Setup Time (Note 20) Read or Write in Sleep Mode tS 150 µs 33 cycles NOTES: 14. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 15. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing. 16. The relative propagation delay is the timing of the output clock of any A/D with respect to the nominal timing of any other A/D, given that all devices are clocked at the same time and are matched in temperature and voltage. It is specified over the full operating temperature and voltage range, and is established by characterization and not production tested. 17. The pipeline latency of this converter is fixed. 18. SPI Interface timing is directly proportional to the A/D sample period (tSAMPLE). 19. The SPI may operate asynchronously with respect to the A/D sample clock. 20. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup time (4ns min). FN7604 Rev.3.0 Jul 6, 2021 Page 9 of 33 ISLA112P50 Typical Performance Curves 90 85 80 75 70 65 60 55 50 45 40 0M HARMONIC MAGNITUDE (dBc) SNR (dBFS) AND SFDR (dBc) All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. SFDR SNR 200M 400M 600M 800M 1G -40 -50 HD3 -60 HD2 -70 -80 -90 -100 0M 200M 400M INPUT FREQUENCY (Hz) HD2 (dBc) 90 SFDR (dBFS) SNR (dBFS) SNR AND SFDR SNR AND SFDR -60 60 SFDR (dBc) 50 SNR (dBc) 40 -70 -80 HD3 (dBc) -90 HD2 (dBFS) -100 30 20 -40 -35 -30 -25 -20 -15 -10 -5 -110 -40 0 HD3 (dBFS) -35 -30 -20 -15 -10 -5 0 FIGURE 8. HD2 AND HD3 vs AIN FIGURE 7. SNR AND SFDR vs AIN 95 100 90 90 HD2 SFDR HD3 85 80 80 dBc SNR (dBFS) AND SFDR (dBc) -25 INPUT AMPLITUDE (dBFS) INPUT AMPLITUDE (dBFS) 75 70 60 70 50 65 60 250 1G -50 100 70 800M FIGURE 6. HD2 AND HD3 vs f IN FIGURE 5. SNR AND SFDR vs fIN 80 600M INPUT FREQUENCY (Hz) SNR 300 350 400 450 SAMPLE RATE (MSPS) FIGURE 9. SNR AND SFDR vs fSAMPLE FN7604 Rev.3.0 Jul 6, 2021 500 40 250 300 350 400 450 SAMPLE RATE (MSPS) FIGURE 10. HD2 AND HD3 vs fSAMPLE Page 10 of 33 500 ISLA112P50 Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued) 0.6 0.4 500 DNL (LSBs) TOTAL POWER (mW) 550 450 400 350 0.2 0 -0.2 -0.4 300 250M 300M 350M 400M 450M -0.6 500M 0 500 1000 1500 2000 SAMPLE RATE (Hz) 2500 3000 3500 4000 CODE FIGURE 11. POWER vs fSAMPLE IN 3mA LVDS MODE FIGURE 12. DIFFERENTIAL NONLINEARITY 90 0.6 SNRFS (dBFS) AND SFDR (dBc) SFDR 0.4 INL (LSBs) 0.2 0 -0.2 -0.4 -0.6 0 500 1000 1500 2000 2500 3000 3500 85 80 75 70 SNR 65 60 300 4000 350 400 CODE 450 500 550 600 FIGURE 13. INTEGRAL NONLINEARITY AMPLITUDE (dBFS) NUMBER OF HITS 5M 4M 2570000 2M 1420000 800 -30 -50 -70 -90 1M 0 750 AIN = -1.0dBFS SNR = 66.01dBFS SFDR = 84.70dBc SINAD = 65.95dBFS -10 5820000 3M 700 FIGURE 14. SNR AND SFDR vs VCM 7M 6M 650 VCM (mV) 2 2054 1853 151133 2055 2056 2057 2058 2059 42073 171 0 2060 2061 2062 CODE FIGURE 15. NOISE HISTOGRAM FN7604 Rev.3.0 Jul 6, 2021 -110 0M 50M 100M 150M 200M 250M FREQUENCY (Hz) FIGURE 16. SINGLE-TONE SPECTRUM @ 105MHz Page 11 of 33 ISLA112P50 Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued) AIN = -1.0dBFS SNR = 65.80dBFS SFDR = 81.85dBc SINAD = 65.65dBFS -30 -50 -70 -90 -110 0M 50M AIN = -1.0dBFS SNR = 64.72dBFS SFDR = 70.55dBc SINAD = 63.78dBFS -10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -10 100M 150M 200M -30 -50 -70 -90 -110 0M 250M 50M FREQUENCY (Hz) 100M 150M FIGURE 18. SINGLE-TONE SPECTRUM @ 495MHz 0 AIN = -1.0dBFS SNR = 62.10dBFS SFDR = 49.21dBc SINAD = 49.67dBFS IMD = 88.9dBc -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -30 -50 -70 -90 -40 -60 -80 -100 -110 0M 50M 100M 150M 200M -120 0M 250M 50M 100M 150M 200M 250M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 20. TWO-TONE SPECTRUM @ 70MHz (1MHz SPACING) FIGURE 19. SINGLE-TONE SPECTRUM @ 995MHz 90 0 SNRFS (dBFS) AND SFDR (dBc) IMD = 90.2dBc -20 AMPLITUDE (dBFS) 250M FREQUENCY (Hz) FIGURE 17. SINGLE-TONE SPECTRUM @ 190MHz -10 200M -40 -60 -80 -100 -120 0M 50M 100M 150M 200M 250M FREQUENCY (Hz) FIGURE 21. TWO-TONE SPECTRUM @ 170MHz (1MHz SPACING) FN7604 Rev.3.0 Jul 6, 2021 SFDR 85 80 75 70 65 SNR 60 55 50 45 40 0M 50M 100M 150M 200M 250M FREQUENCY (Hz) FIGURE 22. INPUT FREQUENCY SWEEP WITH I2E FROZEN, I2E PREVIOUSLY CALIBRATED @ 105MHz Page 12 of 33 ISLA112P50 Typical Performance Curves 80 78 76 74 72 70 68 66 64 62 60 250M SNRFS (dBFS) AND SFDR (dBc) SNRFS (dBFS) AND SFDR (dBc) All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued) SFDR SNR 300M 350M 400M 450M 500M 85 SFDR 80 75 70 65 SNR 60 -40 -20 FREQUENCY (Hz) 0 20 40 60 TEMPERATURE (°C) FIGURE 23. INPUT FREQUENCY SWEEP WITH I2E FROZEN, I2E PREVIOUSLY CALIBRATED @ 330MHz FIGURE 24. TEMPERATURE SWEEP WITH I2E FROZEN, I2E PREVIOUSLY CALIBRATED SNRFS (dBFS) AND SFDR (dBc) 90 SFDR 85 80 75 70 65 SNR 60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 SUPPLY VOLTAGE (AVDD) FIGURE 25. ANALOG SUPPLY VOLTAGE SWEEP WITH I2E FROZEN, I2E PREVIOUSLY CALIBRATED FN7604 Rev.3.0 Jul 6, 2021 Page 13 of 33 80 ISLA112P50 Theory of Operation Functional Description The ISLA112P50 is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 26). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. The converter pipeline requires twelve samples to produce a result. Digital error correction is also applied, resulting in a total latency of 17 clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. The device contains two core A/D converters with carefully matched transfer characteristics. The cores are clocked on alternate clock edges, resulting in a doubling of the sample rate. Time–interleaved A/D systems can exhibit non–ideal artifacts in the frequency domain if the individual core A/D characteristics are not well matched. Gain, offset and timing skew mismatches are of primary concern. The Interleave Engine (I2E) performs automatic interleave calibration for the offset, gain, and sample time skew mismatch between the core A/Ds. The I2E circuitry also adjusts in real-time for temperature and voltage variations. Residual gain and sample time skew mismatch result in fundamental image spurs at fNYQUIST ± fIN. Offset mismatches create spurs at DC and multiples of fNYQUIST. Power-On Calibration As mentioned previously, the cores perform a self-calibration at start-up. An internal power-on-reset (POR) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. The following conditions must be adhered to for the power-on calibration to execute successfully: • A frequency-stable conversion clock must be applied to the CLKP/CLKN pins • DNC pins must not be connected • SDO (pin 66) must be high • RESETN (pin 25) must begin low • SPI communications must not be attempted A user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. Pins 3, 4, and SDO require an external 4.7k pull-up to OVDD. If these pins are pulled low externally during power-up, calibration will not be executed properly. After the power supply has stabilized the internal POR releases RESETN and an internal pull-up pulls it high, which starts the calibration sequence. If a subsequent user-initiated reset is desired, the RESETN pin should be connected to an open-drain driver with a drive strength in its high impedance state of less than 0.5mA. The calibration sequence is initiated on the rising edge of RESETN, as shown in Figure 27. The over-range output (OR) is set high once RESETN is pulled low, and remains in that state until calibration is complete. The OR output returns to normal operation at that time, so it is important that the analog input be within the converter’s full-scale range to observe the transition. If the input is in an over-range condition the OR pin will stay high, and it will not be possible to detect the end of the calibration cycle. CLOCK GENERATION INP SHA INN 1.25V + – 2.5-BIT FLASH 6-STAGE 1.5-BIT/STAGE 3-STAGE 1-BIT/STAGE 3-BIT FLASH DIGITAL ERROR CORRECTION LVDS/LVCMOS OUTPUTS FIGURE 26. A/D CORE BLOCK DIAGRAM FN7604 Rev.3.0 Jul 6, 2021 Page 14 of 33 ISLA112P50 CLKN CLKP CALIBRATION TIME 3 SNR CHANGE (dBfs) While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is set low. Normal operation of the output clock resumes at the next input clock edge (CLKP/CLKN) after RESETN is deasserted. At 500MSPS the nominal calibration time is 200ms, while the maximum calibration time is 550ms. CAL DONE AT +85°C 2 1 0 -1 -2 CAL DONE AT -40°C -3 RESETN -4 -40 CALIBRATION BEGINS -15 10 CAL DONE AT +25°C 35 60 85 TEMPERATURE (°C) ORP CALIBRATION COMPLETE FIGURE 28. SNR PERFORMANCE vs TEMPERATURE AFTER +25°C CALIBRATION CLKOUTP FIGURE 27. CALIBRATION TIMING User Initiated Reset Recalibration of the A/D can be initiated at any time by driving the RESETN pin low for a minimum of one clock cycle. An open-drain driver with a drive strength in its high impedance state of less than 0.5mA is recommended, as RESETN has an internal high impedance pull-up to OVDD. As is the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the ISLA112P50 changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements. Best performance will be achieved by recalibrating the A/D under the environmental conditions at which it will operate. A supply voltage variation of less than 100mV will generally result in an SNR change of less than 0.5dBFS and SFDR change of less than 3dBc. In situations where the sample rate is not constant, best results will be obtained if the device is calibrated at the highest sample rate. Reducing the sample rate by less than 80MSPS will typically result in an SNR change of less than 0.5dBFS and an SFDR change of less than 3dBc. Figures 28 and 29 show the effect of temperature on SNR and SFDR performance with power on calibration performed at -40°C, +25°C, and +85°C. Each plot shows the variation of SNR/SFDR across temperature after a single power on calibration at -40°C, +25°C and +85°C. Best performance is typically achieved by a user-initiated power on calibration at the operating conditions, as stated earlier. However, it can be seen that performance drift with temperature is not a very strong function of the temperature at which the power on calibration is performed. To achieve the performance demonstrated in the SFDR plot, I2E must be in Track mode. FN7604 Rev.3.0 Jul 6, 2021 SFDR CHANGE (dBc) 15 CAL DONE AT -40°C 10 5 0 -5 CAL DONE AT +25°C CAL DONE AT +85°C -10 -15 -40 -15 10 35 TEMPERATURE (°C) 60 85 FIGURE 29. SFDR PERFORMANCE vs TEMPERATURE AFTER +25°C CALIBRATION Analog Input A single fully differential input (VINP/VINN) connects to the sample and hold amplifier (SHA) of each unit A/D. The ideal full-scale input voltage is 1.45V, centered at the VCM voltage of 0.535V as shown in Figure 30. 1.8 1.4 1.0 INN 0.725V INP VCM 0.6 0.535V 0.2 FIGURE 30. ANALOG INPUT RANGE Best performance is obtained when the analog inputs are driven differentially. The common-mode output voltage, VCM, should be used to properly bias the inputs as shown in Figures 31 through 33. An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. Two different transformer input schemes are shown in Figures 31 and 32. Page 15 of 33 ISLA112P50 ADT1-1WT ADT1-1WT 1000pF A/D VCM 0.1µF and CML drive levels. To maintain the lowest possible aperture jitter, it is recommended to have high slew rate at the zero crossing of the differential clock input signal. The recommended drive circuit is shown in Figure 34. A duty range of 40% to 60% is acceptable. The clock can be driven single-ended, but this will reduce the edge rate and may impact SNR performance. The clock inputs are internally self-biased to AVDD/2 to facilitate AC coupling.  1kO  1kO FIGURE 31. TRANSFORMER INPUT FOR GENERAL PURPOSE APPLICATIONS AVDD 200pF TC4-1W ADTL1-12 ADTL1-12 1000pF CLKP 1000pF 200pF 0.1µF  200O A/D 1000pF VCM CLKN 200pF This dual transformer scheme is used to improve common-mode rejection, which keeps the common-mode level of the input matched to VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the ISLA112P50 is 500. The SHA design uses a switched capacitor input stage (see Figure 47), which creates current spikes when the sampling capacitance is reconnected to the input voltage. This causes a disturbance at the input which must settle before the next sampling point. Lower source impedance will result in faster settling and improved performance. Therefore a 1:1 transformer and low shunt resistance are recommended for optimal performance.  348O  69.8O 0.22µF 1 SNR = 20 log 10  -------------------  2f t   100O  217O A/D  25O  348O (EQ. 1) IN J 100 95 tj = 0.1ps 90 14 BITS 85 80 tj = 1ps 75 0.1µF FIGURE 33. DIFFERENTIAL AMPLIFIER INPUT A differential amplifier, as shown in Figure 33, can be used in applications that require DC-coupling. In this configuration, the amplifier will typically dominate the achievable SNR and distortion performance. Clock Input The clock input circuit is a differential pair (see Figure 48). Driving these inputs with a high level (up to 1.8VP-P on each input) sine or square wave will provide the lowest jitter performance. A transformer with 4:1 impedance ratio will provide increased drive levels. The clock input is functional with AC-coupled LVDS, LVPECL, 12 BITS 70 tj = 10ps 60 VCM  69.8O FN7604 Rev.3.0 Jul 6, 2021 In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter (tJ) and SNR is shown in Equation 1 and is illustrated in Figure 35. 50 10 BITS tj = 100ps 55 CM  49.9O Jitter 65  25O  100O FIGURE 34. RECOMMENDED CLOCK DRIVE SNR (dB) FIGURE 32. TRANSMISSION-LINE TRANSFORMER INPUT FOR HIGH IF APPLICATIONS 1M 10M 100M INPUT FREQUENCY (Hz) 1G FIGURE 35. SNR vs CLOCK JITTER This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as linearity, aperture jitter and thermal noise. Internal aperture jitter is the uncertainty in the sampling instant shown in Figure 3. The internal aperture jitter combines with the input clock jitter in a root-sum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR. Voltage Reference A temperature compensated voltage reference provides the reference charges used in the successive approximation operations. The full-scale range of each A/D is proportional to the reference voltage. The nominal value of the voltage reference is 1.25V. Page 16 of 33 ISLA112P50 Digital Outputs Wake-up from Sleep Mode Sequence (CSB high) Output data is available as a parallel bus in LVDS-compatible or CMOS modes. In either case, the data is presented in double data rate (DDR) format. Figures 3 and 4 show the timing relationships for LVDS and CMOS modes, respectively. • Pull CSB Low Additionally, the drive current for LVDS mode can be set to a nominal 3mA or a power-saving 2mA. The lower current setting can be used in designs where the receiver is in close physical proximity to the A/D. The applicability of this setting is dependent upon the PCB layout, therefore the user should experiment to determine if performance degradation is observed. • Wait 1ms until A/D fully powered on The output mode and LVDS drive current are selected via the OUTMODE pin as shown in Table 2. TABLE 2. OUTMODE PIN SETTINGS OUTMODE PIN MODE AVSS LVCMOS Float LVDS, 3mA AVDD LVDS, 2mA The output mode can also be controlled through the SPI port, which overrides the OUTMODE pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. An external resistor creates the bias for the LVDS drivers. A 10k, 1% resistor must be connected from the RLVDS pin to OVSS. Over-Range Indicator The over-range (OR) bit is asserted when the output code reaches positive full-scale (e.g., 0xFFF in offset binary mode). The output code does not wrap around during an over-range condition. The OR bit is updated at the sample rate. Power Dissipation The power dissipated by the ISLA112P50 is primarily dependent on the sample rate and the output modes: LVDS vs CMOS and DDR vs SDR. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. The output supply dissipation changes to a lesser degree in LVDS mode, but is more strongly related to the clock frequency in CMOS mode. Nap/Sleep Portions of the device may be shut down to save power during times when operation of the A/D is not required. Two power saving modes are available: Nap and Sleep. Nap mode reduces power dissipation to less than 164mW and recovers to normal operation in approximately 2.75µs. Sleep mode reduces power dissipation to less than 6mW but requires approximately 1ms to recover from a sleep command. Wake-up time from sleep mode is dependent on the state of CSB; in a typical application CSB would be held high during sleep, requiring a user to wait 150µs max after CSB is asserted (brought low) prior to writing ‘001x’ to SPI Register 25. The device would be fully powered up, in normal mode 1ms after this command is written. FN7604 Rev.3.0 Jul 6, 2021 • Wait 150µs • Write ‘001x’ to Register 25 In an application where CSB was kept low in sleep mode, the 150µs CSB setup time is not required as the SPI registers are powered on when CSB is low, the chip power dissipation increases by ~15mW in this case. The 1ms wake-up time after the write of a ‘001x’ to register 25 still applies. It is generally recommended to keep CSB high in sleep mode to avoid any unintentional SPI activity on the A/D. All digital outputs (Data, CLKOUT and OR) are placed in a high impedance state during Nap or Sleep. The input clock should remain running and at a fixed frequency during Nap or Sleep, and CSB should be high. Recovery time from Nap mode will increase if the clock is stopped, since the internal DLL can take up to 52µs to regain lock at 250MSPS. By default after the device is powered on, the operational state is controlled by the NAPSLP pin as shown in Table 3. TABLE 3. NAPSLP PIN SETTINGS NAPSLP PIN MODE AVSS Normal Float Sleep AVDD Nap The power-down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. Data Format Output data can be presented in three formats: two’s complement, Gray code and offset binary. The data format is selected via the OUTFMT pin as shown in Table 4. TABLE 4. OUTFMT PIN SETTINGS OUTFMT PIN MODE AVSS Offset Binary Float Two’s Complement AVDD Gray Code The data format can also be controlled through the SPI port, which overrides the OUTFMT pin setting. Details on this are contained in “Serial Peripheral Interface” on page 22. Offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two’s complement coding simply complements the MSB of the offset binary representation. Page 17 of 33 ISLA112P50 When calculating Gray code the MSB is unchanged. The remaining bits are computed as the XOR of the current bit position and the next most significant bit. Figure 36 shows this operation. BINARY 11 10 9 •••• 1 11 10 •••• 9 1 Differences in the offset, gain, and sample times of time-interleaved A/Ds create artifacts in the digital outputs. Each of these artifacts creates a unique signature that may be detectable in the captured samples. The I2E algorithm optimizes performance by detecting error signatures and adjusting each unit A/D using minimal additional power. 0 FIGURE 36. BINARY TO GRAY CODE CONVERSION Converting back to offset binary from Gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 37. GRAY CODE 11 10 9 •••• Overview I2E is a blind and background capable algorithm, designed to transparently eliminate interleaving artifacts. This circuitry eliminates interleave artifacts due to offset, gain, and sample time mismatches between unit A/Ds, and across supply voltage and temperature variations in real-time. 0 •••• GRAY CODE I2E Requirements and Restrictions 1 0 •••• The I2E algorithm can be put in Active Run state via SPI. When the I2E algorithm is in Active Run state, it detects and corrects for offset, gain, and sample time mismatches in real time (see Track Mode description). However, certain analog input characteristics can obscure the estimation of these mismatches. The I2E algorithm is capable of detecting these obscuring analog input characteristics, and as long as they are present, I2E will stop updating the correction in real time. Effectively, this freezes the current correction circuitry to the last known good state (see Hold Mode description). Once the analog input signal stops obscuring the interleaved artifacts, the I2E algorithm will automatically start correcting for mismatch in real time again. Active Run State During the Active Run state the I2E algorithm actively suppresses artifacts due to interleaving based on statistics in the digitized data. I2E has two modes of operation in this state (described below), dynamically chosen in real-time by the algorithm based on the statistics of the analog input signal. •••• BINARY 11 10 9 •••• 1 0 FIGURE 37. GRAY CODE TO BINARY CONVERSION Mapping of the input voltage to the various data formats is shown in Table 5. TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING INPUT VOLTAGE OFFSET BINARY TWO’S COMPLEMENT GRAY CODE –Full Scale 000 00 000 00 00 100 00 000 00 00 000 00 000 00 00 –Full Scale +1LSB 000 00 000 00 01 100 00 000 00 01 000 00 000 00 01 Mid–Scale 100 00 000 00 00 000 00 000 00 00 110 00 000 00 00 +Full Scale -1LSB 111 11 111 11 10 011 11 111 11 10 100 00 000 00 01 +Full Scale 111 11 111 11 11 011 11 111 111 1 100 00 000 00 00 FN7604 Rev.3.0 Jul 6, 2021 Track Mode refers to the default state of the algorithm, when all artifacts due to interleaving are actively being eliminated. To be in Track Mode, the analog input signal to the device must adhere to the following requirements: • Possess total power greater than -20dBFS, integrated from 1MHz to Nyquist but excluding signal energy in a 100kHz band centered at fS/4 The criteria above assumes 500MSPS operation; the frequency bands should be scaled proportionally for lower sample rates. Note that the effect of excluding energy in the 100kHz band around of fS/4 exists in every Nyquist zone. This band generalizes to the form (N*fS/4-50kHz) to (N*fS/4+50kHz), where N is any odd integer. An input signal that violates these criteria briefly (approximately 10µs), before and after which it meets this criteria, will not impact system performance. The algorithm must be in Track Mode for approximately one second (defined as I2Epost_t in the specification table on page 7) after power-up before the specifications apply. Once this requirement has been met, the specifications of the device will continue to be met while I2E remains in Track Mode, even in the presence of temperature and supply voltage changes. Page 18 of 33 ISLA112P50 Hold Mode refers to the state of the I2E algorithm when the analog input signal does not meet the requirements specified above. If the algorithm detects that the signal no longer meets the criteria, it automatically enters Hold Mode. In Hold Mode, the I2E circuitry freezes the adjustment values based on the most recent set of valid input conditions. However, in Hold Mode, the I2E circuitry will not correct for new changes in interleave artifacts induced by supply voltage and temperature changes. The I2E circuitry will remain in Hold Mode until such time as the analog input signal meets the requirements for Track Mode. Power Meter The power meter calculates the average power of the analog input, and determines if it’s within range to allow operation in Track Mode. Both AC RMS and total RMS power are calculated, and there are separate SPI programmable thresholds and hysteresis values for each. Notch Filter A digital filter removes the signal energy in a 100kHz band around fS/4 before the I2E circuitry uses these samples for estimating offset, gain, and sample time mismatches (data samples produced by the A/D are unaffected by this filtering). This allows the I2E algorithm to continue in Active Run state while in the presence of a large amount of input energy near the fS/4 frequency. This filter can be powered down if it’s known that the signal characteristics won’t violate the restrictions. Powering FN7604 Rev.3.0 Jul 6, 2021 down the Notch filter will reduce power consumption by approximately 70mW. Nyquist Zones The I2E circuitry allows the use of any one Nyquist zone without configuration, but requires the use of only one Nyquist zone. Inputs that switch dynamically between Nyquist zones will cause poor performance for the I2E circuitry. For example, I2E will function properly for a particular application that has fS = 500MSPS and uses the 1st Nyquist zone (0MHz to 250MHz). I2E will also function properly for an application that uses fS = 500MSPS and the 2nd Nyquist zone (250MHz to 500MHz). I2E will not function properly for an application that uses fS = 500MSPS, and input frequency bands from 150MHz to 210MHz and 250MHz to 290MHz simultaneously. There is no need to configure the I2E algorithm to use a particular Nyquist zone, but no dynamic switching between Nyquist zones is permitted while I2E is running. Configurability and Communication I2E can respond to status queries, be turned on and turned off, and generally configured via SPI programmable registers. Configuring of I2E is generally unnecessary unless the application cannot meet the requirements of Track Mode on or after power up. Parameters that can be adjusted and read back include Notch filter threshold and status, Power Meter threshold and status, and initial values for the offset, gain, and sample time values to use when I2E starts. Page 19 of 33 ISLA112P50 Clock Divider Synchronous Reset An output clock (CLKOUTP, CLKOUTN) is provided to facilitate latching of the sampled data. This clock is at half the frequency of the sample clock, and the absolute phase of the output clocks for multiple A/Ds is indeterminate. This feature allows the phase of multiple A/Ds to be synchronized (refer to Figure 38), which greatly simplifies data capture in systems employing multiple A/Ds. The reset signal must be well-timed with respect to the sample clock (see “Switching Specifications” on page 9). Sample Clock Input s1 L+td1 Analog Input s2 tRSTH CLKDIVRSTP 2 tRSTS tRSTRT ADC1 Output Data s0 s1 s2 s3 s0 s1 s2 s3 ADC1 CLKOUTP ADC2 Output Data ADC2 CLKOUTP (phase 1) 3 ADC2 CLKOUTP (phase 2) 3 1 Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay td 2 CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge. CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP 3 Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization FIGURE 38. SYNCHRONOUS RESET OPERATION FN7604 Rev.3.0 Jul 6, 2021 Page 20 of 33 ISLA112P50 CSB SCLK SDIO R/W W1 W0 A12 A11 A1 A10 A0 D7 D6 D5 D4 D3 D2 D1 D0 D2 D3 D4 D5 D6 D7 FIGURE 39. MSB-FIRST ADDRESSING CSB SCLK SDIO A0 A1 A2 A11 A12 W0 W1 R/W D1 D0 FIGURE 40. LSB-FIRST ADDRESSING tDSW CSB tDHW tS tCLK tHI tH tLO SCLK SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 SPI WRITE FIGURE 41. SPI WRITE tDSW CSB tDHW tS tCLK tHI tH tDHR tDVR tLO SCLK WRITING A READ COMMAND SDIO R/W W1 W0 A12 A11 A10 A9 A2 A1 READING DATA (3 WIRE MODE) A0 D7 SDO D6 D3 D2 D1 D0 (4 WIRE MODE) D7 D3 D2 D1 D0 SPI READ FIGURE 42. SPI READ FN7604 Rev.3.0 Jul 6, 2021 Page 21 of 33 ISLA112P50 CSB STALLING CSB SCLK SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD 2 FIGURE 43. 2-BYTE TRANSFER LAST LEGAL CSB STALLING CSB SCLK SDIO INSTRUCTION/ADDRESS DATA WORD 1 DATA WORD N FIGURE 44. N-BYTE TRANSFER Serial Peripheral Interface A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) serial data output (SDO), and serial data input/output (SDIO). The maximum SCLK rate is equal to the A/D sample rate (fSAMPLE) divided by 32 for write operations and fSAMPLE divided by 132 for reads. At fSAMPLE = 250MHz, maximum SCLK is 15.63MHz for writing and 3.79MHz for read operations. There is no minimum SCLK rate. The following sections describe various registers that are used to configure the SPI or adjust performance or functional parameters. Many registers in the available address space (0x00 to 0xFF) are not defined in this document. Additionally, within a defined register there may be certain bits or bit combinations that are reserved. Undefined registers and undefined values within defined registers are reserved and should not be selected. Setting any reserved register or value may produce indeterminate results. SPI Physical Interface The serial clock pin (SCLK) provides synchronization for the data transfer. By default, all data is presented on the serial data input/output (SDIO) pin in three-wire mode. The state of the SDIO pin is set automatically in the communication protocol (described in the following). A dedicated serial data output pin (SDO) can be activated by setting 0x00[7] high to allow operation in four-wire mode. The SPI port operates in a half duplex master/slave configuration, with the ISLA112P50 functioning as a slave. Multiple slave devices can interface to a single master in three-wire mode only, since the SDO output of an unaddressed device is asserted in four wire mode. The chip-select bar (CSB) pin determines when a slave device is being addressed. Multiple slave devices can be written to concurrently, but only one slave device can be read from at a given time (again, only in three-wire mode). If multiple slave FN7604 Rev.3.0 Jul 6, 2021 devices are selected for reading at the same time, the results will be indeterminate. The communication protocol begins with an instruction/address phase. The first rising SCLK edge following a high to low transition on CSB determines the beginning of the two-byte instruction/address command; SCLK must be static low before the CSB transition. Data can be presented in MSB-first order or LSB-first order. The default is MSB-first, but this can be changed by setting 0x00[6] high. Figures 39 and 40 show the appropriate bit ordering for the MSB-first and LSB-first modes, respectively. In MSB-first mode, the address is incremented for multi-byte transfers, while in LSB-first mode it’s decremented. In the default mode, the MSB is R/W, which determines if the data is to be read (active high) or written. The next two bits, W1 and W0, determine the number of data bytes to be read or written (see Table 6). The lower 13 bits contain the first address for the data transfer. This relationship is illustrated in Figure 41, and timing values are given in “Switching Specifications” on page 9. After the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the A/D (based on the R/W bit status). The data transfer will continue as long as CSB remains low and SCLK is active. Stalling of the CSB pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. For transfers of four bytes or more, CSB is allowed to stall in the middle of the instruction/address bytes or before the first data byte. If CSB transitions to a high state after that point the state machine will reset and terminate the data transfer. TABLE 6. BYTE TRANSFER SELECTION [W1:W0] BYTES TRANSFERRED 00 1 01 2 10 3 11 4 or more Page 22 of 33 ISLA112P50 Figures 43 and 44 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The operation for a 3-byte transfer can be inferred from these diagrams. SPI Configuration ADDRESS 0X00: CHIP_PORT_CONFIG Bit ordering and SPI reset are controlled by this register. Bit order can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB first) to accommodate various micro controllers. Bit 7 SDO Active Bit 6 LSB First Setting this bit high configures the SPI to interpret serial data as arriving in LSB to MSB order. Bit 5 Soft Reset Setting this bit high resets all SPI registers to default values. command. It is important to note that only a single converter can be addressed at a time. This register defaults to 00h, indicating that no A/D is addressed. Error code ‘AD’ is returned if any indexed register is read from without properly setting device_index_A. ADDRESS 0X20: OFFSET_COARSE ADDRESS 0X21: OFFSET_FINE The input offset of the A/D core can be adjusted in fine and coarse steps. Both adjustments are made via an 8-bit word as detailed in Table 7. The data format is two’s complement. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value, then write the incremented or decremented value back to the same register. TABLE 7. OFFSET ADJUSTMENTS Bit 4 Reserved This bit should always be set high. PARAMETER 0x20[7:0] COARSE OFFSET 0x21[7:0] FINE OFFSET Bits 3:0 These bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. Steps 255 255 –Full Scale (0x00) -133LSB (-47mV) -5LSB (-1.75mV) ADDRESS 0X02: BURST_END Mid–Scale (0x80) 0.0LSB (0.0mV) 0.0LSB If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redundant addressing. In 3-wire SPI mode, the burst is ended by pulling the CSB pin high. If the device is operated in 2-wire mode the CSB pin is not available. In that case, setting the burst_end address determines the end of the transfer. During a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. +Full Scale (0xFF) +133LSB (+47mV) +5LSB (+1.75mV) Nominal Step Size 1.04LSB (0.37mV) 0.04LSB (0.014mV) Bits 7:0 Burst End Address This register value determines the ending address of the burst data. Device Information ADDRESS 0X08: CHIP_ID ADDRESS 0X09: CHIP_VERSION The generic die identifier and a revision number, respectively, can be read from these two registers. Indexed Device Configuration/Control ADDRESS 0X22: GAIN_COARSE ADDRESS 0X23: GAIN_MEDIUM ADDRESS 0X24: GAIN_FINE Gain of the A/D core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. Multiple Coarse Gain Bits can be set for a total adjustment range of ±4.2%. (‘0011’  -4.2% and ‘1100’  +4.2%) It is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the registers at 23h and 24h. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. TABLE 8. COARSE GAIN ADJUSTMENT ADDRESS 0X10: DEVICE_INDEX_A Bits 1:0 ADC01, ADC00 Determines which A/D is addressed. Valid states for this register are 0x01 or 0x10. The two A/D cores cannot be adjusted concurrently. A common SPI map, which can accommodate single-channel or multi-channel devices, is used for all Renesas A/D products. Certain configuration commands (identified as Indexed in the SPI map) can be executed on a per-converter basis. This register determines which converter is being addressed for an Indexed FN7604 Rev.3.0 Jul 6, 2021 0x22[3:0] NOMINAL COARSE GAIN ADJUST (%) Bit3 +2.8 Bit2 +1.4 Bit1 -2.8 Bit0 -1.4 Page 23 of 33 ISLA112P50 TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS PARAMETER 0x23[7:0] MEDIUM GAIN 0x24[7:0] FINE GAIN Steps 256 256 –Full Scale (0x00) -2% -0.20% Mid–Scale (0x80) 0.00% 0.00% +Full Scale (0xFF) +2% +0.2% Nominal Step Size 0.016% 0.0016% ADDRESS 0X25: MODES Two distinct reduced power modes can be selected. By default, the tri-level NAPSLP pin can select normal operation, nap or sleep modes (refer to“Nap/Sleep” on page 17). This functionality can be overridden and controlled through the SPI. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. This register is not changed by a Soft Reset. TABLE 10. POWER-DOWN CONTROL VALUE 0x25[2:0] POWER DOWN MODE 000 Pin Control 001 Normal Operation 010 Nap Mode 100 Sleep Mode ADDRESS 0X30: I2E STATUS ADDRESS 0X31: I2E CONTROL The I2E general control register. This register can be written while I2E is running to control various parameters. Bit 0: 0 = turn I2E off, 1= turn I2E on Bit 1: 0 = no action, 1 = freeze I2E, leaving all settings in the current state. Subsequently writing a 0 to this bit will allow I2E to continue from the state it was left in. Bit 2-4: Disable any of the interleave adjustments of offset, gain, or sample time skew Bit 5: 0 = bypass notch filter, 1 = use notch filter on incoming data before estimating interleave mismatch terms ADDRESS 0X32: I2E STATIC CONTROL The I2E general static control register. This register must be written prior to turning I2E on for the settings to take effect. Bit 1-4: Reserved, always set to 0 Bit 5: 0 = normal operation, 1 = skip coarse adjustment of the offset, gain, and sample time skew analog controls when I2E is first turned on. This bit would typically be used if optimal analog adjustment values for offset, gain, and sample time skew have been preloaded in order to have the I2E algorithm converge more quickly. The system gain of the pair of interleaved core A/Ds can be set by programming the medium and fine gain of the reference A/D before turning I2E on. In this case, I2E will adjust the non-reference A/D’s gain to match the reference A/D’s gain. The I2E general status register. Bit 7: Reserved, always set to 0 Bits 0 and 1 indicate if the I2E circuitry is in Active Run or Hold state. The state of the I2E circuitry is dependent on the analog input signal itself. If the input signal obscures the interleave mismatched artifacts such that I2E cannot estimate the mismatch, the algorithm will dynamically enter the Hold state. For example, a DC mid-scale input to the A/D does not contain sufficient information to estimate the gain and sample time skew mismatches, and thus the I2E algorithm will enter the Hold state. In the Hold state, the analog adjustments for interleave correction will be frozen and mismatch estimate calculations will cease until such time as the analog input achieves sufficient quality to allow the I2E algorithm to make mismatch estimates again. ADDRESS 0X4A: I2E POWER DOWN Bit 0: 0 = I2E has not detected a low power condition. 1 = I2E has detected a low power condition, and the analog adjustments for interleave correction are frozen. Bit 1: 0 = I2E has not detected a low AC power condition. 1 = I2E has detected a low AC power condition, and I2E will continue to correct with best known information but will not update its interleave correction adjustments until the input signal achieves sufficient AC RMS power. Bit 2: When first started, the I2E algorithm can take a significant amount of time to settle (~1s), dependent on the characteristics of the analog input signal. 0 = I2E is still settling, 1 = I2E has completed settling. FN7604 Rev.3.0 Jul 6, 2021 This register provides the capability to completely power down the I2E algorithm and the Notch filter. This would typically be done to conserve power. BIT 0: Power down the I2E Algorithm BIT 1: Power down the Notch Filter ADDRESS 0X50-0X55: I2E FREEZE THRESHOLDS This group of registers provides programming access to configure I2E’s dynamic freeze control. As with any interleave mismatch correction algorithm making estimates of the interleave mismatch errors using the digitized application input signal, there are certain characteristics of the input signal that can obscure the mismatch estimates. For example, a DC input to the A/D contains no information about the sample time skew mismatch between the core A/Ds, and thus should not be used by the I2E algorithm to update its sample time skew estimate. Under such circumstances, I2E enters Hold state. In the Hold state, the analog adjustments will be frozen and mismatch estimate calculations will cease until such time as the analog input achieves sufficient quality to allow the I2E algorithm to make mismatch estimates again. These registers allow the programming of the thresholds of the meters used to determine the quality of the input signal. This can be used by the application to optimize I2E’s behavior based on knowledge of the input signal. For example, if a specific Page 24 of 33 ISLA112P50 application had an input signal that was typically 30dB down from full scale, and was primarily concerned about analog performance of the A/D at this input power, lowering the RMS power threshold would allow I2E to continue tracking with this input power level, thus allowing it to track over voltage and temperature changes. The writing of the AC RMS Power Threshold is different than other SPI registers, and these registers are not listed in the SPI memory map table. The required algorithm is documented below. 0x50 (LSBs), 0x51 (MSBs) RMS Power Threshold 3. Write the LSBs of the 16-bit quantity to SPI Address 0x14F This 16-bit quantity is the RMS power threshold at which I2E will enter Hold state. The RMS power of the analog input is calculated continuously by I2E on incoming data. A 12-bit number squared produces a 24-bit result (for A/D resolutions under 12-bits, the A/D samples are MSB-aligned to 12-bit data). A dynamic number of these 24-bit results are averaged to compare with this threshold approximately every 1µs to decide whether or not to freeze I2E. The 24-bit threshold is constructed with bits 23 through 20 (MSBs) assigned to 0, bits 19 through 4 assigned to this 16-bit quantity, and bits 3 through 0 (LSBs) assigned to 0. As an example, if the application wanted to set this threshold to trigger near the RMS analog input of a 20dBFS sinusoidal input, the calculation to determine this register’s value would be (EQ. 2) 2 hex  290  = 0x014884 TruncateMSBandLSBhexdigit = 0x1488 (EQ. 3) Therefore, programming 0x1488 into these two registers will cause I2E to freeze when the signal being digitized has less RMS power than a -20dBFS sinusoid. The default value of this register is 0x1000, causing I2E to freeze when the input amplitude is less than -21.2 dBFS. The freezing of I2E by the RMS power meter threshold affects the gain and sample time skew interleave mismatch estimates, but not the offset mismatch estimate. 0x52 RMS Power Hysteresis In order to prevent I2E from constantly oscillating between the Hold and Track state, there is hysteresis in the comparison described above. After I2E enters a frozen state, the RMS input power must achieve threshold value + hysteresis to again enter the Track state. The hysteresis quantity is a 24-bit value, constructed with bits 23 through 12 (MSBs) being assigned to 0, bits 11 through 4 assigned to this register’s value, and bits 3 through 0 (LSBs) assigned to 0. AC RMS Power Threshold Similar to RMS power threshold, there must be sufficient AC RMS power (or dV/dt) of the input signal to measure sample time skew mismatch for an arbitrary input. This is clear from observing the effect when a high voltage (and therefore large RMS value) DC input is applied to the A/D input. Without sufficient dV/dt in the input signal, no information about the sample time skew between the core A/Ds can be determined from the digitized samples. The AC RMS Power Meter is implemented as a high-passed (via DSP) RMS power meter. FN7604 Rev.3.0 Jul 6, 2021 2. Write the MSBs of the 16-bit quantity to SPI Address 0x150 A 12-bit number squared produces a 24-bit result (for A/D resolutions under 12-bits, the A/D samples are MSB-aligned to 12-bit data). A dynamic number of these 24-bit results are averaged to compare with this threshold approximately every 1µs to decide whether or not to freeze I2E. The 24-bit threshold is constructed with bits 23 through 20 (MSBs) assigned to 0, bits 19 through 4 assigned to this 16-bit quantity, and bits 3 through 0 (LSBs) assigned to 0. The calculation methodology to set this register is identical to the description in the RMS power threshold description. The freezing of I2E when the AC RMS power meter threshold is not met affects the sample time skew interleave mismatch estimate, but not the offset or gain mismatch estimates. 0x55 AC RMS Power Hysteresis 20-  –---------  20  12 2 RMS codes = -------  10  2  290codes 2 1. Write the value 0x80 to the Index Register (SPI address 0x10) In order to prevent I2E from constantly oscillating between the Hold and Track state, there is hysteresis in the comparison described above. After I2E enters a frozen state, the AC RMS input power must achieve  threshold value + hysteresis to again enter the Track state. The hysteresis quantity is a 24-bit value, constructed with bits 23 through 12 (MSBs) being assigned to 0, bits 11 through 4 assigned to this register’s value, and bits 3 through 0 (LSBs) assigned to 0. ADDRESS 0X60-0X64: I2E INITIALIZATION These registers provide access to the initialization values for each of offset, gain, and sample time skew that I2E programs into the target core A/D before adjusting to minimize interleave mismatch. They can be used by the system to, for example, reduce the convergence time of the I2E algorithm by programming in the optimal values before turning I2E on. In this case, I2E only needs to adjust for temperature and voltage-induced changes since the optimal values were recorded. Global Device Configuration/Control ADDRESS 0X70: SKEW_DIFF The value in the skew_diff register adjusts the timing skew between the two A/D cores. The nominal range and resolution of this adjustment are given in Table 11. The default value of this register after power-up is 80h. TABLE 11. DIFFERENTIAL SKEW ADJUSTMENT PARAMETER 0x70[7:0] DIFFERENTIAL SKEW Steps 256 –Full Scale (0x00) -6.5ps Mid–Scale (0x80) 0.0ps +Full Scale (0xFF) +6.5ps Nominal Step Size 51fs Page 25 of 33 ISLA112P50 ADDRESS 0X71: PHASE_SLIP TABLE 13. OUTPUT FORMAT CONTROL The output data clock is generated by dividing down the A/D input sample clock. Some systems with multiple A/Ds can more easily latch the data from each A/D by controlling the phase of the output data clock. This control is accomplished through the use of the phase_slip SPI feature, which allows the rising edge of the output data clock to be advanced by one input clock period, as shown in Figure 45. Execution of a phase_slip command is accomplished by first writing a '0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address 0x71. VALUE 0x93[2:0] OUTPUT FORMAT 000 Pin Control 001 Two’s Complement 010 Gray Code 100 Offset Binary ADDRESS 0X74: OUTPUT_MODE_B ADC Input Clock (500MHz) ADDRESS 0X75: CONFIG_STATUS 2ns Output Data Clock (250MHz) No clock_slip 4ns Bit 6 DLL Range This bit sets the DLL operating range to fast (default) or slow. 2ns Output Data Clock (250MHz) 1 clock_slip Internal clock signals are generated by a delay-locked loop (DLL), which has a finite operating range. Table 14 shows the allowable sample rate ranges for the slow and fast settings. Output Data Clock (250MHz) 2 clock_slip TABLE 14. DLL RANGES FIGURE 45. PHASE SLIP ADDRESS 0X73: OUTPUT_MODE_A The output_mode_A register controls the physical output format of the data, as well as the logical coding. The ISLA112P50 can present output data in two physical formats: LVDS or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (3mA) or low (2mA). By default, the tri-level OUTMODE pin selects the mode and drive level (refer to “Digital Outputs” on page 17). This functionality can be overridden and controlled through the SPI, as shown in Table 12. Data can be coded in three possible formats: two’s complement, Gray code or offset binary. By default, the tri-level OUTFMT pin selects the data format (refer to “Data Format” on page 17). This functionality can be overridden and controlled through the SPI, as shown in Table 13. This register is not changed by a Soft Reset. TABLE 12. OUTPUT MODE CONTROL VALUE 0x93[7:5] OUTPUT MODE 000 Pin Control 001 LVDS 2mA 010 LVDS 3mA 100 LVCMOS DLL RANGE MIN MAX UNIT Slow 80 200 MSPS Fast 160 500 MSPS The output_mode_B and config_status registers are used in conjunction to enable DDR mode and select the frequency range of the DLL clock generator. The method of setting these options is different from the other registers. READ OUTPUT_MODE_B 0x74 READ CONFIG_STATUS 0x75 DESIRED VALUE WRITE TO 0x74 FIGURE 46. SETTING OUTPUT_MODE_B REGISTER The procedure for setting output_mode_B is shown in Figure 46. Read the contents of output_mode_B and config_status and XOR them. Then XOR this result with the desired value for output_mode_B and write that XOR result to the register. Device Test The ISLA112P50 can produce preset or user defined patterns on the digital outputs to facilitate in-situ testing. A static word can be placed on the output bus, or two different words can alternate. In the alternate mode, the values defined as Word 1 and Word 2 (as shown in Table 15) are set on the output bus on alternating clock phases. The test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus. ADDRESS 0XC0: TEST_IO Bits 7:6 User Test Mode These bits set the test mode to static (0x00) or alternate (0x01) mode. Other values are reserved. FN7604 Rev.3.0 Jul 6, 2021 Page 26 of 33 ISLA112P50 The four LSBs in this register (Output Test Mode) determine the test pattern in combination with registers 0xC2 through 0xC5. Refer to “SPI Memory Map” on page 28. TABLE 15. OUTPUT TEST MODES VALUE 0xC0[3:0] OUTPUT TEST MODE 0000 Off 0001 WORD 1 WORD 2 Midscale 0x8000 N/A 0010 Positive Full-Scale 0xFFFF N/A 0011 Negative Full-Scale 0x0000 N/A 0100 Checkerboard 0xAAAA 0x5555 0101 Reserved N/A N/A 0110 Reserved N/A N/A 0111 One/Zero 0xFFFF 0x0000 1000 User Pattern user_patt1 user_patt2 ADDRESS 0XC2: USER_PATT1_LSB ADDRESS 0XC3: USER_PATT1_MSB These registers define the lower and upper eight bits, respectively, of the first user-defined test word. Digital Temperature Sensor This set of registers provides digital access to an IPTAT-based temperature sensor, allowing the system to estimate the temperature of the die. This information is of particular interest for applications that do not keep I2E in Active Run state when in normal use, allowing easy access to information that can be used to decide when to recalibrate the A/D as needed. This set of registers is not included in the SPI memory map table. The most accurate usage of this information requires knowledge of the temperature at which the digital value is first read (time = 0, T(0) = °C at time = 0, and register_value(0) = the digital value of the temperature registers at time = 0). Any future reading of the registers indicates temperature change according to Equation 4:  register_value(1)  –  register_value(0)  T = T  1  – T  0  = ------------------------------------------------------------------------------------------------------------  T  0  – 216   256  (EQ. 4) A less accurate method for evaluating the temperature change does not require knowledge of the temperature at time = 0, and is given by Equation 5:  register_value(1)  –  register_value(0)  T = T  1  – T  0  = ------------------------------------------------------------------------------------------------------------ -0.72  (EQ. 5) ADDRESS 0XC5: USER_PATT2_MSB The digital temperature sensor is a weak function of the AVDD supply voltage, so to achieve best accuracy the AVDD supply voltage should be held fairly constant across the operating temperature range. These registers define the lower and upper eight bits, respectively, of the second user-defined test word. The algorithm to access this set of registers is as follows: ADDRESS 0XC4: USER_PATT2_LSB 1. Write the value 0x80 to the Index Register (SPI address 0x10) 2. Write the value 0x88 to SPI address 0x120 to turn the temperature sensor on. 3. Read the register_value LSBs at SPI register 0x11E 4. Read the register_value MSBs at SPI register 0x11F 5. Write the value 0x60 to SPI address 0x120 to turn the temperature sensor off. FN7604 Rev.3.0 Jul 6, 2021 Page 27 of 33 ISLA112P50 SPI Memory Map I2E Control and Status Indexed Device Config/Control Info SPI Config TABLE 16. SPI MEMORY MAP ADDR (Hex) PARAMETER NAME BIT 7 (MSB) BIT 6 BIT 5 00 port_config SDO Active LSB First Soft Reset 01 reserved Reserved 02 burst_end Burst end address [7:0] 03-07 reserved Reserved 08 chip_id 09 chip_version 10 device_index_A 11-1F reserved Reserved 20 offset_coarse 21 offset_fine 22 gain_coarse 23 gain_medium 24 gain_fine 25 modes 26-2F reserved 30 I2E Status 31 I2E Control 32 I2E Static Control 33-49 reserved 4A I2E Power Down 4B-4F reserved Reserved 50 I2E RMS Power Threshold LSBs RMS Power Threshold, LSBs 00h G 51 I2E RMS Power Threshold MSBs RMS Power Threshold, MSBs 10h G 52 I2E RMS Hysteresis RMS Power Hysteresis FFh G 53-54 reserved Reserved FN7604 Rev.3.0 Jul 6, 2021 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) Mirror (bit5) Mirror (bit6) Mirror (bit7) DEF. VALUE INDEXED/GL (Hex) OBAL 00h G 00h G Chip ID # Read only G Chip Version # Read only G 00h I Coarse Offset cal. value I Fine Offset cal. value I cal. value I Medium Gain cal. value I Fine Gain cal. value I 00h NOT affected by Soft Reset I Reserved ADC01 Reserved ADC00 Coarse Gain Reserved Power-Down Mode [2:0] 000 = Pin Control 001 = Normal Operation 010 = Nap 100 = Sleep Other codes = Reserved Reserved Reserved Disable Offset Enable notch filter Reserved must be set to 0 Skip coarse adjustment Disable Gain I I2E Settled Low AC Low RMS Power RMS Power Disable Skew Freeze Run Reserved, must be set to 0 Read only G 20h G 00h G Reserved G Notch Filter Power Down I2E Power Down 00h G G G Page 28 of 33 ISLA112P50 Device Test Global DeviceConfig/Control I2E Control and Status (continued) TABLE 16. SPI MEMORY MAP (Continued) ADDR (Hex) PARAMETER NAME BIT 7 (MSB) 55 I2E AC RMS Hysteresis AC RMS Power Hysteresis 56-5F reserved Reserved 60 Coarse Offset Init Coarse Offset Initialization value 80h G 61 Fine Offset Init Fine Offset Initialization value 80h G 62 Medium Gain Init Medium Gain Initialization value 80h G 63 Fine Gain Init Fine Gain Initialization value 80h G 64 Sample Time Skew Init Sample Time Skew Initialization value 80h G 65-6F reserved Reserved 70 skew_diff Differential Skew 71 phase_slip 72 Reserved 73 output_mode_A 74 output_mode_B 75 config_status 76-BF reserved C0 test_io BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) DEF. VALUE INDEXED/GL (Hex) OBAL 10h G G G 80h G 00h G Reserved (must be 0) 00h NOT affected by Soft Reset G Output Format [2:0] 000 = Pin Control 001 = Twos Complement 010 = Gray Code 100 = Offset Binary Other codes = Reserved 00h NOT affected by Soft Reset G DLL Range 0 = fast 1 = slow 00h NOT affected by Soft Reset G XOR Result Read Only G 00h G 00h G Reserved Next Clock Edge Reserved Output Mode [2:0] 000 = Pin Control 001 = LVDS 2mA 010 = LVDS 3mA 100 = LVCMOS other codes = reserved Reserved Output Test Mode [3:0] User Test Mode [1:0] 00 = Single 01 = Alternate 10 = Reserved 11 = Reserved 0 = Off 1 = Midscale Short 2 = +FS Short 3 = -FS Short 4 = Checker Board 5 = reserved 6 = reserved 7 = One/Zero Word Toggle 8 = User Input 9-15 = reserved C1 Reserved C2 user_patt 1_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h G C3 user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 00h G C4 user_patt 2_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h G C5 user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 00h G C6-FF reserved FN7604 Rev.3.0 Jul 6, 2021 Reserved Reserved Page 29 of 33 ISLA112P50 Equivalent Circuits AVDD TO CLOCKPHASE GENERATION AVDD CLKP AVDD CSAMP 1.6pF TO CHARGE PIPELINE  F3 INP 2 F 1 F  500O CSAMP 1.6pF AVDD TO CHARGE PIPELINE 3 F INN 2 F  F1 AVDD  11kO CLKN FIGURE 48. CLOCK INPUTS AVDD (20k PULL-UP ON RESETN ONLY) AVDD  75kO AVDD TO SENSE LOGIC  75kO  280O INPUT  18kO AVDD 11kO  FIGURE 47. ANALOG INPUTS AVDD  18kO OVDD OVDD OVDD 20k INPUT  75kO  75kO TO LOGIC 280 FIGURE 49. TRI-LEVEL DIGITAL INPUTS FIGURE 50. DIGITAL INPUTS OVDD 2mA OR 3mA OVDD DATA DATA D[7:0]P OVDD OVDD D[7:0]N OVDD DATA DATA DATA D[7:0] 2mA OR 3mA FIGURE 51. LVDS OUTPUTS FN7604 Rev.3.0 Jul 6, 2021 FIGURE 52. CMOS OUTPUTS Page 30 of 33 ISLA112P50 Equivalent Circuits (Continued) AVDD VCM 0.535V + – FIGURE 53. VCM_OUT OUTPUT A/D Evaluation Platform LVCMOS Outputs Renesas offers an A/D Evaluation platform which can be used to evaluate any of Renesas’ high speed A/D products. The platform consists of an FPGA based data capture motherboard and a family of A/D daughter cards. This USB based platform allows a user to quickly evaluate the A/D’s performance at a user’s specific application frequency requirements. More information is available on the website. Output traces and connections must be designed for 50 characteristic impedance. Layout Considerations Split Ground and Power Planes Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip. Clock Input Considerations Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate transformers and terminations as close to the chip as possible. Exposed Paddle The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance. Bypass and Filtering Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops. LVDS Outputs Output traces and connections must be designed for 50 (100 differential) characteristic impedance. Keep traces direct and minimize bends where possible. Avoid crossing ground and power-plane breaks with signal traces. FN7604 Rev.3.0 Jul 6, 2021 Unused Inputs Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will not be operated do not require connection to ensure optimal A/D performance. These inputs can be left floating if they are not used. Tri-level inputs (NAPSLP, OUTMODE, OUTFMT) accept a floating input as a valid state, and therefore should be biased according to the desired functionality. Definitions Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD - 1.76)/6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage less 2 LSB. It is typically expressed in percent. I2E The Interleave Engine. This highly configurable circuitry performs estimates of offset, gain, and sample time skew mismatches between the core converters, and updates analog adjustments for each to minimize interleave spurs. Integral Non-Linearity (INL) is the maximum deviation of the A/D’s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of LSBs. Page 31 of 33 ISLA112P50 Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N-1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the A/D output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. Power Supply Rejection Ratio (PSRR) is the ratio of the observed magnitude of a spur in the A/D FFT, caused by an AC signal superimposed on the power supply voltage. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. SNR and SINAD are either given in units of dB when the power of the fundamental is used as the reference, or dBFS (dB to full scale) when the converter’s full-scale input power is used as the reference. Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the largest spurious spectral component. The largest spurious spectral component may or may not be a harmonic. Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION Jul 6, 2021 3.0 Jul 6, 2011 2.0 CHANGE Updated links throughout. Updated Ordering Information table format and updated applicable notes. Updated termination finish from Matte Sn (e3) to NiPdAu-Ag (e4). Changed POD from L72.10x10C to L72.10x10J. Removed Products section. – Updated Intersil Trademark statement at bottom of page 1 per directive from Legal. – Converted to new datasheet template. – Replaced all occurrences of "Fs/4 filter" with "Notch filter". – Updated over temp note in Min Max column of spec tables from: Unless otherwise noted, parameters with Min and/or MAX limits are 100% production tested at their worst case temperature extreme (+85°C). To new standard: "Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." May 19, 2010 1.0 – On page 1: Removed CLKDIV from key feature list (Selectable Clock Divider: ÷1 or ÷2) Removed CLKDIV pin from “”(was right nexto to CLKDIVRSTP pin) – On page 3: Removed CLKDIV pin from “Pin Configuration” diagram, replaced with a DNC pin (pin 16) – On page 4: Removed CLKDIV pin from “Pin Descriptions” list, added pin 16 to DNC list – On page 7: Under “CMOS INPUTS” in the “Digital Specifications” table, added CSB and SCLK to the CMOS pin list (in Parameter column) for I_IH, I_IL, V_IH, V_IL Removed CLKDIV reference from “Input Current High (OUTMODE, NAPSLP, OUTFMT) (Note 14)” and “Input Current Low (OUTMODE, NAPSLP, OUTFMT)” specs – On page 16: Removed text and table describing CLKDIV function – On page 20: Removed sentences referencing the “2GSPS” block diagram under the “Clock Divider Synchronous Reset” section as we no longer support this clock distribution block diagram, nor su/hold times to support closing timing at 1GHz input clock – On page 21: Removed Sync generation block diagram (former FIGURE 38. SYNCHRONIZATION SCHEME) because we no longer support this architecture – On page 26: Updated “ADDRESS 0X71: PHASE_SLIP” section to reflect functionality in the CLKDIV1 mode. New timing diagram Figure 45 to show functionality. Removed the “ADDRESS 0X72: CLOCK_DIVIDE” section and table for SPI address 0x72, clock_divide feature – On page 28: Removed the clock_divide SPI register from Table 16 under ADDR 72, replacing with Reserved (and indicating which bits must be set to 0) – On page 31: Removed the CLKDIV reference in “Unused Inputs” section Mar 30, 2010 FN7604 Rev.3.0 Jul 6, 2021 0.0 Initial Release of Production Datasheet Page 32 of 33 ISLA112P50 Package Outline Drawing For the most recent package outline drawing, see L72.10x10J. L72.10x10J 72 Lead Quad Flat No-Lead Plastic Package (QFN) Rev 0, 4/20 FN7604 Rev.3.0 Jul 6, 2021 Page 33 of 33 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.