DATASHEET
ISLA212P50
FN7843
Rev.3.0
Jul 6, 2021
12-Bit, 500MSPS ADC
The ISLA212P50 is a 12-bit, 500MSPS analog-to-digital
converter designed with Renesas’ proprietary FemtoCharge™
technology on a standard CMOS process. The ISLA212P50 is
part of a pin-compatible portfolio of 12 to 16-bit A/Ds with
maximum sample rates ranging from 130MSPS to 500MSPS.
Features
The device utilizes two time-interleaved 250MSPS unit ADCs to
achieve the ultimate sample rate of 500MSPS. A single
500MHz conversion clock is presented to the converter, and all
interleave clocking is managed internally. The proprietary
Interleave Engine (I2E) performs automatic correction of
offset, gain, and sample time mismatches between the unit
ADCs to optimize performance.
• 75f clock jitter
A serial peripheral interface (SPI) port allows for extensive
configurability of the A/D. The SPI also controls the interleave
correction circuitry, allowing the system to issue offline and
continuous calibration commands as well as configure many
dynamic parameters.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA212P50 is available in a 72 Ld QFN package
with an exposed paddle. Operating from a 1.8V supply,
performance is specified over the full industrial temperature
range (-40°C to +85°C).
Specifications
CLKOUTN
12-BIT
250 MSPS
ADC
D[11:0]P
D[11:0]N
VREF
VINP
Gain, Offset
and Skew
Adjustments
VINN
ORP
I2E
DIGITAL
ERROR
CORRECTION
12-BIT
250 MSPS
ADC
SHA
VREF
OVSS
RLVDS
RESETN
NAPSLP
AVSS
FN7843 Rev.3.0
Jul 6, 2021
SPI
CONTROL
CSB
SCLK
SDIO
SDO
+
–
VCM
• 700MHz bandwidth
• Programmable built-in test patterns
• Multi-ADC support
- SPI programmable fine gain and offset control
- Support for multiple ADC synchronization
- Optimized output timing
• Nap and sleep modes
- 200µs sleep wake-up time
• Data output clock
• DDR LVDS-compatible or LVCMOS outputs
• Selectable clock divider
Applications
• Radar array processing
• Broadband communications
• High-performance data acquisition
• Communications test equipment
OVDD
CLKOUTP
CLOCK
MANAGEMENT
SHA
• Clock duty cycle stabilizer
Pin-Compatible Family
CLKDIVRSTN
CLKDIVRSTP
CLKDIV
AVDD
CLKP
• Single supply 1.8V operation
• Software defined radios
• SNR @ 500MSPS
- = 70.3dBFS fIN = 30MHz
- = 68.7dBFS fIN = 363MHz
• SFDR @ 500MSPS
- = 84dBc fIN = 30MHz
- = 76dBc fIN = 363MHz
• Total Power Consumption = 823mW @ 500MSPS
CLKN
• Automatic fine interleave correction calibration
ORN
MODEL
RESOLUTION
SPEED
(MSPS)
ISLA216P25
16
250
ISLA216P20
16
200
ISLA216P13
16
130
ISLA214P50
14
500
ISLA214P25
14
250
ISLA214P20
14
200
ISLA214P13
14
130
ISLA212P50
12
500
ISLA212P25
12
250
ISLA212P20
12
200
ISLA212P13
12
130
Page 1 of 38
© 2011 Renesas Electronics
ISLA212P50
Table of Contents
Pin-Compatible Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Configuration- LVDS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions - 72 Ld QFN, LVDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration- CMOS MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Descriptions - 72 Ld QFN, CMOS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2E Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
20
20
20
20
21
21
21
I2E Requirements and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Active Run State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
FS/4 Filter (Notch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Nyquist Zones. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configurability and Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address 0x60-0x64: I2E initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
25
26
26
28
28
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FN7843 Rev.3.0
Jul 6, 2021
Page 2 of 38
ISLA212P50
A/D Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
36
36
36
36
36
36
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FN7843 Rev.3.0
Jul 6, 2021
Page 3 of 38
ISLA212P50
Pin Configuration- LVDS MODE
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
OVDD
OVSS
DNC
DNC
DNC
DNC
D0P
D0N
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54
D1P
DNC
2
53
D1N
NAPSLP
3
52
D2P
VCM
4
51
D2N
AVSS
5
50
D3P
AVDD
6
49
D3N
AVSS
7
48
CLKOUTP
VINN
8
47
CLKOUTN
VINN
9
46
RLVDS
VINP 10
45
OVSS
VINP 11
44
D4P
AVSS 12
43
D4N
AVDD 13
42
D5P
AVSS 14
41
D5N
CLKDIV 15
40
D6P
39
D6N
38
D7P
37
D7N
IPTAT 16
DNC 17
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
Connect Thermal Pad to AVSS
24
25
26
27
28
29
30
31
AVDD
AVDD
CLKP
CLKN
CLKDIVRSTP
CLKDIVRSTN
OVSS
OVDD
D11N
D11P
D10N
D10P
32
33
34
35
36
D8P
23
D8N
22
D9P
21
D9N
20
OVDD
19
AVDD
RESETN 18
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
1, 2, 17, 57, 58, 59, 60
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71, 72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
Common Mode Output
8, 9
VINN
Analog Input Negative
FN7843 Rev.3.0
Jul 6, 2021
LVDS PIN FUNCTION
Tri-Level Power Control (Nap, Sleep modes)
Page 4 of 38
ISLA212P50
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
10, 11
VINP
15
CLKDIV
16
IPTAT
18
RESETN
(Continued)
LVDS PIN FUNCTION
Analog Input Positive
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN
28, 29
D11N, D11P
LVDS Bit 11 (MSB) Output Complement, True
30, 31
D10N, D10P
LVDS Bit 10 Output Complement, True
33, 34
D9N, D9P
LVDS Bit 9 Output Complement, True
35, 36
D8N, D8P
LVDS Bit 8 Output Complement, True
37, 38
D7N, D7P
LVDS Bit 7 Output Complement, True
39, 40
D6N, D6P
LVDS Bit 6 Output Complement, True
41, 42
D5N, D5P
LVDS Bit 5 Output Complement, True
43, 44
D4N, D4P
LVDS Bit 4 Output Complement, True
46
RLVDS
47, 48
CLKOUTN, CLKOUTP
LVDS Clock Output Complement, True
49, 50
D3N, D3P
LVDS Bit 3 Output Complement, True
51, 52
D2N, D2P
LVDS Bit 2 Output Complement, True
53, 54
D1N, D1P
LVDS Bit 1 Output Complement, True
55, 56
D0N, D0P
LVDS Bit 0 (LSB) Output Complement, True
63, 64
ORN, ORP
LVDS Over Range Complement, True
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
FN7843 Rev.3.0
Jul 6, 2021
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
LVDS Bias Resistor (connect to OVSS with 1% 10k)
Page 5 of 38
ISLA212P50
Pin Configuration- CMOS MODE
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
OR
DNC
OVDD
OVSS
DNC
DNC
DNC
DNC
D0
DNC
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54
D1
DNC
2
53
DNC
NAPSLP
3
52
D2
VCM
4
51
DNC
AVSS
5
50
D3
AVDD
6
49
DNC
AVSS
7
48
CLKOUT
VINN
8
47
DNC
VINN
9
46
RLVDS
VINP 10
45
OVSS
VINP 11
44
D4
AVSS 12
43
DNC
AVDD 13
42
D5
AVSS 14
41
DNC
CLKDIV 15
40
D6
39
DNC
38
D7
37
DNC
IPTAT 16
DNC 17
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
Connect Thermal Pad to AVSS
27
28
29
30
31
CLKDIVRSTP
CLKDIVRSTN
OVSS
OVDD
DNC
D11
DNC
D10
32
33
34
35
36
D8
26
DNC
25
D9
24
DNC
23
OVDD
22
CLKN
AVDD
21
CLKP
20
AVDD
19
AVDD
RESETN 18
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
1, 2, 17, 28, 30, 33, 35, 37, 39, 41,
43, 47, 49, 51, 53, 55, 57, 58, 59,
60, 63
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71, 72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
FN7843 Rev.3.0
Jul 6, 2021
CMOS PIN FUNCTION
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
Page 6 of 38
ISLA212P50
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
(Continued)
CMOS PIN FUNCTION
8, 9
VINN
Analog Input Negative
10, 11
VINP
Analog Input Positive
15
CLKDIV
16
IPTAT
18
RESETN
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN
29
D11
CMOS Bit 11 (MSB) Output
31
D10
CMOS Bit 10 Output
34
D9
CMOS Bit 9 Output
36
D8
CMOS Bit 8 Output
38
D7
CMOS Bit 7 Output
40
D6
CMOS Bit 6 Output
42
D5
CMOS Bit 5 Output
44
D4
CMOS Bit 4 Output
46
RLVDS
48
CLKOUT
CMOS Clock Output
50
D3
CMOS Bit 3 Output
52
D2
CMOS Bit 2 Output
54
D1
CMOS Bit 1 Output
56
D0
CMOS Bit 0 (LSB) Output
64
OR
CMOS Over Range
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
LVDS Bias Resistor (connect to OVSS with 1% 10k)
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
PACKAGE DESCRIPTION
(RoHS Compliant)
PKG.
DWG. #
CARRIER TYPE
TEMP. RANGE
72 Ld QFN
L72.10X10G
Tray
-40 to +85°C
ISLA212P50IRZ
ISLA212P50 IRZ
ISLA214P50IR72EV1Z
14-bit 500MSPS ADC Evaluation Board (This 14-bit ADC evaluation board can be configured for 12-bit testing.)
NOTES:
1. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), see theISLA212P50 device information. For more information about MSL, see TB363.
FN7843 Rev.3.0
Jul 6, 2021
Page 7 of 38
ISLA212P50
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latch up (Tested per JESD-78C; Class 2, Level A . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
23
0.9
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379.
4. For JC, the case temperature location is the center of the exposed metal pad on the package underside.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = 500MSPS. Boldface limits apply across the operating temperature range,
-40°C to +85°C.
ISLA212P50
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
2.0
2.15
VP-P
DC SPECIFICATIONS (Note 6)
ANALOG INPUT
Full-Scale Analog Input Range
VFS
Differential
Input Resistance
RIN
Differential
1.95
300
Ω
Input Capacitance
CIN
Differential
9
pF
Full Scale Range Temp. Drift
AVTC
Full Temp
Input Offset Voltage
VOS
Common-Mode Output Voltage
VCM
0.94
V
Common-Mode Input Current
(per pin)
ICM
2.6
µA/MSPS
Inputs Common Mode Voltage
0.9
V
CLKP, CLKN Input Swing
1.8
V
160
-5.0
-1.3
ppm/°C
5.0
mV
Clock Inputs
POWER REQUIREMENTS
1.8V Analog Supply Voltage
AVDD
1.7
1.8
1.9
V
1.8V Digital Supply Voltage
OVDD
1.7
1.8
1.9
V
1.8V Analog Supply Current
IAVDD
372
391
mA
1.8V Digital Supply Current (Note 6)
IOVDD
3mA LVDS, (I2E powered down,
Fs/4 Filter powered down)
85
95
mA
Power Supply Rejection Ratio
PSRR
30MHz, 45mVP-P signal on AVDD
60
FN7843 Rev.3.0
Jul 6, 2021
dB
Page 8 of 38
ISLA212P50
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = 500MSPS. Boldface limits apply across the operating temperature range,
-40°C to +85°C. (Continued)
ISLA212P50
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
TOTAL POWER DISSIPATION
Normal Mode
PD
Nap Mode
PD
Sleep Mode
PD
Nap/Sleep Mode Wakeup Time
2mA LVDS, (I2E powered down,
Fs/4 Filter powered down)
809
3mA LVDS, (I2E powered down,
Fs/4 Filter powered down)
823
3mA LVDS, (I2E on, Fs/4 Filter off)
858
3mA LVDS, (I2E on, Fs/4 Filter on)
892
943
mW
89
104
mW
7
19
mW
CSB at logic high
Sample Clock Running
mW
875
mW
mW
200
µs
AC SPECIFICATIONS
Differential Nonlinearity
Integral Nonlinearity
DNL
fIN = 105MHz
No Missing Codes
-0.7
±0.16
0.7
INL
fIN = 105MHz
-1.8
±0.7
1.8
LSB
80
MSPS
Minimum Conversion Rate (Note 7)
fS MIN
Maximum Conversion Rate
fS MAX
Signal-to-Noise Ratio (Note 8)
SNR
500
fIN = 30MHz
Effective Number of Bits (Note 8)
SINAD
70.3
dBFS
dBFS
fIN = 190MHz
69.8
dBFS
fIN = 363MHz
68.7
dBFS
fIN = 461MHz
68.1
dBFS
fIN = 605MHz
66.9
dBFS
69.6
dBFS
69.6
dBFS
fIN = 190MHz
68.8
dBFS
fIN = 363MHz
68.1
dBFS
fIN = 461MHz
66.1
dBFS
fIN = 605MHz
62.4
dBFS
67.5
fIN = 30MHz
11.27
Bits
11.27
Bits
fIN = 190MHz
11.14
Bits
fIN = 363MHz
11.02
Bits
fIN = 461MHz
10.69
Bits
fIN = 605MHz
10.07
Bits
fIN = 105MHz
FN7843 Rev.3.0
Jul 6, 2021
68.0
fIN = 30MHz
fIN = 105MHz
ENOB
MSPS
70.3
fIN = 105MHz
Signal-to-Noise and Distortion
(Note 8)
LSB
10.92
Page 9 of 38
ISLA212P50
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = 500MSPS. Boldface limits apply across the operating temperature range,
-40°C to +85°C. (Continued)
ISLA212P50
PARAMETER
SYMBOL
Spurious-Free Dynamic Range
(Note 8)
SFDR
CONDITIONS
SFDRX23
Intermodulation Distortion
IMD
TYP
fIN = 30MHz
MAX
(Note 5)
UNITS
84
dBc
82
dBc
fIN = 190MHz
78
dBc
fIN = 363MHz
76
dBc
fIN = 461MHz
66
dBc
fIN = 605MHz
61
dBc
fIN = 30MHz
88
dBc
fIN = 105MHz
89
dBc
fIN = 190MHz
88
dBc
fIN = 363MHz
83
dBc
fIN = 461MHz
84
dBc
fIN = 605MHz
77
dBc
fIN = 70MHz
88
dBFS
fIN = 170MHz
96
dBFS
fIN = 105MHz
Spurious-Free Dynamic Range
Excluding H2, H3 (Note 8)
MIN
(Note 5)
72
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
700
MHz
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each
digital output.
7. The DLL Range setting must be changed for low-speed operation.
8. Minimum specification guaranteed when calibrated at +85°C.
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
INPUTS (Note 9)
Input Current High (RESETN)
IIH
VIN = 1.8V
Input Current Low (RESETN)
IIL
VIN = 0V
Input Current High (SDIO)
IIH
VIN = 1.8V
Input Current Low (SDIO)
IIL
VIN = 0V
Input Current High (CSB)
IIH
VIN = 1.8V
Input Current Low (CSB)
IIL
VIN = 0V
0
1
10
µA
-25
-12
-8
µA
4
12
µA
-600
-415
-300
µA
40
58
75
µA
5
10
µA
Input Current High (CLKDIV)
IIH
16
25
34
µA
Input Current Low (CLKDIV)
IIL
-34
-25
-16
µA
Input Voltage High (SDIO, RESETN)
VIH
1.17
Input Voltage Low (SDIO, RESETN)
VIL
.63
V
Input Capacitance
CDI
V
4
pF
LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)
Input Common Mode Range
Input Differential Swing (peak-to-peak, single-ended)
FN7843 Rev.3.0
Jul 6, 2021
VICM
825
1575
mV
VID
250
450
mV
Page 10 of 38
ISLA212P50
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
MAX
(Note 5)
TYP
UNITS
CLKDIVRSTP Input Pull-down Resistance
RIpd
100
kΩ
CLKDIVRSTN Input Pull-up Resistance
RIpu
100
kΩ
LVDS OUTPUTS
Differential Output Voltage (Note 10)
Output Offset Voltage
VT
3mA Mode
VOS
3mA Mode
612
1120
mVP-P
1150
1200
mV
Output Rise Time
tR
240
ps
Output Fall Time
tF
240
ps
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
OVDD - 0.3 OVDD - 0.1
V
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
NOTES:
9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
I2E Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
Offset Mismatch-induced Spurious Power
I2E Settling Times
Minimum Duration of Valid Analog Input
Largest Interleave Spur
I2Epost_t
tTE
CONDITIONS
Sample Time Mismatch Between Unit ADCs
Gain Mismatch Between Unit ADCs
Offset Mismatch Between Unit ADCs
FN7843 Rev.3.0
Jul 6, 2021
TYP
MAX
(Note 5)
UNITS
No I2E Calibration performed
-65
dBFS
Active Run state enabled
-70
dBFS
Calibration settling time for
Active Run state
1000
ms
Allow one I2E iteration of Offset,
Gain and Phase correction
100
µs
fIN = 10MHz to 240MHz, Active
Run State enabled, in Track Mode
-99
dBc
-80
dBc
fIN = 260MHz to 490MHz, Active
Run State enabled, in Track Mode
-99
dBc
fIN = 260MHz to 490MHz, Active
Run State enabled and previously
settled, in Hold Mode
-75
dBc
Active Run State enabled, in
Track Mode, fIN is a broadband
signal in the 1st Nyquist zone
-85
dBc
Active Run State enabled, in
Track Mode, fIN is a broadband
signal in the 2nd Nyquist zone
-75
dBc
fIN = 10MHz to 240MHz, Active
Run State enabled and previously
settled, in Hold Mode
Total Interleave Spurious Power
MIN
(Note 5)
Active Run State enabled, in
Track Mode
-75
25
fS
0.01
%FS
1
mV
Page 11 of 38
ISLA212P50
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[11:0]N
DATA N-L
D[11:0]P
DATA N-L+1
DATA N
FIGURE 1A. LVDS
INP
INN
tA
CLK
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
DATA N-L
DATA N-L+1
D[11:0]
DATA N
FIGURE 1B. CMOS
FIGURE 1. TIMING DIAGRAMS
FN7843 Rev.3.0
Jul 6, 2021
Page 12 of 38
ISLA212P50
Switching Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
CONDITION
SYMBOL
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
ADC OUTPUT
Aperture Delay
tA
114
ps
RMS Aperture Jitter
jA
75
fS
Input Clock to Output Clock Propagation
Delay
Relative Input Clock to Output Clock
Propagation Delay (Note 13)
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
tCPD
1.65
2.4
3
ns
AVDD, OVDD = 1.8V, TA = +25°C
tCPD
1.9
2.3
2.75
ns
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
dtCPD
-450
450
ps
tPD
1.65
2.4
3.5
ns
Input Clock to Data Propagation Delay
Output Clock to Data Propagation Delay,
LVDS Mode
Rising/Falling Edge
tDC
-0.1
0.16
0.5
ns
Output Clock to Data Propagation Delay,
CMOS Mode
Rising/Falling Edge
tDC
-0.1
0.2
0.65
ns
Synchronous Clock Divider Reset Setup
Time (With Respect to the Positive Edge of
CLKP)
tRSTS
0.4
0.06
Synchronous Clock Divider Reset Hold Time
(With Respect to the Positive Edge of CLKP)
tRSTH
0.02
tRSTRT
52
µs
L
20
cycles
tOVR
2
cycles
Synchronous Clock Divider Reset Recovery
Time
DLL recovery time after
Synchronous Reset
Latency (Pipeline Delay)
Overvoltage Recovery
ns
0.35
ns
SPI INTERFACE (Notes 11, 12)
SCLK Period
Write Operation
t
CLK
32
cycles
Read Operation
tCLK
32
cycles
CSB to SCLKSetup Time
Read or Write
tS
56
cycles
CSB after SCLK Hold Time
Write
tH
10
cycles
CSB after SCLK↓ Hold Time
Read
tHR
32
cycles
Data Valid to SCLK Setup Time
Write
tDS
12
cycles
Data Valid after SCLK Hold Time
Read or Write
tDH
8
cycles
Data Valid after SCLK↓ Time
Read
tDVR
10
cycles
NOTES:
11. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 2ns sample period, and must be scaled
proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
12. The SPI may operate asynchronously with respect to the ADC sample clock.
13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
FN7843 Rev.3.0
Jul 6, 2021
Page 13 of 38
ISLA212P50
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted:
AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS.
-55
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
95
90
SFDR (EXCLUDING H2,H3)
85
80
SFDR
75
SNR
70
65
60
55
0
100
200
300
400
500
-60
-65
-70
HD2
-75
-80
HD3
-85
-90
-95
600
0
100
INPUT FREQUENCY (MHz)
FIGURE 2. SNR AND SFDR vs fIN
HD2 AND HD3 MAGNITUDE
-40
SNR AND SFDR
70
50
SNR (dBFS)
SFDR (dBc)
40
SNR (dBc)
30
-50
-40
-30
-20
-10
-10
0
HD3 (dBc)
-70
-80
HD2 (dBFS)
-90
-100
HD3 (dBFS)
-50
-40
-30
-20
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
FIGURE 4. SNR AND SFDR vs AIN
FIGURE 5. HD2 AND HD3 vs AIN
90
-75
-80
SFDR
85
HD3
-85
dBc
SNR (dBFS) AND SFDR (dBc)
-60
-120
-60
0
HD2 (dBc)
-50
-110
20
10
-60
600
-30
SFDR (dBFS)
80
60
500
FIGURE 3. HD2 AND HD3 vs fIN
100
90
200
300
400
INPUT FREQUENCY (MHz)
80
-90
HD2
-95
75
-100
SNR
70
250
300
350
400
SAMPLE RATE (MSPS)
450
FIGURE 6. SNR AND SFDR vs fSAMPLE
FN7843 Rev.3.0
Jul 6, 2021
500
-105
250
300
350
400
SAMPLE RATE (MSPS)
450
500
FIGURE 7. HD2 AND HD3 vs fSAMPLE
Page 14 of 38
ISLA212P50
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted:
AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued)
1.00
900
0.75
0.50
DNL (LSBs)
TOTAL POWER (mW)
850
800
750
0.25
0
-0.25
-0.50
700
-0.75
650
250
300
350
400
SAMPLE RATE (MSPS)
450
-1.00
500
0
FIGURE 8. POWER vs fSAMPLE IN 3mA LVDS MODE
500
1000
1500
2000 2500
CODE
3000
3500
4000
1.10
1.15
FIGURE 9. DIFFERENTIAL NONLINEARITY
1.0
90
SNR (dBFS) AND SFDR (dBc)
0.8
0.6
INL (LSBs)
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
500
1000
1500
2000 2500
CODE
3000
3500
85
80
75
70
65
60
0.75
4000
FIGURE 10. INTEGRAL NONLINEARITY
AMPLITUDE (dBFS)
160,000
NUMBER OF HITS
0.90
0.95
1.00
VCM (V)
1.05
0
182,936
180,000
140,000
120,000
100,000
80,000
60,000
40,000
0
0.85
FIGURE 11. SNR AND SFDR vs VCM
200,000
20,000
0.80
AIN = -1.0 dBFS
SNR = 70.4 dBFS
-20 SFDR = 81.1 dBc
SINAD = 69.8 dBFS
-40
-60
-80
-100
0
0
2042
2043
10,849
2044
6,212
2045 2046
CODE
3
0
0
2047
2048
2049
FIGURE 12. NOISE HISTOGRAM
FN7843 Rev.3.0
Jul 6, 2021
-120
0
50
100
150
FREQUENCY (MHz)
200
250
FIGURE 13. SINGLE-TONE SPECTRUM @ 105MHz
Page 15 of 38
ISLA212P50
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted:
AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued)
0
AIN = -1.0 dBFS
SNR = 69.9 dBFS
-20 SFDR = 78.4 dBc
SINAD = 69.0 dBFS
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
-40
-60
-80
-40
-60
-80
-100
-100
-120
AIN = -1.0 dBFS
SNR = 69.1 dBFS
-20 SFDR = 75.4 dBc
SINAD = 68.1 dBFS
0
50
100
150
FREQUENCY (MHz)
200
-120
250
-40
-60
-80
IMD3 = -88 dBFS
0
50
100
150
200
-60
-80
-120
250
IMD3 = -96 dBFS
0
50
100
100
FIS (INTERLEAVING SPUR)
95
FIS IS APPROX. 96dB
BELOW FULL SCALE
AT CAL FREQUENCY
90
85
80
SFDR
75
70
SNR
30
50
70
90
110 130 150 170 190 210 230 250
FREQUENCY (MHz)
FIGURE 18. INPUT FREQUENCY SWEEP WITH I2E FROZEN, I2E
PREVIOUSLY CALIBRATED AT 105MHZ
FN7843 Rev.3.0
Jul 6, 2021
150
200
250
FREQUENCY (MHz)
FIGURE 17. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz
-7dBFS)
SNR (dBFS), SFDR (dBc) AND FIS (dBc)
FIGURE 16. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz
-7dBFS)
SNR (dBFS), SFDR (dBc) AND FIS (dBc)
250
-40
FREQUENCY (MHz)
65
200
-100
-100
-120
100
150
FREQUENCY (MHz)
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
-20
50
FIGURE 15. SINGLE-TONE SPECTRUM @ 363MHz
FIGURE 14. SINGLE-TONE SPECTRUM @ 190MHz
0
0
100
FIS IS APPROX. 97dB
BELOW FULL SCALE
AT CAL FREQUENCY
95
90
85
FIS (INTERLEAVING SPUR)
80
75
SFDR
70
SNR
65
60
250
300
350
400
FREQUENCY (MHz)
450
500
FIGURE 19. INPUT FREQUENCY SWEEP WITH I2E FROZEN, I2E
PREVIOUSLY CALIBRATED AT 363MHZ
Page 16 of 38
ISLA212P50
Typical Performance Curves
SNR (dBFS) AND SFDR (dBc)
85
SNR (dBFS), SFDR (dBc) AND FIS (dBc)
All Typical Performance Characteristics apply under the following conditions unless otherwise noted:
AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 500MSPS. (Continued)
SFDR IS DETERMINED BY FIS
(INTERLEAVING SPUR)
80
SFDR (= FIS)
75
70
SNR
65
60
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 20. TEMPERATURE SWEEP WITH I2E FROZEN, I2E
PREVIOUSLY CALIBRATED AT +25°C, fIN= 105MHZ
100
95
90
FIS
85
SFDR
80
75
70
SNR
65
1.70
1.75
1.80
1.85
1.90
SUPPLY VOLTAGE (AVDD)
FIGURE 21. ANALOG SUPPLY VOLTAGE SWEEP WITH I2E FROZEN,
I2E PREVIOUSLY CALIBRATED AT 1.8V, fIN= 105MHZ
Theory of Operation
Power-On Calibration
Functional Description
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully:
The ISLA212P50 is based upon a 12-bit, 250MSPS A/D converter
core that utilizes a pipelined successive approximation
architecture (see Figure 22). The input voltage is captured by a
Sample-Hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. Digital error correction is also
applied, resulting in a total latency of 20 clock cycles. This is
evident to the user as a latency between the start of a conversion
and the data being available on the digital outputs.
The device contains two core A/D converters with carefully
matched transfer characteristics. The cores are clocked on
alternate clock edges, resulting in a doubling of the sample rate.
Time–interleaved A/D systems can exhibit non–ideal artifacts in
the frequency domain if the individual core A/D characteristics
are not well matched. Gain, offset and timing skew mismatches
are of primary concern.
The Interleave Engine (I2E) performs automatic interleave
calibration for the offset, gain, and sample time skew mismatch
between the core A/Ds. The I2E circuitry also adjusts in real-time
for temperature and voltage variations.
Residual gain and sample time skew mismatch result in
fundamental image spurs at fNYQUIST ± fIN. Offset mismatches
create spurs at DC and multiples of fNYQUIST.
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins.
• DNC pins must not be connected.
• SDO has an internal pull-up and should not be driven
externally.
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
• SPI communications must not be attempted.
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 23. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs output 0xCCCC during calibration;
this can also be used to determine calibration status.
While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is
set low. Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is de-asserted.
At 250MSPS the nominal calibration time is 200ms, while the
maximum calibration time is 550ms.
FN7843 Rev.3.0
Jul 6, 2021
Page 17 of 38
ISLA212P50
CLOCK
GENERATION
INP
SHA
INN
1.25V
2.5-BIT
2.5-BIT
FLASH
FLASH
+
–
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1- BIT/ STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/ LVCMOS
OUTPUTS
FIGURE 22. A/D CORE BLOCK DIAGRAM
CLKN
CLKP
CALIBRATION
TIME
RESETN
CALIBRATION
BEGINS
CAL_STATUS
BIT
CALIBRATION
COMPLETE
CLKOUTP
Figures 24 through 26 show the effect of temperature on SNR
and SFDR performance with power on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated earlier. Applications working
across the full temperature range can use the on-chip calibration
feature to maximize performance when large temperature
variations are expected.
FIGURE 23. CALIBRATION TIMING
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength in its high impedance
state of less than 0.5mA is recommended, as RESETN has an
internal high impedance pull-up to OVDD. As is the case during
power-on reset, RESETN and DNC pins must be in the proper
state for the calibration to successfully execute.
The performance of the ISLA212P50 changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the A/D under the environmental conditions at
which it will operate.
A supply voltage variation of less than 100mV will generally
result in an SNR change of less than 0.5dBFS and SFDR change
of less than 3dBc.
In situations where the sample rate is not constant, best results
will be obtained if the device is calibrated at the highest sample
rate. Reducing the sample rate by less than 80MSPS will typically
result in an SNR change of less than 0.5dBFS and an SFDR
change of less than 3dBc.
FN7843 Rev.3.0
Jul 6, 2021
Page 18 of 38
ISLA212P50
Temperature Calibration
90
90
SFDR (dBc)
SFDR (dBc)
85
SNR AND SFDR
SNR AND SFDR
85
80
80
75
75
SNR (dBFS)
70
-40
-35
-30
TEMPERATURE (°C)
SNR (dBFS)
-25
-20
5
10
15
20
25
30
35
40
45
TEMPERATURE (°C)
FIGURE 25. TYPICAL SNR, SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, 500MSPS OPERATION,
fIN = 105MHz
FIGURE 24. TYPICAL SNR, SFDR PERFORMANCE vs
TEMPERATURE,DEVICE CALIBRATED AT -40°C,
500MSPS OPERATION, fIN = 105MHz
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs as shown in Figures 28 through 30.
An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate frequency (IF)
inputs. Two different transformer input schemes are shown in
Figures 28 and 29.
83
SFDR (dBc)
SNR AND SFDR
70
78
ADT1-1WT
73
SNR (dBFS)
ADT1-1WT
1000pF
A/D
VCM
68
65
70
75
80
85
TEMPERATURE (°C)
FIGURE 26. TYPICAL SNR, SFDR PERFORMANCE vs
TEMPERATURE, DEVICE CALIBRATED AT +85°C,
500MSPS OPERATION, fIN = 105MHz
Analog Input
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit A/D. The ideal
full-scale input voltage is 2.0V, centered at the VCM voltage of
0.94V as shown in Figure 27.
VINN
1.8
VINP
1.4
1.0
1.0V
VCM
0.94V
0.6
0.2
FIGURE 27. ANALOG INPUT RANGE
FN7843 Rev.3.0
Jul 6, 2021
0.1µF
FIGURE 28. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
ADTL1-12
1000pF
TX-2-5-1
A/D
VCM
1000pF
FIGURE 29. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA212P50 is 300. The
SHA design uses a switched capacitor input stage (see Figure 43
on page 35), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
Page 19 of 38
ISLA212P50
settling and improved performance. Therefore a 1:1 transformer
and low shunt resistance are recommended for optimal
performance.
A/D
Clock Input
The clock input circuit is a differential pair (see Figure 44).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, it is recommended to have high
slew rate at the zero crossing of the differential clock input
signal.
The recommended drive circuit is shown in Figure 31. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
1000pF
CLKP
200
CLKN
1000pF
1000pF
FIGURE 31. RECOMMENDED CLOCK DRIVE
A selectable 2x frequency divider is provided in series with the
clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate. This allows
the use of the Phase Slip feature, which enables synchronization
of multiple ADCs. The Phase Slip feature can be used as an
alternative to using the CLKDIVRST pins to synchronize ADCs in a
multiple ADC system.
FN7843 Rev.3.0
Jul 6, 2021
DIVIDE RATIO
AVSS
2
Float
1
AVDD
Not Allowed
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (tJ) and SNR is shown in Equation 1 and is
illustrated in Figure 32.
(EQ. 1)
100
95
tj = 0.1ps
90
14 BITS
85
SNR (dB)
A differential amplifier, as shown in the simplified block diagram
in Figure 30, can be used in applications that require
DC-coupling. In this configuration, the amplifier will typically
dominate the achievable SNR and distortion performance. The
ISL552xx differential amplifier family can also be used in certain
AC applications with minimal performance degradation.
0.01µF
CLKDIV PIN
1
SNR = 20 log 10 --------------------
2f t
IN J
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
TC4-19G2+
TABLE 1. CLKDIV PIN SETTINGS
80
tj = 1ps
75
12 BITS
70
tj = 10ps
65
60
55
50
10 BITS
tj = 100ps
1M
10M
100M
INPUT FREQUENCY (Hz)
1G
FIGURE 32. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure 1A. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this determines
the total jitter in the system. The total jitter, combined with other
noise sources, then determines the achievable SNR.
Voltage Reference
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional to the
reference voltage. The nominal value of the voltage reference is
1.25V.
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible
(default) or CMOS modes. In either case, the data is presented in
double data rate (DDR) format. Figure 1 shows the timing
relationships for LVDS and CMOS modes, respectively.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA(default) or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the A/D. The applicability of this setting is
Page 20 of 38
ISLA212P50
dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
BINARY
11
10
9
The output mode can be controlled through the SPI port, by
writing to address 0x73, see “Serial Peripheral Interface” on
page 25.
An external resistor creates the bias for the LVDS drivers. A 10k,
1% resistor must be connected from the RLVDS pin to OVSS.
1
0
••••
GRAY CODE
Power Dissipation
The power dissipated by the ISLA212P50 is primarily dependent
on the sample rate and the output modes: LVDS vs CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock frequency in
CMOS mode.
••••
11
10
••••
9
1
0
FIGURE 33. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 34.
GRAY CODE
11
10
9
••••
1
0
Nap/Sleep
Portions of the device may be shutdown to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to less than 104mW while Sleep mode reduces power
dissipation to less than 19mW.
••••
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 500MSPS.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
••••
BINARY
11
10
9
••••
1
0
Mapping of the input voltage to the various data formats is
shown in Table 3.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 25.
–Full Scale
0000 0000 0000
1000 0000 0000
0000 0000 0000
–Full Scale
+ 1LSB
0000 0000 0001
1000 0000 0001
0000 0000 0001
Data Format
Mid–Scale
1000 0000 0000
0000 0000 0000
1100 0000 0000
Output data can be presented in three formats: two’s
complement (default), Gray code and offset binary. The data
format can also be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 25.
+Full Scale
– 1LSB
1111 1111 1110
0111 1111 1110
1000 0000 0001
+Full Scale
1111 1111 1111
0111 1111 1111
1000 0000 0000
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation. When calculating Gray code
the MSB is unchanged. The remaining bits are computed as the
XOR of the current bit position and the next most significant bit.
Figure 33 shows this operation.
FN7843 Rev.3.0
Jul 6, 2021
Page 21 of 38
ISLA212P50
I2E Requirements and
Restrictions
Overview
I2E is a blind and background capable algorithm, designed to
transparently eliminate interleaving artifacts. This circuitry
eliminates interleave artifacts due to offset, gain, and sample time
mismatches between unit A/Ds, and across supply voltage and
temperature variations in real-time.
Differences in the offset, gain, and sample times of
time-interleaved A/Ds create artifacts in the digital outputs. Each
of these artifacts creates a unique signature that may be
detectable in the captured samples. The I2E algorithm optimizes
performance by detecting error signatures and adjusting each
unit A/D using minimal additional power.
2. Hold Mode refers to the state of the I2E algorithm when the
analog input signal does not meet the requirements specified
above. If the algorithm detects that the signal no longer
meets the criteria, it automatically enters Hold Mode. In Hold
Mode, the I2E circuitry freezes the adjustment values based
on the most recent set of valid input conditions. However, in
Hold Mode, the I2E circuitry will not correct for new changes
in interleave artifacts induced by supply voltage and
temperature changes. The I2E circuitry will remain in Hold
Mode until such time as the analog input signal meets the
requirements for Track Mode.
Power Meter
The power meter calculates the average power of the analog
input, and determines if it’s within range to allow operation in
Track Mode. Both AC RMS and total RMS power are calculated,
and there are separate SPI programmable thresholds and
hysteresis values for each.
I2E calibration is off by default at power-up. The I2E algorithm
can be put in Active Run state via SPI. When the I2E algorithm is
in Active Run state, it detects and corrects for offset, gain, and
sample time mismatches in real time (see Track Mode
description under “Active Run State” on page 22). However,
certain analog input characteristics can obscure the estimation
of these mismatches. The I2E algorithm is capable of detecting
these obscuring analog input characteristics, and as long as they
are present I2E will stop updating the correction in real time.
Effectively, this freezes the current correction circuitry to the last
known-good state (see Hold Mode description under “Active Run
State” on page 22). Once the analog input signal stops obscuring
the interleaved artifacts, the I2E algorithm will automatically
start correcting for mismatch in real time again.
A digital filter removes the signal energy in a 100kHz band
around fS/4 before the I2E circuitry uses these samples for
estimating offset, gain, and sample time mismatches (data
samples produced by the A/D are unaffected by this filtering).
This allows the I2E algorithm to continue in Active Run state
while in the presence of a large amount of input energy near the
fS/4 frequency. This filter can be powered down if it’s known that
the signal characteristics won’t violate the restrictions. Powering
down the FS/4 filter will reduce power consumption by
approximately 30mW.
Active Run State
Nyquist Zones
During the Active Run state the I2E algorithm actively suppresses
artifacts due to interleaving based on statistics in the digitized
data. I2E has two modes of operation in this state (described in
the following), dynamically chosen in real-time by the algorithm
based on the statistics of the analog input signal.
The I2E circuitry allows the use of any one Nyquist zone without
configuration, but requires the use of only one Nyquist zone.
Inputs that switch dynamically between Nyquist zones will cause
poor performance for the I2E circuitry. For example, I2E will
function properly for a particular application that has
fS=500MSPS and uses the 1st Nyquist zone (0MHz to 250MHz).
I2E will also function properly for an application that uses
fS = 500MSPS and the 2nd Nyquist zone (250MHz to 500MHz).
I2E will not function properly for an application that uses
fS = 500MSPS, and input frequency bands from 150MHz to
210MHz and 250MHz to 290MHz simultaneously. There is no
need to configure the I2E algorithm to use a particular Nyquist
zone, but no dynamic switching between Nyquist zones is
permitted while I2E is running.
1. Track Mode refers to the default state of the algorithm, when
all artifacts due to interleaving are actively being eliminated.
To be in Track Mode the analog input signal to the device must
adhere to the following requirements:
• Possess total power greater than -20dBFS, integrated from
1MHz to Nyquist but excluding signal energy in a 100kHz band
centered at fS/4
The criteria above assumes 500MSPS operation; the frequency
bands should be scaled proportionally for lower sample rates.
Note that the effect of excluding energy in the 100kHz band
around of fS/4 exists in every Nyquist zone. This band generalizes
to the form (N*fS/4 - 50kHz) to (N*fS/4 + 50kHz), where N is any
odd integer. An input signal that violates these criteria briefly
(approximately 10µs), before and after which it meets this
criteria, will not impact system performance.
The algorithm must be in Track Mode for approximately one
second (defined as I2Epost_t on “I2E Specifications” on page 11)
after power-up before the specifications apply. Once this
requirement has been met, the specifications of the device will
continue to be met while I2E remains in Track Mode, even in the
presence of temperature and supply voltage changes.
FN7843 Rev.3.0
Jul 6, 2021
FS/4 Filter (Notch)
Configurability and Communication
I2E can respond to status queries, be turned on and turned off,
and generally configured via SPI programmable registers.
Configuring of I2E is generally unnecessary unless the
application cannot meet the requirements of Track Mode on or
after power up. Parameters that can be adjusted and read back
include Fs/4 filter threshold and status, Power Meter threshold
and status, and initial values for the offset, gain, and sample
time values to use when I2E starts.
Page 22 of 38
ISLA212P50
Clock Divider Synchronous Reset
An output clock (CLKOUTP, CLKOUTN) is provided to facilitate
latching of the sampled data. This clock is at half the frequency
of the sample clock, and the absolute phase, relative to the
sample clock, is initially indeterminate. The clock divider
synchronous reset allows the phase of the output clock of
multiple A/Ds to be synchronized (refer to Figure 35), which
greatly simplifies data capture in systems employing multiple
A/Ds. The reset signal must be well-timed with respect to the
sample clock (see “Switching Specifications” Table on page 13).
A 100Ω differential termination resistor must be supplied
between CLKDIVRSTP and CLKDIVRSTN, external to the ADC, (on
the PCB) and should be located as close to the CLKDIVRSTP/N
pins as possible.
SAMPLE CLOCK
INPUT
s1
L+td
ANALOG INPUT
(Note 14)
s2
tRSTH
CLKDIVRSTP
(Note 15)
tRSTS
tRSTRT
ADC1 OUTPUT DATA
s0
s1
s2
s3
s0
s1
s2
s3
ADC1 CLKOUTP
ADC2 OUTPUT DATA
ADC2 CLKOUTP
(PHASE 1) (Note 16)
ADC2 CLKOUTP
(PHASE 2) (Note 16)
NOTES:
14. Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay, td
15. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge. CLKDIVRSTN is not shown,
but must be driven, and is the complement of CLKDIVRSTP.
16. Either Output Clock Phase (phase 1 or phase 2) equally likely prior to synchronization.
FIGURE 35. SYNCHRONOUS RESET OPERATION
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 36. MSB-FIRST ADDRESSING
FN7843 Rev.3.0
Jul 6, 2021
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ISLA212P50
CSB
SCLK
SDIO
A0
A1
A11
A2
A12
W0
W1
R/W
D1
D0
D2
D3
D4
D5
D6
D7
FIGURE 37. LSB-FIRST ADDRESSING
tDSW
CSB
tDHW
tS
t CLK
tHI
tH
tLO
SCLK
SDIO
W1
R/W
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
SPI WRITE
FIGURE 38. SPI WRITE
tDSW
CSB
tCLK
tHI
tS
tDHW
tHR
tDVR
tLO
SCLK
WRITING A READ COMMAND
SDIO
R/W
W1
W0
A12
A11
A10
A9
A2
A1
READING DATA ( 3 WIRE MODE )
A0
D7 D6
D3
D2
D1 D0
( 4 WIRE MODE)
SDO
D7
D3
D2
D1 D0
FIGURE 39. SPI READ
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 40. 2-BYTE TRANSFER
FN7843 Rev.3.0
Jul 6, 2021
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ISLA212P50
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 41. N-BYTE TRANSFER
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The SPI
bus consists of chip select (CSB), serial clock (SCLK) serial data
output (SDO), and serial data input/output (SDIO). The maximum
SCLK rate is equal to the A/D sample rate (fSAMPLE) divided by 32
for both write operations and read operations. At
fSAMPLE = 500MHz, maximum SCLK is 15.63MHz for writing and
read operations. There is no minimum SCLK rate.
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described in the following). A dedicated serial data output pin
(SDO) can be activated by setting 0x00[7] high to allow operation
in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the ISLA212P50 functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an unaddressed
device is asserted in four wire mode.
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high to low
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 36 and 37 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
FN7843 Rev.3.0
Jul 6, 2021
MSB-first mode, the address is incremented for multi-byte
transfers, while in LSB-first mode it is decremented.
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 4). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 38,
and timing values are given in “Switching Specifications on
page 13.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
A/D (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed to stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
TABLE 4. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
Figures 40 and 41 on page 24 illustrate the timing relationships
for 2-byte and N-byte transfers, respectively. The operation for a
3-byte transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various micro controllers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
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ISLA212P50
ADDRESS 0X22: GAIN_COARSE__ADC0
Bit 4 Reserved
This bit should always be set high.
Bits 3:0
These bits should always mirror bits 4:7 to avoid ambiguity in bit
ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing.
Setting the burst_end address determines the end of the
transfer; during a write operation, the user must be cautious to
transmit the correct number of bytes based on the starting and
ending addresses.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
Device Information
ADDRESS 0X23: GAIN_MEDIUM_ADC0
ADDRESS 0X24: GAIN_FINE_ADC0
Gain of the A/D core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse gain bits can be set for a total
adjustment range of ±4.2%. (‘0011’ -4.2% and ‘1100’ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 23h and 24h.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x23 and 0x24 to be used by the
ADC (see Address 0XFE: Offset/Gain_adjust_enable on page 30).
TABLE 6. COARSE GAIN ADJUSTMENT
ADDRESS 0X08: CHIP_ID
0x22[3:0] core 0
0x26[3:0] core 1
NOMINAL COARSE GAIN ADJUST
(%)
The generic die identifier and a revision number, respectively, can
be read from these two registers.
Bit3
+2.8
Bit2
+1.4
Device Configuration/Control
Bit1
-2.8
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Renesas A/D products.
Bit0
-1.4
ADDRESS 0X09: CHIP_VERSION
TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS
ADDRESS 0X20: OFFSET_COARSE_ADC0
ADDRESS 0X21: OFFSET_FINE_ADC0
The input offset of the A/D core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is twos complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x20 and 0x21 to be used by the
ADC (see Address 0XFE: Offset/Gain_adjust_enable on page 30).
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
ADDRESS 0X25: MODES
PARAMETER
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
Steps
255
255
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to“Nap/Sleep” on page 21). This functionality
can be overridden and controlled through the SPI. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin. This register is not changed by
a Soft Reset.
–Full Scale (0x00)
-133LSB (-47mV)
-5LSB (-1.75mV)
TABLE 8. POWER-DOWN CONTROL
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
+Full Scale (0xFF)
+133LSB (+47mV)
+5LSB (+1.75mV)
VALUE
0x25[2:0]
POWER DOWN MODE
Nominal Step Size
1.04LSB (0.37mV)
0.04LSB (0.014mV)
000
Pin Control
001
Normal Operation
TABLE 5. OFFSET ADJUSTMENTS
FN7843 Rev.3.0
Jul 6, 2021
010
Nap Mode
100
Sleep Mode
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ISLA212P50
ADDRESS 0X26: OFFSET_COARSE_ADC1
ADDRESS 0X31: I2E CONTROL
ADDRESS 0X27: OFFSET_FINE_ADC1
The I2E general control register. This register can be written while
I2E is running to control various parameters.
The input offset of A/D core#1 can be adjusted in fine and
coarse steps in the same way that offset for core#0 can be
adjusted. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is two’s complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x26 and 0x27 to be used by the
ADC (see Address 0XFE: Offset/Gain_adjust_enable on page 30).
ADDRESS 0X28: GAIN_COARSE__ADC1
ADDRESS 0X29: GAIN_MEDIUM_ADC1
ADDRESS 0X2A: GAIN_FINE_ADC1
Gain of A/D core #1 can be adjusted in coarse, medium and fine
steps in the same way that core #0 can be adjusted. Coarse gain is
a 4-bit adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment range of ±4.2.
Bit 0 in register 0xFE must be set high to enable updates written to
0x29 and 0x2A to be used by the ADC
(see Address 0XFE: Offset/Gain_adjust_enable on page 30).
ADDRESS 0X30: I2E STATUS
The I2E general status register.
Bits 0 and 1 indicate if the I2E circuitry is in Active Run or Hold
state. The state of the I2E circuitry is dependent on the analog
input signal itself. If the input signal obscures the interleave
mismatched artifacts such that I2E cannot estimate the
mismatch, the algorithm will dynamically enter the Hold state.
For example, a DC mid-scale input to the A/D does not contain
sufficient information to estimate the gain and sample time
skew mismatches, and thus the I2E algorithm will enter the Hold
state. In the Hold state, the analog adjustments for interleave
correction will be frozen and mismatch estimate calculations will
cease until such time as the analog input achieves sufficient
quality to allow the I2E algorithm to make mismatch estimates
again.
Bit 0: 0 = I2E has not detected a low power condition. 1 = I2E has
detected a low power condition, and the analog adjustments for
interleave correction are frozen.
Bit 1: 0 = I2E has not detected a low AC power condition. 1 = I2E
has detected a low AC power condition, and I2E will continue to
correct with best known information but will not update its
interleave correction adjustments until the input signal achieves
sufficient AC RMS power.
Bit 2: When first started, the I2E algorithm can take a significant
amount of time to settle (~1s), dependent on the characteristics
of the analog input signal. 0 = I2E is still settling, 1 = I2E has
completed settling.
FN7843 Rev.3.0
Jul 6, 2021
Bit 0: 0 = turn I2E off, 1= turn I2E on
Bit 1: 0 = no action, 1 = freeze I2E, leaving all settings in the
current state. Subsequently writing a 0 to this bit will allow I2E to
continue from the state it was left in.
Bit 2-4: Disable any of the interleave adjustments of offset, gain,
or sample time skew.
Bit 5: 0 = bypass notch (Fs/4) filter, 1 = use notch filter on
incoming data before estimating interleave mismatch terms.
ADDRESS 0X32: I2E STATIC CONTROL
The I2E general static control register. This register must be
written prior to turning I2E on for the settings to take effect.
Bit 1-4: Reserved, always set to 0
Bit 5: 0 = normal operation, 1 = skip coarse adjustment of the
offset, gain, and sample time skew analog controls when I2E is
first turned on. This bit would typically be used if optimal analog
adjustment values for offset, gain, and sample time skew have
been preloaded in order to have the I2E algorithm converge more
quickly.
The system gain of the pair of interleaved core A/Ds can be set
by programming the medium and fine gain of the reference A/D
before turning I2E on. In this case, I2E will adjust the nonreference A/D’s gain to match the reference A/D’s gain.
Bit 7: Reserved, always set to 0
ADDRESS 0X4A: I2E POWER DOWN
This register provides the capability to completely power down
the I2E algorithm and the Notch (Fs/4) filter. This would typically
be done to conserve power.
BIT 0: Power down the I2E Algorithm
BIT 1: Power down the Notch (Fs/4) Filter
ADDRESS 0X50-0X55: I2E FREEZE THRESHOLDS
This group of registers provides programming access to configure
I2E’s dynamic freeze control. As with any interleave mismatch
correction algorithm making estimates of the interleave
mismatch errors using the digitized application input signal,
there are certain characteristics of the input signal that can
obscure the mismatch estimates. For example, a DC input to the
A/D contains no information about the sample time skew
mismatch between the core A/Ds, and thus should not be used
by the I2E algorithm to update its sample time skew estimate.
Under such circumstances, I2E enters Hold state. In the Hold
state, the analog adjustments will be frozen and mismatch
estimate calculations will cease until such time as the analog
input achieves sufficient quality to allow the I2E algorithm to
make mismatch estimates again.
These registers allow the programming of the thresholds of the
meters used to determine the quality of the input signal. This can
be used by the application to optimize I2E’s behavior based on
knowledge of the input signal. For example, if a specific
Page 27 of 38
ISLA212P50
application had an input signal that was typically 30dB down
from full scale, and was primarily concerned about analog
performance of the A/D at this input power, lowering the RMS
power threshold would allow I2E to continue tracking with this
input power level, thus allowing it to track over voltage and
temperature changes.
sample time skew between the core A/Ds can be determined
from the digitized samples. The AC RMS Power Meter is
implemented as a high-passed (via DSP) RMS power meter.
0x50 (LSBs), 0x51 (MSBs) RMS Power Threshold
2. Write the LSBs of the 16-bit quantity to SPI Address 0x53
This 16-bit quantity is the RMS power threshold at which I2E will
enter Hold state. The RMS power of the analog input is calculated
continuously by I2E on incoming data.
Only the upper 12-bit of the ADC sample outputs are used in the
averaging process for comparison to the power threshold
registers. A 12-bit number squared produces a 24-bit result (for
A/D resolutions under 12-bit, the A/D samples are MSB-aligned
to 12-bit data). A dynamic number of these 24-bit results are
averaged to compare with this threshold approximately every
1µs to decide whether or not to freeze I2E. The 24-bit threshold is
constructed with bits 23 through 20 (MSBs) assigned to 0, bits
19 through 4 assigned to this 16-bit quantity, and bits 3 through
0 (LSBs) assigned to 0. The calculation methodology to set this
register is identical to the description in the RMS power threshold
description.
Only the upper 12 bits of the ADC sample outputs are used in the
averaging process for comparison to the power threshold
registers. A 12-bit number squared produces a 24-bit result (for
A/D resolutions under 12-bits, the A/D samples are MSB-aligned
to 12-bit data). A dynamic number of these 24-bit results are
averaged to compare with this threshold approximately every
1µs to decide whether or not to freeze I2E. The 24-bit threshold is
constructed with bits 23 through 20 (MSBs) assigned to 0, bits
19 through 4 assigned to this 16-bit quantity, and bits 3 through
0 (LSBs) assigned to 0. As an example, if the application wanted
to set this threshold to trigger near the RMS analog input of a
-20dBFS sinusoidal input, the calculation to determine this
register’s value would be:
20
–---------
20
12
2
RMS codes = ------- 10
2 290 codes
2
(EQ. 2)
2
hex 290 = 0x14884 TruncateMSBandLSBhexdigit = 0x1488
(EQ. 3)
Therefore, programming 0x1488 into these two registers will
cause I2E to freeze when the signal being digitized has less RMS
power than a -20dBFS sinusoid.
The default value of this register is 0x1000, causing I2E to freeze
when the input amplitude is less than -21.2 dBFS.
The freezing of I2E by the RMS power meter threshold affects the
gain and sample time skew interleave mismatch estimates, but
not the offset mismatch estimate.
0x52 RMS Power Hysteresis
In order to prevent I2E from constantly oscillating between the
Hold and Track state, there is hysteresis in the comparison
described above. After I2E enters a frozen state, the RMS input
power must achieve ³ threshold value + hysteresis to again enter
the Track state. The hysteresis quantity is a 24-bit value,
constructed with bits 23 through 12 (MSBs) being assigned to 0,
bits 11 through 4 assigned to this register’s value, and bits 3
through 0 (LSBs) assigned to 0.
The required algorithm is documented as follows.
1. Write the MSBs of the 16-bit quantity to SPI Address 0x54
The freezing of I2E when the AC RMS power meter threshold is
not met affects the sample time skew interleave mismatch
estimate, but not the offset or gain mismatch estimates.
0x55 AC RMS Power Hysteresis
In order to prevent I2E from constantly oscillating between the
Hold and Track state, there is hysteresis in the comparison
described above. After I2E enters a frozen state, the AC RMS input
power must achieve threshold value + hysteresis to again enter the
Track state. The hysteresis quantity is a 24-bit value, constructed
with bits 23 through 12 (MSBs) being assigned to 0, bits 11
through 4 assigned to this register’s value, and bits 3 through 0
(LSBs) assigned to 0.
Address 0x60-0x64: I2E initialization
These registers provide access to the initialization values for
each of offset, gain, and sample time skew that I2E programs
into the target core A/D before adjusting to minimize interleave
mismatch. They can be used by the system to, for example,
reduce the convergence time of the I2E algorithm by
programming in the optimal values before turning I2E on. In this
case, I2E only needs to adjust for temperature and
voltage-induced changes since the optimal values were recorded.
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing skew
between the two A/D cores. The nominal range and resolution of
this adjustment are given in Table 9. The default value of this
register after power-up is 80h.
0X53(LSBS), 0X54(MSBS) AC RMS POWER
THRESHOLD
Similar to RMS power threshold, there must be sufficient AC RMS
power (or dV/dt) of the input signal to measure sample time
skew mismatch for an arbitrary input. This is clear from
observing the effect when a high voltage (and therefore large
RMS value) DC input is applied to the A/D input. Without
sufficient dV/dt in the input signal, no information about the
FN7843 Rev.3.0
Jul 6, 2021
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ISLA212P50
TABLE 9. DIFFERENTIAL SKEW ADJUSTMENT
Data can be coded in three possible formats: two’s complement
(default), Gray code or offset binary. See Table 12.
PARAMETER
0x70[7:0]
DIFFERENTIAL SKEW
Steps
256
–Full Scale (0x00)
-6.5ps
Mid–Scale (0x80)
0.0ps
VALUE
0x73[7:5]
OUTPUT MODE
+Full Scale (0xFF)
+6.5ps
000
LVDS 3mA (Default)
Nominal Step Size
51fs
001
LVDS 2mA
100
LVCMOS
This register is not changed by a Soft Reset.
TABLE 11. OUTPUT MODE CONTROL
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the A/D
input sample clock. Some systems with multiple A/Ds can more
easily latch the data from each A/D by controlling the phase of
the output data clock. This control is accomplished through the
use of the phase_slip SPI feature, which allows the rising edge of
the output data clock to be advanced by one input clock period,
as shown in the Figure 42. Execution of a phase_slip command is
accomplished by first writing a '0' to bit 0 at address 0x71,
followed by writing a '1' to bit 0 at address 0x71.
TABLE 12. OUTPUT FORMAT CONTROL
VALUE
0x73[2:0]
OUTPUT FORMAT
000
Two’s Complement (Default)
010
Gray Code
100
Offset Binary
ADDRESS 0X74: OUTPUT_MODE_B
ADC INPUT
CLOCK (500MHZ)
Bit 6 DLL Range
2ns
OUTPUT DATA
CLOCK (250MHZ)
NO CLOCK_SLIP
4ns
2ns
OUTPUT DATA
CLOCK (250MHZ)
1 CLOCK_SLIP
OUTPUT DATA
CLOCK (250MHZ)
2 CLOCK_SLIP
TABLE 13. DLL RANGES
FIGURE 42. PHASE SLIP
ADDRESS 0X72: CLOCK_DIVIDE
The ISLA212P50 has a selectable clock divider that can be set to
divide by two or one (no division). By default, the tri-level CLKDIV
pin selects the divisor This functionality can be overridden and
controlled through the SPI, as shown in Table 10. This register is
not changed by a Soft Reset.
TABLE 10. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
other
Not Allowed
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The ISLA212P50 can
present output data in two physical formats: LVDS (default) or
LVCMOS. Additionally, the drive strength in LVDS mode can be set
high (default, 3mA or low (2mA).
FN7843 Rev.3.0
Jul 6, 2021
This bit sets the DLL operating range to fast (default) or slow.
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 13 shows the allowable
sample rate ranges for the slow and fast settings. Note that Bit 4
at 0x74 is reserved and must not change value. A user writing to
Bit 6 should first read 0x74 to determine proper value to write
back to Bit 4 when writing to 0x74.
DLL RANGE
MIN
MAX
UNIT
Slow
80
200
MSPS
Fast
160
500
MSPS
ADDRESS 0XB6: CALIBRATION STATUS
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete.This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which can’t be read until calibration is complete.
DEVICE TEST
The ISLA212P50 can produce preset or user defined patterns on
the digital outputs to facilitate in-situ testing. A user can pick
from preset built-in patterns by writing to the output test mode
field [7:4] at C0h or user defined patterns by writing to the user
test mode field [2:0] at C0h. The user defined patterns should be
loaded at address space C1 through D0, see the “SPI Memory
Map” on page 31 for more detail. The predefined patterns are
shown in Table 14. The test mode is enabled asynchronously to
the sample clock, therefore several sample clock cycles may
elapse before the data is present on the output bus.
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ISLA212P50
ADDRESS 0XC0: TEST_IO
ADDRESS 0XCB: USER_PATT6_LSB
Bits 7:4 Output Test Mode
ADDRESS 0XCC: USER_PATT6_MSB
These bits set the test mode according to table below. Other
values are reserved.User test patterns loaded at 0xC1 through
0xD0 are also available by writing ‘1000’ to [7:4] at 0xC0 and a
pattern depth value to [2:0] at 0xC0. See the memory map.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 6.
ADDRESS 0XCD: USER_PATT7_LSB
Bits 2:0 User Test Mode
ADDRESS 0XCE: USER_PATT7_MSB
The three LSBs in this register determine the test pattern in
combination with registers 0xC1 through 0xD0. Refer to the SPI
Memory Map on page 31.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
TABLE 14. OUTPUT TEST MODES
VALUE
0xC0[7:4]
OUTPUT TEST MODE
0000
Off
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XD0: USER_PATT8_MSB
WORD 1
WORD 2
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
0001
Midscale
0x8000
N/A
ADDRESS 0XFE: OFFSET/GAIN_ADJUST_ENABLE
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
Checkerboard (DDR)
0101
Reserved
N/A
N/A
0110
Reserved
N/A
N/A
0111
All on/off (DDR)
1000
User Pattern
user_patt1
user_patt2
1001
Reserved
N/A
N/A
Bit 0 at this register must be set high to enable manual
adjustment of offset coarse and fine adjustments ADC0 (0x20
and 0x21), ADC1 (0x26 and 0x27) and gain medium and gain
fine adjustments ADC0 (0x23 and 0x24), ADC1 (0x29 and 0x2A).
It is recommended that new data be written to the offset and
gain adjustment registers ADC0(0x20, 0x21, 0x23, 0x24) and
ADC1(0x26, 0x27, 0x29, 0x2A) while Bit 0 is a '0'. Subsequently,
Bit 0 should be set to '1' to allow the values written to the
aforementioned registers to be used by the ADC. Bit 0 should be
set to a '0' upon completion.
1010
Ramp
N/A
N/A
ADDRESS 0XC1: USER_PATT1_LSB
ADDRESS 0XC2: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 1.
ADDRESS 0XC3: USER_PATT2_LSB
ADDRESS 0XC4: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 2.
ADDRESS 0XC5: USER_PATT3_LSB
ADDRESS 0XC6: USER_PATT3_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 3.
Digital Temperature Sensor
Address 0x4B: TEMP_COUNTER_HIGH
Bits [2:0] of this register hold the 3 MSBs of the 11-bit
temperature code.
Bit [7] of this register indicates a valid temperature_counter read
was performed. A logic ‘1’ indicates a valid read.
Address 0x4C: TEMP_COUNTER_LOW
Bits [7:0] of this register hold the lower 8 LSBs of the 11-bit
temperature code.
Address 0x4D: TEMP_COUNTER_CONTROL
Bit [7] Measurement mode select bit, set to ‘1’ for recommended
PTAT mode. ‘0’ (default) is IPTAT mode and is less accurate and
not recommended.
Bit [6] Temperature counter enable bit. Set to ‘1’ to enable.
ADDRESS 0XC7: USER_PATT4_LSB
Bit [5] Temperature counter power down bit. Set to ‘1’ to power
down temperature counter.
ADDRESS 0XC8: USER_PATT4_MSB
Bit [4] Temperature counter reset bit. Set to ‘1’ to reset count.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 4.
ADDRESS 0XC9: USER_PATT5_LSB
ADDRESS 0XCA: USER_PATT5_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 5.
FN7843 Rev.3.0
Jul 6, 2021
Bit [3:1] Three bit frequency divider field. Sets temperature
counter update rate. Update rate is proportional to ADC sample
clock rate and divide ratio. A ‘101’ updates the temp counter
every ~ 66µs (for 250Msps). Faster updates rates result in lower
precision.
Bit [0] Select sampler bit. Set to ‘0’.
Page 30 of 38
ISLA212P50
This set of registers provides digital access to an PTAT or
IPTAT-based temperature sensor, allowing the system to
estimate the temperature of the die, allowing easy access to
information that can be used to decide when to recalibrate the
A/D as needed.
The nominal transfer function of the temperature monitor should
be estimated for each device by reading the temperature sensor
at two temperatures and extrapolating a line through these two
points.
A typical temperature measurement can occur as follows:
2. Wait ≥ 132µs (at 250Msps) - longer wait time ensures the
sensor completes one valid cycle.
3. Write ‘0x20’ to address 0x4D - power-down, disable temp
counter - recommended between measurements. This
ensures that the output does not change between MSB and
LSB reads.
4. Read address 0x4B (MSBs)
5. Read address 0x4C (LSBs)
6. Record temp code value
7. Write ‘0x20’ to address 0x4D - power-down, disable temp
counter
1. Write ‘0xCA’ to address 0x4D - enable temp counter,
divide = ‘101’
Device Config/Control
DUT Info SPI Config/Control
SPI Memory Map
Addr.
(Hex)
Parameter Name
00
port_config
Bit 7
(MSB)
SDO
Active
Bit 6
Bit 5
LSB First
Soft
Reset
Bit 4
Bit 3
01
Reserved
Reserved
02
burst_end
Burst end address [7:0]
03-07
Reserved
Reserved
Bit 2
Bit 1
Bit 0 (LSB)
Def. Value
(Hex)
Mirror
(bit5)
Mirror
(bit6)
Mirror (bit7)
00h
00h
08
chip_id
Chip ID #
Read only
09
chip_version
Chip Version #
Read only
0A-0F
Reserved
Reserved
10-1F
Reserved
Reserved
20
offset_coarse_adc0
Coarse Offset
cal. value
21
offset_fine_adc0
Fine Offset
cal. value
22
gain_coarse_adc0
23
gain_medium_adc0
24
gain_fine_adc0
25
modes_adc0
26
offset_coarse_adc1
Coarse Offset
cal. value
27
offset_fine_adc1
Fine Offset
cal. value
28
gain_coarse_adc1
29
gain_medium_adc1
2A
gain_fine_adc1
2B
modes_adc1
2C-2F
Reserved
FN7843 Rev.3.0
Jul 6, 2021
Reserved
Coarse Gain
cal. value
Medium Gain
cal. value
Fine Gain
Reserved
cal. value
Power Down Mode ADC0 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
Reserved
Coarse Gain
cal. value
Medium Gain
cal. value
Fine Gain
Reserved
00h
NOT reset by
Soft Reset
cal. value
Power Down Mode ADC1 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
00h
NOT reset by
Soft Reset
Reserved
Page 31 of 38
ISLA212P50
I2E Control and Status
I2E Control and Status
SPI Memory Map (Continued)
Addr.
(Hex)
Parameter Name
30
I2E_status
31
I2E_control
32
I2E_static_control
33-49
Reserved
4A
I2E_power_down
4B
temp_counter_high
4C
temp_counter_low
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0 (LSB)
I2E
Settled
Low AC
RMS
Power
Low
RMS
Power
Read only
Disable
Skew
Freeze
Run
20h
Should be
set to 1
01h
I2E
Power
Down
03h
Reserved
Enable
Notch
(Fs/4)
Filter
Disable
Offset
Reserved, must be set to 0
Skip
coarse
adj.
Reserved
must be
set to 0
Disable
Gain
Def. Value
(Hex)
Bit 2
Reserved
Notch
(Fs/4)
Filter
Power
Down
Temp Counter [10:8]
Temp Counter [7:0]
Enable
PD
Reset
Read only
Read only
4D
temp_counter_control
4E-4F
Reserved
Reserved
Divider [2:0]
Select
00h
50
I2E_rms_power_threshold_
lsb
RMS Power Threshold, LSBs [7:0]
00h
51
I2E_rms_power_threshold_
msb
RMS Power Threshold, MSBs [15:8]
10h
52
I2E_rms_hysteresis
RMS Power Hysteresis
FFh
53
I2E_ac_rms_power_thresh
old_lsb
AC Power Threshold, LSBs, [7:0]
50h
54
I2E_ac_rms_power_thresh
old_msb
AC Power Threshold, MSBs, [15:8]
00h
10h
55
I2E_ac_rms_hysteresis
AC RMS Power Hysteresis
56-5F
Reserved
Reserved
60
coarse_offset_init
Coarse Offset Initialization value
80h
61
fine_offset_init
Fine Offset Initialization value
80h
62
medium_gain_init
Medium Gain Initialization value
80h
63
fine_gain_init
Fine Gain Initialization value
80h
64
sample_time_skew_init
Sample Time Skew Initialization value
80h
65-6F
Reserved
Reserved
FN7843 Rev.3.0
Jul 6, 2021
Page 32 of 38
ISLA212P50
SPI Memory Map (Continued)
DeviceConfig/Control
Addr.
(Hex)
Parameter Name
Bit 7
(MSB)
Bit 6
Bit 5
70
skew_diff
71
phase_slip
72
clock_divide
73
output_mode_A
Output Mode [7:5]
000 =LVDS 3mA (Default)
001 = LVDS 2mA
100 = LVCMOS
Other codes = Reserved
74
output_mode_B
DLL Range
0 = Fast
1 = Slow
(Default =
‘0’)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Differential Skew
Reserved
Def. Value
(Hex)
80h
Next Clock
Edge
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
Other codes = Reserved
00h
00h
NOT reset by
Soft Reset
00h
Output Format [2:0]
000 = Two’s Complement (Default) NOT reset by
Soft Reset
010 = Gray Code
100 = Offset Binary
Other codes = Reserved
Reserved
00h
NOT reset by
Soft Reset
75-BF
Reserved
Reserved
A4
dll_ctrl_upper_adc0
Consult Factory
cal. value
A5
dll_ctrl_lower_adc0
Consult Factory
cal. value
A6
dll_status_upper_adc0
Consult Factory
Read only
A7
dll_status_lower_adc0
Consult Factory
Read only
A8
dll_ctrl_upper_adc1
Consult Factory
cal. value
A9
dll_ctrl_lower_adc1
Consult Factory
cal. value
AA
dll_status_upper_adc1
Consult Factory
Read only
AB
dll_status_lower_adc1
Consult Factory
Read only
AC-B5
Reserved
B6
Cal_Status
B7-BF
Reserved
FN7843 Rev.3.0
Jul 6, 2021
Reserved
Reserved
Calibration
Done
Read only
Reserved
Page 33 of 38
ISLA212P50
SPI Memory Map (Continued)
Addr.
(Hex)
Parameter Name
C0
test_io
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Output Test Mode (DDR) [7:4]
Bit 1
Bit 0 (LSB)
User Test Mode(DDR) [2:0]
0 = Off (Note 14)
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Checker Board output - 0xAAAA, 0x5555
DDR
5 = Reserved
6 = Reserved
7 = 0xFFFF,0x0000 all on pattern, DDR Word
Toggle
8 = User Pattern (1 to 8 deep, DDR, MSB
justified)
9 = Reserved
10 = Ramp
11-15 = Reserved
Device Test
Bit 2
Def. Value
(Hex)
00h
0 = cycle pattern 1 through 2
1 = cycle pattern 1 through 4
2 = cycle pattern 1 through 6
3 = cycle pattern 1 through 8
4-7 =NA
C1
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C2
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C3
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C4
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C5
user_patt3_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C6
user_patt3_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C7
user_patt4_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
C8
user_patt4_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
C9
user_patt5_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CA
user_patt5_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CB
user_patt6_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CC
user_patt6_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CD
user_patt7_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
CE
user_patt7_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
CF
user_patt8_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
D0
user_patt8_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
Enable
“1” =-Enable
00h
D1-FD
Reserved
FE
Offset/Gain_Adjust_Enable
FF
Reserved
Reserved
Reserved
Reserved
NOTE:
14. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of
calibration. This behavior can be used as an option to monitoring Over range to determine calibration state.
FN7843 Rev.3.0
Jul 6, 2021
Page 34 of 38
ISLA212P50
Equivalent Circuits
AVDD
TO
CLOCKPHASE
GENERATION
AVDD
CLKP
AVDD
CSAMP
9pF
INP
E2
E1
E2
AVDD
FIGURE 44. CLOCK INPUTS
AVDD
(20k PULL-UP
ON RESETN
ONLY)
AVDD
75kO
OVDD
OVDD
TO
SENSE
LOGIC
75kO
280O
INPUT
18kO
CLKN
E3
FIGURE 43. ANALOG INPUTS
AVDD
18kO
AVDD 11kO
TO
CHARGE
PIPELINE
INN
E1
11kO
E3
CSAMP
9pF
AVDD
AVDD
TO
CHARGE
PIPELINE
OVDD
20k
INPUT
75kO
75kO
TO
LOGIC
280
FIGURE 46. DIGITAL INPUTS
FIGURE 45. TRI-LEVEL DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
OVDD
D[11:0]P
OVDD
OVDD
D[11:0]N
DATA
D[11:0]
DATA
DATA
2mA OR
3mA
FIGURE 47. LVDS OUTPUTS
FN7843 Rev.3.0
Jul 6, 2021
FIGURE 48. CMOS OUTPUTS
Page 35 of 38
ISLA212P50
Equivalent Circuits (Continued)
AVDD
VCM
0.94V
+
–
FIGURE 49. VCM_OUT OUTPUT
A/D Evaluation Platform
LVCMOS Outputs
Renesas offers an A/D Evaluation platform which can be used to
evaluate any of Renesas’ high speed A/D products. The platform
consists of a FPGA based data capture motherboard and a family
of A/D daughtercards. This USB based platform allows a user to
quickly evaluate the A/D’s performance at a user’s specific
application frequency requirements. More information is
available on our website.
Output traces and connections must be designed for 50
characteristic impedance.
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces will
increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
LVDS Outputs
Output traces and connections must be designed for 50 (100
differential) characteristic impedance. Keep traces direct and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
FN7843 Rev.3.0
Jul 6, 2021
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will
not be operated do not require connection to ensure optimal A/D
performance. These inputs can be left floating if they are not
used. Tri-level inputs (NAPSLP) accept a floating input as a valid
state, and therefore should be biased according to the desired
functionality.
Definitions
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less 2 LSB. It is typically expressed in percent.
I2E The Interleave Engine. This highly configurable circuitry
performs estimates of offset, gain, and sample time skew
mismatches between the core converters, and updates analog
adjustments for each to minimize interleave spurs.
Integral Non-Linearity (INL) is the maximum deviation of the
A/D’s transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
Page 36 of 38
ISLA212P50
Least Significant Bit (LSB) is the bit that has the smallest value or
weight in a digital word. Its value in terms of input voltage is
VFS/(2N-1) where N is the resolution in bits.
Missing Codes are output codes that are skipped and will never
appear at the A/D output. These codes cannot be reached with
any input value.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the A/D FFT, caused by an AC signal
superimposed on the power supply voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to full
scale) when the converter’s full-scale input power is used as the
reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
Jul 6, 2021
3.0
Updated links throughout.
Removed Related literature section.
Updated Ordering Information table format and updated applicable notes.
Changed POD from L72.10x10E to L72.10x10G.
Removed About Intersil section.
Jan 16, 2013
2.0
Improved the quality, accuracy and clarity of the datasheet.
May 25, 2011
1.0
Initial Release to Web
FN7843 Rev.3.0
Jul 6, 2021
CHANGE
Page 37 of 38
ISLA212P50
Package Outline Drawing
For the most recent package outline drawing, see L72.10x10G.
L72.10x10G
72 Lead Quad Flat No-Lead Plastic Package (QFN)
Rev 0, 4/20
FN7843 Rev.3.0
Jul 6, 2021
Page 38 of 38
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