DATASHEET
ISLA214P13, ISLA214P20, ISLA214P25
FN7572
Rev.4.0
Jul 6, 2021
14-Bit, 250MSPS/200MSPS/130MSPS ADC
The ISLA214P is a series of low power, high performance
14-bit analog-to-digital converters. Designed with the Renesas
proprietary FemtoCharge™ technology on a standard CMOS
process, the series supports sampling rates of up to 250MSPS.
The ISLA214P is part of a pin-compatible family of 12 to 16-bit
A/Ds with maximum sample rates ranging from 130MSPS to
500MSPS.
Features
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters,
such as gain and offset. Digital output data is presented in
selectable LVDS or CMOS formats, and can be configured as
full-width, single data rate (SDR) or half-width, double data
rate (DDR). The ISLA214P is available in a 72-contact QFN
package with an exposed paddle. Operating from a 1.8V
supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
• Programmable built-in test patterns
Key Specifications
• Single supply 1.8V operation
• Clock duty cycle stabilizer
• 75fs clock jitter
• 700MHz bandwidth
• Multi-ADC support
- SPI programmable fine gain and offset control
- Support for multiple ADC synchronization
- Optimized output timing
• Nap and sleep modes
- 200µs sleep wake-up time
• Data output clock
• SDR/DDR LVDS-compatible or LVCMOS outputs
• SNR @ 250/200/130MSPS
73.0/73.8/74.9dBFS fIN = 30MHz
70.6/71.1/70.9dBFS fIN = 363MHz
• SFDR @ 250/200/130MSPS
82/88/88dBc fIN = 30MHz
78/82/84dBc fIN = 363MHz
• Total Power Consumption = 480mW @ 250MSPS
• Selectable clock divider
Applications
• Radar array processing
• Software defined radios
• Broadband communications
• High-performance data acquisition
CLKP
TABLE 1. PIN-COMPATIBLE FAMILY
14-BIT
250 MSPS
ADC
RESETN
AVSS
NAPSLP
FN7572 Rev.4.0
Jul 6, 2021
ISLA216P25
16
250
ISLA216P20
16
200
ISLA216P13
16
130
ISLA214P50
14
500
ISLA214P25
14
250
ISLA214P20
14
200
ISLA214P13
14
130
DIGITAL
ERROR
CORRECTION
D[13:0]P
ISLA212P50
12
500
D[13:0]N
ISLA212P25
12
250
SPI
CONTROL
ISLA212P20
12
200
ISLA212P13
12
130
OVSS
+
–
VCM
CSB
SCLK
SDIO
SDO
SHA
VINN
SPEED
(MSPS)
CLKOUTN
RLVDS
VINP
RESOLUTION
CLKOUTP
CLOCK
MANAGEMENT
CLKN
MODEL
OVDD
CLKDIVRSTN
CLKDIVRSTP
AVDD
CLKDIV
• Communications test equipment
Page 1 of 36
© 2011 Renesas Electronics
ISLA214P13, ISLA214P20, ISLA214P25
Table of Contents
Pin Configuration - LVDS MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions - 72 Ld QFN, LVDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration - CMOS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Descriptions - 72 Ld QFN, CMOS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
22
22
22
22
23
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
27
27
28
29
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A/D Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
33
33
33
33
34
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
FN7572 Rev.4.0
Jul 6, 2021
Page 2 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FN7572 Rev.4.0
Jul 6, 2021
Page 3 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Pin Configuration - LVDS MODE
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
OVDD
OVSS
D0P
D0N
D1P
D1N
D2P
D2N
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54 D3P
DNC
2
53 D3N
NAPSLP
3
52 D4P
VCM
4
51 D4N
AVSS
5
50 D5P
AVDD
6
49 D5N
AVSS
7
48 CLKOUTP
VINN
8
47 CLKOUTN
VINN
9
46 RLVDS
VINP 10
45 OVSS
VINP 11
44 D6P
AVSS 12
43 D6N
AVDD 13
42 D7P
AVSS 14
41 D7N
CLKDIV 15
40 D8P
IPTAT 16
39 D8N
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
DNC 17
Connect Thermal Pad to AVSS
38 D9P
RESETN 18
FN7572 Rev.4.0
Jul 6, 2021
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD
AVDD
AVDD
CLKP
CLKN
CLKDIVRSTP
CLKDIVRSTN
OVSS
OVDD
D13N
D13P
D12N
D12P
OVDD
D11N
D11P
D10N
D10P
37 D9N
Page 4 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
1, 2, 17
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71,
72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
DDR MODE COMMENTS
Tri-Level Power Control (Nap, Sleep modes)
Common Mode Output
8, 9
VINN
Analog Input Negative
10, 11
VINP
Analog Input Positive
15
CLKDIV
16
IPTAT
18
RESETN
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN
28
D13N
LVDS Bit 13(MSB) Output Complement
NC in DDR Mode
29
D13P
LVDS Bit 13 (MSB) Output True
NC in DDR Mode
30
D12N
LVDS Bit 12 Output Complement
DDR Logical Bits 12, 13
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute
temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
31
D12P
LVDS Bit 12 Output True
DDR Logical Bits 12, 13
33
D11N
LVDS Bit 11 Output Complement
NC in DDR Mode
34
D11P
LVDS Bit 11 Output True
NC in DDR Mode
35
D10N
LVDS Bit 10 Output Complement
DDR Logical Bits 10, 11
36
D10P
LVDS Bit 10 Output True
DDR Logical Bits 10, 11
37
D9N
LVDS Bit 9 Output Complement
NC in DDR Mode
38
D9P
LVDS Bit 9 Output True
NC in DDR Mode
39
D8N
LVDS Bit 8 Output Complement
DDR Logical Bits 8, 9
40
D8P
LVDS Bit 8 Output True
DDR Logical Bits 8, 9
41
D7N
LVDS Bit 7 Output Complement
NC in DDR Mode
42
D7P
LVDS Bit 7 Output True
NC in DDR Mode
43
D6N
LVDS Bit 6 Output Complement
DDR Logical Bits 6, 7
44
D6P
LVDS Bit 6 Output True
DDR Logical Bits 6, 7
46
RLVDS
47, 48
CLKOUTN, CLKOUTP
49
D5N
LVDS Bit 5 Output Complement
NC in DDR Mode
50
D5P
LVDS Bit 5 Output True
NC in DDR Mode
51
D4N
LVDS Bit 4 Output Complement
DDR Logical Bits 4, 5
52
D4P
LVDS Bit 4 Output True
DDR Logical Bits 4, 5
53
D3N
LVDS Bit 3 Output Complement
NC in DDR Mode
54
D3P
LVDS Bit 3 Output True
NC in DDR Mode
55
D2N
LVDS Bit 2 Output Complement
DDR Logical Bits 2, 3
56
D2P
LVDS Bit 2 Output True
DDR Logical Bits 2, 3
57
D1N
LVDS Bit 1 Output Complement
NC in DDR Mode
FN7572 Rev.4.0
Jul 6, 2021
LVDS Bias Resistor (Connect to OVSS with 1% 10k)
LVDS Clock Output Complement, True
Page 5 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Pin Descriptions - 72 Ld QFN, LVDS Mode
(Continued)
PIN NUMBER
LVDS PIN NAME
58
D1P
LVDS Bit 1 True
LVDS PIN FUNCTION
NC in DDR Mode
DDR MODE COMMENTS
59
D0N
LVDS Bit 0 (LSB) Output Complement
DDR Logical Bits 0, 1
60
D0P
LVDS Bit 0 (LSB) Output True
DDR Logical Bits 0, 1
63, 64
ORN, ORP
LVDS Over Range Complement, True
DDR Over Range
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
Pin Configuration - CMOS MODE
AVDD
AVDD
AVDD
SDIO
SCLK
CSB
SDO
OVSS
OR
DNC
OVDD
OVSS
D0
DNC
D1
DNC
D2
DNC
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNC
1
54 D3
DNC
2
53 DNC
NAPSLP
3
52 D4
VCM
4
51 DNC
AVSS
5
50 D5
AVDD
6
49 DNC
AVSS
7
48 CLKOUT
VINN
8
47 DNC
VINN
9
46 RLVDS
VINP 10
45 OVSS
VINP 11
44 D6
AVSS 12
43 DNC
AVDD 13
42 D7
AVSS 14
41 DNC
CLKDIV 15
40 D8
IPTAT 16
39 DNC
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
DNC 17
Connect Thermal Pad to AVSS
38 D9
RESETN 18
FN7572 Rev.4.0
Jul 6, 2021
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD
AVDD
AVDD
CLKP
CLKN
CLKDIVRSTP
CLKDIVRSTN
OVSS
OVDD
DNC
D13
DNC
D12
OVDD
DNC
D11
DNC
D10
37 DNC
Page 6 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
1, 2, 17, 28, 30, 33, 35,
37, 39, 41, 43, 47, 49,
51, 53, 55, 57, 59, 63
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71,
72
AVDD
1.8V Analog Supply
5, 7, 12, 14
AVSS
Analog Ground
27, 32, 62
OVDD
1.8V Output Supply
26, 45, 61, 65
OVSS
Output Ground
3
NAPSLP
4
VCM
Common Mode Output
8, 9
VINN
Analog Input Negative
10, 11
VINP
Analog Input Positive
15
CLKDIV
16
IPTAT
18
RESETN
22, 23
CLKP, CLKN
24, 25
CMOS PIN FUNCTION
DDR MODE COMMENTS
Tri-Level Power Control (Nap, Sleep modes)
Tri-Level Clock Divider Control
Temperature Monitor (Output current proportional to absolute
temperature)
Power On Reset (Active Low)
Clock Input True, Complement
CLKDIVRSTP, CLKDIVRSTN Synchronous Clock Divider Reset True, Complement
29
D13
CMOS Bit 13 (MSB) Output
NC in DDR Mode
31
D12
CMOS Bit 12 Output
DDR Logical Bits 12, 13
34
D11
CMOS Bit 11 Output
NC in DDR Mode
36
D10
CMOS Bit 10 Output
DDR Logical Bits 10, 11
38
D9
CMOS Bit 9 Output
NC in DDR Mode
40
D8
CMOS Bit 8 Output
DDR Logical Bits 8, 9
42
D7
CMOS Bit 7 Output
NC in DDR Mode
44
D6
CMOS Bit 6 Output
DDR Logical Bits 6, 7
46
RLVDS
LVDS Bias Resistor (connect to OVSS with 1% 10k)
48
CLKOUT
CMOS Clock Output
50
D5
CMOS Bit 5 Output
NC in DDR Mode
52
D4
CMOS Bit 4 Output
DDR Logical Bits 4, 5
54
D3
CMOS Bit 3 Output
NC in DDR Mode
56
D2
CMOS Bit 2 Output
DDR Logical Bits 2, 3
58
D1
CMOS Bit 1 Output
NC in DDR Mode
60
D0
CMOS Bit 0 (LSB) Output
DDR Logical Bits 0, 1
64
OR
CMOS Over Range
DDR Over Range
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
FN7572 Rev.4.0
Jul 6, 2021
Page 7 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Ordering Information
PART NUMBER
(Notes 1,2)
PART
MARKING
ISLA214P13IRZ
ISLA214P13 IRZ
ISLA214P20IRZ
ISLA214P20 IRZ
ISLA214P25IRZ
ISLA214P25 IRZ
ISLA214IR72EV1Z
Evaluation Board
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
CARRIER TYPE
TEMP. RANGE
72 Ld QFN
L72.10x10G
Tray
-40°C to +85°C
NOTES:
1. These Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu-Ag plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), see the ISLA214P13, ISLA214P20, ISLA214P25 device pages. . For more information about MSL, see TB363.
FN7572 Rev.4.0
Jul 6, 2021
Page 8 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
23
0.9
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379.
4. For JC, the case temperature location is the center of the exposed metal pad on the package underside.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (Typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
Boldface limits apply over the operating temperature range, -40°C to +85°C.
ISLA214P25
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
1.95
2.0
ISLA214P20
MAX
MIN
(Note 5) (Note 5)
TYP
ISLA214P13
MAX
MIN
(Note 5) (Note 5)
TYP
MAX
(Note 5)
UNIT
2.0
2.1
VP-P
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input
Range
VFS
Differential
2.1
1.95
2.0
2.1
1.95
Input Resistance
RIN
Differential
600
600
600
Ω
Input Capacitance
CIN
Differential
4.5
4.5
4.5
pF
Full Temp
108
82
74
ppm/°C
Full Scale Range Temp.
Drift
AVTC
Input Offset Voltage
VOS
Common-Mode Output
Voltage
VCM
0.94
0.94
0.94
V
Common-Mode Input
Current (per pin)
ICM
2.6
2.6
2.6
µA/MSPS
Inputs Common Mode
Voltage
0.9
0.9
0.9
V
CLKP,CLKN Input Swing
(Note 7)
1.8
1.8
1.8
V
-5.0
-1.7
5.0
-5.0
-1.7
5.0
-5.0
-1.7
5.0
mV
Clock Inputs
Power Requirements
1.8V Analog Supply
Voltage
AVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Digital Supply
Voltage
OVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Analog Supply
Current
IAVDD
188
200
174
184
152
161
mA
1.8V Digital Supply
Current (Note 6)
I
OVDD
3mA LVDS (SDR)
78.5
88
75
84
68.5
77
mA
Power Supply Rejection
Ratio
PSRR
30MHz, 30mVP-P signal
on AVDD
FN7572 Rev.4.0
Jul 6, 2021
40
40
40
dB
Page 9 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (Typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
ISLA214P25
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
ISLA214P20
MAX
MIN
(Note 5) (Note 5)
TYP
ISLA214P13
MAX
MIN
(Note 5) (Note 5)
TYP
MAX
(Note 5)
UNIT
Total Power Dissipation
Normal Mode
PD
Nap Mode
PD
Sleep Mode
PD
Nap/Sleep Mode
Wakeup Time
2mA LVDS
454
3mA LVDS (SDR)
480
3mA LVDS (DDR)
450
410
360
mW
CMOS (SDR)
432
392
313
mW
CMOS (DDR)
420
375
310
mW
CSB at logic high
Sample Clock Running
422
518
448
369
482
397
mW
428
mW
55.8
60
52.2
57
48.6
53
mW
6
11
6
11
6
10
mW
200
400
630
µs
AC SPECIFICATIONS
Differential Nonlinearity
DNL
fIN = 105MHz
No Missing Codes
Integral Nonlinearity
INL
fIN = 105MHz
Minimum Conversion
Rate (Note 8)
fS MIN
Maximum Conversion
Rate
fS MAX
Signal-to-Noise Ratio
(Note 9)
SNR
Signal-to-Noise and
Distortion
(Note 9)
Effective Number of Bits
(Note 9)
FN7572 Rev.4.0
Jul 6, 2021
2.0
-0.99
±2.5
250
fIN = 30MHz
±0.25
±0.25
130
73.7
73.0
LSB
LSB
40
73.8
72.1
1.4
±2.5
40
200
73
-0.99
±2.5
73
70.1
1.4
MSPS
MSPS
74.9
dBFS
74.3
dBFS
fIN = 190MHz
72.1
72.8
73.3
dBFS
fIN = 363MHz
70.6
71.1
70.9
dBFS
fIN = 461MHz
69.9
70.0
69.5
dBFS
fIN = 605MHz
68.4
68.5
67.8
dBFS
fIN = 30MHz
72.4
73.5
74.6
dBFS
73.6
dBFS
fIN = 105MHz
ENOB
±0.3
40
fIN = 105MHz
SINAD
-0.99
69.4
72.4
71.0
73.1
70.8
fIN = 190MHz
70.7
72.3
72.2
dBFS
fIN = 363MHz
69.8
70.7
70.6
dBFS
fIN = 461MHz
66.1
67.4
65.9
dBFS
fIN = 605MHz
60.5
61.1
61.1
dBFS
fIN = 30MHz
11.73
11.92
12.10
Bits
fIN = 105MHz
11.29 11.73
11.50 11.83
11.47 11.93
Bits
fIN = 190MHz
11.45
11.72
11.70
Bits
fIN = 363MHz
11.30
11.45
11.44
Bits
fIN = 461MHz
10.69
10.90
10.65
Bits
fIN = 605MHz
9.76
9.86
9.86
Bits
Page 10 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -40°C to +85°C (Typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
ISLA214P25
PARAMETER
SYMBOL
Spurious-Free Dynamic
Range
(Note 9)
SFDR
CONDITIONS
MIN
(Note 5)
fIN = 30MHz
fIN = 105MHz
TYP
ISLA214P20
MAX
MIN
(Note 5) (Note 5)
82
72
83
TYP
ISLA214P13
MAX
MIN
(Note 5) (Note 5)
88
72
84
70
TYP
MAX
(Note 5)
UNIT
88
dBc
83
dBc
fIN = 190MHz
78
84
78
dBc
fIN = 363MHz
78
82
84
dBc
fIN = 461MHz
68
71
68
dBc
fIN = 605MHz
61
62
61
dBc
Spurious-Free Dynamic SFDRX23 fIN = 30MHz
Range Excluding H2, H3
fIN = 105MHz
89
93
99
dBc
91
90
95
dBc
fIN = 190MHz
88
89
91
dBc
fIN = 363MHz
87
90
95
dBc
fIN = 461MHz
88
93
94
dBc
fIN = 605MHz
88
88
87
dBc
fIN = 70MHz
87
86
87
dBFS
fIN = 170MHz
97
104
101
dBFS
10-12
10-12
700
700
Intermodulation
Distortion
IMD
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
700
MHz
NOTES:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output
7. See “Clock Input” on page 21.
8. The DLL Range setting must be changed for low-speed operation.
9. Minimum specification guaranteed when calibrated at +85°C.
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
TYP
MAX
(Note 5) UNITS
0
1
10
µA
-25
-12
-8
µA
4
12
µA
-600
-415
-300
µA
40
58
75
5
10
INPUTS (Note 10)
Input Current High (RESETN)
IIH
VIN = 1.8V
Input Current Low (RESETN)
IIL
VIN = 0V
Input Current High (SDIO)
IIH
VIN = 1.8V
Input Current Low (SDIO)
IIL
VIN = 0V
Input Current High (CSB)
IIH
VIN = 1.8V
Input Current Low (CSB)
IIL
VIN = 0V
Input Current High (CLKDIV)
IIH
16
25
34
µA
Input Current Low (CLKDIV)
IIL
-34
-25
-16
µA
Input Voltage High (SDIO, RESETN)
VIH
1.17
Input Voltage Low (SDIO, RESETN)
VIL
Input Capacitance
CDI
FN7572 Rev.4.0
Jul 6, 2021
V
0.63
4
V
pF
Page 11 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Digital Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 5)
MAX
(Note 5) UNITS
TYP
LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN)
Input Common Mode Range
VICM
825
1575
mV
Input Differential Swing (peak to peak, single-ended)
VID
250
450
mV
CLKDIVRSTP Input Pull-down Resistance
RIpd
100
k
CLKDIVRSTN Input Pull-up Resistance
RIpu
100
k
612
mVP-P
LVDS OUTPUTS
Differential Output Voltage (Note 11)
Output Offset Voltage
VT
3mA Mode
VOS
3mA Mode
1120
1150
1200
mV
Output Rise Time
tR
240
ps
Output Fall Time
tF
240
ps
OVDD - 0.1
V
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
OVDD - 0.3
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
NOTES:
10. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD
depending on desired function.
11. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
D[12/10/8/6/4/2/0]N
D[12/10/8/6/4/2/0]P
tPD
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
FIGURE 1A. LVDS DDR
FN7572 Rev.4.0
Jul 6, 2021
Page 12 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Timing Diagrams (Continued)
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[13:0]N
DATA
N-L
D[13:0]P
DATA
N
DATA
N-L+1
FIGURE 1B. LVDS SDR
FIGURE 1. LVDS TIMING DIAGRAMS
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
D[12/10/8/6/4/2/0]
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
FIGURE 2A. CMOS DDR
FN7572 Rev.4.0
Jul 6, 2021
Page 13 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Timing Diagrams (Continued)
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
DATA
N-L
D[13:0]
DATA
N
DATA
N-L+1
FIGURE 2B. CMOS SDR
FIGURE 2. CMOS TIMING DIAGRAMS
Switching Specifications
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITION
MIN
(Note 5)
TYP
MAX
(Note 5)
UNIT
ADC OUTPUT
Aperture Delay
tA
114
ps
RMS Aperture Jitter
jA
75
fs
Input Clock to Output Clock Propagation
Delay
Relative Input Clock to Output Clock
Propagation Delay (Note 12)
tCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
1.65
2.4
3
ns
tCPD
AVDD, OVDD = 1.8V, TA = +25°C
1.9
2.3
2.75
ns
dtCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
-450
450
ps
Input Clock to Data Propagation Delay
tPD
Output Clock to Data Propagation Delay,
LVDS Mode
tDC
Output Clock to Data Propagation Delay,
CMOS Mode
tDC
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
tRSTS
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
tRSTH
Synchronous Clock Divider Reset Recovery
Time
tRSTRT
Latency (Pipeline Delay)
Overvoltage Recovery
FN7572 Rev.4.0
Jul 6, 2021
1.65
2.4
3.5
ns
Rising/Falling Edge
-0.1
0.16
0.5
ns
Rising/Falling Edge
-0.1
0.2
0.65
ns
0.4
0.06
0.02
DLL recovery time after
Synchronous Reset
ns
0.35
ns
52
µs
L
10
cycles
tOVR
1
cycles
Page 14 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Switching Specifications
PARAMETER
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
MIN
(Note 5)
CONDITION
TYP
MAX
(Note 5)
UNIT
SPI INTERFACE (Notes 13, 14)
t
SCLK Period
CLK
Write Operation
16
cycles
tCLK
Read Operation
16
cycles
CSB to SCLKSetup Time
tS
Read or Write
28
cycles
CSB after SCLK Hold Time
tH
Write
5
cycles
CSB after SCLK↓ Hold Time
tHR
Read
16
cycles
Data Valid to SCLK Setup Time
tDS
Write
6
cycles
Data Valid after SCLK Hold Time
tDH
Read or Write
4
cycles
Data Valid after SCLK↓ Time
tDVR
Read
5
cycles
NOTES:
12. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
13. SPI Interface timing is directly proportional to the ADC sample period (tS). Values above reflect multiples of a 4ns sample period, and must be scaled
proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
14. The SPI may operate asynchronously with respect to the ADC sample clock.
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 250MSPS.
-60
90
SFDR @ 130MSPS
85
SFDR @ 250MSPS
80
75
70
65
60
SNR @ 250MSPS
0
100
200
SNR @ 130MSPS
300
400
INPUT FREQUENCY (MHz)
FIGURE 3. SNR AND SFDR vs fIN
FN7572 Rev.4.0
Jul 6, 2021
500
600
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
95
HD3 @ 250MSPS
-65
HD2 @ 250MSPS
-70
-75
-80
-85
-90
HD3 @ 130MSPS
-95
HD2 @ 130MSPS
-100
-105
0
100
200
300
400
500
INPUT FREQUENCY (MHz)
FIGURE 4. HD2 AND HD3 vs fIN
Page 15 of 36
600
ISLA214P13, ISLA214P20, ISLA214P25
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
-30
100
90
-40
HD2 AND HD3 MAGNITUDE
SFDR (dBfs)
SNR AND SFDR
80
70
SNR (dBfs)
60
SFDR (dBc)
50
SNR (dBc)
40
30
20
10
-60
-50
-40
-30
-20
-10
-60
HD3 (dBc)
-70
HD2 (dBfs)
-80
HD3 (dBfs)
-90
-100
-110
0
HD2 (dBc)
-50
-60
-50
INPUT AMPLITUDE (dBFS)
FIGURE 5. SNR AND SFDR vs AIN
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
-20
-10
0
-75
85
SFDR
80
SNR
75
70
90
110
130
150
170
190
210
230
-80
HD3
-85
-90
HD2
-95
-100
-105
70
250
90
110
FIGURE 7. SNR AND SFDR vs fSAMPLE
150
170
190
210
230
250
FIGURE 8. HD2 AND HD3 vs fSAMPLE
500
1.0
475
0.8
0.6
450
DNL (LSBs)
0.4
425
LVDS
400
375
CMOS
350
0.2
0
-0.2
-0.4
-0.6
325
300
130
SAMPLE RATE (MSPS)
SAMPLE RATE (MSPS)
TOTAL POWER (mW)
-30
FIGURE 6. HD2 AND HD3 vs AIN
90
70
-40
INPUT AMPLITUDE (dBFS)
-0.8
40
60
80
100 120 140 160 180
SAMPLE RATE (MSPS)
200
220
240
FIGURE 9. POWER vs fSAMPLE IN 3mA LVDS MODE (SDR) AND
CMOS MODE (DDR)
FN7572 Rev.4.0
Jul 6, 2021
-1.0
0
2000
4000
6000
8000 10000 12000 14000 16000
CODES
FIGURE 10. DIFFERENTIAL NONLINEARITY
Page 16 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
4
85
SNR (dBFS) AND SFDR (dBc)
3
INL (LSBs)
2
1
0
-1
-2
-3
-4
0
2000
4000
6000
80
75
70
SFDR AIN = -2dBFS
65
60
0.75
8000 10000 12000 14000 16000
CODES
FIGURE 11. INTEGRAL NONLINEARITY
70000
AMPLITUDE (dBFS)
NUMBER OF HITS
50000
35036
30000
23400
20000
10120
10000
4668
0 0 0 23 581
0
8170 8172 8174 8176 8178
CODE
590 43 1 0 0
8180 8182 8184
-40
-60
-80
-120
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 14. SINGLE-TONE SPECTRUM @ 105MHz
0
0
AIN = -1.0 dBFS
SNR = 72.6 dBFS
-20 SFDR = 78.1 dBc
SINAD = 71.2 dBFS
AIN = -1.0 dBFS
SNR = 70.9 dBFS
SFDR = 78.4 dBc
SINAD = 70.1 dBFS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
AIN = -1.0 dBFS
SNR = 73.4 dBFS
SFDR = 80.7 dBc
SINAD = 72.5 dBFS
-100
FIGURE 13. NOISE HISTOGRAM
-40
-60
-80
-100
-120
1.15
0
-20
40000
0.85
0.95
1.05
INPUT COMMON MODE (V)
FIGURE 12. SNR AND SFDR vs VCM
64687
60851
60000
SNR
AIN = -1dBFS
SFDR AIN = -1dBFS
-40
-60
-80
-100
0
20
40
60
80
100
FREQUENCY (MHz)
FIGURE 15. SINGLE-TONE SPECTRUM @ 190MHz
FN7572 Rev.4.0
Jul 6, 2021
120
-120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 16. SINGLE-TONE SPECTRUM @ 363MHz
Page 17 of 36
ISLA214P13, ISLA214P20, ISLA214P25
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C,
AIN = -1dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
0
0
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
-40
-60
IMD3 = -87 dBFS
-80
-40
-60
IMD3 = -97 dBFS
-80
-100
-100
-120
IMD2
IMD3
2ND HARMONICS
3RD HARMONICS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-20
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 17. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz AT
-7dBFS)
Theory of Operation
Functional Description
The ISLA214P is based on a 14-bit, 250MSPS A/D converter core
that utilizes a pipelined successive approximation architecture
(see Figure 19). The input voltage is captured by a Sample-Hold
Amplifier (SHA) and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively compare the
input to a series of reference charges. Decisions made during the
successive approximation operations determine the digital code
for each input value. Digital error correction is also applied,
resulting in a total latency of 10 clock cycles. This is evident to the
user as a latency between the start of a conversion and the data
being available on the digital outputs.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
following conditions must be adhered to for the power-on
calibration to execute successfully.
-120
0
Filename
Core fs (MHz)
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 18. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz AT
-7dBFS)
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 20. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
If the selectable clock divider is set to 1 (default), the output
clock (CLKOUTP/CLKOUTN) will not be affected by the assertion
of RESETN. If the selectable clock divider is set to 2 or 4, the
output clock is set low while RESETN is asserted (low). Normal
operation of the output clock resumes at the next input clock
edge (CLKP/CLKN) after RESETN is de-asserted. At 250MSPS,
the nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins must not be connected
• SDO has an internal pull-up and should not be driven externally
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
FN7572 Rev.4.0
Jul 6, 2021
Page 18 of 36
ISLA214P13, ISLA214P20, ISLA214P25
CLOCK
GENERATION
INP
SHA
INN
1.25V
2.5-BIT
2.5-BIT
FLASH
FLASH
+
–
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1- BIT/ STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/ LVCMOS
OUTPUTS
FIGURE 19. A/D CORE BLOCK DIAGRAM
CLKN
CLKP
CALIBRATION
TIME
RESETN
CALIBRATION
BEGINS
CAL_STATUS
BIT
CALIBRATION
COMPLETE
Figures 21 through 26 show the effect of temperature on SNR
and SFDR performance with power on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated earlier. However, it can be seen
that performance drift with temperature is not a very strong
function of the temperature at which the power on calibration is
performed.
CLKOUTP
FIGURE 20. CALIBRATION TIMING
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength in its high impedance
state of less than 0.5mA is recommended, as RESETN has an
internal high impedance pull-up to OVDD. As is the case during
power-on reset, RESETN and DNC pins must be in the proper
state for the calibration to successfully execute.
The performance of the ISLA214P changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the A/D under the environmental conditions at
which it will operate.
A supply voltage variation of
工商网监
湘ICP备2023018690号
