ISLA216S13IR1Z

DATASHEET ISLA216S FN7996 Rev 1.00 April 19, 2013 16-Bit, 250/200/130 MSPS JESD204B High Speed Serial Output ADC The ISLA216S is a series of low-power, high-performance, 16-bit, analog-to-digital converters. Designed with FemtoCharge™ technology on a standard CMOS process, the series supports sampling rates of up to 250MSPS. The ISLA216S is part of a pin-compatible family of 12-, 14-, and 16-bit A/Ds with maximum sample rates ranging from 130 to 500MSPS and shares the same analog core as Intersil's proven ISLA216P series of ADCs. The family minimizes power consumption while providing state-of-the art dynamic performance, offering an optimal performance-vs-power trade-off. Differentiating the ISLA216S from the ISLA216P is its highly configurable, JESD204B-compliant, high speed serial output link. The link offers data rates up to 4.375Gbps per lane and multiple packing modes. It uses two lanes to transmit the conversion data. The SERDES transmitter also provides deterministic latency and multi-chip time alignment support to satisfy an application's complex synchronization requirements. A serial peripheral interface (SPI) port allows for extensive configurability of the JESD204B transmitter including access to its built-in link and transport-layer test patterns. The SPI port also provides control for numerous additional features including the fine gain and offset adjustments of the two ADC cores as well as the programmable clock divider, enabling 2x and 4x harmonic clocking. The ISLA216S is available in a space-saving 7mmx7mm 48 Ld QFN package. The package features a thermal pad for improved thermal performance and is specified over the full industrial temperature range (-40°C to +85°C). Features • JESD204A/B High Speed Data Interface - JESD204A Compliant - JESD204B Device Subclass 0 Compliant - JESD204B Device Subclass 2 Compatible - JESD204 Output Lanes Run up to 4.375Gbps - Highly Configurable JESD204 Transmitter • Multiple Chip Time Alignment and Deterministic Latency Support (JESD204B Device Subclass 2) • SPI Programmable Debugging Features and Test Patterns • 48-pin QFN 7mmx7mm Package Key Specifications • SNR @ 250/200/130MSPS 75.8/77.2/78.0 dBFS fIN = 30MHz 74.6/75.2/74.8 dBFS fIN = 190MHz • SFDR @ 250/200/130MSPS 87/93/94 dBc fIN = 30MHz 82/81/81 dBc fIN = 190MHz • Total Power Consumption: 887mW @ 250MSPS Applications • • • • • Radar and Satellite Antenna Array Processing Broadband Communications and Microwave Receivers High-Performance Data Acquisition Communications Test Equipment High-Speed Medical Imaging Pin-Compatible Family RESOLUTION SPEED (MSPS) PRODUCT AVAILABILITY ISLA216S25 16 250 Now ISLA216S20 16 200 Now ISLA216S13 16 130 Now MODEL ISLA214S50 14 500 Now ISLA212S50 12 500 Soon ISLA214S25 14 250 Soon ISLA212S25 12 250 Soon FIGURE 1. SERDES DATA EYE AT 4.375Gbps FN7996 Rev 1.00 April 19, 2013 Page 1 of 34 OVDD (PLL) OVDD SYNC AVDD ISLA216S CLKP CLOCK GENERATION CLKN LANE[1:0]P VINP 16-BIT 250MSPS ADC SHA VINN 1.25V VCM + – LANE[1:0]N JESD204 TRANSMITTER VREF OVSS CSB SCLK SDIO SDO RESETN NAPSLP AVSS AVSS (PLL) SPI CONTROL FIGURE 2. BLOCK DIAGRAM Pin Configuration FN7996 Rev 1.00 April 19, 2013 DNC DNC AVDD NAPSLP CLKDIV SDIO SCLK CSB SDO OVDD OVSS OVSS ISLA216S (48 LD QFN) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 VCM 1 36 OVDD AVDD 2 35 OVSS AVSS 3 34 DNC AVSS 4 33 DNC VINN 5 32 OVSS VINN 6 31 LANE1N VINP 7 30 LANE1P VINP 8 29 OVSS AVSS 9 28 LANE0N AVSS 10 27 LANE0P AVDD 11 DNC 12 26 OVSS PAD – Exposed Paddle 13 14 15 16 17 18 19 20 21 22 23 24 RESETN AVDD AVDD CLKP CLKN SYNCP SYNCN DNC OVSS (PLL) OVDD (PLL) OVSS (PLL) OVDD (PLL) 25 OVDD Page 2 of 34 ISLA216S Pin Descriptions PIN NUMBER NAME FUNCTION 2, 11, 14, 15, 46 AVDD 1.8V Analog Supply 12, 20, 33, 34, 47, 48 DNC Do Not Connect 3, 4, 9, 10 AVSS Analog Ground 7, 8 VINP Analog Input, Positive 5, 6 VINN Analog Input, Negative 1 VCM Common Mode Output 44 CLKDIV 16, 17 CLKP, CLKN 45 NAPSLP Power Control (Nap, Sleep modes) 13 RESETN Power On Reset (Active Low) 26, 29, 32, 35, 37, 38 OVSS Output Ground 25, 36, 39 OVDD 1.8V Digital Supply 22, 24 OVDD (PLL) 1.8V Analog Supply for SERDES PLL 21, 23 OVSS (PLL) Analog Ground Supply for SERDES PLL 18, 19 SYNCP, SYNCN 27, 28 LANE0P, LANE0N SERDES Lane 0 30, 31 LANE1P, LANE1N SERDES Lane 1 40 SDO SPI Serial Data Output 41 CSB SPI Chip Select (active low) 42 SCLK SPI Clock 43 SDIO SPI Serial Data Input/Output PAD AVSS Exposed Paddle. Analog Ground (connect to AVSS) Clock Divider Control Clock Input True, Complement JESD204 SYNC Input Ordering Information PART NUMBER (Notes 1, 2) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISLA216S25IR1Z ISLA216S25 IR1Z -40 to +85 48 Ld QFN L48.7x7G ISLA216S20IR1Z ISLA216S20 IR1Z -40 to +85 48 Ld QFN L48.7x7G ISLA216S13IR1Z ISLA216S13 IR1Z -40 to +85 48 Ld QFN L48.7x7G Coming Soon ISLA216S25IR48EV1Z Evaluation Board NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA216S13, ISLA216S20, ISLA216S25. For more information on MSL please see techbrief TB363. FN7996 Rev 1.00 April 19, 2013 Page 3 of 34 ISLA216S Table of Contents Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 15 Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 16 17 17 17 17 17 18 Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 JESD204 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Initial Lane Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADDRESS 0xDF - 0xF3: JESD204 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address 0xDF-0xEE: JESD204 Parameter Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 23 23 23 24 25 25 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CML Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 32 32 32 32 32 32 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FN7996 Rev 1.00 April 19, 2013 Page 4 of 34 ISLA216S Absolute Maximum Ratings Thermal Information AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 48 Ld QFN (Notes 3, 4, 5) . . . . . . . . . . . . . . 24 0.4 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 5. For solder stencil layout and reflow guidelines, please see Tech Brief TB389. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40°C to +85°C. ISLA216S25 PARAMETER SYMBOL CONDITIONS MIN (Note 6) TYP 1.95 2.14 ISLA216S20 ISLA216S13 MAX MIN MAX MIN MAX (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) UNITS DC SPECIFICATIONS Analog Input Full-Scale Analog Input Range VFS Differential 2.22 1.95 2.08 2.22 1.95 2.03 2.22 VP-P Input Resistance RIN Differential 300 300 300  Input Capacitance CIN Differential 10.7 10.7 10.7 pF Full Temp 145 124 68 ppm/°C Full Scale Range Temp. Drift AVTC Input Offset Voltage VOS Gain Error EG 1 1 1 % Common-Mode Output Voltage VCM 0.94 0.94 0.94 V Common Mode Input Current (per pin) ICM 12.0 12.0 12.0 µA/MSPS Inputs Common Mode Voltage 0.9 0.9 0.9 V CLKP, CLKN Swing 1.8 1.8 1.8 V -5.0 ±1 5.0 -5.0 ±1 5.0 -5.0 ±1 5.0 mV Clock Inputs Power Requirements 1.8V Analog Supply Voltage AVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.8 V 1.8V Digital Supply Voltage OVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.8 V 1.8V Analog Supply Current IAVDD 354 378 325 349 283 306 mA 1.8V Digital Supply Current IOVDD 139 152 128 140 109 122 mA FN7996 Rev 1.00 April 19, 2013 Page 5 of 34 ISLA216S Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) ISLA216S25 PARAMETER SYMBOL Power Supply Rejection Ratio (Note 7) PSRR CONDITIONS MIN (Note 6) TYP ISLA216S20 ISLA216S13 MAX MIN MAX MIN MAX (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) UNITS 30MHz 200mVP-P 38 38 38 dB 1MHz 200mVP-P 44 44 44 dB Total Power Dissipation Normal Mode PD 887 954 815 880 706 770 mW Nap Mode PD 323 367 300 342 267 310 mW Sleep Mode PD CSB at logic high 6 14 6 14 6 14 mW Nap Mode Wakeup Time Sample Clock Running 5 5 5 µs Sleep Mode Wakeup Time Sample Clock Running 1 1 1 ms ±0.14 LSB AC SPECIFICATIONS (Note 8) Differential Nonlinearity DNL Integral Nonlinearity INL Minimum Conversion Rate (Note 9) fS MIN Maximum Conversion Rate fS MAX Signal-to-Noise Ratio (Note 10) SNR Signal-to-Noise and Distortion (Note 10) Effective Number of Bits (Note 10) FN7996 Rev 1.00 April 19, 2013 -0.99 ±0.17 250 fIN = 30MHz 200 130 77.2 78.0 dBFS 76.8 dBFS 74.8 dBFS fIN = 363MHz 72.4 72.5 71.2 dBFS fIN = 495MHz 70.8 70.6 69.6 dBFS fIN = 605MHz 69.3 69.2 67.3 dBFS fIN = 30MHz 75.5 77.1 77.7 dBFS 76.3 75.0 MSPS 75.2 73.6 76.6 MSPS 74.6 74.9 74.3 LSB 100 fIN = 190MHz 71.1 75.5 ±9.0 100 75.8 72.3 -0.99 ±12.0 100 fIN = 105MHz ENOB -0.99 ±16.0 fIN = 105MHz SINAD ±0.24 76.3 dBFS fIN = 190MHz 73.9 74.1 74.2 73.8 dBFS fIN = 363MHz 69.8 69.0 66.0 dBFS fIN = 495MHz 66.5 66.3 65.9 dBFS fIN = 605MHz 64.9 64.1 58.4 dBFS fIN = 30MHz 12.20 12.45 12.59 Bits fIN = 105MHz 11.51 12.14 11.93 12.36 12.03 12.36 Bits fIN = 190MHz 11.95 12.03 11.91 Bits fIN = 363MHz 11.27 11.19 10.66 Bits fIN = 495MHz 10.76 10.72 10.61 Bits fIN = 605MHz 10.52 10.43 9.52 Bits Page 6 of 34 ISLA216S Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) ISLA216S25 PARAMETER SYMBOL Spurious-Free Dynamic Range (Note 10) SFDR Spurious-Free Dynamic Range Excluding H2, H3 (Note 10) CONDITIONS MIN (Note 6) fIN = 30MHz fIN = 105MHz 74 IMD ISLA216S13 MAX MIN MAX MIN MAX (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) 87 93 84 76 88 76 UNITS 94 dBc 85 dBc fIN = 190MHz 82 81 81 dBc fIN = 363MHz 72 70 66 dBc fIN = 495MHz 67 67 67 dBc fIN = 605MHz 65 64 57 dBc 88 94 100 dBc fIN = 105MHz 89 95 94 dBc fIN = 190MHz 87 91 89 dBc fIN = 363MHz 81 86 84 dBc fIN = 495MHz 79 87 80 dBc fIN = 605MHz 75 83 77 dBc fIN = 70MHz 96 97 96 dBFS fIN = 170MHz 87 86 87 dBFS 10-13 10-13 620 620 SFDRX23 fIN = 30MHz Intermodulation Distortion TYP ISLA216S20 Word Error Rate WER 10-13 Full Power Bandwidth FPBW 620 MHz NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. PSRR is calculated by the equation 20*log10(A/B), where B is the amplitude of a disturber sinusoid on AVDD at the device pins, and A is the amplitude of the spur in the captured data at the frequency of the disturber sinusoid. 8. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to “Power-On Calibration” on page 14 and “User Initiated Reset” on page 15 for more detail. 9. The DLL Range setting must be changed via SPI for ADC core sample rates below 80MSPS. The JESD204 transmitter can support ADC sample rates below 100MSPS, as long as the lane data rate is greater than or equal to 1Gbps. 10. Minimum specification guaranteed when calibrated at +85°C. Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS CMOS INPUTS Input Current High (RESETN) IIH VIN = 1.8V Input Current Low (RESETN) IIL VIN = 0V Input Current High (SDIO, SCL, SDA SCLK) IIH VIN = 1.8V Input Current Low (SDIO, SCL, SDA SCLK) IIL VIN = 0V Input Current High (CSB) IIH VIN = 1.8V Input Current Low (CSB) IIL VIN = 0V Input Voltage High (SDIO, RESETN) VIH Input Voltage Low (SDIO, RESETN) VIL Input Current High (NAPSLP, CLKDIV) (Note 11) IIH 19 Input Current Low (NAPSLP, CLKDIV) IIL --30 FN7996 Rev 1.00 April 19, 2013 1 10 µA -12 -7 µA 4 12 µA -600 -400 -300 µA 40 52 70 µA 1 10 µA -25 1.17 V 0.63 V 25 30 µA -25 -19 µA Page 7 of 34 ISLA216S Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL Input Capacitance MIN (Note 6) CONDITIONS TYP CDI MAX (Note 6) UNITS 4 pF LVDS INPUTS (SYNCP, SYNCN) Input Common Mode Range VICM 825 1575 mV Input Differential Swing (peak-to-peak, single-ended) VID 250 450 mV Input Pull-up and Pull-down Resistance RIpu 100 kΩ 1.14 V CML OUTPUTS Output Common Mode Voltage Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL CONDITION MIN (Note 6) TYP MAX (Note 6) UNITS ADC OUTPUT Aperture Delay tA 190 ps RMS Aperture Jitter jA 100 fs 250 µs L 10 cycles tOVR 1 cycles PLL Lock Time 295 µs PLL Bandwidth 2.2 MHz Added Random Jitter 5 ps RMS Added Deterministic Jitter 7 ps P-P 5 ps rms 75 ps Synchronous Clock Divider Reset Recovery Time (Note 12) Latency (ADC Pipeline Delay) Overvoltage Recovery tRSTRT DLL recovery time after Synchronous Reset SERDES Maximum Input Sample Clock Total Jitter to Maintain SERDES BER