ISLA222P20IRZ

DATASHEET ISLA222P FN7853 Rev 1.00 June 17, 2011 Dual 12-Bit, 250MSPS/200MSPS/130MSPS ADC The ISLA222P is a family of dual-channel 12-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The ISLA222P is part of a pin-compatible portfolio of 12-bit and 14-bit dual-channel A/Ds with maximum sample rates ranging from 130MSPS to 250MSPS. Features A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of various parameters such as gain and offset. • Programmable Built-in Test Patterns Digital output data is presented in selectable LVDS or CMOS formats. The ISLA222P is available in a 72 lead QFN package with an exposed paddle. Operating from a 1.8V supply, performance is specified over the full industrial temperature range (-40°C to +85°C). • Single Supply 1.8V Operation • Clock Duty Cycle Stabilizer • 75fs Clock Jitter • 700MHz Bandwidth • Multi-ADC Support - SPI Programmable Fine Gain and Offset Control - Support for Multiple ADC Synchronization - Optimized Output Timing • Nap and Sleep Modes - 200µs Sleep Wake-up Time • Data Output Clock Key Specifications • DDR LVDS-Compatible or LVCMOS Outputs • SNR @ 250/200/130MSPS 70.3/71.0/71.3dBFS fIN = 30MHz 68.5/68.8/68.4dBFS fIN = 363MHz • SFDR @ 250/200/130MSPS 85/87/86dBc fIN = 30MHz 73/75/80dBc fIN = 363MHz • Total Power Consumption = 823mW @ 250MSPS • User-accessible Digital Temperature Monitor Applications • Radar Array Processing • Software Defined Radios • Broadband Communications • High-Performance Data Acquisition CLKP Pin-Compatible Family OVDD CLKDIVRSTN CLKDIVRSTP AVDD CLKDIV • Communications Test Equipment CLKOUTP CLOCK MANAGEMENT CLKN 12-BIT 250 MSPS ADC SHA VINBN VREF DIGITAL ERROR CORRECTION VCM 12-BIT 250 MSPS ADC VREF + 1.25V –- RESETN AVSS NAPSLP SHA VINAP SPEED (MSPS) ISLA224P20 14 200 ISLA224P13 14 130 ISLA222P25 12 250 D[11:0]P D[11:0]N ISLA222P20 12 200 ORP ORN ISLA222P13 12 130 OUTFMT OUTMODE SPI CONTROL CSB SCLK SDIO SDO VINAN RESOLUTION OVSS VINBP CLKOUTN MODEL Pin-Compatible Family MODEL RESOLUTION SPEED (MSPS) ISLA224P25 14 250 FN7853 Rev 1.00 June 17, 2011 Page 1 of 33 ISLA222P Pin Configuration - LVDS Mode AVDD AVDD AVDD SDIO SCLK CSB SDO OVSS ORP ORN OVDD OVSS DNC DNC DNC DNC D0P D0N ISLA222P (72 LD QFN) TOP VIEW 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 DNC 1 54 D1P DNC 2 53 D1N NAPSLP 3 52 D2P VCM 4 51 D2N AVSS 5 50 D3P VINBP 6 49 D3N VINBN 7 48 CLKOUTP AVSS 8 47 CLKOUTN AVDD 9 46 RLVDS AVDD 10 45 OVSS AVSS 11 44 D4P VINAN 12 43 D4N VINAP 13 42 D5P AVSS 14 41 D5N CLKDIV 15 40 D6P IPTAT 16 39 D6N Thermal Pad Not Drawn to Scale. Consult Mechanical Drawing for Physical Dimensions DNC 17 38 D7P Connect Thermal Pad to AVSS 37 D7N 23 24 25 26 27 28 29 30 31 32 AVDD AVDD CLKP CLKN CLKDIVRSTP CLKDIVRSTN OVSS OVDD D11N D11P D10N D10P OVDD 33 34 35 36 D8P 22 D8N 21 D9P 20 D9N 19 AVDD RESETN 18 Pin Descriptions - 72 Ld QFN, LVDS Mode PIN NUMBER LVDS PIN NAME LVDS PIN FUNCTION 1, 2, 17, 57, 58, 59, 60 DNC Do Not Connect 9, 10, 19, 20, 21, 70, 71, 72 AVDD 1.8V Analog Supply 5, 8, 11, 14 AVSS Analog Ground 27, 32, 62 OVDD 1.8V Output Supply 26, 45, 61, 65 OVSS Output Ground 3 NAPSLP Tri-Level Power Control (Nap, Sleep modes) 4 VCM 6, 7 VINBP, VINBN Channel B Analog Input Positive, Negative 12, 13 VINAN, VINAP Channel A Analog Input Negative, Positive FN7853 Rev 1.00 June 17, 2011 Common Mode Output Page 2 of 33 ISLA222P Pin Descriptions - 72 Ld QFN, LVDS Mode (Continued) PIN NUMBER LVDS PIN NAME LVDS PIN FUNCTION 15 CLKDIV 16 IPTAT 18 RESETN 22, 23 CLKP, CLKN 24, 25 CLKDIVRSTP, CLKDIVRSTN 28, 29 D11N, D11P LVDS Bit 11 (MSB) Output Complement, True 30, 31 D10N, D10P LVDS Bit 10 Output Complement, True 33, 34 D9N, D9P LVDS Bit 9 Output Complement, True 35, 36 D8N, D8P LVDS Bit 8 Output Complement, True 37, 38 D7N, D7P LVDS Bit 7 Output Complement, True 39, 40 D6N, D6P LVDS Bit 6 Output Complement, True 41, 42 D5N, D5P LVDS Bit 5 Output Complement, True 43, 44 D4N, D4P LVDS Bit 4 Output Complement, True 46 RLVDS 47, 48 CLKOUTN, CLKOUTP LVDS Clock Output Complement, True 49, 50 D3N, D3P LVDS Bit 3 Output Complement, True Tri-Level Clock Divider Control Temperature Monitor (Output current proportional to absolute temperature) Power On Reset (Active Low) Clock Input True, Complement Synchronous Clock Divider Reset True, Complement LVDS Bias Resistor (connect to OVSS with 1% 10k) 51, 52 D2N, D2P LVDS Bit 2 Output Complement, True 53, 54 D1N, D1P LVDS Bit 1 Output Complement, True 55, 56 D0N, D0P LVDS Bit 0 (LSB) Output Complement, True 63, 64 ORN, ORP LVDS Over Range Complement, True 66 SDO SPI Serial Data Output 67 CSB SPI Chip Select (active low) 68 SCLK SPI Clock 69 SDIO SPI Serial Data Input/Output Exposed Paddle AVSS Analog Ground FN7853 Rev 1.00 June 17, 2011 Page 3 of 33 ISLA222P Pin Configuration - CMOS Mode AVDD AVDD AVDD SDIO SCLK CSB SDO OVSS OR DNC OVDD OVSS DNC DNC DNC DNC D0 DNC ISLA222P (72 LD QFN) TOP VIEW 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 DNC 1 54 D1 DNC 2 53 DNC NAPSLP 3 52 D2 VCM 4 51 DNC AVSS 5 50 D3 VINBP 6 49 DNC VINBN 7 48 CLKOUT AVSS 8 47 DNC AVDD 9 46 RLVDS AVDD 10 45 OVSS AVSS 11 44 D4 VINAN 12 43 DNC VINAP 13 42 D5 AVSS 14 41 DNC CLKDIV 15 16 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CLKDIVRSTP CLKDIVRSTN OVSS OVDD DNC D11 DNC D10 OVDD DNC D9 DNC D8 37 DNC CLKN 18 CLKP RESETN 38 D7 AVDD 17 AVDD DNC 39 DNC Connect Thermal Pad to AVSS AVDD IPTAT 40 D6 Thermal Pad Not Drawn to Scale. Consult Mechanical Drawing for Physical Dimensions Pin Descriptions - 72 Ld QFN, CMOS Mode PIN NUMBER CMOS PIN NAME 1, 2, 17, 28, 30, 33, 35, 37, 39, 41, 43, 47, 49, 51, 53, 55, 57, 58, 59, 60, 63 DNC Do Not Connect 9, 10, 19, 20, 21, 70, 71, 72 AVDD 1.8V Analog Supply 5, 8, 11, 14 AVSS Analog Ground 27, 32, 62 OVDD 1.8V Output Supply 26, 45, 61, 65 OVSS Output Ground 3 NAPSLP 4 VCM FN7853 Rev 1.00 June 17, 2011 CMOS PIN FUNCTION Tri-Level Power Control (Nap, Sleep modes) Common Mode Output Page 4 of 33 ISLA222P Pin Descriptions - 72 Ld QFN, CMOS Mode PIN NUMBER (Continued) CMOS PIN NAME CMOS PIN FUNCTION 6, 7 VINBP, VINBN Channel B Analog Input Positive, Negative 12, 13 VINAN, VINAP Channel A Analog Input Negative, Positive 15 CLKDIV 16 IPTAT 18 RESETN 22, 23 CLKP, CLKN 24, 25 CLKDIVRSTP, CLKDIVRSTN 29 D11 CMOS Bit 11 (MSB) Output 31 D10 CMOS Bit 10 Output 34 D9 CMOS Bit 9 Output 36 D8 CMOS Bit 8 Output 38 D7 CMOS Bit 7 Output 40 D6 CMOS Bit 6 Output 42 D5 CMOS Bit 5 Output 44 D4 CMOS Bit 4 Output 46 RLVDS 48 CLKOUT CMOS Clock Output 50 D3 CMOS Bit 3 Output 52 D2 CMOS Bit 2 Output 54 D1 CMOS Bit 1 Output 56 D0 CMOS Bit 0 (LSB) Output 64 OR CMOS Over Range 66 SDO SPI Serial Data Output 67 CSB SPI Chip Select (active low) 68 SCLK SPI Clock 69 SDIO SPI Serial Data Input/Output Exposed Paddle AVSS Analog Ground FN7853 Rev 1.00 June 17, 2011 Tri-Level Clock Divider Control Temperature Monitor (Output current proportional to absolute temperature) Power On Reset (Active Low) Clock Input True, Complement Synchronous Clock Divider Reset True, Complement LVDS Bias Resistor (connect to OVSS with 1% 10k) Page 5 of 33 ISLA222P Ordering Information PART NUMBER (Notes 1, 2) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISLA222P13IRZ ISLA222P13 IRZ -40°C to +85°C 72 Ld QFN L72.10x10E ISLA222P20IRZ ISLA222P20 IRZ -40°C to +85°C 72 Ld QFN L72.10x10E ISLA222P25IRZ ISLA222P25 IRZ -40°C to +85°C 72 Ld QFN L72.10x10E ISLA224IR72EV1Z 14 Bit ADC Evaluation Board - This board can be configured for 12-bit testing NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA222P. For more information on MSL please see techbrief TB363. FN7853 Rev 1.00 June 17, 2011 Page 6 of 33 ISLA222P Table of Contents Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 19 19 19 19 20 20 20 Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 24 24 24 25 27 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 A/D Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 31 31 31 31 31 31 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FN7853 Rev 1.00 June 17, 2011 Page 7 of 33 ISLA222P Absolute Maximum Ratings Thermal Information AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Latch Up (Tested per JESD-78C; Class 2, Level A) . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . . 23 0.9 Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40°C to +85°C. ISLA222P25 PARAMETER SYMBOL CONDITIONS ISLA222P20 MIN MAX MIN (Note 5) TYP (Note 5) (Note 5) TYP ISLA222P13 MAX MIN (Note 5) (Note 5) TYP MAX (Note 5) UNITS 2.2 VP-P DC SPECIFICATIONS (Note 6) Analog Input Full-Scale Analog Input Range VFS Differential 1.95 2.0 2.2 1.95 2.0 2.2 1.95 2.0 Input Resistance RIN Differential 600 600 600  Input Capacitance CIN Differential 4.5 4.5 4.5 pF Full Temp 108 82 75 ppm/°C Full-Scale Range Temp. Drift AVTC Input Offset Voltage VOS Common-Mode Output Voltage VCM 0.94 0.94 0.94 V Common-Mode Input Current (per pin) ICM 2.6 2.6 2.6 µA/MSPS Inputs Common Mode Voltage 0.9 0.9 0.9 V CLKP, CLKN Input Swing 1.8 1.8 1.8 V -7.0 -1.7 7.0 -5.0 -1.7 5.0 -5.0 -1.7 5.0 mV Clock Inputs Power Requirements 1.8V Analog Supply Voltage AVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V 1.8V Digital Supply Voltage OVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V 1.8V Analog Supply Current IAVDD 374 389 344 376 293 312 mA 1.8V Digital Supply Current (Note 6) IOVDD 3mA LVDS 83 90 78 85 68 75 mA Power Supply Rejection Ratio PSRR 30MHz, 50mVP-P signal on AVDD -65 FN7853 Rev 1.00 June 17, 2011 -65 -65 dB Page 8 of 33 ISLA222P Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) ISLA222P25 PARAMETER SYMBOL CONDITIONS ISLA222P20 MIN MAX MIN (Note 5) TYP (Note 5) (Note 5) TYP ISLA222P13 MAX MIN (Note 5) (Note 5) TYP MAX (Note 5) UNITS Total Power Dissipation Normal Mode PD Nap Mode PD Sleep Mode PD Nap/Sleep Mode Wakeup Time 2mA LVDS 774 3mA LVDS 823 CMOS 765 CSB at logic high Sample Clock Running 709 862 760 614 830 650 691 mW 697 578 mW mW 87 96 83 93 77 85 mW 6 11 6 11 6 10 mW 200 400 630 µs AC SPECIFICATIONS Differential Nonlinearity DNL fIN = 105MHz No Missing Codes -0.9 ±0.16 0.9 -0.5 ±0.12 0.5 -0.5 ±0.12 0.5 LSB Integral Nonlinearity INL fIN = 105MHz -2.0 ±0.8 2.0 -1.5 ±0.6 1.5 -1.5 ±0.6 1.5 LSB Minimum Conversion Rate (Note 7) fS MIN 40 MSPS Maximum Conversion Rate fS MAX Signal-to-Noise Ratio (Note 8) SNR Signal-to-Noise and Distortion (Note 8) Effective Number of Bits (Note 8) FN7853 Rev 1.00 June 17, 2011 40 250 fIN = 30MHz fIN = 105MHz SINAD 200 70.3 69.1 70.2 130 71.0 70.0 70.8 70.5 MSPS 71.3 dBFS 71.1 dBFS fIN = 190MHz 69.7 70.2 70.3 dBFS fIN = 363MHz 68.5 68.8 68.4 dBFS fIN = 461MHz 67.8 67.7 67.3 dBFS fIN = 605MHz 66.6 66.5 65.7 dBFS fIN = 30MHz 70.0 70.8 71.1 dBFS 70.3 dBFS fIN = 105MHz ENOB 40 67.7 69.3 68.6 70.3 68.7 fIN = 190MHz 68.5 69.4 69.3 dBFS fIN = 363MHz 66.7 67.8 68.0 dBFS fIN = 461MHz 65.6 65.8 65.5 dBFS fIN = 605MHz 63.2 61.6 60.0 dBFS fIN = 30MHz 11.34 11.47 11.52 Bits fIN = 105MHz 10.95 11.22 11.10 11.39 11.12 11.39 Bits fIN = 190MHz 11.09 11.24 11.22 Bits fIN = 363MHz 10.79 10.97 11.00 Bits fIN = 461MHz 10.60 10.64 10.59 Bits fIN = 605MHz 10.21 9.94 9.67 Bits Page 9 of 33 ISLA222P Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) ISLA222P25 PARAMETER SYMBOL Spurious-Free Dynamic Range (Note 8) SFDR CONDITIONS MIN MAX MIN (Note 5) TYP (Note 5) (Note 5) TYP fIN = 30MHz fIN = 105MHz ISLA222P20 85 71 78 ISLA222P13 MAX MIN (Note 5) (Note 5) TYP 87 72 80 71 MAX (Note 5) UNITS 86 dBc 78 dBc fIN = 190MHz 76 77 76 dBc fIN = 363MHz 73 75 80 dBc fIN = 461MHz 69 71 71 dBc fIN = 605MHz 67 64 62 dBc Spurious-Free Dynamic SFDRX23 fIN = 30MHz Range Excluding H2, H3 fIN = 105MHz (Note 8) 88 96 99 dBc 92 94 96 dBc fIN = 190MHz 88 91 92 dBc fIN = 363MHz 87 85 88 dBc fIN = 461MHz 88 83 87 dBc fIN = 605MHz 87 81 83 dBc fIN = 70MHz 87 87 86 dBFS fIN = 170MHz 96 102 100 dBFS fIN = 10MHz 105 100 90 dBFS fIN = 121MHz 100 93 90 dBFS 10-12 10-12 700 700 Intermodulation Distortion IMD Channel-to-Channel Isolation Word Error Rate WER 10-12 Full Power Bandwidth FPBW 700 MHz NOTES: 5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output. 7. The DLL Range setting must be changed for low-speed operation. 8. Minimum specification guaranteed when calibrated at +85°C. Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS 0 1 10 µA -25 -12 -7 µA 4 12 µA -415 -300 µA INPUTS Input Current High (RESETN) IIH VIN = 1.8V Input Current Low (RESETN) IIL VIN = 0V Input Current High (SDIO) IIH VIN = 1.8V Input Current Low (SDIO) IIL VIN = 0V Input Voltage High (SDIO, RESETN) VIH Input Voltage Low (SDIO, RESETN) VIL Input Current High (CLKDIV) (Note 9) IIH 16 Input Current Low (CLKDIV) IIL -34 Input Capacitance CDI FN7853 Rev 1.00 June 17, 2011 -600 1.17 V 0.63 V 25 34 µA -25 -16 µA 3 pF Page 10 of 33 ISLA222P Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS LVDS INPUTS (CLKDIVRSTP, CLKDIVRSTN) Input Common Mode Range VICM 825 1575 mV Input Differential Swing (peak-to-peak, single-ended) VID 250 450 mV CLKDIVRSTP Input Pull-down Resistance RIpd 100 k CLKDIVRSTN Input Pull-up Resistance RIpu 100 k 612 mVP-P LVDS OUTPUTS Differential Output Voltage (Note 10) Output Offset Voltage VT 3mA Mode VOS 3mA Mode 1120 1150 1200 mV Output Rise Time tR 240 ps Output Fall Time tF 240 ps OVDD - 0.1 V CMOS OUTPUTS Voltage Output High VOH IOH = -500µA Voltage Output Low VOL IOL = 1mA OVDD - 0.3 0.1 0.3 V Output Rise Time tR 1.8 ns Output Fall Time tF 1.4 ns NOTES: 9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing. Timing Diagrams INP INN tA CLKN CLKP LATENCY = L CYCLES tCPD CLKOUTN CLKOUTP tDC D[11:0]N D[11:0]P tPD A DATA N-L B DATA N-L A DATA N-L+1 B DATA N-L+1 B DATA N-1 A DATA N B DATA N FIGURE 1. LVDS FN7853 Rev 1.00 June 17, 2011 Page 11 of 33 ISLA222P Timing Diagrams (Continued) INP INN tA CLKN CLKP LATENCY = L CYCLES tCPD CLKOUT tDC tPD A DATA N-L D[11:0] B DATA N-L A DATA N-L+1 B DATA N-L+1 B DATA N-1 A DATA N B DATA N FIGURE 2. CMOS Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL CONDITION MIN (Note 5) TYP MAX (Note 5) UNITS ADC OUTPUT Aperture Delay tA 114 ps RMS Aperture Jitter jA 75 fs Input Clock to Output Clock Propagation Delay Relative Input Clock to Output Clock Propagation Delay (Note 13) tCPD AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C 1.65 2.4 3 ns tCPD AVDD, OVDD = 1.8V, TA = +25°C 1.9 2.3 2.75 ns dtCPD AVDD, OVDD = 1.7V to 1.9V, TA = -40°C to +85°C -450 450 ps Input Clock to Data Propagation Delay tPD Output Clock to Data Propagation Delay, LVDS Mode tDC Output Clock to Data Propagation Delay, CMOS Mode tDC Synchronous Clock Divider Reset Setup Time (with respect to the positive edge of CLKP) tRSTS Synchronous Clock Divider Reset Hold Time (with respect to the positive edge of CLKP) tRSTH Synchronous Clock Divider Reset Recovery Time tRSTRT Latency (Pipeline Delay) Overvoltage Recovery FN7853 Rev 1.00 June 17, 2011 1.65 2.4 3.5 ns Rising/Falling Edge -0.1 0.16 0.5 ns Rising/Falling Edge -0.1 0.2 0.65 ns 0.4 0.06 0.02 DLL recovery time after Synchronous Reset ns 0.35 ns 52 µs L 10 cycles tOVR 1 cycles Page 12 of 33 ISLA222P Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) PARAMETER SYMBOL MIN (Note 5) CONDITION TYP MAX (Note 5) UNITS SPI INTERFACE (Notes 11, 12) SCLK Period tCLK Write Operation 7 cycles tCLK Read Operation 16 cycles CSB to SCLKSetup Time tS Read or Write 28 cycles CSB after SCLK Hold Time tH Write 5 cycles CSB after SCLK↓ Hold Time tHR Read 16 cycles Data Valid to SCLK Setup Time tDS Write 6 cycles Data Valid after SCLK Hold Time tDH Read or Write 4 cycles Data Valid after SCLK↓ Time tDVR Read 5 cycles NOTES: 11. SPI Interface timing is directly proportional to the ADC sample period (tS). Values in Switching Specifications table reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication. 12. The SPI may operate asynchronously with respect to the ADC sample clock. 13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is specified over the full operating temperature and voltage range. Typical Performance Curves All typical performance characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. -65 HD2 AND HD3 MAGNITUDE (dBc) SNR (dBFS) AND SFDR (dBc) 90 85 SFDR AT 130MSPS 80 SFDR AT 250MSPS 75 SNR AT 130MSPS 70 65 60 SNR AT 250MSPS 0 100 200 300 400 INPUT FREQUENCY (MHz) 500 HD3 AT 250MSPS -75 -80 HD3 AT 130MSPS -85 -90 -95 HD2 AT 130MSPS -100 -105 600 HD2 AT 250MSPS -70 0 FIGURE 3. SNR AND SFDR vs fIN HD2 AND HD3 MAGNITUDE (dBc) 80 SNR AND SFDR 500 600 -10 0 -30 90 SFDR (dBfs) 70 SNR (dBfs) 50 SFDR (dBc) 40 SNR (dBc) 30 20 10 -60 200 300 400 INPUT FREQUENCY (MHz) FIGURE 4. HD2 AND HD3 vs fIN 100 60 100 -50 -40 -30 -20 INPUT AMPLITUDE (dBFS) FIGURE 5. SNR AND SFDR vs AIN FN7853 Rev 1.00 June 17, 2011 -10 0 -40 HD2 (dBc) -50 -60 -70 -80 HD3 (dBc) HD2 (dBFS) -90 HD3 (dBFS) -100 -110 -60 -50 -40 -30 -20 INPUT AMPLITUDE (dBFS) FIGURE 6. HD2 AND HD3 vs AIN Page 13 of 33 ISLA222P Typical Performance Curves All typical performance characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued) -75 SFDR AIN = -2dBFS 82 HD2 AND HD3 MAGNITUDE (dBc) SNR (dBFS) AND SFDR (dBc) 84 80 78 SFDR AIN = -1dBFS 76 74 SNR AIN = -1dBFS 72 70 70 90 110 130 150 170 190 SAMPLE RATE (MSPS) 210 230 -85 -90 -95 H2 -100 -105 250 H3 -80 70 850 1.0 800 0.8 650 LVDS 600 550 250 0.2 0 -0.2 -0.6 CMOS 450 60 80 -0.8 100 120 140 160 180 SAMPLE RATE (MSPS) 200 220 -1.0 240 0 FIGURE 9. POWER vs fSAMPLE IN 3mA LVDS AND CMOS MODES 78 SNR (dBFS) AND SFDR (dBc) 80 0.8 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 500 1000 1500 2000 2500 CODES 3000 FIGURE 11. INTEGRAL NONLINEARITY FN7853 Rev 1.00 June 17, 2011 3500 4000 500 1000 1500 2000 2500 CODES 3000 3500 4000 FIGURE 10. DIFFERENTIAL NONLINEARITY 1.0 0.6 INL (LSBs) 230 -0.4 500 0 210 0.4 700 -1.0 130 150 170 190 SAMPLE RATE (MSPS) 0.6 750 400 40 110 FIGURE 8. HD2 AND HD3 vs fSAMPLE DNL (LSBs) TOTAL POWER (mW) FIGURE 7. SNR AND SFDR vs fSAMPLE 90 SFDR 76 74 72 70 68 SNR 66 64 62 60 0.75 0.85 0.95 1.05 INPUT COMMON MODE (V) 1.15 FIGURE 12. SNR AND SFDR vs VCM Page 14 of 33 ISLA222P Typical Performance Curves All typical performance characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued) 140000 0 126,227 100000 80000 AMPLITUDE (dBFS) NUMBER OF HITS 120000 73,478 60000 40000 0 0 0 0 294 1 0 0 0 20 40 60 80 FREQUENCY (MHz) 100 120 AIN = -1.0dBFS SNR = 68.9dBFS SFDR = 75.0dBc SINAD = 67.7dBFS -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 0 0 AIN = -1.0dBFS SNR = 69.9dBFS SFDR = 76.8dBc SINAD = 68.7dBFS -60 -80 -40 -60 -80 -100 -100 0 20 40 60 80 FREQUENCY (MHz) 100 -120 120 FIGURE 15. SINGLE-TONE SPECTRUM @ 190MHz 20 40 60 80 FREQUENCY (MHz) 100 120 0 IMD2 IMD3 2ND HARMONICS 3RD HARMONICS -40 -60 -80 IMD2 IMD3 2ND HARMONICS 3RD HARMONICS -20 AMPLITUDE (dBFS) -20 IMD3 = 87dBFS -40 -60 IMD3 = 96dBFS -80 -100 -100 -120 0 FIGURE 16. SINGLE-TONE SPECTRUM @ 363MHz 0 AMPLITUDE (dBFS) -80 FIGURE 14. SINGLE-TONE SPECTRUM @ 105MHz -40 -120 -60 -120 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 CODE FIGURE 13. NOISE HISTOGRAM -20 -40 -100 20000 0 AIN = -1.0dBFS SNR = 70.3dBFS -20 SFDR = 78.8dBc SINAD = 69.5dBFS 0 20 40 60 80 FREQUENCY (MHz) FIGURE 17. TWO-TONE SPECTRUM (F1 = 70MHz, F2 = 71MHz AT -7dBFS) FN7853 Rev 1.00 June 17, 2011 100 120 -120 0 20 40 60 80 FREQUENCY (MHz) 100 120 FIGURE 18. TWO-TONE SPECTRUM (F1 = 170MHz, F2 = 171MHz AT -7dBFS) Page 15 of 33 ISLA222P Theory of Operation Functional Description The ISLA222P is based on a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (see Figure 20). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. Digital error correction is also applied, resulting in a total latency of 10 clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. Power-On Calibration As mentioned previously, the cores perform a self-calibration at start-up. An internal power-on-reset (POR) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. The following conditions must be adhered to for the power-on calibration to execute successfully: • A frequency-stable conversion clock must be applied to the CLKP/CLKN pins After the power supply has stabilized, the internal POR releases RESETN and an internal pull-up pulls it high, which starts the calibration sequence. If a subsequent user-initiated reset is desired, the RESETN pin should be connected to an open-drain driver with an off-state/high impedance state leakage of less than 0.5mA to assure exit from the reset state so calibration can start. The calibration sequence is initiated on the rising edge of RESETN, as shown in Figure 19. Calibration status can be determined by reading the cal_status bit (LSB) at 0xB6. This bit is ‘0’ during calibration and goes to a logic ‘1’ when calibration is complete. The data outputs produce 0xCCCC during calibration; this can also be used to determine calibration status. While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is set low. Normal operation of the output clock resumes at the next input clock edge (CLKP/CLKN) after RESETN is de-asserted. At 250MSPS the nominal calibration time is 200ms, while the maximum calibration time is 550ms. CLKN CLKP CALIBRATION TIME RESETN CAL_STATUS BIT • DNC pins must not be connected CALIBRATION BEGINS • SDO has an internal pull-up and should not be driven externally • RESETN is pulled low by the ADC internally during POR. External driving of RESETN is optional. CALIBRATION COMPLETE CLKOUTP • SPI communications must not be attempted FIGURE 19. CALIBRATION TIMING A user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. CLOCK GENERATION INP SHA INN 1.25V + – 2.5-BIT FLASH 2.5-BIT FLASH 6- STAGE 1.5-BIT/ STAGE 3- STAGE 1-BIT/ STAGE 3-BIT FLASH DIGITAL ERROR CORRECTION LVDS/LVCMOS OUTPUTS FIGURE 20. A/D CORE BLOCK DIAGRAM FN7853 Rev 1.00 June 17, 2011 Page 16 of 33 ISLA222P User Initiated Reset Recalibration of the A/D can be initiated at any time by driving the RESETN pin low for a minimum of one clock cycle. An open-drain driver with a less than 0.5mA pull-up is recommended, as RESETN has an internal pull-up to OVDD. As is the case during power-on reset, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. The performance of the ISLA222P changes with variations in temperature, supply voltage or sample rate. The extent of these changes may necessitate recalibration, depending on system performance requirements. Best performance will be achieved by recalibrating the A/D under the environmental conditions at which it will operate. A supply voltage variation of