ISLA222S20IR1Z

DATASHEET ISLA222S FN8302 Rev 1.00 July 6, 2015 Dual 12-bit, 250/200/125 MSPS JESD204B High Speed Serial Output ADC The ISLA222S is a series of low-power, high-performance, dual-channel 12-bit, analog-to-digital converters. Designed with FemtoCharge™ technology on a standard CMOS process, the series supports sampling rates of up to 250MSPS. The ISLA222S is part of a pin-compatible family of 12- and 14-bit dual-channel A/Ds with maximum sample rates ranging from 125MSPS to 250MSPS and shares the same analog core as Intersil's proven ISLA222P series of ADCs. The family minimizes power consumption while providing state of the art dynamic performance, offering an optimal performance vs power trade-off. Features Differentiating the ISLA222S from the ISLA222P is its highly configurable, JESD204B-compliant, high-speed serial output link. The link offers data rates up to 4.375Gbps per lane and multiple packing modes. It can be configured to use one, two, or three lanes to transmit the conversion data, allowing for flexibility in the receiver design. The SERDES transmitter also provides deterministic latency and multi-chip time alignment support to satisfy an application's complex synchronization requirements. • SPI programmable debugging features and test patterns A Serial Peripheral Interface (SPI) port allows for extensive configurability of the JESD204B transmitter including access to its built-in link and transport layer test patterns. The SPI port also provides control for numerous additional features including the fine gain and offset adjustments of the two ADC cores as well as the programmable clock divider, enabling 2x and 4x harmonic clocking. The ISLA222S is available in a space saving 7mmx7mm 48 Ld QFN package. The package features a thermal pad for improved thermal performance and is specified over the full industrial temperature range (-40°C to +85°C). • JESD204A/B high-speed data interface - JESD204A compliant - JESD204B device subclass 0 compliant - JESD204B device subclass 2 compatible - Up to 3 JESD204 output lanes running up to 4.375Gbps - Highly configurable JESD204 transmitter • Multiple chip time alignment and deterministic latency support (JESD204B device subclass 2) • 48-pin QFN 7mmx7mm package Key Specifications • SNR at 250/200/125MSPS 70.6/71.2/71.7 dBFS fIN = 30MHz 70.3/70.7/70.9 dBFS fIN = 190MHz • SFDR at 250/200/125MSPS 87/93/95 dBc fIN = 30MHz 84/93/86 dBc fIN = 190MHz • Total Power Consumption: 989mW at 250MSPS Applications • Radar and satellite antenna array processing • Broadband communications and microwave receivers • High-performance data acquisition • Communications test equipment • High-speed medical imaging Pin-compatible Family RESOLUTION SPEED (MSPS) ISLA224S25 14 250 ISLA224S20 14 200 ISLA224S12 14 125 ISLA222S25 12 250 ISLA222S20 12 200 ISLA222S12 12 125 MODEL FIGURE 1. SERDES DATA EYE AT 4.375Gbps FN8302 Rev 1.00 July 6, 2015 Page 1 of 38 ISLA222S Table of Contents Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 16 Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 18 18 19 19 19 19 19 20 Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 JESD204 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Initial Lane Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADDRESS 0xDF - 0xF3: JESD204 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address 0xDF-0xEE: JESD204 Parameter Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 27 27 27 28 29 29 SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CML Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 36 36 36 36 36 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 FN8302 Rev 1.00 July 6, 2015 Page 2 of 38 ISLA222S CLKP OVDD OVDD (PLL) SYNC AVDD Block Diagram CLOCK GENERATION CLKN AINP 12-BIT 250MSPS ADC SHA AINN LANE[2:0]P LANE[2:0]N VREF JESD204 TRANSMITTER VCM BINP 12-BIT 250MSPS ADC SHA BINN VREF + – CSB SCLK SDIO SDO OVSS SPI CONTROL RESETN AVSS (PLL) NAPSLP AVSS 1.25V FIGURE 2. BLOCK DIAGRAM Pin Configuration FN8302 Rev 1.00 July 6, 2015 DNC DNC AVDD NAPSLP CLKDIV SDIO SCLK CSB SDO OVDD OVSS OVSS ISLA222S (48 LD QFN) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 VCM 1 36 OVDD AVDD 2 35 OVSS AVSS 3 34 LANE2N BINP 4 33 LANE2P BINN 5 32 OVSS AVSS 6 31 LANE1N AVSS 7 30 LANE1P AINN 8 29 OVSS AINP 9 28 LANE0N AVSS 10 27 LANE0P AVDD 11 DNC 12 26 OVSS PAD – Exposed Paddle 13 14 15 16 17 18 19 20 21 22 23 24 RESETN AVDD AVDD CLKP CLKN SYNCP SYNCN DNC OVSS (PLL) OVDD (PLL) OVSS (PLL) OVDD (PLL) 25 OVDD Page 3 of 38 ISLA222S Pin Descriptions PIN NUMBER NAME FUNCTION 2, 11, 14, 15, 46 AVDD 1.8V Analog Supply 12, 20, 47, 48 DNC Do Not Connect 3, 6, 7, 10 AVSS Analog Ground 4, 5 BINP, BINN B-Channel Analog Input Positive, Negative 8, 9 AINN, AINP A-Channel Analog Input Negative, Positive 1 VCM 44 CLKDIV 16, 17 CLKP, CLKN 45 NAPSLP Power Control (Nap, Sleep modes) 13 RESETN Power On Reset (Active Low) 26, 29, 32, 35, 37, 38 OVSS Output Ground 25, 36, 39 OVDD 1.8V Digital Supply 22, 24 OVDD (PLL) 1.8V Analog Supply for SERDES PLL 21, 23 OVSS (PLL) Analog Ground Supply for SERDES PLL 18, 19 SYNCP, SYNCN 27, 28 LANE0P, LANE0N SERDES Lane 0 30, 31 LANE1P, LANE1N SERDES Lane 1 33, 34 LANE2P, LANE2N SERDES Lane 2 40 SDO SPI Serial Data Output 41 CSB SPI Chip Select (active low) 42 SCLK SPI Clock 43 SDIO SPI Serial Data Input/Output PAD - Common Mode Output Clock Divider Control Clock Input True, Complement JESD204 SYNC Input Exposed Paddle. Analog Ground (connect to AVSS) Ordering Information PART NUMBER (Notes 1, 2) PART MARKING TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # ISLA222S25IR1Z ISLA222S25 IR1Z -40 to +85 48 Ld QFN L48.7x7G ISLA222S20IR1Z ISLA222S20 IR1Z -40 to +85 48 Ld QFN L48.7x7G ISLA222S12IR1Z ISLA222S12 IR1Z -40 to +85 48 Ld QFN L48.7x7G ISLA224S25IR48EV1Z FMC Based Evaluation Board (Supports 125/200/250 speed grades), Dual 14-bit Evaluation Board, which can be configured for 12-bit operation; Interfaces with ADCMB-HSFMCEV1Z Motherboard and Other FPGA Vendor FMC Based Evaluation Platforms. ADCMB-HSFMCEV1Z FMC Based Motherboard NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA222S12, ISLA222S20, ISLA222S25. For more information on MSL please see techbrief TB363. FN8302 Rev 1.00 July 6, 2015 Page 4 of 38 ISLA222S Absolute Maximum Ratings Thermal Information AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Latch-up (Tested per JESD-78C; Class 2, Level A). . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 48 Ld QFN (Notes 3, 4, 5) . . . . . . . . . . . . . . 24 0.4 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 5. For solder stencil layout and reflow guidelines, please see Tech Brief. TB389 Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply across the operating temperature range, -40°C to +85°C. ISLA222S25 PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP 1.9 2.00 ISLA222S20 ISLA222S12 MAX MIN MAX MIN MAX (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) UNIT DC SPECIFICATIONS Analog Input Full Scale Analog Input Range VFS Differential Input Resistance RIN Differential 600 600 600 Ω Input Capacitance CIN Differential 7.4 7.4 7.4 pF Full Temp 115 58 58 ppm/°C 2.1 1.9 2.0 2.1 1.9 2.0 2.1 VP-P Full Scale Range Temp. Drift AVTC Input Offset Voltage VOS ±1 ±1 ±1 mV Gain Error EG 1 1 1 % Common-mode Output Voltage VCM 0.94 0.94 0.94 V Common Mode Input Current (per pin) ICM 6.0 6.0 6.0 µA/MSPS Inputs Common Mode Voltage 0.9 0.9 0.9 V CLKP, CLKN Swing 1.8 1.8 1.8 V Clock Inputs Power Requirements 1.8V Analog Supply Voltage AVDD 1.8 1.8 1.8 V 1.8V Digital Supply Voltage OVDD 1.8 1.8 1.8 V 1.8V Analog Supply Current IAVDD 353 397 324 365 282 316 mA 1.8V Digital Supply Current IOVDD 195 218 179 200 123 173 mA FN8302 Rev 1.00 July 6, 2015 Minimum number of lanes active Page 5 of 38 ISLA222S Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued) ISLA222S25 PARAMETER SYMBOL Power Supply Rejection Ratio (Note 7) PSRR TEST CONDITIONS MIN (Note 6) TYP ISLA222S20 ISLA222S12 MAX MIN MAX MIN MAX (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) UNIT 30MHz 200mVP-P 40 40 40 dB 1MHz 200mVP-P 47 47 47 dB Total Power Dissipation Normal Mode PD 989 1107 910 1017 731 843 mW Nap Mode PD 422 484 391 450 290 398 mW Sleep Mode PD CSB at logic high 6 12 6 12 6 12 mW Nap Mode Wakeup Time Sample Clock Running 5 5 5 µs Sleep Mode Wakeup Time Sample Clock Running 1 1 1 ms -1.0 ±0.1 LSB -1.0 0.5 AC SPECIFICATIONS (Note 8) Differential Nonlinearity DNL Integral Nonlinearity INL Minimum Conversion Rate (Note 9) fS MIN fIN = 105MHz No Missing Codes -1.0 ±0.15 -1.5 0.8 1.5 -1.0 ±0.1 -1.0 0.4 100 ISLA222S25, ISLA222S20 (3 Lanes, Efficient Packing) 1.0 100 1.0 50 LSB MSPS ISLA222S12 (2 Lanes, Simple Packing) Maximum Conversion Rate fS MAX Efficient Packing Independent of Packing Mode Maximum Serdes Lane Data Rate (See “Lane data rate” on page 22.) Independent of Packing Mode FN8302 Rev 1.00 July 6, 2015 200 125 MSPS Simple Packing Minimum Serdes Lane Data Rate Signal-to-noise Ratio (Note 10) 250 SNR MSPS 1.0 3.75 fIN = 30MHz fIN = 105MHz 4.375 1.0 3.0 70.6 69.4 70.6 4.375 3.75 71.2 70.3 71.1 70.7 1.0 GBPS 4.375 GBPS 71.7 dBFS 71.5 dBFS fIN = 190MHz 70.3 70.7 70.9 dBFS fIN = 363MHz 69.4 69.5 69.3 dBFS fIN = 495MHz 68.6 68.5 68.0 dBFS fIN = 605MHz 67.9 67.6 66.9 dBFS Page 6 of 38 ISLA222S Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued) ISLA222S25 PARAMETER Signal-to-noise and Distortion (Note 10) Effective Number of Bits (Note 10) Spurious-free Dynamic Range (Note 10) Spurious-Free Dynamic Range Excluding H2, H3 (Note 10) Intermodulation Distortion SYMBOL SINAD TEST CONDITIONS fIN = 30MHz fIN = 105MHz ENOB SFDR MIN (Note 6) 70.4 71.1 70.2 71.0 70.4 UNIT 71.7 dBFS 71.3 dBFS 70.0 70.5 70.7 dBFS fIN = 363MHz 69.0 68.9 67.8 dBFS fIN = 495MHz 65.4 64.0 61.4 dBFS fIN = 605MHz 59.3 58.0 54.1 dBFS fIN = 30MHz 11.42 11.52 11.61 Bits fIN = 105MHz 11.17 11.40 11.37 11.50 11.40 11.55 Bits fIN = 190MHz 11.34 11.42 11.46 Bits fIN = 363MHz 11.16 11.16 10.97 Bits fIN = 495MHz 10.57 10.34 9.91 Bits fIN = 605MHz 9.56 9.35 8.69 Bits fIN = 30MHz 87 93 95 dBc 87 dBc 74 83 76 89 76 fIN = 190MHz 84 93 86 dBc fIN = 363MHz 79 88 71 dBc fIN = 495MHz 66 85 61 dBc fIN = 605MHz 58 83 52 dBc 87 93 98 dBc fIN = 105MHz 89 95 96 dBc fIN = 190MHz 88 93 90 dBc fIN = 363MHz 84 88 85 dBc fIN = 495MHz 85 85 82 dBc fIN = 605MHz 88 83 81 dBc fIN = 70MHz -84 -82 -81 dBFS fIN = 170MHz -92 -99 -100 dBFS fIN = 10MHz 88 90 100 dB fIN = 124MHz 82 87 86 dB 10-13 10-13 675 675 SFDRX23 fIN = 30MHz Channel-to-channel Isolation MAX MIN MAX MIN MAX (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) 70.5 69.0 ISLA222S12 fIN = 190MHz fIN = 105MHz IMD TYP ISLA222S20 Word Error Rate WER 10-13 Full Power Bandwidth FPBW 675 MHz NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. PSRR is calculated by the equation 20*log10(A/B), where B is the amplitude of a disturber sinusoid on AVDD at the device pins, and A is the amplitude of the spur in the captured data at the frequency of the disturber sinusoid. 8. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to “Power-on Calibration” on page 15 and “User Initiated Reset” on page 16 for more detail. 9. The DLL Range setting must be changed via SPI for ADC core sample rates below 80MSPS. The JESD204 transmitter can support ADC sample rates below 100MSPS, as long as the SERDES lane data rate is greater than or equal to 1Gbps. 10. Minimum specification guaranteed when calibrated at +85°C. FN8302 Rev 1.00 July 6, 2015 Page 7 of 38 ISLA222S Digital Specifications Boldface limits apply across the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT 1 10 µA -12 -7 µA 4 12 µA -600 -400 -300 µA 40 52 70 µA 1 10 µA CMOS INPUTS Input Current High (RESETN) IIH VIN = 1.8V Input Current Low (RESETN) IIL VIN = 0V Input Current High (SDIO, SCL, SDA SCLK) IIH VIN = 1.8V Input Current Low (SDIO, SCL, SDA SCLK) IIL VIN = 0V Input Current High (CSB) IIH VIN = 1.8V Input Current Low (CSB) IIL VIN = 0V Input Voltage High (SDIO, RESETN) VIH Input Voltage Low (SDIO, RESETN) VIL Input Current High (NAPSLP, CLKDIV) (Note 11) IIH 19 Input Current Low (NAPSLP, CLKDIV) IIL --30 Input Capacitance CDI -25 1.17 V 0.63 V 25 30 µA -25 -19 µA 4 pF LVDS INPUTS (SYNCP, SYNCN) Input Common Mode Range VICM 825 1575 mV Input Differential Swing (peak-to-peak, single-ended) VID 250 450 mV Input Pull-up and Pull-down Resistance RIpu 100 kΩ 1.14 V CML OUTPUTS Output Common Mode Voltage Switching Specifications Boldface limits apply across the operating temperature range, -40°C to +85°C. PARAMETER SYMBOL TEST CONDITION MIN (Note 6) TYP MAX (Note 6) UNIT ADC OUTPUT Aperture Delay tA 190 ps RMS Aperture Jitter jA 100 fs 250 µs L 10 cycles tOVR 1 cycles PLL Lock Time 250 µs PLL Bandwidth 2.2 MHz Added Random Jitter 5 ps RMS Added Deterministic Jitter 7 ps P-P 5 ps rms Synchronous Clock Divider Reset Recovery Time (Note 12) Latency (ADC Pipeline Delay) Overvoltage Recovery tRSTRT DLL recovery time after Synchronous Reset SERDES Maximum Input Sample Clock Total Jitter to Maintain SERDES BER