DATASHEET
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
KAD2708C
FN6812
Rev 1.00
April 14, 2011
8-Bit, 275/210/170/105MSPS A/D Converter
OVDD
CLKDIV
AVDD2
AVDD3
The KAD2708C is the industry’s lowest power, 8-bit,
275MSPS, high performance Analog-to-Digital converter. It
is designed with Intersil’s proprietary FemtoCharge™
technology on a standard CMOS process. The KAD2708C
offers high dynamic performance (49.2dBFS SNR @
fIN = 138MHz) while consuming less than 265mW. Features
include an over-range indicator and a selectable divide-by-2
input clock divider. The KAD2708C is one member of a
pin-compatible family offering 8 and 10-bit ADCs with
sample rates from 105MSPS to 350MSPS and LVCMOS or
LVDS-compatible outputs (Table 1). This family of products
is available in 68-pin RoHS-compliant QFN packages with
exposed paddle. Performance is specified over the full
industrial temperature range (-40°C to +85°C).
Features
• On-Chip Reference
• Internal Track and Hold
• 1.5VP-P Differential Input Voltage
• 600MHz Analog Input Bandwidth
• Two’s Complement or Binary Output
• Over-Range Indicator
• Selectable 2 Clock Input
• LVCMOS Outputs
Applications
• High-Performance Data Acquisition
• Portable Oscilloscope
CLK_P
CLKOUT
Clock
Generation
CLK_N
• Cable Head Ends
D7 – D0
8-bit
275MSPS
ADC
INP
S/H
INN
VREF
+
–
VREFSEL
• Medical Imaging
8
• Power-Amplifier Linearization
• Radar and Satellite Antenna Array Processing
LVCMOS
Drivers
OR
1.21 V
2SC
• Broadband Communications
• Point-to-Point Microwave Systems
• Communications Test Equipment
VCM
AVSS
OVSS
Key Specifications
• SFDR of 66.6dBc at fS = 275MSPS, fIN = 138MHz
Ordering Information
• Power Consumption 265mW at fS = 275MSPS
PART NUMBER
SPEED
(MSPS)
TEMP.
RANGE (°C)
KAD2708C-27Q68
275
-40 to +85
68 Ld QFN L68.10x10B
KAD2708C-21Q68
210
-40 to +85
68 Ld QFN L68.10x10B
KAD2708C-17Q68
170
-40 to +85
68 Ld QFN L68.10x10B
KAD2708C-10Q68
105
-40 to +85
68 Ld QFN L68.10x10B
PACKAGE PKG. DWG. #
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information
page for KAD2708C-10, KAD2708C-17, KAD2708C-21 and
KAD2708C-27. For more information on MSL please see techbrief
TB363.
FN6812 Rev 1.00
April 14, 2011
• SNR of 49.2dBFS at fS = 275MSPS, fIN = 138MHz
Pin-Compatible Family
TABLE 1. PIN-COMPATIBLE PRODUCTS
RESOLUTION, SPEED LVDS OUTPUTS LVCMOS OUTPUTS
8 Bits 350MSPS
KAD2708L-35
10 Bits 275MSPS
KAD2710L-27
KAD2710C-27
8 Bits 275MSPS
KAD2708L-27
KAD2708C-27
10 Bits 210MSPS
KAD2710L-21
KAD2710C-21
8 Bits 210MSPS
KAD2708L-21
KAD2708C-21
10 Bits 170MSPS
KAD2710L-17
KAD2710C-17
8 Bits 170MSPS
KAD2708L-17
KAD2708C-17
10 Bits 105MSPS
KAD2710L-10
KAD2710C-10
8 Bits 105MSPS
KAD2708L-10
KAD2708C-10
Page 1 of 17
KAD2708C
Table of Contents
Absolute Maximum Ratings ........................................ 3
Thermal Information ..................................................... 3
Electrical Specifications .............................................. 3
Digital Specifications ................................................... 4
Timing Diagram ............................................................ 6
Timing Specifications .................................................. 6
ESD ................................................................................ 6
Pin Descriptions ........................................................... 7
Pin Configuration ......................................................... 8
Typical Performance Curves ....................................... 9
Functional Description ................................................ 12
Reset ......................................................................... . 12
Voltage Reference ..................................................... . 12
Analog Input .............................................................. . 12
Clock Input ................................................................. . 13
Jitter ........................................................................... . 13
Digital Outputs ........................................................... . 14
Equivalent Circuits ....................................................... 14
Layout Considerations ................................................ 15
Split Ground and Power Planes ................................ . 15
Clock Input Considerations ........................................ . 15
Bypass and Filtering .................................................. . 15
LVCMOS Outputs ...................................................... . 15
Unused Inputs ........................................................... . 15
Definitions ..................................................................... 15
Package Outline Drawing ............................................ 16
FN6812 Rev 1.00
April 14, 2011
Page 2 of 17
KAD2708C
Absolute Maximum Ratings
Thermal Information
AVDD2 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
AVDD3 to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V
OVDD2 to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V
Analog Inputs to AVSS. . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V
Clock Inputs to AVSS. . . . . . . . . . . . . . . . . . -0.4V to AVDD2 + 0.3V
Logic Inputs to AVSS (VREFSEL, CLKDIV) -0.4V to AVDD3 + 0.3V
Logic Inputs to OVSS (RST, 2SC) . . . . . . . . -0.4V to OVDD2 + 0.3V
VREF to AVSS . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD3 + 0.3V
Analog Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Logic Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
CMOS Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Thermal Resistance (Typical, Notes 3, 4) JA (°C/W)
JC (°C/W)
68 Ld QFN Package. . . . . . . . . . . . . . .
23
1.8
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), fSAMPLE = 275MSPS, 210MSPS, 170MSPS and
105MSPS, fIN = Nyquist at -0.5dBFS. Boldface limits apply over the operating temperature range, -40°C to
+85°C.
KAD2708C-27
PARAMETER
MIN
SYMBOL CONDITIONS (Note 5)
TYP
KAD2708C-21
MAX
MIN
(Note 5) (Note 5)
TYP
KAD2708C-17
MAX
MIN
(Note 5) (Note 5)
TYP
KAD2708C-10
MAX
MIN
(Note 5) (Note 5)
TYP
MAX
(Note 5) UNITS
DC SPECIFICATIONS
Analog Input
Full-Scale Analog
Input Range
VFS
Full Scale Range
Temp. Drift
AVTC
Common-Mode
Output Voltage
VCM
1.4
Full Temp
1.5
1.6
1.4
1.5
1.6
1.4
1.5
1.6
1.4
1.5
1.6
VP-P
230
210
198
178
ppm/°C
860
860
860
860
mV
Power Requirements
1.8V Analog
Supply Voltage
AVDD2
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
3.3V Analog
Supply Voltage
AVDD3
3.15
3.3
3.45
3.15
3.3
3.45
3.15
3.3
3.45
3.15
3.3
3.45
V
1.8V Digital
Supply Voltage
OVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Analog
Supply Current
IAVDD2
44
51
38
42
35
39
29
33
mA
3.3V Analog
Supply Current
IAVDD3
41
45
33
37
28
32
21
24
mA
1.8V Digital
Supply Current
I
OVDD
26
30
25
28
24
27
23
26
mA
PD
261
294
222
248
199
224
163
185
mW
Power
Dissipation
AC SPECIFICATIONS
Maximum
Conversion Rate
fS MAX
FN6812 Rev 1.00
April 14, 2011
275
210
170
105
MSPS
Page 3 of 17
KAD2708C
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD2 = 1.8V, AVDD3 = 3.3V,
OVDD = 1.8V, TA = -40°C to +85°C (typical specifications at +25°C), fSAMPLE = 275MSPS, 210MSPS, 170MSPS and
105MSPS, fIN = Nyquist at -0.5dBFS. Boldface limits apply over the operating temperature range, -40°C to
+85°C. (Continued)
KAD2708C-27
PARAMETER
Minimum
Conversion Rate
MIN
SYMBOL CONDITIONS (Note 5)
TYP
fS MIN
KAD2708C-21
MAX
MIN
(Note 5) (Note 5)
KAD2708C-17
MAX
MIN
(Note 5) (Note 5)
TYP
50
TYP
50
KAD2708C-10
MAX
MIN
(Note 5) (Note 5)
TYP
50
MAX
(Note 5) UNITS
50
MSPS
Differential
Nonlinearity
DNL
-0.3
±0.2
0.4
-0.3
±0.2
0.4
-0.3
±0.2
0.4
-0.3
±0.2
0.4
LSB
Integral
Nonlinearity
INL
-0.8
±0.2
0.8
-0.8
±0.2
0.8
-0.8
±0.2
0.8
-0.8
±0.2
0.8
LSB
Signal-to-Noise
Ratio
SNR
Signal-to-Noise
and Distortion
SINAD
fIN = 10MHz
49.5
fIN = Nyquist
46.5
Spurious-Free
Dynamic Range
49.2
46.5
49.2
46.5
dBFS
49.2
dBFS
49.0
49.1
49.1
49.1
dBFS
49.2
49.5
49.5
49.5
dBFS
49.2
dBFS
48.9
dBFS
7.9
Bits
7.9
Bits
46.5
49.2
46.5
48.9
fIN = 10MHz
7.4
49.2
46.5
48.9
7.9
fIN = Nyquist
SFDR
46.5
49.5
fIN = 430MHz
fIN = Nyquist
ENOB
49.2
49.5
fIN = 10MHz
fIN = 430MHz
Effective Number
of Bits
49.5
7.4
46.5
49.0
7.9
7.9
49.2
7.9
7.9
7.4
7.9
7.4
fIN = 430MHz
7.8
7.8
7.8
7.8
Bits
fIN = 10MHz
67.6
69.1
69.1
69.1
dBc
fIN = Nyquist
69.1
dBc
fIN = 430MHz
61
66.1
66.6
61
69.0
69.1
61
69.0
69.1
61
68.9
dBc
fIN = 133MHz,
135MHz
63
65
65
65
dBc
Two-Tone SFDR
2TSFDR
Word Error Rate
WER
10-12
10-12
10-12
10-12
Full Power
Bandwidth
FPBW
600
600
600
600
MHz
NOTE:
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Digital Specifications
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
INPUTS
0.8*AVDD3
V
High Input Voltage (VREFSEL)
VREFSEL VIH
Low Input Voltage (VREFSEL)
VREFSEL VIL
Input Current High (VREFSEL)
VREFSEL IIH
VIN = AVDD3
0
1
10
µA
Input Current Low (VREFSEL)
VREFSEL IIL
VIN = AVSS
25
65
75
µA
High Input Voltage (CLKDIV)
CLKDIV VIH
Low Input Voltage (CLKDIV)
CLKDIV VIL
Input Current High (CLKDIV)
CLKDIV IIH
VIN = AVDD3
25
Input Current Low (CLKDIV)
CLKDIV IIL
VIN = AVSS
0
High Input Voltage (RST,2SC)
RST,2SC VIH
Low Input Voltage (RST,2SC)
RST,2SC VIL
Input Current High (RST,2SC)
RST,2SC IIH
FN6812 Rev 1.00
April 14, 2011
0.2*AVDD3
0.8*AVDD3
V
0.2*AVDD3
V
65
75
µA
1
10
µA
0.8*OVDD2
VIN = OVDD
0
V
V
1
0.2*OVDD2
V
10
µA
Page 4 of 17
KAD2708C
Digital Specifications
PARAMETER
Input Current Low (RST,2SC)
(Continued)
SYMBOL
RST,2SC IIL
CONDITIONS
VIN = OVSS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
25
50
75
µA
3
pF
Input Capacitance
CDI
CLKP, CLKN P-P Differential
Input Voltage
VCDI
CLKP, CLKN Differential Input
Resistance
RCDI
10
M
CLKP, CLKN Common-Mode
Input Voltage
VCCI
0.9
V
Voltage Output High
VOH
1.8
V
Voltage Output Low
VOL
0
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
0.5
3.6
VP-P
LVCMOS OUTPUTS
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6812 Rev 1.00
April 14, 2011
Page 5 of 17
KAD2708C
Timing Diagram
Sample N
INP
INN
tA
CLKN
CLKP
L
tPID
CLKOUT
tPCD
tPH
D[7:0]
Data N-L
Data N-L+1
Data N
invalid
FIGURE 1. LVCMOS TIMING DIAGRAM
Timing Specifications
PARAMETER
SYMBOL
MIN
(Note 7)
TYP
MAX
(Note 7)
UNITS
Aperture Delay
tA
1.7
ns
RMS Aperture Jitter
jA
200
fs
Input Clock to Data Propagation Delay
tPID
3.5
Data Hold Time
tPH
-300
Output Clock to Data Propagation Delay
Latency (Pipeline Delay)
Overvoltage Recovery
5.0
6.5
ns
ps
tPCD
2.8
L
28
cycles
tOVR
1
cycle
3.7
ns
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
ESD
Electrostatic charge accumulates on humans, tools and
equipment and may discharge through any metallic package
contacts (pins, balls, exposed paddle, etc.) of an integrated
circuit. Industry-standard protection techniques have been
utilized in the design of this product. However, reasonable care
must be taken in the storage and handling of ESD sensitive
products. Contact Intersil for the specific ESD sensitivity rating
of this product.
FN6812 Rev 1.00
April 14, 2011
Page 6 of 17
KAD2708C
Pin Descriptions
PIN NUMBER
NAME
1, 14, 18, 20
AVDD2
2, 7, 10, 19, 21, 24
AVSS
Analog Supply Return
3
VREF
Reference Voltage Out/In
4
VREFSEL
5
VCM
6, 15, 16, 25
AVDD3
3.3V Analog Supply
8, 9
INP, INN
Analog Input Positive, Negative
11-13, 29-36, 37, 39, 42, 46, 48,
50, 52, 54, 56, 58, 62, 63, 67
DNC
17
CLKDIV
22, 23
CLKN, CLKP
26, 45, 61
OVSS
27, 41, 44, 60
OVDD2
28
RST
Power On Reset (Active Low)
38
D0
LVCMOS Bit 0 (LSB) Output
40
D1
LVCMOS Bit 1 Output
43
CLKOUT
LVCMOS Clock Output
47
D2
LVCMOS Bit 2 Output
49
D3
LVCMOS Bit 3 Output
51
D4
LVCMOS Bit 4 Output
53
D5
LVCMOS Bit 5 Output
55
D6
LVCMOS Bit 6 Output
57
D7
LVCMOS Bit 7 Output
59
OR
Over-Range
64-66
1.8V Analog Supply
Reference Voltage Select (0:Int 1:Ext)
Common-Mode Voltage Output
Do Not Connect
Clock Divide by Two (Active Low)
Clock Input Complement, True
Output Supply Return
1.8V CMOS Supply
Connect to OVDD2
68
2SC
Exposed Paddle
AVSS
FN6812 Rev 1.00
April 14, 2011
FUNCTION
Two’s Complement Select (Active Low)
Analog Supply Return
Page 7 of 17
KAD2708C
2SC
DNC
OVDD2
OVDD2
OVDD2
DNC
DNC
OVSS
OVDD2
OR
DNC
D7
DNC
D6
DNC
D5
DNC
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
Pin Configuration
AVDD2
AVSS
VREF
1
2
3
51
50
49
D4
DNC
D3
VREFSEL
VCM
4
5
48
47
DNC
D2
AVDD3
6
46
DNC
AVSS
INP
INN
7
8
9
KAD2708C
45
44
43
OVSS
OVDD2
CLKOUT
AVSS
10
DNC
11
68 QFN
42
DNC
41
OVDD2
DNC
DNC
AVDD2
12
13
14
40
39
38
D1
DNC
D0
AVDD3
15
37
DNC
AVDD3
CLKDIV
16
17
36
35
DNC
DNC
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
AVSS
AVDD2
AVSS
CLKN
CLKP
AVSS
AVDD3
OVSS
OVDD2
RST
DNC
DNC
DNC
DNC
DNC
DNC
AVDD2
18
Top View
Not to Scale
FIGURE 2. PIN CONFIGURATION
FN6812 Rev 1.00
April 14, 2011
Page 8 of 17
KAD2708C
Typical Performance Curves
AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25°C, fSAMPLE = 275MSPS, fIN = 137MHz,
AIN = -0.5dBFS unless noted.
-50
70
SFDR
-60
60
HD 2, HD3((dBc)
dBc
S N R( d B F S ), S FD R (dBc)
(dB
-55
65
55
50
HD3
-70
-75
-80
SNR
45
-65
HD2
-85
-90
40
5
105
205
305
f IN (M Hz)
405
5
505
10 5
205
3 05
f IN( MHz)
405
505
FIGURE 4. HD2 AND HD3 vs fIN
FIGURE 3. SNR AND SFDR vs fIN
80
HD3
-30
HD2, HD3 (dBc)
dBc
(dBc)
S N R (d B F S ) , S F D R (d
-20
70
60
-40
SNR
50
-50
HD2
-60
40
SFDR
-70
30
20
-30
-2 5
-20
-1 5
A IN ( d B F S )
-1 0
-5
0
-80
-30
-25
-15
-10
-5
0
300
350
Input Amplitude (dBFS)
FIGURE 5. SNR AND SFDR vs AIN
FIGURE 6. HD2 AND HD3 vs AIN
80
-65
76
SFDR
72
-70
68
HD2, HD3(dBc)
SNR(dBFS), SFDR (dBc)
-20
64
60
56
52
-75
HD3
-80
-85
48
SNR
44
HD2
-90
40
50
100
150
200
250
f SA MP LE (fS ) (MSPS)
FIGURE 7. SNR AND SFDR vs fSAMPLE
FN6812 Rev 1.00
April 14, 2011
300
350
50
100
150
200
250
fSAMPLE (MHz)
FIGURE 8. HD2 AND HD3 vs fSAMPLE
Page 9 of 17
KAD2708C
AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25°C, fSAMPLE = 275MSPS, fIN = 137MHz,
AIN = -0.5dBFS unless noted. (Continued)
280
1
260
0 .75
240
0.5
220
DNL (LS Bs)
Power Dissipation (PD) (mW)
Typical Performance Curves
200
180
160
0 .25
0
-0 .25
140
-0.5
120
-0 .75
100
50
100
150
200
f SAMPLE (f S) (MSPS)
250
-1
300
0
32
64
96
12 8
CODE
160
19 2
2 24
2 55
FIGURE 10. DIFFERENTIAL NONLINEARITY vs OUTPUT CODE
FIGURE 9. POWER DISSIPATION vs fSAMPLE
50,000
1
45,000
0.7 5
40,000
35,000
CODE COUNT
INL (L SBs)
0.5
0.2 5
0
-0.2 5
30,000
25,000
20,000
15,000
-0.5
10,000
-0.7 5
-1
0
5,000
32
64
96
12 8
CODE
1 60
192
224
0
124
255
125
FIGURE 11. INTEGRAL NONLINEARITY vs OUTPUT CODE
128
129
0
Ain = -0.47dBFS
Ain = -0.47dBFS
SNR = 49.4dBFS
-20
-20
SFDR = 68.4dBc
HD2 = -86dBc
-60
HD3 = -69dBc
-80
SNR = 49.4dBFS
SFDR = 69.2dBc
-40
SINAD = 49.3dBFS
-40
AMPLITUDE (dB)
AMPLITUDE (dB)
127
CODE
FIGURE 12. NOISE HISTOGRAM
0
SINAD = 49.4dBFS
HD2 = -81dBc
-60
HD3 = -91dBc
-80
-100
-100
-120
0
126
20
40
60
80
FREQUENCY (MHz)
100
FIGURE 13. OUTPUT SPECTRUM @ 9.865MHz
FN6812 Rev 1.00
April 14, 2011
120
-120
0
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 14. OUTPUT SPECTRUM @ 133.805MHz
Page 10 of 17
130
KAD2708C
Typical Performance Curves
AVDD2 = OVDD2 = 1.8V, AVDD3 = 3.3V, TA = +25°C, fSAMPLE = 275MSPS, fIN = 137MHz,
AIN = -0.5dBFS unless noted. (Continued)
0
0
Ain = -0.48dBFS
Ain = -7.1dBFS
SNR = 49.3dBFS
-20
-20
2TSFDR = 67dBc
IMD3 = -74dBF S
SINAD = 49.1dBFS
-40
HD2 = -63dBc
HD3 = -67dBc
-60
-40
AMPLITUDE (dB)
AMPLITUDE (dB)
SFDR = 63dBc
-80
-60
-80
-100
-100
-120
0
20
40
60
80
FREQUENCY (MHz)
100
-120
120
0
FIGURE 15. OUTPUT SPECTRUM @ 299.645MHz
20
40
60
80
FREQUENCY (MHz)
0
Ain = -7dBFS
Ain = -7dBFS
2TSFDR = 63dBc
-20
2TSF DR = 73dBc
-20
IMD3 = -76dBFS
IMD3 = -81dBFS
-40
AMPLITUDE (dB)
AMPLIT UDE (dB)
-40
-60
-60
-80
-80
-100
-100
0
20
40
60
80
FREQ UENCY (MHz)
100
-120
0
120
FIGURE 17. TWO-TONE SPECTRUM @ 140MHz, 141MHz
20
40
60
80
FREQUENCY (MHz)
100
120
FIGURE 18. TWO-TONE SPECTRUM @ 300MHz, 305MHz
800
75
70
700
SFDR
65
600
60
tCAL (ms)
SNR(dBFS), SFDR(dBc)
120
FIGURE 16. TWO-TONE SPECTRUM @ 69MHz, 70MHz
0
-120
100
500
55
400
50
45
300
SNR
40
-40
-20
0
20
40
60
AMBIENT TEMPERATURE, C
FIGURE 19. SNR AND SFDR vs TEMPERATURE
FN6812 Rev 1.00
April 14, 2011
80
200
100
125
150
175
200
f SAMPLE (f S) (MSPS)
225
250
FIGURE 20. CALIBRATION TIME vs fS
Page 11 of 17
275
KAD2708C
Functional Description
Voltage Reference
The KAD2708 is an 8-bit, 275MSPS A/D converter in a
pipelined architecture. The input voltage is captured by a
sample & hold circuit and converted to a unit of charge.
Proprietary charge domain techniques are used to compare
the input to a series of reference charges. These comparisons
determine the digital code for each input value. The converter
pipeline requires 24 sample clocks to produce a result. Digital
error correction is also applied, resulting in a total latency of 28
clock cycles. This is evident to the user as a latency between
the start of a conversion and the data being available on the
digital outputs.
The VREF pin is the full-scale reference, which sets the
full-scale input voltage for the chip and requires a bypass
capacitor of 0.1µF or larger. An internally generated reference
voltage is provided from a bandgap voltage buffer. This buffer
can sink or source up to 50µA externally.
At start-up, a self-calibration is performed to minimize gain and
offset errors. The reset pin (RST) is initially held low internally
at power-up and will remain in that state until the calibration is
complete. The clock frequency should remain fixed during this
time.
Calibration accuracy is maintained for the sample rate at which
it is performed, and therefore should be repeated if the clock
frequency is changed by more than 10%. Recalibration can be
initiated via the RST pin, or power cycling, at any time.
Reset
Recalibration of the ADC can be initiated at any time by driving
the RST pin low for a minimum of one clock cycle. An opendrain driver is recommended.
The calibration sequence is initiated on the rising edge of RST,
as shown in Figure 21. The over-range output (OR) is set high
once RST is pulled low, and remains in that state until
calibration is complete. The OR output returns to normal
operation at that time, so it is important that the analog input be
within the converter’s full-scale range in order to observe the
transition. If the input is in an over-range state the OR pin will
stay high and it will not be possible to detect the end of the
calibration cycle.
While RST is low, the output clock (CLKOUT) stops toggling
and is set low. Normal operation of the output clock resumes at
the next input clock edge (CLKP/CLKN) after RST is deasserted. At 275MSPS the nominal calibration time is ~240ms.
CLKN
CLKP
Calibration Time
RST
Calibration Begins
OR
An external voltage may be applied to this pin to provide a
more accurate reference than the internally generated
bandgap voltage or to match the full-scale reference among a
system of KAD2708C chips. One option in the latter
configuration is to use one KAD2708C's internally generated
reference as the external reference voltage for the other chips
in the system. Additionally, an externally provided reference
can be changed from the nominal value to adjust the full-scale
input voltage within a limited range.
To select whether the full-scale reference is internally
generated or externally provided, the digital input port
VREFSEL should be set appropriately, low for internal or high
for external.This pin also has an internal 18k pull-up resistor.
To use the internally generated reference, VREFSEL can be
tied directly to AVSS, and to use an external reference,
VREFSEL can be left unconnected.
Analog Input
The fully differential ADC input (INP/INN) connects to the
sample and hold circuit. The ideal full-scale input voltage is
1.5VPP, centered at the VCM voltage of 0.86V as shown in
Figure 22.
V
1.8
1.4
0.75V
INN
INP
VCM
1.0
0.86V
0.6
-0.75V
0.2
t
FIGURE 22. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are
driven differentially in an AC-coupled configuration. The
common-mode output voltage, VCM, should be used to
properly bias each input as shown in Figures 23 and 24. An RF
transformer will give the best noise and distortion performance
for wideband and/or high intermediate frequency (IF) inputs.
The recommended biasing is shown in Figures 23 and 24.
Calibration Complete
CLKOUT
FIGURE 21. CALIBRATION TIMING
FN6812 Rev 1.00
April 14, 2011
Page 12 of 17
KAD2708C
Clock Input
0.01µF
Analog
In
50O
KAD2708
VCM
ADT1-1WT
ADT1-1WT
0.1µF
FIGURE 23. TRANSFORMER INPUT, GENERAL APPLICATION
ADTL1-12
Analog
Input
ADTL1-12
The clock input circuit is a differential pair (see Figure 29).
Driving these inputs with a high level (up to 1.8VPP on each
input) sine or square wave will provide the lowest jitter
performance. The recommended drive circuit is shown in
Figure 26. The clock can be driven single-ended, but this will
reduce the edge rate and may impact SNR performance.
1kO
1kO
AVDD2
CLKP
1nF
25O
1nF
KAD2708
1nF
VCM
25O
1nF
Clock
Input
200O
0.1µF
CLKN
TC4-1W
FIGURE 24. TRANSFORMER INPUT, HIGH IF APPLICATION
A back-to-back transformer scheme is used to improve
common-mode rejection, which keeps the common-mode level
of the input matched to VCM. The value of the termination
resistor should be determined based on the desired
impedance.
The sample and hold circuit design uses a switched capacitor
input stage, which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This creates a
disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 1:1
transformer and low shunt resistance are recommended for
optimal performance.
A differential amplifier can be used in applications that require
DC coupling, at the expense of reduced dynamic performance.
In this configuration the amplifier will typically reduce the
achievable SNR and distortion performance. A typical
differential amplifier configuration is shown in Figure 25.
348O
69.8O
25O
100O
+
Vin
-
151O
0.22µF
CM
VCM
100O
49.9O
25O
69.8O
348O
0.1µF
FIGURE 25. DIFFERENTIAL AMPLIFIER INPUT
FN6812 Rev 1.00
April 14, 2011
KAD2708
FIGURE 26. RECOMMENDED CLOCK DRIVE
Use of the clock divider is optional. The KAD2708C's ADC
requires a clock with 50% duty cycle for optimum performance.
If such a clock is not available, one option is to generate twice
the desired sampling rate, then use the KAD2708C's divide-by2 to generate a 50%-duty-cycle clock. This frequency divider
uses the rising edge of the clock, so 50% clock duty cycle is
assured. Table 2 describes the CLKDIV connection.
TABLE 2. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
AVDD
1
CLKDIV is internally pulled low, so a pull-up resistor or logic
driver must be connected for undivided clock.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter and maximum SNR is shown in Equation 1
and is illustrated in Figure 27.
1
SNR = 20 log 10 --------------------
2f t
IN J
(EQ. 1)
Where tJ is the RMS uncertainty in the sampling instant.
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality, achievable
SNR is limited by internal factors such as differential
nonlinearity, aperture jitter and thermal noise.
Page 13 of 17
KAD2708C
Any internal aperture jitter combines with the input clock jitter,
in a root-sum-square fashion since they are not statistically
correlated, and this determines the total jitter in the system.
The total jitter, combined with other noise sources, then
determines the achievable SNR.
10 0
95
tj=0.1 ps
90
14 Bits
SN R - dB
85
80
tj=1 ps
12 Bits
75
Digital Outputs
70
tj=10 p s
65
60
Data is output on a parallel bus with LVDS-compatible drivers.
1 0 Bits
tj=1 00 ps
The output format (Binary or Two’s Complement) is selected
via the 2SC pin as shown in Table 3.
55
50
1
10
1 00
1 00 0
In put Fr equen cy - MH z
TABLE 3. 2SC PIN SETTINGS
FIGURE 27. SNR vs CLOCK JITTER
2SC PIN
MODE
AVSS
Two’s Complement
AVDD
Binary
Equivalent Circuits
AVDD2
AVDD3
INP
2pF
F1
Csamp
0.3pF
F2
To
Charge
Pipeline
AVDD2
To Clock
Generation
CLKP
AVDD3
INN
2pF
1
F
Csamp
0.3pF
F2
To
Charge
Pipeline
AVDD2
CLKN
FIGURE 28. ANALOG INPUTS
FIGURE 29. CLOCK INPUTS
OVDD
DATA
OVDD
D[9:0]
FIGURE 30. LVCMOS OUTPUT
FN6812 Rev 1.00
April 14, 2011
Page 14 of 17
KAD2708C
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the inputs for the analog
input and clock signals. Locate transformers, drivers and
terminations as close to the chip as possible.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep
ceramic bypass capacitors very close to device pins. Longer
traces will increase inductance, resulting in diminished
dynamic performance and accuracy. Make sure that
connections to ground are direct and low impedance.
Clock Duty Cycle is the ratio of the time the clock wave is at
logic high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any code
width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB,
it is calculated as: ENOB = (SINAD - 1.76)/6.02.
Integral Non-Linearity (INL) is the deviation of each individual
code from a line drawn from negative full-scale (1/2 LSB below
the first code transition) through positive full-scale (1/2 LSB above
the last code transition). The deviation of any given code from this
line is measured from the center of that code.
Least Significant Bit (LSB) is the bit that has the smallest
value or weight in a digital word. Its value in terms of input
voltage is VFS/(2N - 1) where N is the resolution in bits.
Missing Codes are output codes that are skipped and will
never appear at the ADC output. These codes cannot be
reached with any input value.
LVCMOS Outputs
Most Significant Bit (MSB) is the bit that has the largest value
or weight. Its value in terms of input voltage is VFS/2.
Output traces and connections must be designed for 50
characteristic impedance. Avoid crossing ground and
power-plane breaks with signal traces.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the corresponding data.
Unused Inputs
Power Supply Rejection Ratio (PSRR) is the ratio of a
change in power supply voltage to the input voltage necessary
to negate the resultant change in output code.
The RST and 2SC inputs are internally pulled up, and can be
left open-circuit if not used.
CLKDIV is internally pulled low, which divides the input clock
by two.
VREFSEL is internally pulled up. It must be held low for internal
reference, but can be left open for external reference.
Definitions
Analog Input Bandwidth is the analog input frequency at
which the spectral output power at the fundamental frequency
(as determined by FFT analysis) is reduced by 3dB from its
full-scale low-frequency value. This is also referred to as Full
Power Bandwidth.
Aperture Delay or Sampling Delay is the time required after
the rise of the clock input for the sampling switch to open, at
which time the signal is held for conversion.
Aperture Jitter is the RMS variation in aperture delay for a set
of samples.
FN6812 Rev 1.00
April 14, 2011
Signal to Noise-and-Distortion (SINAD) is the ratio of the
RMS signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Signal-to-Noise Ratio (SNR) (without Harmonics) is the ratio
of the RMS signal amplitude to the RMS sum of all other
spectral components below one-half the sampling frequency,
excluding harmonics and DC.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the
RMS signal amplitude to the RMS value of the peak spurious
spectral component. The peak spurious spectral component
may or may not be a harmonic.
Two-Tone SFDR is the ratio of the RMS value of either input
tone to the RMS value of the peak spurious component. The
peak spurious component may or may not be an IMD product.
Page 15 of 17
KAD2708C
© Copyright Intersil Americas LLC 2008-2011. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6812 Rev 1.00
April 14, 2011
Page 16 of 17
KAD2708C
Package Outline Drawing
L68.10x10B
68 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/08
PIN 1
INDEX AREA
6
10.00
A
4X 8.00
B
52
PIN 1
INDEX AREA
6
68
51
1
35
17
64X 0.50
Exp. DAP
7.70 Sq.
10.00
0.15 (4X)
34
18
68X 0.55
TOP VIEW
68X 0.25
4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 Max
8.00 Sq
0.10 C
C
0.08 C
SEATING PLANE
64X 0.50
SIDE VIEW
68X 0.25
9.65 Sq
C
7.70 Sq
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
68X 0.75
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6812 Rev 1.00
April 14, 2011
Page 17 of 17
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