DATASHEET
KAD5610P
FN6810
Rev 3.00
May 31, 2016
Dual 10-Bit, 250/210/170/125MSPS A/D Converter
The KAD5610P is a family of low-power, high performance,
dual-channel 10-bit, analog-to-digital converters. Designed
with Intersil’s proprietary FemtoCharge™ technology on a
standard CMOS process, the family supports sampling rates of
up to 250MSPS. The KAD5610P-25 is the fastest member of
this pin-compatible family, which also features sample rates of
210MSPS (KAD5610P-21), 170MSPS (KAD5610P-17) and
125MSPS (KAD5610P-12).
Features
A Serial Peripheral Interface (SPI) port allows for extensive
configurability, as well as fine control of gain, skew and offset
matching between the two converter cores.
• Clock phase selection
• Programmable gain, offset and skew control
• 1.3GHz analog input bandwidth
• 60fs clock jitter
• Over-range indicator
• Selectable clock divider: ÷1, ÷2 or ÷4
• Nap and sleep modes
• Two’s complement, gray code or binary data format
Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5610P is available in a 72 Ld QFN package
with an exposed paddle. Performance is specified over the full
industrial temperature range (-40°C to +85°C).
• DDR LVDS compatible or LVCMOS outputs
• Programmable built-in test patterns
• Single-supply 1.8V operation
Key Specifications
• Pb-free (RoHs compliant)
• SNR = 60.7dBFS for fIN = 105MHz (-1dBFS)
Applications
• SFDR = 86.1dBc for fIN = 105MHz (-1dBFS)
• Power amplifier linearization
• Power consumption
- 411mW at 250MSPS
- 327mW at 125MSPS
• Radar and satellite antenna array processing
• Broadband communications
• High-performance data acquisition
• Communications test equipment
CLKP
OVDD
CLKDIV
AVDD
• WiMAX and microwave receivers
CLKOUTP
CLOCK
GENERATION
CLKN
AINP
CLKOUTN
10-BIT
250MSPS
ADC
SHA
AINN
VREF
VCM
BINP
D[9:0]P
D[9:0]N
ORP
DIGITAL
ERROR
CORRECTION
ORN
OUTFMT
10-BIT
250MSPS
ADC
SHA
BINN
OUTMODE
VREF
OVSS
SPI
CONTROL
CSB
SCLK
SDIO
SDO
+
–
RESETN
AVSS
NAPSLP
1.25V
FIGURE 1. BLOCK DIAGRAM
FN6810 Rev 3.00
May 31, 2016
Page 1 of 30
KAD5610P
Table of Contents
Key Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User-Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Range Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
16
16
17
17
18
18
18
18
18
19
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
22
22
22
23
24
25
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
27
27
27
27
27
28
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FN6810 Rev 3.00
May 31, 2016
Page 2 of 30
KAD5610P
Ordering Information
PART NUMBER
(Notes 1, 2)
PART MARKING
SPEED
(MSPS)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG. DWG. #
KAD5610P-25Q72
KAD5610P-25 Q72EP-I
250
-40 to +85
72 Ld QFN
L72.10x10D
KAD5610P-21Q72
KAD5610P-21 Q72EP-I
210
-40 to +85
72 Ld QFN
L72.10x10D
KAD5610P-17Q72
KAD5610P-17 Q72EP-I
170
-40 to +85
72 Ld QFN
L72.10x10D
KAD5610P-12Q72
KAD5610P-12 Q72EP-I
125
-40 to +85
72 Ld QFN
L72.10x10D
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and
NiPdAu-plate--e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see product information page for KAD5610P-25, KAD5610P-21, KAD5610P-17, KAD5610P-12. For more
information on MSL, please see tech brief TB363.
TABLE 1. PIN-COMPATIBLE FAMILY
RESOLUTION
SPEED
(MSPS)
KAD5612P-25
12
250
KAD5612P-21
12
210
KAD5612P-17
12
170
KAD5612P-12
12
125
KAD5610P-25
10
250
KAD5610P-21
10
210
KAD5610P-17
10
170
KAD5610P-12
10
125
MODEL
FN6810 Rev 3.00
May 31, 2016
Page 3 of 30
KAD5610P
Absolute Maximum Ratings
Thermal Information
JA (°C/W)
3. Thermal Resistance (Typical), Note 4)
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
72 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = maximum conversion rate (per speed grade).
PARAMETER
SYMBOL
TEST
CONDITIONS
KAD5610P-25
(Note 5)
KAD5610P-21
(Note 5)
KAD5610P-17
(Note 5)
KAD5610P-12
(Note 5)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
1.40
1.47
1.54
1.40
1.47
1.54
1.40
1.47
1.54
1.40
1.47
1.54
VP-P
DC SPECIFICATIONS
Analog Input
Full-Scale Analog
Input Range
VFS
Differential
Input Resistance
RIN
Differential
1000
1000
1000
1000
Ω
Input Capacitance
CIN
Differential
1.8
1.8
1.8
1.8
pF
Full-Scale Range
Temperature Drift
AVTC
Full
Temperature
90
90
90
90
ppm/°C
Input Offset Voltage
VOS
Gain Error
EG
Common-Mode
Output Voltage
-10
±2
10
-10
±2
VCM
435
535
±2
10
-10
±0.6
635
435
535
±2
10
-10
±0.6
635
435
535
±2
10
±0.6
635
435
535
mV
%
635
mV
Clock Inputs
Inputs
Common-Mode
Voltage
0.9
0.9
0.9
0.9
V
CLKP, CLKN Input
Swing
1.8
1.8
1.8
1.8
V
Power Requirements
1.8V Analog Supply
Voltage
AVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Digital Supply
Voltage
OVDD
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
1.7
1.8
1.9
V
1.8V Analog Supply
Current
IAVDD
170
187
158
175
142
162
128
145
mA
1.8V Digital Supply
Current (Note 6)
IOVDD
3mA LVDS
58
65
57
63
55
62
53
60
mA
Power Supply
Rejection Ratio
PSRR
30MHz,
200mVP-P
signal on AVDD
-36
FN6810 Rev 3.00
May 31, 2016
-36
-36
-36
dB
Page 4 of 30
KAD5610P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = maximum conversion rate (per speed grade). (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
KAD5610P-25
(Note 5)
MIN
TYP
MAX
411
KAD5610P-21
(Note 5)
MIN
TYP
MAX
438
387
KAD5610P-17
(Note 5)
MIN
TYP
MAX
411
357
KAD5610P-12
(Note 5)
MIN
TYP
MAX
UNIT
387
327
351
mW
Total Power Dissipation
Normal Mode
PD
Nap Mode
PD
Sleep Mode
PD
3mA LVDS
148
170.2
142
164.2
136
158.2
129
150.2
mW
CSB at logic
high
2
6
2
6
2
6
2
6
mW
Nap Mode Wakeup
Time (Note 7)
Sample clock
running
1
1
1
1
µs
Sleep Mode Wakeup
Time (Note 7)
Sample clock
running
1
1
1
1
ms
AC SPECIFICATIONS
Differential
Nonlinearity
DNL
-0.5
±0.12
0.5
-0.5
±0.17
0.5
-0.5
±0.17
0.5
-0.5
±0.17
0.5
LSB
Integral Nonlinearity
INL
-0.75 ±0.20
0.75
-0.75 ±0.30
0.75
-0.75 ±0.30
0.75
-0.75 ±0.30
0.75
LSB
40
MSPS
Minimum
Conversion Rate
(Note 8)
fS MIN
Maximum
Conversion Rate
fS MAX
Signal-to-Noise
Ratio
SNR
Signal-to-Noise and
Distortion
Effective Number of
Bits
FN6810 Rev 3.00
May 31, 2016
40
250
fIN = 10MHz
fIN = 105MHz
SINAD
210
60.8
59.5
60.7
40
170
60.8
60.0
60.9
125
61.0
60.2
61.0
60.2
MSPS
61.0
dBFS
61.0
dBFS
fIN = 190MHz
60.6
60.8
60.9
60.9
dBFS
fIN = 364MHz
60.5
60.6
60.7
60.7
dBFS
fIN = 695MHz
59.9
60.0
60.1
60.0
dBFS
fIN = 995MHz
59.1
59.2
59.3
59.2
dBFS
fIN = 10MHz
fIN = 105MHz
ENOB
40
60.7
59.3
60.7
60.8
59.9
60.9
60.9
60.0
60.9
60.0
61.0
dBFS
61.0
dBFS
60.9
dBFS
fIN = 190MHz
60.5
60.8
fIN = 364MHz
60.4
60.5
60.6
60.4
dBFS
fIN = 695MHz
56.5
57.3
56.9
56.6
dBFS
fIN = 995MHz
49.8
46.9
47.7
49.1
dBFS
fIN = 10MHz
fIN = 105MHz
9.8
9.5
9.8
60.8
9.8
9.6
9.8
9.8
9.6
9.8
9.6
9.8
Bits
9.8
Bits
fIN = 190MHz
9.8
9.8
9.8
9.8
Bits
fIN = 364MHz
9.7
9.8
9.8
9.7
Bits
fIN = 695MHz
9.1
9.2
9.2
9.1
Bits
fIN = 995MHz
8.0
7.5
7.6
7.9
Bits
Page 5 of 30
KAD5610P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = maximum conversion rate (per speed grade). (Continued)
PARAMETER
TEST
CONDITIONS
SYMBOL
Spurious-Free
Dynamic Range
Intermodulation
Distortion
SFDR
IMD
Channel-to-Channel
Isolation
MIN
TYP
fIN = 10MHz
fIN = 105MHz
KAD5610P-21
(Note 5)
KAD5610P-25
(Note 5)
MAX
MIN
83.0
70.0
86.1
TYP
MAX
KAD5610P-17
(Note 5)
MIN
82.0
70.0
86.6
TYP
MAX
KAD5610P-12
(Note 5)
MIN
78.0
70.0
84.6
70.0
TYP
MAX
UNIT
79.0
dBc
85.8
dBc
fIN = 190MHz
78.0
80.1
81.0
81.2
dBc
fIN = 364MHz
76.2
77.1
77.9
72.1
dBc
fIN = 695MHz
60.8
61.9
61.0
61.1
dBc
fIN = 995MHz
50.2
47.2
47.9
49.4
dBc
fIN = 70MHz
-86.1
-92.1
-94.5
-95.1
dBFS
fIN = 170MHz
-96.9
-87.1
-91.6
-85.7
dBFS
fIN = 10MHz
90
90
90
90
dB
fIN = 124MHz
90
90
90
90
dB
Word Error Rate
WER
10-12
10-12
10-12
10-12
Full Power
Bandwidth
FPBW
1.3
1.3
1.3
1.3
GHz
NOTES:
5. Parameters with MIN and/or MAX limits are 100% production tested at their worst case temperature extreme (+85°C).
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output.
7. See “Nap/Sleep” on page 18 for more detail.
8. The DLL Range setting must be changed for low speed operation. See Table 16 on page 24 for more detail.
Digital Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
1
10
µA
-25
-12
-5
µA
INPUTS
Input Current High (SDIO,RESETN)
IIH
VIN = 1.8V
Input Current Low (SDIO,RESETN)
IIL
VIN = 0V
Input Voltage High (SDIO, RESETN)
VIH
Input Voltage Low (SDIO, RESETN)
VIL
Input Current High (OUTMODE, NAPSLP, CLKDIV, OUTFMT)
(Note 9)
IIH
15
Input Current Low (OUTMODE, NAPSLP, CLKDIV, OUTFMT)
IIL
-40
Input Capacitance
CDI
1.17
V
0.63
V
25
40
µA
25
-15
µA
3
pF
620
mVP-P
LVDS OUTPUTS
Differential Output Voltage
Output Offset Voltage
VT
3mA Mode
VOS
3mA Mode
950
965
980
mV
Output Rise Time
tR
500
ps
Output Fall Time
tF
500
ps
FN6810 Rev 3.00
May 31, 2016
Page 6 of 30
KAD5610P
Digital Specifications (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
OVDD - 0.3
OVDD - 0.1
UNIT
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
V
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
Timing Diagrams
SAMPLE N
SAMPLE N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
tCPD
tCPD
LATENCY = L CYCLES
CLKOUTN
CLKOUTP
LATENCY = L CYCLES
CLKOUT
tDC
D[9:0]P
D[9:0]N
tDC
tPD
tPD
A DATA
N-L
B DATA
N-L
A DATA
N-L + 1
B DATA
N-L + 1
A DATA
N-L + 2
B DATA
N-L + 2
A DATA
N
FIGURE 2. LVDS TIMING DIAGRAM (DDR) (See “Digital Outputs”
on page 18)
FN6810 Rev 3.00
May 31, 2016
D[9:0]
A DATA
N-L
B DATA
N-L
A DATA
N-L + 1
B DATA
N-L + 1
A DATA
N-L + 2
B DATA
N-L + 2
A DATA
N
FIGURE 3. CMOS TIMING DIAGRAM (DDR) (See “Digital Outputs”
on page 18)
Page 7 of 30
KAD5610P
Switching Specifications
PARAMETER
TEST CONDITIONS
SYMBOL
MIN
TYP
MAX
UNIT
ADC
Aperture Delay
tA
375
ps
RMS Aperture Jitter
jA
60
fs
Output Clock to Data Propagation Delay,
LVDS Mode (Note 10)
Output Clock to Data Propagation Delay,
CMOS Mode (Note 10)
Rising Edge
tDC
-260
-50
120
ps
Falling Edge
tDC
-160
10
230
ps
Rising Edge
tDC
-220
-10
200
ps
Falling Edge
tDC
-310
-90
110
ps
Latency (Pipeline Delay)
Overvoltage Recovery
L
7.5
cycles
tOVR
1
cycles
SPI INTERFACE (Notes 11, 12)
SCLK Period
Write Operation
tCLK
16
cycles
(Note 11)
Read Operation
tCLK
66
cycles
SCLK Duty Cycle (tHI/tCLK or tLO/tCLK)
Read or Write
SCLK Duty Cycle (tHI/tCLK or tLO/tCLK)
Read or Write
tS
1
cycles
CSBto SCLK Set-Up Time
Read or Write
tH
3
cycles
CSBafter SCLK Hold Time
Write
tDS
1
cycles
Data Valid to SCLK Set-Up Time
Write
tDH
3
cycles
Data Valid after SCLK Hold Time
Read
Data Valid after SCLK Time
Read
Sleep Mode CSB to SCLKSet-Up Time
(Note 13)
Read or Write in Sleep Mode
25
50
75
16.5
tS
%
cycles
3
cycles
150
µs
NOTES:
9. The Tri-Level Inputs internal switching thresholds are approximately .43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most
applications. Contact Intersil support for more info if needed.
11. SPI Interface timing is directly proportional to tS, the ADC sample period (4ns at 250Msps).
12. The SPI may operate asynchronously with respect to the ADC sample clock.
13. The CSB set-up time increases in sleep mode due to the reduced power state, CSB set-up time in Nap mode is equal to normal mode CSB set-up time
(4ns min).
FN6810 Rev 3.00
May 31, 2016
Page 8 of 30
KAD5610P
Pin Descriptions
PIN #
LVDS [LVCMOS] NAME
1, 6, 19, 24, 71
AVDD
1.8V Analog Supply
2, 3, 4, 5, 17, 18, 28,
29, 30, 31, 32, 33,
34, 35
DNC
Do Not Connect
7, 10-12, 72
AVSS
Analog Ground
8, 9
BINP, BINN
B-Channel Analog Input Positive, Negative
13, 14
AINN, AINP
A-Channel Analog Input Negative, Positive
15
VCM
16
CLKDIV
20, 21
CLKP, CLKN
Clock Input True, Complement
22
OUTMODE
Output Mode (LVDS, LVCMOS)
23
NAPSLP
Power Control (Nap, Sleep modes)
25
RESETN
Power-On Reset (Active Low, See “User-Initiated Reset” on page 16)
26, 45, 55, 65
OVSS
Output Ground
27, 36, 56
OVDD
1.8V Output Supply
37
D0N
[NC]
LVDS Bit 0 (LSB) Output Complement
[NC in LVCMOS]
38
D0P
[D0]
LVDS Bit 0 (LSB) Output True
[LVCMOS Bit 0]
39
D1N
[NC]
LVDS Bit 1 Output Complement
[NC in LVCMOS]
40
D1P
[D1]
LVDS Bit 1 Output True
[LVCMOS Bit 1]
41
D2N
[NC]
LVDS Bit 2 Output Complement
[NC in LVCMOS]
42
D2P
[D2]
LVDS Bit 2 Output True
[LVCMOS Bit 2]
43
D3N
[NC]
LVDS Bit 3 Output Complement
[NC in LVCMOS]
44
D3P
[D3]
LVDS Bit 3 Output True
[LVCMOS Bit 3]
46
RLVDS
47
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
48
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[ LVCMOS CLKOUT]
49
D4N
[NC]
LVDS Bit 4 Output Complement
[NC in LVCMOS]
50
D4P
[D4]
LVDS Bit 4 Output True
[LVCMOS Bit 4]
51
D5N
[NC]
LVDS Bit 5 Output Complement
[NC in LVCMOS]
52
D5P
[D5]
LVDS Bit 5 Output True
[LVCMOS Bit 5]
53
D6N
[NC]
LVDS Bit 6 Output Complement
[NC in LVCMOS]
FN6810 Rev 3.00
May 31, 2016
LVDS [LVCMOS] FUNCTION
Common-Mode Output
Clock Divider Control
LVDS Bias Resistor (connect to OVSS with a 10kΩ, 1% resistor)
Page 9 of 30
KAD5610P
Pin Descriptions (Continued)
PIN #
LVDS [LVCMOS] NAME
LVDS [LVCMOS] FUNCTION
54
D6P
[D6]
LVDS Bit 6 Output True
[LVCMOS Bit 6]
57
D7N
[NC]
LVDS Bit 7 Output Complement
[NC in LVCMOS]
58
D7P
[D7]
LVDS Bit 7 Output True
[LVCMOS Bit 7]
59
D8N
[NC]
LVDS Bit 8 Output Complement
[NC in LVCMOS]
60
D8P
[D8]
LVDS Bit 8 Output True
[LVCMOS Bit 8]
61
D9N
[NC]
LVDS Bit 9 (MSB) Output Complement
[NC in LVCMOS]
62
D9P
[D9]
LVDS Bit 9 (MSB) Output True
[LVCMOS Bit 9]
63
ORN
[NC]
LVDS Over-Range Complement,
[NC in LVCMOS]
64
ORP
[OR]
LVDS Over-Range True
[LVCMOS Over Range]
66
SDO
SPI Serial Data Output (4.7kΩ pull-up to OVDD is required)
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
70
OUTFMT
Exposed Paddle
AVSS
Output Data Format (Two’s Complement, Gray Code, Offset Binary)
Analog Ground
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection).
FN6810 Rev 3.00
May 31, 2016
Page 10 of 30
KAD5610P
Pin Configuration
AVSS
AVDD
OUTFMT
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
D9P
D9N
D8P
D8N
D7P
D7N
OVDD
OVSS
KAD5610P
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD
1
54 D6P
DNC
2
53 D6N
DNC
3
52 D5P
DNC
4
51 D5N
DNC
5
50 D4P
AVDD
6
49 D4N
AVSS
7
48 CLKOUTP
BINP
8
47 CLKOUTN
BINN
9
AVSS
10
45 OVSS
AVSS
11
44 D3P
AVSS
12
43 D3N
AINN
13
42 D2P
AINP
14
41 D2N
VCM
15
40 D1P
CLKDIV
16
39 D1N
DNC
17
DNC
18
FN6810 Rev 3.00
May 31, 2016
46 RLVDS
EXPOSED PADDLE
38 D0P
CONNECT THERMAL PAD TO AVSS
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD
CLKP
CLKN
OUTMODE
NAPSLP
AVDD
RESETN
OVSS
OVDD
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
OVDD
37 D0N
Page 11 of 30
KAD5610P
Typical Performance Curves
All Typical performance characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = maximum conversion rate (per speed grade).
-50
85
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
90
SFDR AT 125MSPS
80
SFDR AT 250MSPS
75
70
SNR AT 125MSPS
65
60
55
SNR AT 250MSPS
50
0M
200M
400M
600M
800M
-55
-65
-70 HD2 AT 250MSPS
-75
HD3 AT125MSPS
-80
-85
HD3 AT 250MSPS
-90
-95
-100
1G
HD2 AT 125MSPS
-60
0M
200M
INPUT FREQUENCY (Hz)
90
SNR AND SFDR
HD2 AND HD3 MAGNITUDE
SFDRFS (dBFS)
80
70
60
SNRFS (dBFS)
50
40
SFDR (dBc)
30
SNR (dBc)
20
10
-60
-50
-40
-30
-20
-10
-10
0
-20
-30
-40
-50
HD2 (dBc)
-60
-70
HD2 (dBFS)
-80
-90
-100
-110
-60
0
HD3 (dBc)
HD3 (dBFS)
-50
-40
-30
-20
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
FIGURE 6. SNR AND SFDR vs AIN
FIGURE 7. HD2 AND HD3 vs AIN
90
-60
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
1G
-10
100
85
SFDR
80
75
70
65
SNR
60
55
800M
FIGURE 5. HD2 AND HD3 vs fIN
FIGURE 4. SNR AND SFDR vs fIN
0
400M
600M
INPUT FREQUENCY (Hz)
40
70
100
130
160
190
SAMPLE RATE (MSPS)
FIGURE 8. SNR AND SFDR vs fSAMPLE
FN6810 Rev 3.00
May 31, 2016
220
250
-70
HD3
-80
-90
HD2
-100
-110
-120
40
70
100
130
160
190
220
250
SAMPLE RATE (MSPS)
FIGURE 9. HD2 AND HD3 vs fSAMPLE
Page 12 of 30
KAD5610P
Typical Performance Curves
450
0.25
400
0.20
350
0.15
0.10
300
DNL (LSBs)
TOTAL POWER (mW)
All Typical performance characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = maximum conversion rate (per speed grade). (Continued)
250
200
150
0.05
0.00
-0.05
-0.10
100
-0.15
50
-0.20
0
40
70
100
130
160
190
SAMPLE RATE (MSPS)
220
-0.25
250
0
FIGURE 10. POWER vs fSAMPLE IN 3mA LVDS MODE
85
SNR (dBFS) AND SFDR (dBc)
90
0.20
0.15
INL (LSBs)
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
0
128
256
384
512
CODE
640
768
896
512
CODE
640
768
896
1024
SFDR
75
70
65
SNR
60
55
50
300
1024
400
500
600
700
800
INPUT COMMON MODE (mV)
FIGURE 13. SNR AND SFDR vs VCM
70000
0
40000
AIN = -1.0dBFS
SNR = 60.7dBFS
SFDR = 82.5dBc
SINAD = 60.7dBFS
-20
10000
AMPLITUDE (dBFS)
NUMBER OF HITS
384
80
FIGURE 12. INTEGRAL NONLINEARITY
80000
50000
20000
90000
60000
-40
-60
-80
-100
30000
0
2050
256
FIGURE 11. DIFFERENTIAL NONLINEARITY
0.25
-0.25
128
2051
2052
2053
2054 2055
CODE
2056
FIGURE 14. NOISE HISTOGRAM
FN6810 Rev 3.00
May 31, 2016
2057
2058
-120
0M
20M
40M
60M
80M
FREQUENCY (Hz)
100M
120M
FIGURE 15. SINGLE-TONE SPECTRUM AT 10MHz
Page 13 of 30
KAD5610P
Typical Performance Curves
All Typical performance characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = maximum conversion rate (per speed grade). (Continued)
0
-20
AMPLITUDE (dBFS)
-20
AMPLITUDE (dBFS)
0
AIN = -1.0dBFS
SNR = 60.7dBFS
SFDR = 85.9dBc
SINAD = 60.7dBFS
-40
-60
-80
-100
-120
AIN = -1.0dBFS
SNR = 60.6dBFS
SFDR = 78.5dBc
SINAD = 60.5dBFS
-40
-60
-80
-100
0M
20M
40M
60M
80M
100M
-120
120M
0M
20M
40M
FIGURE 16. SINGLE-TONE SPECTRUM AT 105MHz
0
-60
-80
-100
120M
-40
-60
-80
-100
0M
20M
40M
60M
80M
100M
-120
120M
0M
20M
FREQUENCY (Hz)
0
0
IMD = -86.1dBFS
100M
120M
IMD = -96.9dBFS
-20
AMPLITUDE (dBFS)
-20
-40
-60
-80
-40
-60
-80
-100
-100
-120
40M
60M
80M
FREQUENCY (Hz)
FIGURE 19. SINGLE-TONE SPECTRUM AT 995MHz
FIGURE 18. SINGLE-TONE SPECTRUM AT 495MHz
AMPLITUDE (dBFS)
100M
AIN = -1.0dBFS
SNR = 58.9dBFS
SFDR = 49.8dBc
SINAD = 49.5dBFS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
-40
-120
80M
FIGURE 17. SINGLE-TONE SPECTRUM AT 190MHz
AIN = -1.0dBFS
SNR = 60.2dBFS
SFDR = 68.9dBc
SINAD = 59.4dBFS
-20
60M
FREQUENCY (Hz)
FREQUENCY (Hz)
0M
20M
40M
60M
80M
FREQUENCY (Hz)
100M
FIGURE 20. TWO-TONE SPECTRUM AT 70MHz
FN6810 Rev 3.00
May 31, 2016
120M
-120
0M
20M
40M
60M
80M
FREQUENCY (Hz)
100M
120M
FIGURE 21. TWO-TONE SPECTRUM AT 170MHz
Page 14 of 30
KAD5610P
Theory of Operation
voltages are above a threshold. The following conditions must be
adhered to for the power-on calibration to execute successfully:
Functional Description
The KAD5610P is based upon a 10-bit, 250MSPS A/D converter
core that utilizes a pipelined successive approximation
architecture (Figure 22). The input voltage is captured by a
Sample-Hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. The converter pipeline
requires six samples to produce a result. Digital error correction is
also applied, resulting in a total latency of seven and one half clock
cycles. This is evident to the user as a latency between the start of
a conversion and the data being available on the digital outputs.
The device contains two A/D converter cores with carefully
matched transfer characteristics. At start-up, each core performs
a self-calibration to minimize gain and offset errors. The reset pin
(RESETN) is initially set high at power-up and will remain in that
state until the calibration is complete. The clock frequency
should remain fixed during this time, and no SPI
communications should be attempted. Recalibration can be
initiated via the SPI port at any time after the initial
self-calibration.
Power-On Calibration
The ADC performs a self-calibration at start-up. An internal
Power-On-Reset (POR) circuit detects the supply voltage ramps
and initiates the calibration when the analog and digital supply
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins (especially 3, 4 and 18) must not be pulled up or
down
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
The SDO pin requires an external 4.7kΩ pull-up to OVDD. If the
SDO pin is pulled low externally during power-up, calibration will
not be executed properly.
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
required, the RESETN pin should be connected to an open-drain
driver with a drive strength of less than 0.5mA.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 23. The Over-Range (OR) output is
set high once RESETN is pulled low, and remains in that state
until calibration is complete. The OR output returns to normal
operation at that time, so it is important that the analog input be
within the converter’s full-scale range to observe the transition. If
the input is in an over-range condition the OR pin will stay high,
and it will not be possible to detect the end of the calibration
cycle.
CLOCK
GENERATION
INP
SHA
INN
1.25V
+
–
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 22. ADC CORE BLOCK DIAGRAM
FN6810 Rev 3.00
May 31, 2016
Page 15 of 30
KAD5610P
CLKN
CLKP
CALIBRATION
TIME
3
SNR CHANGE (dBfs)
While RESETN is low, the output clock (CLKOUTP/CLKOUTN) is
set low. Normal operation of the output clock resumes at the
next input clock edge (CLKP/CLKN) after RESETN is deasserted.
At 250MSPS the nominal calibration time is 200ms, while the
maximum calibration time is 550ms.
CAL DONE AT
+85°C
2
1
0
-1
-2
-4
-40
CALIBRATION
BEGINS
CAL DONE AT
+25°C
CAL DONE AT
-40°C
-3
RESETN
-15
10
35
60
85
TEMPERATURE (°C)
ORP
FIGURE 24. SNR PERFORMANCE vs TEMPERATURE
CALIBRATION
COMPLETE
CLKOUTP
FIGURE 23. CALIBRATION TIMING
User-Initiated Reset
Recalibration of the ADC can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength of less than 0.5mA is
recommended, RESETN has an internal high impedance pull-up
to OVDD. As is the case during power-on reset, the SDO, RESETN
and DNC pins must be in the proper state for the calibration to
successfully execute.
The performance of the KAD5610P changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the ADC under the environmental conditions at
which it will operate.
A supply voltage variation of less than 100mV will generally
result in an SNR change of less than 0.1dBFS and SFDR change
of less than 3dBc.
In situations where the sample rate is not constant, best results
will be obtained if the device is calibrated at the highest sample
rate. Reducing the sample rate by less than 75MSPS will typically
result in an SNR change of less than 0.1dBFS and an SFDR
change of less than 3dBc.
Figures 24 and 25 show the effect of temperature on SNR and
SFDR performance with calibration performed at -40°C, +25°C,
and +85°C. Each plot shows the variation of SNR/SFDR across
temperature after a single calibration at -40°C, +25°C and
+85°C. Best performance is typically achieved by a user-initiated
calibration at the operating conditions, as stated earlier.
However, it can be seen that performance drift with temperature
is not a very strong function of the temperature at which the
calibration is performed. Full-rated performance will be achieved
after power-up calibration regardless of the operating conditions.
FN6810 Rev 3.00
May 31, 2016
SFDR CHANGE (dBc)
15
CAL DONE AT
-40°C
10
5
0
-5
CAL DONE AT
+85°C
-10
-15
-40
-15
CAL DONE AT
+25°C
10
35
TEMPERATURE (°C)
60
85
FIGURE 25. SFDR PERFORMANCE vs TEMPERATURE
Analog Input
Each ADC core contains a fully differential input (AINP/AINN,
BINP/BINN) to the Sample and Hold Amplifier (SHA). The ideal
full-scale input voltage is 1.45V, centered at the VCM voltage of
0.535V as shown in Figure 26.
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs as shown in Figures 27 through
29.
1.8
1.4
1.0
INN
0.725V
INP
VCM
0.6
0.535V
0.2
FIGURE 26. ANALOG INPUT RANGE
Page 16 of 30
KAD5610P
An RF transformer will give the best noise and distortion
performance for wideband and/or high Intermediate Frequency
(IF) inputs. Two different transformer input schemes are shown in
Figures 27 and 28.
ADT1-1WT
ADT1-1WT
1000pF
KAD5610P
VCM
0.1µF
Clock Input
The clock input circuit is a differential pair (see Figure 43).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels.
The recommended drive circuit is shown in Figure 30. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
200pF
TC4-1W
FIGURE 27. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
1000pF
200pF
ADTL1-12
ADTL1-12
1000pF
CLKN
KAD5610P
FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the KAD5610P is 1000Ω.
The SHA design uses a switched capacitor input stage (see
Figure 42), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input, which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 1:1 transformer
and low shunt resistance are recommended for optimal
performance.
348
25
CM
0.22µF
49.9
200pF
VCM
100
217
KAD5610P
VCM
100
25
69.8
348
0.1µF
FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT
A differential amplifier, as shown in Figure 29, can be used in
applications that require DC coupling. In this configuration the
amplifier will typically dominate the achievable SNR and
distortion performance.
FN6810 Rev 3.00
May 31, 2016
200
0.1µF
1000pF
69.8
CLKP
FIGURE 30. RECOMMENDED CLOCK DRIVE
A selectable 2x frequency divider is provided in series with the
clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate. This allows
the use of the Phase Slip feature, which enables synchronization
of multiple ADCs.
TABLE 2. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 21.
A Delay-Locked Loop (DLL) generates internal clock signals for
various stages within the charge pipeline. If the frequency of the
input clock changes, the DLL may take up to 52µs to regain lock
at 250MSPS. The lock time is inversely proportional to the
sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (tJ) and SNR is shown in Equation 1 and is
illustrated in Figure 31.
1
SNR = 20 log 10 --------------------
2f t
(EQ. 1)
IN J
Page 17 of 30
KAD5610P
The output mode can also be controlled through the SPI port,
which overrides the OUTMODE pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 21.
100
95
tJ = 0.1ps
90
14 BITS
SNR (dB)
85
80
tJ = 1ps
75
12 BITS
70
tJ = 10ps
65
60
50
1M
10M
100M
INPUT FREQUENCY (Hz)
1G
FIGURE 31. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure 2 on page 7. The internal
aperture jitter combines with the input clock jitter in a
root-sum-square fashion, since they are not statistically
correlated, and this determines the total jitter in the system. The
total jitter, combined with other noise sources, then determines
the achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides the
reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional to the
reference voltage. The nominal value of the voltage reference is
1.25V.
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible or
CMOS modes. In either case, the data is presented in Double Data
Rate (DDR) format with the A and B channel data available on
alternating clock edges. When CLKOUT is low Channel A data is
output, while on the high phase Channel B data is presented.
Figures 2 and 3 show the timing relationships for LVDS and CMOS
modes, respectively.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA or a power-saving 2mA. The lower current setting
can be used in designs where the receiver is in close physical
proximity to the ADC. The applicability of this setting is
dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
The output mode and LVDS drive current are selected via the
OUTMODE pin as shown in Table 3.
TABLE 3. OUTMODE PIN SETTINGS
OUTMODE PIN
MODE
AVSS
LVCMOS
Float
LVDS, 3mA
AVDD
LVDS, 2mA
FN6810 Rev 3.00
May 31, 2016
Over-Range Indicator
The Over-Range (OR) bit is asserted when the output code
reaches positive full-scale (e.g. 0xFFF in offset binary mode). The
output code does not wrap around during an over-range
condition. The OR bit is updated at the sample rate.
10 BITS
tJ = 100ps
55
An external resistor creates the bias for the LVDS drivers. A 10kΩ,
1% resistor must be connected from the RLVDS pin to OVSS.
Power Dissipation
The power dissipated by the KAD5610P is primarily dependent
on the sample rate and the output modes: LVDS vs CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock frequency in
CMOS mode.
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the ADC is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to less than 170.2mW and recovers to normal
operation in approximately 1µs. Sleep mode reduces power
dissipation to less than 6mW but requires approximately 1ms to
recover from a sleep command.
Wake-up time from sleep mode is dependent on the state of
CSB; in a typical application CSB would be held high during sleep,
requiring a user to wait 150µs maximum after CSB is asserted
(brought low) prior to writing ‘001x’ to SPI register 25. The device
would be fully powered up, in normal mode 1ms after this
command is written.
Wake-up from Sleep Mode Sequence (CSB high)
• Pull CSB Low
• Wait 150µs
• Write ‘001x’ to Register 25
• Wait 1ms until ADC fully powered on
In an application where CSB was kept low in sleep mode, the
150µs CSB set-up time is not required as the SPI registers are
powered on when CSB is low, the chip power dissipation increases
by ~ 15mW in this case. The 1ms wake-up time after the write of a
‘001x’ to register 25 still applies. It is generally recommended to
keep CSB high in sleep mode to avoid any unintentional SPI
activity on the ADC.
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 250MSPS.
Page 18 of 30
KAD5610P
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 4.
TABLE 4. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 33.
GRAY CODE
9
8
7
••••
1
0
••••
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 21. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin.
••••
Data Format
Output data can be presented in three formats: two’s
complement, Gray code and offset binary. The data format is
selected via the OUTFMT pin as shown in Table 5.
TABLE 5. OUTFMT PIN SETTINGS
BINARY
OUTFMT PIN
MODE
AVSS
Offset Binary
Float
Two’s Complement
AVDD
Gray Code
9
8
7
••••
1
0
FIGURE 33. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats is
shown in Table 6.
TABLE 6. INPUT VOLTAGE TO OUTPUT CODE MAPPING
The data format can also be controlled through the SPI port,
which overrides the OUTFMT pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 21.
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 32 shows this
operation.
BINARY
9
8
7
••••
1
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full-Scale
000 00 000 00
100 00 000 00
000 00 000 00
–Full-Scale
+ 1 LSB
000 00 000 01
100 00 000 01
000 00 000 01
Mid–Scale
100 00 000 00
000 00 000 00
110 00 000 00
+Full-Scale
– 1 LSB
111 11 111 10
011 11 111 10
100 00 000 01
+Full-Scale
111 11 111 11
011 11 111 11
100 00 000 00
0
••••
GRAY CODE
9
8
7
••••
1
0
FIGURE 32. BINARY TO GRAY CODE CONVERSION
FN6810 Rev 3.00
May 31, 2016
Page 19 of 30
KAD5610P
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A1
A10
A0
D7
D6
D5
D4
D3
D2
D1D
0
FIGURE 34. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D1
D0
D2
D3
D4
D5
D6
D7
FIGURE 35. LSB-FIRST ADDRESSING
tDSW
CSB
tDHW
tS
tCLK
tHI
tH
tLO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
SPI WRITE
FIGURE 36. ISPI WRITE
tDSW
CSB
tDHW
tS
tCLK
tHI
tH
tDHR
tDVR
tLO
SCLK
READING DATA (3-WIRE MODE)
WRITING A READ COMMAND
SDIO
R/W
W1
W0
A12
A11
A10
A9
A2
A1
A0
D7
SDO
D6
D3
D2
D1 D0
(4-WIRE MODE)
D7
D3
D2
D1 D0
SPI READ
FIGURE 37. SPI READ
FN6810 Rev 3.00
May 31, 2016
Page 20 of 30
KAD5610P
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 38. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 39. N-BYTE TRANSFER
Serial Peripheral Interface
A Serial Peripheral Interface (SPI) bus is used to facilitate
configuration of the device and to optimize performance. The SPI
bus consists of Chip Select (CSB), Serial Clock (SCLK) Serial Data
Input (SDI), and Serial Data Input/Output (SDIO). The maximum
SCLK rate is equal to the ADC sample rate (fSAMPLE) divided by
16 for write operations and fSAMPLE divided by 66 for reads. At
fSAMPLE = 250MHz, maximum SCLK is 15.63MHz for writing and
3.79MHz for read operations. There is no minimum SCLK rate.
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional
parameters. Many registers in the available address space (0x00
to 0xFF) are not defined in this document. Additionally, within a
defined register there may be certain bits or bit combinations
that are reserved. Undefined registers and undefined values
within defined registers are reserved and should not be selected.
Setting any reserved register or value may produce
indeterminate results.
SPI Physical Interface
The Serial Clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the Serial Data
Input/Output (SDIO) pin in 3-wire mode. The state of the SDIO pin
is set automatically in the communication protocol (described in
the following). A dedicated Serial Data Output (SDO) pin can be
activated by setting 0x00[7] high to allow operation in 4-wire
mode.
The SPI port operates in a half duplex master/slave
configuration, with the KAD5610P functioning as a slave.
Multiple slave devices can interface to a single master in 3-wire
mode only, since the SDO output of an unaddressed device is
asserted in 4-wire mode.
concurrently, but only one slave device can be read from at a
given time (again, only in 3-wire mode). If multiple slave devices
are selected for reading at the same time, the results will be
indeterminate.
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a HIGH to LOW
transition on CSB determines the beginning of the two-byte
instruction/address command, SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 34 and 35 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
MSB-first mode the address is incremented for multi-byte
transfers, while in LSB-first mode it is decremented.
In the default mode the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 7). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 36,
and timing values are given in “Switching Specifications” on
page 8.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
ADC (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
The Chip-Select Bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
FN6810 Rev 3.00
May 31, 2016
Page 21 of 30
KAD5610P
TABLE 7. BYTE TRANSFER SELECTION
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
10
3
11
4 or more
Figures 37 and 39 illustrate the timing relationships for 2-byte
and N-byte transfers, respectively. The operation for a 3-byte
transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0x00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various microcontrollers.
Bit 7 SDO Active
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
Bit 5 Soft Reset
Indexed Device Configuration/Control
ADDRESS 0x10: DEVICE_INDEX_A
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil ADC products.
Certain configuration commands (identified as Indexed in the SPI
map) can be executed on a per-converter basis. This register
determines which converter is being addressed for an Indexed
command. It is important to note that only a single converter can
be addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed. Error code ‘AD’ is returned if any indexed register is
read from without properly setting device_index_A.
ADDRESS 0x20: OFFSET_COARSE
ADDRESS 0x21: OFFSET_FINE
The input offset of each ADC core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 8.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
TABLE 8. OFFSET ADJUSTMENTS
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0x02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. In
3-wire SPI mode the burst is ended by pulling the CSB pin high. If
the device is operated in 2-wire mode the CSB pin is not
available. In that case, setting the burst_end address determines
the end of the transfer. During a write operation, the user must
be cautious to transmit the correct number of bytes based on the
starting and ending addresses.
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
Device Information
ADDRESS 0x08: CHIP_ID
ADDRESS 0x09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
FN6810 Rev 3.00
May 31, 2016
PARAMETER
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
Steps
255
255
–Full-Scale (0x00)
-133 LSB (-47mV)
-5 LSB (-1.75mV)
Mid–Scale (0x80)
0.0 LSB (0.0mV)
0.0LSB
+Full-Scale (0xFF)
+133 LSB (+47mV)
+5 LSB (+1.75mV)
Nominal Step Size
1.04 LSB (0.37mV)
0.04LSB (0.014mV)
ADDRESS 0x22: GAIN_COARSE
ADDRESS 0x23: GAIN_MEDIUM
ADDRESS 0x24: GAIN_FINE
Gain of the ADC core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’ -4.2% and ‘1100’ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using
the registers at 23h and 24h.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
Page 22 of 30
KAD5610P
TABLE 9. COARSE GAIN ADJUSTMENT
TABLE 12. DIFFERENTIAL SKEW ADJUSTMENT
0x22[3:0]
NOMINAL COARSE GAIN ADJUST
(%)
PARAMETER
0X70[7:0]
DIFFERENTIAL SKEW
Bit3
+2.8
Steps
256
Bit2
+1.4
–Full Scale (0x00)
-6.5ps
Bit1
-2.8
Mid–Scale (0x80)
0.0ps
Bit0
-1.4
+Full Scale (0xFF)
+6.5ps
Nominal Step Size
51fs
TABLE 10. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
256
–Full-Scale (0x00)
-2%
-0.20%
Mid-Scale (0x80)
0.00%
0.00%
+Full-Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
ADDRESS 0x71: PHASE_SLIP
When using the clock divider, it’s not possible to determine the
synchronization of the incoming and divided clock phases. This is
particularly important when multiple ADCs are used in a
time-interleaved system. The phase slip feature allows the rising
edge of the divided clock to be advanced by one input clock cycle
when in CLK/4 mode, as shown in Figure 40. Execution of a
phase_slip command is accomplished by first writing a ‘0’ to Bit 0 at
address 71h followed by writing a ‘1’ to Bit 0 at address 71h (32
SCLK cycles).
CLK = CLKP-CLKN
ADDRESS 0x25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to “Nap/Sleep” on page 18). This functionality
can be overridden and controlled through the SPI. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin. This register is not changed by
a soft reset.
TABLE 11. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER-DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
Global Device Configuration/Control
ADDRESS 0x70: SKEW_DIFF
The value in the skew_diff register adjusts the timing skew
between the two ADCs cores. The nominal range and resolution
of this adjustment are given in Table 12. The default value of this
register after power-up is 00h.
FN6810 Rev 3.00
May 31, 2016
CLK
1.00ns
CLK ÷
4.00ns
CLK ÷
SLIP ONCE
CLK
SLIP TWICE
FIGURE 40. PHASE SLIP: CLK ÷ 4 MODE, fCLOCK = 1000MHz
ADDRESS 0x72: CLOCK_DIVIDE
The KAD5610P has a selectable clock divider that can be set to
divide by four, two or one (no division). By default, the tri-level
CLKDIV pin selects the divisor (refer to “Clock Input” on page 17).
This functionality can be overridden and controlled through the
SPI, as shown in Table 13. This register is not changed by a soft
reset.
TABLE 13. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
Page 23 of 30
KAD5610P
ADDRESS 0x73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The KAD5610P can
present output data in two physical formats: LVDS or LVCMOS.
Additionally, the drive strength in LVDS mode can be set high
(3mA) or low (2mA). By default, the tri-level OUTMODE pin selects
the mode and drive level (refer to “Digital Outputs” on page 18).
This functionality can be overridden and controlled through the
SPI, as shown in Table 14.
Data can be coded in three possible formats: two’s complement,
Gray code or offset binary. By default, the tri-level OUTFMT pin
selects the data format (refer to “Data Format” on page 19). This
functionality can be overridden and controlled through the SPI,
as shown in Table 15.
This register is not changed by a soft reset.
TABLE 14. OUTPUT MODE CONTROL
VALUE
0x93[7:5]
OUTPUT MODE
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
TABLE 15. OUTPUT FORMAT CONTROL
VALUE
0x93[2:0]
OUTPUT FORMAT
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
ADDRESS 0x74: OUTPUT_MODE_B
ADDRESS 0x75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or slow.
Internal clock signals are generated by a Delay-Locked Loop
(DLL), which has a finite operating range. Table 16 shows the
allowable sample rate ranges for the slow and fast settings.
TABLE 16. DLL RANGES
DLL RANGE
MIN
MAX
UNIT
Slow
40
100
MSPS
Fast
80
fS MAX
MSPS
The output_mode_B and config_status registers are used in
conjunction to select the frequency range of the DLL clock
generator. The method of setting these options is different from
the other registers.
READ
OUTPUT_MODE_B
0x74
READ
CONFIG_STATUS
0x75
WRITE TO
0x74
DESIRED
VALUE
FIGURE 41. SETTING OUTPUT_MODE_B REGISTER
The procedure for setting output_mode_B is shown in Figure 41.
Read the contents of output_mode_B and config_status and XOR
them. Then XOR this result with the desired value for
output_mode_B and write that XOR result to the register.
Device Test
The KAD5610 can produce preset or user defined patterns on the
digital outputs to facilitate in-situ testing. A static word can be
placed on the output bus, or two different words can alternate. In
the alternate mode, the values defined as Word 1 and Word 2 (as
shown in Table 17) are set on the output bus on alternating clock
phases. The test mode is enabled asynchronously to the sample
clock, therefore several sample clock cycles may elapse before
the data is present on the output bus.
ADDRESS 0xC0: TEST_IO
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
The four LSBs in this register (Output Test Mode) determine the
test pattern in combination with registers 0xC2 through 0xC5.
Refer to Table “SPI Memory Map” on page 25.
TABLE 17. OUTPUT TEST MODES
VALUE
0xC0[3:0]
OUTPUT TEST MODE
0000
Off
WORD 1
WORD 2
0001
Midscale
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
Checkerboard
0xAAAA
0x5555
0101
Reserved
N/A
N/A
0110
Reserved
N/A
N/A
0111
One/Zero
0xFFFF
0x0000
1000
User Pattern
user_patt1
user_patt2
ADDRESS 0xC2: USER_PATT1_LSB
ADDRESS 0xC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0xC4: USER_PATT2_LSB
ADDRESS 0xC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
FN6810 Rev 3.00
May 31, 2016
Page 24 of 30
KAD5610P
SPI Memory Map
INDEXED DEVICE CONFIG/CONTROL
INFO
SPI CONFIG
TABLE 18. SPI MEMORY MAP
ADDR
(HEX)
PARAMETER
NAME
BIT 7
(MSB)
BIT 6
BIT 5
00
port_config
SDO
Active
LSB
First
Soft
Reset
01
Reserved
Reserved
02
burst_end
Burst end address [7:0]
03-07
Reserved
Reserved
08
chip_id
09
chip_version
10
device_index_A
11-1F
Reserved
Reserved
20
offset_coarse
21
offset_fine
22
gain_coarse
23
gain_medium
24
gain_fine
25
modes
26-5F
Reserved
Reserved
60-6F
Reserved
Reserved
70
skew_diff
Differential Skew
71
phase_slip
GLOBAL DEVICECONFIG/CONTROL
72
BIT 2
BIT 1
BIT 0
(LSB)
DEF. VALUE
(Hex)
INDEXED/
GLOBAL
Mirror
(Bit5)
Mirror
(Bit6)
Mirror
(Bit7)
00h
G
00h
G
Chip ID #
Read only
G
Chip Version #
Read only
G
00h
I
Coarse Offset
Cal. value
I
Fine Offset
Cal. value
I
Cal. value
I
Medium Gain
Cal. value
I
Fine Gain
Cal. value
I
00h
NOT
affected by
soft
reset
I
BIT 4
BIT 3
Reserved
ADC01
Reserved
ADC00
Coarse Gain
Reserved
Power-Down Mode [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
Reserved
clock_divide
80h
00h
G
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
Other Codes = Reserved
00h
NOT
affected by
soft reset
G
Output Format [2:0]
000 = Pin Control
001 = Twos Complement
010 = Gray Code
100 = Offset Binary
Other Codes = Reserved
00h
NOT
affected by
soft reset
G
Next
Clock
Edge
73
output_mode_A
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
other codes = Reserved
74
output_mode_B
DLL
Range
0 = fast
1 = slow
00h
NOT
affected by
soft
reset
G
75
config_status
XOR
Result
Read Only
G
76-BF
Reserved
FN6810 Rev 3.00
May 31, 2016
Reserved
Page 25 of 30
KAD5610P
DEVICE TEST
TABLE 18. SPI MEMORY MAP (Continued)
ADDR
(HEX)
PARAMETER
NAME
C0
test_io
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 0
(LSB)
BIT 1
Output Test Mode [3:0]
User Test Mode [1:0]
00 = Single
01 = Alternate
10 = Reserved
11 = Reserved
0 = Off
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Checker Board
5 = Reserved
6 = Reserved
DEF. VALUE
(Hex)
INDEXED/
GLOBAL
00h
G
00h
G
7 = One/Zero
Word Toggle
8 = User Input
9-15 = Reserved
C1
Reserved
Reserved
C2
user_patt 1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C3
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C4
user_patt 2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C5
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C6-FF
Reserved
Reserved
Equivalent Circuits
AVDD
TO
CLOCKPHASE
GENERATION
AVDD
CLKP
AVDD
CSAMP
1.6pF
TO
CHARGE
PIPELINE
F3
INP
2
F
1
F
1000
CSAMP
1.6pF
AVDD
TO
CHARGE
PIPELINE
3
F
INN
F
2
1
F
AVDD
11k
CLKN
FIGURE 43. CLOCK INPUTS
(20k PULL-UP
ON RESETN
ONLY)
AVDD
AVDD
75k
AVDD
INPUT
18k
AVDD 11k
FIGURE 42. ANALOG INPUTS
AVDD
18k
OVDD
TO
SENSE
LOGIC
75k
280
OVDD
OVDD
20k
INPUT
280
75k
75k
FIGURE 44. TRI-LEVEL DIGITAL INPUTS
FN6810 Rev 3.00
May 31, 2016
TO
LOGIC
FIGURE 45. DIGITAL INPUTS
Page 26 of 30
KAD5610P
Equivalent Circuits
(Continued)
OVDD
2mA OR
3mA
OVDD
DATA
DATA
D[9:0]P
OVDD
OVDD
OVDD
D[9:0]N
DATA
D[9:0]
DATA
DATA
2mA OR
3mA
FIGURE 47. CMOS OUTPUTS
FIGURE 46. LVDS OUTPUTS
AVDD
VCM
0.535V
+
–
FIGURE 48. VCM_OUT OUTPUT
ADC Evaluation Platform
Intersil offers an ADC Evaluation platform, which can be used to
evaluate any of the KADxxxxx ADC family. The platform consists
of a FPGA based data capture motherboard and a family of ADC
daughtercards. This USB based platform allows a user to quickly
evaluate the ADC’s performance at a user’s specific application
frequency requirements. More information is available at
http://www.intersil.com/converters/adc_eval_platform/.
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs benefit
from isolating the analog and digital sections. Analog supply and
ground planes should be laid out under signal and clock inputs.
Locate the digital planes under outputs and logic pins. Grounds
should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
FN6810 Rev 3.00
May 31, 2016
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces will
increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to ground
are direct and low impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50Ω (100Ω
differential) characteristic impedance. Keep traces direct and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
characteristic impedance.
Page 27 of 30
KAD5610P
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will
not be operated do not require connection to ensure optimal ADC
performance. These inputs can be left floating if they are not
used. Tri-level inputs (NAPSLP, OUTMODE, OUTFMT, CLKDIV)
accept a floating input as a valid state, and therefore should be
biased according to the desired functionality.
Definitions
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Differential Nonlinearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less 2 LSB. It is typically expressed in percent.
Integral Nonlinearity (INL) is the maximum deviation of the ADC’s
transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
Least Significant Bit (LSB) is the bit that has the smallest value or
weight in a digital word. Its value in terms of input voltage is
VFS/(2N-1) where N is the resolution in bits.
Missing Codes are output codes that are skipped and will never
appear at the ADC output. These codes cannot be reached with
any input value.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the ADC FFT, caused by an AC signal
superimposed on the power supply voltage.
Signal to Noise and Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to
full-scale) when the converter’s full-scale input power is used as
the reference.
Spurious Free Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
Two-Tone SFDR is the ratio of the RMS value of the lowest power
input tone to the RMS value of the peak spurious component,
which may or may not be an IMD product.
© Copyright Intersil Americas LLC 2009-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6810 Rev 3.00
May 31, 2016
Page 28 of 30
KAD5610P
Revision History
.
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE
REVISION
CHANGE
May 31, 2016
FN6810.3
Converted to new datasheet template and applied Intersil standards.
Added MSL note to ordering information on page 3.
Updated the Electrical Specs Power Requirements and Total Power Dissipation for IAVDD and NAP
Mode as follows: IAVDD -25:177 to 187 -21:165 to 175 -17:152 to 162 -12:135 to 145
NAP Mode -25:163 to 170.2 -21:157 to 164.2 -17:151 to 158.2 -12:143 to 150.2
Updated 163 to 170.2 in “Nap/Sleep” on page 18.
Added About Intersil section.
May 14, 2009
FN6810.2
1)Updated pin diagram ; Added nap mode, sleep mode wake up times to spec table
2) Added CSB,SCLK Setup time specs for nap,sleep modes to spec table
4) Changed SPI setup spec wording in spec table
5) Change to pin description table for clarification
6) Added thermal pad note
7) Updated fig 24 and fig 25 and description in text.
8) Update multple device usage note on at “SPI Physical Interface” on page 21
9) Added ‘Reserved’ to SPI memory map at address 25H
10) Added section on “ADC Evaluation Platform” on page 27
11) Intersil standards applied: Added Pb-free bullet in features and pb-free reflow link in thermal
information, added over-temp note reference in spec table.
1. Change to SPI interface section in spec table, timing in cycles now, added write, read specific timing
specs
2. Updated SPI timing diagrams, Figures 36, 37
3. Updated wakeup time description in “Nap/Sleep” on page 18.
4. Removed calibration note in spec table
5) updated user reset section desc.
6) moved label in fig 45
January 15, 2009
FN6810.1
P1; revised Key Specs
P1; changed RESET to RESETN in block diagram
P2; added Part Marking column to Order Info
P4; Moved Thermal Impedance under Thermal Info (used to be on p. 7). Added Theta JA
Note 2.
P4-7; edits throughout the Specs table. Added Notes 8 and 9. Revised Notes 6 and 7.
P7; Removed ESD section
P10-12; revised Performance Curves throughout
P14; User Inititated Reset section; revised 2nd sentence of 1st paragraph
P19; Serial Peripheral Interface; revised 2nd to last sentence of 1st paragraph. SPI Physical Interface;
revised 2nd and 3rd sentences of 4th paragraph
P20; added last 2 sentences to 1st paragraph of "ADDRESS 0X24: GAIN_FINE". Revised Table 8
P21; revised last 2 sentences of "ADDRESS 0X71: PHASE_SLIP". Removed Figure of "PHASE SLIP:
CLK÷2 MODE, fCLOCK = 500MHz"
P24; revised Figure 44
P24; Table 17; revised Bits7:4, Addr C0
Throughout; formatted graphics to Intersil standards
August 6, 2008
FN6810.1
Initial Release of Production Datasheet
December 5, 2008
FN6810.0
Converted to intersil template. Assigned file number FN6810. Rev 0 - first release with new file number.
Applied Intersil Standards.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
FN6810 Rev 3.00
May 31, 2016
Page 29 of 30
KAD5610P
Package Outline Drawing
L72.10x10D
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 11/08
10.00
PIN 1
INDEX AREA
A
4X 8.50
B
55
6
72
1
54
68X 0.50
Exp. DAP
6.00 Sq.
10.00
(4X)
PIN 1
INDEX AREA
6
18
37
0.15
36
19
72X 0.24
72X 0.40
TOP VIEW
4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 Max
0.10 C
C
0.08 C
SEATING PLANE
68X 0.50
SIDE VIEW
72X 0.24
9.80 Sq
6.00 Sq
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
72X 0.60
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6810 Rev 3.00
May 31, 2016
Page 30 of 30
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