KGF12N05-400-SP

DATASHEET KGF12N05 FN8787 Rev 1.00 December 18, 2015 N-Channel 5.5V Power MOSFET The KGF12N05 is a 5.5V, 1.9mΩ, chip-scale, N-channel, multidirectional current flow MOSFET. The device uses technology that uniquely integrates low cost CMOS and WLCSP fabrication processes. The chip-scale WLCSP package offers small area, low vertical profile and is fully compatible with standard SMT assembly processes. The KGF12N05 device offers unprecedented low on-resistance and total gate charge, outperforming conventional trench MOSFETs and enabling high frequency, low voltage switching. The device offers extremely high power density, reducing the board size of DC/DC converters and other power management systems. Features • Industry leading figures of merit: rDS(ON) × Qg and rDS(ON) × Qgd • Low profile/small footprint chip-scale WLCSP package • High frequency switching • Known Good FET (KGF) Quality Assurance Process Applications • Low thermal resistance • Point-of-load DC/DC converters • Portable electronics PRODUCT SUMMARY ID TA = +25°C 12A Maximum • OR’ing diodes V(BR)DSS ID = 10mA 5.5V Minimum rDS(ON) VGS = 4.5V 1.9mΩ Typical Related Literature rDS(ON) VGS = 3.5V 2.1mΩ Typical Qg ID = 12A 5nC Typical 1.2nC Typical Qgd • AN1968, “Unclamped Inductive Switching (UIS) Test and Rating Methodology” D G S FIGURE 1. EQUIVALENT CIRCUIT FN8787 Rev 1.00 December 18, 2015 FIGURE 2. N-CHANNEL MOSFET WLCSP PACKAGE Page 1 of 7 KGF12N05 Ordering Information PART NUMBER TEMP RANGE (°C) PART MARKING KGF12N05-400-SP S Pin Configuration 6 Bump WLCSP Pin Descriptions KGF12N05 (6 BUMP WLCSP) LAND GRID ARRAY VIEW 5 S 1 -55 to +150 PACKAGE (RoHS Compliant) G PIN # PIN NAME DESCRIPTION 1 G Gate of MOSFET 2, 3, 4, 5 S Source of MOSFET 6 D Drain of MOSFET 6 D 2 S 4 S S 3 FN8787 Rev 1.00 December 18, 2015 Page 2 of 7 KGF12N05 Absolute Maximum Ratings Thermal Information (Note 1) Drain-to-Source Voltage (VDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5V Gate-to-Source Voltage (VGS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5.5V Drain Current Continuous (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12A Pulsed (IDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40A Single Pulse Avalanche Current (IAS) L ≤ 50µH, RG ≤ 25Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10A Thermal Resistance (Typical) JA (°C/W) JP (°C/W) WLCSP Package . . . . . . . . . . . . . . . . . . . . . . 50 10 Maximum Power Dissipation (PD) (Note 2) TA = +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W (10s) TA = +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6W Junction and Storage Temperature Range (TJ, Tstg). . . . .-55°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. TJ = +25°C unless otherwise noted. 2. When mounted on 1 inch square 2oz copper clad FR-4. Electrical Characteristics SYMBOL TJ = +25°C unless otherwise noted. PARAMETER TEST CONDITIONS MIN (Note 3) TYP (Note 4) MAX (Note 3) UNIT Drain-to-Source Breakdown Voltage VGS = 0V, ID = 10mA Zero Gate Voltage Drain Current VDS = 3.5V, VGS = 0V, TJ = +25°C 1 µA VDS = 5.5V, VGS = 0V, TJ = +25°C 25 µA VDS = 5.5V, VGS = 0V, TJ = +125°C 250 µA Gate-Body Leakage VGS = 5.5V, VDS = 0V 150 nA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA 0.62 0.80 V rDS(ON) Drain-to-Source On-State Resistance VGS = 3.5V, ID = 12A 2.1 2.6 mΩ VGS = 4.5V, ID = 12A 1.9 2.4 mΩ VDS = 5.5V, VGS = 0V, f = 1MHz 750 940 pF V(BR)DSS IDSS IGSS 5.5 0.52 V Ciss Input Capacitance Coss Output Capacitance 940 1175 pF Crss Reverse Transfer Capacitance 230 300 pF Ciss Input Capacitance 790 990 pF Coss Output Capacitance 1450 1800 pF Crss Reverse Transfer Capacitance 270 400 pF VDS = 0V, VGS = 0V, f = 1MHz rg Gate Resistance VDS = 0V, f = 1MHz 1.0 Qg Total Gate Charge VGS = 3.5V, ID = 12A, VDS = 4.4V 5.0 6.0 nC Qgs Gate-to-Source Charge 1.1 1.5 nC Qgd Gate-to-Drain Charge 1.2 2.0 nC Qg Total Gate Charge VGS = 4.5V, ID = 12A, VDS = 4.4V 6.2 7.0 nC trr Source-to-Drain Reverse Recovery Time IS = 3A, di/dt = 33A/µs 100 Diode Forward Voltage IS = 5A, VGS = 0V 0.65 VSD Ω ns 1.00 NOTES: 3. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 4. Typical values are for TA = +25°C. FN8787 Rev 1.00 December 18, 2015 Page 3 of 7 V KGF12N05 Typical Performance Curves 40 40 VGS = 5.0 TO 1.5V 35 ID - DRAIN CURRENT (A) ID - DRAIN CURRENT (A) 35 30 25 20 15 10 5 30 25 20 15 0 0.5 1 1.5 TJ = +25°C 5 1.0V 0 TJ = +125°C 10 0 0.00 2 0.50 VDS - DRAIN-TO-SOURCE VOLTAGE (V) 20 30 ID - DRAIN CURRENT (A) 40 50 rDS(ON) - ON-STATE RESISTANCE (mΩ) rDS(ON) - ON-STATE RESISTANCE (mΩ) VGS = 4.5V 10 16 14 12 10 VGS = 3.5V ID = 12A 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -25 0 25 50 75 100 125 150 TJ - JUNCTION TEMPERATURE (°C) FIGURE 7. ON-STATE RESISTANCE vs JUNCTION TEMPERATURE FN8787 Rev 1.00 December 18, 2015 VGS(th) - GATE THRESHOLD VOLTAGE (V) (NORMALIZED) rDS(ON) - ON-STATE RESISTANCE (mΩ) 1.4 -50 ID = 12A 8 6 4 2 0 0.00 1.00 2.00 3.00 4.00 VGS - GATE-TO-SOURCE VOLTAGE (V) 5.00 FIGURE 6. ON-RESISTANCE vs GATE-TO-SOURCE VOLTAGE 1.5 1.2 2.00 18 FIGURE 5. ON-RESISTANCE vs DRAIN CURRENT 1.3 1.50 FIGURE 4. TRANSFER CHARACTERISTICS VGS = 3.5V 0 1.00 VGS - GATE-TO-SOURCE (V) FIGURE 3. OUTPUT CHARACTERISTICS 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 TJ = -55°C 1.4 1.3 ID = 250µA 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 -50 -25 0 25 50 75 100 125 150 TJ - JUNCTION TEMPERATURE (°C) FIGURE 8. GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE Page 4 of 7 KGF12N05 1.10 100 IS - SOURCE CURRENT (A) V(BR)DSS - DRAIN-TO-SOURCE BREAKDOWN VOLTAGE (V) (NORMALIZED Typical Performance Curves (Continued) 1.05 ID = 10mA 1.00 0.95 0.90 -50 -25 0 25 50 75 100 125 1 150 0 0.2 TJ - JUNCTION TEMPERATURE C - CAPACITANCE (pF) VGS - GATE-TO-SOURCE VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 2 3 0.8 1 1.2 1600 1600 VDS = 4.4V ID = 5A VGS = 0 to 4.5V 0 0.6 FIGURE 10. SOURCE-TO-DRAIN DIODE FORWARD VOLTAGE 4.5 3.5 0.4 VSD - DIODE FORWARD VOLTAGE (V) FIGURE 9. DRAIN-TO-SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 4.0 TJ = +25oC TJ = +125oC 10 4 5 6 1400 1400 1200 1200 1000 1000 800 800 600 600 400 400 200 200 00 7 00 11 22 33 44 55 VDS - DRAIN-TO-SOURCE VOLTAGE (V) VDS - DRAIN-TO-SOURCE VOLTAGE (V) QG - TOTAL GATE CHARGE (nC) FIGURE 11. GATE CHARGE FIGURE 12. CAPACITANCE ID - DRAIN CURRENT (A) 100 1ms 10 10ms 100ms 1 rDS(ON) LIMIT PACKAGE LIMIT THERMAL LIMIT 0.1 DC TA = +25oC, SINGLE PULSE VGS = 4.5V 0.01 0.1 1 10 VDS - DRAIN-TO-SOURCE VOLTAGE (V) FIGURE 13. MAXIMUM RATED FORWARD BIASED SAFE OPERATING AREA FN8787 Rev 1.00 December 18, 2015 Page 5 of 7 KGF12N05 r(t) - TRANSIENT THERMAL RESISTANCE (NORMALIZED) Typical Performance Curves (Continued) 1.00 0.5 0.2 0.10 0.1 0.05 0.02 = +50oC/W SINGLE PULSE 0.01 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 t, TIME (s) FIGURE 14. TRANSIENT THERMAL RESPONSE, JUNCTION-TO-AMBIENT Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE December 18, 2015 FN8787.1 Added “Note 1. TJ = +25°C unless otherwise noted.” to Abs Max on page 3. October 30, 2015 FN8787.0 Initial release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8787 Rev 1.00 December 18, 2015 Page 6 of 7 KGF12N05 Dimensional Outline and Pad Layout Die Size = 1.47mm ± 0.005mm (square) Pad Thickness = 3µm NiAu Die Thickness = 400µm ± 15µm FN8787 Rev 1.00 December 18, 2015 Page 7 of 7