M30082040054X0IWAY

High Performance Serial MRAM Memory M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Description Features Mxxxx204 is a magneto-resistive random-access memory (MRAM). It is offered in density ranging from 4Mbit to 16Mbit. MRAM technology is analogous to Flash technology with SRAM compatible read/write timings (Persistent SRAM, P-SRAM). Data is always non-volatile.  Interface MRAM is a true random-access memory; allowing both reads and writes to occur randomly in memory. MRAM is ideal for applications that must store and retrieve data without incurring large latency penalties. It offers low latency, low power, virtually infinite endurance and retention, and scalable non-volatile memory technology.    Mxxxx204 is available in small footprint 8-pad DFN (WSON) and 8pin SOIC packages. These packages are compatible with similar low-power volatile and non-volatile products.  Mxxxx204 is offered with industrial (-40°C to 85°C) and industrial plus (-40°C to 105°C) operating temperature ranges.  Typical Applications • Ideal for applications that must store and retrieve data without incurring large latency penalties. • Factory Automation • Multifunction Printers • Industrial Control And Monitoring • Medical Diagnostics • Data Switches And Routers Serial Peripheral Interface QSPI (4-4-4) • Single Data Rate Mode: 108MHz • Double Data Rate Mode: 54MHz Technology • 40nm pMTJ STT-MRAM Virtually unlimited Endurance and Data Retention (see Endurance and Data Retention specification on page 38) Density • 4Mb, 8Mb, 16Mb Operating Voltage Range • VCC: 1.71V – 2.00V • VCC: 2.70V – 3.60V Operating Temperature Range • Industrial: -40°C to 85°C • Industrial Plus: -40°C to 105°C Packages • 8-pad DFN (WSON) (5.0mm x 6.0mm) • 8-pin SOIC (5.2mm x 5.2mm) Data Protection • Hardware Based: Write Protect Pin (WP#) Software Based: Address Range Selectable through Configuration bits (Top/Bottom, Block Protect[2:0]) Identification • 64-bit Unique ID • 64-bit User Programmable Serial Number Augmented Storage Array • 256-byte User Programmable with Write Protection Supports JEDEC Reset RoHS Compliant •      Block Diagram CS# Status Register Column Decoder Command Register IO[3] Row Decoder SO / IO[1] WP# / IO[2] VCC Address Register Serial I/Os Command & Control MRAM MRAM MRAM Array Array Array CLK High Voltage Generator VSS SI / IO[0] Regulator Feb.25.21 Data Buffer Page 1 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Contents 1. Performance ............................................................................................................................................................................................3 2. General Description ...............................................................................................................................................................................3 3. Ordering Options ....................................................................................................................................................................................4 3.1 Valid Combinations — Standard .........................................................................................................................................................4 4. Signal Description and Assignment..................................................................................................................................................7 5. Package Options ....................................................................................................................................................................................9 5.1 8-Pad DFN (WSON) (Top View)..........................................................................................................................................................9 5.2 8-Pin SOIC (Top View) ........................................................................................................................................................................9 6. Package Drawings ...............................................................................................................................................................................10 6.1 8-Pad DFN (WSON) ..........................................................................................................................................................................10 6.2 8-Pin SOIC ........................................................................................................................................................................................11 7. Architecture ............................................................................................................................................................................................12 8. Device Initialization ..............................................................................................................................................................................14 9. Memory Map ..........................................................................................................................................................................................16 10. Augmented Storage Array Map .......................................................................................................................................................16 11. Register Addresses .............................................................................................................................................................................16 12. Register Map..........................................................................................................................................................................................17 12.1 Status Register / Device Protection Register (Read/Write) ...............................................................................................................17 12.2 Augmented Storage Array Protection Register (Read/Write) ............................................................................................................18 12.3 Device Identification Register (Read Only) ........................................................................................................................................19 12.4 Serial Number Register (Read/Write) ................................................................................................................................................19 12.5 Unique Identification Register (Read Only) .......................................................................................................................................19 12.6 Configuration Register 1 (Read/Write)...............................................................................................................................................20 12.7 Configuration Register 2 (Read/Write)...............................................................................................................................................21 12.8 Configuration Register 3 (Read/Write)...............................................................................................................................................23 12.9 Configuration Register 4 (Read/Write)...............................................................................................................................................23 13. Instruction Set........................................................................................................................................................................................24 14. Instruction Description and Structures...........................................................................................................................................27 15. Electrical Specifications......................................................................................................................................................................38 15.1 CS# Operation & Timing....................................................................................................................................................................42 15.2 Data Output Operation & Timing .......................................................................................................................................................44 15.3 WP# Operation & Timing ...................................................................................................................................................................45 Enter Deep Power Down Command (EDP – B9h) ............................................................................................................................46 Exit Deep Power Down Command (EXDPD - ABh) ..........................................................................................................................47 Enter Hibernate Command (EHBN – BAh) ........................................................................................................................................48 16. Thermal Resistance.............................................................................................................................................................................49 17. Revision History ....................................................................................................................................................................................50 Feb.25.21 Page 2 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 1. Performance Device Operation Typical Values Units Frequency of Operation 108 (maximum) MHz 160 (typical) µA Standby Current Deep Power Down Current 2. 5 (typical) µA Hibernate Current 0.1 (typical) µA Active Read Current – (4-4-4) SDR @ 108MHz 19 (typical) mA Active Write Current – (4-4-4) SDR @ 108MHz 38 (typical) mA General Description Mxxxx204 is a magneto-resistive random-access memory (MRAM). It is offered in density ranging from 4Mbit to 16Mbit. MRAM technology is analogous to Flash technology with SRAM compatible read/write timings (Persistent SRAM, P-SRAM). Data is always non-volatile. Figure 1: Technology Comparison Non-Volatility Write Performance Read Performance Endurance Power SRAM − √ √ √ − Flash √ − − − − EEPROM √ − − − − MRAM √ √ √ √ √ MRAM is a true random-access memory; allowing both reads and writes to occur randomly in memory. MRAM is ideal for applications that must store and retrieve data without incurring large latency penalties. It offers low latency, low power, virtually infinite endurance and retention, and scalable non-volatile memory technology. Mxxxx204 has a Serial Peripheral Interface (SPI). SPI is a synchronous interface which uses separate lines for data and clock to help keep the host and slave in perfect synchronization. The clock tells the receiver exactly when to sample the bits on the data line. This can be either the rising (low to high) or falling (high to low) or both edges of the clock signal; please consult the instruction sequences in this datasheet for more details. When the receiver detects that correct edge, it can latch in the data. Mxxxx204 is available in small footprint 8-pad DFN (WSON) and 8-pin SOIC packages. These packages are compatible with similar low-power volatile and non-volatile products. Mxxxx204 is offered with industrial (-40°C to 85°C) and industrial plus (-40°C to 105°C) operating temperature ranges. Feb.25.21 Page 3 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 3. Ordering Options The ordering part numbers are formed by a valid combination of the following options: M 1 004 2 04 0108 X 0I WA R Packing Type R: Tape & Reel Y: Tray Package Type WA: 8-pad DFN (WSON) SA: 8-pin SOIC Temperature Range 0I: Industrial (-40°C to +85°C) 0P: Industrial Plus (-40°C to +105°C) Reserved Performance 0108: 108MHz 0054: 54MHz Sub-Interface Type 04: x4 Interface Type 2: Serial Peripheral Interface (DDR) Density 004: 4 Megabit 008: 8 Megabit 016: 16 Megabit Operational Voltage 1: 1.8V (1.71V to 2.0V) 3: 3.0V (2.70V to 3.60V) Brand – Product Family M: Renesas - Persistant SRAM 3.1 Valid Combinations — Standard Valid Combinations list includes device configurations currently available. Contact your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Feb.25.21 Page 4 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Table 1: Valid Combinations List Valid Combinations – 108MHz Base Part Number M10042040108X Temperature Range Package Type Packing Type 0I, 0P WA, SA R, Y Part Number M10042040108X0IWAR M10042040108X0IWAY M10042040108X0ISAR M10042040108X0ISAY M10042040108X0PWAR M10042040108X0PWAY M10042040108X0PSAR M10042040108X0PSAY M30042040108X 0I, 0P WA, SA R, Y M30042040108X0IWAR M30042040108X0IWAY M30042040108X0ISAR M30042040108X0ISAY M30042040108X0PWAR M30042040108X0PWAY M30042040108X0PSAR M30042040108X0PSAY M10082040108X 0I, 0P WA, SA R, Y M10082040108X0IWAR M10082040108X0IWAY M10082040108X0ISAR M10082040108X0ISAY M10082040108X0PWAR M10082040108X0PWAY M10082040108X0PSAR M10082040108X0PSAY M30082040108X 0I, 0P WA, SA R, Y M30082040108X0IWAR M30082040108X0IWAY M30082040108X0ISAR M30082040108X0ISAY M30082040108X0PWAR M30082040108X0PWAY M30082040108X0PSAR M30082040108X0PSAY M10162040108X 0I, 0P WA, SA R, Y M10162040108X0IWAR M10162040108X0IWAY M10162040108X0ISAR M10162040108X0ISAY M10162040108X0PWAR M10162040108X0PWAY M10162040108X0PSAR M10162040108X0PSAY M30162040108X 0I, 0P WA, SA R, Y M30162040108X0IWAR M30162040108X0IWAY M30162040108X0ISAR M30162040108X0ISAY M30162040108X0PWAR M30162040108X0PWAY M30162040108X0PSAR M30162040108X0PSAY Valid Combinations – 54MHz Base Part Number M10042040054X Temperature Range Package Type Packing Type 0I, 0P WA, SA R, Y Part Number M10042040054X0IWAR M10042040054X0IWAY M10042040054X0ISAR M10042040054X0ISAY M10042040054X0PWAR M10042040054X0PWAY M10042040054X0PSAR M10042040054X0PSAY M30042040054X 0I, 0P WA, SA R, Y M30042040054X0IWAR M30042040054X0IWAY Feb.25.21 Page 5 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Valid Combinations – 54MHz Base Part Number Temperature Range Package Type Packing Type Part Number M30042040054X0ISAR M30042040054X0ISAY M30042040054X0PWAR M30042040054X0PWAY M30042040054X0PSAR M30042040054X0PSAY M10082040054X 0I, 0P WA, SA R, Y M10082040054X0IWAR M10082040054X0IWAY M10082040054X0ISAR M10082040054X0ISAY M10082040054X0PWAR M10082040054X0PWAY M10082040054X0PSAR M10082040054X0PSAY M30082040054X 0I, 0P WA, SA R, Y M30082040054X0IWAR M30082040054X0IWAY M30082040054X0ISAR M30082040054X0ISAY M30082040054X0PWAR M30082040054X0PWAY M30082040054X0PSAR M30082040054X0PSAY M10162040054X 0I, 0P WA, SA R, Y M10162040054X0IWAR M10162040054X0IWAY M10162040054X0ISAR M10162040054X0ISAY M10162040054X0PWAR M10162040054X0PWAY M10162040054X0PSAR M10162040054X0PSAY M30162040054X 0I, 0P WA, SA R, Y M30162040054X0IWAR M30162040054X0IWAY M30162040054X0ISAR M30162040054X0ISAY M30162040054X0PWAR M30162040054X0PWAY M30162040054X0PSAR M30162040054X0PSAY Feb.25.21 Page 6 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 4. Signal Description and Assignment Figure 2: Device Pinout CS# WP# / IO[2] SI / IO[0] CLK 4Mb – 16Mb Quad SPI MRAM SO / IO[1] IO[3] Signal Type CS# Input WP# / IO[2] Input / Bidirectional CLK Input IO[3] Bidirectional SI / IO[0] Input / Bidirectional Feb.25.21 Table 2: Signal Description Description Chip Select: When CS# is driven High, the device will enter standby mode. All other input pins are ignored and the output pin is tri-stated. Driving CS# Low enables the device, placing it in the active mode. After power-up, a falling edge on CS# is required prior to the start of any instructions. Write Protect (SPI): Write protects the status register in conjunction with the enable/disable bit of the status register. This is important since other write protection features are controlled through the Status Register. When the enable/disable bit of the status register is set to 1 and the WP# signal is driven Low, the status register becomes read-only and the WRITE STATUS REGISTER operation will not execute. This signal does not have internal pullups, it cannot be left floating and must be driven. WP# is valid only in Single SPI mode. Bidirectional Data 2 (DPI/QPI): The bidirectional I/O transfers data into and out of the device in Dual and Quad SPI modes. Clock: Provides the timing for the serial interface. Depending on the mode selected, either single (rising or falling) edge or both edges of the clock are utilized for information transfer. In Single Data Rate mode (SDR) command, address and data inputs are latched on the rising edge of the clock. Data is output on the falling edge of the clock. In Double Data Rate mode (DDR) command is latched on the rising edge of the clock. Address and Data inputs are latched on both edges of the clock. Similarly, Data is output on both edges of the clock. The following two SPI clock modes are supported. • SPI Mode 0 (CPOL = 0, CPHA = 0) – SDR and DDR • SPI Mode 3 (CPOL = 1, CPHA = 1) – SDR only Bidirectional Data 3 (DPI/QPI): The bidirectional I/O transfers data into and out of the device in Dual and Quad SPI modes. Serial Data Input (SPI): The unidirectional I/O transfers data into the device on the rising edge of the clock in Single SPI mode. Bidirectional Data 0 (DPI/QPI): The bidirectional I/O transfers data into and out of the device in Dual and Quad SPI modes. Page 7 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Signal Type Description SO / IO[1] Output / Bidirectional Serial Data Output (SPI): The unidirectional I/O transfers data out of the device on the falling edge of the clock in Single SPI mode. Bidirectional Data 1 (DPI/QPI): The bidirectional I/O that transfers data into and out of the device in Dual and Quad SPI modes. VCC Supply VCC: Core and I/O power supply. VSS Supply VSS: Core and I/O ground supply. Feb.25.21 Page 8 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 5. 5.1 Package Options 8-Pad DFN (WSON) (Top View) Figure 3: 8-Pad DFN (WSON) 5.2 CS# 1 8 VCC SO / IO[1] 2 7 IO[3] WP# / IO[2] 3 6 CLK VSS 4 5 SI / IO[0] 8-Pin SOIC (Top View) Figure 4: 8-Pin SOIC Feb.25.21 CS# 1 8 VCC SO / IO[1] 2 7 IO[3] WP# / IO[2] 3 6 CLK VSS 4 5 SI / IO[0] Page 9 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 6. 6.1 Package Drawings 8-Pad DFN (WSON) Feb.25.21 Page 10 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 6.2 8-Pin SOIC Feb.25.21 Page 11 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 7. Architecture Mxxxx204 is a high performance serial STT-MRAM device. It features a SPI-compatible bus interface running at 108MHz, eXecute-In-Place (XIP) functionality, and hardware/software based data protection mechanisms. When CS# is Low, the device is selected and in active power mode. When CS# is High, the device is deselected but can remain in active power mode until ongoing internal operations are completed. Then the device goes into standby power mode and device current consumption drops to ISB. Mxxxx204 contains an 8-bit instruction register. All functionality is controlled through the values loaded into this instruction register. In Single SPI mode, the device is accessed via the SI / IO[0] pin. In Dual and Quad SPI modes, IO[0:1] and IO[0:3] are used to access the device respectively. Furthermore, Single Data Rate (SDR) and Double Data Rate (DDR) instructions utilize CLK edges differently to transfer information; SDR uses a single CLK edge whereas DDR uses both edges of CLK. Table 3 summarizes all the different interface modes supported and their respective I/O usage. Table 4 shows the clock edge used for each instruction component. Nomenclature adoption: A typical SPI instruction consists of command, address and data components. The bus width to transmit these three components varies based on the SPI interface mode selected. To accurately represent the number of I/Os used to transmit these three components, a nomenclature (command-address-data) is adopted and used throughout this document. Integers placed in the (command-address-data) fields represent the number of I/Os used to transmit the particular component. As an example, 1-1-1 means command, address and data are transmitted on a single I/O (SI / IO[0] or SO / IO[1]). On the other hand, 1-4-4 represents command being sent on a single I/O (SI / IO[0]) and address/data being sent on four I/Os (IO[3:0]). Instruction Component Command Address Data Input Data Output Single SPI (1-1-1) SI / IO[0] SI / IO[0] SI / IO[0] SO / IO[1] Table 3: Interface Modes of Operations Dual Dual DPI Quad Input I/O Input Output SPI Output SPI SPI (1-1-2) (1-2-2) (2-2-2) (1-1-4) SI / IO[0] SI / IO[0] IO[1:0] SI / IO[0] SI / IO[0] IO[1:0] IO[1:0] SI / IO[0] IO[1:0] IO[1:0] IO[1:0] IO[3:0] IO[1:0] IO[1:0] IO[1:0] IO[3:0] Quad I/O SPI QPI (1-4-4) SI / IO[0] IO[3:0] IO[3:0] IO[3:0] (4-4-4) IO[3:0] IO[3:0] IO[3:0] IO[3:0] Table 4: Clock Edge Used for instructions in SDR and DDR modes Instruction Type Command Address Data Input (1-1-1) SDR (1-1-1) DDR (1-1-2) (1-2-2) (2-2-2) (2-2-2) (1-1-4) (1-4-4) (1-4-4) (4-4-4) (4-4-4) SDR SDR SDR DDR SDR SDR DDR SDR DDR R R R R Data Output F R 1 F R F F 1 R R R R F 1 R R R F 1 R R R R R F R R R R R R R R R R F R R R F R 1 1 F F F F 1 R 1 F F 1 R F R F 1 F R F R 1 Notes: R: Rising Clock Edge F: Falling Clock Edge 1: Data output from Mxxxx204 always begins on the falling edge of the clock – SDR & DDR Feb.25.21 Page 12 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Mxxxx204 supports eXecute-In-Place (XIP) which allows completing a series of read and write instructions without having to individually load the read or write command for each instruction. Thus, XIP mode saves command overhead and reduces random read & write access time. A special XIP byte must be entered after the address bits to enable/disable (Axh/Fxh) XIP. Mxxxx204 offers both hardware and software based data protection schemes. Hardware protection is through WP# pin. Software protection is controlled by configuration bits in the Status register. Both schemes inhibit writing to the registers and memory array. Mxxxx204 has a 256-byte Augmented Storage Array which is independent from the main memory array. It is user programmable and can be write protected against inadvertent writes. Two lower power states are available in Mxxxx204, namely Deep Power Down and Hibernate. Data is not lost while the device is in either of these two low power states. Moreover, the device maintains all its configurations. Figure 5: Functional Block Diagram CS# VCC Address Register Status Register Serial I/Os Column Decoder Command Register WP# / IO[2] IO[3] Row Decoder SO / IO[1] Command & Control MRAM MRAM MRAM Array Array Array CLK High Voltage Generator VSS SI / IO[0] Regulator Mode Standby Active - Read Active - Write Deep Power Down Hibernate Current ISB IREAD IWRITE IDPD IHBN Data Buffer Table 5: Modes of Operation CS# CLK SI / IO[3:0] H Gated Gated / Hi-Z L Toggle Command, Address L Toggle Command, Address, Data Input H Gated Gated / Hi-Z H Gated Gated / Hi-Z SO / IO[3:0] Hi-Z / Hi-Z Data Output Hi-Z Hi-Z / Hi-Z Hi-Z / Hi-Z Notes: H: High (Logic ‘1’) L: Low (Logic ‘0’) Hi-Z: High Impedance Feb.25.21 Page 13 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 8. Device Initialization When powering up, the following procedure is required to initialize the device correctly: • Ramp up VCC (RVR) • CS# must follow VCC during power-up (a 10KΩ pull-up Resistor to VCC is recommended) • It is recommended that no instructions are sent to the device when VCC is below VCC (minimum) • During initial Power-up, recovering from power loss or brownout, a delay of tPU is required before normal operation commences • Upon Power-up, the device is in Standby mode Figure 6: Power-Up Behavior Voltage Device Fully Operational VCC (Maximum) VCC (Minimum) tPU Time 0V When powering down, the following procedure is required to turn off the device correctly: • Ramp down VCC (RVF) • CS# must follow VCC during power-down (a 10KΩ pull-up Resistor to VCC is recommended) • It is recommended that no instructions are sent to the device when VCC is below VCC (minimum) • The Power-up timing needs to be observed after VCC goes above VCC (minimum) Figure 7: Power-Down Behavior Voltage Device Fully Operational VCC (Maximum) VCC (Minimum) VCC-CUTOFF (Cut Off) tPU Time 0V Feb.25.21 Page 14 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Table 6: Power Up/Down Timing – 3.0V Parameter Symbol Test Conditions Minimum 3.0V Typical Maximum Units VCC Range VCC 2.7 - 3.6 V VCC Ramp Up Time RVR 30 - - µs/V VCC Ramp Down Time RVF 20 - - µs/V VCC Power Up to First Instruction tPU VCC- 250 - - µs 1.6 - - V - - 3 µs VCC Cutoff – Must Initialize Device CUTOFF All operating voltages and temperatures Time to Enter Deep Power Down tEDPD Time to Exit Deep Power Down tEXDPD - - 400 µs Time to Enter Hibernate tENTHIB - - 3 µs Time to Exit Hibernate tEXHIB - - 450 µs CS# Pulse Width tCSDPD 50 - - ns Table 7: Power Up/Down Timing – 1.8V Minimum 1.8V Typical Maximum Units VCC Range VCC 1.71 - 2.0 V VCC Ramp Up Time RVR 30 - - µs/V VCC Ramp Down Time RVF 20 - - µs/V VCC Power Up to First Instruction tPU VCC- 250 - - µs 1.6 - - V - - 3 µs Parameter VCC Cutoff – Must Initialize Device Symbol CUTOFF Test Conditions All operating voltages and temperatures Time to Enter Deep Power Down tEDPD Time to Exit Deep Power Down tEXDPD - - 400 µs Time to Enter Hibernate tENTHIB - - 3 µs Time to Exit Hibernate tEXHIB - - 450 µs CS# Pulse Width tCSDPD 50 - - ns Feb.25.21 Page 15 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 9. Memory Map Table 8: Memory Map Density 4Mb 8Mb 16Mb Address Range 000000h – 07FFFFh 000000h – 0FFFFFh 000000h – 1FFFFFh 24-bit Address [23:0] [23:19] – Logic ‘0’ [18:0] - Addressable [23:20] – Logic ‘0’ [19:0] - Addressable [23:21] – Logic ‘0’ [20:0] - Addressable 10. Augmented Storage Array Map Density 4Mb 8Mb 16Mb Table 9: Augmented Storage Array Map Address Range 24-bit Address [23:0] 1 000000h – 0000FFh [23:8] – Logic ‘0’ [7:0] - Addressable 000000h – 0000FFh 1 [23:8] – Logic ‘0’ [7:0] - Addressable 000000h – 0000FFh 1 [23:8] – Logic ‘0’ [7:0] - Addressable Notes: 1: The 256-byte augmented storage array is divided into 8 individually readable and writeable sections (32 bytes per section). After an individual section is programmed, it can be write protected to prevent further programming. Section 0 1 2 3 4 5 6 7 Table 10: Individual Section Address Range Address Range 24-bit Address [23:0] 000000h – 00001Fh [23:8] – Logic ‘0’ [7:0] - Addressable 000020h – 00003Fh [23:8] – Logic ‘0’ [7:0] - Addressable 000040h – 00005Fh [23:8] – Logic ‘0’ [7:0] - Addressable 000060h – 00007Fh [23:8] – Logic ‘0’ [7:0] - Addressable 000080h – 00009Fh [23:8] – Logic ‘0’ [7:0] - Addressable 0000A0h – 0000BFh [23:8] – Logic ‘0’ [7:0] - Addressable 0000C0h – 0000DFh [23:8] – Logic ‘0’ [7:0] - Addressable 0000E0h – 0000FFh [23:8] – Logic ‘0’ [7:0] - Addressable 11. Register Addresses Table 11: Register Addresses Register Name Status Register Configuration Register 1 Configuration Register 2 Configuration Register 3 Configuration Register 4 Device Identification Register Unique Identification Register Address 0x000000h 0x000002h 0x000003h 0x000004h 0x000005h 0x000030h 0x000040h Note: 1: Register address space is different from the memory array and augmented storage array. MRAM INITIALIZATION REQUIREMENT After reflow temp cycle, MRAM Registers must be reconfigured to default settings. Please see the apps note; “Programming Non-Volatile Registers to Factory Default State Post-Reflow Application Note” for details. Feb.25.21 Page 16 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 12. Register Map 12.1 Status Register / Device Protection Register (Read/Write) Status register is a legacy SPI register and contains options for enabling/disabling data protection. Bits Name SR[7] WP#EN SR[6] SNPEN SR[5] TBSEL SR[4] SR[3] SR[2] BPSEL[2] BPSEL[1] BPSEL[0] SR[1] WREN SR[0] RSVD BPSEL [2] 0 Table 13: Top Block Protection Address Range Selection (TBPSEL=0) BPSEL BPSEL Protected 4Mb 8Mb 16Mb [1] [0] Portion None None None 0 0 None 0 0 1 Upper 1/64 0 1 0 Upper 1/32 0 1 1 Upper 1/16 1 0 0 Upper 1/8 1 0 1 Upper 1/4 1 1 0 Upper 1/2 1 1 1 All BPSEL [2] 0 Feb.25.21 Table 12: Status Register – Read and Write Read / Default Selection Description Write State Options 1: Protection Enabled – write protects Hardware Based WP# when WP# is Low R/W 0 Protection Enable/Disable 0: Protection Disabled – Doesn’t write protect when WP# is Low 1: S/N Write protected - protection Serial Number Protection R/W 0 enabled Enable/Disable 0: S/N Writable - protection disabled 1: Bottom Protection Enabled (Lower Software Top/Bottom Address Range) Memory Array Protection R/W 0 0: Top Protection Enabled (Higher Selection Address Range) Block Protect Selection Bit 2 R/W 0 Block Protection Bits (Table 13, Table Block Protect Selection Bit 1 R/W 0 14) Block Protect Selection Bit 0 R/W 0 Write Operation Protection 1: Write Operation Protection Disabled R 0 Enable/Disable 0: Write Operation Protection Enabled Reserved R 0 Reserved for future use 07E000h – 07FFFFh 07C000h – 07FFFFh 078000h – 07FFFFh 070000h – 07FFFFh 060000h – 07FFFFh 040000h – 07FFFFh 000000h – 07FFFFh 0FC000h – 0FFFFFh 0F8000h – 0FFFFFh 0F0000h – 0FFFFFh 0E0000h – 0FFFFFh 0C0000h – 0FFFFFh 080000h – 0FFFFFh 000000h – 0FFFFFh 1F8000h – 1FFFFFh 1F0000h – 1FFFFFh 1E0000h – 1FFFFFh 1C0000h – 1FFFFFh 180000h – 1FFFFFh 1F0000h – 1FFFFFh 000000h – 1FFFFFh Table 14: Bottom Block Protection Address Range Selection (TBPSEL=1) BPSEL BPSEL Protected 4Mb 8Mb 16Mb [1] [0] Portion None None None 0 0 None 0 0 1 Lower 1/64 0 1 0 Lower 1/32 000000h – 001FFFh 000000h – 003FFFh 000000h – 003FFFh 000000h – 007FFFh 000000h – 007FFFh 000000h – 00FFFFh Page 17 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 BPSEL [2] BPSEL [1] BPSEL [0] Protected Portion 0 1 1 Lower 1/16 1 0 0 Lower 1/8 1 0 1 Lower 1/4 1 1 0 Lower 1/2 1 1 1 All WREN (Status Register) 0 1 1 1 4Mb 8Mb 16Mb 000000h – 007FFFh 000000h – 00FFFFh 000000h – 01FFFFh 000000h – 03FFFFh 000000h – 07FFFFh 000000h – 00FFFFh 000000h – 01FFFFh 000000h – 03FFFFh 000000h – 07FFFFh 000000h – 0FFFFFh 000000h – 01FFFFh 000000h – 03FFFFh 000000h – 07FFFFh 000000h – 0FFFFFh 000000h – 1FFFFFh Table 15: Write Protection Modes Status WP#EN WP# & (Status Register) (Pin) Configuration Registers X X Protected 0 X Unprotected 1 Low Protected 1 High Unprotected Memory1 Array Protected Area Protected Protected Protected Protected Memory1 Array Unprotected Area Protected Unprotected Unprotected Unprotected Notes: High: Logic ‘1’ Low: Logic ‘0’ X: Don’t Care – Can be Logic ‘0’ or ‘1’ Protected: Write protected Unprotected: Writable 1: Memory address range protection based on Block Protection Bits 12.2 Augmented Storage Array Protection Register (Read/Write) Augmented Storage Array Protection register contains options for enabling/disabling data protection for eight 32-byte sections. Table 16: Augmented Storage Array Protection Register – Read and Write Read Default Selection Bits Name Description / State Options Write ASA Section 7 Write 1: Protection Enabled ASP[7] ASPS[7] R/W 0 0: Protection Disabled Protection Enable/Disable ASA Section 6 Write 1: Protection Enabled ASP[6] ASPS[6] R/W 0 0: Protection Disabled Protection Enable/Disable ASA Section 5 Write 1: Protection Enabled ASP[5] ASPS[5] R/W 0 0: Protection Disabled Protection Enable/Disable ASA Section 4 Write 1: Protection Enabled ASP[4] ASPS[4] R/W 0 0: Protection Disabled Protection Enable/Disable ASA Section 3 Write 1: Protection Enabled ASP[3] ASPS[3] R/W 0 0: Protection Disabled Protection Enable/Disable ASA Section 2 Write 1: Protection Enabled ASP[2] ASPS[2] R/W 0 0: Protection Disabled Protection Enable/Disable ASA Section 1 Write 1: Protection Enabled ASP[1] ASPS[1] R/W 0 0: Protection Disabled Protection Enable/Disable ASA Section 0 Write 1: Protection Enabled ASP[0] ASPS[0] R/W 0 0: Protection Disabled Protection Enable/Disable Feb.25.21 Page 18 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 12.3 Device Identification Register (Read Only) Device identification register contains Avalanche’s Manufacturing ID along with device configuration information. Table 17: Device Identification Register – Read Only Avalanche Device Manufacturer's ID Configuration Bits ID[31:0] ID[31:24] Interface Voltage Temp Density Freq ID[23:20] ID[19:16] ID[15:12] ID[11:8] ID[7:0] Manufacturer ID Interface Voltage Temperature Density Frequency 31-24 23-20 19-16 15-12 11-8 7-0 1110 0110 0000-HP QSPI 0001 - 3V 0000 - -40⁰C- 85⁰C 0010 - 4Mb 00000001 - 108MHz 0010 - 1.8V 0001 - -40⁰C-105⁰C 0011 - 8Mb 00000010 – 54MHz 0100 - 16Mb 00000011 - Reserved 00000100 - Reserved 00000101 - Reserved 12.4 Serial Number Register (Read/Write) Serial Number register is user writable. Bits Name SN[63:0] SN Table 18: Serial Number Register – Read and Write Read Selection Description / Default State 1 Options Write 000000000000 Value stored is based on the customer Serial Number Value R/W 0000h Notes: 1: The default value is how the device is shipped from the factory. 12.5 Unique Identification Register (Read Only) Unique Identification register contains a number unique to every device. Bits Name UID[63:0] UID Feb.25.21 Table 19: Unique ID Register – Read Only Read / Selection Description Write Options Unique Identification Value stored is written in the factory and is R device specific Number Value Page 19 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 12.6 Configuration Register 1 (Read/Write) Configuration Register 1 controls locking/unlocking data protection options set in the Status register. Once locked, the protection options cannot be changed in the Status register. Bits Name Table 20: Configuration Register 1 – Read and Write Read Default Description / State Write Selection Options CR1[7] RSVD Reserved R 0 Reserved for future use CR1[6] RSVD Reserved R 0 Reserved for future use CR1[5] RSVD Reserved R 0 Reserved for future use CR1[4] RSVD Reserved R 0 Reserved for future use CR1[3] RSVD Reserved R 0 Reserved for future use R/W 0 CR1[2] MAPLK Status Register Lock Enable/Disable 1: Lock TBSEL and BPSEL[2:0] 0: Unlock TBSEL and BPSEL[2:0] (TBSEL, BPSEL[2:0] CR1[1] CR1[0] RSVD Reserved ASPLK Augmented Storage Array Data Protection R 0 Reserved for future use 1: Write Protect Augmented Storage Array R/W 0 0: Not Write Protect Augmented Storage Array Feb.25.21 Page 20 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 12.7 Configuration Register 2 (Read/Write) Configuration Register 2 controls the interface type along with memory array access latency. Bits Name Table 21: Configuration Register 2 – Read and Write Read Default Description / State Write CR2[7] RSVD Reserved R 0 CR2[6] QPISL Quad SPI (QPI 4-4-4) Interface Mode Enable/Disable R2 0 Selection Options Reserved for future use 1: Quad SPI (QPI 4-4-4) Enabled 0: Single SPI (SPI 1-1-1) Enabled CR2[5] RSVD Reserved R 0 CR2[4] DPISL Dual SPI (DPI 2-2-2) Interface Mode Enable/Disable R2 0 Reserved for future use 1: Dual SPI (DPI 2-2-2) Enabled 0: Single SPI (SPI 1-1-1) Enabled 0000: 0 Cycles - Default CR2[3] MLATS[3] 0 CR2[2] MLATS[2] 0 CR2[1] MLATS[1] 0 0001: 1 Cycle 0010: 2 Cycles 0011: 3 Cycles 0100: 4 Cycles 0101: 5 Cycles 0110: 6 Cycles Memory Array Read Latency Selection 1 0111: 7 Cycles R/W 1000: 8 Cycles 1001: 9 Cycle 1010: 10 Cycles CR2[0] MLATS[0] 0 1011: 11 Cycles 1100: 12 Cycles 1101: 13 Cycles 1110: 14 Cycles 1111: 15 Cycles Notes: 1: Latency is frequency dependent. Please consult Table 22 and Table 23. 2: These interface options can only be set through instructions. Feb.25.21 Page 21 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Table 22: Memory Array Read Latency Cycles vs. Maximum Clock Frequency (with XIP) Read Type (1-1-1) SDR (1-1-1) DDR (1-1-2) SDR (1-2-2) SDR (2-2-2) SDR (2-2-2) DDR (1-1-4) SDR (1-4-4) SDR (1-4-4) DDR Latency 8-15 12-15 (4-4-4) SDR (4-4-4) DDR Max Frequency Mxxxx2x108xx Mxxxx2x054xx 108MHz 54MHz 54MHz 27MHz 108MHz 54MHz 108MHz 54MHz 108MHz 54MHz 54MHz 27MHz 108MHz 54MHz 108MHz 54MHz 54MHz 27MHz 108MHz 54MHz 54MHz 27MHz Table 23: Memory Read Latency Cycles vs. Maximum Clock Frequency (without XIP) Read Type Latency (1-1-1) SDR 0 Max Frequency Mxxxx2x108xx Mxxxx2x054xx 50MHz 40MHz Table 24: Augmented Storage Array Read Latency Cycles vs. Maximum Clock Frequency Read Type Latency (1-1-1) SDR 8-15 Max Frequency Mxxxx2x108xx Mxxxx2x054xx 50MHz 40MHz Table 25: Read Any Register Command Latency Cycles vs. Maximum Clock Frequency Feb.25.21 Read Type Max Frequency Latency Cycles (1-1-1) SDR (2-2-2) SDR (4-4-4) SDR 108MHz 108MHz 108MHz 8 4 2 Page 22 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 12.8 Configuration Register 3 (Read/Write) Configuration Register 3 controls the output driver strength along with read data wrap selection. Table 26: Configuration Register 3 – Read and Write Read Default Selection Bits Name Description / Options Write 1.8V 3.0V CR3[7] ODSEL[2] CR3[6] ODSEL[1] CR3[5] ODSEL[0] CR3[4] WRAPS CR3[3] RSVD CR3[2] WRPLS[2] CR3[1] WRPLS[1] CR3[0] WRPLS[0] Output Driver Strength Selector Read WRAP Enable / Disable (16/32/64/128/256 Byte) R/W 0 0 0 1 0 1 1.8V 45Ω1 120Ω 90Ω 70Ω 45Ω 60Ω 30Ω 20Ω 3.0V 35Ω 75Ω 60Ω 45Ω1 35Ω 40Ω 20Ω 15Ω R/W 0 1: Read Data Wrap Enabled 0: Read Data Wrap Disabled R 0 Reserved for future use Reserved 0 Wrap Length Selector2 000: 001: 010: 011: 100: 101: 110: 111: R/W 0 0 000: 16-byte Boundary 001: 32-byte Boundary 010: 64-byte Boundary 011: 128-byte Boundary 100: 256-byte Boundary 101: Reserved 110: Reserved 111: Reserved Notes: 1: Default Setting (VCC dependent). 2: If Wrap is enabled, the read data wraps within an aligned 16/32/64/128/256-byte boundary at any address. The starting address entered selects the group of bytes and the first data returned is the addressed byte. Bytes are then read sequentially until the end of the group boundary is reached. If read continues, the address wraps to the beginning of the group and continues to read sequentially. 12.9 Configuration Register 4 (Read/Write) Configuration Register 4 controls Write Enable protection (WREN – Status Register) reset functionality during memory array writing1. This functionality makes SPI MRAM compatible to other SPI devices. Table 27: Configuration Register 4 – Read and Write Read Default Selection Bits Name Description / State Options Write Reserved for future use CR4[7] RSVD Reserved 0 Reserved for future use CR4[6] RSVD Reserved 0 Reserved for future use CR4[5] RSVD Reserved 0 Reserved for future use CR4[4] RSVD Reserved 0 Reserved for future use CR4[3] RSVD Reserved 0 Reserved2 CR4[2] RSVD Reserved 1 00: Normal: WREN is prerequisite to all Memory Array R/W WREN Reset Write instruction. (WREN is reset after CS# goes High) Selector CR4[1] WRENS[1] 0 01: SRAM: WREN is not a prerequisite to Memory Array CR4[0] WRENS[0] (Memory & Augmented Storage Array Write Functionality) 1 Write instruction (WREN is ignored) 10: Back-to-Back: WREN is prerequisite to only the first Memory Array Write instruction. WREN disable instruction must be executed to reset WREN. (WREN does not reset once CS# goes High) 11: Illegal - Reserved for future use Notes: 1: Write Enable protection (WREN – Status Register) for Registers is maintained irrespective of the Configuration Register 4 settings. In other words, all register write instructions require WREN to be set and WREN resets once CS# goes High for the write instruction. 2: Must be set to “1”. Writing a “0” to this bit may impact device functionality. Feb.25.21 Page 23 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 13. Instruction Set Prerequisite Max. Frequency Data Bytes Latency Cycles DDR SDR XIP (4-4-4) (4-0-4) (4-0-0) (1-4-4) (1-1-4) (2-2-2) (2-0-2) (2-0-0) (1-2-2) (1-1-2) (1-1-1) (1-0-1) (1-0-0) Instruction Name # Command (Opcode) Table 28: Instruction Set Control Instructions 1 No Operation NOOP 00h • • • • 108 MHz 2 Write Enable WREN 06h • • • • 108 MHz 3 Write Disable WRDI 04h • • • • 108 MHz 4 Enable DPI DPIE 37h • • • 108 MHz 5 Enable QPI QPIE 38h • • 108 MHz 6 Enable SPI SPIE FFh 7 Enter Deep Power Down DPDE B9h 8 Enter Hibernate 9 • • • • 108 MHz • • • • 108 MHz HBNE BAh • • • • 108 MHz Software Reset Enable SRTE 66h • • • • 108 MHz 10 Software Reset SRST 99h • • • • 108 MHz 11 Exit Deep Power Down DPDX ABh • • • • 108 MHz SRTE Read Register Instructions 12 Read Status Register RDSR 05h • • • • 1 54 MHz 13 Read Configuration Register 1 RDC1 35h • • • • 1 54 MHz 14 Read Configuration Register 2 RDC2 3Fh • • • • 1 54 MHz 15 Read Configuration Register 3 RDC3 44h • • • • 1 54 MHz 16 Read Configuration Register 4 RDC4 45h • • • • 1 54 MHz 17 Read Configuration Register 1, 2, 3, 4 RDCX 46h • • • • 4 54 MHz 18 Read Device ID RDID 9Fh • • • • 4 54 MHz 19 Read Unique ID RUID 4Ch • • • • 8 54 MHz Feb.25.21 Page 24 22 Read Any Register - Address Based RDAR 65h 1 to 8 108 MHz 23 Write Status Register WRSR 01h • • • • 1 108 MHz WREN 24 Write Configuration Registers 1, 2, 3, 4 WRCX 87h • • • • 4 108 MHz WREN 25 Write Serial Number Register WRSN C2h • • • • 8 108 MHz WREN 26 Write Augmented Array Protection Register WRAP 1Ah • • • • 1 108 MHz WREN 27 Write Any Register - Address Based WRAR 71h • 1 to 8 108 MHz WREN • 1 to ∞ 50 MHz • 1 to ∞ 108 MHz • 1 to ∞ 54 MHz • • • • • Prerequisite Max. Frequency 54 MHz Latency Cycles 1 DDR • SDR • XIP • (4-4-4) • (4-0-4) RDAP 14h (4-0-0) Read Augmented Array Protection Register (1-4-4) 21 (1-1-4) 54 MHz (2-2-2) 8 (2-0-2) • (2-0-0) • (1-2-2) • (1-1-2) • (1-1-1) RDSN C3h (1-0-1) Read Serial Number Register (1-0-0) 20 Instruction Name # Command (Opcode) Data Bytes M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Write Register Instructions • • • Read Memory Array Instructions 28 Read Memory Array - SDR READ 03h • 29 Fast Read Memory Array - SDR RDFT 0Bh • • • • 30 Fast Read Memory Array - DDR DRFR 0Dh • • • • 31 Read Dual Output Memory Array - SDR RDDO 3Bh 32 Read Quad Output Memory Array - SDR RDQO 6Bh 33 Read Dual I/O Memory Read SDR RDDI BBh 34 Read Dual I/O Memory Read DDR DRDI BDh 35 Read Quad I/O Memory Read SDR RDQI EBh • • 36 Read Quad I/O Memory Read DDR DRQI EDh • • • • • • • 1 to ∞ 108 MHz • • • 1 to ∞ 108 MHz • • • • 1 to ∞ 108 MHz • • • 1 to ∞ 54 MHz • 1 to ∞ 108 MHz • 1 to ∞ 54 MHz • 1 to ∞ 108 MHz WREN • 1 to ∞ 108 MHz WREN 1 to ∞ 54 MHz WREN • • • • • Write Memory Array Instructions 37 Write Memory Array - SDR WRTE 02h • 38 Fast Write Memory Array - SDR WRFT DAh • • • • 39 Fast Write Memory Array DDR DRFW DEh • • • • Feb.25.21 • Page 25 Prerequisite DWQO D1h Max. Frequency Write Quad I/O Memory Array DDR Data Bytes 45 • • 1 to ∞ 108 MHz WREN • • 1 to ∞ 54 MHz WREN Latency Cycles WQIO D2h • DDR Write Quad I/O Memory Array SDR SDR 44 XIP WDIO A1h WREN (4-4-4) Write Dual I/O Memory Array SDR 108 MHz (4-0-4) 43 1 to ∞ • (4-0-0) DWQI 31h • (1-4-4) Write Quad Input Memory Array - DDR • (1-1-4) 42 (2-2-2) WQDI 32h (2-0-2) Write Quad Input Memory Array - SDR (2-0-0) 41 (1-2-2) WDUI A2h (1-1-2) Write Dual Input Memory Array - SDR (1-1-1) 40 (1-0-1) Instruction Name (1-0-0) # Command (Opcode) M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 • • • 1 to ∞ 108 MHz WREN • • • 1 to ∞ 108 MHz WREN • • 1 to ∞ 54 MHz WREN 1 to 256 50 MHz 1 to ∞ 108 MHz • • Augmented Storage Array Instructions 46 Read Augmented Storage Array - SDR RDAS 4Bh • • 47 Write Augmented Storage Array - SDR WRAS 42h • • • WREN Notes: 1: A typical SPI instruction consists of command, address and data components. The bus width to transmit these three components varies based on the SPI interface mode selected. To accurately represent the number of I/Os used to transmit these three components, a nomenclature (command-addressdata) is adopted and used throughout this document. Integers placed in the (command-address-data) fields represent the number of I/Os used to transmit the particular component. As an example, 1-1-1 means command, address and data are transmitted on a single I/O (SI / IO[0] or SO / IO[1]). On the other hand, 1-4-4 represents command being sent on a single I/O (SI / IO[0]) and address/data being sent on four I/Os (IO[3:0]). 2: XIP allows completing a series of read and write instructions without having to individually load the read or write command for each instruction. A special mode byte must be entered after the address bits to enable/disable XIP – Axh / Fxh. 3: Read instruction must include Latency cycles to meet higher frequency. They are configurable (Configuration Register 2 – CR2[3:0]) and frequency dependent. 4: The augmented storage array is 256-Bytes in size. The address bits ADDR[23:8] must be Logic ‘0’ for this instruction. 5: Registers do not wrap data during reads. Reading beyond the specified number of bytes will yield indeterminate data. 6: WREN prerequisite for array writing is configurable (Configuration Register 4 – CR4[1:0]). 7: For the Exit Deep Power Down command, the maximum frequency is 108MHz for 1-1-1 operation and 36MHz for 2-2-2 and 4-4-4 operations. Feb.25.21 Page 26 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 14. Instruction Description and Structures All communication between a host and Mxxxx204 is in the form of instructions. Instructions define the operation that must be executed. Instructions consist of a command followed by an optional address modifier and data transfer to or from Mxxxx204. All command, address and data information is transferred sequentially. Instructions are structured as follows: • Each instruction begins with CS# going Low (logic ‘0’) and ends with CS# returning High (Logic’1’). • CLK marks the transfer of each bit. • Each instructions starts out with an 8-bit command. The command selects the type of operation Mxxxx204 must perform. The command is transferred on the rising edges of CLK. • The command can be stand alone or followed by address to select a memory location or register. The address is always 24-bits wide.  SDR: The address is transferred on the rising edges of CLK.  DDR: The address is transferred on both edges of the CLK in DDR. • The address bits are followed by data bits. For Write instructions:  SDR: Write data bits to Mxxxx204 are transferred on the rising edges of CLK.  DDR: Write data bits to Mxxxx204 are transferred on both edges of CLK. • In normal operational mode, Write instructions must be preceded by the WREN instruction. WREN instruction sets the WREN bit in the Status register. WREN bit is reset at the end of every Write instruction. WREN bit can also be reset by executing the WRDI instruction. Mxxxx204 offers two other modes, namely SRAM and Back-to-Back Write where WREN does not get reset after a write instruction to the memory array or the augmented storage array. These modes are set in Configuration Register 4. • Similar to write instructions, the address bits are followed by data bits for read instructions:  SDR: Read data bits from Mxxxx204 are transferred on the falling edges of CLK.  DDR: Read data bits from Mxxxx204 are transferred on both edges of CLK. The start of read data transfer is always on the falling edge of the CLK. • Mxxxx204 is a high performance serial memory and at higher frequencies, read instructions require latency cycles to compensate for the memory array access time. The number of latency cycles required depends on the operational frequency and is configurable – Configuration Register 2. The latency cycles are inserted after the address bits before the data comes out of Mxxxx204. • For Read and Write instructions, Mxxxx204 offers XIP mode. XIP allows similar instructions to be executed sequentially without incurring the command cycles overhead. XIP is enabled by entering byte Axh and disabled by entering byte Fxh. These respective bytes must be entered following the address bits. • For Read instructions, Mxxxx204 offers wrap mode. Wrap bursts are confined to address aligned 16/32/64/128/256 byte boundary. The read address can start anywhere within the wrap boundary. 16/32/64/128/256 wrap configuration is set in Configuration Register 3. • The entire memory array can be read from or written to using a single read or write instruction. After the staring address is entered, subsequent address are internally incremented as long as CS# is Low and CLK continues to cycle. • All commands, address and data are shifted with the most significant bit first. Feb.25.21 Page 27 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Figure 8 to Figure 24 show the description of SDR instruction types supported. Figure 8: Description of (1-0-0) Instruction Type 1 Byte CS# 3 0 CLK Command SI / IO[0] 7 6 5 4 3 2 1 0 Figure 9: Description of (1-0-1) Instruction Type 1 Byte 1 to 8 Bytes CS# 3 0 CLK Command SI / IO[0] 7 6 5 4 3 Input Data 2 1 0 7 6 5 4 2 1 0 Read/Write Output Data SO / IO[1] 7 6 5 4 2 1 0 Figure 10: Description of (1-1-1) Instruction Type (Without XIP) 1 Byte 1 to ∞ Bytes 3 Bytes CS# CLK 3 0 Command SI / IO[0] 7 6 5 4 3 2 Address 1 0 7 6 5 4 Input Data 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 4 2 1 0 Read/Write Output Data SO / IO[1] 7 6 5 4 2 1 0 7 6 5 Figure 11: Description of (1-1-1) Augmented Storage Instruction Type 1 Byte 8-15 Latency Cycles 3 Bytes CS# CLK 3 0 Command SI / IO[0] 7 6 5 4 3 2 Address 1 0 7 6 5 4 Input Data 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 4 2 1 0 Read/Write Output Data SO / IO[1] Feb.25.21 7 6 5 Page 28 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Figure 12: Description of (1-1-1) Instruction Type (With XIP) 1 Byte XIP (Axh, Fxh) (Enable, Disable) 3 Bytes 8 to 15 Latency Cycles 1 to ∞ Bytes CS# CLK 3 0 Command SI / IO[0] 7 6 5 4 3 2 Address 1 0 7 6 5 XIP 4 2 1 0 7 6 5 4 Input Data 3 2 1 0 7 6 5 4 1 2 0 7 6 5 4 2 1 0 Read/Write Output Data SO / IO[1] 7 6 5 4 2 1 0 Figure 13: Description of (1-1-2) Instruction Type (With XIP) 1 Byte XIP (Axh, Fxh) (Enable, Disable) 3 Bytes 1 to ∞ Bytes 8 to 15 Latency Cycles (Read) CS# CLK 3 0 Command IO[0] 7 6 5 4 3 Address 2 1 0 7 6 5 4 Output Data XIP 2 1 0 7 6 5 4 3 2 1 0 6 4 0 6 4 0 7 5 1 7 5 1 Read IO[1] 1 to ∞ Bytes (Write) 6 4 0 6 4 0 6 4 0 Input Data 7 5 1 7 6 4 0 Write Input Data 5 1 7 5 1 7 5 1 Figure 14: Description of (1-2-2) Instruction Type (With XIP) 1 Byte 3 Bytes 1 to ∞ Bytes 8 to 15 Latency Cycles XIP (A xh, Fxh) (E nabl e, Disable) (Read) CS# CLK 3 0 Command IO[0] 7 6 5 4 3 2 Address 1 0 XIP 6 4 0 4 2 0 6 4 2 0 6 4 7 5 1 5 3 1 7 5 3 1 7 5 0 6 4 0 Read Output Data IO[1] 1 7 5 1 1 to ∞ Bytes (Write) 6 4 0 6 4 0 6 4 0 6 4 0 7 5 1 7 5 1 7 5 1 7 5 1 Write Feb.25.21 Page 29 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Figure 15: Description of (2-0-0) Instruction Type B yt e CS# 3 0 CLK Comm and IO[0] 6 4 2 0 IO[1] 7 5 3 1 Figure 16: Description of (2-0-2) Instruction Type 1 to 8 Bytes (Read) B yt e CS# CLK 3 0 Comm and IO[0] 6 4 2 0 6 4 0 6 4 2 0 3 1 Read Output Data IO[1] 7 5 3 1 7 5 1 7 5 Figure 17: Description of (2-2-2) Any Register Instruction Type 4 Latency Cycles 3 Bytes B yt e CS# CLK 3 0 Address Comm and IO[0] 6 4 2 0 6 4 0 4 2 0 6 4 0 6 4 0 6 4 0 Read Output Data IO[1] 7 5 3 1 7 5 1 5 3 1 7 5 1 7 5 1 7 5 1 1 to 8 Bytes (Write) 6 4 0 6 4 0 6 4 0 6 4 0 7 5 1 7 5 1 7 5 1 7 5 1 Write Feb.25.21 Page 30 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Figure 18: Description of (2-2-2) Instruction Type (With XIP) 3 Bytes B yt e 1 to ∞ Bytes 8 to 15 Latency Cycles XIP (A xh, Fx h) (E nabl e, Dis able) (Read) CS# CLK 3 0 Address Comm and IO[0] 6 4 2 0 6 4 0 XIP 4 2 0 6 4 2 0 6 4 0 6 4 0 Read Output Data IO[1] 7 5 3 1 7 5 1 5 3 1 7 5 3 1 5 7 1 7 5 1 1 to ∞ Bytes (Write) 6 4 0 6 4 0 6 4 0 6 4 0 7 5 1 7 5 1 7 5 1 7 5 1 Write Figure 19: Description of (1-1-4) Instruction Type (With XIP) 1 Byte XIP (Axh, Fxh) (Enable, Disable) 3 Bytes 1 to ∞ Bytes 8 to 15 Latency Cycles (Read) CS# CLK 3 0 Command IO[0] 7 6 5 4 3 2 Address 1 0 7 6 5 4 Output Data XIP 2 1 0 7 6 5 4 3 2 1 0 4 0 4 0 4 0 IO[1] 5 1 5 1 5 1 IO[2] 6 2 6 2 6 2 7 3 7 3 7 3 Read IO[3] 1 to ∞ Bytes (Write) 4 0 4 0 4 0 4 0 Input Data 4 0 4 0 Input Data 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 Write Feb.25.21 Page 31 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Figure 20: Description of (1-4-4) Instruction Type (With XIP) 1 Byte XIP (Axh, Fxh) (Enable, Disable) 3 Bytes 1 to ∞ Bytes 8 to 15 Latency Cycles (Read) CS# CLK 3 0 Command IO[0] 7 6 5 4 3 2 Address 1 0 XI P Output Dat a 4 0 4 0 4 0 4 0 4 0 4 0 4 0 IO[1] 5 1 5 1 5 1 5 1 5 1 5 1 5 1 IO[2] 6 3 6 2 6 2 6 2 6 2 6 2 6 2 IO[3] 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Read 1 to ∞ Bytes (Wr ite) 4 0 4 0 4 0 4 0 Input Data 4 0 4 0 Input Data 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 Write Figure 21: Description of (4-0-0) Instruction Type 1 Byte CS# CLK 3 0 Command Feb.25.21 IO[0] 4 0 IO[1] 5 1 IO[2] 6 2 IO[3] 7 3 Page 32 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Figure 22: Description of (4-0-4) Instruction Type 1 Byte 1 to 8 Bytes (Read) CS# 3 0 CLK Command Output Data IO[0] 4 0 4 0 4 0 4 0 IO[1] 5 1 5 1 5 1 5 1 IO[2] 6 2 6 2 6 2 6 2 IO[3] 7 3 7 3 7 3 7 3 Read Figure 23: Description of (4-4-4) Any Register Instruction Type (Without XIP) 1 Byte 2 Latency Cycles 3 Bytes CS# CLK 3 0 Comman d Address Output Data IO[0] 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 IO[1] 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 IO[2] 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 IO[3] 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 4 0 Read 1 to 8 Bytes (Write) 4 0 4 0 4 0 4 0 Input Data 4 0 Input Data 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 Write Feb.25.21 Page 33 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Figure 24: Description of (4-4-4) Instruction Type (With XIP) 1 Byte XIP (Axh, Fxh) (Enable, Disable) 3 Bytes 1 to ∞ Bytes 8 to 15 Latency Cycles (Read) CS# CLK 3 0 Command Address XIP Output Data IO[0] 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 IO[1] 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 IO[2] 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 IO[3] 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 Read 1 to ∞ Bytes (Write) 4 0 5 1 4 0 4 0 4 0 5 1 5 1 Input Data 5 1 4 0 4 0 5 1 Input Data 5 1 Write Feb.25.21 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 Page 34 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Figure 25 to Figure 29 show the description of DDR instruction types supported. Figure 25: Description of (1-1-1) DDR Instruction Type (With XIP) 1 Byte XIP (Axh, Fxh) (Enable, Disable) 3 Bytes 8 to 15 Latency Cycles 1 to ∞ Bytes CS# CLK 0 Command SI / IO[0] 7 6 5 4 Address 3 2 1 0 7 6 5 4 XI P 2 1 0 7 6 5 4 Input Data 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 2 1 0 Read/Write Output Dat a SO / IO[1] 7 6 5 4 2 1 0 Figure 26: Description of (2-2-2) DDR Instruction Type (With XIP) 1 Byte 3 Bytes Comm and Address 1 to ∞ Bytes 8 to 15 Latency Cycles XIP (A xh, Fxh) (E nabl e, Disable) (Read) CS# CLK IO[0] 6 4 2 0 6 4 1 6 XIP 4 0 6 4 2 0 6 4 0 6 4 2 0 Read Output Data IO[1] 7 5 3 1 7 5 0 7 5 1 7 5 3 1 7 5 1 7 5 3 1 1 to ∞ Bytes (Write) 6 4 0 6 4 2 0 6 4 0 6 4 2 0 7 5 1 7 5 3 1 7 5 1 7 5 3 1 Write Feb.25.21 Page 35 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Figure 27: Description of (4-4-4) DDR Instruction Type (With XIP) XIP (Axh, Fxh) (Enable, Disable) 3 Bytes 1 to ∞ Bytes 8 to 15 Latency Cycles (Read) CS# CLK Command Address XIP Output Data IO[0] 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 IO[1] 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 Read IO[2] 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 IO[3] 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 1 to ∞ Bytes (Write) 4 0 4 0 4 0 4 0 Input Data 4 0 4 0 Input Data 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 Write Figure 28: Description of (1-2-2) DDR Instruction Type (With XIP) 3 Bytes 1 to ∞ Bytes 8 to 15 Latency Cycles XIP (A xh, Fx h) (E nabl e, Dis able) (Read) CS# CLK Command IO[0] 7 6 5 4 3 Address 2 1 0 XIP 6 4 2 0 4 2 0 6 4 2 0 6 4 7 5 3 1 5 3 1 7 5 3 1 7 5 2 0 6 4 2 0 3 1 Read Output Data IO[1] 3 1 7 5 1 to ∞ Bytes (Write) 6 4 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 1 7 5 3 1 7 5 3 1 7 5 3 1 Write Feb.25.21 Page 36 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Figure 29: Description of (1-4-4) DDR Instruction Type (With XIP) XIP (Axh, Fxh) (Enable, Disable) 3 Bytes 1 to ∞ Bytes 8 to 15 Latency Cycles (Read) CS# CLK Command IO[0] 7 6 Address XIP Output Data 4 0 4 0 4 0 4 0 4 0 4 0 4 0 IO[1] 5 1 5 1 5 1 5 1 5 1 5 1 5 1 IO[2] 6 2 6 2 6 2 6 2 6 2 6 2 6 2 IO[3] 7 3 7 3 7 3 7 3 7 3 7 3 7 3 5 4 3 2 1 0 Read 1 to ∞ Bytes (Write) 4 0 4 5 1 5 6 2 7 3 0 4 0 4 0 1 5 1 5 1 5 6 2 6 2 6 2 7 3 7 3 7 3 Input Data 4 0 4 0 1 5 1 6 2 6 2 7 3 7 3 Input Data Write Feb.25.21 Page 37 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 15. Electrical Specifications Table 29: Recommended Operating Conditions Parameter / Condition Operating Temperature Minimum Typical Maximum Units Industrial -40.0 - 85.0 °C Industrial Plus -40.0 - 105.0 °C VCC Supply Voltage (3.0V) 3.0V 2.7 3.0 3.6 V VCC Supply Voltage (1.8V) 1.8V 1.71 1.8 2.0 V 0.0 0.0 0.0 V VSS Supply Voltage Table 30: Pin Capacitance Parameter Test Conditions Symbol Maximum Units Input Pin Capacitance TEMP = 25°C; f = 1 MHz; VIN = 3.0V CIN 5.0 pF Output Pin Capacitance TEMP = 25°C; f = 1 MHz; VIN = 3.0V CINOUT 6.0 pF Table 31: Endurance & Retention Symbol Test Conditions Parameter Write Endurance END Data Retention Minimum Units - 1014 cycles 105°C 10 85°C 1,000 75°C 10,000 65°C 1,000,000 RET years Table 32: 3.0V DC Characteristics 3.0V Device (2.7V-3.6V) Parameter Symbol Read Current (1-1-1) SDR IREAD1 Read Current (2-2-2) SDR IREAD2 Read Current (4-4-4) SDR IREAD3 Read Current (1-1-1) SDR IREAD4 Read Current (2-2-2) SDR IREAD5 Read Current (4-4-4) SDR IREAD6 Read Current (1-1-1) DDR IREAD7 Read Current (2-2-2) DDR IREAD8 Read Current (4-4-4) DDR IREAD9 Write Current (1-1-1) SDR IWRITE1 Write Current (2-2-2) SDR IWRITE2 Write Current (4-4-4) SDR IWRITE3 Feb.25.21 Test Conditions VCC = 3.6V, IOUT=0mA, CLK=54MHz (VIL / VIH), CS#= VIL, SI= VIL or VIH VCC = 3.6V, IOUT=0mA, CLK=108MHz (VIL / VIH), CS#= VIL, SI= VIL or VIH VCC = 3.6V, IOUT=0mA, CLK=54MHz (VIL / VIH), CS#= VIL, SI= VIL or VIH VCC = 3.6V, IOUT=0mA, CLK=54MHz (VIL / VIH), CS#= VIL, SI= VIL or VIH Minimum Typical Maximum Units - 8 9 mA - 9 10 mA - 10 12 mA - 13 15 mA - 15 17 mA - 19 21 mA - 13 18 mA - 20 24 mA - 23 28 mA - 14 16 mA - 17 20 mA - 22 25 mA Page 38 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 3.0V Device (2.7V-3.6V) Parameter Symbol Write Current (1-1-1) SDR IWRITE4 Write Current (2-2-2) SDR IWRITE5 Write Current (4-4-4) SDR IWRITE6 Write Current (1-1-1) DDR IWRITE7 Write Current (2-2-2) DDR IWRITE8 Write Current (4-4-4) DDR IWRITE9 Standby Current ISB Test Conditions Minimum Typical Maximum Units - 22 28 mA - 25 32 mA - 38 45 mA - 15 25 mA - 20 30 mA - 30 45 mA Ta = 25⁰C - 160 - µA Ta = 85⁰C - - 400 µA Ta =105⁰C - - 600 µA VCC = 3.6V, IOUT=0mA, CLK=108MHz (VIL / VIH), CS#= VIL, SI= VIL or VIH VCC = 3.6V, IOUT=0mA, CLK=54MHz (VIL / VIH), CS#= VIL, SI= VIL or VIH VCC = 3.6V, CLK=VCC, CS#=VCC, SI=VCC Deep Power Down Current IDPD VCC = 3.6V, CLK=VCC, CS#=VCC, SI=VCC - 5 25 µA Hibernate Current IHBN VCC = 3.6V, CLK=VCC, CS#=VCC, SI=VCC - 0.1 - µA Input Leakage Current ILI VIN=0 to VCC (max) - - ±1.0 µA Output Leakage Current ILO VOUT=0 to VCC (max) - - ±1.0 µA Input High Voltage VIH 0.7xVCC - VCC+0.3 V Input Low Voltage VIL -0.3 - 0.3xVCC V Output High Voltage Level VOH IOH = -100µA VCC-0.2 - - V IOH = -1mA 2.4 - - V Output Low Voltage Level VOL IOL = 150µA - - 0.2 V IOL = 2mA - - 0.4 V Table 33: 1.8V DC Characteristics 1.8V Device (1.71V-2.0V) Parameter Symbol Read Current (1-1-1) SDR IREAD1 Read Current (2-2-2) SDR IREAD2 Read Current (4-4-4) SDR IREAD3 Read Current (1-1-1) SDR IREAD4 Read Current (2-2-2) SDR IREAD5 Read Current (4-4-4) SDR IREAD6 Read Current (1-1-1) DDR IREAD7 Read Current (2-2-2) DDR IREAD8 Read Current (4-4-4) DDR IREAD9 Write Current (1-1-1) SDR IWRITE1 Write Current (2-2-2) SDR IWRITE2 Feb.25.21 Test Conditions VCC = 2.0V, IOUT=0mA, CLK=54MHz (VIL / VIH), CS#= VIL, SI= VIL or VIH VCC = 2.0V, IOUT=0mA, CLK=108MHz (VIL / VIH), CS#= VIL, SI= VIL or VIH VCC = 2.0V, IOUT=0mA, CLK=54MHz (VIL / VIH), CS#= VIL, SI= VIL or VIH VCC = 2.0V, IOUT=0mA, CLK=54MHz (VIL / VIH), Minimum Typical Maximum Units - 5 8 mA - 6 9 mA - 7 11 mA - 8 12 mA - 9 13 mA - 12 17 mA - 11 14 mA - 17 20 mA - 21 25 mA - 13 15 mA - 16 19 mA Page 39 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 1.8V Device (1.71V-2.0V) Parameter Symbol Write Current (4-4-4) SDR IWRITE3 Write Current (1-1-1) SDR IWRITE4 Write Current (2-2-2) SDR IWRITE5 Write Current (4-4-4) SDR IWRITE6 Write Current (1-1-1) DDR IWRITE7 Write Current (2-2-2) DDR IWRITE8 Write Current (4-4-4) DDR IWRITE9 Standby Current ISB Test Conditions Minimum Typical Maximum Units - 20 23 mA - 20 26 mA - 23 30 mA - 36 43 mA - 13 23 mA - 19 28 mA - 28 43 mA Ta = 25⁰C - 140 - µA Ta = 85⁰C - - 350 µA Ta=105⁰C - - 500 µA CS#= VIL, SI= VIL or VIH VCC = 2.0V, IOUT=0mA, CLK=108MHz (VIL / VIH), CS#= VIL, SI= VIL or VIH VCC = 2.0V, IOUT=0mA, CLK=54MHz (VIL / VIH), CS#= VIL, SI= VIL or VIH VCC = 2.0V, CLK=VCC, CS#=VCC, SI=VCC Deep Power Down Current IDPD VCC = 2.0V, CLK=VCC, CS#=VCC, SI=VCC - 4 20 µA Hibernate Current IHBN VCC = 2.0V, CLK=VCC, CS#=VCC, SI=VCC - 0.1 - µA Input Leakage Current ILI VIN=0 to VCC (max) - - ±1.0 µA WP# Leakage Current IWP#LI VIN=0 to VCC (max) -100.0 - +1.0 µA Output Leakage Current ILO VOUT=0 to VCC (max) - - ±1.0 µA Input High Voltage VIH 0.7xVCC - VCC+0.3 V Input Low Voltage VIL -0.3 - 0.3xVCC V Output High Voltage Level VOH IOH = -100µA VCC-0.2 - - V IOH = -1mA 1.5 - - V Output Low Voltage Level VOL IOL = 150µA - - 0.2 V IOL = 2mA - - 0.4 V Feb.25.21 Page 40 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Absolute Maximum Ratings Stresses greater that those listed may cause permanent damage to the device. This is a stress rating only. Exposure to maximum rating for extended periods may adversely affect reliability. Table 34:Absolute Maximum Ratings Parameter Minimum Maximum Units Magnetic Field During Write --- 24000 A/m Magnetic Field During Read --- 24000 A/m Junction Temperature --- 125 °C Storage Temperature -55 to 150 °C ESD HBM (Human Body Model) ANSI/ESDA/JEDEC JS-001-2017 ≥ |2000 V| V ESD CDM (Charged Device Model) ANSI/ESDA/JEDEC JS-002-2018 ≥ |500 V| V ≥ |100 mA| mA Passed --- Latch-Up (I-test) JESD78 Latch-Up (Vsupply over-voltage test) JESD78 Table 35: AC Test Conditions Parameter Input pulse levels Value 0.0V to VCC Input rise and fall times 3.0ns Input and output measurement timing levels VCC/2 Output Load Feb.25.21 CL = 30.0pF Page 41 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 15.1 CS# Operation & Timing Figure 30: CS# Operation & Timing CS# tCS tCSS tCSH CLK tCSS Table 36: CS# Operation Symbol Clock Frequency fCLK Clock Low Time tCL Clock High Time tCH Chip Deselect Time after Read Cycle tCS1 Chip Deselect Time after Register Write Cycle1 tCS2 Chip Deselect Time after Write Cycle (SPI) tCS3 Chip Deselect Time after Write Cycle (DPI) tCS4 Chip Deselect Time after Write Cycle (QPI) tCS5 CS# Setup Time (w.r.t CLK) tCSS CS# Hold Time (w.r.t CLK) tCSH Parameter Minimum 1 0.45 * 1/ fCLK 0.45 * 1/ fCLK 20 5 280 350 490² 5 4 Maximum 108 (SDR) - Units MHz ns ns ns µs ns ns ns ns ns Notes: Power supplies must be stable 1:SDR operation only 2:For single byte operations, tCS5 is 280ns Feb.25.21 Page 42 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Command, Address, XIP and Data Input Operation & Timing Figure 31: SDR Command, Address and Data Input Operation & Timing CS# tCSS CLK tSU tHD New Data SI Don’t Care Table 37: SDR Command, Address, XIP, and Data Input Operation & Timing Parameter Symbol Minimum Maximum Data Setup Time (w.r.t CLK) tSU 2.0 Data Hold Time (w.r.t CLK) tHD 3.0 - Units ns ns Notes: Power supplies must be stable Figure 32: DDR Command, Address and Data Input Operation & Timing CS# tCSS CLK tSU SI tHD New Data 1 tSU tHD New Data 2 Don’t Care Table 38: DDR Command, Address, XIP, and Data Input Operation & Timing Parameter Symbol Minimum Maximum Data Setup Time (w.r.t CLK) tSU 4.0 Data Hold Time (w.r.t CLK) tHD 4.0 - Units ns ns Notes: Power supplies must be stable Feb.25.21 Page 43 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 15.2 Data Output Operation & Timing Figure 33: SDR Data Output Operation & Timing CS# tCSS tCSH CLK tOH tCO SO High-Z tHZ CS New Data 1 New Data 2 tCLZ Don’t Care Table 39: SDR Data Output Operation & Timing Parameter Symbol Minimum CLK Low to Output Low Z (Active) tCLZ 0 Output Valid (w.r.t CLK) tCO Output Hold Time (w.r.t CLK) tOH 1.0 Output Disable Time (w.r.t CS#) tHZCS - Maximum 7.0 7.0 Units ns ns ns ns Notes: Power supplies must be stable Figure 34: DDR Data Output Operation & Timing CS# tCSS CLK SO High-Z tOH tOH tCO New Data 1 New Data 2 tHZ CS New Data 3 tCLZ Table 40: DDR Data Output Operation & Timing Parameter Symbol Minimum CLK Low to Output Low Z (Active) tCLZ 0 Output Valid (w.r.t CLK) tCO Output Hold Time (w.r.t CLK) tOH 1.0 Output Disable Time (w.r.t CS#) tHZCS - Don’t Care Maximum 7.0 6.0 Units ns ns ns ns Notes: Power supplies must be stable Feb.25.21 Page 44 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 15.3 WP# Operation & Timing Figure 35: WP# Operation & Timing CS# WP# tWPHD tWPSU Table 41: WP# Operation & Timing Symbol Minimum tWPSU 20 tWPHD 20 Parameter WP# Setup Time (w.r.t CS#) WP# Hold Time (w.r.t CS#) Maximum - Units ns ns Notes: Power supplies must be stable JEDEC Reset Operation & Timing Figure 36: JEDEC Reset Operation & Timing Device Fully Operational 1 CS# tCSL 2 3 4 tCSH CLK SI Device Reset Parameter CS# Low Time CS# High Time SI Setup Time (w.r.t CS#) SI Hold Time (w.r.t CS#) JEDEC Hardware Reset Software Reset1 Table 42: JEDEC Reset Operation & Timing Symbol Minimum tCL 1.0 tCH 1.0 tSU 5.0 tHD 5.0 tRESET tSRST - Maximum 450.0 50.0 Units µs µs ns ns µs µs Notes: Power supplies must be stable 1: Software Reset timing is for Instruction based Reset (SRST) Feb.25.21 Page 45 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Enter Deep Power Down Command (EDP – B9h) The command sequences are shown below. Executing the Enter Deep Power down (EDP) command is the only way to put the device in the deep power down mode. The device consumption drops to IDP. The deep power down mode subsequently reduces the standby current from ISB to IDP. No other command must be issued while the device is in deep power down mode. To enter the deep power down mode, CS# is driven low, following the enter deep power down (EDPD) command, CS# must be driven high after the eighth bit of the command code has been latched in or the EDP command will not be executed. After CS# is driven high, it requires a delay of tEDPD (Table 6 and 7) before the supply current is reduced to IDP and the Deep Power Down mode is entered. The command can be issued in SPI, DPI or QPI modes. CS# tEDPD 0 1 3 2 4 6 5 7 CLK Command (ABh) SI(I/O0) X 1 1 0 0 1 0 1 MSB X 1 LSB Standby Deep Power Down High Z SO(I/O1) Figure 37: Enter Deep Power Down in SPI Command Sequence CS# tEDPD 0 2 1 3 CLK Command (B9h) SI(I/O0) High Z 0 1 0 1 1 1 LSB SO(I/O1) High Z High Z 1 Standby Mode Deep Power Down Mode High Z 0 MSB Figure 38: Enter Deep Power Down in DPI Command Sequence CS# tEDPD 0 1 CLK Command (B9h) SI(I/O0) High Z 1 High Z 1 LSB SO(I/O1) WP#(I/O2) High Z High Z 1 0 0 0 High Z High Z Standby I/O3 High Z 1 1 Deep Power Down High Z MSB Figure 39: Enter Deep Power Down in QPI Command Sequence Feb.25.21 Page 46 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Exit Deep Power Down Command (EXDPD - ABh) The command sequences are shown below. There are two ways to exit deep power down mode: 1. Toggling CS# with a CS# pulse width of tCSDPD while CLK and I/Os are Don’t Care. During waking up from deep power down, I/Os remain to be in high Z. 2. Driving CS# low follows with the Exit Deep Power Down (EXDPD) command. CS# must be driven high after the eight bit of the command code has been latched in or the EXDPD command will not executed. tEXDPD tCSDPD CS# Standby Deep Power Down CLK High Z I/Os X Figure 41: Exit Deep Power Down by Toggling CS# CS# tEXDPD 0 1 3 2 4 6 5 7 CLK Command (B9h) SI(I/O0) X 1 1 0 1 1 0 MSB 0 X 1 LSB Standby Deep Power Down High Z SO(I/O1) Figure 40: Exit Deep Power Down in SPI Command Sequence It requires a delay of tEXDPD (Table 6 and 7) before the device can fully exit the deep power down mode and enter standby mode. The command can be issued in SPI, DPI, and QPI mode. Status of all non-volatile bits in registers remains unchanged when the SPnvSRAM enters or exits the deep power down mode. CS# CS# tEXDPD 0 tEXDPD 4 6 5 7 CLK Command (ABh) SI(I/O0) Command (ABh) SI(I/O0) High Z 0 0 0 0 1 1 1 0 High Z 1 LSB SO(I/O1) High Z High Z High Z 1 LSB SO(I/O1) 1 CLK High Z 1 1 0 0 High Z Standby Deep Power Down High Z WP#(I/O2) High Z High Z Deep Power Down MSB I/O3 High Z 1 1 Standby High Z MSB Figure 42: Exit Deep Power Down in DPI Command Sequence Feb.25.21 Figure 43: Exit Deep Power Down in QPI Command Sequence Page 47 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 Enter Hibernate Command (EHBN – BAh) The command sequences are shown below. Executing the Enter Hibernate command is the only way to put the device in the hibernate mode. The device drops down to the lowest power consumption mode: IHBN. When in hibernate mode, the CLK and SI pins are ignored and SO will be high-Z. To enter the hibernate mode, CS# is driven low, following the Enter Hibernate (EHBN) command. After CS# is driven high, it requires a delay of tENTHIB time (Table 6 and 7) before the supply current is reduced to IHBN and the hibernate mode is entered. Toggling CS# (low to high) will return the SPnvSRAM to standby mode. The command can be issued in SPI, DPI, and QPI modes. CS# tENTHIB 0 1 3 2 4 6 5 7 0 1 2 CLK tEXHIB Command (BAh) SI(I/O0) X 1 1 0 1 1 0 1 MSB 0 LSB SO(I/O1) Enter Hibernate Hibernate Mode Exit Hibernate High Z Figure 44: Enter Hibernate in SPI Command Sequence CS# tENTHIB 0 2 1 3 CLK Command (BAh) High Z SI(I/O0) 1 0 0 SO(I/O1) High Z 1 1 1 High Z 0 LSB Standby Mode Hibernate Mode High Z 1 MSB Figure 45: Enter Hibernate in DPI Command Sequence CS# tENTHIB 0 1 CLK Command (BAh) SI(I/O0) High Z 1 High Z 0 LSB SO(I/O1) WP#(I/O2) High Z High Z 1 1 0 0 High Z High Z Standby I/O3 High Z 1 1 Hibernate High Z MSB Figure 46: Enter Hibernate in QPI Command Sequence Feb.25.21 Page 48 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 16. Thermal Resistance Table 43: Thermal Resistance Parameter Description Test Conditions θJA Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 θJC 8-pad DFN (WSON) 43.67 8-pin SOIC Unit 53.59 oC/W 18.54 4.29 Notes: 1: These parameters are guaranteed by characterization; not tested in production. Feb.25.21 Page 49 M1004204/M1008204/M1016204 M3004204/M3008204/M3016204 17. Revision History Revision Date Description of Change Apr.16.20 Initial release. Feb.25.21 Update to the Endurance and Electrical parameters. Thermal Resistance table added to the datasheet. Revise various tables including Tables 22, 31, 32, 33, 34, 36 and 43. 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