To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY
M30201 Group User's manual
Keep safety first in your circuit designs!
q
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
q
q
q
q
q
q q
q
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http:// www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon ductor product distributor for further details on these materials or the products con tained therein.
How to Use This Manual
This user's manual is written for the M30201 group. The reader of this manual is expected to have the basic knowledge of electric and logic circuits and microcomputers. This manual is for the use of the models below. • M30201M4-XXXSP/FP • M30201M4T-XXXFP • M30201M6-XXXFP • M30201M6T-XXXFP • M30201F6SP/FP • M30201F6TFP These products have similar features except for the memories, which differ from one product to another. This manual gives descriptions of M30201M4-XXXSP. Memories built-in are as shown below. Be careful when writing a program, as the memories have different capacities. The figure of each register configuration describes its functions, contents at reset, and attributes as follows :
RAM Size (Byte)
2K
M30201F6SP/FP M30201F6TFP M30201M6-XXXFP M30201M6T-XXXFP M30201M4-XXXSP/FP M30201M4T-XXXFP
1K
512
16K
32K
48K
ROM Size (Byte)
This manual comprises of eight chapters. Use the suggested chapters as a reference for the following topics:
• Bit attribute R.....Read O.....Possible to read X.....Impossible to read W.....Write O.....Possible to write X.....Impossible to write Bit attribute
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Address 038216
When reset 00X000002
Bit symbol
TA0OS TA1OS TA2OS TA3OS TA4OS
Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag
Function 1 : Timer start When read, the value is “0”
RW
Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TA0TGL TA0TGH
Timer A0 event/trigger select bit
b7 b6
0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to “0”.
This manual comprises of five chapters. Use the suggested chapters as a reference for the following topics: * To understand hardware specifications ................................................... Chapter 1 Hardware * To understand the basic way of using peripheral features and the operation timing ................................ Chapter 2 Peripheral Functions Usage * To observe applications of peripheral features ........................ Chapter 3 Examples of Peripheral Functions Applications * To understand interrupt timing in detail .................................................... Chapter 4 Interrupts * To understand standard data............................................ Chapter 5 Standard Characteristics This manual includes a quick reference immediately following the Table of Contents, indicate the page of the topic to be pursued. * To find a page describing a specific register by the register address ............................... Quick Reference to Pages Classified by Address
M16C Family-related document list
Usages (Microcomputer development flow)
Type of document
Data sheet and data book User’s manual
Selection of microcomputer
Contents
Hardware specifications (pin assignment, memory map, specifications of peripheral functions, electrical characteristics, timing charts) Detailed description about hardware specifications, operation, and application examples (connection with peripherals, relationship with software) Method for creating programs using assembly and C languages Detailed description about operation of each instruction (assembly language)
Outline design of system Detail design of system Hardware development Software development
Hardware Software
Programming manual Software manual
System evaluation
M16C Family Line-up
M16C Family M16C/80 Series M16C/80 Group
M16C/60 Series
M16C/60 Group M16C/61 Group M16C/62 Group
M16C/20 Series
M16C/20 Group M16C/21 Group M16C/22 Group M16C/24 Group
Table of Contents
Chapter 1 Hardware ________________________________________
Description ............................................................................................................................................2 Memory .................................................................................................................................................9 Central Processing Unit (CPU) ........................................................................................................... 12 Reset ................................................................................................................................................... 15 Software Reset ................................................................................................................................... 17 Clock Generating Circuit ..................................................................................................................... 18 Clock Control ...................................................................................................................................... 19 Clock Output ....................................................................................................................................... 22 Stop Mode ..........................................................................................................................................23 Wait Mode ...........................................................................................................................................23 Power Saving ...................................................................................................................................... 25 Protection ............................................................................................................................................ 27 Interrupt .............................................................................................................................................. 28 Watchdog Timer .................................................................................................................................. 46 Timer ................................................................................................................................................... 48 Timer A ............................................................................................................................................... 49 Timer B ............................................................................................................................................... 59 Timer X ............................................................................................................................................... 65 Serial I/O ............................................................................................................................................. 75 A-D Converter ..................................................................................................................................... 89 Programmable I/O Ports ..................................................................................................................... 99 Usage Precaution ............................................................................................................................. 107 Electrical characteristics ................................................................................................................... 111 Outline Performance (Flash Memory) ............................................................................................... 125 Flash Memory ................................................................................................................................... 126 CPU Rewrite Mode ........................................................................................................................... 127 Parallel I/O Mode .............................................................................................................................. 134 Standard Serial I/O Mode ................................................................................................................. 146
Chapter 2 Peripheral Functions Usage ________________________
2.1 Protect ........................................................................................................................................172 2.1.1 Overview ..............................................................................................................................172 2.1.2 Protect Operation .................................................................................................................172 2.1.3 Precaution for Protect .......................................................................................................... 173 2.2 Timer A ....................................................................................................................................... 174 2.2.1 Overview ..............................................................................................................................174 2.2.2 Operation of Timer A (timer mode) ...................................................................................... 180 2.2.3 Operation of Timer A (timer mode, gate function selected) ................................................. 182 2.2.4 Operation of Timer A (timer mode, pulse output function selected) .................................... 184 2.2.5 Operation of Timer A (event counter mode, reload type selected) ...................................... 186 2.2.6 Operation of Timer A (event counter mode, free run type selected) .................................... 188 2.2.7 Operation of timer A (2-phase pulse signal process in event counter mod normal mode selected) .................................................................................................................................. 190 2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode,multiply-by-4 mode selected) ..............................................................................................................................192 2.2.9 Operation of Timer A (one-shot timer mode) ....................................................................... 194 2.2.10 Operation of Timer A (one-shot timer mode, external trigger selected) ............................. 196 2.2.11 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected) .......... 198 2.2.12 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected) ............ 200 2.2.13 Precautions for Timer A (timer mode) ................................................................................ 202 2.2.14 Precautions for Timer A (event counter mode) .................................................................. 203 2.2.15 Precautions for Timer A (one-shot timer mode) ................................................................. 204 2.2.16 Precautions for Timer A (pulse width modulation mode) ................................................... 205 2.3 Timer B ....................................................................................................................................... 206 2.3.1 Overview ..............................................................................................................................206 2.3.2 Operation of Timer B (timer mode) ...................................................................................... 210 2.3.3 Operation of Timer B (event counter mode) ........................................................................ 212 2.3.4 Operation of Timer B (pulse period measurement mode) ................................................... 214 2.3.5 Operation of Timer B (pulse width measurement mode) ..................................................... 216 2.3.6 Precautions for Timer B (timer mode, event counter mode) ................................................ 218 2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode) ........................... 219 2.4 Timer X ....................................................................................................................................... 220 2.4.1 Overview ..............................................................................................................................220 2.4.2 Operation of Timer X (timer mode) ...................................................................................... 224
2.4.3 Operation of Timer X (timer mode, gate function selected) ................................................. 226 2.4.4 Operation of Timer X (timer mode, pulse output function selected) .................................... 228 2.4.5 Operation of Timer X (event counter mode, reload type selected) ...................................... 230 2.4.6 Operation of Timer X (event counter mode, free run type selected) .................................... 232 2.4.7 Operation of Timer X (one-shot timer mode) ....................................................................... 234 2.4.8 Operation of Timer X (pulse period measurement mode) ................................................... 236 2.4.9 Operation of Timer X (pulse width measurement mode) ..................................................... 238 2.4.10 Operation of Timer X (pulse width modulation mode, 16-bit PWM mode selected) .......... 240 2.4.11 Operation of Timer X (pulse width modulation mode, 8-bit PWM mode selected) ............ 242 2.4.12 Precautions for Timer X (timer mode, event counter mode) .............................................. 244 2.4.13 Precautions for Timer X (one-shot timer mode) ................................................................. 245 2.4.14 Precautions for Timer X (pulse period/pulse width measurement mode) ......................... 246 2.4.15 Precautions for Timer X (pulse width modulation mode) ................................................... 247 2.5 Clock-Synchronous Serial I/O ..................................................................................................... 248 2.5.1 Overview .............................................................................................................................. 248 2.5.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode) ..................... 254 2.5.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected) ........................................................................ 258 2.5.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode) ........................... 262 2.5.5 Precautions for Serial I/O (in clock-synchronous serial I/O) ................................................ 266 2.6 Clock-Asynchronous Serial I/O (UART) ...................................................................................... 268 2.6.1 Overview .............................................................................................................................. 268 2.6.2 Operation of Serial I/O (transmission in UART mode) ......................................................... 276 2.6.3 Operation of Serial I/O (reception in UART mode) .............................................................. 280 2.7 A-D Converter ............................................................................................................................. 284 2.7.1 Overview .............................................................................................................................. 284 2.7.2 Operation of A-D converter (one-shot mode) ...................................................................... 290 2.7.3 Operation of A-D Converter (in repeat mode) ...................................................................... 292 2.7.4 Operation of A-D Converter (in single sweep mode) ........................................................... 294 2.7.5 Operation of A-D Converter (in repeat sweep mode 0) ....................................................... 296 2.7.6 Operation of A-D Converter (in repeat sweep mode 1) ....................................................... 298 2.7. 7 Precautions for A-D Converter ............................................................................................ 300 2.7.8 Method of A-D Conversion (10-bit mode) ............................................................................ 301 2.7.9 Method of A-D Conversion (8-bit mode) .............................................................................. 303 2.7.10 Absolute Accuracy and Differential Non-Linearity Error .................................................... 305
2.7.11 Internal Equivalent Circuit of Analog Input ......................................................................... 307 2.7.12 Sensor’s Output Impedance under A-D Conversion .......................................................... 308 2.8 Watchdog Timer .........................................................................................................................310 2.8.1 Overview .............................................................................................................................. 310 2.8.2 Operation of Watchdog Timer .............................................................................................. 312 2.9 Address Match Interrupt .............................................................................................................314 2.9.1 Overview ..............................................................................................................................314 2.9.2 Operation of Address Match Interrupt .................................................................................. 316 2.10 Key-Input Interrupt .................................................................................................................... 318 2.10.1 Overview ............................................................................................................................ 318 2.10.2 Operation of Key-Input Interrupt ........................................................................................320 2.11 Power Control ........................................................................................................................... 322 2.11.1 Overview ............................................................................................................................ 322 2.11.2 Stop Mode Set-Up .............................................................................................................327 2.11.3 Wait Mode Set-Up .............................................................................................................328 2.11.4 Precautions in Power Control ............................................................................................ 329 2.12 Programmable I/O Ports ...........................................................................................................330 2.12.1 Overview ............................................................................................................................ 330
Chapter 3 Examples of Peripheral functions Applications ________
3.1 Long-Period Timers .................................................................................................................... 338 3.2 Variable-Period Variable-Duty PWM Output ............................................................................... 342 3.3 Delayed One-Shot Output .......................................................................................................... 346 3.4 Buzzer Output ............................................................................................................................. 350 3.5 Solution for External Interrupt Pins Shortage ............................................................................. 352 3.6 Controlling Power Using Stop Mode ........................................................................................... 354 3.7 Controling Power Using Wait Mode ............................................................................................ 358
Chapter 4 Interrupt_________________________________________
4.1 Overview of Interrupt ..................................................................................................................364 4.1.1 Type of Interrupts .................................................................................................................364 4.1.2 Software Interrupts .............................................................................................................. 365 4.1.3 Hardware Interrupts .............................................................................................................366 4.1.4 Interrupts and Interrupt Vector Tables ................................................................................. 367
4.2 Interrupt Control .......................................................................................................................... 369 4.2.1 Interrupt Enable Flag ........................................................................................................... 371 4.2.2 Interrupt Request Bit ............................................................................................................ 371 4.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) .................... 372 4.2.4 Rewrite the interrupt control register .................................................................................... 373 4.3 Interrupt Sequence ..................................................................................................................... 374 4.3.1 Interrupt Response Time ..................................................................................................... 374 4.3.2 Variation of IPL when Interrupt Request is Accepted .......................................................... 375 4.3.3 Saving Registers .................................................................................................................. 376 4.4 Returning from an Interrupt Routine ........................................................................................... 378 4.5 Interrupt Priority .......................................................................................................................... 378 4.6 Multiple Interrupts ....................................................................................................................... 380 4.7 Precautions for Interrupts ........................................................................................................... 382
Chapter 5 Standard Characteristics ___________________________
5.1 Standard DC Characteristics ...................................................................................................... 386 5.1.1 Standard Ports Characteristics ............................................................................................ 386 5.1.2 Standard Characteristics of ICC-f(XIN) ................................................................................. 389 5.2 Standard Characteristics of Pull-Up Resistor ............................................................................. 391 5.3 Standard DC Characteristics (Flash memory version) ............................................................... 392 5.3.1 Standard Ports Characteristics ............................................................................................ 392 5.3.2 Standard Characteristics of ICC-f(XIN) ................................................................................. 394 5.4 Standard Characteristics of Pull-Up Resistor (Flash memory version) ....................................... 395
Quick Reference to Pages Classified by Address
Address
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Register
Page
Address
004016 004116 004216 004316
Register
Page
Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR)
17 21 44 27
004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16
Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Address match interrupt register 0 (RMAD0)
47 44
004E16 004F16 005016 005116 005216 005316 005416
Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC)
34
UART0 UART0 UART1 UART1
transmit interrupt control register (S0TIC) receive interrupt control register (S0RIC) transmit interrupt control register (S1TIC) receive interrupt control register (S1RIC)
34
Address match interrupt register 1 (RMAD1)
44
005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16
Timer A0 interrupt control register (TA0IC) Timer X0 interrupt control register (TX0IC) Timer X1 interrupt control register (TX1IC) Timer X2 interrupt control register (TX2IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) 34
34
Quick Reference to Pages Classified by Address
Address
038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16
Register
Page
Address
03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016
Register
Page
Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) Timer A0 (TA0) Timer X0 (TX0) Timer X1 (TX1) Timer X2 (TX2) Clock divided counter (CDC) Timer B0 (TB0)
50 51 50 50
A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7) 92
66
60 Timer B1 (TB1)
03D116 03D216 03D316 03D416 03D516
A-D control register 2 (ADCON2) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1)
92 91
Timer A0 mode register (TA0MR) Timer X0 mode register (TX0MR) Timer X1 mode register (TX1MR) Timer X2 mode register (TX2MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR)
49 65
03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16
59
UART0 transmit/receive mode register (U0MR)
78 77 78 79 77 78 77 78 79 77 79
03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316
UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Port P0 (P0) Port P1 (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 (P2) Port P3 (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 (P4) Port P5 (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 (P6) Port P7 (P7) Port P6 direction register (PD6) Port P7 direction register (PD7)
104 103 104 103 104 103 104 103
Flash memory control register 0 (FCON0) (Note) Flash memory control register 1 (FCON1) (Note) Flash command register (FCMD) (Note)
03F416
127
03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16
Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2)
105
Note: This register is only exist in flash memory version.
Chapter 1
Hardware
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Description
The M30201 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core. M30201 group is packaged in a 52-pin plastic molded SDIP, or 56-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. The M30201 group includes a wide range of products with different internal memory types and sizes and various package types.
Features
• Basic machine instructions .................. Compatible with the M16C/60 series • Memory capacity .................................. ROM/RAM (See figure 1.4. ROM expansion.) • Shortest instruction execution time ...... 100ns (f(XIN)=10MHz) • Supply voltage ..................................... 4.0 to 5.5V (f(XIN)=10MHz) :mask ROM version 2.7 to 5.5V (f(XIN)=3.5MHz ):mask ROM version 4.0 to 5.5V (f(XIN)=10MHz) :flash memory version • Interrupts .............................................. 13 internal and 3 external interrupt sources, 4 software (including key input interrupt) • Multifunction 16-bit timer ...................... Timer A x 1, timer B x 2, timer X x 3 • Clock output • Serial I/O .............................................. 1 channel for UART or clock synchronous, 1 for UART • A-D converter ....................................... 10 bits X 8 channels (Expandable up to 13 channels) • Watchdog timer .................................... 1 line • Programmable I/O ............................... 43 lines • LED drive ports .................................... 8 ports • Clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Home appliances, Audio, office equipment, Automobiles
------Table of Contents-----Central Processing Unit (CPU) ..................... 12 Reset ............................................................. 15 Clock Generating Circuit ............................... 18 Protection ...................................................... 27 Interrupts ....................................................... 28 Watchdog Timer ............................................ 46 Timer ............................................................. 48 Serial I/O ....................................................... 75 A-D Converter ............................................... 89 Programmable I/O Ports ............................... 99 Electric Characteristics ............................... 111 Flash Memory version ................................. 125
2
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Pin Configuration
Figures 1.1 to 1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
AVSS P60/AN0 VREF AVCC P54/CKOUT/AN54 P53/CLKS/AN53 P52/CLK0/AN52 P51/RXD0/AN51 P50/TXD0/AN50 CNVSS P71/TB1IN/XCIN P70/TB0IN/XCOUT RESET XOUT VSS XIN VCC P45/TX2INOUT P44/INT1/TX1INOUT P43/INT0/TX0INOUT P42/RXD1 P41/TA0OUT P40/TA0IN/TXD1 P35 P34 P33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P00/KI0 P01/KI1 P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P10(LED0) P11(LED1) P12(LED2) P13(LED3) P14(LED4) P15(LED5) P16(LED6) P17(LED7) P30 P31 P32
Figure 1.1. Pin configuration for the M30201 group (shrink DIP product) (top view)
M30201MX-XXXSP M30201F6SP
Package: 52P4B
3
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
PIN CONFIGURATION (top view)
P53/CLKS/AN53 P54/CKOUT/AN54
P52/CLK0/AN52
P51/RXD0/AN51 P50/TXD0/AN50 CNVSS P71/TB1IN/XCIN P70/TB0IN/XCOUT RESET N.C. XOUT VSS XIN VCC P45/TX2INOUT
P44/INT1/TX1INOUT P43/INT0/TX0INOUT
54 53 52 51 50 49 48 47 46 45 44 43
56 55
N.C. AVCC VREF
P60/AN0 AVSS P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5
P66/AN6
1 2 3
4 5 6
7 8
9 10 11
12 13 14
42 41 40
39 38 37
36 35 34
33 32 31
30 29
P67/AN7 N.C. P00/KI0 P01/KI1
P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P10(LED0) P11(LED1) P12(LED2) P13(LED3)
M30201MX-XXXFP M30201MXT-XXXFP M30201F6FP M30201F6TFP
P42/RXD1 P41/TA0OUT P40/TA0IN/TXD1 N.C. P35 P34
P33 P32 P31 P30 P17(LED7) P16(LED6) P15(LED5) P14(LED4)
15 16 17 18 19 20 21 22 23 24 25 26 27 28
Package: 56P6S-A
Figure 1.2. Pin configuration for the M30201 group (QFP product) (top view)
4
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Block Diagram
Figure 1.3 is a block diagram of the M30201 group.
8
8
6
6
5
8
2
I/O ports
Port P0
Port P1
Port P3
Port P4
Port P5
Port P6
Port P7
Internal peripheral functions
Timer
A-D converter
(10 bits X 8 channels
Expandable up to 13 channels)
System clock generator XIN-XOUT XCIN-XCOUT
Timer TA0 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TX0 (16 bits) Timer TX1 (16 bits) Timer TX2 (16 bits)
UART/clock synchronous SI/O
(8 bits X 1 channel)
UART
(8 bits X 1 channel)
M16C/60 series16-bit CPU core
Registers
Memory
ROM (Note 1)
RAM (Note 2)
Watchdog timer
(15 bits)
Program counter PC
R0H R0L R0H R0L R1H R1L R1H R1L R2 R2 R3 R3 A0 A0 A1 A1 FB FB
SB
Vector table INTB
Stack pointer
ISP USP
FLG
Multiplier
Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type.
Figure 1.3. Block diagram for the M30201 group
5
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Performance Outline
Table 1.1 is performance outline of M30201 group. Table 1.1. Performance outline of M30201 group Item Number of basic instructions Shortest instruction execution time Memory ROM capacity RAM I/O port P0 to P7 Multifunction TA0 timer TB0, TB1 TX0, TX1, TX2 Serial I/O UART0 UART1 A-D converter Watchdog timer Interrupt Clock generating circuit Performance 91 instructions 100ns (f(XIN)=10MHz (See figure 4. ROM expansion.) (See figure 4. ROM expansion.) 43 lines 16 bits x 1 16 bits x 2 16 bits x 3 (UART or clock synchronous) x 1 UART x 1 10 bits x 8 channels (Expandable up to 13 channels) 15 bits x 1 (with prescaler) 13 internal and 3 external sources, 4 software sources 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) 4.0 to 5.5V (f(XIN)=10MHz) :mask ROM version 2.7 to 5.5V (f(XIN)=3.5MHz) :mask ROM version 4.0 to 5.5V (f(XIN)=10MHz) :flash memory version 11mW (f(XIN)=3.5MHz , Vcc=3V) :mask ROM version 95mW (f(XIN)=10MHz, Vcc=5V) :flash memory version 5V 5mA (15mA:LED drive port) CMOS silicon gate 52-pin plastic mold SDIP 56-pin plastic mold QFP
Supply voltage
Power consumption I/O I/O withstand voltage characteristics Output current Device configuration Package
6
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Mitsubishi plans to release the following products in the M30201 group: (1) Support for mask ROM version and flash memory version (2) ROM capacity (3) Package 52P4B : Plastic molded SDIP (mask ROM version and flash memory version) 56P6S-A : Plastic molded QFP (mask ROM version and flash memory version) Apr. 2001
RAM Size (Byte)
2K
M30201F6SP/FP M30201F6TFP M30201M6-XXXFP M30201M6T-XXXFP M30201M4-XXXSP/FP M30201M4T-XXXFP
1K
512
16K
32K
48K
ROM Size (Byte)
Figure 1.4. ROM expansion
Type No.
M30201 M 4 T – XXX SP
Package type: SP : Package FP : Package 52P4B 56P6S-A
ROM No. Omitted for flash memory version Shows difference of characteristics and usage etc: Nothing : Common T : Automobiles ROM capacity: 4 : 32K bytes 6 : 48K bytes Memory type: M : Mask ROM version F : Flash memory version Shows pin count, etc (The value itself has no specific meaning) M30201 Group M16C Family
Figure 1.5. Type No., memory size, and package
7
U de nd ve er lo pm en
t
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name VCC, VSS CNVSS RESET XIN XOUT Signal name Power supply input CNVSS Reset input Clock input Clock output Input Input Input Output I/O type Function Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin. Connect it to the VSS pin. A “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin is a power supply input for the A-D converter. Connect it to VCC. This pin is a power supply input for the A-D converter. Connect it to VSS. Input Input/output This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. This is an 8-bit I/O port equivalent to P0. This is a 6-bit I/O port equivalent to P0. This is a 6-bit I/O port equivalent to P0. The P40 pin is shared with timer A0 input and serial I/O output TxD1. The P41 pin is shared with timer A0 output. The P42 pin is shared with serial I/O input RxD1. The P43 pin is shared with external interrupt INT0 and timer X0 input/output TX0INOUT. The P44 pin is shared with external interrupt INT1 and timer X1 input/output TX1INOUT. The P45 pin is shared with timer X2 input/output TX2INOUT. This is a 5-bit I/O port equivalent to P0. The P50, P51, P52, and P53 pins are shared with serial I/O pins TxD0, RxD0, CLK0, and CLKS. The P54 pin is shared with clock output CLKOUT. Also, these pins are shared with analog input pins AN50 through AN54. This is an 8-bit I/O port equivalent to P0. These pins are shared with analog input pins AN0 through AN7. This is a 2-bit I/O port equivalent to P0 . These pins are used for input/output to and from the oscillator circuit for the clock. Connect a crystal oscillator between the XCIN and the XCOUT pins.
AVCC AVSS
Analog power supply input Analog power supply input Reference voltage input I/O port P0
VREF P00 to P07
P10 to P17 P30 to P35 P40 to P45
I/O port P1 I/O port P3 I/O port P4
Input/output Input/output Input/output
P50 to P54
I/O port P5
Input/output
P60 to P67
I/O port P6
Input/output
P70 to P71
I/O port P7
Input/output
8
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory Operation of Functional Blocks
The M30201 accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, A-D converter, and I/O ports. The following explains each unit.
Memory
Figure 1.6 is a memory map of the M30201. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30201M4-XXXSP, there is 32K bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as the reset are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30201M4-XXXSP, there is 1K byte of internal RAM from 0040016 to 007FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area For details, see Figures 1.7 to 1.8 FFE0016
0040016
Internal RAM area Special page vector table
YYYYY16
RAM size 1K bytes 2K bytes Address YYYYY16 007FF16
FFFDC16
00BFF16
Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC
ROM size 32K bytes 48K bytes
Address XXXXX16 F800016 F400016
XXXXX16 Internal ROM area FFFFF16
FFFFF16
Reset
Figure 1.6. Memory map
9
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
004016 004116 004216 004316
Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR)
004416 004516 004616 004716 004816 004916 004A16 004B16
Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Address match interrupt register 0 (RMAD0)
004C16 004D16 004E16 004F16 005016 005116 005216
Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC)
Address match interrupt register 1 (RMAD1)
005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16
UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC) Timer X0 interrupt control register (TX0IC) Timer X1 interrupt control register (TX1IC) Timer X2 interrupt control register (TX2IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC)
Note: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.7. Location of peripheral unit control registers (1)
10
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16
Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) Timer A0 (TA0) Timer X0 (TX0) Timer X1 (TX1) Timer X2 (TX2) Clock divided counter (CDC) Timer B0 (TB0) Timer B1 (TB1)
03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516
A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7)
A-D control register 2 (ADCON2) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1)
Timer A0 mode register (TA0MR) Timer X0 mode register (TX0MR) Timer X1 mode register (TX1MR) Timer X2 mode register (TX2MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR)
03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Port P0 (P0) Port P1 (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 (P2) (Reserved) Port P3 (P3) Port P2 direction register (PD2) (Reserved) Port P3 direction register (PD3) Port P4 (P4) Port P5 (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 (P6) Port P7 (P7) Port P6 direction register (PD6) Port P7 direction register (PD7)
Flash memory control register 0 (FCON0) (Note1) Flash memory control register 1 (FCON1) (Note1) Flash command register (FCMD) (Note)
03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16
Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Port P1 drive control register (DRR)
Note 1: This register is only exist in flash memory version. Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.8. Location of peripheral unit control registers (2)
11
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.9. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks.
b15
b8 b7
b0
R0(Note)
H
L
b15
b8 b7
b0
b19
b0
R1(Note)
H
L Data registers
PC
Program counter
b15
b0
b19
b0
R2(Note)
INTB
H
L
Interrupt table register
b0
b15
b0
b15
R3(Note)
USP
User stack pointer
b15
b0
b15
b0
A0(Note) Address registers
ISP
Interrupt stack pointer
b15
b0
b15
b0
A1(Note)
SB
Static base register
b15
b0
b15
b0
FB(Note)
Frame base registers
FLG
Flag register
IPL
U
I OBS Z DC
Note: These registers consist of two register banks.
Figure 1.9. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H, R1H), and low-order bits as (R0L, R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0, R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
12
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.10 shows the flag register (FLG). The following explains the function of each flag: • Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. • Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged. • Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”. • Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”. • Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”. • Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”. • Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.
13
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
• Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed. • Bits 8 to 11: Reserved area • Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. • Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
b15
b0
IPL
U
I
OBSZDC
Flag register (FLG)
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area
Figure 1.10. Flag register (FLG)
14
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.11 shows the example reset circuit. Figure 1.12 shows the reset sequence.
5V 4.0V VCC RESET VCC 0V 5V RESET 0.8V 0V RESET VCC
Power source voltage detection circuit
5V 4.0V VCC 0V 5V RESET 0V
Example when VCC = 5V.
Figure 1.11. Example reset circuit
XIN More than 20 cycles are needed
RESET
BCLK
24cycles
BCLK
(Internal clock)
Content of reset vector Address
(Internal address signal)
FFFFC16
FFFFE16
Figure 1.12. Reset sequence
15
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(1) Processor mode register 0 (2) Processor mode register 1 (3) System clock control register 0 (4) System clock control register 1 (5) Address match interrupt enable register (6) Protect register (7) Watchdog timer control register (8) Address match interrupt register 0
(000416)··· (000516)··· 0
0000 00
(33) Timer B0 mode register (34) Timer B1 mode register (35) UART0 transmit/receive mode register (36) UART0 transmit/receive control register 0 (37) UART0 transmit/receive control register 1 (38) UART1 transmit/receive mode register (39) UART1 transmit/receive control register 0 (40) UART1 transmit/receive control register 1 (41) UART transmit/receive control register 2 (42) Flash memory control register 0 (Note ) (43) Flash memory control register 1 (Note) (44) Flash command register (45) A-D control register 2 (46) A-D control register 0 (47) A-D control register 1 (48) Port P0 direction register (49) Port P1 direction register (50) Port P2 direction register (51) Port P3 direction register (52) Port P4 direction register (53) Port P5 direction register (54) Port P6 direction register (55) Port P7 direction register (56) Pull-up control register 0 (57) Pull-up control register 1 (58) Port P1 drive capacity control register (59) Data registers (R0/R1/R2/R3) (60) Address registers (A0/A1) (61) Frame base register (FB)
(039B16)··· 0 0 ? (039C16)··· 0 0 ? (03A016)···
0000 0000 0016
(000616)··· 0 1 0 0 1 0 0 0 (000716)··· 0 0 1 0 0 0 0 0 (000916)··· (000A16)··· 00 000
(03A416)··· 0 0 0 0 1 0 0 0 (03A516)··· 0 0 0 0 0 0 1 0 (03A816)··· 0016
(000F16)··· 0 0 0 ? ? ? ? ? (001016)··· (001116)··· (001216)··· 0016 0016 0000 0016 0016 0000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 00?000 00?000 0000
(03AC16)··· 0 0 0 0 1 0 0 0 (03AD16)··· 0 0 0 0 0 0 1 0 (03B016)··· 000000
(03B416)··· 0 0 1 0 0 0 0 0 (03B516)··· (03B616)··· (03D416)··· 0016 0000 00
(9) Address match interrupt register 1
(001416)··· (001516)··· (001616)···
(10) Key input interrupt control register (11) A-D conversion interrupt control register (12) UART0 transmit interrupt control register (13) UART0 receive interrupt control register (14) UART1 transmit interrupt control register (15) UART1 receive interrupt control register (16) Timer A0 interrupt control register (17) Timer X0 interrupt control register (18) Timer X1 interrupt control register (19)Timer X2 interrupt control register (20)Timer B0 interrupt control register (21)Timer B1 interrupt control register (22)INT0 interrupt control register (23)INT1 interrupt control register (24)Count start flag (25)Clock prescaler reset flag (26)One-shot start flag (27)Trigger select flag (28) Up-down flag (29)Timer A0 mode register (30)Timer X0 mode register (31)Timer X1 mode register (32)Timer X2 mode register
(004D16)··· (004E16)··· (005116)··· (005216)··· (005316)··· (005416)··· (005516)··· (005616)··· (005716)··· (005816)··· (005A16)··· (005B16)··· (005D16)··· (005E16)···
(03D616)··· 0 0 0 0 0 ? ? ? (03D716)··· (03E216)··· (03E316)··· (03E616)··· (03E716)··· (03EA16)··· (03EB16)··· (03EE16)··· (03EF16)··· (03FC16)··· (03FD16)··· (03FE16)··· 0016 0016 0016 000016 000016 000016 0000016 000016 000016 000016 000016 0016 0016 0016 0000000 000000 0 00 0 00 00000 0016 00
(038016)··· 0 0 0 (038116)··· 0 (038216)··· (038316)··· (038416)··· (039616)··· (039716)··· (039816)··· (039916)···
0000 0016 0 0016 0016 0016 0016 0
(62) Interrupt table register (INTB) (63) User stack pointer (USP) (64) Interrupt stack pointer (ISP) (65) Static base register (SB) (66) Flag register (FLG)
x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note: This register is only exist in flash memory version.
Figure 1.13. Device's internal status after a reset is cleared
16
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are preserved. Figure 1.14 shows the processor mode register 0 and 1.
Processor mode register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
00
0
Symbol PM0
Address 000416
When reset XXXX00002
Bit symbol
Reserved bit
PM03
Bit name
Function
Must always be set to “0”
RW
Software reset bit
The device is reset when this bit is set to “1”. The value of this bit is “0” when read.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Processor mode register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Symbol PM1
Address 000516
When reset 0XXXXXX02
Bit symbol
Reserved bit Nothing is assigned.
Bit name
Function
Must always be set to “0”
RW
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Reserved bit Must always be set to “0”
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Figure 1.14. Processor mode register 0 and 1.
17
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 1.2. Main clock and sub-clock generating circuits Use of clock Main clock generating circuit Sub clock generating circuit • CPU’s operating clock source • CPU’s operating clock source • Internal peripheral units’ • Timer A/B/X’s count clock operating clock source source Ceramic or crystal oscillator Crystal oscillator XIN, XOUT XCIN, XCOUT Available Available Oscillating Stopped Externally derived clock can be input
Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset Other
Example of oscillator circuit
Figure 1.15 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.16 shows some examples of subclock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 15 and 16 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator.
M30201
(Built-in feedback resistor)
M30201
(Built-in feedback resistor)
XIN
XOUT (Note) Rd
XIN
XOUT Open
Externally derived clock CIN COUT Vcc Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction.
Figure 1.15. Examples of main clock
M30201
(Built-in feedback resistor)
M30201
(Built-in feedback resistor)
XCIN
XCOUT (Note) RCd
XCIN
XCOUT Open
Externally derived clock CCIN CCOUT Vcc Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN and XCOUT following the instruction.
Figure 1.16. Examples of sub-clock
18
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit Clock Control
Figure 1.17 shows the block diagram of the clock generating circuit.
XCIN CM04
XCOUT 1/32
fC32
f1
fAD
f8
f32
fC
Sub clock
CM10 “1” Write signal
SQ
XIN
XOUT
b c
R
RESET Software reset
a
Divider
d
CM07=0
CM05
Interrupt request level judgment output
Main clock CM02
fC CM07=1
BCLK
SQ
WAIT instruction
R
b
c
1/2
1/2
a
1/2
1/2
1/2
CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10
d
CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16
CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00
Details of divider
Figure 1.17. Clock generating circuit
19
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be selected as BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock (f1, f8, f32, fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A, timer B and timer X counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog timer.
20
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 1.18 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0 Bit symbol
CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07
Address 000616 Bit name
Clock output function select bit
When reset 4816 Function
b1 b0
RW
0 0 : I/O port P54 0 1 : fC output 1 0 : f8 output 1 1 : Clock divide counter output
0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8)
WAIT peripheral function clock stop bit
XCIN-XCOUT drive capacity 0 : LOW select bit (Note 2) 1 : HIGH Port XC select bit Main clock (XIN-XOUT) stop bit (Note 3,4,5) Main clock division select bit 0 (Note 7) System clock select bit (Note 6) 0 : I/O port 1 : XCIN-XCOUT generation 0 : On 1 : Off 0 : CM16 and CM17 valid 1 : Division by 8 mode 0 : XIN, XOUT 1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: Changes to “1” when shifting to stop mode and at a reset. Note 3: This bit is used to stop the main clock when placing the device in a low-power mode. If you want to operate with XIN after exiting from the stop mode, set this bit to “0”. When operating with a self-excited oscillator, set the system clock select bit (CM07) to “1” before setting this bit to “1”. Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT (“H”) via the feedback resistor. Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”. Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock oscillating before setting this bit from “1” to “0”. Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 8: fC32 is not included. Do not set to “1” when using low-speed or low power dissipation mode.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
00
0
Symbol CM1 Bit symbol
CM10
Address 000716 Bit name
All clock stop control bit (Note 4)
When reset 2016 Function
0 : Clock on 1 : All clocks off (stop mode) Always set to “0” Always set to “0” Always set to “0” Always set to “0” 0 : LOW 1 : HIGH
b7 b6
RW
Reserved bit Reserved bit Reserved bit Reserved bit CM15 CM16 CM17 XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3)
0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8. Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-impedance state.
Figure 1.18. Clock control registers 0 and 1
21
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit Clock Output
The clock output function select bit allows you to choose the clock from f8, fc, or a divide-by-n clock that is output from the P54/CKOUT pin. The clock divide counter is an 8-bit counter whose count source is f32, and its divide ratio can be set in the range of 0016 to FF16. Figure 1.19 shows a block diagram of clock output.
Clock source selection
P54 f8 fC P54/CKOUT
1/2
f32
Clock divided couter (8) Division n+1 n=0016 to FF16 Reload register (8)
Low-order 8 bits
Address 038E16
Data bus low-order bits
Example: When f(XIN)=10MHz n=0716 : approx. 19.5kHz n=2616 : approx. 4.0kHz n=4D16 : approx. 2.0kHz n=9B16 : approx. 1.0kHz
Figure 1.19. Block diagram of clock output
22
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ClockMode, Wait Mode Stop Generating Circuit
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation of BCLK, f1 to f32, fc, fc32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A, timer B and timer X operate provided that the event counter mode is set to an external pulse, and UART0 functions provided an external clock is selected. Table 1.3 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed. When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Table 1.3. Port status during stop mode Pin Port CLKOUT When fC selected
States Retains status before stop mode “H”
When f8, clock devided Retains status before stop mode counter output selected
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32 does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU running in lowspeed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. Table 1.4 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed. Table 1.4. Port status during wait mode Pin Port CLKOUT When fC selected
States Retains status before wait mode Does not stop
When f8, clock devided Does not stop when the WAIT counter output selected peripheral function clock stop bit is “0”. When the WAIT peripheral function clock stop bit is “1”,the status immediately prior to entering wait mode is maintained.
23
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating of BCLK Status Transition Circuit Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.5 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped. Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock. Table 1.5. Operating modes dictated by settings of system clock control registers 0 and 1 CM17 0 1 Invalid 1 0 Invalid Invalid CM16 1 0 Invalid 1 0 Invalid Invalid CM07 0 0 0 0 0 1 1 CM06 0 0 1 0 0 Invalid Invalid CM05 0 0 0 0 0 0 1 CM04 Invalid Invalid Invalid Invalid Invalid 1 1 Operating mode of BCLK Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode Low-speed mode Low power dissipation mode
24
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Saving Clock Generating Circuit Power Saving
There are three power save modes.
(1) Normal operating mode
• High-speed mode In this mode, one main clock cycle forms BCLK. The CPU operates on the BCLK. The peripheral functions operate on the clocks specified for each respective function. • Medium-speed mode In this mode, the main clock is divided into 2, 4, 8, or 16 to form BCLK. The CPU operates on the BCLK. The peripheral functions operated on the clocks specified for each respective function. • Low-speed mode In this mode, fc forms BCLK. The CPU operates on the fc clock. fc is the clock supplied by the subclock. The peripheral functions operate on the clocks specified for each respective function. • Low power-dissipation mode This mode is selected when the main clock is stopped from low-speed mode. The CPU operates on the fc clock. fc is the clock supplied by the subclock. Only the peripheral functions for which the subclock was selected as the count source continue to run.
(2) Wait mode
CPU operation is halted in this mode. The oscillator continues to run.
(3) Stop mode
All oscillators stop in this mode. The CPU and internal peripheral functions all stop. Of all 3 power saving modes, power savings are greatest in this mode. Figure 1.20 shows the transition between each of the three modes, (1), (2), and (3).
25
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Saving Clock Generating Circuit
Transition of stop mode, wait mode Reset
All oscillators stopped
WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction Interrupt
CPU operation stopped
Stop mode
All oscillators stopped
CM10 = “1” Interrupt Interrupt CM10 = “1”
Medium-speed mode (divided-by-8 mode)
Wait mode
CPU operation stopped
Stop mode
All oscillators stopped
High-speed/mediumspeed mode
Wait mode
CPU operation stopped
Stop mode
CM10 = “1” Interrupt
Low-speed/low power dissipation mode
Wait mode
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode)
CM06 = “1” BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” CM04 = “1” (Notes 1, 3) CM07 = “0” (Note 1) CM06 = “1” CM04 = “0”
Main clock is oscillating CM04 = “0” Sub clock is oscillating High-speed mode
BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0”
Medium-speed mode (divided-by-2 mode)
BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1”
Medium-speed mode (divided-by-8 mode)
BCLK : f(XIN)/8 CM07 = “0” CM06 = “1”
Main clock is oscillating Sub clock is oscillating Low-speed mode
CM07 = “0” (Note 1, 3) BCLK : f(XCIN) CM07 = “1” CM07 = “1” (Note 2)
Medium-speed mode (divided-by-4 mode)
BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0”
Medium-speed mode (divided-by-16 mode)
BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1”
CM05 = “0” CM04 = “0”
CM05 = “1”
Main clock is oscillating Sub clock is stopped
CM04 = “1”
High-speed mode
BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” CM06 = “0” (Notes 1,3)
Medium-speed mode (divided-by-2 mode)
BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1”
Main clock is stopped Sub clock is oscillating Low power dissipation mode
CM07 = “1” (Note 2) CM05 = “1” BCLK : f(XCIN) CM07 = “1” CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1”
Medium-speed mode (divided-by-4 mode)
BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0”
Medium-speed mode (divided-by-16 mode)
BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow.
Figure 1.20. Clock transition
26
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit Protection Protection
The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.21 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) and port P4 direction register (address 03EA16) can only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to port P4. If, after “1” (write-enabled) has been written to the port P4 direction register write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PRCR
Bit symbol
PRC0
Address 000A16
Bit name
When reset XXXXX0002
Function RW
Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516) Enables writing to port P4 direction register (address 03EA16) (Note) 0 : Write-inhibited 1 : Write-enabled
PRC1
PRC2
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit to “0” . Other bits do not automatically return to “0” and they must therefore be reset by the program.
Figure 1.21. Protect register
27
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Overview of Interrupt Type of Interrupts
Figure 1.22 lists the types of interrupts.
Software
Special
Hardware
Peripheral I/O*1
*1 Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 1.22. Classification of interrupts
• Maskable interrupt
: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. • Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level.
28
Interrupt
Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction
________
Reset DBC Watchdog timer Single step Address matched
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
29
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts. • Reset Reset occurs if an “L” is input to the RESET pin. • DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. • Watchdog timer interrupt Generated by the watchdog timer. • Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed. • Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. • Key-input interrupt ___ A key-input interrupt occurs if an “L” is input to the KI pin. • A-D conversion interrupt This is an interrupt that the A-D converter generates. • UART0 and UART1 transmission interrupt These are interrupts that the serial I/O transmission generates. • UART0 and UART1 reception interrupt These are interrupts that the serial I/O reception generates. • Timer A0 interrupt This is an interrupts that timer A0 generates. • Timer B0 and timer B2 interrupt These are interrupts that timer B generates. • Timer X0 to timer X2 interrupt These are interrupts that timer X generates. ________ ________ • INT0 and INT1 interrupt ______ ______ An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
30
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.23 shows format for specifying interrupt vector addresses. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.
MSB
LSB Low address Mid address 0000 0000 High address 0000
Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3
Figure 1.23. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.6 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 1.6. Interrupt and fixed vector address Interrupt source Undefined instruction Overflow BRK instruction Address match Single step (Note) Watchdog timer
________
Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 FFFE816 to FFFEB16 FFFEC16 to FFFEF16 FFFF016 to FFFF316 FFFF416 to FFFF716 FFFF816 to FFFFB16 FFFFC16 to FFFFF16
Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector is filled with FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use Do not use -
DBC (Note) Reset
Note: Interrupts used for debugging purposes only.
31
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.7 shows the interrupts assigned to the variable vector tables and addresses of vector tables.
Table 1.7. Interrupt causes (variable interrupt vector addresses)
Software interrupt number Software interrupt number 0 Vector table address
Address (L) to address (H)
Interrupt source BRK instruction
Remarks Cannot be masked by I flag
+0 to +3 (Note)
Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14
+44 to +47 (Note) +48 to +51 (Note) +52 to +55 (Note) +56 to +59 (Note) Key input interrupt A-D
Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 to Software interrupt number 63
+68 to +71 (Note) +72 to +75 (Note) +76 to +79 (Note) +80 to +83 (Note) +84 to +87 (Note) +88 to +91 (Note) +92 to +95 (Note) +96 to +99 (Note) +100 to +103 (Note) +104 to +107 (Note) +108 to +111 (Note) +112 to +115 (Note) +116 to +119 (Note) +120 to +123 (Note) +124 to +127 (Note) +128 to +131 (Note) to +252 to +255 (Note)
UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer X0 Timer X1 Timer X2
Timer B0 Timer B1
INT0 INT1
Software interrupt
Cannot be masked by I flag
Note : Address relative to address in interrupt table register (INTB).
32
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level select bit, and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 1.24 shows the interrupt control registers.
33
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt control register (Note 2)
Symbol KUPIC ADIC SiTIC(i=0, 1) SiRIC(i=0, 1) TAiIC(i=0) TXiIC(i=0 to 2) TBiIC(i=0, 1) Address 004D16 004E16 005116, 005316 005216, 005416 005516 005616 to 005816 005A16, 005B16 When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7
R
W
ILVL1
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested 1 : Interrupt requested
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts.
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol INTiIC(i=0, 1)
Address 005D16, 005E16
When reset XX00X0002
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to “0”
R
W
ILVL1
ILVL2
IR
Interrupt request bit
(Note 1)
POL
Polarity select bit
Reserved bit Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts.
Figure 1.24. Interrupt control register
34
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Interrupt Enable Flag
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to “1” by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to “0” by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 1.8 shows the settings of interrupt priority levels and Table 1.9 shows the interrupt levels enabled, according to the contents of the IPL. The following are conditions under which an interrupt is accepted: · interrupt enable flag (I flag) = 1 · interrupt request bit = 1 · interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another.
Table 1.8. Settings of interrupt priority levels
Table 1.9. Interrupt levels enabled according to the contents of the IPL
IPL
IPL2 IPL1 IPL0
Interrupt priority level select bit
b2 b1 b0
Interrupt priority level Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7
Priority order 0 Low 0 0 0 1 1 1 High 1
Enabled interrupt priority levels 0 1 0 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1
1 Interrupt levels 4 and above are enabled 0 1 0 1 Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled
35
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Changing the Interrupt Control Register
< Program examples > The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG
; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
If changing the interrupt control register using an instruction other than the instructions listed hear, and if an interrupt occurs associated with this register during execution of the instruction, there can be instances in which the interrupt request bit is not set. To avoid this problem, use one of the instructions given below to change the register. Following instructions: AND, OR, BCLR or BSET
36
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. After this, the corresponding interrupt request bit becomes "0". (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however, does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed). (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.25 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged Time
Instruction (a)
Interrupt sequence (b)
Instruction in interrupt routine
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed.
Figure 1.25. Interrupt response time
37
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.10. Table 1.10. Time required for executing the interrupt sequence
Interrupt vector address Even Even Odd (Note 2) Odd (Note 2) Stack pointer (SP) value Even Odd Even Odd
________
16-bit bus, without wait 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1)
8-bit bus, without wait 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1)
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK Address bus Data bus R W The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Address 000016
Interrupt information
Indeterminate Indeterminate Indeterminate
SP-2 SP-2 contents
SP-4 SP-4 contents
vec vec contents
vec+2 vec+2 contents
PC
Figure 1.26. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.11 is set in the IPL. Table 1.11. Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels Watchdog timer Reset Other Value set in the IPL 7 0 Not changed
38
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8 loworder bits of the FLG register, 16 bits in total, in the stack area, then saves 16 low-order bits of the program counter. Figure 1.27 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address MSB
Stack area LSB
Address MSB
Stack area LSB [SP] New stack pointer value
m–4 m–3 m–2 m–1 m m+1 Content of previous stack Content of previous stack [SP] Stack pointer value before interrupt occurs
m–4 m–3 m–2 m–1 m m+1
Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH)
Content of previous stack Content of previous stack
Stack status before interrupt request is acknowledged
Stack status after interrupt request is acknowledged
Figure 1.27. State of stack before and after acceptance of interrupt request
39
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer (Note), at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.28 shows the operation of the saving registers. Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).
(1) Stack pointer (SP) contains even number
Address Stack area Sequence in which order registers are saved
[SP] – 5 (Odd) [SP] – 4 (Even) [SP] – 3(Odd) [SP] – 2 (Even) [SP] – 1(Odd) [SP] (Even) Finished saving registers in two operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) (1) Saved simultaneously, all 16 bits (2) Saved simultaneously, all 16 bits
(2) Stack pointer (SP) contains odd number
Address Stack area Sequence in which order registers are saved
[SP] – 5 (Even) [SP] – 4(Odd) [SP] – 3 (Even) [SP] – 2(Odd) [SP] – 1 (Even) [SP] (Odd) Finished saving registers in four operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH)
(3) (4) (1) (2)
Saved simultaneously, all 8 bits
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 1.28. Operation of saving registers
40
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 1.29 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.
Interrupt Priority Level Judge Circuit
This circuit selects the interrupt with the highest priority level when two or more interrupts are generated simultaneously. Figure 1.30 shows the interrupt resolution circuit.
41
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
________
Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 1.29. Hardware interrupts priorities
Priority level of each interrupt INT1 Timer B0 Timer X2 Timer X0 INT0 Timer B1 Timer X1 UART1 reception UART0 reception A-D conversion Timer A0 UART1 transmission UART0 transmission Key input interrupt Processor interrupt priority level (IPL) Interrupt enable flag (I flag) Address match Watchdog timer DBC Reset
Level 0 (initial value)
High
Priority of peripheral I/O interrupts (if priority levels are same)
Low
Interrupt request level judgment output Interrupt request accepted
Figure 1.30. Interrupt resolution circuit
42
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Key Input Interrupts Interrupt Key Input Interrupt
If the direction register of any of P00 to P07 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. Figure 1.31 shows the block diagram of the key input interrupt. Note that if an “L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt.
Port P04-P07 pull-up select bit
Pull-up transistor
Key input interrupt control register
Port P07 direction register
Port P07 direction register
(address 004D16)
P07/KI7
Pull-up transistor
Port P06 direction register
P06/KI6
Pull-up transistor
Interrupt control circuit
Port P01 direction register
Key input interrupt request
P01/KI1
Pull-up transistor
Port P00 direction register
P00/KI0
Figure 1.31. Block diagram of key input interrupt
43
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Address Match Interrupt Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the value of the program counter (PC) that is saved to the stack area varies depending on the instruction being executed. Figure 1.32 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit symbol
Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit
When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW
AIER0 AIER1
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Address match interrupt register i (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1
Address 001216 to 001016 001616 to 001416
When reset X0000016 X0000016
Function Address setting register for address match interrupt Nothing is assigned.
Values that can be set R W 0000016 to FFFFF16
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Figure 1.32. Address match interrupt-related registers
44
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts Precautions for Interrupts (1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset, generating any interrupts is prohibited.
(3) External interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 ________ and INT1 regardless of the CPU operation clock. ________ ________ • When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear the ______ interrupt request bit after changing the polarity. Figure 1.33 shows the switching condition of INT interrupt request.
Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt enable flag to “1” (Enable interrupt)
______
Figure 1.33. Switching condition of INT interrupt request
(4) Changing interrupt control register
See "Changing Interrupt Control Register".
45
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). When XIN is selected in BCLK Watchdog timer cycle = When XCIN is selected in BCLK Watchdog timer cycle = Prescaler division ratio (2) x watchdog timer count (32768) BCLK Prescaler division ratio (16 or 128) x watchdog timer count (32768) BCLK
For example, when BCLK is 10MHz and the prescaler division ratio is set to 16, the watchdog timer cycle is approximately 52.4 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). In stop mode and wait mode the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes are released. Figure 1.34 shows the block diagram of the watchdog timer. Figure 1.35 shows the watchdog timer-related registers.
Prescaler
“CM07 = 0” “WDC7 = 0”
1/16
BCLK
1/128
“CM07 = 0” “WDC7 = 1”
Watchdog timer
Watchdog timer interrupt request
“CM07 = 1”
1/2
Write to the watchdog timer start register (address 000E16)
Set to “7FFF16”
RESET
Figure 1.34. Block diagram of watchdog timer
46
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol WDC
Bit symbol
Address 000F16
Bit name
When reset 000XXXXX2
Function RW
High-order bit of watchdog timer
Reserved bit Reserved bit
WDC7
Must always be set to “0” Must always be set to “0”
Prescaler select bit
0 : Divided by 16 1 : Divided by 128
Watchdog timer start register
b7 b0
Symbol WDTS
Address 000E16
When reset Indeterminate
RW
Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written.
Figure 1.35. Watchdog timer control and start registers
47
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A Timer
There are six 16-bit timers. These timers can be classified by function into timer A (one), timers B (two) and timers X (three). All these timers function independently. Figure 1.36 show the block diagram of timers.
XIN
f1
Clock prescaler
1/8
1/4
f8 f32
XCIN
Clock prescaler reset flag (bit 7 at address 038116) set to “1”
1/32
Reset
fC32
f1 f8 f32 fc32
• Timer mode • One-shot mode • PWM mode
Timer A0
TA0IN
Noise filter
Timer A0
• Event counter mode
• Timer mode • One-shot mode • PWM mode • Pulse width measuring mode
Timer X0
TX0INOUT
Noise filter
Timer X0
• Event counter mode
• Timer mode • One-shot mode • PWM mode • Pulse width measuring mode
Timer X1
TX1INOUT
Noise filter
Timer X1
• Event counter mode
• Timer mode • One-shot mode • PWM mode • Pulse width measuring mode
Timer X2
TX2INOUT
Noise filter
Timer X2
• Event counter mode
• Timer mode • Pulse width measuring mode
TB0IN
Noise filter
Timer B0
Timer B0
• Event counter mode • Timer mode • Pulse width measuring mode
TB1IN
Noise filter
Timer B1 Timer B1
• Event counter mode
Figure 1.36. Timer block diagram
48
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A Timer A
Figure 1.37 shows the block diagram of timer A. Figures 1.38 to 1.40 show the timer A-related registers. Use the timer A0 mode register bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts pulses from an external source or a timer over flow. • One-shot timer mode: The timer stops counting when the count reaches “000016”. • Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source selection
f1 f8 f32 fC32
Polarity selection TA0IN
• Timer • One shot • PWM • Timer (gate function) • Event counter
Data bus low-order bits Low-order 8 bits Reload register (16) High-order 8 bits
Counter (16) Clock selection Up count/down count Always down count except in event counter mode
Count start flag Down count
External trigger
TB1 overflow TX0 overflow TX2 overflow
Up/down flag
Pulse output
TA0OUT Toggle flip-flop
Figure 1.37. Block diagram of timer A
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TA0MR
Address 039616
When reset 0016
Bit symbol
TMOD0
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode
RW
TMOD1
MR0 MR1 MR2 MR3 TCK0 TCK1
Function varies with each operation mode
Count source select bit (Function varies with each operation mode)
Figure 1.38. Timer A-related registers (1)
49
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A0 register (Note 1)
(b15) b7 (b8) b0 b7 b0
Symbol TA0
Address 038716,038616
When reset Indeterminate
Function • Timer mode Counts an internal count source
Values that can be set
RW
000016 to FFFF16
• Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow • One-shot timer mode Counts a one shot width • Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator • Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator Note 1: Read and write data in 16-bit units. Note 2: Use MOV instruction to write to this register. 000016 to FFFF16 (Note 2) 000016 to FFFE16 (Note 2) 0016 to FF16(Note 2) (Both high-order and low-order addresses)
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 000X00002
Bit symbol TA0S TX0S TX1S TX2S
Bit name Timer A0 count start flag Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Function 0 : Stops counting 1 : Starts counting
RW
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
TB0S TB1S CDCS Timer B0 count start flag Timer B1 count start flag
Clock devided count start flag
0 : Stops counting 1 : Starts counting
Up/down flag (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF
Address 038416
When reset XXX0XXX02
Bit symbol TA0UD
Bit name Timer A0 up/down flag
Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
TA0P Timer A0 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note : Use MOV instruction to write to this register.
Figure 1.39. Timer A-related registers (2)
50
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Address 038216
When reset XXXX00002
Bit symbol
TA0OS TX0OS TX1OS TX2OS
Bit name Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag
Function
1 : Timer start When read, the value is “0”
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Address 038316
When reset 0016
Bit symbol
TA0TGL
Bit name Timer A0 event/trigger select bit
Function
b1 b0
RW
TA0TGH TX0TGL
0 0 : Input on TA0IN is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected
b3 b2
Timer X0 event/trigger select bit
TX0TGH TX1TGL TX1TGH
0 0 : Input on TX0INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected
b5 b4
Timer X1 event/trigger select bit
0 0 : Input on TX1INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected
b7 b6
TX2TGL TX2TGH
Timer X2 event/trigger select bit
0 0 : Input on TX2INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”(input mode).
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol Nothing is assigned.
Bit name
Function
RW
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Figure 1.40. Timer A-related registers (3)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A (1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.12.) Figure 1.41 shows the timer A0 mode register in timer mode. Table 1.12. Specifications of timer mode Item Count source Count operation Specification f1, f8, f32, fc32 • Down count • When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) When the timer underflows Programmable I/O port or gate input Programmable I/O port or pulse output Count value can be read out by reading timer A0 register • When counting stopped When a value is written to timer A0 register, it is written to both reload register and counter • When counting in progress When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time) • Gate function Counting can be started and stopped by the TA0IN pin’s input signal • Pulse output function Each time the timer underflows, the TA0OUT pin’s polarity is reversed
Divide ratio Count start condition Count stop condition Interrupt request generation timing TA0IN pin function TA0OUT pin function Read from timer Write to timer
Select function
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol TA0MR Bit symbol TMOD0 TMOD1 MR0
Address 039616 Bit name Operation mode select bit Pulse output function select bit
When reset 0016 Function
b1 b0
RW
0 0 : Timer mode 0 : Pulse is not output (TA0OUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA0OUT pin is a pulse output pin)
b4 b3
MR1
Gate function select bit
0 X (Note 2): Gate function not available
(TA0IN pin is a normal port pin)
MR2
1 0 : Timer counts only when TA0IN pin is held “L” (Note 3) 1 1 : Timer counts only when TA0IN pin is held “H” (Note 3) 0 (Must always be “0” in timer mode) Count source select bit
b7 b6
MR3 TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0” (input mode).
Figure 1.41. Timer A0 mode register in timer mode
52
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A (2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timer A0 can count a single-phase and a two-phase external signal. Table 1.13 lists timer specifications when counting a single-phase external signal. Figure 1.42 shows the timer A0 mode register in event counter mode. Table 1.14 lists timer specifications when counting a two-phase external signal. Figure 1.43 shows the timer A0 mode register in event counter mode. Table 1.13. Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source • External signals input to TA0IN pin (effective edge can be selected by software) • TB1 overflow, TX0 overflow, TX2 overflow Count operation • Up count or down count can be selected by external signal or software • When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TA0IN pin function Programmable I/O port or count source input TA0OUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer A0 register Write to timer • When counting stopped When a value is written to timer A0 register, it is written to both reload register and counter • When counting in progress When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it • Pulse output function Each time the timer overflows or underflows, the TA0OUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected.
Timer A0 mode register (When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol TA0MR Bit symbol TMOD0 TMOD1 MR0 Bit name
Address 039616
When reset 0016 Function
b1 b0
RW RW
Operation mode select bit Pulse output function select bit
0 1 : Event counter mode 0 : Pulse is not output (TA0OUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA0OUT pin is a pulse output pin) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 3)
MR1 MR2 MR3 TCK0 TCK1
Count polarity select bit (Note 2) Up/down switching cause select bit
0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type 1 : Free-run type
Two-phase pulse operation 0 : Normal processing operation select bit (Note 4) 1 : Multiply-by-4 processing operation
Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to “0” (input mode). Note 4: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to “1” and event/trigger select bits (addresses 038316) to “00”.
Figure 1.42. Timer A0 mode register in event counter mode
53
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Table 1.14. Timer specifications in event counter mode (when processing two-phase pulse signal) Item Count source Count operation Specification • Two-phase pulse signals input to TA0IN or TA0OUT pin • Up count or down count can be selected by two-phase pulse signal • When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note) • 1/ (FFFF16 - n + 1) for up count • 1/ (n + 1) for down count n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) Timer overflows or underflows Two-phase pulse input Two-phase pulse input Count value can be read out by reading timer A0 register • When counting stopped When a value is written to timer A0 register, it is written to both reload register and counter • When counting in progress When a value is written to timer A0 register, it is written to only reload register. (Transferred to counter at next reload time.) • Normal processing operation The timer counts up rising edges or counts down falling edges on the TA0IN pin when input signal on the TA0OUT pin is “H”
Divide ratio Count start condition Count stop condition
Interrupt request generation timing
TA0IN pin function TA0OUT pin function Read from timer Write to timer
Select function
TA0OUT TA0IN
Up count Up count Up count Down count Down count Down count
• Multiply-by-4 processing operation If the phase relationship is such that the TA0IN pin goes “H” when the input signal on the TA0OUT pin is “H”, the timer counts up rising and falling edges on the TA0OUT and TA0IN pins. If the phase relationship is such that the TA0IN pin goes “L” when the input signal on the TA0OUT pin is “H”, the timer counts down rising and falling edges on the TA0OUT and TA0IN pins.
TA0OUT
Count up all edges Count down all edges
TA0IN
Count up all edges
Count down all edges
Note: This does not apply when the free-run function is selected.
54
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A0 mode register
(When using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
010001
Symbol TA0MR
Address 039616
When reset 0016
Bit name
TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Operation mode select bit
b1 b0
Function
0 1 : Event counter mode
RW
0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) 1 (Must always be “1” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) Count operation type select bit Two-phase pulse processing operation select bit (Note) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation
Note: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 038316) to “00”.
Figure 1.43. Timer A0 mode register in event counter mode
55
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A (3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.15.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.44 shows the timer A0 mode register in one-shot timer mode. Table 1.15. Timer specifications in one-shot timer mode Item Count source Count operation Specification f1, f8, f32, fC32 • The timer counts down • When the count reaches 000016, the timer stops counting after reloading a new count • If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : Set value • An external trigger is input • The timer overflows • The one-shot start flag is set (= 1) • A new count is reloaded after the count has reached 000016 • The count start flag is reset (= 0) The count reaches 000016 Programmable I/O port or trigger input Programmable I/O port or pulse output When timer A0 register is read, it indicates an indeterminate value • When counting stopped When a value is written to timer A0 register, it is written to both reload register and counter • When counting in progress When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time)
Divide ratio Count start condition
Count stop condition
Interrupt request generation timing
TA0IN pin function TA0OUT pin function Read from timer Write to timer
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
10
Symbol TA0MR Bit symbol TMOD0 TMOD1 MR0
Address 039616 Bit name Operation mode select bit Pulse output function select bit
When reset 0016 RW
Function
b1 b0
1 0 : One-shot timer mode 0 : Pulse is not output (TA0OUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TA0OUT pin is a pulse output pin)
0 : Falling edge of TA0IN pin's input signal (Note 3) 1 : Rising edge of TA0IN pin's input signal (Note 3)
MR1 MR2
External trigger select bit (Note 2) Trigger select bit
0 : One-shot start flag is valid 1 : Selected by event/trigger select register
MR3 TCK0 TCK1
0 (Must always be “0” in one-shot timer mode) Count source select bit
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: Valid only when the TA0IN pin is selected by the event/trigger select bit
(addresses 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0” (input mode).
Figure 1.44. Timer A0 mode register in one-shot timer mode
56
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A (4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.16.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.45 shows the timer A0 mode register in pulse width modulation mode. Figure 1.46 shows the example of how a 16-bit pulse width modulator operates. Figure 1.47 shows the example of how an 8-bit pulse width modulator operates. Table 1.16. Timer specifications in pulse width modulation mode Item Specification Count source f1, f8, f32, fc32 Count operation • The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) • The timer reloads a new count at a rising edge of PWM pulse and continues counting • The timer is not affected by a trigger that occurs when counting 16-bit PWM • High level width n / fi n : Set value • Cycle time (216-1) / fi fixed 8-bit PWM • High level width n (m+1) / fi n : values set to timer A0 register’s high-order address • Cycle time (28-1) (m+1) / fi m : values set to timer A0 register’s low-order address Count start condition • External trigger is input • The timer overflows • The count start flag is set (= 1) Count stop condition • The count start flag is reset (= 0) 8 bits PWM • Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L” Interrupt • Set value of "H" level width is FF16, 0016 : Timing that count value goes to 0116 request generation 16 bits PWM • Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L” timing • Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 000116 TA0IN pin function Programmable I/O port or trigger input TA0OUT pin function Pulse output Read from timer When timer A0 register is read, it indicates an indeterminate value Write to timer • When counting stopped :When a value is written to timer A0 register, it is written to both reload register and counter • When counting in progress : When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time)
Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
11
1
Symbol TA0MR Bit symbol TMOD0 TMOD1 MR0 MR1 MR2
Address 039616 Bit name Operation mode select bit
When reset 0016 Function
b1 b0
RW
1 1 : PWM mode
1 (Must always be “1” in PWM mode) External trigger select bit (Note 1) Trigger select bit
0: Falling edge of TA0IN pin's input signal (Note 2) 1: Rising edge of TA0IN pin's input signal (Note 2)
0: Count start flag is valid 1: Selected by event/trigger select register
0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator
b7 b6
MR3
16/8-bit PWM mode select bit Count source select bit
TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Valid only when the TA0IN pin is selected by the event/trigger select bit (addresses 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 2: Set the corresponding port direction register to “0” (input mode). Note 3: Set the corresponding port direction register to “1” (output mode) when the pulse is output.
Figure 1.45. Timer A0 mode register in pulse width modulation mode
57
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Condition : Reload register = 000316, when external trigger (rising edge of TA0IN pin input signal) is selected
1 / fi X (2 16 – 1)
Count source
TA0IN pin input signal
“H”
“L”
Trigger is not generated by this signal
1 / fi X n
PWM pulse output from TA0OUT pin
Timer A0 interrupt request bit
“H”
“L” “1” “0”
fi : Frequency of count source (f1, f8, f32, fC32) Cleared to “0” when interrupt request is accepted, or cleared by software Note: n = 000016 to FFFF16.
Figure 1.46. Example of how a 16-bit pulse width modulator operates
Condition :
Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TA0IN pin input signal) is selected
1 / fi X (m + 1) X (2 8 – 1)
Count source (Note1)
TA0IN pin input signal
“H” “L”
1 / fi X (m + 1) Underflow signal of 8-bit prescaler (Note2) “L”
“H”
1 / fi X (m + 1) X n PWM pulse output from TA0OUT pin Timer A0 interrupt request bit
“H” “L” “1” “0”
fi : Frequency of count source (f1, f8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleaerd by software
Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FF16.
Figure 1.47. Example of how an 8-bit pulse width modulator operates
58
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B Timer B
Figure 1.48 shows the block diagram of timer B. Figures 1.49 and 1.50 show the timer B-related registers. Use the timer Bi mode register (i = 0, 1) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: • Timer mode : The timer counts an internal count source. • Event counter mode : The timer counts pulses from an external source or a timer overflow. • Pulse period/pulse width measuring mode : The timer measures an external signal's pulse period or pulse width.
Data bus high-order bits Data bus low-order bits Low-order 8 bits High-order 8 bits
Clock source selection
f1 f8 f32 fC32
TBiIN (i = 0, 1)
• Timer • Pulse period/pulse width measurement
Reload register (16)
• Event counter Polarity switching and edge pulse Count start flag
Counter (16)
Counter reset circuit Can be selected in only event counter mode TBj overflow (j = 1 when i = 0, j = 0 when i = 1)
Figure 1.48. Block diagram of timer B
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TBiMR(i = 0, 1)
Address 039B16, 039C16
When reset 00XX00002
Bit symbol
TMOD0 TMOD1
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Inhibited
R
W
MR0 MR1 MR2
Function varies with each operation mode
(Note 1) (Note 2)
MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode)
Note 1: Timer B0. Note 2: Timer B1. Note 3: Must set “00” to operation mode select bit of M30200.
Figure 1.49. Timer B-related registers (1)
59
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer Bi register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TB0 TB1
Address 039116, 039016 039316, 039216
When reset Indeterminate Indeterminate
Function
• Timer mode Counts the timer's period • Event counter mode Counts external pulses input or a timer overflow • Pulse period / pulse width measurement mode Measures a pulse period or width Note1: Read and write data in 16-bit units.
Values that can be set
RW
000016 to FFFF16
000016 to FFFF16
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 000X00002
Bit symbol TA0S TX0S TX1S TX2S
Bit name Timer A0 count start flag Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Function 0 : Stops counting 1 : Starts counting
RW
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
TB0S TB1S CDCS Timer B0 count start flag Timer B1 count start flag
Clock devided count start flag
0 : Stops counting 1 : Starts counting
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol Nothing is assigned.
Bit name
Function
RW
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Figure 1.50. Timer B-related registers (2)
60
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B (1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.17.) Figure 1.51 shows the timer Bi mode register in timer mode. Table 1.17. Timer specifications in timer mode Item Count source Count operation Specification f1, f8, f32, fC32 • Counts down • When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows Programmable I/O port Count value is read out by reading timer Bi register • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time)
Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TBiMR(i=0, 1)
Address 039B16 to 039C16
When reset 00XX00002
Bit symbol TMOD0 TMOD1 MR0 MR1
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode
R
W
Invalid in timer mode Can be “0” or “1”
Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. MR3 Invalid in timer mode. In an attempt to write to this bit, write “0”. The value, if read in timer mode, turns out to be indeterminate. Count source select bit
b7 b6
TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Figure 1.51. Timer Bi mode register in timer mode
61
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B (2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.18.) Figure 1.52 shows the timer Bi mode register in event counter mode. Table 1.18. Timer specifications in event counter mode Item Specification Count source • External signals input to TBiIN pin • Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation • Counts down • When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows TBiIN pin function Count source input Read from timer Count value can be read out by reading timer Bi register Write to timer • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol TBiMR(i=0, 1)
Address 039B16 to 039C16
When reset 00XX00002
Bit symbol
TMOD0 TMOD1 MR0
Bit name
Operation mode select bit
b1 b0
Function
0 1 : Event counter mode
b3 b2
R
W
Count polarity select bit (Note 1)
MR1
0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Inhibited
Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. MR3 Invalid in event counter mode. In an attempt to write to this bit, write “0”. The value, if read in event counter mode, turns out to be indeterminate. Invalid in event counter mode. Can be “0” or “1”. Event clock select 0 : Input from TBiIN pin (Note 2) 1 : TBj overflow ( j = 1 when i = 0, j = 0 when i = 1)
TCK0 TCK1
Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be “0” or “1”. Note 2: Set the corresponding port direction register to “0” (input mode).
Figure 1.52. Timer Bi mode register in event counter mode
62
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B (3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.19.) Figure 1.53 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 1.54 shows the operation timing when measuring a pulse period. Figure 1.55 shows the operation timing when measuring a pulse width. Table 1.19. Timer specifications in pulse period/pulse width measurement mode Item Count source Count operation Specification f1, f8, f32, fc32 • Up count • Counter value “000016” is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1) • When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to “1”. The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the timer Bi mode register.) TBiIN pin function Measurement pulse input Read from timer When timer Bi register is read, it indicates the reload register’s content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol TBiMR(i=0 , 1)
Address 039B16 , 039C16
When reset 00XX00002
Bit symbol
TMOD0 TMOD1 MR0
Bit name
Operation mode select bit Measurement mode select bit
b1 b0
Function
1 0 : Pulse period / pulse width measurement mode
b3 b2
R
W
MR1
0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Inhibited
Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. MR3 TCK0 TCK1 Timer Bi overflow flag ( Note) Count source select bit 0 : Timer did not overflow 1 : Timer has overflowed
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note : The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the timer Bi mode register. This flag cannot be set to “1” by software.
Figure 1.53. Timer Bi mode register in pulse period/pulse width measurement mode
63
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
When measuring measurement pulse time interval from falling edge to falling edge
Count source
Measurement pulse
“H” “L” Transfer (indeterminate value) Transfer (measured value)
Reload register transfer timing
counter (Note 1) (Note 1) (Note 2)
Timing at which counter reaches “000016” Count start flag
“1” “0”
Timer Bi interrupt request bit
“1” “0”
Cleared to “0” when interrupt request is accepted, or cleared by software. Timer Bi overflow flag
“1” “0”
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 1.54. Operation timing when measuring a pulse period
Count source
Measurement pulse
“H” “L”
Transfer (indeterminate value) Transfer (measured value) Transfer (measured value) Transfer (measured value)
Reload register transfer timing
counter
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
Timing at which counter reaches “000016”
“1” “0”
Count start flag
Timer Bi interrupt request bit
“1” “0”
Cleared to “0” when interrupt request is accepted, or cleared by software. Timer Bi overflow flag
“1” “0”
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 1.55. Operation timing when measuring a pulse width
64
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X Timer X
Figure 1.56 shows the block diagram of timer X. Figures 1.57 to 1.59 show the timer X-related registers. Use the timer Xi mode register bits 0 and 1 to choose the desired mode. Timer X has the five operation modes listed as follows: • Timer mode : The timer counts an internal count source. • Event counter mode : The timer counts pulses from an external source or a timer overflow. • One-shot timer mode : The timer stops counting when the count reaches “000016”. • Pulse period/pulse width measuring mode : The timer measures an external signal's pulse period or pulse width. • Pulse width modulation (PWM) mode : The timer outputs pulses of a given width.
Data bus high-order bits
Clock source selection
f1 f8 f32 fC32
TXiINOUT (i=0 to 2)
Polarity switching and edge pulse
• Timer • One shot • PWM • Pulse period/pulse width measurement • Timer (gate function) • Event counter
Data bus low-order bits Low-order 8 bits Reload register (16) High-order 8 bits
Counter (16) Clock selection
Count start flag Counter reset circuit
TB1 overflow *1 *2
Pulse output
External trigger *1 = TA0, *2 = TX1 when TX0 *1 = TX0, *2 = TX2 when TX1 *1 = TX1, *2 = TA0 when TX2
Toggle flip-flop
Figure 1.56. Block diagram of timer X
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address TXiMR(i = 0 to 2) 039716 to 039916
When reset 0016
Bit symbol
TMOD0 TMOD1
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode or pulse period/ pulse width measurement mode 1 1 : Pulse width modulation (PWM) mode
R
W
MR0 MR1 MR2 MR3 TCK0 TCK1
Function varies with each operation mode
Count source select bit (Function varies with each operation mode)
Figure 1.57. Timer X-related registers (1)
65
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Timer Xi register (Note 1)
(b15) b7 (b8) b0 b7 b0
Symbol TX0 TX1 TX2
Address 038916,038816 038B16,038A16 038D16,038C16
When reset Indeterminate Indeterminate Indeterminate
Values that can be set
Function • Timer mode Counts an internal count source
RW
000016 to FFFF16
• Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow • One-shot timer mode Counts a one shot width 000016 to FFFF16 (Note 2)
• Pulse period / pulse width measurement mode Measures a pulse period or width
• Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator • Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator Note 1: Read and write data in 16-bit units. Note 2: Use MOV instruction to write to this register. 000016 to FFFE16 (Note 2) 0016 to FF16(Note 2) (High-order addresses) 0016 to FF16 (Note 2) (Low-order addresses)
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 000X00002
Bit symbol
Bit name
Function
RW
TA0S TX0S TX1S TX2S
Timer A0 count start flag Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
0 : Stops counting 1 : Starts counting
Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TB0S TB1S CDCS Timer B0 count start flag Timer B1 count start flag
Clock devided count start flag
0 : Stops counting 1 : Starts counting
Figure 1.58. Timer X-related registers (2)
66
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Address 038216
When reset XXXX00002
Bit symbol
TA0OS TX0OS TX1OS TX2OS
Bit name Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag
Function
RW
1 : Timer start When read, the value is “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Address 038316
When reset 0016
Bit symbol
TA0TGL
Bit name Timer A0 event/trigger select bit
Function
b1 b0
RW
TA0TGH TX0TGL
0 0 : Input on TA0IN is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected
b3 b2
Timer X0 event/trigger select bit
TX0TGH TX1TGL TX1TGH
0 0 : Input on TX0INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected
b5 b4
Timer X1 event/trigger select bit
0 0 : Input on TX1INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected
b7 b6
TX2TGL TX2TGH
Timer X2 event/trigger select bit
0 0 : Input on TX2INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”(input mode).
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol Nothing is assigned.
Bit name
Function
RW
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Figure 1.59. Timer X-related registers (3)
67
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X (1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.20.) Figure 1.60 shows the timer Xi mode register in timer mode. Table 1.20. Specifications of timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TXiINOUT pin function Read from timer Write to timer Specification f1, f8, f32, fC32 • Down count • When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) When the timer underflows Programmable I/O port, gate input or pulse output Count value can be read out by reading timer Xi register • When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time) • Gate function Counting can be started and stopped by the TXiINOUT pin’s input signal • Pulse output function Each time the timer underflows, the TXiINOUT pin’s polarity is reversed
Select function
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol Address When reset TXiMR(i = 0 to 2) 039716 to 039916 0016 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode select bit Pulse output function select bit
b1 b0
Function 0 0 : Timer mode 0 : Pulse is not output (TXiINOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TXiINOUT pin is a pulse output pin)
b4 b3
RW
MR1
Gate function select bit
0 X (Note 2): Gate function not available
(TXiINOUT pin is a normal port pin)
MR2
1 0 : Timer counts only when TXiINOUT pin is held “L” (Note 3) 1 1 : Timer counts only when TXiINOUT pin is held “H” (Note 3) 0 (Must always be fixed to “0” in timer mode) Count source select bit
b7 b6
MR3 TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Set the corresponding port direction register to “1” (output mode). Gate function cannot be selected when pulse output function is selected. Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0” (input mode). Pulse output function cannot be selected when gate function is selected.
Figure 1.60. Timer Xi mode register in timer mode
68
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X (2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. (See Table 1.21.) Figure 1.61 shows the timer Xi mode register in event counter mode. Table 1.21. Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source • External signals input to TXiINOUT pin (effective edge can be selected by software) • TB1 overflow, TA0 overflow, TXi overflow Count operation • Down count • When the timer underflows, it reloads the reload register contents before continuing counting (Note) Divide ratio 1/ (n + 1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows TXiINOUT pin function Programmable I/O port, count source input or pulse output Read from timer Count value can be read out by reading timer Xi register Write to timer • When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer underflows, the reload register content is not reloaded to it • Pulse output function Each time the timer underflows, the TXiINOUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected.
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol Address TXiMR(i = 0 to 2) 039716 to 039916 Bit symbol TMOD0 TMOD1 MR0 Pulse output function select bit Bit name Operation mode select bit
b1 b0
When reset 0016 Function RW RW
0 1 : Event counter mode (Note 1) 0 : Pulse is not output (TXiINOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TXiINOUT pin is a pulse output pin) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge
MR1 MR2 MR3 TCK0 TCK1
Count polarity select bit (Note 3)
Invalid in event counter mode. Can be “0” or “1”. 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type 1 : Free-run type
Invalid in event counter mode. Can be “0” or “1”.
Note 1: Count source is selected by event/trigger select bit(address 038316) in event counter mode. Note 2: Set the corresponding port direction register to “1” (output mode). TXiINOUT pin input is not selected as count source when pulse output function is selected. Note 3: This bit is valid when only counting an external signal.
Figure 1.61. Timer Xi mode register in event counter mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X (3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.22.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.62 shows the timer Xi mode register in one-shot timer mode. Table 1.22. Timer specifications in one-shot timer mode Item Count source Count operation Specification f1, f8, f32, fC32 • The timer counts down • When the count reaches 000016, the timer stops counting after reloading a new count • If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : Set value • An external trigger is input • The timer overflows • The one-shot start flag is set (= 1) • A new count is reloaded after the count has reached 000016 • The count start flag is reset (= 0) The count reaches 000016 Programmable I/O port, trigger input or pulse output When timer Xi register is read, it indicates an indeterminate value • When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time)
Divide ratio Count start condition
Count stop condition
Interrupt request generation timing
TXiINOUT pin function Read from timer Write to timer
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
10
Symbol Address When reset TXiMR(i = 0 to 2) 039716 to 039916 0016 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode select bit Pulse output function select bit
b1 b0
Function 1 0 : One-shot timer mode or pulse period / pulse width measurement mode 0 : Pulse is not output (TXiINOOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TXiINOOUT pin is a pulse output pin)
0 : Falling edge of TXiINOOUT pin's input signal (Note 3) 1 : Rising edge of TXiINOOUT pin's input signal (Note 3)
RW
MR1 MR2
External trigger select bit (Note 2) Trigger select bit
0 : One-shot start flag is valid 1 : Selected by event/trigger select register (Note 4)
MR3 TCK0 TCK1
0 (Must always be “0” in one-shot timer mode) Count source select bit
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Set the corresponding port direction register to “1” (output mode). External trigger cannot be selected as count start condition when pulse output function is selected. Note 2: Valid only when the TXiINOUT pin is selected by the event/trigger select bit (addresses 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0” (input mode). Note 4: Pulse output function cannot be selected when TXiINOUT pin is selected by the event/trigger select bit (addresses 038316).
Figure 1.62. Timer Xi mode register in one-shot timer mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X (4) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.23.) Figure 1.63 shows the timer Xi mode register in pulse period/pulse width measurement mode. Figure 1.64 shows the operation timing when measuring a pulse period. Figure 1.65 shows the operation timing when measuring a pulse width. Table 1.23. Timer specifications in pulse period/pulse width measurement mode Item Count source Count operation Specification f1, f8, f32, fc32 • Up count • Counter value “000016” is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1) • When an overflow occurs. (Simultaneously, the timer Xi overflow flag changes to “1”. The timer Xi overflow flag changes to “0” when the count start flag is “1” and a value is written to the timer Xi mode register.) TXiINOUT pin function Measurement pulse input Read from timer When timer Xi register is read, it indicates the reload register’s content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Xi register is indeterminate until the second effective edge is input after the timer.
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
10
Symbol Address When reset 002 TXiMR(i = 0 to 2) 039716 to 039916
Bit symbol
TMOD0 TMOD1 MR0
Bit name
Operation mode select bit Measurement mode select bit
b1 b0
Function
1 0 : One-shot timer mode or pulse period / pulse width measurement mode
b3 b2
RW
MR1
0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Inhibited 0 : Timer did not overflow 1 : Timer has overflowed
MR 2 MR3 TCK0 TCK1
Timer Xi overflow flag (Note)
1 (Must always be “1” in pulse period / pulse width measurement mode) Count source select bit
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note: The timer Xi overflow flag changes to “0” when the count start flag is “1” and a value is written to the timer Xi mode register. This flag cannot be set to “1” by software.
Figure 1.63. Timer Xi mode register in pulse period/pulse width measurement mode
71
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
When measuring measurement pulse time interval from falling edge to falling edge
Count source
Measurement pulse
“H” “L” Transfer (indeterminate value) Transfer (measured value)
Reload register transfer timing
counter (Note 1) (Note 1) (Note 2)
Timing at which counter reaches “000016” Count start flag
“1” “0”
Timer Xi interrupt request bit
“1” “0”
Cleared to “0” when interrupt request is accepted, or cleared by software. Timer Xi overflow flag
“1” “0”
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 1.64. Operation timing when measuring a pulse period
Count source
Measurement pulse
“H” “L”
Transfer (indeterminate value) Transfer (measured value) Transfer (measured value) Transfer (measured value)
Reload register transfer timing
counter
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
Timing at which counter reaches “000016”
“1” “0”
Count start flag
Timer Xi interrupt request bit
“1” “0”
Cleared to “0” when interrupt request is accepted, or cleared by software. Timer Xi overflow flag
“1” “0”
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 1.65. Operation timing when measuring a pulse width
72
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X (5) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.24.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.66 shows the timer Xi mode register in pulse width modulation mode. Figure 1.67 shows the example of how a 16-bit pulse width modulator operates. Figure 1.68 shows the example of how an 8-bit pulse width modulator operates. Table 1.24. Timer specifications in pulse width modulation mode Item Count source Count operation Specification f1, f8, f32, fC32 • Down counts (operating as an 8-bit or a 16-bit pulse width modulator) • The timer reloads a new count at a rising edge of PWM pulse and continues counting • The timer is not affected by a trigger that occurs when counting • "H" level width n / fi n : Set value • Cycle time (216-1) / fi fixed • "H" level width n (m+1)/ fi n:values set to timer Xi register’s high-order address • Cycle time (28-1) (m+1) / fi m : values set to timer Xi register’s low-order address • The timer overflows • The count start flag is set (= 1) • The count start flag is reset (= 0) • Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L” • Set value of "H" level width is FF16, 0016 : Timing that count value goes to 0116 • Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L” • Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 000116 Pulse output When timer Xi register is read, it indicates an indeterminate value • When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time)
16-bit PWM 8-bit PWM Count start condition Count stop condition Interrupt 8 bits PWM request generation 16 bits PWM timing TXiINOUT pin function Read from timer Write to timer
Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
11
1
Symbol Address When reset TXiMR(i = 0 to 2) 039716 to 039916 0016 Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 Bit name Operation mode select bit
b1 b0
Function 1 1 : PWM mode
RW
1 (Must always be “1” in PWM mode) Invalid in PWM mode. Can be “0” or “1”. Trigger select bit 0: Count start flag is valid (Note 1) 1: Selected by event/trigger select register
0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator
b7 b6
MR3
16/8-bit PWM mode select bit Count source select bit
TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: TXiINOUT pin inout cannot be selected by the event/trigger select bit(addresses 038316). Note 2: Set the corresponding port direction register to “1” (output mode).
Figure 1.66. Timer Xi mode register in pulse width modulation mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Condition : Reload register = 000316, when trigger (timer overflow) is selected
1 / fi X (2 16 – 1)
Count source
Trigger signal
“H” “L”
Trigger is not generated by this signal 1 / fi X n
PWM pulse output from TXiINOUT pin Timer Xi interrupt request bit
“H” “L” “1” “0”
fi : Frequency of count source (f1, f8, f32, fC32) Cleared to “0” when interrupt request is accepted, or cleared by software Note1: n = 000016 to FFFF16.
Figure 1.67. Example of how a 16-bit pulse width modulator operates
Condition :
Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 Trigger (timer overflow) is selected
1 / fi X (m + 1) X (2 8 – 1)
Count source (Note1)
Trigger signal
“H” “L”
1 / fi X (m + 1)
“H” Underflow signal of 8-bit prescaler (Note2) “L”
1 / fi X (m + 1) X n PWM pulse output from TXiINOUT pin Timer Xi interrupt request bit
“H” “L” “1” “0”
fi : Frequency of count source (f1, f8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleaerd by software
Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FF16.
Figure 1.68. Example of how an 8-bit pulse width modulator operates
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O Serial I/O
Serial I/O is configured as two channels: UART0 and UART1. UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.69 shows the block diagram of UART0 and UART1. Figure 1.70 shows the block diagram of the transmit/receive unit. UART0 has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/ O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016 and 03A816) determine whether UART0 is used as a clock synchronous serial I/O or as a UART. UART1 is used as a UART only. Figures 1.71 through 1.73 show the registers related to UARTi.
(UART0) RxD0
UART reception
TxD0
1/16
Clock source selection
f1 f8 f32 fC Internal Bit rate generator
Clock synchronous type
1/16
Reception control circuit
Receive clock
Transmit/ receive unit
1 / (m+1)
External
UART transmission
Clock synchronous type
Transmission control circuit
Transmit clock
Clock synchronous type
1/2
(when internal clock is selected)
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CLK0 CLKS
CLK polarity reversing circuit Clock output pin select switch
(UART1) RxD1
Clock source selection
f1 f8 f32 fC Bit rate generator
1/16
TxD1
Reception control circuit Receive clock Transmit/ receive unit
1 / (n+1)
1/16
Transmission control circuit
Transmit clock
m : Values set to UART0 bit rate generator (BRG0) n : Values set to UART1 bit rate generator (BRG1)
Figure 1.69. Block diagram of UARTi (i = 0, 1)
75
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Clock synchronous type Clock synchronous PAR type disabled UART (7 bits) UART (8 bits) UART (7 bits)
UARTi receive register
1SP
RxDi
SP 2SP
SP
PAR
UART PAR enabled
UART (9 bits)
Clock synchronous type UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive buffer register
MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi transmit buffer register
UART (8 bits) UART (9 bits) UART (9 bits) Clock synchronous type
2SP SP SP 1SP
PAR
PAR enabled
UART
TxDi
Clock PAR disabled synchronous type UART (7 bits) UART (8 bits) Clock synchronous type UART (7 bits)
UARTi transmit register
“0”
SP: Stop bit PAR: Parity bit
Note: UART1 cannot be used in clock synchronous serial I/O.
Figure 1.70. Block diagram of transmit/receive unit
76
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit buffer register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB
Address 03A316, 03A216 03AB16, 03AA16
When reset Indeterminate Indeterminate
Function
RW
Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note : Use MOV instruction to write to this register.
UARTi receive buffer register
(b15) b7 (b8) b0 b7 b0
Symbol U0RB U1RB
Address 03A716, 03A616 03AF16, 03AE16
When reset Indeterminate Indeterminate
Bit symbol
Bit name
Function (During clock synchronous serial I/O mode) Receive data
Function (During UART mode) Receive data
RW
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. OER FER PER SUM Overrun error flag (Note) Framing error flag (Note) Parity error flag (Note) Error sum flag (Note) 0 : No overrun error 1 : Overrun error found Invalid Invalid Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found
Note: Bits 15 through 12 are set to “0” when the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A616, and 03AE16) is read out.
UARTi bit rate generator (Note 1, 2)
b7 b0
Symbol U0BRG U1BRG
Address 03A116 03A916
When reset Indeterminate Indeterminate
Function
Values that can be set 0016 to FF16
RW
Assuming that set value = n, BRGi divides the count source by n + 1
Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register.
Figure 1.71. Serial I/O-related registers (1)
77
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol
Bit name
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
SMD0 Serial I/O mode select bit (Note 1) SMD1 SMD2 CKDIR Internal/external clock select bit (Note 2) STPS PRY Stop bit length select bit
0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited 0 : Internal clock (Note 3) 1 : External clock (Note 4) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
0 : Internal clock (Note 3) 1 : External clock (Note 4) Invalid
Odd/even parity select bit Invalid
PRYE SLEP
Parity enable bit Sleep select bit
Invalid Must always be “0”
Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: UART1 can use only internal clock. Must set this bit to “1”. Note 3: Set the corresponding port direction register to “1” (output mode). Note 4: Set the corresponding port direction register to “0” (input mode).
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol UiC0(i=0,1)
Bit symbol CLK0 CLK1
Set this bit to “0”.
Address 03A416, 03AC16
When reset 0816
Function (During UART mode)
b1 b0
Bit name BRG count source select bit
Function (Note) (During clock synchronous serial I/O mode)
b1 b0
RW
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected
TXEPT
Transmit register empty flag
0 : Data present in transmit 0 : Data present in transmit register register (during transmission) (during transmission) 1 : No data present in transmit 1 : No data present in transmit register (transmission register (transmission completed) completed)
Set this bit to “1”.
NCH
Data output select bit
0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output
CKPOL
CLK polarity select bit
Must always be “0”
UFORM Transfer format select bit 0 : LSB first 1 : MSB first Note: UART1 cannot be used in clock synchronous serial I/O.
Must always be “0”
Figure 1.72. Serial I/O-related registers (2)
78
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC1(i=0,1)
Address 03A516,03AD16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit Transmit buffer empty flag
Function (Note 1) (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
RW
RE RI
Receive enable bit (Note 2) Receive complete flag
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: If you are using clock asynchronous serial I/O mode, you can enable 'receive enable bit' when RxD port input is “H”. If RxD port input is “L” and you have enabled 'receive enable bit' , then receive operation starts immediately.
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UCON
Address 03B016
When reset XX0000002
Bit symbol
U0IRS
Bit name
UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit
Function (During clock synchronous serial I/O mode)
0 : Transmit buffer empty
(Tl = 1)
Function (During UART mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1)
RW
1 : Transmission completed
(TXEPT = 1)
U1IRS
Set this bit to “0”.
U0RRM UART0 continuous receive mode enable bit
0 : Continuous receive mode disabled 1 : Continuous receive mode enable
Must always be “0”
Set this bit to “0”. CLKMD0 CLK/CLKS select bit 0 Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode
(CLK output is CLK0 only)
Must always be “0”
CLKMD1 CLK/CLKS select bit 1 (Note 2)
Must always be “0”
1 : Transfer clock output from multiple pins function selected
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: When using multiple pins to output the transfer clock, the following requirements must be met: • UART0 internal/external clock select bit (bit 3 at address 03A016) = “0”.
Figure 1.73. Serial I/O-related registers (3)
79
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock I/O Serial synchronous serial I/O mode (1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. (See Table 1.25.) Figure 1.65 shows the UART0 transmit/receive mode register. Table 1.25. Specifications of clock synchronous serial I/O mode Specification Item Transfer data format • Transfer data length: 8 bits • When internal clock is selected (bit 3 at address 03A016 = “0”) : fi/ 2(n+1) (Note 1) Transfer clock fi = f1, f8, f32, fc • When external clock is selected (bit 3 at address 03A016 = “1”) : Input from CLK0 pin • To start transmission, the following requirements must be met: Transmission start _ Transmit enable bit (bit 0 at address 03A516) = “1” condition _ Transmit buffer empty flag (bit 1 at addresses 03A516) = “0” • Furthermore, if external clock is selected, the following requirements must also be met: _ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H” _ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L” Reception start • To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at address 03A516) = “1” conditio _ Transmit enable bit (bit 0 at address 03A516) = “1” _ Transmit buffer empty flag (bit 1 at address 03A516) = “0” • Furthermore, if external clock is selected, the following requirements must also be met: _ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H” _ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L” • When transmitting Interrupt request _ Transmit interrupt cause select bit (bit 0 at address 03B016) = “0”: Interrupts regeneration timing quested when data transfer from UART0 transfer buffer register to UART0 transmit register is completed _ Transmit interrupt cause select bit (bit 0 at address 03B016) = “1”: Interrupts requested when data transmission from UART0 transfer register is completed • When receiving _ Interrupts requested when data transfer from UART0 receive register to U A R T 0 receive buffer register is completed • Overrun error (Note 2) Error detection This error occurs when the next data is ready before contents of UART0 r e c e i v e buffer register are read out • CLK polarity selection Select function Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected • LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected • Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register • Transfer clock output from multiple pins selection UART0 transfer clock can be chosen by software to be output from one of the two pins set Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UART0 receive buffer will have the next data written in. Note also that the UART0 receive interrupt request bit does not change.
80
Mitsubishi microcomputers
M30201 Group
Clock I/O Serial synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART0 transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol U0MR Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE SLEP
Address 03A016 Bit name
When reset 0016 Function
b2 b1 b0
RW
Serial I/O mode select bit
0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock (Note 1) 1 : External clock (Note 2)
Internal/external clock select bit
Invalid in clock synchronous serial I/O mode 0 (Must always be “0” in clock synchronous serial I/O mode)
Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: Set the corresponding port direction register to “0” (input mode).
Figure 1.74. UART0 transmit/receive mode register in clock synchronous serial I/O mode
Table 1.26 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that for a period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.26. Input/output pin functions in clock synchronous serial I/O mode
Pin name TxD0 (P50) RxD0 (P51) CLK0 (P52) Function Serial data output Serial data input Transfer clock output Transfer clock input Method of selection Port P50 direction register (bit 0 at address 03EB16)= “1” (Outputs dummy data when performing reception only) Port P51 direction register (bit 1 at address 03EB16)= “0” (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016) = “0” Internal/external clock select bit (bit 3 at address 03A016) = “1” Port P52 direction register (bit 2 at address 03EB16) = “0”
81
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock I/O Serial synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1” “0” “1” “0” Data is set in UART0 transmit buffer register
Transmit enable bit (TE) Transmit buffer empty flag (Tl)
TCLK
CLK0
Transferred from UART0 transmit buffer register to UART0 transmit register
Stopped pulsing because transfer enable bit = “0”
TxD0 Transmit register empty flag (TXEPT)
“1” “0”
D 0 D1 D 2 D 3 D 4 D 5 D 6 D 7 D0 D1 D 2 D3 D4 D5 D6
D7
D 0 D1 D2 D3 D 4 D 5 D 6 D7
Transmit interrupt “1” request bit (IR) “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • Internal clock is selected. • CLK polarity select bit = “0”. • Transmit interrupt cause select bit = “0”. Tc = TCLK = 2(n + 1) / fi fi: frequency of BRG0 count source (f1, f8, f32, fc) n: value set to BRG0
• Example of receive timing (when external clock is selected)
Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl)
“1” “0” “1” “0” “1” “0”
Dummy data is set in UART0 transmit buffer register
Transferred from UART0 transmit buffer register to UART0 transmit register
1 / fEXT
CLK0
Receive data is taken in
RxD0 Receive complete flag (Rl) “0” Receive interrupt request bit (IR)
“1” “0”
D 0 D1 D 2 D3 D 4 D5 D6 D 7
Transferred from UART0 receive register “1” to UART0 receive buffer register
D0 D 1 D 2
D3 D4 D5
Read out from UART0 receive buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • External clock is selected. • CLK polarity select bit = “0”. fEXT: frequency of external clock Meet the following conditions are met when the CLK input before data reception = “H” • Transmit enable bit “1” • Receive enable bit “1” • Dummy data write to UART0 transmit buffer register
Figure 1.75. Typical transmit/receive timings in clock synchronous serial I/O mode
82
Mitsubishi microcomputers
M30201 Group
Clock I/O Serial synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Polarity select function As shown in Figure 1.76, the CLK polarity select bit (bit 6 at addresses 03A416) allows selection of the polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLK0 TXD0 RXD0 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 1: The CLK0 pin level when not transferring data is “H”.
• When CLK polarity select bit = “1”
CLK0 TXD0 RXD0 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 2: The CLK0 pin level when not transferring data is “L”.
Figure 1.76. Polarity of transfer clock (b) LSB first/MSB first select function As shown in Figure 1.77, when the transfer format select bit (bit 7 at addresses 03A416) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format select bit = “0”
CLK0 TXD0 RXD0 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7
LSB first
D7
• When transfer format select bit = “1”
CLK0 TXD0 RXD0 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0
MSB first
D0
Note: This applies when the CLK polarity select bit = “0”.
Figure 1.77. Transfer format
83
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock I/O Serial synchronous serial I/O mode
(c) Transfer clock output from multiple pins function This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.78.) The multiple pins function is valid only when the internal clock is selected for UART0.
Microcomputer
TXD0 (P50)
CLKS (P53) CLK0 (P52) IN CLK IN CLK
Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode. Figure 1.78. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again.
84
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock I/O Serial asynchronous serial I/O (UART) mode (2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. (See Table 1.27.) Figure 1.79 shows the UARTi transmit/receive mode register. Table 1.27. Specifications of UART Mode Item Transfer data format Specification • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected • Start bit: 1 bit • Parity bit: Odd, even, or nothing as selected • Stop bit: 1 bit or 2 bits as selected • When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32, fC • When external clock is selected (bit 3 at addresses 03A016=“1”) : fEXT/16(n+1) (Note 1) (Note 2) • To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1” - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0” • To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1” - Start bit detection • When transmitting - Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed • When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed • Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out • Framing error This error occurs when the number of stop bits set is not detected • Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set • Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered • Sleep mode selection This mode is used to transfer data to and from one of multiple slave microcomputers
Transfer clock
Transmission start condition Reception start condition Interrupt request generation timing
Error detection
Select function
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: fEXT is input from the CLK0 pin. Since UART1 does not have this pin, cannot select external clock. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change.
85
Mitsubishi microcomputers
M30201 Group
Clock I/O Serial asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol
SMD0 SMD1 SMD2 CKDIR STPS PRY
Bit name
Serial I/O mode select bit
b2 b1 b0
Function
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 : Internal clock (Note 2) 1 : External clock (Note 3) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
RW
Internal / external clock select bit (Note 1) Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit
PRYE SLEP
Note 1: UART1 can use only internal clock. Must set this bit to “1”. Note 2: Set the corresponding port direction register to “1” (output mode). Note 3: Set the corresponding port direction register to “0” (input mode).
Figure 1.79. UARTi transmit/receive mode register in UART mode Table 1.28 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the Nchannel open-drain is selected, this pin is in floating state.) Table 1.28. Input/output pin functions in UART mode
Pin name TxDi (P50, P40) RxDi (P51, P42) CLK0 (P52) Function Serial data output Method of selection Port P51 and P42 direction register (bit 0 at address 03EB16, bit 0 at address 03EA16)= “1” (Can be used as an input port when performing reception only) Port P51 and P42 direction register (bit 1 at address 03EB16, bit 2 at address 03EA16)= “0” (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016) = “0” Internal/external clock select bit (bit 3 at address 03A016) = “1”
Serial data input
Programmable I/O port Transfer clock input
86
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock I/O Serial asynchronous serial I/O (UART) mode
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
“1” “0” “1” “0”
Data is set in UARTi transmit buffer register.
Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi Transmit register “1” empty flag “0” (TXEPT) Transmit interrupt “1” request bit (IR) “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32, fc) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Parity bit
P
Stop bit
SP
Stopped pulsing because transmit enable bit = “0”
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
“1” “0” “1” “0”
Data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi Transmit register empty flag (TXEPT)
“1” “0”
Stop bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Transmit interrupt “1” request bit (IR) “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is disabled. • Two stop bits. • Transmit interrupt cause select bit = “0”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
Figure 1.80. Typical transmit timings in UART mode
87
Mitsubishi microcomputers
M30201 Group
Clock I/O Serial asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count source Receive enable bit RxDi “1” “0” Start bit Sampled “L” Receive data taken in Transfer clock Receive complete flag Receive interrupt request bit Reception triggered when transfer clock “1” is generated by falling edge of start bit “0” “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software The above timing applies to the following settings : •Parity is disabled. •One stop bit. Transferred from UARTi receive register to UARTi receive buffer register
Stop bit
D0
D1
D7
Figure 1.81. Typical receive timing in UART mode
(a) Sleep mode This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
88
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P60 to P67, and P50 to P54 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.29 shows the performance of the A-D converter. Figure 1.82 shows the block diagram of the A-D converter, and Figures 1.83 and 1.84 show the A-D converter-related registers. Table 1.29. Performance of A-D converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVCC (VCC) Operating clock φAD (Note 2) VCC = 5V fAD, divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN) VCC = 3V divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision VCC = 5V • Without sample and hold function ±3LSB • With sample and hold function (8-bit resolution) ±2LSB • With sample and hold function (10-bit resolution) ±3LSB VCC = 3V • Without sample and hold function (8-bit resolution) ±2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8 pins (AN0 to AN7) + 5 pins (AN50 to AN54) A-D conversion start condition • Software trigger A-D conversion starts when the A-D conversion start flag changes to “1” Conversion speed per pin • Without sample and hold function 8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles • With sample and hold function 8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Without sample and hold function, set the φAD frequency to 250kHz min. With the sample and hold function, set the φAD frequency to 1MHz min.
89
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
CKS1=1
fAD 1/2 1/2
CKS0=1 CKS1=0
φAD
A-D conversion rate selection
CKS0=0
V REF
VCUT=0
Resistor ladder
AV SS
VCUT=1
Successive conversion register A-D control register 1 (address 03D716)
A-D control register 0 (address 03D616)
Addresses
(03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16)
A-D register 0(16) A-D register 1(16) A-D register 2(16) A-D register 3(16) A-D register 4(16) A-D register 5(16) A-D register 6(16) A-D register 7(16) VIN Comparator Vref Decoder
Data bus high-order Data bus low-order
Port P6 group
P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7
CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 ADGSEL0=0
Port P5 group
P50/AN50 P51/AN51 P52/AN52 P53/AN53 P54/AN54
CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 ADGSEL0=1
Figure 1.82. Block diagram of A-D converter
90
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin select bit
CH1
CH2 MD0 MD1 Set this bit to “0”. ADST CKS0 A-D conversion start flag Frequency select bit 0 A-D operation mode select bit 0
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
(Note 2, 3)
0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1
(Note 2)
0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
A-D sweep pin select bit
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
(Note 2, 3)
0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 0 : Vref not connected 1 : Vref connected
BITS CKS1 VCUT
Set this bit to “0”. ADGSEL0 A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate. If port P5 group is selected, do not select 8 pins sweep mode.
Figure 1.83. A-D converter-related registers (1)
91
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
When reset
XXXX00002
000
Bit symbol
SMP Reserved bit
Bit name
A-D conversion method select bit
Function
0 : Without sample and hold 1 : With sample and hold Always set to “0”
RW
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D register i
(b15) b7 (b8) b0 b7
Symbol
ADi(i=0 to 7)
Address When reset 03C016 to 03CF16 Indeterminate
b0
Function
Eight low-order bits of A-D conversion result • During 10-bit mode Two high-order bits of A-D conversion result • During 8-bit mode The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
RW
Figure 1.84. A-D converter-related registers (2)
92
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter (1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. (See Table 1.30.) Figure 1.85 shows the A-D control register in one-shot mode. Table 1.30. One-shot mode specifications Item Specification Function The pin selected by the analog input pin select bit is used for one A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”) • Writing “0” to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin One of AN0 to AN7, as selected (Note) Reading of result of A-D converter Read A-D register corresponding to selected pin Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin select bit
CH1
CH2 MD0 A-D operation mode select bit 0
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
(Note 2, 3) (Note 2)
0 0 : One-shot mode
MD1 Set this bit to “0”. ADST CKS0
A-D conversion start flag Frequency select bit 0
0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
01
0
Symbol ADCON1 Bit symbol
SCAN0 SCAN1 MD2 BITS CKS1 VCUT
Address 03D716 Bit name
When reset 0016 Function
Invalid in one-shot mode
RW
A-D sweep pin select bit
A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
Set this bit to “0” in this mode. 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
Set this bit to “0”. ADGSEL0 A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.85. A-D conversion register in one-shot mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter (2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. (See Table 1.31.) Figure 1.86 shows the A-D control register in repeat mode. Table 1.31. Repeat mode specifications Item Specification Function The pin selected by the analog input pin select bit is used for repeated A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timing None generated Input pin One of AN0 to AN7, as selected (Note) Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time) Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
001
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin select bit
CH1
CH2 MD0 A-D operation mode select bit 0
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
(Note 2, 3) (Note 2)
0 1 : Repeat mode
MD1 Set this bit to “0”. ADST CKS0
A-D conversion start flag Frequency select bit 0
0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
01
0
Symbol ADCON1 Bit symbol
SCAN0 SCAN1 MD2 BITS CKS1 VCUT
Address 03D716 Bit name
When reset 0016 Function
Invalid in repeat mode
RW
A-D sweep pin select bit
A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
Set this bit to “0” in this mode. 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
Set this bit to “0”. ADGSEL0 A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.86. A-D conversion register in repeat mode
94
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter (3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. (See Table 1.32.) Figure 1.87 shows the A-D control register in single sweep mode. Table 1.32. Single sweep mode specifications Item Specification Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Writing “1” to A-D converter start flag Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”.) • Writing “0” to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note) Reading of result of A-D converter Read A-D register corresponding to selected pin Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
010
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in single sweep mode RW
Analog input pin select bit
CH1
CH2 A-D operation mode select bit 0 MD1 Set this bit to “0”. ADST CKS0 A-D conversion start flag Frequency select bit 0 MD0
b4 b3
1 0 : Single sweep mode
0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
01
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
A-D sweep pin select bit
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) Set this bit to “0” in this mode. 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
(Note 2, 3)
MD2 BITS CKS1 VCUT
Set this bit to “0”. ADGSEL0 A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate. If port P5 group is selected, do not select 8 pins sweep mode.
Figure 1.87. A-D conversion register in single sweep mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter (4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. (See Table 1.33.) Figure 1.88 shows the A-D control register in repeat sweep mode 0. Table 1.33. Repeat sweep mode 0 specifications Item Specification Function The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timing None generated Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note) Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time) Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
011
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in repeat sweep mode 0 RW
Analog input pin select bit
CH1
CH2 MD0 A-D operation mode select bit 0
b4 b3
1 1 : Repeat sweep mode 0
MD1 Set this bit to “0”. ADST CKS0
A-D conversion start flag Frequency select bit 0
0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
01
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
A-D sweep pin select bit
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) Set this bit to “0” in this mode. 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
(Note 2, 3)
MD2 BITS CKS1 VCUT
Set this bit to “0”. ADGSEL0 A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate. If port P5 group is selected, do not select 8 pins sweep mode.
Figure 1.88. A-D conversion register in repeat sweep mode 0
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter (5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. (See Table 1.34.) Figure 1.89 shows the A-D control register in repeat sweep mode 1. Table 1.34. Repeat sweep mode 1 specifications Item Specification Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timing None generated Input pin AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) (Note) Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time) Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
011
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in repeat sweep mode 1 RW
Analog input pin select bit
CH1
CH2 A-D operation mode select bit 0 MD1 Set this bit to “0”. ADST CKS0 A-D conversion start flag Frequency select bit 0 MD0
b4 b3
1 1 : Repeat sweep mode 1
0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
01
1
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 1 are selected
b1 b0
RW
A-D sweep pin select bit
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
0 0 : AN0 (1 pins) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) Set “1” in this mode. 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected
(Note 2)
MD2 BITS CKS1 VCUT
Set this bit to “0”. ADGSEL0 A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Figure 1.89. A-D conversion register in repeat sweep mode 1
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter • Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φAD cycle is achieved with 8-bit resolution and 33 φAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Programmable I/O Ports
There are 43 programmable I/O ports: P0 to P7. Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. The port P1 allows the drive capacity of its N-channel output transistor to be set as necessary. Figures 1.90 to 1.92 show the programmable I/O ports. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices, they function as outputs regardless of the contents of the direction registers. See the descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.93 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin.
(2) Port registers
Figure 1.94 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.95 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input.
(4) Port P1 drive capacity control register
Figure 1.95 shows a structure of the port P1 drive capacity control register. This register is used to control the drive capacity of the port P1's N-channel output transistor. Each bit in this register corresponds one for one to the port pins.
99
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection Direction register P30 to P35
Data bus
Port latch
Pull-up selection P00 to P07, P42, P71 Direction register
Data bus
Port latch
Input to respective peripheral functions
Pull-up selection Direction register P41, P70 output
Data bus
Port latch
Pull-up selection Direction register P40, P43, P44, P45 output
Data bus
Port latch
Input to respective peripheral functions
Figure 1.90. Programmable I/O ports (1)
100
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection P10 to P17 Direction register
Data bus
Port latch
Drive capacity control register
Pull-up selection P51 Direction register
Data bus
Port latch
Analog input Serial I/O input Pull-up selection Direction register P50, P53, P54 output
Data bus
Port latch
Analog input Pull-up selection Direction register P52 output
Data bus
Port latch
Analog input Serial clock input
Figure 1.91. Programmable I/O ports (2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection P60 to P67 Direction register
Data bus
Port latch
Analog input
Figure 1.92. Programmable I/O ports (3)
102
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi direction register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PDi (i = 0 to 7)
Address 03E216, 03E316, 03E716, 03EA16, 03EB16, 03EE16, 03EF16
When reset 0016 0016
Bit symbol
PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7
Bit name
Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register
Function
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 7 except 2)
RW
Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port P4 direction register. Note 2: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to P77. These bits can either be set nor reset. When read, its contents are indeterminate.
Figure 1.93. Direction register
103
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Pi (i = 0 to 7)
Address 03E016, 03E116, 03E516, 03E816, 03E916, 03EC16, 03ED16 Bit name Function
When reset Indeterminate Indeterminate RW
Bit symbol
Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7
Port Pi0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register
Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data (i = 0 to 7 except 2)
Note: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to P77. This bit can either be set nor reset. When read, its content is indeterminate.
Figure 1.94. Port register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0 Bit symbol
PU00 PU01 PU02 PU03
Address 03FC16 Bit name
P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up
When reset 0016 Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
PU06 PU07
P30 to P33 pull-up P34 to P35 pull-up
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1 Bit symbol
PU10 PU11 PU12 PU13 PU14 PU15 PU16
Address 03FD16 Bit name
P40 to P43 pull-up P44 to P47 pull-up P50 to P53 pull-up P54 pull-up P60 to P63 pull-up P64 to P67 pull-up P70 to P71 pull-up
When reset 0016 Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW
Port P1 drive capacity control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DRR Bit symbol
DRR0 DRR1 DRR2 DRR3 DRR4 DRR5 DRR6 DRR7
Address 03FE16 Bit name
Port P10 drive capacuty Port P11 drive capacuty Port P12 drive capacuty Port P13 drive capacuty Port P14 drive capacuty Port P15 drive capacuty Port P16 drive capacuty Port P17 drive capacuty
When reset 0016 Function
Set P1 N-channel output transistor drive capacity 0 : LOW 1 : HIGH RW
Figure 1.95. Pull-up control register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Example connection of unused pins
Table 1.36. Example connection of unused pins
Pin name Ports P0, P1, P3 to P7 Connection After setting for input mode, connect every pin to VSS (pull-down); or after setting for output mode, leave these pins open. Open Connect to VCC Connect to VSS
XOUT (Note) AVCC AVSS, VREF
Note: With external clock input to XIN pin.
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Usage precaution Usage Precaution Timer A (timer mode)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16”. Reading the timer A0 register after setting a value in the timer A0 register with a count halted but before the counter starts counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16” by underflow or “000016” by overflow. Reading the timer A0 register after setting a value in the timer A0 register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again.
Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows: • The counter stops counting and a content of reload register is reloaded. • The TA0OUT pin outputs “L” level. • The interrupt request generated and the timer A0 interrupt request bit goes to “1”. (2) The timer A0 interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures: • Selecting one-shot timer mode after reset. • Changing operation mode from timer mode to one-shot timer mode. • Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0” after the above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer A0 interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures: • Selecting PWM mode after reset. • Changing operation mode from timer mode to PWM mode. • Changing operation mode from event counter mode to PWM mode. Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TA0OUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer A0 interrupt request bit goes to “1”. If the TA0OUT pin is outputting an “L” level in this instance, the level does not change, and the timer A0 interrupt request bit does not becomes “1”.
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Usage precaution
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value.
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated.
Timer X (timer mode)
(1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16”. Reading the timer A0 register after setting a value in the timer Xi register with a count halted but before the counter starts counting gets a proper value.
Timer X (event counter mode)
(1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16” by underflow or “000016” by overflow. Reading the timer Xi register after setting a value in the timer Xi register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again.
Timer X (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows: • The counter stops counting and a content of reload register is reloaded. • The TXiINOUT pin outputs “L” level. • The interrupt request generated and the timer Xi interrupt request bit goes to “1”. (2) The timer Xi interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures: • Selecting one-shot timer mode after reset. • Changing operation mode from timer mode to one-shot timer mode. • Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after the above listed changes have been made.
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M30201 Group
Usage precaution Timer X (pulse width modulation mode)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) The timer Xi interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures: • Selecting PWM mode after reset. • Changing operation mode from timer mode to PWM mode. • Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after the above listed changes have been made. (2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TXiINOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer Xi interrupt request bit goes to “1”. If the TXiINOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Xi interrupt request bit does not becomes “1”.
Timer X (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Xi interrupt request bit goes to “1”. (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Xi interrupt request is not generated.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an elapse of 1 µs or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by AD conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock.
Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When shifting to WAIT mode or STOP mode, the program stops after reading 8 bytes from the WAIT instruction and the instruction that sets all clock stop bits to “1” in the instruction queue. Therefore, insert a minimum of 8 NOPs after the WAIT instruction and the instruction that sets all clock stop bits to “1”. (3) When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with WAIT peripheral function clock stop bit set to “1”.
109
Mitsubishi microcomputers
M30201 Group
Usage precaution
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
(1) Reading address 0000016 • When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software. (2) Setting the stack pointer • The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset, generating any interrupt is prohibited. (3) External interrupt ________ ________ • When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear the interrupt request bit after changing the polarity. (4) Changing interrupt control register See "Changing Interrupt Control Register".
110
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
Electrical characteristics
Table 1.36. Absolute maximum ratings
Symbol
Vcc AVcc VI Supply voltage Analog supply voltage Input voltage RESET, CNVss, P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71, VREF, XIN P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71, VREF, XIN Ta = 25 °C
Parameter
Condition
Rated value
- 0.3 to 6.5 (Note 1) - 0.3 to 6.5 (Note 1) - 0.3 to Vcc + 0.3 (Note 2)
Unit
V V V
VO Pd Topr Tstg
Output voltage Power dissipation
- 0.3 to Vcc + 0.3 1000 (Note 3) - 20 to 85 (Note 4) - 40 to 150 (Note 5)
V mW °C °C
Operating ambient temperature Storage temperature
Note 1: Flash memory version: –0.3 to 7 (V) . Note 2: When writing to flash MCU, CNVss is –0.3 to 13 (V) . Note 3: Flat package (56P6S-A) is 300 mW. Note 4: Extended operating temperature version: -40 to 85 °C. When flash memory version is program/erase mode: 25±5 °C. Note 5: Extended operating temperature version: -65 to 150 °C.
111
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
Table 1.37. Recommended operating conditions (Note 1)
Symbol
Vcc
Parameter Supply voltage Analog supply voltage Supply voltage Analog supply voltage
HIGH input voltage P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71, XIN, RESET, CNVSS, LOW input voltage P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71, XIN, RESET, CNVSS
Min Mask ROM version Flash memory version
2.7 4.0
Standard Typ.
5.0 5.0 Vcc 0 0
Max.
5.5 5.5
Unit
V V V V
AVcc Vss AVss VIH V IL
0.8Vcc 0
Vcc 0.2Vcc - 10.0 10.0
V V mA mA
I OH (peak) HIGH peak output P00 to P07, P10 to P17, P30 to P35, P40 to P45, current P50 to P54, P60 to P67, P70, P71 I OL (peak) LOW peak output P00 to P07, P30 to P35, P40 to P45, current P50 to P54, P60 to P67, P70, P71 LOW peak output I OL (peak) current I OH (avg) I OL (avg) I OL (avg) HIGH average output current LOW average output current LOW average output current P10 to P17
HIGHPOWER LOWPOWER
30.0 10.0 - 5.0 5.0 mA mA
P00 to P07, P10 to P17, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71 P00 to P07, P30 to P35, P40 to P45, P50 to P54, P60 to P67, P70, P71 P10 to P17 Mask ROM version
HIGHPOWER LOWPOWER
mA
15.0 0 0 0 32.768 5.0 10 5 x VCC - 10.000 10 50 mA MHz MHz MHz kHz
f (XIN)
Main clock input oscillation frequency
Vcc=4.0V to 5.5V Vcc=2.7V to 4.0V
Flash memory version Vcc=4.0V to 5.5V f (XcIN) Subclock oscillation frequency
Note 1: Unless otherwise noted: VCC = 2.7V to 5.5V, Vss = 0V, Ta = – 20 to 85oC (Extended operating temperature version:– 40 to 85oC). Flash version: VCC = 4.0V to 5.5V, Vss = 0V, Ta = – 20 to 85oC (Extended operating temperature version:– 40 to 85oC.) Note 2: The average output current is an average value measured over 100ms. Note 3: Keep output current as follows: The sum of port P3 and P4 IOL (peak) is under 40 mA. The sum of port P1 IOL (peak) is under 60 mA. The sum of port P1, P3 and P4 IOH (peak) is under 40 mA. The sum of port P0, P5, P6 and P7 IOL (peak) is under 80 mA. The sum of port P0, P5, P6 and P7 IOH (peak) is under 80 mA. Note 4: Relationship between main clock oscillation frequency and supply voltage.
Highest operation frequency [MHz]
Main clock input oscillation frequency (Without wait)
10.0
5 x Vcc - 10.000MHz
3.5 0.0
2.7
4.0
5.5
Power supply voltage [V] (Main clock : no division)
112
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Table 1.38. Electrical characteristics (Note1)
Symbol
VOH VOH HIGH output voltage HIGH output voltage HIGH output voltage HIGH output voltage LOW output voltage LOW output voltage LOW output voltage LOW output voltage LOW output voltage LOW output voltage Hysteresis
Parameter
P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67,P70,P71 P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67, P70,P71 XOUT HIGHPOWER LOWPOWER XCOUT HIGHPOWER LOWPOWER P00 to P07,P30 to P35,P40 to P45 P50 to P54,P60 to P67,P70,P71 P00 to P07,P30 to P35,P40 to P45 P50 to P54,P60 to P67,P70,P71 P10 to P17 HIGHPOWER LOWPOWER P10 to P17 XOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER XOUT HIGHPOWER LOWPOWER TA0IN,TX0INOUT,TX1INOUT,TX2INOUT TB0IN,TB1IN INT0,INT1,CLK0,KI0 to KI7 RxD0, RxD1 RESET P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67 P70,P71, RESET, CNVss P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67, P70,P71, RESET, CNVss
Measuring condition
IO H = - 5 m A IOH = - 200 µA IO H = - 1 m A IOH = - 0.5 mA No load No load IOL = 5 mA IO L = 2 0 0 µ A IOL = 15mA IOL = 5 mA IOL = 200 µA IOL = 200 µA IOH = 1 mA IOH = 0.5 mA No load No load
Min.
3.0 4.7 3.0 3.0
Standard Unit Typ. Max.
V V
VOH
V 3.0 1.6 2.0
VOH VOL
V
V V
VOL
0.45 2.0 2.0 0.3 0.45 2.0 2.0 0
VOL
V
VOL VOL
V
V
VOL
V 0
VT+ -VT-
0.2 0.2 VI = 5V VI = 0V
0.8 1.8 5.0
V V µA
VT+ -VTII H
Hysteresis HIGH input current LOW input current Pull-up resistor
IIL
-5.0
µA kΩ MΩ MΩ V
RPULLUP RXIN RXCIN V RAM
P00 to P07,P10 to P17,P30 to P35, VI = 0V P40 to P45,P50 to P54,P60 to P67, P70,P71 XIN XCIN When clock is stopped f(XIN)=10MHz Square wave, no division I/O pin has no load f(XCIN)=32kHz Square wave f(XCIN)=32kHz When a WAIT instruction is executed (Note 2) Ta=25 C when clock is stopped Ta=85 C when clock is stopped
30.0
50.0 167.0 1.0 6.0
Feedback resistor Feedback resistor
RAM retention voltage
2.0 19.0 90.0 4.0 1.0 38.0
mA µA µA
Icc
Power supply current
µA 20.0
Note 1: Unless otherwise noted: VCC = 5V, VSS = 0V at Ta = -20 to 85oC, f(XIN) = 10MHz (Extended operating temprature version; -40 to 85oC) Note 2: With one timer operated using fC32.
113
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Table 1.39. A-D conversion characteristics (Note)
Symbol – – Parameter Resolution Absolute Sample & hold function not available accuracy Sample & hold function available(10bit) Sample & hold function available(8bit) RLADDER tCONV tCONV tSAMP VREF VIA Ladder resistance Conversion time(10bit) Conversion time(8bit) Sampling time Reference voltage Analog input voltage Measuring condition VREF =VCC
VREF =VCC = 5V VREF =VCC= 5V VREF = VCC = 5V
Min.
Standard Typ. Max. 10 ±3 ±3 ±2
Unit Bits LSB LSB LSB kohm µs µs µs V V
VREF =VCC
10 3.3 2.8 0.3 2 0
40
VCC VREF
Note : Unless otherwise noted: VCC =AVCC = VREF =5V, VSS =AVSS = 0V at Ta = -25oC, f(XIN) = 10MHz
114
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = -20 to 85oC(*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.40. External clock input
Symbol
tc tw(H) tw(L) tr tf External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time
Parameter
Standard Min. Max.
100 40 40 15 15
Unit
ns ns ns ns ns
Table 1.41. Timer A input (counter input in event counter mode)
Symbol
tc(TA) tw(TAH) tw(TAL) TA0IN input cycle time TA0IN input HIGH pulse width TA0IN input LOW pulse width
Parameter
Standard Min. Max.
100 40 40
Unit
ns ns ns
Table 1.42. Timer A input (gating input in timer mode)
Symbol
tc(TA) tw(TAH) tw(TAL) TA0IN input cycle time TA0IN input HIGH pulse width TA0IN input LOW pulse width
Parameter
Standard Min. Max.
400 200 200
Unit
ns ns ns
Table 1.43. Timer A input (external trigger input in one-shot timer mode)
Symbol
tc(TA) tw(TAH) tw(TAL) TA0IN input cycle time TA0IN input HIGH pulse width TA0IN input LOW pulse width
Parameter
Standard Min. Max.
200 100 100
Unit
ns ns ns
Table 1.44. Timer A input (external trigger input in pulse width modulation mode)
Symbol
tw(TAH) tw(TAL) TA0IN input HIGH pulse width TA0IN input LOW pulse width
Parameter
Standard Min. Max.
100 100
Unit
ns ns
Table 1.45. Timer A input (up/down input in event counter mode)
Symbol
tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TA0OUT input cycle time TA0OUT input HIGH pulse width TA0OUT input LOW pulse width TA0OUT input setup time TA0OUT input hold time
Parameter
Standard Min. Max.
2000 1000 1000 400 400
Unit
ns ns ns ns ns
115
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = -20 to 85oC(*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.46. Timer B input (counter input in event counter mode)
Symbol
tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Parameter
TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges)
Standard Min. Max.
100 40 40 200 80 80
Unit
ns ns ns ns ns ns
Table 1.47. Timer B input (pulse period measurement mode)
Symbol
tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width
Parameter
Standard Min. Max.
400 200 200
Unit
ns ns ns
Table 1.48. Timer B input (pulse width measurement mode)
Symbol
tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width
Parameter
Standard Min. Max.
400 200 200
Unit
ns ns ns
Table 1.49. Timer X input (counter input in event counter mode)
Symbol
tc(TX) tw(TXH) tw(TXL) TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width
Parameter
Standard Min. Max.
100 40 40
Unit
ns ns ns
Table 1.50. Timer X input (gate input in timer mode)
Symbol
tc(TX) tw(TXH) tw(TXL) TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width
Parameter
Standard Min. Max.
400 200 200
Unit
ns ns ns
Table 1.51. Timer X input (external trigger input in one-shot timer mode)
Symbol
tc(TX) tw(TXH) tw(TXL) TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width
Parameter
Standard Min. Max.
200 100 100
Unit
ns ns ns
116
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = -20 to 85oC(*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.52. Timer X input (pulse period measurement mode)
Symbol
tc(TX) tw(TXH) tw(TXL) TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width
Parameter
Standard Min. Max.
400 200 200
Unit
ns ns ns
Table 1.53. Timer X input (pulse width measurement mode)
Symbol
tc(TX) tw(TXH) tw(TXL) TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width
Parameter
Standard Min. Max.
400 200 200
Unit
ns ns ns
Table 1.54. Serial I/O
Symbol
tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLK0 input cycle time CLK0 input HIGH pulse width CLK0 input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time 0 30 90
Parameter
Standard Min. Max.
200 100 100 80
Unit
ns ns ns ns ns ns ns
_______
Table 1.55. External interrupt INTi inputs
Symbol
tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width
Parameter
Standard Min. Max.
250 250
Unit
ns ns
117
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
tc(TA) tw(TAH) TA0IN input tw(TAL) tc(UP) tw(UPH) TA0OUT input tw(UPL) TA0OUT input (Up/down input) During event counter mode TA0IN input
(When count on falling edge is selected)
VCC = 5V
th(TIN–UP)
tsu(UP–TIN)
TA0IN input
(When count on rising edge is selected)
tc(TB) tw(TBH) TBiIN input tw(TBL) tc(TX) tw(TXH) TXiINOUT input tw(TXL) tc(CK) tw(CKH) CLK0 tw(CKL) TxDi td(C–Q) RxDi tw(INL) INTi input tw(INH) tsu(D–C) th(C–D) th(C–Q)
118
Mitsubishi microcomputers
M30201 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Table 1.56. Electrical characteristics (Note 1)
Symbol
VOH HIGH output voltage HIGH output voltage HIGH output voltage LOW output voltage LOW output voltage LOW output voltage LOW output voltage Hysteresis
Parameter
P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67,P70,P71 XOUT HIGHPOWER LOWPOWER XCOUT HIGHPOWER LOWPOWER P00 to P07,P30 to P35,P40 to P45 P50 to P54,P60 to P67,P70,P71 P10 to P17 HIGHPOWER LOWPOWER XOUT HIGHPOWER LOWPOWER XOUT HIGHPOWER LOWPOWER TA0IN,TX0INOUT,TX1INOUT,TX2INOUT TB0IN,TB1IN INT0,INT1,CLK0,KI0 to KI7 RxD0, RxD1 RESET P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67, P70,P71, RESET, CNVss P00 to P07,P10 to P17,P30 to P35, P40 to P45,P50 to P54,P60 to P67, P70,P71, RESET, CNVss
Measuring condition
IOH = - 1mA IOH = - 1 mA IOH = - 50 µA No load No load IOL = 1 mA IOL = 3 mA IOL = 1 mA IOH = 0.1 mA IOH = 50 µA No load No load
Min.
2.5 2.5 2.5
Standard Unit Typ. Max.
V V 3.0 1.6 0.5 0.5 0.5 0.5 V 0.5 0 V 0
VOH
VOH VOL
V
V
VOL
V
VOL
VOL
VT+ -VT-
0.2
0.8
V
VT+ -VTII H
Hysteresis HIGH input current LOW input current Pull-up resistor
0.2 VI = 3 V
1.8 4.0
V µA
II L
VI = 0 V
-4.0
µA kΩ MΩ MΩ V
RPULLUP RXIN RXIN V RAM
P00 to P07,P10 to P17,P30 to P35, VI = 0 V P40 to P45,P50 to P54,P60 to P67, P70,P71 XIN XIN When clock is stopped f(XIN)=3.5MHz Square wave, no division f(XCIN)=32kHz Square wave f(XCIN)=32kHz When a WAIT instruction is executed Oscillation capacity HIGH (Note 2) f(XCIN)=32kHz When a WAIT instruction is executed Oscillation capacity LOW (Note 2) Ta=25 C when clock is stopped Ta=85 C when clock is stopped
66.0
120.0 3.0 10.0
500.0
Feedback resistor Feedback resistor
RAM retention voltage
2.0 3.5 40.0 7.0
mA µA
Icc
Power supply current
I/O pin has no load
2.8
µA
0.9
µA
1.0 µA 20.0
Note 1: Unless otherwise noted: VCC = 3V, VSS = 0V at Ta = -20 to 85oC, f(XIN) = 3.5MHz) (Extended operating temprature version; -40 to 85oC) Note 2: With one timer operated using fC32.
119
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
Table 1.57. A-D conversion characteristics (Note)
Symbol – – RLADDER tCONV VREF VIA Parameter Resolution Absolute Sample & hold function not available accuracy (8bit) Ladder resistance Conversion time(8bit) Reference voltage Analog input voltage Measuring condition VREF =VCC
VREF =VCC = 3V, ØAD = fAD VREF =VCC
Min.
Standard Typ. Max. 10 ±2
Unit Bits LSB kohm µs V V
10 14.0 2.7 0
40 VCC VREF
Note : Unless otherwise noted: VCC =AVCC = VREF =3V, VSS =AVSS = 0V at Ta = 25oC, f(XIN) = 3.5MHz.
120
Mitsubishi microcomputers
M30201 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = -20 to 85oC(*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.58. External clock input
Symbol
tc tw(H) tw(L) tr tf External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time
Parameter
Standard Min. Max.
286 120 120 18 18
Unit
ns ns ns ns ns
Table 1.59. Timer A input (counter input in event counter mode)
Symbol
tc(TA) tw(TAH) tw(TAL) TA0IN input cycle time TA0IN input HIGH pulse width TA0IN input LOW pulse width
Parameter
Standard Min. Max.
300 120 120
Unit
ns ns ns
Table 1.60. Timer A input (gating input in timer mode)
Symbol
tc(TA) tw(TAH) tw(TAL) TA0IN input cycle time TA0IN input HIGH pulse width TA0IN input LOW pulse width
Parameter
Standard Min. Max.
1200 600 600
Unit
ns ns ns
Table 1.61. Timer A input (external trigger input in one-shot timer mode)
Symbol
tc(TA) tw(TAH) tw(TAL) TA0IN input cycle time TA0IN input HIGH pulse width TA0IN input LOW pulse width
Parameter
Standard Min. Max.
600 300 300
Unit
ns ns ns
Table 1.62. Timer A input (external trigger input in pulse width modulation mode)
Symbol
tw(TAH) tw(TAL) TA0IN input HIGH pulse width TA0IN input LOW pulse width
Parameter
Standard Min. Max.
300 300
Unit
ns ns
Table 1.63. Timer A input (up/down input in event counter mode)
Symbol
tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TA0OUT input cycle time TA0OUT input HIGH pulse width TA0OUT input LOW pulse width TA0OUT input setup time TA0OUT input hold time
Parameter
Standard Min. Max.
6000 3000 3000 1200 1200
Unit
ns ns ns ns ns
121
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = -20 to 85oC(*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.64. Timer B input (counter input in event counter mode)
Symbol
tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL)
Parameter
TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges)
Standard Min. Max.
300 120 120 600 320 320
Unit
ns ns ns ns ns ns
Table 1.65. Timer B input (pulse period measurement mode)
Symbol
tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width
Parameter
Standard Min. Max.
1200 600 600
Unit
ns ns ns
Table 1.66. Timer B input (pulse width measurement mode)
Symbol
tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width
Parameter
Standard Min. Max.
1200 600 600
Unit
ns ns ns
Table 1.67. Timer X input (counter input in event counter mode)
Symbol
tc(TX) tw(TXH) tw(TXL) TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width
Parameter
Standard Min. Max.
300 120 120
Unit
ns ns ns
Table 1.68. Timer X input (gate input in timer mode)
Symbol
tc(TX) tw(TXH) tw(TXL) TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width
Parameter
Standard Min. Max.
1200 600 600
Unit
ns ns ns
Table 1.69. Timer X input (external trigger input in one-shot timer mode)
Symbol
tc(TX) tw(TXH) tw(TXL) TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width
Parameter
Standard Min. Max.
600 300 300
Unit
ns ns ns
122
Mitsubishi microcomputers
M30201 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = -20 to 85oC(*) unless otherwise specified) * Extended operating temprature version; -40 to 85oC Table 1.70. Timer X input (pulse period measurement mode)
Symbol
tc(TX) tw(TXH) tw(TXL) TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width
Parameter
Standard Min. Max.
1200 600 600
Unit
ns ns ns
Table 1.71. Timer X input (pulse width measurement mode)
Symbol
tc(TX) tw(TXH) tw(TXL) TXiINOUT input cycle time TXiINOUT input HIGH pulse width TXiINOUT input LOW pulse width
Parameter
Standard Min. Max.
1200 600 600
Unit
ns ns ns
Table 1.72. Serial I/O
Symbol
tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLK0 input cycle time CLK0 input HIGH pulse width CLK0 input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time 0 50 90
Parameter
Standard Min. Max.
300 150 150 160
Unit
ns ns ns ns ns ns ns
_______
Table 1.73. External interrupt INTi inputs
Symbol
tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width
Parameter
Standard Min. Max.
380 380
Unit
ns ns
123
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
tc(TA) tw(TAH) TA0IN input tw(TAL) tc(UP) tw(UPH) TA0OUT input tw(UPL) TA0OUT input (Up/down input) During event counter mode TA0IN input
(When count on falling edge is selected)
VCC = 3V
th(TIN–UP)
tsu(UP–TIN)
TA0IN input
(When count on rising edge is selected)
tc(TB) tw(TBH) TBiIN input tw(TBL) tc(TX) tw(TXH) TXiINOUT input tw(TXL) tc(CK) tw(CKH) CLK0 tw(CKL) TxDi td(C–Q) RxDi tw(INL) INTi input tw(INH) tsu(D–C) th(C–D) th(C–Q)
124
Mitsubishi microcomputers
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Description (Flash memory version) Outline Performance
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.74 shows the outline performance of the M30201 (flash memory version).
Table 1.74. Outline Performance of the M30201 (flash memory version)
Item Power supply voltage Program/erase voltage
Performance 4.0V to 5.5 V (f(XIN)=10MHz) VPP=12V ± 5% (f(XIN)=10MHz, Ta=25±5°C) VCC=5V ± 10% (f(XIN)=10MHz, Ta=25±5°C)
Flash memory operation mode Erase block division Program method Erase method Program/erase control method Number of commands Program/erase count ROM code protect
Three modes (parallel I/O, standard serial I/O, CPU rewrite) See Figure 1.96 One division (3.5 Kbytes) (Note) In units of byte Collective erase Program/erase control by software command 6 commands 100 times Parallel I/O mode is supported.
User ROM area Boot ROM area
Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode.
125
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description (Flash memory version)
Flash Memory
The M30201 (flash memory version) contains the NOR type of flash memory that requires a high-voltage VPP power supply for program/erase operations, in addition to the VCC power supply for device operation. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode.
Microcomputer mode
Parallel I/O mode
CPU rewrite mode Standard serial I/O mode
0000016 SFR 0040016 RAM YYYYY16 RAM RAM SFR SFR
DF00016 Collective erasable/ programmable area DFDFF16 Boot ROM area (3.5K bytes) Boot ROM area (3.5K bytes)
XXXXX16 User ROM area FFFFF16 Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area. Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input. The user ROM area is selected when this address input is high and the boot ROM area is selected when this address input is low. Collective erasable/ programmable area User ROM area Collective erasable/ programmable area User ROM area
Type No. M30201F6
XXXXX16 F400016
YYYYY16 00BFF16
Figure 1.96. Block diagram of flash memory version
126
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash memory version)
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, the flash memory can be operated on by reading or writing to the flash memory control register and flash command register. Figure 1.97, Figure 1.98 show the flash memory control register, and flash command register respectively. Also, in CPU rewrite mode, the CNVSS pin is used as the VPP power supply pin. Apply the power supply voltage, VPPH, from an external source to this pin. In CPU rewrite mode, only the user ROM area shown in Figure 1.96 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block commands are issued for only the user ROM area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to internal RAM before it can be executed.
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FCON0 Bit symbol
Address
03B416
When reset
001000002
0
10
0
Bit name
Function 0: CPU rewrite mode is invalid 1: CPU rewrite mode is valid This bit can not write. The value, if read, turns out to be indeterminate. 0: CPU rewrite mode is invalid 1: CPU rewrite mode is valid Must always be set to "0". Must always be set to "1".
RW RW
FCON00 CPU rewrite mode select bit Reserved bit FCON02 CPU rewrite mode monitor flag Reserved bit Reserved bit
Nothing is assigned. In an attempt to write this bit, write "0". The value, if read, turns out to be "0". Reserved bit Must always be set to "0".
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FCON1 Bit symbol
Address
03B516
When reset
XXXXXX002
0
0
Bit name
Function Must always be set to "0".
RW RW
Reserved bit
Nothing is assigned. In an attempt to write these bits, write "0". The value, if read, turns out to be indeterminate.
Figure 1.97. Flash memory control register
Flash command register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FCMD
Address
03B616
When reset
0016 RW RW
Function Writing of software command •Read command •Program command •Program verify command •Erase command •Erase verify command •Reset command "0016" "4016" "C016" "2016" +"2016" "A016" "FF16" +"FF6"
Figure 1.98. Flash command register
127
Mitsubishi microcomputers
M30201 Group
CPU Rewrite Mode (Flash memory version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 1.96 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low (VSS). In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P52 pin high (VCC), the CNVSS pin high(VPPH), the CPU starts operating using the control program in the boot ROM area. This mode is called the “boot” mode. The control program in the boot ROM area can also be used to rewrite the user ROM area.
CPU rewrite mode operation procedure
The internal flash memory can be operated on to program, read, verify, or erase it while being placed onboard by writing commands from the CPU to the flash memory control register (addresses 03B416, 03B516) and flash command register (address 03B616). Note that when in CPU rewrite mode, the boot ROM area cannot be accessed for program, read, verify, or erase operations. Before this can be accomplished, a CPU write control program must be written into the boot ROM area in parallel input/output mode. The following shows a CPU rewrite mode operation procedure.
(1) Apply VPPH to the CNVSS/VPP pin and VCC to the port P52 pin for reset release. Or the user can jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU write control program. In this case, set the CPU write mode select bit of the flash memory control register to “1” before applying VPPH to the CNVSS/VPP pin. (2) After transferring the CPU write control program from the boot ROM area to the internal RAM, jump to this control program in RAM. (The operations described below are controlled by this program.) (3) Set the CPU rewrite mode select bit to “1”. (4) Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled. (5) Execute operation on the flash memory by writing software commands to the flash command register. Note 1: In addition to the above, various other operations need to be performed, such as for entering the data to be written to flash memory from an external source (e.g., serial I/O), initializing the ports, and writing to the watchdog timer.
(1) Apply VSS to the CNVSS/VPP pin. (2) Set the CPU rewrite mode select bit to “0”.
128
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash memory version)
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During erase/program mode, set BCLK to 5 MHz or less by changing the divide ratio. (2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use No interrupts can be used that look up the fixed vector table in the flash memory area. Maskable interrupts may be used by setting the interrupt vector table in a location outside the flash memory area.
129
Mitsubishi microcomputers
M30201 Group
CPU Rewrite Mode (Flash memory version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Commands
Table 1.75 lists the software commands available with the M30201 (flash memory version). When CPU rewrite mode is enabled, write software commands to the flash command register to specify the operation to erase or program. The content of each software command is explained below. Table 1.75. List of Software Commands (CPU Rewrite Mode)
First bus cycle Command Read Program Mode Write Write Address 03B616 03B616 Data (D0 to D7) 0016 4016 Write Program address Verify address 03B616 Verify address 03B616 Program data Verify data 2016 Verify data FF16 Second bus cycle Mode Address Data (D0 to D7)
Program verify
Write
03B616
C016
Read
Erase Erase verify
Write Write
03B616 03B616
2016 A016
Write Read
Reset
Write
03B616
FF16
Write
Read Command (0016) The read mode is entered by writing the command code “0016” to the flash command register in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D0–D7), 8 bits at a time. The read mode is retained intact until another command is written. After reset and after the reset command is executed, the read mode is set.
Program Command (4016) The program mode is entered by writing the command code “4016” to the flash command register in the first bus cycle. When the user execute an instruction to write byte data to the desired address (e.g., STE instruction) in the second bus cycle, the flash memory control circuit executes the program operation. The program operation requires approximately 20 µs. Wait for 20 µs or more before the user go to the next processing. During program operation, the watchdog timer remains idle, with the value “7FFF16” set in it. Note 1: The write operation is not completed immediately by writing a program command once. The user must always execute a program-verify command after each program command executed. And if verification fails, the user need to execute the program command repeatedly until the verification passes. See Figure 1.99 for an example of a programming flowchart.
130
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash memory version)
Program-verify command (C016) The program-verify mode is entered by writing the command code “C016” to the flash command register in the first bus cycle. When the user execute an instruction (e.g., LDE instruction) to read byte data from the address to be verified (the previously programmed address) in the second bus cycle, the content that has actually been written to the address is read out from the memory. The CPU compares this read data with the data that it previously wrote to the address using the program command. If the compared data do not match, the user need to execute the program and program-verify operations one more time. Erase command (2016 + 2016) The flash memory control circuit executes an erase operation by writing command code “2016” to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing. Before this erase command can be performed, all memory locations to be erased must have had data “0016” written to by using the program and program-verify commands. During erase operation, the watchdog timer remains idle, with the value “7FFF16 set in it. Note 1: The erase operation is not completed immediately by writing an erase command once. The user must always execute an erase-verify command after each erase command executed. And if verification fails, the user need to execute the erase command repeatedly until the verification passes. See Figure 1.99 for an example of an erase flowchart. Erase-verify command (A016) The erase-verify mode is entered by writing the command code “A016” to the flash command register in the first bus cycle. When the user execute an instruction to read byte data from the address to be verified (e.g., LDE instruction) in the second bus cycle, the content of the address is read out. The CPU must sequentially erase-verify memory contents one address at a time, over the entire area erased. If any address is encountered whose content is not “FF16” (not erased), the CPU must stop erase-verify at that point and execute erase and erase-verify operations one more time. Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. In this case, however, the user does not need to write data “0016” to memory before erasing.
131
Mitsubishi microcomputers
M30201 Group
CPU Rewrite Mode (Flash memory version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset command (FF16 + FF16) The reset command is used to stop the program command or the erase command in the middle of operation. After writing command code “4016” or “2016” twice to the flash command register, write command code “FF16” to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. The program command or erase command is disabled, with the flash memory placed in read mode.
Program
Erase
Start
Start
Address = first location
YES
Loop counter : X=0 Write program command Write : 4016
All bytes = "0016"? NO Program all bytes = "0016" Address = First address Loop counter X=0
Write program data/ address
Write : Program data
Duration = 20 µs
Write erase command Write erase command Duration = 20ms
Write:2016 Write:2016
Loop counter : X=X+1
Write program verify command
Write : C016
Loop counter X=X+1 Write erase verify command/address
Duration = 6 µs
Write:A016
X=25 ? NO FAIL
YES
Duration = 6µs
X=1000 ?
YES
PASS Verify OK ? PASS Verify OK ? FAIL
Next address NO FAIL
NO Verify OK? PASS Last address? PASS Verify OK? FAIL Read: expect value=FF16
Next address ?
NO
Last address ?
Write read command
Write read command
Write : 0016
Write read command PASS
Write read command FAIL
Write:0016
PASS
FAIL
Figure 1.99. Program and erase execution flowchart in the CPU rewrite mode
132
Mitsubishi microcomputers
M30201 Group
Appendix Parallel I/O Mode (Flash memory version)
Description of Pin Function (Flash Memory Parallel I/O Mode)
Pin name VCC,VSS CNVSS RESET XIN XOUT AVCC, AVSS VREF P00 to P07 P10 to P17 P30 to P33 P34 to P35 P40 P41 P43 P42, P44, P45 P50 P51 P52 P53, P54 P60 to P63 P64 to P67 P70 to P71 Signal name Power supply input CNVSS Reset input Clock input Clock output Analog power supply input Reference voltage input Data I/O D0 to D7 Address input A8 to A15 Address input A4 to A7 Input port P3 WE input OE input CE input Input port P4 Address input A17 VRFY input Input port P5 Input port P5 Address input A0 to A3 Input port P6 Input port P7 I I/O I I I I I I I I I I I I I I I I I O I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Function Apply 5 V ± 10 % to the Vcc pin and 0 V to the Vss pin. Apply 12 V ± 5 % to the CNVSS pin. Connect this pin to VSS. Connect a ceramic or crystal resonator between the XIN and XOUT pins. When entering an externally derived clock, enter it from XIN and leave XOUT open. Connect AVSS to Vss and AVcc to Vcc, respectively. Connect this pin to VSS. These are data D0–D7 input/output pins. These are address A8–A15 input pins. These are address A4–A7 input pins. Enter low signals to these pins. This is a WE input pin. This is a OE input pin. This is a CE input pin. Enter high signals or low signals to these pins. This is address A17 input pin. Apply VIH (5 V) to this pin when VPP = VPPH (12 V), or VIL (0 V) when VPP = VPPL (5 V). Enter low signal to this pin. Enter high signals or low signals to these pins. These are address A0–A3 input pins. Enter high signals or low signals to these pins. Enter high signals or low signals to these pins.
133
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Parallel I/O Mode (Flash memory version)
Parallel I/O Mode
The parallel I/O mode is entered by making connections shown in Figures 1.101 and 1.102 and then turning the VPPH power supply on. In this mode, the M30201 (flash memory version) operates in a manner similar to the NOR flash memory M5M28F101 from Mitsubishi. Note, however, that there are some differences with regard to the functions not available with the microcomputer (function of read device identification code) and matters related to memory capacity. Table 1.76 shows pin relationship between the M30201 and M5M28F101 in parallel I/O mode.
Table 1.76. Pin relationship in parallel I/O mode
M30201(flash memory version) VCC VSS Address input Data I/O OE input CE input WE input VRFY input (Note) VCC VSS P60 to P63, P30 to P33, P10 to P17, P50 P00 to P07 P41 P43 P40 P51 VCC VSS A0 to A15, A17 D0 to D7 OE CE WE M5M28F101
Note: The VRFY input only selects read-only or read/write mode, and does not have any pin associated with it on the M5M28F101.
Microcomputer mode
Parallel I/O mode
CPU rewrite mode Standard serial I/O mode
0000016 SFR 0040016 RAM YYYYY16 RAM RAM SFR SFR
DF00016 Collective erasable/ programmable area DFDFF16 Boot ROM area (3.5K bytes) Boot ROM area (3.5K bytes)
XXXXX16 User ROM area FFFFF16 Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area. Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input. The user ROM area is selected when this address input is high and the boot ROM area is selected when this address input is low. Collective erasable/ programmable area User ROM area Collective erasable/ programmable area User ROM area
Type No. M30201F6
XXXXX16 F400016
YYYYY16 00BFF16
Figure 1.100. Block diagram of flash memory version
134
Mitsubishi microcomputers
M30201 Group
Appendix Parallel I/O Mode (Flash memory version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A0
AVSS P60/AN0 VREF AVCC P54/CKOUT/AN54
1 2 3
52 51 50
P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P00/KI0
A1
A2
A3
P53/CLKS/AN53
4 5 6
49 48 47
VRFY
A17
VPPH
P52/CLK0/AN52 P51/RXD0/AN51 P50/TXD0/AN50 CNVSS P71/TB1IN/XCIN
7 8 9
46 45 44
D0
M30201F6SP
Connect oscillator circuit.
VCC
CE
P70/TB0IN/XCOUT RESET XOUT VSS XIN VCC P45/TX2INOUT P44/INT1/TX1INOUT P43/INT0/TX0INOUT P42/RXD1
10 11 12
43 42 41
P01/KI1 P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P10(LED0) P11(LED1) P12(LED2) P13(LED3) P14(LED4) P15(LED5) P16(LED6) P17(LED7) P30 P31 P32
D1 D2
D3
D4
13 14 15
40 39 38
D5
D6
D7
16 17 18
37 36
A8
A9
19 20 21
35 34 33
A10
A11 A12 A13 A14 A15 A4 A5 A6
OE
WE
P41/TA0OUT P40/TA0IN/TXD1 P35 P34 P33
22 23 24
32 31 30
A7
VSS
25 26
29 28 27
Figure 1.101. Pin connection diagram in parallel I/O mode (1)
135
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Parallel I/O Mode (Flash memory version)
A0
A1
P52/CLK0/AN52 P53/CLKS/AN53 P54/CKOUT/AN54
A2 A3
P66/AN6
VRFY
A17
VPPH
P51/RXD0/AN51 P50/TXD0/AN50 CNVSS P71/TB1IN/XCIN P70/TB0IN/XCOUT RESET
N.C. XOUT VSS XIN
1 2
3 4 5
6 7 8
9 10
11 12 13
14
56 55 54 53 52 51 50 49 48 47 46 45 44 43
N.C. AVCC VREF
P60/AN0 AVSS P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5
42 41
40 39 38
P67/AN7
N.C. P00/KI0
P01/KI1 P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P10(LED0) P11(LED1) P12(LED2) P13(LED3)
D0 D1 D2 D3 D4 D5 D6
A8 A10 A11
Connect oscillator circuit.
M30201F6FP M30201F6TFP
37 36 35
34 33 32
31 30 29
VCC
VCC P45/TX2INOUT
P44/INT1/TX1INOUT P43/INT0/TX0INOUT
D7
A9
P40/TA0IN/TXD1 N.C.
P41/TA0OUT
A15
OE
A14 A13
Figure 1.102. Pin connection diagram in parallel I/O mode (2)
136
VSS
A7
A5
A12
WE
A6
A4
P33 P32 P31 P30 P17(LED7) P16(LED6) P15(LED5) P14(LED4)
P42/RXD1
P35 P34
15 16 17 18 19 20 21 22 23 24 25 26 27 28
CE
Mitsubishi microcomputers
M30201 Group
Appendix Parallel I/O Mode (Flash memory version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.100 can be rewritten. In the boot ROM area, an erase block operation is applied to only one 3.5 K byte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, the user does not need to write to the boot ROM area.
Functional Outline (Parallel I/O Mode)
In parallel I/O mode, bus operation modes—Read, Output Disable, Standby, and Write—are selected by _____ _____ _____ the status of the CE, OE, WE, VRFY, and CNVSS input pins. The contents of erase, program, and other operations are selected by writing a software command. The data in memory can only be read out by a read after software command input. Program and erase operations are controlled using software commands.
Table 1.77. Relationship between control signals and bus operation modes
Mode Read only Read Output disabled Stand by Read Read/ Write Output disabled Stand by Write Note: X can be VIL or VIH. Pin name CE VIL VIL VIH VIL VIL VIH VIL OE VIL VIH X VIL VIH X VIH WE VIH VIH X VIH VIH X VIL VRFY VIL VIL VIL VIH VIH VIH VIH VPP VPPH VPPH VPPH VPPH VPPH VPPH VPPH D0 to D7 Data output Hi-Z Hi-Z Data output Hi-Z Hi-Z Data input
137
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Parallel I/O Mode (Flash memory version)
The following explains about bus operation modes, software commands, and status register.
Bus Operation Modes
Read-only mode is entered by applying VPPH to the CNVSS pin and a low voltage to the VRFY pin. Read-only mode has three states: Read, Output Disable, and Standby which are selected by _____ _____ ______ setting the CE, OE, and WE pins high or low. Read-write mode is entered by applying VPPH to the CNVSS pin and a high voltage to the VRFY pin. Read-write mode has four states: Read, Output Disable, Standby, and Write which are selected by _____ _____ ______ setting the CE, OE, and WE pins high or low. Read ______ _____ _____ The Read mode is entered by pulling the WE pin high when the CE and OE pins are low. In Read mode, the data corresponding to each software command entered is output from the data I/O pins D0–D7. Output Disable _____ _____ _____ The Output Disable mode is entered by pulling the CE pin low and the WE and OE pins high. Also, the data I/O pins are placed in the high-impedance state. Standby _____ The Standby mode is entered by driving the CE pin high. Also, the data I/O pins are placed in the high-impedance state. Write The Write mode is entered by applying VPPH to the CNVSS pin and a high voltage to the VRFY pin _____ _____ _____ and then pulling the WE pin low when the CE pin is low and OE pin is high. In this mode, the device accepts the software commands or write data entered from the data I/O pins. A program, erase, or some other operation is initiated depending on the content of the software command entered here. _____ The input data such as address is latched at the falling edge of WE pin. The input data such as _____ software command is latched at the rising edge of WE pin.
138
Mitsubishi microcomputers
M30201 Group
Appendix Parallel I/O Mode (Flash memory version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Commands
Table 1.78 lists the software commands available with the M30201 (flash memory version). By entering a software command from the data I/O pins (D0–D7) in Write mode, specify the content of the operation, such as erase or program operation, to be performed. The following explains the content of each software command.
Table 1.78. Software command list (parallel I/O mode)
First bus cycle Command Read Program Mode Write Write Address x x Data (D0 to D7) 0016 4016 Write Program address x Program data Verify data 2016 Verify data FF16 Second bus cycle Mode Address Data (D0 to D7)
Program verify
Write
x
C016
Read
Erase Erase verify
Write Write
x Verify address x
2016 A016
Write Read
x x
Reset
Write
FF16
Write
x
Read Command (0016) The read mode is entered by writing the command code “0016” in the first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data I/O pins (D0–D7). The read mode is retained intact until another command is written. After reset and after the reset command is executed, the read mode is set. Program Command (4016) The program mode is entered by writing the command code “4016” in the first bus cycle. When an address and data to be program is write in the second bus cycle, the flash memory control circuit executes the program operation. The program operation requires approximately 20 µs. Wait for 20 µs or more before the user go to the next processing. Note 1: The write operation is not completed immediately by writing a program command once. The user must always execute a program-verify command after each program command executed. And if verification fails, the user need to execute the program command repeatedly until the verification passes. See Figure 1.103 for an example of a programming flowchart.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Parallel I/O Mode (Flash memory version)
Program-verify command (C016) The program-verify mode is entered by writing the command code “C016” in the first bus cycle and the verify data is output from the data I/O pins (D0–D7) in the second bus cycle. Erase command (2016 + 2016) The flash memory control circuit executes an erase operation by writing command code “2016” in the first bus cycle and the same command code again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing. Before this erase command can be performed, all memory locations to be erased must have had data “0016” written to by using the program and program-verify commands. Note 1: The erase operation is not completed immediately by writing an erase command once. The user must always execute an erase-verify command after each erase command executed. And if verification fails, the user need to execute the erase command repeatedly until the verification passes. See Figure 1.103 for an example of an erase flowchart. Erase-verify command (A016) The erase-verify mode is entered by writing the command code “A016” in the first bus cycle and the verify data is output from the data I/O pins (D0–D7) in the second bus cycle. Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. In this case, however, the user does not need to write data “0016” to memory before erasing.
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Appendix Parallel I/O Mode (Flash memory version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset command (FF16 + FF16) The reset command is used to stop the program command or the erase command in the middle of operation. After writing command code “4016” or “2016” twice, write command code “FF16” in the first bus cycle and the same command code again in the second bus cycle. The program command or erase command is disabled, with the flash memory placed in read mode.
Program
Erase
Start
Start
Address = first location
YES
Loop counter : X=0 Write program command Write : 4016
All bytes = "0016"? NO Program all bytes = "0016" Address = First address Loop counter X=0
Write program data/ address
Write : Program data
Duration = 20 µs
Write erase command Write erase command Duration = 20ms
Write:2016 Write:2016
Loop counter : X=X+1
Write program verify command
Write : C016
Loop counter X=X+1 Write erase verify command/address
Duration = 6 µs
Write:A016
X=25 ? NO FAIL
YES
Duration = 6µs
X=1000 ?
YES
PASS Verify OK ? PASS Verify OK ? FAIL
Next address NO FAIL
NO Verify OK? PASS Last address? PASS Verify OK? FAIL Read: expect value=FF16
Next address ?
NO
Last address ?
Write read command
Write read command
Write : 0016
Write read command PASS
Write read command FAIL
Write:0016
PASS
FAIL
Figure 1.103. Program and erase execution flowchart in the CPU rewrite mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Parallel I/O Mode (Flash memory version)
Protect function
In parallel I/O mode, the internal flash memory has the “protect function” available. This function protects the flash memory contents from being read or rewritten easily. Depending on the content at the protect control address (FFFFF16) in parallel I/O mode, this function inhibits the flash memory contents against read or modification. The protect control address (FFFFF16) is shown in Figure 1.104. (This address exists in the user ROM area.) The protect function is enabled by setting one of the two protect set bits to “0”, so that the internal flash memory contents are inhibited against read or modification. The protect function is disabled by setting both of the two protect reset bits to “00”, so that the internal flash memory contents can be read or modified. Once the protect function is set, the user cannot change settings of the protect clear bits while in parallel I/O mode. Settings of the protect reset bits can only be changed in CPU rewrite mode.
Protect control address
b7 b6 b5 b4 b3 b2 b1 b0
1111
Symbol ROMCP
Address FFFFF16
When shipping FF16
Bit symbol
Bit name
Function Always set to "1".
b5 b4
Reserved bit
ROMCR
Protect reset bit
00: Protect removed 01: Protect set bit effective 10: Protect set bit effective 11: Protect set bit effective
b7 b6
ROMCP
Protect set bit
00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled
Note 1: When protect is turned on, the flash memory version is protected against readout or modification in parallel I/O mode. Note 2: The protect reset bits can be used to turn off protect . However, since these bits cannot be changed in parallel I/O mode, they need to be rewritten in CPU rewrite mode.
Figure 1.104. Protect control address
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Appendix Standard Serial I/O Mode (Flash Memory Version)
Pin functions (Flash memory standard serial I/O mode)
Pin VCC,VSS CNVSS RESET XIN XOUT AVCC, AVSS VREF P00 to P07 P10 to P17 P30 to P35 P40 to P45 P54 P50 P51 P52 P53 Name Power input CNVSS Reset input I I I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description Apply 5V ± 10 % to Vcc pin and 0 V to Vss pin. Mode entry pin. Apply 12V ± 5 % to this pin. Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect AVSS to Vss and AVcc to Vcc, respectively.
Clock input Clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P3 Input port P4 Input port P5 TxD output RxD input SCLK input BUSY
I O
I I I I I I O I I
Enter the reference voltage for AD from this pin. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Serial data output pin. Serial data input pin. Mode entry pin. Supply "H" level when powering on MCU. When startup is completed this pin serves the serial input clock.
This pin sets the type of serial flash programming mode. •An "H" level input (mode 1) sets the mode to clock synchronous. I - O •An "L" level input (mode 2) sets the mode to clock asynchronous. > This pin changes to "output" after entry into standard serial I/O mode. I I Input "H" or "L" level signal or open. Input "H" or "L" level signal or open.
P60 to P67 P70 to P71
Input port P6 Input port P7
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Appendix Standard Serial I/O Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mode setup method
Signal
CNVSS RESET SCLK
Value
VPPH VSS VCC VCC (Note)
Note: Apply VCC when powering on MCU.
VSS
AVSS P60/AN0
1 2
3 4 5
6 7 8
9 10 11
12 13 14
15 16 17
18 19 20
21 22 23
24 25 26
52
51 50 49
48 47
46 45 44
43 42 41
40 39 38
37 36 35
34 33
32 31 30
29 28 27
P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 P00/KI0
P01/KI1 P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P10(LED0) P11(LED1) P12(LED2) P13(LED3) P14(LED4) P15(LED5) P16(LED6) P17(LED7) P30 P31 P32
VCC
VREF AVCC P54/CKOUT/AN54
P53/CLKS/AN53
BUSY
SCLK
RXD
TXD
CNVSS
P52/CLK0/AN52 P51/RXD0/AN51 P50/TXD0/AN50 CNVSS
P71/TB1IN/XCIN P70/TB0IN/XCOUT RESET
VSS
M30201F6SP
RESET
Connect oscillator circuit.
XOUT VSS XIN
VCC
P45/TX2INOUT P44/INT1/TX1INOUT P43/INT0/TX0INOUT
P42/RXD1 P41/TA0OUT P40/TA0IN/TXD1 P35 P34 P33
VCC
Figure 1.105. Pin connections for standard serial I/O mode (1)
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Appendix Standard Serial I/O Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mode setup method
Signal
CNVSS RESET SCLK
Value
VPPH VSS VCC VCC (Note)
BUSY
SCLK
VCC
Note: Apply VCC when powering on MCU.
P52/CLK0/AN52 P53/CLKS/AN53 P54/CKOUT/AN54
P60/AN0 AVSS P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5
VSS
R XD TXD CNVSS
56 55 54 53 52 51 50 49 48 47 46 45 44 43
N.C. AVCC VREF
P66/AN6
P51/RXD0/AN51 P50/TXD0/AN50 CNVSS P71/TB1IN/XCIN P70/TB0IN/XCOUT RESET N.C. XOUT VSS XIN VCC P45/TX2INOUT P44/INT1/TX1INOUT P43/INT0/TX0INOUT
Connect oscillator circuit.
RESET
VSS VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
42 41 40 39 38
P67/AN7 N.C. P00/KI0 P01/KI1 P02/KI2 P03/KI3 P04/KI4 P05/KI5 P06/KI6 P07/KI7 P10(LED0) P11(LED1) P12(LED2) P13(LED3)
M30201F6FP M30201F6TFP
37 36 35 34 33 32 31 30 29
Figure 1.106. Pin connections for serial I/O mode (2)
P42/RXD1 P41/TA0OUT P40/TA0IN/TXD1 N.C.
P33 P32 P31 P30 P17(LED7) P16(LED6) P15(LED5) P14(LED4)
P35 P34
15 16 17 18 19 20 21 22 23 24 25 26 27 28
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Appendix Standard Serial I/O Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is released, which is done when the P52 (SCLK) pin is "H" level, the CNVss pin "VppH" level. (In the ordinary command mode, set CNVss pin to "L" level.) This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figures 1.105 and 1.106 show the pin connections for the standard serial I/O mode. Serial data I/O uses UART0 and transfers the data serially in 8-bit units. Standard serial I/O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of P53 (BUSY) pin when the reset is released. To use standard serial I/O mode 1 (clock synchronized), set the P53 (BUSY) pin to "H" level and release the reset. The operation uses the four UART0 pins CLK0, RxD0, TxD0 and P53 (BUSY). The CLK0 pin is the transfer clock input pin through which an external transfer clock is input. The TxD0 pin is for CMOS output. The P53 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts. To use standard serial I/O mode 2 (clock asynchronized), set the P53 (BUSY) pin to "L" level and release the reset. The operation uses the two UART0 pins RxD0 and TxD0. In the standard serial I/O mode, only the user ROM area indicated in Figure 1.96 can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit are not accepted unless the ID code matches.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview of standard serial I/O mode 1 (clock synchronized)
In standard serial I/O mode 1, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using clock-synchronized serial I/O (UART0) and P53 (BUSY). Standard serial I/O mode 1 is engaged by releasing the reset with the P53 (BUSY) pin "H" level. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the CLK0 pin, and are then input to the MCU via the RxD0 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD0 pin. The TxD0 pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the P53 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the P53 (BUSY) pin is "L" level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Software Commands
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.79 lists software commands. In the standard serial I/O mode 1, erase operations, programs and reading are controlled by transferring software commands via the RxD0 pin. Software commands are explained here below. Table 1.79. Software commands (Standard serial I/O mode 1)
Control command 1 Page read FF16 2nd byte Address (middle) Address (middle) D016 SRD output SRD1 output 3rd byte Address (high) Address (high) 4th byte 5th byte 6th byte Data output Data input Data output Data input Data output Data input When ID is not verificate Not acceptable
2
Page program
4116
3 4 5 6
Erase all unlocked blocks Read status register Clear status register Read lockbit status
A716 7016 5016 7116
Data output to 259th byte Data Not input to acceptable 259th byte Not acceptable Acceptable Not acceptable Not acceptable
Address (middle) Address (low) Size (low)
Address (high) Address (middle) Size (high)
7 8
ID check function Download function
F516 FA16
Lock bit data output Address ID size (high) CheckData sum input
ID1
To ID7
Acceptable
9
Version data output function FB16
10 Boot area output function
FC16
Version data output Address (middle)
Version data output Address (high)
To Not required acceptable number of times Version Version Version Version Acceptable data data data data output output output output to 9th byte Data Data Data Not Data output output output output to acceptable 259th byte
Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) P53(BUSY)
FF16
A8 to A15
A16 to A23
data0
data255
Figure 1.107. Timing for page read Read Status Register Command This command reads status information. When the “7016” command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) P53(BUSY)
7016
SRD output
SRD1 output
Figure 1.108. Timing for reading the status register
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clear Status Register Command This command clears the bits (SR3–SR4) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the P53 (BUSY) signal changes from the “H” to the “L” level.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) P53(BUSY)
Figure 1.109. Timing for clearing the status register
5016
Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “4116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the P53 (BUSY) signal changes from the “H” to the “L” level. The result of the page program can be known by reading the status register. For more information, see the section on the status register.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) P53(BUSY)
4116
A8 to A15
A16 to A23
data0
data255
Figure 1.110. Timing for the page program
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Transfer the “A716” command code with the 1st byte. (2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the P53 (BUSY) signal changes from the “H” to the “L” level. The result of the erase operation can be known by reading the status register.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) P53(BUSY)
A716
D016
Figure 1.111. Timing for erasing all unlocked blocks Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following. (1) Transfer the “7116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. Write the highest address of the specified block for addresses A8 to A23. The M30201 (flash memory version) does not have the lock bit, so the read value is always “1” (block unlock).
CLK0 7116 A8 to A15 A16 to A23
RxD0 (M16C reception data) TxD0 (M16C transmit data) P53(BUSY)
DQ6
Figure 1.112. Timing for reading lock bit status
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM.
CLK0
Program data
RxD0 (M16C reception data) TxD0 (M16C transmit data) P53(BUSY)
FA16
Data size (low)
Check sum
Program data
Data size (high)
Figure 1.113. Timing for download
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the “FB16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) P53(BUSY)
FB16
'V'
'E'
'R'
'X'
Figure 1.114. Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the “FC16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the fall of the clock.
CLK0 A8 to A15 A16 to A23
RxD0 (M16C reception data) TxD0 (M16C transmit data) P53(BUSY)
FC16
data0
data255
Figure 1.115. Timing for boot ROM area output
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the “F516” command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) P53(BUSY)
F516
DF16
FF16
0F16
ID size
ID1
ID7
Figure 1.116. Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses.
Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 Reset vector
4 bytes
Figure 1.117. ID code storage addresses
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (7016). Also, the status register is cleared by writing the clear status register command (5016). Table 1.80 gives the definition of each status register bit. After clearing the reset, the status register outputs “8016”. Table 1.80. Status register (SRD) SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name
Status bit Reserved Erase bit Program bit Reserved Reserved Reserved Reserved Definition "1" Ready Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally -
Status bit (SR7) The status bit indicates the operating status of the flash memory. When power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase operation, but it is set back to “1” when the operation ends. Erase Status (SR5) The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. Program Status (SR4) The program status reports the operating status of the auto write operation. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 1.81 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and the flag status is maintained even after the reset. Table 1.81. Status register 1 (SRD1) SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) Status name Boot update completed bit Reserved Reserved Checksum match bit ID check completed bits Definition "1"
Update completed
"0" Not update Mismatch Not verified Verification mismatch Reserved Verified Normal operation -
Match 00 01 10 11 Time out -
SR9 (bit1) SR8 (bit0)
Data receive time out Reserved
Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. Check Sum Consistency Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Reception Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example Circuit Application for The Standard Serial I/O Mode 1
The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information.
Clock input P53 output Data input
Data output
CLK0 P53(BUSY)
RXD0 TXD0
VPP
M30201 Flash memory version
CNVss
(1) Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. (2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch.
Figure 1.118. Example circuit application for the standard serial I/O mode 1
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview of standard serial I/O mode 2 (clock asynchronized)
In standard serial I/O mode 2, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART0). Standard serial I/O mode 2 is engaged by releasing the reset with the P53 (BUSY) pin "L" level. The TxD0 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After the reset is released, connections can be established at 9,600 bps when initial communications (Figure 1.119) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by executing software commands. However, communication errors may occur because of the oscillation frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. Data and status registers in memory can be read after transmitting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained initial communications with peripheral units, how frequency is identified and software commands.
Initial communications with peripheral units
After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation frequency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (Figure 1.119). (1) Transmit "B016" from a peripheral unit. If the oscillation frequency input by the main clock is 10 MHz, the MCU with internal flash memory outputs the "B016" check code. If the oscillation frequency is anything other than 10 MHz, the MCU does not output anything. (2) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (3) The MCU with internal flash memory outputs the "B016" check code and initial communications end successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. *1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock.
Peripheral unit
MCU with internal flash memory Reset
(1) Transfer "B016" (2) Transfer "0016" 16 times At least 15ms transfer interval 15 th 16th
"B016" "B016" 1st 2nd "0016" "0016" "0016" "0016" "B016" (3) Transfer check code "B016" If the oscillation frequency input by the main clock is 10 MHz, the MCU outputs "B016". If other than 10 MHz, the MCU does not output anything.
The bit rate generator setting completes (9600bps)
Figure 1.119. Peripheral unit and initial communication
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
How frequency is identified
When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 10 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 1.82 gives the operation frequency and the baud rate that can be attained for.
Table 1.82 Operation frequency and the baud rate
Operation frequency (MH Z) 10MH Z 8MH Z 7.3728MH Z 6MH Z 5MH Z 4.5MH Z 4.194304MH Z 4MH Z 3.58MH Z 3MH Z 2MH Z Baud rate 9,600bps √ √ √ √ √ √ √ √ √ √ √ Baud rate 19,200bps √ √ √ √ √ √ √ √ √ √ – Baud rate 38,400bps – – √ √ – – √ – √ √ – Baud rate 57,600bps √ √ √ – – √ – – √ – –
√ : Communications possible – : Communications not possible
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Software Commands
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.83 lists software commands. In the standard serial I/O mode 2, erase operations, programs and reading are controlled by transferring software commands via the RxD0 pin. Standard serial I/O mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software commands of standard serial I/O mode 1. Software commands are explained here below. Table 1.83. Software commands (Standard serial I/O mode 2)
Control command 1 2 Page read Page program
1st byte transfer
2nd byte Address (middle) Address (middle) D016 SRD output Address (middle) Address (low)
3rd byte Address (high) Address (high)
4th byte 5th byte 6th byte Data output Data input Data output Data input Data output Data input Data output to 259th byte Data input to 259th byte
FF16 4116
When ID is not verified Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable
3 4 5 6 7 8
Erase all unlocked blocks Read status register Clear status register Read lock bit status Code processing function Download function
A716 7016 5016 7116 F516
SRD1 output Address (high) Lock bit data output Address (high) Checksum Version data output Data output
Address (middle) Size FA16 Size (low) (high) Version data output Address (middle) B016 B116 B216 B316 Version data output Address (high)
9
Version data output function
FB16
ID1 To Data required input number of times Version Version data data output output Data output Data output
ID size
To ID7
Acceptable Not acceptable
10 Boot ROM area output function 11 Baud rate 9600 12 Baud rate 19200 13 Baud rate 38400 14 Baud rate 57600
FC16 B016 B116 B216 B316
Version data output to 9th byte Data output to 259th byte
Acceptable Not acceptable Acceptable Acceptable Acceptable Acceptable
Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank.
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the fall of the clock.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
FF16
A8 to A15
A16 to A23
data0
data255
Figure 1.120. Timing for page read Read Status Register Command This command reads status information. When the “7016” command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
7016
SRD output
SRD1 output
Figure 1.121. Timing for reading the status register
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clear Status Register Command This command clears the bits (SR3–SR4) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
5016
Figure 1.122. Timing for clearing the status register Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “4116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the page program can be known by reading the status register. For more information, see the section on the status register.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
4116
A8 to A15
A16 to A23
data0
data255
Figure 1.123. Timing for the page program
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Transfer the “A716” command code with the 1st byte. (2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the erase operation can be known by reading the status register.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
A716
D016
Figure 1.124. Timing for erasing all unlocked blocks
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following. (1) Transfer the “7116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. Write the highest address of the specified block for addresses A8 to A23. The M30201 (flash memory version) does not have the lock bit, so the read value is always “1” (block unlock).
RxD0 (M16C reception data) TxD0 (M16C transmit data)
7116
A8 to A15
A16 to A23
DQ6
Figure 1.125. Timing for reading lock bit status
Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
FA16
Data size (low)
Check sum
Program data
Program data
Data size (high)
Figure 1.126. Timing for download
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the “FB16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
FB16
'V'
'E'
'R'
'X'
Figure 1.127. Timing for version information output
Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the “FC16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
FC16
A8 to A15
A16 to A23
data0
data255
Figure 1.128. Timing for boot ROM area output
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the “F516” command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
F516
DF16
FF16
0F16
ID size
ID1
ID7
Figure 1.129. Timing for the ID check
ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses.
Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 Reset vector
4 bytes
Figure 1.130. ID code storage addresses
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Baud Rate 9600 This command changes baud rate to 9,600 bps. Execute it as follows. (1) Transfer the "B016" command code with the 1st byte. (2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
B016
B016
Figure 1.131. Timing of baud rate 9600
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Baud Rate 19200 This command changes baud rate to 19,200 bps. Execute it as follows. (1) Transfer the "B116" command code with the 1st byte. (2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
B116
B116
Figure 1.132. Timing of baud rate 19200 Baud Rate 38400 This command changes baud rate to 38,400 bps. Execute it as follows. (1) Transfer the "B216" command code with the 1st byte. (2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
B216
B216
Figure 1.133. Timing of baud rate 38400 Baud Rate 57600 This command changes baud rate to 57,600 bps. Execute it as follows. (1) Transfer the "B316" command code with the 1st byte. (2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
B316
B316
Figure 1.134. Timing of baud rate 57600
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example Circuit Application for The Standard Serial I/O Mode 2
The below figure shows a circuit application for the standard serial I/O mode 2.
CLK0 P53(BUSY) Data input Data output RXD0 TXD0
VPP
M30201 Flash memory version
CNVss
(1) Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. (2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch.
Figure 1.135. Example circuit application for the standard serial I/O mode 2
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
52P4B
EIAJ Package Code SDIP52-P-600-1.78
MMP
JEDEC Code – Weight(g) 5.1 Lead Material Alloy 42/Cu Alloy
Plastic 52pin 600mil SDIP
52
27
1
26
Symbol
D
e SEATING PLANE
b1
b
b2
A A1 A2 b b1 b2 c D E e e1 L
Dimension in Millimeters Min Nom Max – – 5.5 0.51 – – – 3.8 – 0.4 0.5 0.59 0.9 1.0 1.3 0.65 0.75 1.05 0.22 0.27 0.34 45.65 45.85 46.05 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° – 15°
A
56P6S-A
EIAJ Package Code QFP56-P-1010-0.65 JEDEC Code – Weight(g) 0.59 Lead Material Alloy 42
A1
L
A2
Plastic 56pin 10✕10mm body QFP
MD
56
43
1
42
b2
I2 Recommended Mount Pad
HE
Symbol A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME
14
29
15
28
A
L1
e y
F
b
A1
x
M
L Detail F
Dimension in Millimeters Min Nom Max 3.05 – – 0 0.1 0.2 2.8 – – 0.25 0.3 0.4 0.13 0.15 0.2 9.8 10.0 10.2 9.8 10.0 10.2 0.65 – – 12.5 12.8 13.1 12.5 12.8 13.1 0.4 0.6 0.8 1.4 – – – – 0.13 0.1 – – 0° 10° – 0.35 – – – – 1.3 10.6 – – – – 10.6
E
A2
170
c
ME
HD D
e
e1
E
c
Chapter 2
Peripheral Functions Usage
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protect 2.1 Protect 2.1.1 Overview
'Protect' is a function that causes a value held in a register to be unchanged even when a program runs away. The following is an overview of the protect function: (1) Registers affected by the protect function The registers affected by the protect function are: (a) System clock control registers 0, 1 (addresses 000616 and 000716) (b) Processor mode registers 0, 1 (addresses 000416 and 000516) (c) Port P4 direction register (address 03EA16) The values in registers (1) through (3) cannot be changed in write-protect state. To change values in the registers, put the individual registers in write-enabled state. (2) Protect register Figure 2.1.1 shows protect register.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PRCR Bit symbol
PRC0
Address 000A16 Bit name
When reset XXXXX0002 Function RW
Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516) Enables writing to port P4 direction register (address 03EA16) (Note) 0 : Write-inhibited 1 : Write-enabled
PRC1
PRC2
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
Figure 2.1.1. Protect register
2.1.2 Protect Operation
The following explains the protect operation. Figure 2.1.2 shows the set-up procedure. Operation (1) Setting “1” in the write-enable bit of system clock control registers 0 and 1 causes system clock control register 0 and system clock control register 1 to be in write-enabled state. (2) The contents of system clock control register 0 and that of system clock control register 1 are changed. (3) Setting “0” in the write-enable bit of system control registers 0 and 1 causes system clock control register 0 and system control register 1 to be in write-inhibited state. (4) To change the contents of processor mode register 0 and that of processor mode register 1, follow the same steps as in dealing with system clock control registers. (5) The write-enable bit of port P4 direction register goes to “0” when the next write instruction is executed after write-enabled state is readied. Make changes in input/output immediately after the instruction that sets “1” in the write-enable bit of port P4 direction register (avoid causing an interrupt).
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Protect
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Clearing the protect (set to write-enabled state)
b7 b0
1
Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled Enables writing to port P4 direction register (address 03EA16) 0 : Write-inhibited 1 : Write-enabled
(2)
Setting system clock control register i (i = 0, 1)
(3) Setting the protect (set to write-inhibited state)
b7 b0
0
Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 0 : Write-inhibited Enables writing to port P4 direction register (address 03EA16) 0 : Write-inhibited 1 : Write-enabled
(4) Clearing the protect (set to write-enabled state)
b7 b0
1
Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 0 : Write-inhibited 1 : Write-enabled Enables writing to port P4 direction register (address 03EA16) 1 : Write-enabled
(5)
Changes in port P4 direction register
Figure 2.1.2. Set-up procedure for protect function
2.1.3 Precaution for Protect
(1) The write-enable bit of port P4 direction register goes to “0” when the next write instruction is executed after write-enabled state is readied. Make changes in input/output immediately after the instruction that sets “1” in the write-enable bit of port P4 direction register (avoid causing an interrupt).
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
2.2 Timer A 2.2.1 Overview
The following is an overview for timer A, a 16-bit timer. (1) Mode Timer A operates in one of the four modes: (a) Timer mode In this mode, the internal count source is counted. Two functions can be selected: the pulse output function that reverses output from a port every time an overflow occurs, or the gate function which controls the count start/stop according to the input signal from a port. • Timer mode operation .............................................................................................................. P180 • Timer mode, gate function operation ........................................................................................ P182 • Timer mode, pulse output function operation ........................................................................... P184 (b) Event counter mode This mode counts the pulses from the outside and the number of overflows in other timers. The freerun type, in which nothing is reloaded from the reload register, can be selected when an underflow occurs. The pulse output function can also be selected. Please refer to the timer mode explanation for details, as the operation is identical. • Event counter mode operation ................................................................................................. P186 • Event counter mode, free run type operation ........................................................................... P188 Furthermore, Timer A has a 2-phase pulse signal processing function which generates an up count or down count in the event counter mode, depending on the phase of the two input signals. • Operation of the 2-phase pulse signal processing function in normal event counter mode ..... P190 • Operation of the 2-phase pulse signal processing function in 4-multiplication mode ............... P192 (c) One-shot timer mode In this mode, the timer is started by the trigger and stops when the timer goes to “0”. The trigger can be selected from the following 3 types: an external input signal, an overflow of the timer, or a software trigger. The pulse output function can also be selected. Please refer to the timer mode explanation for details, as the operation is identical. • Operation in one-shot timer mode effected by software ........................................................... P194 • Operation in one-shot timer mode effected by an external trigger ........................................... P196 (d) Pulse width modulation (PWM) mode In this mode, the arbitrary pulses are successively output. Either a 16-bit fixed-period PWM mode or 8-bit variable-period mode can be selected. The trigger for initiating output can also be selected. Please refer to the one-shot timer mode explanation for details, as the operation is identical. • 16-bit PWM mode operation ..................................................................................................... P198 • 8-bit PWM mode operation ....................................................................................................... P200
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Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Count source The internal count source can be selected from f1, f8, f32, and fC32. Clocks f1, f8, and f32 are derived by dividing the CPU's main clock by 1, 8, and 32 respectively. Clock fC32 is derived by dividing the CPU's secondary clock by 32. (3) Frequency division ratio In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency division ratio when a down count is performed, or [FFFF16 - the set value + 1] becomes the frequency division ratio when an up count is performed. In one-shot timer mode, the value set in the timer register becomes the frequency division ratio. The counter overflows (or underflows) when a count source equal to a frequency division ratio is input, and an interrupt occurs. For the pulse output function, the output from the port varies (the value in the port register does not vary). (4) Reading the timer Either in timer mode or in event counter mode, reading the timer register takes out the count at that moment. Read it in 16-bit units. The data either in one-shot timer mode or in pulse width modulation mode is indeterminate. (5) Writing to the timer To write to the timer register when a count is in progress, the value is written only to the reload register. When writing to the timer register when a count is stopped, the value is written both to the reload register and to the counter. Write a value in 16-bit units. (6) Relation between the input/output to/from the timer and the direction register With the output function of the timer, set the direction register of the relevant port to input. To input an external signal to the timer, set the direction register of the relevant port to input. (7) Pins related to timer A Input pins to timer A. (a) TA0IN (b) TA0OUT Output pins from timer A. They become input pins to timer A when event counter mode is active.
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Timer A
(8) Registers related to timer A Figure 2.2.1 shows the memory map of timer A-related registers. Figures 2.2.2 through 2.2.5 show timer A-related registers.
005516 038016 038116 038216 038316 038416 038516 038616 038716 039616
Timer A0 interrupt control register (TA0IC) Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF)
Timer A0 (TA0)
Timer A0 mode register (TA0MR)
Figure 2.2.1. Memory map of timer A-related registers
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TA0MR
Address 039616
When reset 0016
Bit symbol
TMOD0
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode
RW
TMOD1
MR0 MR1 MR2 MR3 TCK0 TCK1
Function varies with each operation mode
Count source select bit (Function varies with each operation mode)
Figure 2.2.2. Timer A-related registers (1)
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Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A0 register (Note 1)
(b15) b7 (b8) b0 b7 b0
Symbol TA0
Address 038716,038616
When reset Indeterminate
Function • Timer mode Counts an internal count source • Event counter mode Counts pulses from an external source or timer overflow • One-shot timer mode Counts a one shot width • Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator • Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator Note 1: Read and write data in 16-bit units. Note 2: Use MOV instruction to write to this register.
Values that can be set
RW
000016 to FFFF16 000016 to FFFF16 000016 to FFFF16 (Note 2) 000016 to FFFE16 (Note 2) 0016 to FF16(Note 2) (Both high-order and low-order addresses)
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 000X00002
Bit symbol
TA0S TX0S TX1S TX2S
Bit name
Timer A0 count start flag Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Function
0 : Stops counting 1 : Starts counting
RW
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
TB0S TB1S CDCS Timer B0 count start flag Timer B1 count start flag
Clock devided count start flag
0 : Stops counting 1 : Starts counting
Figure 2.2.3. Timer A-related registers (2)
177
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Up/down flag (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF
Address 038416
When reset XXX0XXX02
Bit symbol
Bit name Timer A0 up/down flag
Function
RW
TA0UD
0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
TA0P Timer A0 two-phase pulse signal processing select bit
0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note : Use MOV instruction to write to this register.
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Address 038216
When reset XXXX00002
Bit symbol
TA0OS TX0OS TX1OS TX2OS
Bit name Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag
Function
1 : Timer start When read, the value is “0”
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Figure 2.2.4. Timer A-related registers (3)
178
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Address 038316
When reset 0016
Bit symbol
TA0TGL
Bit name Timer A0 event/trigger select bit
Function
b1 b0
RW
TA0TGH TX0TGL
0 0 : Input on TA0IN is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected
b3 b2
Timer X0 event/trigger select bit
TX0TGH TX1TGL TX1TGH
0 0 : Input on TX0INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected
b5 b4
Timer X1 event/trigger select bit
0 0 : Input on TX1INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected
b7 b6
TX2TGL TX2TGH
Timer X2 event/trigger select bit
0 0 : Input on TX2INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”(input mode).
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol Nothing is assigned.
Bit name
Function
RW
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Figure 2.2.5. Timer A-related registers (4)
179
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
2.2.2 Operation of Timer A (timer mode)
In timer mode, choose functions from those listed in Table 2.2.1. Operations of the circled items are described below. Figure 2.2.6 shows the operation timing, and Figure 2.2.7 shows the set-up procedure. Table 2.2.1. Choosed functions
Item Count source Pulse output function O O Set-up Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output Gate function O No gate function Performs count only for the period in which the TA0IN pin is at “L” level Performs count only for the period in which the TA0IN pin is at “H” level
Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
n = reload register content
Counter content (hex)
FFFF16
(1) Start count
(2) Underflow
(3) Stop count
n
Start count again
000016 Time
Set to “1” by software
Cleared to “0” by software Set to “1” by software
Count start flag
“1 ” “0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer A0 interrupt request bit
“1 ” “0”
Figure 2.2.6. Operation timing of timer mode
180
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting timer mode and functions
b7 b0
0
0
0
0
0
Timer A0 mode register [Address 039616] TA0MR Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Gate function select bit
b4 b3
00: 01:
Gate function not available (TA0IN pin is a normal port pin)
0 (Must always be “0” in timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
Timer A0 register [Address 038716, 038616] TA0
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer A0 count start flag
Start count
Figure 2.2.7. Set-up procedure of timer mode
181
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
2.2.3 Operation of Timer A (timer mode, gate function selected)
In timer mode, choose functions from those listed in Table 2.2.2. Operations of the circled items are described below. Figure 2.2.8 shows the operation timing, and Figure 2.2.9 shows the set-up procedure. Table 2.2.2. Choosed functions
Item Count source Pulse output function O O Set-up Internal count source(f1 / f8 / f32 / fc32) No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TA0IN pin is at “L” level O Performs count only for the period in which the TA0IN pin is at “H” level
Operation (1) When the count start flag is set to “1” and the TA0IN pin inputs at “H” level, the counter performs a down count on the count source. (2) When the TA0IN pin inputs at “L” level, the counter holds its value and stops. (3) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Note • Make the pulse width of the signal input to the TA0IN pin not less than two cycles of the count source.
n = reload register content FFFF16 n
Counter content (hex)
(1) Start count
(3) Underflow
(2) Stop count
(4) Stop count
Start count again.
000016
Set to “1” by software
Cleared to “0” by software
Time
Set to “1” by software
Count start flag
“1 ” “0”
“H” “L”
Cleared to “0” when interrupt request is accepted, or cleared by software
TA0IN pin input signal
Timer A0 interrupt “1” request bit “0”
Figure 2.2.8. Operation timing of timer mode, gate function selected
182
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting timer mode and functions
b7 b0
0
1
1
0
0
0
Timer A0 mode register [Address 039616] TA0MR
Selection of timer mode
Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin)
Gate function select bit
b4 b3
1 1 : Timer counts only when TA0IN pin is held “H” (Note)
0 (Must always be “0” in timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note: Set the corresponding port direction register to “0” (input mode).
Setting divide ratio
(b15) b7 (b8) b0 b7
b0
Timer A0 register [Address 038716, 038616] TA0
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer A0 count start flag
Start count
Figure 2.2.9. Set-up procedure of timer mode, gate function selected
183
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
2.2.4 Operation of Timer A (timer mode, pulse output function selected)
In timer mode, choose functions from those listed in Table 2.2.3. Operations of the circled items are described below. Figure 2.2.10 shows the operation timing, and Figure 2.2.11 shows the set-up procedure.
Table 2.2.3. Choosed functions
Item Count source Pulse output function O Gate function O O Internal count source(f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TA0IN pin is at “L” level Performs count only for the period in which the TA0IN pin is at “H” level Set-up
Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer A0 interrupt request bit goes to “1”. Also, the output polarity of the TA0OUT pin reverses. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TA0OUT pin outputs an “L” level.
n = reload register content FFFF16
(1) Start count (2) Underflow (3) Stop count
Counter content (hex)
n
Start count again
000016 Time
Set to “1” by software
Cleared to “0” by software
Set to “1” by software
Count start flag
“1”
“0”
Pulse output from “H” TA0OUT pin “L”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer A0 interrupt “1” request bit “0”
Figure 2.2.10. Operation timing of timer mode, pulse output function selected
184
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting timer mode and functions
b7 b0
0
0
1
0
0
Timer A0 mode register [Address 039616] TA0MR Selection of timer mode Pulse output function select bit (Note) 1 : Pulse is output (TA0OUT pin is a pulse output pin) Gate function select bit
b4 b3
00: 01:
Gate function not available (TA0IN pin is a normal port pin)
0 (Must always be “0” in timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note: Set the corresponding port direction register to “1” (output mode).
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
Timer A0 register [Address 038716, 038616] TA0
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer A0 count start flag
Start count
Figure 2.2.11. Set-up procedure of timer mode, pulse output function selected
185
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
2.2.5 Operation of Timer A (event counter mode, reload type selected)
In event counter mode, choose functions from those listed in Table 2.2.4. Operations of the circled items are described below. Figure 2.2.12 shows the operation timing, and Figure 2.2.13 shows the set-up procedure. Table 2.2.4. Choosed functions
Item Count source O Set-up Input signal to TA0IN (counting falling edges) Input signal to TA0IN (counting rising edges) Timer overflow (TB1/TX0/TX2 overflow) Item Pulse output function O Set-up No pulses output Pulses output Count operation type O Reload type Free-run type Factor for switching between up and down O Content of up/down flag Input signal to TA0OUT
Operation (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (3) If switching from an up count to a down count or vice versa while a count is in progress, the switch takes effect from the next effective edge of the count source. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. (5) If an overflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer A0 interrupt request bit goes to “1”.
n = reload register content FFFF16 (3) Switch count (1) Start count n (2) Underflow
(5) Overflow
Counter content (hex)
(4) Stop count Start count again 000016 Set to “1” by software Cleared to “0” by software Set to “1” by software Time
Count start flag Up/down flag
“1” “0” “1” “0”
Set to “1” by software
Cleared to “0” when interrupt request is accepted, or cleared by software Timer A0 interrupt “1” request bit “0”
Figure 2.2.12. Operation timing of event counter mode, reload type selected
186
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting event counter mode and functions
b7 b0
0
0
0
0
0
0
1
Timer A0 mode register [Address 039616] TA0MR Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Count polarity select bit 0 : Counts external signal's falling edge Up/down switching cause select bit 0 : Up/down flag's content 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type Invalid when not using two-phase pulse signal processing
Setting up/down flag
b7 b0
0
0
Up/down flag [Address 038416] UDF Timer A0 up/down flag 0 : Down count Timer A0 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled
Setting trigger select register
b7 b0
Trigger select register [Address 038316] TRGSR Timer A0 event/trigger select bit
b1 b0
0 0 : Input on TA0IN is selected (Note)
Note: Set the corresponding port direction register to “0” (input mode).
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
Timer A0 register [Address 038716, 038616] TA0
Can be set to 000016 to FFFF16
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer A0 count start flag
Start count
Figure 2.2.13. Set-up procedure of event counter mode, reload type selected
187
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
2.2.6 Operation of Timer A (event counter mode, free run type selected)
In event counter mode, choose functions from those listed in Table 2.2.5. Operations of the circled items are described below. Figure 2.2.14 shows the operation timing, and Figure 2.2.15 shows the set-up procedure. Table 2.2.5. Choosed functions
Item Count source O Set-up Input signal to TA0IN (counting falling edges) Input signal to TA0IN (counting rising edges) Timer overflow (TB1/TX0/TX2 overflow) Item Pulse output function O Set-up No pulses output Pulses output Count operation type O Factor for switching between up and down O Reload type Free-run type Content of up/down flag Input signal to TA0OUT
Operation (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (3) If switching from an up count to a down count or vice versa while a count is in progress, the switch takes effect from the next effective edge of the count source. (4) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”.
n = reload register content
(2) Underflow (3) Switch count (4) Overflow
FFFF16
Counter content (hex)
(1) Start count
n
000016 Time
Set to “1” by software
Count start flag
“1”
“0”
Set to “1” by software
Up/down flag
“1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software
Timer A0 interrupt “1” request bit “0”
Figure 2.2.14. Operation timing of event counter mode, free run type selected
188
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting event counter mode and functions
b7 b0
1
0
0
0
0
0
1
Timer A0 mode register [Address 039616] TA0MR Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Count polarity select bit 0 : Counts external signal's falling edge Up/down switching cause select bit 0 : Up/down flag's content 0 (Must always be “0” in event counter mode) Count operation type select bit 1 : Free-run type Invalid when not using two-phase pulse signal processing
Setting up/down flag
b7 b0
0
0
Up/down flag [Address 038416] UDF Timer A0 up/down flag 0 : Down count Timer A0 two-phase pulse signal processing select bit 0 : Two-phase pulse signal processing disabled
Setting trigger select register
b7 b0
Trigger select register [Address 038316] TRGSR Timer A0 event/trigger select bit
b1 b0
0 0 : Input on TA0IN is selected (Note) Note: Set the corresponding port direction register to “0” (input mode).
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
Timer A0 register [Address 038716, 038616] TA0
Can be set to 000016 to FFFF16
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer A0 count start flag
Start count
Figure 2.2.15. Set-up procedure of event counter mode, free run type selected
189
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
2.2.7 Operation of timer A (2-phase pulse signal process in event counter mode, normal mode selected)
In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table 2.2.6. Operations of the circled items are described below. Figure 2.2.16 shows the operation timing, and Figure 2.2.17 shows the set-up procedure. Table 2.2.6. Choosed functions
Item Count operation type O 2-phase pulses process O Reload type Free run type Normal processing 4-multiplication processing Set-up
Operation (1) Setting the count start flag to “1” causes the counter to count effective edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”. Note • The up count or down count conditions are as follows: If a rising edge is present at the TA0IN pin when the input signal level to the TA0OUT pin is “H”, an up count is performed. If a falling edge is present at the TA0IN pin when the input signal level to the TA0OUT pin is “H”, a down count is performed.
(1) Start count
Input pulse
TA0OUT TA0IN
“H” “L” “H” “L”
(2) Underflow (3) Overflow
Counter content (hex)
FFFF16
000016 Set to “1” by software “1” “0”
Time
Count start flag
Timer A0 interrupt “1” request bit “0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.2.16. Operation timing of 2-phase pulse signal process in event counter mode, normal mode selected
190
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting event counter mode and functions
b7 b0
0
1
0
1
0
0
0
1
Timer A0 mode register [Address 039616] TA0MR Selection of event counter mode 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) 1 (Must always be “1” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) Count operation type select bit 1 : Free-run type Two-phase pulse signal processing operation select bit 0 : Normal processing operation
Note: Set the corresponding port direction register which inputs the pulse to “0” (input mode).
Two-phase pulse signal processing select bit
b7 b0
1
Up/down flag [Address 038416] UDF Timer A0 two-phase pulse signal processing select bit 1 : Two-phase pulse signal processing enabled
b7
b0
0
0
Trigger select register [Address 038316] TRIGGER 00 (Must always be “00” when using two-phase pulse signal processing)
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
Timer A0 register [Address 038716, 038616] TA0
Can be set to 000016 to FFFF16
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer A0 count start flag
Start count
Figure 2.2.17. Set-up procedure of 2-phase pulse signal process in event counter mode, normal mode selected
191
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode, multiply-by-4 mode selected)
In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table 2.2.7. Operations of the circled items are described below. Figure 2.2.18 shows the operation timing, and Figure 2.2.19 shows the set-up procedure. Table 2.2.7. Choosed functions
Item Count operation type O Set-up Reload type Free run type Item Processing 2 phase pulses Set-up Normal processing O 4-multiplication processing
Operation (1) Setting the count start flag to “1” causes the counter to count effective edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”. (3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer A0 interrupt request bit goes to “1”. Note • The up count or down count conditions are as follows:
Table 2.2.8. The up count or down count conditions
Input signal to the TA0OUT pin Up count “H” level “L” level Rising Falling Input signal to the TA0IN pin Rising Falling “L” level “H” level Down count Input signal to the TA0OUT pin “H” level “L” level Rising Falling Input signal to the TA0IN pin Falling Rising “H” level “L” level
(1) Start count
Input pulse
TA0OUT TA0IN
“H” “L” “H” “L”
Counter content (hex)
FFFF16
000016 Set to “1” by software (2) Underflow Count start flag “1” Cleared to “0” when interrupt request is accepted, or cleared by software “0” Timer A0 interrupt “1” request bit “0” Time (3) Overflow
Figure 2.2.18. Operation timing of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected
192
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting event counter mode and functions
b7 b0
1
1
0
1
0
0
0
1
Timer A0 mode register [Address 039616] TA0MR Selection of event counter mode 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) 1 (Must always be “1” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) Count operation type select bit 1 : Free-run type Two-phase pulse signal processing operation select bit 1 : Multiply-by-4 processing operation
Note: Set the corresponding port direction register which inputs the pulse to “0” (input mode).
Two-phase pulse signal processing select bit
b7 b0
1
Up/down flag [Address 038416] UDF Timer A0 two-phase pulse signal processing select bit 1 : Two-phase pulse signal processing enabled
b7
b0
0
0
Trigger select register [Address 038316] TRIGGER 00 (Must always be “00” when using two-phase pulse signal processing)
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
Timer A0 register [Address 038716, 038616] TA0
Can be set to 000016 to FFFF16
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer A0 count start flag
Start count
Figure 2.2.19. Set-up procedure of2-phase pulse signal process in event counter mode, multiply-by-4 mode selected
193
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.9 Operation of Timer A (one-shot timer mode)
In one-shot timer mode, choose functions from those listed in Table 2.2.9. Operations of the circled items are described below. Figure 2.2.20 shows the operation timing, and Figure 2.2.21 shows the set-up procedure. Table 2.2.9. Choosed functions
Item Count source Pulse output function O Count start condition O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output External trigger input (falling edge of input signal to the TA0IN pin) External trigger input (rising edge of input signal to the TA0IN pin) Timer overflow (TB1/TX0/TX2 overflow) O Writing “1” to the one-shot start flag Set-up
Operation (1) Setting the one-shot start flag to “1” with the count start flag set to “1” causes the counter to perform a down count on the count source. At this time, the TA0OUT pin outputs an “H” level. (2) The instant the value of the counter becomes “000016”, the TA0OUT pin outputs an “L” level, and the counter reloads the content of the reload register and stops counting. At this time, the timer A0 interrupt request bit goes to “1”. (3) If a trigger occurs while a count is in progress, the counter reloads the value in the reload register again and continues counting. The reload timing is in step with the next count source input after the trigger. (4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the reload register. Also, the TA0OUT pin outputs an “L” level. At this time, the timer A0 interrupt request bit goes to “1”.
n = reload register content
Counter content (hex)
FFFF16 n
(1) Start count
(2) Stop count (3) Start count
Start count
(4) Stop count
Reload
Reload
Reload
000116
Set to “1” by software Cleared to “0” by software
Time
Count start flag Write signal to one-shot start flag
“1” “0”
1 / fi X (n)
1 / fi X (n+1)
One-shot pulse output “H” from TA0OUT pin “L” Timer A0 interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.2.20. Operation timing of one-shot mode
194
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting one-shot timer mode and functions
b7 b0
0
0
1
1
0
Timer A0 mode register [Address 039616] TA0MR Selection of one-shot timer mode Pulse output function select bit 1 : Pulse is output (Note) External trigger select bit When internal is selected, this bit can be “1” or “0” Trigger select bit 0 : When the one-shot start flag is set “1” 0 (Must always be “0” in one-shot timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note: Set the corresponding port direction register to “1” (output mode).
Clearing timer A0 interrupt request bit
b7 b0
Refer to 'Precaution for Timer A (one shot timer mode)'
0
Timer A0 interrupt control register [Address 005516] TA0IC Interrupt request bit
Setting one-shot timer's time
(b15) b7 (b8) b0 b7 b0
Timer A0 register [Address 038716, 038616] TA0
Can be set to 000116 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer A0 count start flag
Setting one-shot start flag
b7 b0
One-shot start flag [Address 038216] ONSF Timer A0 one-shot start flag
Start count
Figure 2.2.21. Set-up procedure of one-shot mode
195
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.10 Operation of Timer A (one-shot timer mode, external trigger selected)
In one-shot timer mode, choose functions from those listed in Table 2.2.10. Operations of the circled items are described below. Figure 2.2.22 shows the operation timing, and Figure 2.2.23 shows the set-up procedure. Table 2.2.10. Choosed functions
Item Count source Pulse output function O Count start condition O O Set-up Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output External trigger input (falling edge of input signal to the TA0IN pin) External trigger input (rising edge of input signal to the TA0IN pin) Timer overflow (TB1/TX0/TX2 overflow) Writing “1” to the one-shot start flag
Operation (1) If the TA0IN pin input level changes from “L” to “H” with the count start flag set to “1”, the counter performs a down count on the count source. At this time, the TA0OUT pin output level goes to “H” level. (2) If the value of the counter becomes “000016”, the TA0OUT pin outputs an “L” level, and the counter reloads the content of the reload register and stops counting. At this time, the timer A0 interrupt request bit goes to “1”. (3) If a trigger occurs while a count is in progress, the counter reloads the value of the reload register again and continues counting. The reload timing is in step with the next count source input after the trigger. (4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the reload register. Also, the TA0OUT pin outputs an “L” level. At this time, the timer A0 interrupt request bit goes to “1”.
FFFF16
Counter content (hex)
n = reload register content (1) Start count
(2) Stop count (3) Start count
Start count
(4) Stop count
n Reload
Reload
Reload
000116
Set to “1” by software
Cleared to “0” by software
Time
Count start flag TA0IN pin input signal
“1” “0” “H” “L” 1 / fi X (n)
Trigger during count
1 / fi X (n+1)
One-shot pulse output “H” from TA0OUT pin “L” Timer A0 interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.2.22. Operation timing of one-shot mode, external trigger selected
196
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting one-shot timer mode and functions
b7 b0
0
1
1
1
1
0
Timer A0 mode register [Address 039616] TA0MR Selection of one-shot timer mode Pulse output function select bit 1 : Pulse is output (Note 1) External trigger select bit 1 : Rising edge of TA0IN pin's input signal Trigger select bit 1 : Selected by event/trigger select register 0 (Must always be “0” in one-shot timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note 1: Set the corresponding port direction register to “1” (output mode).
Clearing timer A0 interrupt request bit
b7 b0
Refer to 'Precaution for Timer A (one shot timer mode)'
0
Timer A0 interrupt control register [Address 005516] TA0IC Interrupt request bit
Setting Trigger select register
b7 b0
00
Trigger select register [Address 038316] TRGSR Timer A0 event/trigger select bit
b1 b0
0 0 : Input on TA0IN is selected (Note 2) Note 2: Set the corresponding port direction register to “0” (input mode).
Setting one-shot timer's time
(b15) b7 (b8) b0 b7 b0
Timer A0 register [Address 038716, 038616] TA0
Can be set to 000116 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer A0 count start flag
Start count
Figure 2.2.23. Set-up procedure of one-shot mode, external trigger selected
197
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.11 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected)
In pulse width modulation mode, choose functions from those listed in Table 2.2.11. Operations of the circled items are described below. Figure 2.2.24 shows the operation timing, and Figure 2.2.25 shows the set-up procedure. Table 2.2.11. Choosed functions
Item Count source PWM mode O O Set-up Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM Count start condition O External trigger input (falling edge of input signal to the TA0IN pin) External trigger input (rising edge of input signal to the TA0IN pin) Timer overflow (TB1/TX0/TX2 overflow)
Operation (1) If the TA0IN pin input level changes from “L” to “H” with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TA0OUT pin outputs an “H” level. (2) The TA0OUT pin output level changes from “H” to “L” when a set time period elapses. At this time, the timer A0 interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TA0OUT outputs an “L” level. Note • PWM pulse cycle is (216 -1)/fi, whereas H level duration is n/fi. However, when “000016” is set for the timer A0 register, the PWM output is “L” level for the entire period, and an interrupt request is generated for every PWM output cycle. Also, when “FFFF16” is set for the timer A0 register, the PWM output is “H” level for the entire period, and an interrupt request is generated for every PWM output cycle. (fi: Count source frequency f1, f8, f32, fC32 n: Timer value)
Conditions: Reload register = 000316, external trigger (rising edge of TA0IN pin input signal) is selected 1 / fi X (2
Count source
16
–1)
“H ”
TA0IN pin input signal
“L”
Trigger is not generated by this signal
Set to “1” by software
Count start flag
“1” “0” (1) Start count (2) Output level “H” to “L” 1 / fi X n
Cleared to “0” by software
(3) One period is complete
(4) Stop count
PWM pulse output from TA0OUT pin
“H ”
“L” “1 ” “0 ”
Timer A0 interrupt request bit
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: n = 000016 to FFFE16
Figure 2.2.24. Operation timing of pulse width modulation mode, 16-bit PWM mode selected
198
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting PWM mode and functions
b7 b0
0
1
1
1
1
1
Timer A0 mode register [Address 039616] TA0MR Selection of PWM mode 1 (Must always be “1” in PWM mode) External trigger select bit 1 : Rising edge of TA0IN pin's input signal (Note 1) Trigger select bit 1 : Selected by event/trigger select register 16/8-bit PWM mode select bit 0 : Functions as a 16-bit pulse width modulator Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f81 0 : f321 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note 1: Set the corresponding port direction register which outputs the pulse to “1” (output mode).
Clearing timer A0 interrupt request bit
b7 b0
Refer to 'Precaution for Timer A (pulse width modulation mode)'
0
Timer A0 interrupt control register [Address 005516] TA0IC Interrupt request bit
Setting trigger select register
b7 b0
Trigger select register [Address 038316] TRGSR Timer A0 event/trigger select bit
b1 b0
0 0 : Input on TA0IN is selected (Note 2)
Note 2: Set the corresponding port direction register to “0” (input mode).
Setting PWM pulse's “H” level width
(b15) b7 (b8) b0 b7 b0
Timer A0 register [Address 038716, 038616] TA0
Can be set to 000016 to FFFE16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count starts flag
b7 b0
Count start flag [Address 038016] TABSR Timer A0 count start flag
Start count
Figure 2.2.25. Set-up procedure of pulse width modulation mode, 16-bit PWM mode selected
199
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.12 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected)
In pulse width modulation mode, choose functions from those listed in Table 2.2.12. Operations of the circled items are described below. Figure 2.2.26 shows the operation timing, and Figure 2.2.27 shows the set-up procedure. Table 2.2.12. Choosed functions
Item Count source PWM mode O Count start condition O O Set-up Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM External trigger input (falling edge of input signal to the TA0IN pin) External trigger input (rising edge of input signal to the TA0IN pin) Timer overflow (TB1/TX0/TX2 overflow)
Operation (1) If the TA0IN pin input level changes from “H” to “L” with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TA0OUT pin outputs an “H” level. (2) The TA0OUT pin output level changes from “H” to “L” when a set time period elapses. At this time, the timer A0 interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TA0OUT pin outputs an “L” level. Note • PWM pulse cycle is (m + 1( x (28 -1)/fi, whereas “H” level duration is n x (m + 1)/fi. However, when “0016” is set for the significant 8 bits of the timer A0 register, the PWM output is “L” level for the entire period, and an interrupt request is generated for every PWM output cycle. Also, when “FF16” is set for the significant 8 bits of the timer A0 register, the PWM output is “H” level for the entire period, and an interrupt request is generated for every PWM output cycle. (fi: Count source frequency f1, f8, f32, fC32 n: Timer value)
Conditions: Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TA0IN pin input signal) is selected 1 / fi X (m + 1) X (2 – 1) Count source (Note 1) Count start flag TA0IN pin input
“1” “0” “H” “L”
8
(4) Stop count
(1) Start count
(2) Output level “H” to “L” 1 / fi X (m+1)
(3) One period is complete
Underflow signal of 8-bit “H” prescaler (Note 2) “L” PWM pulse output from TA0OUT pin Timer A0 interrupt request bit
“H” “L” “1” “0”
1 / fi X (m + 1) X n Cleared to “0” when interrupt request is accepted, or cleared by software
Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FF16.
Figure 2.2.26. Operation timing of pulse width modulation mode, with 8-bit PWM mode selected
200
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Selecting PWM mode and function
b7 b0
1
1
0
1
1
1
Timer A0 mode register [Address 039616] TA0MR Selection of PWM mode 1 (Must always be “1” in PWM mode) External trigger select bit 0 : Falling edge of TA0IN pin's input signal (Note 1) Trigger select bit 1 : Selected by event/trigger select register 16/8-bit PWM mode select bit 1: Functions as an 8-bit pulse width modulator Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note 1: Set the corresponding port direction register which outputs the pulse to “1” (output mode).
Clearing timer A0 interrupt request bit
b7 b0
Refer to 'Precaution for Timer A (pulse width modulation mode)'
0
Timer A0 interrupt control register [Address 005516 ] TA0IC Interrupt request bit
Setting trigger select register
b7 b0
Trigger select register [Address 038316] TRGSR Timer A0 event/trigger select bit
b1 b0
0 0 : Input on TA0IN is selected (Note 2) Note 2: Set the corresponding port direction register to “0” (input mode).
Setting PWM pulse's period and “H” level width
(b15) b7 (b8) b0 b7 b0
Timer A0 register [Address 038716, 038616] TA0
Can be set to 0016 to FE16 Can be set to 0016 to FE16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer A0 count start flag
Start count
Figure 2.2.27. Set-up procedure of pulse width modulation mode, 8-bit PWM mode selected
201
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.13 Precautions for Timer A (timer mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer A0 register, then set the flag to “1”. (2) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer A0 register with the reload timing shown in Figure 2.2.28 gets “FFFF16”. Reading the timer A0 register after setting a value in the timer A0 register with a count halted but before the counter starts counting gets a proper value.
Reload
Counter value (Hex.)
2
1
0
n
n–1
Read value (Hex.)
2
1
0
FFFF
n–1
Time n = reload register content
Figure 2.2.28. Reading timer A0 register
202
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.14 Precautions for Timer A (event counter mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer A0 register, then set the flag to “1”. (2) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer A0 register with the reload timing shown in Figure 2.2.29 gets “FFFF16” by underflow or “000016” by overflow. Reading the timer A0 register after setting a value in the timer A0 register with a count halted but before the counter starts counting gets a proper value. (3) Please note the standards for the differences between the 2 pulses used in the 2-phase pulse signals input signals to the TA0IN pin and TA0OUT pin as shown in Figure 2.2.30. (4) When free run type is selected, if count is stopped, set a value in the timer A0 register again.
(1) Down count
Reload
(2) Up count
R eload
Counter value (Hex.) Read value (Hex.)
2
1
0
n
n–1
Counter value (Hex.) Read value (Hex.)
FFFD FFFE FFFF
n
n+1
2
1
0
FFFF n – 1
Time
FFFD FFFE FFFF 0000 n + 1
Time
n = reload register content
n = reload register content
Figure 2.2.29. Reading timer A0 register
T1 TA2IN TA3IN TA4IN TA2OUT TA3OUT TA4OUT
Vcc = 5V, f(XIN) = 10MHz
T1 (Min.) T2, T3 (Min.)
800ns
200ns
Vcc = 3V, f(XIN) = 7MHz, one-wait
T2 T3
T1 (Min.) 2µs
T2, T3 (Min.) 500ns
Figure 2.2.30. Standard of 2-phase pulses
203
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.15 Precautions for Timer A (one-shot timer mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer A0 register, then set the flag to “1”. (2) Setting the count start flag to “0” while a count is in progress causes as follows: • The counter stops counting and a content of reload register is reloaded. • The TA0OUT pin outputs “L” level. • The interrupt request generated and the timer A0 interrupt request bit goes to “1”. (3) The output from the one-shot timer synchronizes with the count source generated internally. Therefore, when an external trigger has been selected, a delay of one cycle of count source as a maximum occurs between the trigger input to the TA0IN pin and the one-shot timer output. (4) The timer A0 interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures: • Selecting one-shot timer mode after reset. • Changing operation mode from timer mode to one-shot timer mode. • Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0” after the above listed changes have been made. (5) If a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To generate a trigger while a count is in progress, generate the second trigger after an elapse longer than one cycle of the timer's count source after the previous trigger occurred.
TA0IN pin input signal “H” “L” Count source
Trigger input
One-shot pulse output from TA0OUT pin
Start one-shot pulse output
Note: The above applies when an external trigger (falling edge of TA0IN pin input signal) is selected.
Figure 2.2.31. One-shot timer delay
204
Mitsubishi microcomputers
M30201 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.2.16 Precautions for Timer A (pulse width modulation mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer A0 register, then set the flag to “1”. (2) The timer A0 interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures: • Selecting PWM mode after reset. • Changing operation mode from timer mode to PWM mode. • Changing operation mode from event counter mode to PWM mode. Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0” after the above listed changes have been made. (3) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TA0OUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer A0 interrupt request bit goes to “1”. If the TA0OUT pin is outputting an “L” level in this instance, the level does not change, and the timer A0 interrupt request bit does not becomes “1”. (4) Normal PWM output is restored according to the interrupt request generate timing, both in the case of 16-bit PWM and 8-bit PWM, when PWM output is either “H” or “L” level for the entire period. This holds only when a value other than “000016” or “FFFF16” is set during 16bit PWM, or a value other than “0016” or “FF16” is set during 8-bit PWM.
Normal PWM restored here
When PWM output is “H” level for the entire period
Writing to the timer A0
1 / fi X (n)
PWM pulse output from TA0OUT pin
Timer A0 interrupt request bit
"H"
"L"
"1" "0"
Cleared to “0” when interrupt request is accepted, or cleared by software
When PWM output is “L” level for the entire period
Writing to the timer A0
PWM pulse output from TA0OUT pin
Timer A0 interrupt request bit
"H" "L" 1 / fi X (n)
"1" "0"
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.2.32. Operation timing of PWM output mode
205
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B 2.3 Timer B 2.3.1 Overview
The following is an overview for timer B, a 16-bit timer. (1) Mode Timer B operates in one of three modes: (a) Timer mode The internal count source is counted. • Operation in timer mode ........................................................................................................... P210 (b) Event counter mode The number of pulses coming from outside and the number of the timer overflows are counted. • Operation in event counter mode ............................................................................................. P212 (c) Pulse period measurement/pulse width measurement mode External pulse period or external pulse widths are measured. If pulse period measurement mode is selected, the periods of input pulses are continuously measured. If pulse width measurement mode is selected, widths of “H” level pulses and those of “L” level pulses are continuously measured. • Operation in pulse period measurement mode ........................................................................ P214 • Operation in pulse width measurement mode .......................................................................... P216 (2) Count source An internal count source can be selected from f1, f8, f32, and fC32. f1, f8, and f32 are clocks obtained by dividing the CPU main clock by 1, 8, and 32 respectively. fC32 is the clock obtained by dividing the CPU secondary clock by 32. (3) Frequency division ratio The frequency division ratio equals [the value set in the timer register + 1]. The counter underflows when a count source equal to a frequency division ratio is input, and an interrupt request occurs. (4) Reading the timer In timer mode or event counter mode, the count value at the time of reading the timer register will be read. Read the register in 16-bit increments. In both the pulse period measurement mode and pulse width measurement mode, an indeterminate value is read until the second effective edge is input after a count is started, otherwise, the measurement results are read. (5) Writing to the timer When writing to the timer register while a count is in progress, the value is written only to the reload register. When writing to the timer register while a count has stopped, the value is written both to the reload register and the count. Write the value in 16-bit increments. The timer register cannot be written to in either the pulse period measurement mode or the pulse width measurement mode.
206
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(6) Input to the timer and the direction register To input an external signal to the timer, set the direction register of the relevant port to input. (7) Pins related to timer B (a) TB0IN, TB1IN Input pins to timer B. (8) Registers related to timer B Figure 2.3.1 shows the memory map of timer B-related registers. Figures 2.3.2 and 2.3.3 show timer B-related registers.
005A16 005B16 038016 038116 038216 038316 038416 039016 039116 039216 039316 039B16 039C16
Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF)
Timer B0 (TB0) Timer B1 (TB1)
Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR)
Figure 2.3.1. Memory map of timer B-related registers
207
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TBiMR(i = 0, 1)
Address 039B16, 039C16
When reset 00XX00002
Bit symbol
TMOD0 TMOD1
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Inhibited
R
W
MR0 MR1 MR2
Function varies with each operation mode
(Note 1) (Note 2)
MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode)
Note 1: Timer B0. Note 2: Timer B1. Note 3: Must set “00” to operation mode select bit of M30200
Figure 2.3.2. Timer B-related registers (1)
208
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer Bi register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TB0 TB1
Address 039116, 039016 039316, 039216
When reset Indeterminate Indeterminate
Function
• Timer mode Counts the timer's period • Event counter mode Counts external pulses input or a timer overflow • Pulse period / pulse width measurement mode Measures a pulse period or width Note1: Read and write data in 16-bit units.
Values that can be set
RW
000016 to FFFF16
000016 to FFFF16
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 000X00002
Bit symbol TA0S TX0S TX1S TX2S
Bit name Timer A0 count start flag Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Function 0 : Stops counting 1 : Starts counting
RW
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
TB0S TB1S CDCS Timer B0 count start flag Timer B1 count start flag
Clock devided count start flag
0 : Stops counting 1 : Starts counting
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol Nothing is assigned.
Bit name
Function
RW
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Figure 2.3.3. Timer B-related registers (2)
209
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B 2.3.2 Operation of Timer B (timer mode)
In timer mode, choose functions from those listed in Table 2.3.1. Operations of the circled items are described below. Figure 2.3.4 shows the operation timing, and Figure 2.3.5 shows the set-up procedure. Table 2.3.1. Choosed functions
Item Count source O Set-up Internal count source (f1 / f8 / f32 / fc32)
Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the counter continues counting. At this time, the timer Bi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
n = reload register content
Counter content (hex)
FFFF16
(1) Start count
(2) Underflow
(3) Stop count
n
Start count again
000016 Time
Set to “1” by software
Cleared to “0” by software Set to “1” by software
Count start flag
“1” “0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Bi interrupt “1” request bit “0”
Figure 2.3.4. Operation timing of timer mode
210
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Selecting timer mode and functions
b7 b0
0
0
Timer Bi mode register (i=0 , 1) [Address 039B16, 039C16] TBiMR (i=0 to 2)
Selection of timer mode
Invalid in timer mode Can be “0” or “1”
Fixed to “0” in timer mode Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Setting divide ratio
(b15) b7 (b8) b0 b7
b0
Timer B0 register [Address 039116, 039016] TB0 Timer B1 register [Address 039316, 039216] TB1
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag
Start count
Figure 2.3.5. Set-up procedure of timer mode
211
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B 2.3.3 Operation of Timer B (event counter mode)
In event counter mode, choose functions from those listed in Table 2.3.2. Operations of the circled items are described below. Figure 2.3.6 shows the operation timing, and Figure 2.3.7 shows the set-up procedure. Table 2.3.2. Choosed functions
Item Count source O Set-up Input signal to the TBiIN pin (counting falling edges) Input signal to the TBiIN pin (counting rising edges) Input signal to the TBiIN pin (counting rising edges and falling edges) Timer overflow(TBj overflow)
Operation (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Bi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
n = reload register content FFFF16 (1) Start count (2) Underflow (3) Stop count
Counter content (hex)
n Start count again
000016 Time Set to “1” by software “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timer Bi interrupt “1” request bit “0” Cleared to “0” by software Set to “1” by softwar
Count start flag
Figure 2.3.6. Operation timing of event counter mode
212
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Selecting event counter mode and functions
b7 b0
0
0
0
0
1
Timer Bi mode register (i=0, 1) [Address 039B16, 039C16] TBiMR (i=0, 1)
Selection of event counter mode
Count polarity select bit
b3 b2
0 0 : Counts external signal falling edges Fixed to “0” in event counter mode Event clock select 0 : Input from TBiIN pin (Note) Note: Set the corresponding port direction register to “0” (input mode).
Setting divide ratio
(b15) b7 (b8) b0 b7
b0
Timer B0 register [Address 039116, 039016] TB0 Timer B1 register [Address 039316, 039216] TB1
Can be set to 000016 to FFFF16 (n)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag
Start count
Figure 2.3.7. Set-up procedure of event counter mode
213
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B 2.3.4 Operation of Timer B (pulse period measurement mode)
In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.3. Operations of the circled items are described below. Figure 2.3.8 shows the operation timing, and Figure 2.3.9 shows the set-up procedure.
Table 2.3.3. Choosed functions
Item Count source Measurement mode O Internal count source (f1 / f8 / f32 / fc32) O Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) Set-up
Operation (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If a measurement pulse changes from “H” to “L”, the value of the counter goes to “000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Bi interrupt request does not generate. (3) If a measurement pulse changes from “H” to “L” again, the value of the counter is transferred to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the value of the counter becomes “000016”, and the measurement is started again. Note • The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine. • The value of the counter at the beginning of a count is indeterminate. Thus there can be instances in which the timer Bi overflow flag goes to “1” immediately after a count is performed. • The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software.
Measurement of pulse time interval from falling edge to falling edge
(1) Start count Count source Measurement pulse Reload register ← counter transfer timing (Note 1) Timing at which counter reaches “000016” Count start flag Timer Bi interrupt request bit Timer Bi overflow flag “1” “0” “1” “0” “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software “H” “L” Transfer (indeterminate value) (Note 1) Transfer (measured value) (Note 2) (2) Start measurement (3) Start measurement again
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 2.3.8. Operation timing of pulse period measurement mode
214
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Selecting pulse period / pulse width measurement mode and functions
b7 b0
0
0
1
0
Timer Bi mode register (i=0 , 1) [Address 039B16, 039C16] TBiMR (i=0, 1) Selection of pulse period / pulse width measurement mode Measurement mode select bit
b3 b2
0 0 : Pulse period measurement (Interval between measurement pulse falling edge to falling edge) Timer Bi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed Count source select bit
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
b7 b6 0 0 1 1 0 1 0 1
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note: Set the corresponding port direction register which sets the measurement pulse to “0” (input mode).
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag
Start count
Clearing overflow flag
b7 b0
0
Timer Bi mode register (i=0, 1) [Address 039B16 to 039D16] TBiMR (i=0, 1) Timer Bi overflow flag 0 : Timer did not overflow
Figure 2.3.9. Set-up procedure of pulse period measurement mode
215
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B 2.3.5 Operation of Timer B (pulse width measurement mode)
In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.4. Operations of the circled items are described below. Figure 2.3.10 shows the operation timing, and Figure 2.3.11 shows the set-up procedure.
Table 2.3.4. Choosed functions
Item Count source Measurement mode O Internal count source (f1 / f8 / f32 / fc32) Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) O Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) Set-up
Operation (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If an effective edge of a pulse to be measured is input, the value of the counter goes to
“000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Bi interrupt request does not generate. (3) If an effective edge of a pulse to be measured is input again, the value of the counter is transferred to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the value of the counter becomes “000016”, and measurement is started again.
Note
• The timer Bi interrupt request bit goes to “1” when an effective edge of a pulse to be measured is input or timer Bi is overflows. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine. • The value of the counter at the beginning of a count is indeterminate. Thus there can be instances in which the timer Bi overflow flag goes to “1” immediately after a count is performed. • The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software.
(1) Start count
(3) Start measurement again
(2) Start measurement Count source Measurement pulse Reload register ← counter transfer timing Timing at which counter reaches “000016” Count start flag “1 ” “0 ” “H” “L” Transfer (indeterminate value) (Note 1) Transfer(measured value)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
Timer Bi interrupt request bit “1” “0 ” Timer Bi overflow flag “1 ” “0” Cleared to “0” when interrupt request is accepted, or cleared by software
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 2.3.10. Operation timing of pulse width measurement mode
216
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Selecting pulse period / pulse width measurement mode and functions
b7 b0
1
0
1
0
Timer Bi mode register (i=0, 1) [Address 039B16, 039C16] TBiMR (i=0 , 1) Selection of pulse period / pulse width measurement mode Measurement mode select bit
b3 b2
1 0 : Pulse width measurement (Interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) Timer Bi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note: Set the corresponding port direction register which sets the measurement pulse to “0” (input mode).
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag
Start count
Clearing overflow flag
b7 b0
0
Timer Bi mode register (i=0, 1) [Address 039B16, 039C16] TBiMR (i=0, 1) Timer Bi overflow flag 0 : Timer did not overflow
Figure 2.3.11. Set-up procedure of pulse width measurement mode
217
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B 2.3.6 Precautions for Timer B (timer mode, event counter mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Bi register, then set the flag to “1”. (2) Reading the timer Bi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing shown in Figure 2.3.12 gets “FFFF16”. Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value.
Reload
Counter value (Hex.)
2
1
0
n
n–1
Read value (Hex.)
2
1
0
FFFF
n–1
Time n = reload register content
Figure 2.3.12. Reading timer Bi register
218
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B 2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode)
(1) The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine. (2) If the timer overflow occurs simultaneously with the input of a measurement pulse, and if the interrupt factor cannot be determined from the timer Bi overflow flag, connect the timers and count the number of overflows. (3) When reset, the timer Bi overflow flag goes to “1”. This flag can be set to “0” by writing to the timer Bi mode register when the count start flag is “1”. (4) Use the timer Bi interrupt request bit to detect only overflows. Use the timer Bi overflow flag only to determine the interrupt factor within the interrupt routine. (5) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. (6) The value of the counter is indeterminate at the beginning of a count. Therefore the timer Bi overflow flag may go to “1” immediately after a count is started. (7) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to “1”. (8) If the input signal to the TBiIN pin is affected by noise, precise measurement may not be performed in some cases. It is recommended to see that measurements fall within a specific range by use of software. (9) For pulse width measurement, pulse widths are successively measured. Use software to check whether the measurement result is an “H” level width or an “L” level width.
219
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4 Timer X 2.4.1 Overview
The following is an overview for timer X, a 16-bit timer. (1) Mode Timer X operates in one of the four modes: (a) Timer mode In this mode, the internal count source is counted. Two functions can be selected: the pulse output function that reverses output from a port every time an overflow occurs, or the gate function which controls the count start/stop according to the input signal from a port. • Timer mode operation .............................................................................................................. P224 • Timer mode, gate function operation ........................................................................................ P226 • Timer mode, pulse output function operation ........................................................................... P228 (b) Event counter mode This mode counts the pulses from the outside and the number of overflows in other timers. The freerun type, in which nothing is reloaded from the reload register, can be selected when an underflow occurs. The pulse output function can also be selected. • Event counter mode operation ................................................................................................. P230 • Event counter mode, free run type operation ........................................................................... P232 (c) One-shot timer mode In this mode, the timer is started by the trigger and stops when the timer goes to “0”. The trigger can be selected from the following 3 types: an external input signal, an overflow of the timer, or a software trigger. • One-shot timer mode operation ................................................................................................ P234 (d) Pulse period measurement/pulse width measurement mode External pulse period or external pulse widths are measured. If pulse period measurement mode is selected, the periods of input pulses are continuously measured. If pulse width measurement mode is selected, widths of “H” level pulses and those of “L” level pulses are continuously measured. • Operation in pulse period measurement mode ........................................................................ P236 • Operation in pulse width measurement mode .......................................................................... P238 (d) Pulse width modulation (PWM) mode In this mode, the arbitrary pulses are successively output. Either a 16-bit fixed-period PWM mode or 8-bit variable-period mode can be selected. The trigger for initiating output can also be selected. • 16-bit PWM mode operation ..................................................................................................... P240 • 8-bit PWM mode operation ....................................................................................................... P242 (2) Count source The internal count source can be selected from f1, f8, f32, and fC32. Clocks f1, f8, and f32 are derived by dividing the CPU's main clock by 1, 8, and 32 respectively. Clock fC32 is derived by dividing the CPU's secondary clock by 32.
220
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
(3) Frequency division ratio In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the frequency division ratio. In event counter mode, [the set value + 1] becomes the frequency division ratio when a down count is performed, or [FFFF16 - the set value + 1] becomes the frequency division ratio when an up count is performed. In one-shot timer mode, the value set in the timer register becomes the frequency division ratio. The counter overflows (or underflows) when a count source equal to a frequency division ratio is input, and an interrupt occurs. For the pulse output function, the output from the port varies (the value in the port register does not vary). (4) Reading the timer Either in timer mode or in event counter mode, reading the timer register takes out the count at that moment. Read it in 16-bit units. The data either in one-shot timer mode or in pulse width modulation mode is indeterminate. In both the pulse period measurement mode and pulse width measurement mode, an indeterminate value is read until the second effective edge is input after a count is started, otherwise, the measurement results are read. (5) Writing to the timer When writing to the timer register while a count is in progress, the value is written only to the reload register. When writing to the timer register while a count has stopped, the value is written both to the reload register and the count. Write the value in 16-bit increments. The timer register cannot be written to in either the pulse period measurement mode or the pulse width measurement mode. (6) Relation between the input/output to/from the timer and the direction register With the output function of the timer, set the direction register of the relevant port to input. To input an external signal to the timer, set the direction register of the relevant port to input. However, pulse output cannot be selected when inputting an external signal to the timer, and vice-versa. (7) Pins related to timer X (a) TX0INOUT, TX1INOUT, TX2INOUT
Input/output pins to timer X.
(8) Registers related to timer X Figure 2.4.1 shows the memory map of timer X-related registers. Figures 2.4.2 and 2.4.3 show timer X-related registers.
005616 005716 005816 038016 038116 038216 038316 038416 038816 038916 038A16 038B16 038C16 038D16 039716 039816 039916 Timer X0 mode register (TX0MR) Timer X1 mode register (TX1MR) Timer X2 mode register (TX2MR) Timer X2 (TX2) Timer X0 interrupt control register (TX0IC) Timer X1 interrupt control register (TX1IC) Timer X2 interrupt control register (TX2IC) Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF)
Timer X0 (TX0) Timer X1 (TX1)
Figure 2.4.1. Memory map of timer X-related registers
221
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address TXiMR(i = 0 to 2) 039716 to 039916
When reset 0016
Bit symbol
TMOD0 TMOD1
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode or pulse period/ pulse width measurement mode 1 1 : Pulse width modulation (PWM) mode
R
W
MR0 MR1 MR2 MR3 TCK0 TCK1
Function varies with each operation mode
Count source select bit (Function varies with each operation mode)
Note 1: Must set “00” to operation mode select bit when using timer X2 of M30200.
Timer Xi register (Note 1)
(b15) b7 (b8) b0 b7 b0
Symbol TX0 TX1 TX2
Function
Address 038916,038816 038B16,038A16 038D16,038C16
When reset Indeterminate Indeterminate Indeterminate
Values that can be set
RW
• Timer mode Counts an internal count source
000016 to FFFF16
• Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow • One-shot timer mode Counts a one shot width
• Pulse period / pulse width measurement mode Measures a pulse period or width
000016 to FFFF16 (Note 2)
• Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator • Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator Note 1: Read and write data in 16-bit units. Note 2: Use MOV instruction to write to this register.
000016 to FFFE16 (Note 2) 0016 to FF16(Note 2) (High-order addresses) 0016 to FF16 (Note 2) (Low-order addresses)
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Address 038016
When reset 000X00002
Bit symbol
TA0S TX0S TX1S TX2S
Bit name
Timer A0 count start flag Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Function
0 : Stops counting 1 : Starts counting
RW
Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TB0S TB1S CDCS Timer B0 count start flag Timer B1 count start flag
Clock devided count start flag
0 : Stops counting 1 : Starts counting
Figure 2.4.2. Timer X-related registers (1)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Address 038216
When reset XXXX00002
Bit symbol
TA0OS TX0OS TX1OS TX2OS
Bit name Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag
Function
1 : Timer start When read, the value is “0”
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Address 038316
When reset 0016
Bit symbol
TA0TGL
Bit name Timer A0 event/trigger select bit
Function
b1 b0
RW
TA0TGH TX0TGL
0 0 : Input on TA0IN is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected
b3 b2
Timer X0 event/trigger select bit
TX0TGH TX1TGL TX1TGH
0 0 : Input on TX0INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected
b5 b4
Timer X1 event/trigger select bit
0 0 : Input on TX1INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected
b7 b6
TX2TGL TX2TGH
Timer X2 event/trigger select bit
0 0 : Input on TX2INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”(input mode).
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol Nothing is assigned.
Bit name
Function
RW
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Figure 2.4.3. Timer X-related registers (2)
223
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.2 Operation of Timer X (timer mode)
In timer mode, choose functions from those listed in Table 2.4.1. Operations of the circled items are described below. Figure 2.4.4 shows the operation timing, and Figure 2.4.5 shows the set-up procedure. Table 2.4.1. Choosed functions
Item Count source Pulse output function O O Set-up Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output Gate function O No gate function Performs count only for the period in which the TXiINOUT pin is at “L” level Performs count only for the period in which the TXiINOUT pin is at “H” level
Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Xi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
n = reload register content
Counter content (hex)
FFFF16
(1) Start count
(2) Underflow
(3) Stop count
n Start count again
000016 Time Set to “1” by software “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timer Xi interrupt request bit “1” “0” Cleared to “0” by software Set to “1” by software
Count start flag
Figure 2.4.4. Operation timing of timer mode
224
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Selecting timer mode and functions
b7 b0
0
0
0
0
0
Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TXiINOUT pin is a normal port pin) Gate function select bit
b4 b3
00: 01:
Gate function not available (TXiINOUT pin is a normal port pin)
0 (Must always be “0” in timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
Timer X0 register [Address 038916, 038916] TX0 Timer X1 register [Address 038B16, 038A16] TX1 Timer X2 register [Address 038D16, 038C16] TX2
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Start count
Figure 2.4.5. Set-up procedure of timer mode
225
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.3 Operation of Timer X (timer mode, gate function selected)
In timer mode, choose functions from those listed in Table 2.4.2. Operations of the circled items are described below. Figure 2.4.6 shows the operation timing, and Figure 2.4.7 shows the set-up procedure. Table 2.4.2. Choosed functions
Item Count source Pulse output function O O Set-up Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TXiINOUT pin is at “L” level O Performs count only for the period in which the TXiINOUT pin is at “H” level
Operation (1) When the count start flag is set to “1” and the TXiINOUT pin inputs at “H” level, the counter performs a down count on the count source. (2) When the TXiINOUT pin inputs at “L” level, the counter holds its value and stops. (3) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer Xi interrupt request bit goes to “1”. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Note • Make the pulse width of the signal input to the TXiINOUT pin not less than two cycles of the count source.
n = reload register content FFFF16 n
Counter content (hex)
(1) Start count
(3) Underflow
(2) Stop count
(4) Stop count
Start count again. 000016 Set to “1” by software Cleared to “0” by software Time Set to “1” by software
Count start flag
“1” “0” “H” “L” Cleared to “0” when interrupt request is accepted, or cleared by software
TXiINOUT pin input signal
Timer Xi interrupt request bit
“1” “0 ”
Figure 2.4.6. Operation timing of timer mode, gate function selected
226
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Selecting timer mode and functions
b7 b0
0
1
1
0
0
0
Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Selection of timer mode Pulse output function select bit 0 : Pulse is not output (Set to “0” when gate function selected) Gate function select bit
b4 b3
1 1 : Timer counts only when TXiINOUT pin is held “H” (Note) 0 (Must always be “0” in timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note: Set the corresponding port direction register to “0” (input mode).
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
Timer X0 register [Address 038916, 038816] TX0 Timer X1 register [Address 038B16, 038A16] TX1 Timer X2 register [Address 038D16, 038c16] TX2
Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Start count
Figure 2.4.7. Set-up procedure of timer mode, gate function selected
227
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.4 Operation of Timer X (timer mode, pulse output function selected)
In timer mode, choose functions from those listed in Table 2.4.3. Operations of the circled items are described below. Figure 2.4.8 shows the operation timing, and Figure 2.4.9 shows the set-up procedure. Table 2.4.3. Choosed functions
Item Count source Pulse output function O Gate function O O Set-up Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TXiINOUT pin is at “L” level Performs count only for the period in which the TXiINOUT pin is at “H” level
Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer Xi interrupt request bit goes to “1”. Also, the output polarity of the TXiINOUT pin reverses. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TXiINOUT pin outputs an “L” level.
n = reload register content (2) Underflow FFFF16 (1) Start count (3) Stop count
Counter content (hex)
n Start count again
000016 Time Set to “1” by software “1” “0” Cleared to “0” by software Set to “1” by software
Count start flag
Pulse output from “H” TXiINOUT pin “L” Cleared to “0” when interrupt request is accepted, or cleared by software Timer Xi interrupt request bit “1” “0”
Figure 2.4.8. Operation timing of timer mode, pulse output function selected
228
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Selecting timer mode and functions
b7 b0
0
0
1
0
0
Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Selection of timer mode Pulse output function select bit 1 : Pulse is output (Note) (TXiINOUT pin is a pulse output pin) Gate function select bit
b4 b3
00: 0 1 : Gate function not available (Set to “0X” when pulse output function selected) 0 (Must always be “0” in timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Note: Set the corresponding port direction register to “1” (output mode).
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
Timer X0 register [Address 038916, 038816] TX0 Timer X1 register [Address 038B16, 038A16] TX1 Timer X2 register [Address 038D16, 038C16] TX2 Can be set to 000016 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Start count
Figure 2.4.9. Set-up procedure of timer mode, pulse output function selected
229
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.5 Operation of Timer X (event counter mode, reload type selected)
In event counter mode, choose functions from those listed in Table 2.4.4. Operations of the circled items are described below. Figure 2.4.10 shows the operation timing, and Figure 2.4.11 shows the set-up procedure. Table 2.4.4. Choosed functions
Item Count source Set-up Input signal to TXiINOUT(counting falling edges) Input signal to TXiINOUT(counting rising edges) O Pulse output function O Count operation type O Timer overflow(TB1/TA0/TXi overflow) No pulses output Pulses output Reload type Free-run type
Operation (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Xi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
n = reload register content FFFF16
Counter content (hex)
(1) Start count
(2) Underflow
(4) Stop count
n Start count again
000016 Time Set to “1” by software “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timer Xi interrupt “1” request bit “0” Cleared to “0” by software Set to “1” by software
Count start flag
Figure 2.4.10. Operation timing of event counter mode, reload type selected
230
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Selecting event counter mode and functions
b7 b0
0
0
1
0
1
Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Selection of event counter mode Pulse output function select bit (Note) 1 : Pulse is output (TXiINOUT pin is a pulse output pin) Invalid when the external signal is not used as a count source. Invalid in event counter mode Can be “0” or “1”. 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type Invalid in event counter mode Can be “0” or “1”.
Note : Set the corresponding port direction register to “1” (output mode). TXiINOUT pin input is not selected as count source when pulse output function is selected.
Setting trigger select register
b7 b0
Trigger select register [Address 038316] TRGSR Timer X0 event/trigger select bit
b3 b2
0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected Timer X1 event/trigger select bit
b5 b4
0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected Timer X1 event/trigger select bit
b7 b6
0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
Timer X0 register [Address 038916, 038816] TX0 Timer X1 register [Address 038B16, 038A16] TX1 Timer X2 register [Address 038D16, 038C16] TX2
Can be set to 000016 to FFFF16
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Start count
Figure 2.4.11. Set-up procedure of event counter mode, reload type selected
231
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.6 Operation of Timer X (event counter mode, free run type selected)
In event counter mode, choose functions from those listed in Table 2.4.5. Operations of the circled items are described below. Figure 2.4.12 shows the operation timing, and Figure 2.4.13 shows the set-up procedure. Table 2.4.5. Choosed functions
Item Count source O Set-up Input signal to TXiINOUT(counting falling edges) Input signal to TXiINOUT(counting rising edges) Timer overflow(TB1/TA0/TXi overflow) Pulse output function O No pulses output Pulses output Count operation type O Reload type Free-run type
Operation (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer Xi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop.
n = reload register content (1) Start count (2) Underflow FFFF16 Start count again n (4) Stop count
Counter content (hex)
000016 Time Set to “1” by software “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timer Xi interrupt “1” request bit “0” Cleared to “0” by software Set to “1” by software
Count start flag
Figure 2.4.12. Operation timing of event counter mode, free run type selected
232
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Selecting event counter mode and functions
b7 b0
1
0
0
0
0
1
Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Selection of event counter mode Pulse output function select bit 0 : Pulse is not output Count polarity select bit 0 : Counts external signal's falling edge Invalid in event counter mode Can be “0” or “1”. 0 (Must always be “0” in event counter mode) Count operation type select bit 1 : Free-run type Invalid in event counter mode Can be “0” or “1”.
Setting trigger select register
b7 b0
Trigger select register [Address 038316] TRGSR Timer X0 event/trigger select bit
b3 b2
0 0 : Input on TX0INOUT is selected (Note) Timer X1 event/trigger select bit
b5 b4
0 0 : Input on TX1INOUT is selected (Note) Timer X1 event/trigger select bit
b7 b6
0 0 : Input on TX2INOUT is selected (Note) Note: Set the corresponding port direction register to “0”(input mode).
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
Timer X0 register [Address 038916, 038816] TX0 Timer X1 register [Address 038B16, 038A16] TX1 Timer X2 register [Address 038D16, 038C16] TX2
Can be set to 000016 to FFFF16
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Start count
Figure 2.4.13. Set-up procedure of event counter mode, free run type selected
233
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.7 Operation of Timer X (one-shot timer mode)
In one-shot timer mode, choose functions from those listed in Table 2.4.6. Operations of the circled items are described below. Figure 2.4.14 shows the operation timing, and Figure 2.4.15 shows the set-up procedure. Table 2.4.6. Choosed functions
Item Count source Pulse output function O Count start condition O Set-up Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output External trigger input (falling edge of input signal to the TXiINOUT pin) External trigger input (rising edge of input signal to the TXiINOUT pin) Timer overflow (TB1/TX0/TXi overflow) O Writing “1” to the one-shot start flag
Operation (1) Setting the one-shot start flag to “1” with the count start flag set to “1” causes the counter to perform a down count on the count source. At this time, the TXiINOUT pin outputs an “H” level. (2) The instant the value of the counter becomes “000016”, the TXiINOUT pin outputs an “L” level, and the counter reloads the content of the reload register and stops counting. At this time, the timer Xi interrupt request bit goes to “1”. (3) If a trigger occurs while a count is in progress, the counter reloads the value in the reload register again and continues counting. The reload timing is in step with the next count source input after the trigger. (4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the reload register. Also, the TXiINOUT pin outputs an “L” level. At this time, the timer Xi interrupt request bit goes to “1”.
n = reload register content
Counter content (hex)
FFFF16 n
(1) Start count
(2) Stop count (3) Start count
Start count
(4) Stop count
Reload
Reload
Reload
000116 Set to “1” by software Count start flag Write signal to one-shot start flag One-shot pulse output “H” from TXiINOUT pin “L” Timer Xi interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software “1” “0” Cleared to “0” by software Time
1 / fi X (n)
1 / fi X (n+1)
Figure 2.4.14. Operation timing of one-shot mode
234
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Selecting one-shot timer mode and functions
b7 b0
0
0
1
1
0
Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Selection of one-shot timer mode Pulse output function select bit (Note) 1 : Pulse is output (TXiINOUT pin is a pulse output pin) Invalid when the external signal is not used as a count source. Trigger select bit 0 : When the one-shot start flag is set “1” 0 (Must always be “0” in one-shot timer mode) Count source select bit
b7 b6
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
0 0 1 1
0 1 0 1
Note: Set the corresponding port direction register to “1” (output mode). TXiINOUT pin is not selected as count source when pulse output function selected.
Clearing timer Xi interrupt request bit
b7 b0
Refer to 'Precaution for Timer X (one shot timer mode)'
0
Timer Xi interrupt control register [Address 005516] TXiIC (i = 0 to 2) Interrupt request bit
Setting one-shot timer's time
(b15) b7 (b8) b0 b7 b0
Timer X0 register [Address 038916, 038816] TX0 Timer X1 register [Address 038B16, 038A16] TX1 Timer X2 register [Address 038D16, 038C16] TX1
Can be set to 000116 to FFFF16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Setting one-shot start flag
b7 b0
One-shot start flag [Address 038216] ONSF Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag
Start count
Figure 2.4.15. Set-up procedure of one-shot mode
235
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.8 Operation of Timer X (pulse period measurement mode)
In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.4.7. Operations of the circled items are described below. Figure 2.4.16 shows the operation timing, and Figure 2.4.17 shows the set-up procedure. Table 2.4.7. Choosed functions
Item Count source Measurement mode O Internal count source (f1 / f8 / f32 / fc32) O Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) Set-up
Operation (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If a measurement pulse changes from “H” to “L”, the value of the counter goes to “000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Xi interrupt request does not generate. (3) If a measurement pulse changes from “H” to “L” again, the value of the counter is transferred to the reload register, and the timer Xi interrupt request bit goes to “1”. Then the value of the counter becomes “000016”, and the measurement is started again. Note • The timer Xi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Xi is overflowed. The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine. • The value of the counter at the beginning of a count is indeterminate. Thus there can be instances in which the timer Xi overflow flag goes to “1” immediately after a count is performed. • The timer Xi overflow flag goes to “0” if timer Xi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software.
Measurement of pulse time interval from falling edge to falling edge
(1) Start count Count source Measurement pulse Reload register ← counter transfer timing (Note 1) Timing at which counter reaches “000016” Count start flag Timer Xi interrupt request bit Timer Xi overflow flag “1” “0” “1” “0” “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software “H” “L” Transfer (indeterminate value) (Note 1) Transfer (measured value) (Note 2) (2) Start measurement (3) Start measurement again
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 2.4.16. Operation timing of pulse period measurement mode
236
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Selecting pulse period / pulse width measurement mode and functions
b7 b0
1
0
0
1
0
Timer Xi mode register (i=0 to 2) [Address 039716 to 039916] TXiMR (i=0 to 2) Selection of pulse period / pulse width measurement mode Measurement mode select bit
b3 b2
0 0 : Pulse period measurement (Interval between measurement pulse falling edge to falling edge) Timer Xi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed 1 (Must always be “1” in pulse period / pulse width measurement mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note: Set the corresponding port direction register which sets the measurement pulse to “0” (input mode).
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Start count
Clearing overflow flag
b7 b0
0
Timer Xi mode register (i=0 to 2) [Address 039716 to 039916] TXiMR (i=0 to 2) Timer Xi overflow flag 0 : Timer did not overflow
Figure 2.4.17. Set-up procedure of pulse period measurement mode
237
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.9 Operation of Timer X (pulse width measurement mode)
In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.4.8. Operations of the circled items are described below. Figure 2.4.18 shows the operation timing, and Figure 2.4.19 shows the set-up procedure. Table 2.4.8. Choosed functions
Item Count source Measurement mode O Internal count source (f1 / f8 / f32 / fc32) Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) O Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) Set-up
Operation (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If an effective edge of a pulse to be measured is input, the value of the counter goes to “000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Xi interrupt request does not generate. (3) If an effective edge of a pulse to be measured is input again, the value of the counter is transferred to the reload register, and the timer Xi interrupt request bit goes to “1”. Then the value of the counter becomes “000016”, and measurement is started again. Note • The timer Xi interrupt request bit goes to “1” when an effective edge of a pulse to be measured is input or timer Xi is overflows. The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine. • The value of the counter at the beginning of a count is indeterminate. Thus there can be instances in which the timer Xi overflow flag goes to “1” immediately after a count is performed. • The timer Xi overflow flag goes to “0” if timer Xi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software.
(1) Start count
(3) Start measurement again
(2) Start measurement Count source Measurement pulse Reload register ← counter transfer timing Timing at which counter reaches “000016” Count start flag “1” “0” “H” “L” Transfer (indeterminate value) (Note 1) Transfer(measured value)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
Timer Xi interrupt request bit “1” “0” Timer Xi overflow flag “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 2.4.18. Operation timing of pulse width measurement mode
238
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Selecting pulse period / pulse width measurement mode and functions
b7 b0
1
1
0
1
0
Timer Xi mode register (i=0 to 2) [Address 039716 to 039916] TXiMR (i=0 to 2) Selection of pulse period / pulse width measurement mode Measurement mode select bit
b3 b2
1 0 : Pulse width measurement (Interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) Timer Xi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed 1 (Must always be “1” in pulse period / pulse width measurement mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note: Set the corresponding port direction register which sets the measurement pulse to “0” (input mode).
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count start flag
b7 b0
Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Start count
Clearing overflow flag
b7 b0
0
Timer Xi mode register (i=0 to 2) [Address 039716 to 039916] TXiMR (i=0 to 2) Timer Xi overflow flag 0 : Timer did not overflow
Figure 2.4.19. Set-up procedure of pulse width measurement mode
239
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.10 Operation of Timer X (pulse width modulation mode, 16-bit PWM mode selected)
In pulse width modulation mode, choose functions from those listed in Table 2.4.9. Operations of the circled items are described below. Figure 2.4.20 shows the operation timing, and Figure 2.4.21 shows the set-up procedure. Table 2.4.9. Choosed functions
Item Count source PWM mode O O Set-up Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM Count start condition O Timer overflow (TB1/TA0/TXi overflow)
Operation (1) Selected timer overflow is generated with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TXiINOUT pin outputs an “H” level. (2) The TXiINOUT pin output level changes from “H” to “L” when a set time period elapses. At this time, the timer Xi interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TXiINOUT outputs an “L” level. Note • PWM pulse cycle is (216 -1)/fi, whereas “H” level duration is n/fi. However, when “000016” is set for the timer A0 register, the PWM output is “L” level for the entire period, and an interrupt request is generated for every PWM output cycle. Also, when “FFFF16” is set for the timer A0 register, the PWM output is “H” level for the entire period, and an interrupt request is generated for every PWM output cycle. (fi: Count source frequency f1, f8, f32, fC32 n: Timer value)
Conditions: Reload register = 000316, when timer overflow is selected in trigger
1 / fi X (2
16
–1)
Count source
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Interrupt request bit becoming trigger “H ”
“L”
Set to “1” by software Count start flag “1” “0” (1) Start count (2) Output level “H” to “L”
1 / fi X n
PWM pulse output “H” from TXiINOUT pin “L”
Cleared to “0” by software
(3) One period is complete
(4) Stop count
Cleared to “0” when interrupt request is accepted, or cleared by software
Timer Xi interrupt “1” request bit “0”
Note: n = 000016 to FFFE16
Figure 2.4.20. Operation timing of pulse width modulation mode, 16-bit PWM mode selected
240
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Selecting PWM mode and functions
b7 b0
0
1
1
1
1
Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Selection of PWM mode 1 (Must always be “1” in PWM mode) Invalid in event counter mode Can be “0” or “1”. Trigger select bit 1 : Selected by event/trigger select register 16/8-bit PWM mode select bit 0 : Functions as a 16-bit pulse width modulator Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note: Set the corresponding port direction register which outputs the pulse to “1” (output mode).
Clearing timer Xi interrupt request bit
b7 b0
Refer to 'Precaution for Timer X (pulse width modulation mode)'
0
Timer Xi interrupt control register (i = 0 to 2) [Address 005616 to 005816] TXiIC (i = 0 to 2) Interrupt request bit
Setting trigger select register
b7 b0
Trigger select register [Address 038316] TRGSR Timer X0 event/trigger select bit
b3 b2
0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected Timer X1 event/trigger select bit
b5 b4
0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected Timer X1 event/trigger select bit
b7 b6
0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected
Setting PWM pulse's “H” level width
(b15) b7 (b8) b0 b7 b0
Timer X0 register [Address 038916, 038816] TX0 Timer X1 register [Address 038B16, 038A16] TX1 Timer X2 register [Address 038D16, 038C16] TX2
Can be set to 000016 to FFFE16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count starts flag
b7 b0
Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Start count
Figure 2.4.21. Set-up procedure of pulse width modulation mode, 16-bit PWM mode selected
241
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.11 Operation of Timer X (pulse width modulation mode, 8-bit PWM mode selected)
In pulse width modulation mode, choose functions from those listed in Table 2.4.10. Operations of the circled items are described below. Figure 2.4.22 shows the operation timing, and Figure 2.4.22 shows the set-up procedure. Table 2.4.10. Choosed functions
Item Count source PWM mode O Count start condition O O Set-up Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM Timer overflow (TB1/TA0/TXi overflow)
Operation (1) Selected timer overflow is generated with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TXiINOUT pin outputs an “H” level. (2) The TXiINOUT pin output level changes from “H” to “L” when a set time period elapses. At this time, the timer Xi interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TXiOUT pin outputs an “L” level. Note • PWM pulse cycle is (m + 1( x (28 -1)/fi, whereas “H” level duration is n x (m + 1)/fi. However, when “0016” is set for the significant 8 bits of the timer A0 register, the PWM output is “L” level for the entire period, and an interrupt request is generated for every PWM output cycle. Also, when “FF16” is set for the significant 8 bits of the timer A0 register, the PWM output is “H” level for the entire period, and an interrupt request is generated for every PWM output cycle. (fi: Count source frequency f1, f8, f32, fC32 n: Timer value)
Conditions:Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 When timer overflow is selected in trigger
1 / fi X (m + 1) X (2 – 1) Count source (Note 1)
8
“1”
Count start flag
“0”
(1) Start count
(2) Output level “H” to “L”
Cleared to “0” when interrupt request is accepted, or cleared by software Interrupt request bit of timer becoming trigger
“H” “L”
(3) One period is complete (4) Stop count
1 / fi X (m+1) Underflow signal of 8 “H” -bit prescaler (Note 2) “L”
“H”
1 / fi X (m + 1) X n
PWM pulse output from TXiINOUT pin Timer Xi interrupt request bit
“L”
Cleared to “0” when interrupt request is accepted, or cleared by software
“1” “0”
Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FF16.
Figure 2.4.22. Operation timing of pulse width modulation mode, with 8-bit PWM mode selected
242
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Selecting PWM mode and functions
b7 b0
1
1
1
1
1
Timer Xi mode register (i = 0 to 2) [Address 039716 to 039916] TXiMR (i = 0 to 2) Selection of PWM mode 1 (Must always be “1” in PWM mode) Invalid in event counter mode Can be “0” or “1”. Trigger select bit 1 : Selected by event/trigger select register 16/8-bit PWM mode select bit 1 : Functions as a 8-bit pulse width modulator Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note: Set the corresponding port direction register which outputs the pulse to “1” (output mode).
Clearing timer Xi interrupt request bit
b7 b0
Refer to 'Precaution for Timer X (pulse width modulation mode)'
0
Timer Xi interrupt control register (i = 0 to 2)[Address 005616 to 005816] TXiIC (i = 0 to 2) Interrupt request bit
Setting trigger select register
b7 b0
Trigger select register [Address 038316] TRGSR Timer X0 event/trigger select bit
b3 b2
0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected Timer X1 event/trigger select bit
b5 b4
0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected Timer X1 event/trigger select bit
b7 b6
0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected
Setting PWM pulse's “H” level width
(b15) b7 (b8) b0 b7 b0
Timer X0 register [Address 038916, 038816] TX0 Timer X1 register [Address 038B16, 038A16] TX1 Timer X2 register [Address 038D16, 038C16] TX2
Can be set to 000016 to FFFE16
Setting clock prescaler reset flag
(This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.)
b7 b0
Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”)
Setting count starts flag
b7 b0
Count start flag [Address 038016] TABSR Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag
Start count
Figure 2.4.23. Set-up procedure of pulse width modulation mode, 8-bit PWM mode selected
243
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.12 Precautions for Timer X (timer mode, event counter mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Xi register, then set the flag to “1”. (2) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Xi register with the reload timing shown in Figure 2.4.24 gets “FFFF16”. Reading the timer Xi register after setting a value in the timer Xi register with a count halted but before the counter starts counting gets a proper value.
Reload
Counter value (Hex.)
2
1
0
n
n–1
Read value (Hex.)
2
1
0
FFFF
n–1
Time n = reload register content
Figure 2.4.24. Reading timer Xi register
244
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
2.4.13 Precautions for Timer X (one-shot timer mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Xi register, then set the flag to “1”. (2) Setting the count start flag to “0” while a count is in progress causes as follows: • The counter stops counting and a content of reload register is reloaded. • The TXiINOUT pin outputs “L” level. • The interrupt request generated and the timer Xi interrupt request bit goes to “1”. (3) The timer Xi interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures: • Selecting one-shot timer mode after reset. • Changing operation mode from timer mode to one-shot timer mode. • Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after the above listed changes have been made. (4) If a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To generate a trigger while a count is in progress, generate the second trigger after an elapse longer than one cycle of the timer's count source after the previous trigger occurred.
245
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.14 Precautions for Timer X (pulse period/pulse width measurement mode)
(1) The timer Xi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Xi is overflowed. The factor of interrupt request can be determined by use of the timer Xi overflow flag within the interrupt routine. (2) If the timer overflow occurs simultaneously with the input of a measurement pulse, and if the interrupt factor cannot be determined from the timer Xi overflow flag, connect the timers and count the number of overflows. (3) When reset, the timer Xi overflow flag goes to “1”. This flag cannot be set to “0” by writing to the timer Xi mode register when the count start flag is “1”. (4) Use the timer Xi interrupt request bit to detect only overflows. Use the timer Xi overflow flag only to determine the interrupt factor within the interrupt routine. (5) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Xi interrupt request is not generated. (6) The value of the counter is indeterminate at the beginning of a count. Therefore the timer Xi overflow flag may go to “1” immediately after a count is started. (7) If changing the measurement mode select bit is set after a count is started, the timer Xi interrupt request bit goes to “1”. (8) If the input signal to the TXiINOUT pin is affected by noise, precise measurement may not be performed in some cases. It is recommended to see that measurements fall within a specific range by use of software. (9) For pulse width measurement, pulse widths are successively measured. Use software to check whether the measurement result is an “H” level width or an “L” level width.
246
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X 2.4.15 Precautions for Timer X (pulse width modulation mode)
(1) To clear reset, the count start flag is set to “0”. Set a value in the timer Xi register, then set the flag to “1”. (2) The timer Xi interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures: • Selecting PWM mode after reset. • Changing operation mode from timer mode to PWM mode. • Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after the above listed changes have been made. (3) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TXiINOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer Xi interrupt request bit goes to “1”. If the TXiINOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Xi interrupt request bit does not becomes “1”. (4) Normal PWM output is restored according to the interrupt request generate timing, both in the case of 16-bit PWM and 8-bit PWM, when PWM output is either “H” or “L” level for the entire period. This holds only when a value other than “000016” or “FFFF16” is set during 16bit PWM, or a value other than “0016” or “FF16” is set during 8-bit PWM.
Normal PWM restored here
When PWM output is “H” level for the entire period
Writing to the timer Xi
1 / fi X (n)
PWM pulse output from TXiINOUT pin Timer Xi interrupt request bit
"H" "L"
"1" "0"
Cleared to “0” when interrupt request is accepted, or cleared by software
When PWM output is “L” level for the entire period
Writing to the timer Xi PWM pulse output from TXiINOUT pin
"H" "L" 1 / fi X (n)
Timer Xi interrupt request bit (i = 0 to 2)
"1" "0"
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.4.25. Operation timing of PWM output mode
247
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
2.5 Clock-Synchronous Serial I/O 2.5.1 Overview
Clock-synchronous serial I/O carries out 8-bit data communications in synchronization with the clock. The following is an overview of the clock-synchronous serial I/O. (1) Transmission/reception format 8-bit data (2) Transfer rate If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit rate generator division, becomes the transfer rate. The bit rate generator count source can be selected from the following: f1, f8, f32, and fC. Clocks f1, f8 and f32 are derived by dividing the CPU’s main clock by 1, 8, and 32 respectively. Clock fC is derived by dividing the CPU’s sub clock by 1 respectively. Furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the CLK pin becomes the transfer rate. (3) Error detection Only overrun error can be detected. Overrun error is an error that occurs when the next data is made ready before the reception buffer register is read. (4) How to deal with an error When receiving data, read an error flag and reception data simultaneously to determine which error has occurred. If the data read is erroneous, initialize the error flag and the UART0 receive buffer register, then receive the data again. To initialize the UART0 receive buffer register 1. Set the receive enable bit to “0” (disable reception). 2. Set the serial I/O mode select bit to “0002” (invalid serial I/O). 3. Set the serial I/O mode select bit. 4. Set the receive enable bit to “1” again (enable reception). To transmit data again due to an error on the reception side when external clock is selected, clear the UART0 transmit buffer register, then transmit the data again. To clear the UART0 transmit buffer register 1. Set the port P52 (CLK0 pin) direction register to “0” (input mode). 2. Set the port P50 (TxD0 pin) direction register to “0” (input mode). 3. Set the internal/external clock select bit to “0” (internal clock). 4. Checking complection of transmission (no data present in transmit register). 5. Set the internal/external clock select bit to “1” (external clock). 6. Set the port P50 (TxD0 pin) direction register to “1” (output mode), then set transmission data in the UART0 transmit buffer register.
248
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
(5) Function selection For clock-synchronous serial I/O, the following functions can be selected: (a) Function for choosing polarity This function switches the polarity of the transfer clock. The following operations are available: • Data is input at the falling edge of the transfer clock, and is output at the rising edge. • Data is input at the rising edge of the transfer clock, and is output at the falling edge. (b) Function for choosing which bit to transmit first This function is to choose whether to transmit data from bit 0 or from bit 7. Choose either of the following: • LSB first Data is transmitted from bit 0. • MSB first Data is transmitted from bit 7. (c) Function for choosing successive reception mode Successive reception mode is a mode in which reading the receive buffer register makes the reception-enabled status ready. In this mode, there is no need to write dummy data to the transmit buffer register so as to make the reception-enabled status ready. But at the time of starting reception, read the receive buffer register into a dummy manner. • Normal mode Writing dummy data to the transmit buffer register makes the reception enabled status ready. Reading the reception buffer register makes the reception-enabled • Successive reception mode status ready. (d) Function for outputting transfer clock to multiple pins This function is to switch among pins to output the transfer clock. This function is effective only when selecting the internal clock. Switching among pins for outputting the transfer clock allows data transmission to two external ICs in a time-sharing manner. (e) Function for choosing a transmission interrupt factor The timing to generate a transmission interrupt can be selected from the following: the instant the transmission buffer is emptied or the instant the transmission register is emptied. When transmission buffer empty timing is selected, an interrupt occurs when transmitted data is moved from the transmission buffer to the transmission register. Therefore, data can be transmitted in succession. When transmission register empty timing is selected, an interrupt occurs when data transmission is complete. Following are some examples in which various functions (a) through (e) are selected: • Transmission Operation WITH: transmission at falling edge of transfer clock, LSB First, interrupt at instant transmission buffer is emptied; WITHOUT transfer clock output to multiple pins function ... ................................................................................................................................................ P254 • Transmission Operation WITH: transmission at falling edge of transfer clock, LSB First, interrupt at instant transmission is completed; WITH transfer clock output to multiple pins function (UART0 selection available) .................................................................................................................. P258 • Reception WITH: reception at falling edge of transfer clock, LSB First, successive reception mode disabled; WITHOUT transfer clock output to multiple pins function ........................................ P262
249
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
(6) Input/output to the serial I/O and the direction register To input an external signal to the serial I/O, set the direction register of the relevant port to input. To output signal from the serial I/O, set the direction register of the relevant port to output. (7) Pins related to the serial I/O • CLK0 pin Input/output pins for the transfer clock • RxD0, RxD1 pins Input pins for data • TxD0, TxD1 pins Output pins for data (Since TxD2 pin is N-channel open drain, this pin needs pull-up resistor.) • CLKS pin Output pin for transfer clock. Can be used as transfer clock output pin in the transfer clock output to multiple pins function. Note : UART1 cannot be used in clock-synchronous serial I/O mode. (8) Registers related to the serial I/O Figure 2.5.1 shows the memory map of serial I/O-related registers, and Figures 2.5.2 to 2.5.4 show serial I/O-related registers.
005116 005216 005316 005416 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116
UART0 UART0 UART1 UART1
transmit interrupt control register (S0TIC) receive interrupt control register (S0RIC) transmit interrupt control regster(S1TIC) receive interrupt control register(S1RIC)
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Figure 2.5.1. Memory map of serial I/O-related registers
250
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
UARTi transmit buffer register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB
Address 03A316, 03A216 03AB16, 03AA16
When reset Indeterminate Indeterminate
Function Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
RW
Note : Use MOV instruction to write to this register.
UARTi receive buffer register
(b15) b7 (b8) b0 b7 b0
Symbol U0RB U1RB
Address 03A716, 03A616 03AF16, 03AE16
When reset Indeterminate Indeterminate
Bit symbol
Bit name
Function (During clock synchronous serial I/O mode) Receive data
Function (During UART mode) Receive data
RW
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. OER FER PER SUM Overrun error flag (Note) Framing error flag (Note) Parity error flag (Note) Error sum flag (Note) 0 : No overrun error 1 : Overrun error found Invalid Invalid Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found
Note: Bits 15 through 12 are set to “0” when the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A616, and 03AE16) is read out.
UARTi bit rate generator (Note 1, 2)
b7 b0
Symbol U0BRG U1BRG
Address 03A116 03A916
When reset Indeterminate Indeterminate
Function Assuming that set value = n, BRGi divides the count source by n + 1
Values that can be set 0016 to FF16
RW
Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register.
Figure 2.5.2. Serial I/O-related registers (1)
251
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol SMD0 SMD1 SMD2
Bit name Serial I/O mode select bit (Note 1)
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited 0 : Internal clock (Note 3) 1 : External clock (Note 4) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
CKDIR Internal/external clock select bit (Note 2) STPS PRY Stop bit length select bit
0 : Internal clock (Note 3) 1 : External clock (Note 4) Invalid
Odd/even parity select bit Invalid
PRYE SLEP
Parity enable bit Sleep select bit
Invalid Must always be “0”
Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: UART1 can use only internal clock. Must set this bit to “1”. Note 3: Set the corresponding port direction register to “1” (output mode). Note 4: Set the corresponding port direction register to “0” (input mode).
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol UiC0(i=0,1)
Bit symbol CLK0 CLK1
Set this bit to “0”.
Address 03A416, 03AC16
When reset 0816
Function (During UART mode)
b1 b0
Bit name BRG count source select bit
Function (Note) (During clock synchronous serial I/O mode)
b1 b0
RW
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected
TXEPT
Transmit register empty flag
0 : Data present in transmit 0 : Data present in transmit register register (during transmission) (during transmission) 1 : No data present in transmit 1 : No data present in transmit register (transmission register (transmission completed) completed)
Set this bit to “1”.
NCH
Data output select bit
0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output
CKPOL
CLK polarity select bit
Must always be “0”
UFORM Transfer format select bit 0 : LSB first 1 : MSB first Note: UART1 cannot be used in clock synchronous serial I/O.
Must always be “0”
Figure 2.5.3. Serial I/O-related registers (2)
252
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC1(i=0,1)
Address 03A516,03AD16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit Transmit buffer empty flag
Function (Note 1) (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
RW
RE RI
Receive enable bit (Note 2) Receive complete flag
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: If you are using clock asynchronous serial I/O mode, you can enable 'receive enable bit' when RxD port input is “H”. If RxD port input is “L” and you have enabled 'receive enable bit' , then receive operation starts immediately.
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UCON
Address 03B016
When reset XX0000002
Bit symbol U0IRS
Bit name UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit
Function (During clock synchronous serial I/O mode)
0 : Transmit buffer empty
(Tl = 1)
Function (During UART mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1)
RW
1 : Transmission completed
(TXEPT = 1)
U1IRS
Set this bit to “0”.
U0RRM UART0 continuous receive mode enable bit
0 : Continuous receive mode disabled 1 : Continuous receive mode enable
Must always be “0”
Set this bit to “0”. CLKMD0 CLK/CLKS select bit 0 Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode
(CLK output is CLK0 only)
Must always be “0”
CLKMD1 CLK/CLKS select bit 1 (Note 2)
Must always be “0”
1 : Transfer clock output from multiple pins function selected Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: When using multiple pins to output the transfer clock, the following requirements must be met: • UART0 internal/external clock select bit (bit 3 at address 03A016) = “0”.
Figure 2.5.4. Serial I/O-related registers (3)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
2.5.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode)
In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.5.1. Operations of the circled items are described below. Figure 2.5.5 shows the operation timing, and Figures 2.5.6 and 2.5.7 show the set-up procedures. Table 2.5.1. Choosed functions
Item Transfer clock source CLK polarity O Internal clock (f1 / f8 / f32 / fc) External clock (CLK0 pin) O Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock Transfer clock O LSB first MSB first Transmission interrupt factor O Transmission buffer empty Transmission complete Set-up
Output transfer clock O Not selected to multiple pins Selected (Note) Note: This can be selected only when UART0 is used in combination with the internal clock.
Operation (1) Setting the transmit enable bit to “1” and writing transmission data to the UART0 transmit buffer register makes data transmissible status ready. (2) In synchronization with the first falling edge of the transfer clock, transmission data held in the UART0 transmit buffer register is transmitted to the UART0 transmit register. At this time, the UART0 transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is transmitted from the TxD0 pin. Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges. (3) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”, which indicates that transmission is completed. The transfer clock stops at “H” level. (4) If the next transmission data is set in the UART0 transmit buffer register while transmission is in progress (before the eighth bit has been transmitted), the data is transmitted in succession.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
Example of wiring
Microcomputer
CLK0 TXD0
Receiver side IC
CLK RXD
Example of operation
(1) Transmission enabled (2) Start transmission Tc Transfer clock
(3) Transmission is complete (4) Transmit next data
Transmit enable bit (TE) Transmit buffer empty flag (Tl)
“1” “0” “1” “0” Transferred from UARTi transmit buffer register to UARTi transmit register TCLK Stopped pulsing because transfer enable bit = “0” Data is set to UARTi transmit buffer register
CLK0
TxD0 Transmit register “1” empty flag “0” (TXEPT) “1” Transmit interrupt request “0” bit (IR)
D0 D 1 D2 D3 D4 D5 D6
D7
D0 D 1 D2 D3 D4 D5 D 6 D7
D 0 D1 D2 D 3 D 4 D 5 D6 D7
Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • Internal clock is selected. • CLK polarity select bit = “0”. • Transmit interrupt cause select bit = “0”. Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32, fC) n: value set to BRGi
Figure 2.5.5. Operation timing of transmission in clock-synchronous serial I/O mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
Setting UART0 transmit/receive mode register
b7 b0
0
0
0
0
1
UART0 transmit/receive mode register
U0MR [Address 03A016]
Must be fixed to “001” Internal/external clock select bit 0 : Internal clock Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must be “0” in clock synchronous I/O mode
Setting UART0 transmit/receive control register 0
b7 b0
00
1
0
UART0 transmit/receive control register 0 U0C0 [Address 03A416]
BRG count source select bit
b1 b0
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fC is selected Must be “0” in clock synchronous I/O mode Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Must be “1” in clock synchronous I/O mode Data output select bit (Note) 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 : LSB first Note: Set the corresponding port direction register to “1” (output mode).
Setting UART transmit/receive control register 2
b7 b0
0
0
0
0
UART transmit/receive control register 2 UCON [Address 03B016] UART0 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) Must be “0” in clock synchronous I/O mode Must be “0” in clock synchronous I/O mode Valid when bit 5 = “1” CLK/CLKS select bit 1 0 : Normal mode
Continued to the next page
Figure 2.5.6. Set-up procedure of transmission in clock-synchronous serial I/O mode (1)
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Clock-Synchronous Serial I/O
Continued from the previous page
Setting UART0 bit rate generator
b7 b0
UART0 bit rate generator [Address 03A116] U0BRG Can be set to 0016 to FF16 (Note)
Note: Write to UART0 bit rate generator when transmission/reception is halted.
Transmission enabled
b7 b0
1
UART0 transmit/receive control register 1 [Address 03A516] U0C1 Transmit enable bit 1 : Transmission enabled
Writing transmit data
(b15) b7 (b8) b0 b7 b0
UART0 transmit buffer register [Address 03A316, 03A216] U0TB Setting transmission data
Start transmission
Checking the status of UART0 transmit buffer register
b7 b0
UART0 transmit/receive control register 1 [Address 03A516]U0C1
Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled)
Writing next transmit data
(b15) b7 (b8) b0 b7 b0
UART0 transmit buffer register [Address 03A316, 03A216] U0TB Setting transmission data
Transmission is complete
Figure 2.5.7. Set-up procedure of transmission in clock-synchronous serial I/O mode (2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
2.5.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected)
In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.5.2. Operations of the circled items are described below. Figure 2.5.8 shows the operation timing, and Figures 2.5.9 and 2.5.10 show the set-up procedures. Table 2.5.2. Choosed functions
Item Transfer clock source CLK polarity O Internal clock (f1 / f8 / f32 / fc) External clock (CLK0 pin) O Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock Transfer clock O LSB first MSB first Transmission interrupt factor Output transfer clock to multiple pins (Note) O Transmission buffer empty Transmission complete Not selected O Selected Set-up
Note: This can be selected only when UART0 is used in combination with the internal clock.
Operation (1) Setting the transmit enable bit to “1” makes data transmissible status ready. (2) When transmission data is written to the UART0 transmit buffer register, transmission data held in the UART0 transmit buffer register is transmitted to the UART0 transmit register in synchronization with the first falling edge of the transfer clock. At this time, the first bit of the transmission data is transmitted from the TxD0 pin. Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges of the transfer clock. (3) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”, which indicates that the transmission is completed. The transfer clock stops at “H” level. At this time, the UART0 transmit interrupt request bit goes to “1”. (4) Setting CLK/CLKS select bit 1 to “1” and setting CLK/CLKS select bit 0 to “1” causes the CLKS pin to go to the transfer clock output pin. Change the transfer clock output pin when transmission is halted.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
Example of wiring
Microcomputer
TXD0 (P50) CLKS (P53) CLK0 (P52) IN CLK IN CLK
Note: This applies when performing only transmission with an internal clock selected in the clock synchronous serial I/O mode.
Example of operation
(1) Transmission enabled (2) Start transmission Transfer clock Transmit enable bit “1” “0” Transmit buffer empty flag CLK, CLKS select bit 1 CLK, CLKS select bit 0 CLK0 CLKS TxD0 Transmit interrupt request bit “1” “0” D 0 D1 D 2 D 3 D 4 D5 D6 D 7 D 0 D1 D 2 D 3 D 4 D5 D6 D 7 “1” “0” “1” “0” “1” “0” (3) Transmission is complete (4) Clock switched
Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 2.5.8. Operation timing of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected
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Clock-Synchronous Serial I/O
Setting UART0 transmit/receive mode register
b7 b0
0
0
0
0
1
UART0 transmit/receive mode register
U0MR [Address 03A016]
Must be fixed to “001” Internal/external clock select bit 0 : Internal clock Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must be “0” in clock synchronous I/O mode
Setting UART0 transmit/receive control register 0
b7 b0
0
0
1
0
UART0 transmit/receive control register 0 U0C0 [Address 03A416]
BRG count source select bit
b1 b0
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fC is selected Must be “0” in clock synchronous I/O mode Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Must be “1” in clock synchronous I/O mode Data output select bit (Note) 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 : LSB first Note: Set the corresponding port direction register to “1” (output mode).
Setting UART transmit/receive control register 2
b7 b0
1
0
0
1
UART transmit/receive control register 2 UCON [Address 03B016] UART0 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) Must be “0” in clock synchronous I/O mode Must be “0” in clock synchronous I/O mode CLK/CLKS select bit 0 0 : Clock output to CLK0 1 : Clock output to CLKS CLK/CLKS select bit 1 1 : Transfer clock output from multiple pins finction selected
Continued to the next page
Figure 2.5.9. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected (1)
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Clock-Synchronous Serial I/O
Continued from the previous page
Setting UART0 bit rate generator
b7 b0
UART0 bit rate generator [Address 03A116] U0BRG Can be set to 0016 to FF16 (Note)
Note: Write to UART0 bit rate generator when transmission/reception is halted.
Transmission enabled
b7 b0
1
UART0 transmit/receive control register 1 [Address 03A516] U0C1 Transmit enable bit 1 : Transmission enabled
Writing transmit data
(b15) b7 (b8) b0 b7 b0
UART0 transmit buffer register [Address 03A316, 03A216] U0TB Setting transmission data
Start transmission
Checking the status of UART0 transmit buffer register
b7 b0
UART0 transmit/receive control register 1 [Address 03A516]U0C1 Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled)
Writing next transmit data
(b15) b7 (b8) b0 b7 b0
UART0 transmit buffer register [Address 03A316, 03A216] U0TB Setting transmission data
Transmission is complete
Figure 2.5.10. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected (2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
2.5.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)
In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.5.3. Operations of the circled items are described below. Figure 2.5.11 shows the operation timing, and Figures 2.5.12 and 2.5.13 show the set-up procedures. Table 2.5.3. Choosed functions
Item Transfer clock source CLK polarity Internal clock (f1 / f8 / f32 / fc) O O External clock (CLK0 pin) Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock Transfer clock O LSB first MSB first Continuous receive mode Output transfer clock to multiple pins (Note) O Disabled Enabled O Not selected Selected Set-up
Note: This can be selected only when UART0 is used in combination with the internal clock.
Operation (1) Writing dummy data to the UART0 transmit buffer register, setting the receive enable bit to “1”, and the transmit enable bit to “1”, makes the data receivable status ready. (2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxD0 pin is stored in the highest bit of the UART0 receive register. Then, data is taken in by shifting right the content of the UART0 reception data in synchronization with the rising edges of the transfer clock. (3) When 1-byte data lines up in the UART0 receive register, the content of the UART0 receive register is transmitted to the UART0 receive buffer register. The transfer clock stops at “H” level. At this time, the receive complete flag and the UART0 receive interrupt request bit goes to “1”. (4) The receive complete flag goes to “0” when the lower-order byte of the UART0 buffer register is read.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
Example of wiring
Microcomputer
CLK0 RXD0
Transmitter side IC
CLK TXD
Example of operation
(1) Reception enabled (2) Start reception Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) “1” “0” “1” “0” “1” “0” (3) Reception is complete (4) Read of reception data
Dummy data is set in UART0 transmit buffer register
Transferred from UART0 transmit buffer register to UART0 transmit register
1 / fEXT
CLK0 Reception data is taken in RxD0 Receive complete “1” flag (Rl) “0” Receive interrupt request bit (IR) “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software D 0 D1 D 2 D3 D 4 D5 D6
Transferred from UART0 receive register to UART0 receive buffer register
D7
D0 D 1 D 2
D3 D4 D5
Read out from UART0 receive buffer register
Shown in ( ) are bit symbols. The above timing applies to the following settings: • External clock is selected. • CLK polarity select bit = “0”. fEXT: frequency of external clock
Make sure that the following conditions are met when the CLK0 pin input =“H” before data reception • Transmit enable bit → “1” • Receive enable bit → “1” • Dummy data write to UART0 transmit buffer register
Figure 2.5.11. Operation timing of reception in clock-synchronous serial I/O mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
Setting UART0 transmit/receive mode register
b7 b0
0
10
01
UART0 transmit/receive mode register U0MR [Address 03A016] Must be fixed to “001” Internal/external clock select bit 1 : External clock Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must be “0” in clock synchronous I/O mode
Setting UARTi transmit/receive control register 0 (i=0 to 2)
b7 b0
0
0
1
0
UART0 transmit/receive control register 0 U0C0 [Address 03A416] BRG count source select bit Invalid when external clock is selected Must be “0” in clock synchronous I/O mode Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Must be “1” in clock synchronous I/O mode Data output select bit 0 : TxD0 pin is CMOS output 1 : TxD0 pin is N-channel open-drain output CLK polarity select bit (Note) 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 : LSB first
Note: Set the corresponding port direction register to “0” (input mode).
Setting UART transmit/receive control register 2
b7 b0
0
0
0
UART transmit/receive control register 2 UCON [Address 03B016] Must be “0” in clock synchronous I/O mode UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled Must be “0” in clock synchronous I/O mode Valid when bit 5 = “1” CLK/CLKS select bit 1 0 : Normal mode
Continued to the next page
Figure 2.5.12. Set-up procedure of reception in clock-synchronous serial I/O mode (1)
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Clock-Synchronous Serial I/O
Continued from the previous page
Reception enabled
b7 b0
1
1
UART0 transmit/receive control register 1 [Address 03A516] U0C1 Transmit enable bit 1 : Transmission enabled Receive enable bit (Note) 1 : Reception enabled
Note: Set the corresponding port direction register to “0” (input mode).
Writing dummy data
(b15) b7 (b8) b0 b7 b0
UART0 transmit buffer register [Address 03A316, 03A216] U0TB Setting dummy data
Start reception
Checking completion of reception
b7 b0
UART0 transmit/receive control register 1 [Address 03A516] U0C1 Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register
Checking error
(b15) b7 (b8) b0 b7 b0
UART0 receive buffer register [Address 03A716, 03A616]U0RB Receive data Overrun error flag 0 : No overrun error 1 : Overrun error found
Processing after reading out reception data
Figure 2.5.13. Set-up procedure of reception in clock-synchronous serial I/O mode (2)
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Clock-Synchronous Serial I/O
2.5.5 Precautions for Serial I/O (in clock-synchronous serial I/O)
Transmission (1) With an external clock selected, perform the following set-up procedure with the CLK0 pin input level = “H” if the CLK polarity select bit = “0” or with the CLK0 pin input level = “L” if the CLK polarity select bit = “1”: 1. Set the transmit enable bit (to “1”) 2. Write transmission data to the UART0 transmit buffer register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock-Synchronous Serial I/O
Reception (1) In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings for transmission even when using the device only for reception. Dummy data is output to the outside from the TxD0 pin (transmission pin) when receiving data. (2) With the internal clock selected, setting the transmit enable bit to “1” (transmission-enabled status) and setting dummy data in the UART0 transmission buffer register generates a shift clock. With the external clock selected, a shift clock is generated when the transmit enable bit is set to “1”, dummy data is set in the UART0 transmit buffer register, and the external clock is input to the CLK0 pin. (3) In receiving data in succession, an overrun error occurs when the next reception data is made ready in the UART0 receive register with the receive complete flag set to “1” (before the content of the UART0 receive buffer register is read), and overrun error flag is set to “1”. In this instance, the next data is written to the UART0 receive buffer register, so handle with this problem by writing programs on transmission side and reception side so that the previous data is transmitted again. If an overrun error occurs, the UART0 receive interrupt request bit does not go to “1”. (4) To receive data in succession, set dummy data in the lower-order byte of the UART0 transmit buffer register every time reception is made. (5) With an external clock selected, perform the following set-up procedure with the CLK0 pin input level = “H” if the CLK polarity select bit = “0” or with the CLK0 pin input level = “L” if the CLK polarity select bit = “1”: 1. Set receive enable bit (to “1”) 2. Set transmit enable bit (to “1”) 3. Write dummy data to the UART0 transmit buffer register
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UART 2.6 Clock-Asynchronous Serial I/O (UART) 2.6.1 Overview
UART handles communications by means of character-by-character synchronization. The transmission side and the reception side are independent of each other, so full-duplex communication is possible. The following is an overview of the clock-asynchronous serial I/O. (1) Transmission/reception format Figure 2.6.1 shows the transmission/reception format, and Table 2.6.1 shows the names and functions of transmission data.
Transfer data length : 7 bits
1ST – 7DATA 1ST – 7DATA 1ST – 7DATA – 1PAR – 1ST – 7DATA – 1PAR – 1ST – 8DATA 1ST – 8DATA 1ST – 8DATA – 1PAR – 1ST – 8DATA – 1PAR – 1ST – 9DATA 1ST – 9DATA 1ST – 9DATA – 1PAR – 1ST – 9DATA – 1PAR – ST DATA PAR SP
1SP 2SP 1SP 2SP 1SP 2SP 1SP 2SP 1SP 2SP 1SP 2SP
Transfer data length : 8 bits
Transfer data length : 9 bits
: Start bit : Character bit (Transfer data) : Parity bit : Stop bit
Figure 2.6.1. Transmission/reception format
Table 2.6.1. Transmission data names and functions
Name ST (start bit) DATA (character bits) PAR (parity bit)
Function A 1-bit “L” signal to be added immediately before character bits. This bit signals the start of data transmission. Transmission data set in the UARTi transmit buffer register. A signal to be added immediately after character bits so as to increase data reliability. The level of this signal so varies that the total number of 1's in character bits and this bit always becomes even or odd depending on which parity is chosen, even or odd. Either 1-bit or 2-bit “H” signal to be added immediately after character bits (after the parity bit if parity is checked). This / they signals the end of data transmission.
SP (stop bit)
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UART
(2) Transfer rate The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the transfer rate. The count source for the transfer rate register can be selected from f1, f8, f32, and the input from the CLK pin. Clocks f1, f8, f32 are derived by dividing the CPU’s main clock by 1, 8, and 32 respectively. Table 2.6.2. Example of baud rate setting
Baud rate (bps) 600 1200 2400 4800 9600 14400 19200 28800 31250 BRG's count source f8 f8 f8 f1 f1 f1 f1 f1 f1 System clock : 10MHz BRG's set value : n 129 (8116) 64 (4016) 32 (2016) 129 (8116) 64 (4016) 42 (2A16) 32 (2016) 21 (1516) 19 (1316) Actual time (bps) 600 1201 2367 4807 9615 14534 18939 28409 31250 System clock : 7.3728MHz BRG's set value : n 95 (5F16) 47 (2F16) 23 (1716) 95 (5F16) 47 (2F16) 31 (1F16) 23 (1716) 15 (F16) Actual time (bps) 600 1200 2400 4800 9600 14400 19200 28800
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UART
(3) An error detection In clock-asynchronous serial I/O mode, detect errors are shown in Table 2.6.3. Table 2.6.3. Error detection
Type of error Overrun error Description • This error occurs when the next data lines up before the content of the UARTi receive buffer register is read. • The next data is written to the UARTi receive buffer register. • The UARTi receive interrupt request bit does not change. • This error occurs when the stop bit falls short of the set number of stop bits. • With parity enabled, this error occurs when the total number of 1's in character bits and the parity bit is different from the specified number. • This flag turns on when any error (overrun, framing, or parity) is detected. When the flag turns on How to clear the flag • Set the receive enable bit to “0”.
Framing error
Parity error
The error is detected • Set the receive enable bit to when data is “0”. transferred from the • Read the lower-order byte of UARTi receive register the UARTi receive buffer to the UARTi receive register. buffer register.
Error-sum flag
• When all error (overrun, framing, and parity) are removed, the flag is cleared.
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UART
(4) Functions selection In operating UART, the following functions can be used: (a) Sleep mode Sleep mode is a mode in which data is transferred to a particular microcomputer among those connected by use of clock-asynchronous serial I/O devices. The following are examples in which functions (a) to (e) are chosen: • Transmission WITHOUT: other functions ................................................................................. P276 • Reception WITHOUT: other functions ...................................................................................... P280 (5) Input/output to the serial I/O and the direction register To input an external signal to the serial I/O, set the direction register of the relevant port to input. To output a signal from the serial I/O, set the direction register of the relevant port to output. (6) Pins related to the serial I/O • CLK0 pins :Input pins for the transfer clock :Input pins for data • RxD0, RxD1 pins • TxD0, TxD1 pins :Output pins for data
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UART
(8) Registers related to the serial I/O Figure 2.6.2 shows the memory map of serial I/O-related registers, and Figures 2.6.3 to 2.6.7 show UARTi-related registers.
005116 005216 005316 005416 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016
UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control regster(S1TIC) UART1 receive interrupt control register(S1RIC) UART0 transmit/receive mode register (U0MR) UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON)
Figure 2.6.2. Memory map of UARTi-related registers
272
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART
UARTi transmit buffer register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB
Address 03A316, 03A216 03AB16, 03AA16
When reset Indeterminate Indeterminate
Function
RW
Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note : Use MOV instruction to write to this register.
UARTi receive buffer register
(b15) b7 (b8) b0 b7 b0
Symbol U0RB U1RB
Address 03A716, 03A616 03AF16, 03AE16
When reset Indeterminate Indeterminate
Bit symbol
Bit name
Function (During clock synchronous serial I/O mode) Receive data
Function (During UART mode) Receive data
RW
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. OER FER PER SUM Overrun error flag (Note) Framing error flag (Note) Parity error flag (Note) Error sum flag (Note) 0 : No overrun error 1 : Overrun error found Invalid Invalid Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found
Note: Bits 15 through 12 are set to “0” when the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A616, and 03AE16) is read out.
UARTi bit rate generator (Note 1, 2)
b7 b0
Symbol U0BRG U1BRG
Address 03A116 03A916
When reset Indeterminate Indeterminate
Function
Values that can be set 0016 to FF16
RW
Assuming that set value = n, BRGi divides the count source by n + 1
Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register.
Figure 2.6.3. UARTi-related registers (1)
273
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol SMD0 SMD1 SMD2
Bit name Serial I/O mode select bit (Note 1)
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited 0 : Internal clock (Note 3) 1 : External clock (Note 4) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
CKDIR Internal/external clock select bit (Note 2) STPS PRY Stop bit length select bit
0 : Internal clock (Note 3) 1 : External clock (Note 4) Invalid
Odd/even parity select bit Invalid
PRYE SLEP
Parity enable bit Sleep select bit
Invalid Must always be “0”
Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: UART1 can use only internal clock. Must set this bit to “1”. Note 3: Set the corresponding port direction register to “1” (output mode). Note 4: Set the corresponding port direction register to “0” (input mode).
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol UiC0(i=0,1)
Bit symbol CLK0 CLK1
Set this bit to “0”.
Address 03A416, 03AC16
When reset 0816
Function (During UART mode)
b1 b0
Bit name BRG count source select bit
Function (Note) (During clock synchronous serial I/O mode)
b1 b0
RW
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fc is selected
TXEPT
Transmit register empty flag
0 : Data present in transmit 0 : Data present in transmit register register (during transmission) (during transmission) 1 : No data present in transmit 1 : No data present in transmit register (transmission register (transmission completed) completed)
Set this bit to “1”.
NCH
Data output select bit
0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output
CKPOL
CLK polarity select bit
Must always be “0”
UFORM Transfer format select bit 0 : LSB first 1 : MSB first Note: UART1 cannot be used in clock synchronous serial I/O.
Must always be “0”
Figure 2.6.4. UARTi-related registers (2)
274
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC1(i=0,1)
Address 03A516,03AD16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit Transmit buffer empty flag
Function (Note 1) (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
RW
RE RI
Receive enable bit (Note 2) Receive complete flag
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: If you are using clock asynchronous serial I/O mode, you can enable 'receive enable bit' when RxD port input is “H”. If RxD port input is “L” and you have enabled 'receive enable bit' , then receive operation starts immediately.
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UCON
Address 03B016
When reset XX0000002
Bit symbol
U0IRS
Bit name
UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit
Function (During clock synchronous serial I/O mode)
0 : Transmit buffer empty
(Tl = 1)
Function (During UART mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1)
RW
1 : Transmission completed
(TXEPT = 1)
U1IRS
Set this bit to “0”.
U0RRM UART0 continuous receive mode enable bit
0 : Continuous receive mode disabled 1 : Continuous receive mode enable
Must always be “0”
Set this bit to “0”. CLKMD0 CLK/CLKS select bit 0 Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode
(CLK output is CLK0 only)
Must always be “0”
CLKMD1 CLK/CLKS select bit 1 (Note 2)
Must always be “0”
1 : Transfer clock output from multiple pins function selected
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: When using multiple pins to output the transfer clock, the following requirements must be met: • UART0 internal/external clock select bit (bit 3 at address 03A016) = “0”.
Figure 2.6.5. UARTi-related registers (3)
275
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART 2.6.2 Operation of Serial I/O (transmission in UART mode)
In transmitting data in UART mode, choose functions from those listed in Table 2.6.4. Operations of the circled items are described below. Figure 2.6.6 shows the operation timing, and Figures 2.6.7 and 2.6.8 show the set-up procedures.
Table 2.6.4. Choosed functions
Item Transfer clock source Transmission interrupt factor Sleep mode O Internal clock (f1 / f8 / f32 / fC) External clock (CLK0 pin) (Note) Transmission buffer empty O O Transmission complete Sleep mode off Sleep mode selected
Note: UART1 cannot be selected external clock.
Set-up
Operation (1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit buffer register readies the data transmissible status. (2) Transmission data held in the UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the first bit (the start bit) of the transmission data is transmitted from the TxDi pin. Then, data is transmitted, bit by bit, in sequence: LSB, ····, MSB, parity bit, and stop bit(s). (3) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which indicates that transmission is completed. At this time, the UARTi transmit interrupt request bit goes to “1”. The transfer clock stops at “H” level. (4) If the transmission condition of the next data is ready when transmission is completed, a start bit is generated following to stop bit(s), and the next data is transmitted.
276
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART
Example of wiring
Microcomputer
Receiver side IC
TXDi
R XD
Example of operation
Tc Transfer clock (1) Transmission enabled (2) Start transmission Transmit enable bit (TE) “1” “0” Data is set in UARTi transmit buffer register (3) Confirme stop bit (4) Start transmission
Transmit buffer “1” empty flag (Tl) “0” Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi Transmit register empty flag (TXEPT) “1” “0” Parity Stop bit bit
P SP
Stopped pulsing because transfer enable bit = “0”
P SP ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1 D2 D3 D4 D5 D6 D7
Transmit “1” interrupt request “0” bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32, fC) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
Figure 2.6.6. Operation timing of transmission in UART mode
277
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART
Setting UARTi transmit/receive mode register (i=0, 1)
b7 b0
0
1
00
0
1
0
1
UART0 transmit/receive mode register U0MR [Address 03A016] UART1 transmit/receive mode register U1MR [Address 03A816] Serial I/O mode select bit
b2 b1 b0
1 0 1 : Transfer data 8 bits long
Internal/external clock select bit 0 : Internal clock
Stop bit length select bit 0 : One stop bit
Odd/even parity select bit (Valid when bit 6 = “1”) 0 : Odd parity Parity enable bit 1 : Parity enabled Sleep select bit 0 : Invalid
Setting UARTi transmit/receive control register 0 (i = 0, 1)
b7 b0
00
1
0
UART0 transmit/receive control register 0 U0C0 [Address 03A416] UART1 transmit/receive control register 0 U1C0 [Address 03AC16]
BRG count source select bit
b1 b0
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : fC is selected Must be “0” in UART mode Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed)
Must be “1” in UART mode
Data output select bit (Note) 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output
Must be “0” in UART mode
Must be “0” in UART mode
Note: Set the corresponding port direction register to “1” (output mode).
Setting UART transmit/receive control register 2
b7 b0
0
0
UART transmit/receive control register 2 UCON [Address 03B016]
UART0 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1)
UART1 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) Invalid in UART mode Must be “0” in UART mode Invalid in UART mode
Must be “0” in UART mode
Continued to the next page
Figure 2.6.7. Set-up procedure of transmission in UART mode (1)
278
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART
Continued from the previous page
Setting UARTi bit rate generator (i = 0,1)
b7 b0
UARTi bit rate generator (i = 0, 1) [Address 03A116, 03A916] UiBRG (i = 0, 1) Can be set to 0016 to FF16 (Note)
Note: Write to UARTi bit rate generator when transmission/reception is halted.
Transmission enabled
b7 b0
UART0 transmit/receive control register 1 U0C1 [Address 03A516] 1 UART1 transmit/receive control register 1 U1C1 [Address 03AD16] Transmit enable bit 1 : Transmission enabled
Writing transmit data
(b15) b7 (b8) b0 b7 b0
UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data
Start transmission
Checking the status of UARTi transmit buffer register (i = 0, 1)
b7 b0
UART0 transmit/receive control register 1 U0C1 [Address 03A516] UART1 transmit/receive control register 1 U1C1 [Address 03AD16] Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled)
Writing next transmit data
(b15) b7 (b8) b0 b7 b0
UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data
Transmission is complete
Figure 2.6.8. Set-up procedure of transmission in UART mode (2)
279
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART 2.6.3 Operation of Serial I/O (reception in UART mode)
In receiving data in UART mode, choose functions from those listed in Table 2.6.5. Operations of the circled items are described below. Figure 2.6.9 shows the operation timing, and Figures 2.6.10 and 2.6.11 show the set-up procedures. Table 2.6.5. Choosed functions
Item Transfer clock source Sleep mode Internal clock (f1 / f8 / f32 / fC) O O External clock (CLK0 pin) (Note) Sleep mode off Sleep mode selected Note: UART1 cannot be selected external clock. Set-up
Operation (1) Setting the receive enable bit to “1” readies data-receivable status. (2) When the first bit (the start bit) of reception data is received from the RxDi pin. Then, data is received, bit by bit, in sequence: LSB, ····, MSB, and stop bit(s). (3) When the stop bit(s) is (are) received, the content of the UARTi receive register is transmitted to the UARTi receive buffer register. At this time, the receive complete flag goes to “1” to indicate that the reception is completed, the UARTi receive interrupt request bit goes to “1”. (4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register is read.
280
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART
Example of wiring
Microcomputer
CLK0 RXD0
Transmitter side IC
CLK TXD
Example of operation
(4) Data is read (1) Reception enabled (2) Start reception BRG0's count source Receive enable bit RxD0
“1” “0”
(3) Receiving is completed
Start bit Sampled “L”
D0
D1
D7
Stop bit
Receive data taken in Transfer clock Reception started when transfer clock is generated by falling edge of start bit Transferred from UART0 receive register to UART0 receive buffer register
Receive complete flag
“1” “0”
Receive interrupt “1” request bit “0”
Read to UART0 receive buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software Timing of transfer data 8 bits long applies to the following settings : •Transfer data length is 8 bits. •Parity is disabled. •One stop bit
Figure 2.6.9. Operation timing of reception in UART mode
281
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART
Setting UART0 transmit/receive mode register
b7 b0
0
0
0
1
1
0
1
UART0 transmit/receive mode register U0MR [Address 03A016] Serial I/O mode select bit
b2 b1 b0
1 0 1 : Transfer data 8 bits long Internal/external clock select bit 1 : External clock (Note) Stop bit length select bit 0 : One stop bit Valid when bit 6 = “1” Parity enable bit 0 : Parity diabled Sleep select bit 0 : Sleep mode diabled
Note: UATRT1 cannot be selected external clock.
Setting UART0 transmit/receive control register 0
b7 b0
00
1
0
UART0 transmit/receive control register 0 U0C0 [Address 03A416] BRG count source select bit Invalid when external clock is selected Must be “0” in UART mode Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) Must be “1” in UART mode Data output select bit 0 : TxD0 pin is CMOS output 1 : TxD0 pin is N-channel open-drain output Must be “0” in UART mode Must be “0” in UART mode
Setting UART transmit/receive control register 2
b7 b0
0
0
UART transmit/receive control register 2 UCON [Address 03B016] Invalid in UART mode Must be “0” in UART mode Invalid in UART mode Must be “0” in UART mode
Continued to the next page
Figure 2.6.10. Set-up procedure of reception in UART mode (1)
282
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART
Continued from the previous page
Setting UART0 bit rate generator
b7 b0
UART0 bit rate generator [Address 03A116, 03A916] U0BRG Can be set to 0016 to FF16 (Note 1) Note 1: Write to UARTi bit rate generator when transmission/reception is halted.
Reception enabled
b7 b0
1
UART0 transmit/receive control register 1 U0C1 [Address 03A516] UART1 transmit/receive control register 1 U1C1 [Address 03AD16] Receive enable bit 1 : Reception enabled
Note 2: Set the corresponding port direction register to “0” (input mode).
Start reception
Checking completion of reception
b7 b0
UART0 transmit/receive control register 1 U0C1 [Address 03A516] Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register
Checking error
(b15) b7 (b8) b0 b7 b0
UART0 receive buffer register [Address 03A716, 03A616]U0RB Receive data Overrun error flag 0 : No overrun error 1 : Overrun error found Framing error flag 0 : No framing error 1 : Framing error found Parity error flag 0 : No parity error 1 : Parity error found Error sum flag 0 : No error 1 : Error found
Processing after reading out reception data
Figure 2.6.11. Set-up procedure of reception in UART mode (2)
283
Mitsubishi microcomputers
M30201 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7 A-D Converter 2.7.1 Overview
The A-D converter used in the M16C/60 group operates on a successive conversion basis. The following is an overview of the A-D converter. (1) Mode The A-D converter operates in one of five modes: (a) One-shot mode Carries out A-D conversion on input level of one specified pin only once. (b) Repetition mode Repeatedly carries out A-D conversion on input level of one specified pin. (c) Single sweep mode Carries out A-D conversion on input level of two or more specified pins only once. (d) Repeated sweep mode 0 Repeatedly carries out A-D conversion on input level of two or more pins. (e) Repeated sweep mode 1 Repeatedly carries out A-D conversion on input level of two or more pins. This mode is different from the repeated sweep mode 0 in that weights can be assigned to specifing pins control the number of conversion times. (2) Operation clock The operation clock in 5 V operation can be selected from the following: fAD, divide-by-2 fAD, and divide-by-4 fAD. In 3 V operation, the selection is divide-by-2 fAD or divide-by-4. The fAD frequency is equal to that of the CPU’s main clock. (3) Conversion time Number of conversion for A-D convertor varies depending on resolution as given. Table 2.7.1 shows relation between the A-D converter operation clock and conversion time. Sample & Hold function selected: 33 cycles for 10-bit resolution, or 28 cycles for 8-bit resolution No Sample & Hold function: 59 cycles for 10-bit resolution, or 49 cycles for 8-bit resolution Table 2.7.1. Conversion time every operation clock Frequency selection bit 1 Frequency selection bit 0 A-D converter's operation clock Min. conversion cycles (Note 1) Min. conversion time (Note 2) 8-bit mode 10-bit mode 8-bit mode 10-bit mode 11.2µs 13.2µs φAD = 0 fAD 4 28 X φAD 33 X φAD 5.6µs 6.6µs 2.8µs 3.3µs φAD = 0 1 fAD 2 1 Invalid φAD = fAD
Note 1: The number of conversion cycles per one analog input pin. Note 2: The conversion time per one analog input pin (when fAD = f(XIN) = 10 MHz)
284
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(4) Functions selection (a) Sample & Hold function Sample & Hold function samples input voltage when A-D conversion starts and carries out A-D conversion on the voltage sampled. When A-D conversion starts, input voltage is sampled for 3 cycles of the operation clock. When the Sample & Hold function is selected, set the operation clock for A-D conversion to 1 MHz or higher. (b) 8-bit A-D to 10-bit A-D switching function Either 8-bit resolution or 10-bit resolution can be selected. When 8-bit resolution is selected, the 8 higher-order bits of the 10-bit A-D are subjected to A-D conversion. The equations for 10-bit resolution and 8-bit resolution are given below: 10-bit resolution (Vref X n / 210 ) – (Vref X 0.5 / 210 ) (n = 1 to 1023), 0 (n = 0) 8-bit resolution (Vref X n / 28 ) – (Vref X 0.5 / 210 ) (n = 1 to 256), 0 (n = 0)
(c) Analog input group function The analog input pins can be switched between the port P6 group (AN0 to AN4) and the port P5 group (AN50 to AN54). (d) Connecting or cutting Vref Cutting Vref allows decrease of the current flowing into the A-D converter. To decrease the microcomputer's power consumption, cut Vref. To carry out A-D conversion, start A-D conversion 1 µs or longer after connecting Vref. The following are exsamples in which functions (a) through (d) are selected: • One-shot mode ......................................................................................................................... P290 • Repeat mode ............................................................................................................................ P292 • Single sweep mode .................................................................................................................. P294 • Repeated sweep mode 0 .......................................................................................................... P296 • Repeated sweep mode 1 .......................................................................................................... P298 (5) Input to A-D converter and direction register To use the A-D converter, set the direction register of the relevant port to input. (6) Pins related to A-D converter (a) AN0 pin through AN7 pin (b) AN50 pin through AN57 pin (c) AVcc pin (d) VREF pin (e) AVss pin
Input pins of the A-D converter (Port P6 group ) Input pins of the A-D converter (Port P5 group ) Power source pin of the analog section Input pin of reference voltage GND pin of the analog section
285
Mitsubishi microcomputers
M30201 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(7) A-D converter and related registers Figure 2.7.1 shows the memory map of A-D converter-related registers, and Figures 2.7.2 through 2.7.4 show A-D converter-related registers.
004E16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D416 03D516 03D616 03D716
A-D conversion interrupt control register (ADIC)
A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7)
A-D control register 2 (ADCON2) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1)
Figure 2.7.1. Memory map of A-D converter-related registers
286
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol ADCON0
Address 03D616
When reset 00000XXX2
Bit symbol
CH0
Bit name
b2 b1 b0
Function
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
RW
Analog input pin select bit
CH1
CH2 MD0 MD1 A-D operation mode select bit 0
(Note 2, 3)
0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1
(Note 2)
Set this bit to “0”.
ADST CKS0 A-D conversion start flag Frequency select bit 0 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Figure 2.7.2. A-D converter-related registers (1)
287
Mitsubishi microcomputers
M30201 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
gg p , gpp g Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
A-D sweep pin select bit
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
(Note 2, 3)
0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 0 : Vref not connected 1 : Vref connected
BITS CKS1 VCUT
Set this bit to “0”.
ADGSEL0 A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4. Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate. If port P5 group is selected, do not select 8 pins sweep mode.
Figure 2.7.3. A-D converter-related registers (2)
288
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
When reset
XXXX00002
000
Bit symbol
SMP Reserved bit
Bit name
A-D conversion method select bit
Function
0 : Without sample and hold 1 : With sample and hold Always set to “0”
RW
Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D register i
(b15) b7 (b8) b0 b7
Symbol
ADi(i=0 to 7)
Address When reset 03C016 to 03CF16 Indeterminate
b0
Function
Eight low-order bits of A-D conversion result • During 10-bit mode Two high-order bits of A-D conversion result • During 8-bit mode The value, if read, turns out to be indeterminate. Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
RW
Figure 2.7.4. A-D converter-related registers (3)
289
Mitsubishi microcomputers
M30201 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7.2 Operation of A-D converter (one-shot mode)
In one-shot mode, choose functions from those listed in Table 2.7.2. Operations of the circled items are described below. Figure 2.7.5 shows the operation timing, and Figure 2.7.6 shows the set-up procedure. Table 2.7.2. Choosed functions
Item Operation clock φAD Resolution Analog input pin Sample & Hold O O O O Divided-by-4 fAD / divided-by-2 fAD / fAD 8-bit / 10-bit One of AN0 pin to AN7 pin (Note) Not activated Activated Set-up
Note : When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54.
Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to begin operating. (2) After A-D conversion is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register i. At this time, the A-D conversion interrupt request bit goes to “1”. Also, the A-D conversion start flag goes to “0”, and the A-D converter stops operating.
(1) Start A-D conversion
8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles
(2) A-D conversion is complete
φAD
Set to “1” by software A-D conversion start flag
“1” “0”
A-D register i
Result
A-D conversion interrupt request
“1” “0”
Cleared to “0” when interrupt request is accepted, or cleared by software Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.7.5. Operation timing of one-shot mode
290
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
Selecting Sample and hold
b7 b0
0
0
0
1
A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Must be fixed to “0”
Setting A-D control register 0 and A-D control register 1
b7 b0 b7 b0
0
0
0
0
A-D control register 0 [Address 03D616] ADCON0 Analog input pin select bit (Note 2)
b2 b1 b0
0
1
0
A-D control register 1 [Address 03D716] ADCON1 Invalid in one-shot mode A-D operation mode select bit 1 (Note 1) 0 (Must always be “0” in one-shot mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected Must be fixed to “0”
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected One-shot mode is selected (Note 1) Must be fixed to “0” A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected
A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note 1: Rewrite to analog input pin select bit after changing A-D operation mode. Note 2: Set the corresponding port direction register to “0” (input mode). When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54.
Setting A-D conversion start flag
b7 b0
1
A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started
Start A-D conversion Stop A-D conversion
Reading conversion result
(b15) b7 (b8) b0 b7 b0
A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7
[Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16]
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate
Figure 2.7.6. Set-up procedure of one-shot mode
291
Mitsubishi microcomputers
M30201 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7.3 Operation of A-D Converter (in repeat mode)
In repeat mode, choose functions from those listed in Table 2.7.3. Operations of the circled items are described below. Figure 2.7.7 shows timing chart, and Figure 2.7.8 shows the set-up procedure. Table 2.7.3. Choosed functions
Item Operation clock φAD Resolution Analog input pin Sample & Hold O O O O Divided-by-4 fAD / divided-by-2 fAD / fAD 8-bit / 10-bit One of AN0 pin to AN7 pin (Note) Not activated Activated Set-up
Note : When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54.
Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start operating. (2) After the first conversion is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register i. The A-D conversion interrupt request bit does not go to “1”. (3) The A-D converter continues operating until the A-D conversion start flag is set to “0” by software. The conversion result is transmitted to A-D register i every time a conversion is completed.
(1) Start A-D conversion
8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles
(2) Conversion result is transferred to the A-D register (3) A-D conversion 8-bit resolution : 28 φAD cycles is complete 10-bit resolution : 33 φAD cycles
φAD Set to “1” by software A-D conversion “1” start flag “0” Cleared to “0” by software
A-D register i
Result
Result
A-D conversion
Stop
Convert
Convert
Convert
Stop
Note: When φAD frequency is less than 1MHz, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.7.7. Operation timing of repeat mode
292
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
Selecting Sample and hold
b7 b0
0
0
0
1
A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Must be fixed to “0”
Setting A-D control register 0 and A-D control register 1
b7 b0 b7 b0
0
0
0
1
A-D control register 0 [Address 03D616] ADCON0 Analog input pin select bit (Note 2)
b2 b1 b0
0
1
0
A-D control register 1 [Address 03D716] ADCON1 Invalid in repeat mode A-D operation mode select bit 1 (Note 1) 0 (Must always be “0” in repeat mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected Must be fixed to “0”
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected Repeat mode is selected (Note 1) Must be fixed to “0” A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected
A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note 1: Rewrite to analog input pin select bit after changing A-D operation mode. Note 2: Set the corresponding port direction register to “0” (input mode). When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54.
Setting A-D conversion start flag
b7 b0
1
A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started
Start A-D conversion
Reading conversion result
(b15) b7 (b8) b0 b7 b0
A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7
[Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16]
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate
Setting A-D conversion start flag
b7 b0
0
A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled
Stop A-D conversion
Figure 2.7.8. Set-up procedure of repeat mode
293
Mitsubishi microcomputers
M30201 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7.4 Operation of A-D Converter (in single sweep mode)
In single sweep mode, choose functions from those listed in Table 2.7.4. Operations of the circled items are described below. Figure 2.7.9 shows timing chart, and Figure 2.7.10 shows the set-up procedure. Table 2.7.4. Choosed functions
Item Operation clock φAD Resolution Analog input pin Sample & Hold O O O O Divided-by-4 fAD / divided-by-2 fAD / fAD 8-bit / 10-bit AN0 and AN1 (2 pins) / AN0 to AN3 (4 pins) / AN0 to AN5 (6 pins) / AN0 to AN7 (8 pins) (Note) Not activated Activated Set-up
Note : When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54.
Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0/AN50 pin. (2) After the A-D conversion of voltage input to the AN0/AN50 pin is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register 0. The A-D converter converts all analog input pins selected by the user. The conversion result is transmitted to A-D register i corresponding to each pin, every time conversion on one pin is completed. (3) When the A-D conversion on all the analog input pins selected is completed, the A-D conversion interrupt request bit goes to “1”. At this time, the A-D conversion start flag goes to “0”. The A-D converter stops operating.
(2) After A-D conversion on AN0/AN50 pin is complete, A-D converter begins converting all pins selected 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles
(1) Start A-D conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles
(3) A-D conversion is complete
φAD Set to “1” by software A-D conversion “1” start flag “0” A-D register 0 Result
A-D register 1
Result
A-D register i A-D conversion “1” interrupt request “0” bit
Result
Cleared to “0” when interrupt request is accepted, or cleared by software Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.7.9. Operation timing of single sweep mode
294
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
Selecting Sample and hold
b7 b0
0
0
0
1
A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Must be fixed to “0”
Setting A-D control register 0 and A-D control register 1
b7 b0 b7 b0
0
0
1
0
A-D control register 0 [Address 03D616] ADCON0 Invalid in single sweep mode Single sweep mode is selected (Note 1) Must be fixed to “0” A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected
0
1
0
A-D control register 1 [Address 03D716] ADCON1 A-D sweep pin select bit (Note 2)
b1 b0
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) A-D operation mode select bit 1 (Note 1)
0 (Must always be “0” in single sweep mode)
8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected Must be fixed to “0” A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note 1: Rewrite to analog input pin select bit after changing A-D operation mode. Note 2: Set the corresponding port direction register to “0” (input mode). When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54.
Setting A-D conversion start flag
b7 b0
1
A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started
Start A-D conversion Stop A-D conversion
Reading conversion result
(b15) b7 (b8) b0 b7 b0
A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7
[Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16]
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate
Figure 2.7.10. Set-up procedure of single sweep mode
295
Mitsubishi microcomputers
M30201 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7.5 Operation of A-D Converter (in repeat sweep mode 0)
In repeat sweep 0 mode, choose functions from those listed in Table 2.7.5. Operations of the circled items are described below. Figure 2.7.11 shows timing chart, and Figure 2.7.12 shows the set-up procedure. Table 2.7.5. Choosed functions
Item Operation clock φAD Resolution Analog input pin Sample & Hold O O O O Divided-by-4 fAD / divided-by-2 fAD / fAD 8-bit / 10-bit AN0 and AN1 (2 pins) / AN0 to AN3 (4 pins) / AN0 to AN5 (6 pins) / AN0 to AN7 (8 pins) (Note) Not activated Activated Set-up
Note : When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54.
Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0/AN50 pin. (2) After the A-D conversion of voltage input to the AN0/AN50 pin is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register 0. (3) The A-D converter converts all pins selected by the user. The conversion result is transmitted to A-D register i corresponding to each pin every time A-D conversion on the pin is completed. The A-D conversion interrupt request bit does not go to “1”. (4) The A-D converter continues operating until the A-D conversion start flag is set to “0” by software.
(1) Start A-D conversion
(2) AN1/AN51 conversion begins after AN0/AN50 conversion is complete (3) Consecutive conversion 8-bit resolution : 28 φAD cycles 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles 10-bit resolution : 33 φAD cycles
(4) A-D conversion is complete
φAD Set to “1” by software. A-D conversion start flag A-D register 0 “1” “0” Result Cleared to “0” by software
A-D register 1
Result
A-D register i
Result
Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.7.11. Operation timing of repeat sweep 0 mode
296
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
Selecting Sample and hold
b7 b0
0
0
0
1
A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Must be fixed to “0”
Setting A-D control register 0 and A-D control register 1
b7 b0 b7 b0
0
0
1
1
A-D control register 0 [Address 03D616] ADCON0 Invalid in repeat sweep mode 0 Repeat sweep mode 0 is selected (Note 1) Must be fixed to “0” A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected
0
1
0
A-D control register 1 [Address 03D716] ADCON1 A-D sweep pin select bit (Note 2)
b1 b0
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) A-D operation mode select bit 1 (Note 1)
0 (Must always be “0” in repeat sweep mode 0)
8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected Must be fixed to “0” A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note 1: Rewrite to analog input pin select bit after changing A-D operation mode. Note 2: Set the corresponding port direction register to “0” (input mode). When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54.
Setting A-D conversion start flag
b7 b0
1
A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started
Repeatedly carries out A-D conversion on pins selected through the A-D sweep pin select bit.
Start A-D conversion
Reading conversion result
(b15) b7 (b8) b0 b7 b0
A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7
[Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16]
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate
Setting A-D conversion start flag
b7 b0
0
A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled
Stop A-D conversion
Figure 2.7.12. Set-up procedure of repeat sweep 0 mode
297
Mitsubishi microcomputers
M30201 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7.6 Operation of A-D Converter (in repeat sweep mode 1)
In repeat sweep 1 mode, choose functions from those listed in Table 2.7.6. Operations of the circled items are described below. Figure 2.7.13 shows ANi pin's sweep sequence, Figure 2.7.14 shows timing chart, and Figure 2.7.15 shows the set-up procedure.
Table 2.7.6. Choosed functions
Item Operation clock φAD Resolution Analog input pin Sample & Hold O O O Divided-by-4 fAD / divided-by-2 fAD / fAD 8-bit / 10-bit AN0 (1 pins) / AN0 to AN1 (2 pins) / AN0 to AN2 (3 pins) / AN0 to AN3 (4 pins) (Note) Not activated Set-up
O Activated Note : When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54.
Operation
(1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0/AN50 pin. (2) After the A-D conversion on voltage input to the AN0/AN50 pin is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register 0. (3) Every time the A-D converter carries out A-D conversion on a selected analog input pin, the A-D converter carries out A-D conversion on only one unselected pin, and then the A-D converter carries out A-D conversion from the AN0 pin again. (See Figure 2.7.13.) The conversion result is transmitted to A-D register i every time conversion on a pin is completed. The A-D conversion interrupt request bit does not go to “1”. (4) The A-D converter continues operating until software goes the A-D conversion start flag to “0”.
When AN0 is selected When AN0, AN1 are selected When AN0 to AN2 are selected When AN0 to AN3 are selected
Converted analog input pin
Converted analog input pin
Converted analog input pin
0 1
0
0
0
0
0
0
0 1
0
2 3 4 5 6 7
2
0 . . .
0 1 2
0 1
0 1
0 1
0 1
0 1
0 1 2
0 . . .
0 1 2 3
0 1 2
0 1 2
0 1 2
0 1 2
0 1 2 3
0 . . .
Converted analog input pin
Time
Time
Time
Time
0 1 2 3 4
0 1 2 3
0 1 2 3
0 1 2 3
0 1 2 3 4
0 . . .
3 4 5 6 7
4 5 6 7
5 6 7
Figure 2.7.13. ANi pin's sweep sequence in repeat sweep mode
(2) Conversion result is transfered to A-D conversion register 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles
(1) Start AN0 /AN50 pin conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles φAD
(3) Consecutive conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles 8-bit resolution : 28 AD cycles 10-bit resolution : 33 AD cycles (4) A-D conversion is complete
Set to “1” by software A-D conversion start flag A-D register 0 A-D register 1 A-D register 2 “1” “0” Result Result
Cleared to “0” by software
Result
Result
Note: When φAD frequency is less than 1MHz, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.7.14. Operation timing of repeat sweep 1 mode
298
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
Selecting Sample and hold
b7 b0
0
0
0
1
A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Must be fixed to “0”
Setting A-D control register 0 and A-D control register 1
b7 b0 b7 b0
0
0
1
1
A-D control register 0 [Address 03D616] ADCON0 Invalid in repeat sweep mode 1 Repeat sweep mode 1 is selected (Note 1) Must be fixed to “0” A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected
0
1
1
A-D control register 1 [Address 03D716] ADCON1 A-D sweep pin select bit (Note 2)
b1 b0
0 0 : AN0 (1 pins) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) A-D operation mode select bit 1 (Note 1)
1 (Must always be “1” in repeat sweep mode 1)
8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected Must be fixed to “0” A-D input group select bit 0 : Port P6 group is selected 1 : Port P5 group is selected
Note 1: Rewrite to analog input pin select bit after changing A-D operation mode. Note 2: Set the corresponding port direction register to “0” (input mode). When the port P5 group is selected, analog input pins are changed from AN0 to AN4 to pins AN50 to AN54.
Setting A-D conversion start flag
b7 b0
1
A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started
Converts non-selected pin after converting pins selected through the A-D sweep pin select bit.
Start A-D conversion
Reading conversion result
(b15) b7 (b8) b0 b7 b0
A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7
[Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16]
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate
Setting A-D conversion start flag
b7 b0
0
A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled
Stop A-D conversion
Figure 2.7.15. Set-up procedure of repeat sweep 1 mode
299
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
2.7. 7 Precautions for A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from 0 to 1, start A-D conversion after an elapse of 1 µs or longer. (2) To reduce conversion error due to noise, connect a voltage to the AVcc pin and to the Vref pin from an independent source. It is recommended to connect a capacitor between the AVss pin and the AVcc pin, between the AVss pin and the Vref pin, and between the AVss pin and the analog input pin (ANi/AN5i). Figure 2.7.16 shows the an example of connecting the capacitors to these pins.
Microcomputer
VCC AVCC
VREF C1 AVSS C3 ANi Note 1: C 10.47 µF, C 20.47 µF, C 3100 pF (for reference) Note 2: Use thick and shortest possible wiring to connect capacitors. C2
Figure 2.7.16. Use of capacitors to reduce noice
(3) Set the direction register of the following ports to input: the port corresponding to a pin to be used as an analog input pin and external trigger input pin. (4) If using the A-D converter with Vcc = 2.7V to 4.0 V: Use without fAD (no frequency division) for AD. Select without the Sample & Hold feature. Select 8-bit mode. (5) Rewrite to analog input pin after changing A-D operation mode. The two cannot be set at the same time. (6) When using the one-shot or single sweep mode Confirm that A-D conversion is complete before reading the A-D register. (Note: When A-D conversion interrupt request bit is set, it shows that A-D conversion is completed.) (7) When using the repeat mode or repeat sweep mode 0 or 1 Use the undivided main clock as the internal CPU clock.
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A-D Converter 2.7.8 Method of A-D Conversion (10-bit mode)
(1) The A-D converter compares the reference voltage (Vref) generated internally based on the contents of the successive comparison register with the analog input voltage (VIN) input from the analog input pin. Each bit of the comparison result is stored in the successive comparison register until analog-to-digital conversion (successive comparison method) is complete. If a trigger occurs, the A-D converter carries out the following: 1. Fixes bit 9 of the successive comparison register. Compares Vref with VIN: [In this instance, the contents of the successive comparison register are “10000000002” (default).] Bit 9 of the successive comparison register varies depending on the comparison result as follows. If Vref < VIN, then “1” is assigned to bit 9. If Vref > VIN, then “0” is assigned to bit 9. 2. Fixes bit 8 of the successive comparison register. Sets bit 8 of the successive comparison register to “1”, then compares Vref with VIN. Bit 8 of the successive comparison register varies depending on the comparison result as follows: If Vref < VIN, then “1” is assigned to bit 8. If Vref > VIN, then “0” is assigned to bit 8. 3. Fixes bit 7 through bit 0 of the successive comparison register. Carries out step 2 above on bit 7 through bit 0. After bit 0 is fixed, the contents of the successive comparison register (conversion result) are transmitted to A-D register i. Vref is generated based on the latest content of the successive comparison register. Table 2.7.7 shows the relationship of the successive comparison register contents and Vref. Table 2.7.8 shows how the successive comparison register and Vref vary while A-D conversion is in progress. Figure 2.7.17 shows theoretical A-D conversion characteristics.
Table 2.7.7. Relationship of the successive comparison register contents and Vref Successive approximation register : n 0 1 to1023 VREF 1024 x Vref (V) 0 n – VREF 2048
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A-D Converter
Table 2.7.8. Variation of the successive comparison register and Vref while A-D conversion is in progress (10-bit mode)
Successive approximation register
b9 A-D converter stopped b0
Vref change VREF [V] 2 VREF VREF [V] – 2048 2 VREF VREF VREF [V] n9 = 0 – ± 2 2048 4
n9 = 1
1000000000 1000000000 n9 1 0 0 0 0 0 0 0 0
1st comparison result
1st comparison 2nd comparison 3rd comparison
+
n9 n8 1 0 0 0 0 0 0 0
2nd comparison result
VREF ± VREF ± VREF – VREF [V] n8 = 0 2 4 8 2048
VREF 4 – VREF 4 + n8 = 1 –
VREF 8 VREF 8
10th comparison Conversion complete
n9 n8 n7 n6 n5 n4 n3 n2 n1 0 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0
This data transfers to the bit 0 to bit 9 of A-D register.
VREF VREF VREF VREF VREF [V] ± ...... ± – ± ± 4 8 2 1024 2048
Result of A-D conversion Theoretical A-D conversion characteristic 3FF16 3FE16
00316 00216 00116 00016 0
VREF x 0.5 1024 VREF x 1 1024 VREF x 2 1024 VREF x 3 1024
Ideal A-D conversion characteristic
VREF x 1021 VREF x 1022 VREF x 1023 1024 1024 1024
VREF
Analog input voltage
Figure 2.7.17. Theoretical A-D conversion characteristics (10-bit mode)
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A-D Converter 2.7.9 Method of A-D Conversion (8-bit mode)
(1) In 8-bit mode, 8 higher-order bits of the 10-bit successive comparison register becomes A-D conversion result. Hence, if compared to a result obtained by using an 8-bit A-D converter, the voltage compared is different by 3 VREF/2048 (see what are underscored in Table 2.7.9), and differences in stepping points of output codes occur as shown in Figure 2.7.18.
Table 2.7.9. The comparison voltage in 8-bit mode compared to 8-bit A-D converter 8-bit mode n=0 Comparison voltage Vref n = 1 to 255 VREF 28 xn 0 – VREF 210 x 0.5 VREF 28 x 8-bit A-D converter 0 n– VREF 28 x 0.5
Optimal conversion characteristics of 8-bit A-D converter (VREF = 5.12 V)
Output code (Result of A-D conversion) 02 01 00
10
30
Analog input voltage (mV)
Optimal conversion characteristics in 8-bit mode (VREF = 5.12 V)
Output code (Result of A-D conversion)
8-bit mode 10-bit mode 09 08 07 06 05 04 03 02 01 00 (Note) 10bit-mode
02 01 00
8bit-mode
17.5
37.5
Analog input voltage (mV)
Note: Differences in stepping points of output code for analog input voltage.
Figure 2.7.18. The level conversion characteristics of 8-bit mode and 8-bit A-D converter
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A-D Converter
Table 2.7.10. Variation of the successive comparison register and Vref while A-D conversion is in progress (8-bit mode)
Successive approximation register
b9 A-D converter stopped b0
Vref change VREF [V] 2 VREF VREF [V] – 2048 2 VREF VREF VREF [V] – ± 2048 2 4
n9 = 1 n9 = 0
1000000000 1000000000 n9 1 0 0 0 0 0 0 0 0
1st comparison result
1st comparison 2nd comparison 3rd comparison
+
n9 n8 1 0 0 0 0 0 0 0
2nd comparison result
VREF VREF VREF VREF [V] – ± ± 2048 4 8 2 n8 = 0
VREF 4 VREF – 4 n8 = 1
+ –
VREF 8 VREF 8
8th comparison Conversion complete
n9 n8 n7 n6 n5 n4 n3 1 0 0 n9 n8 n7 n 6 n 5 n 4 n 3 n 2 0 0
This data transfers to bit 0 to bit 7 of A-D register.
VREF VREF VREF VREF VREF [V] ± ± ± ...... ± – 2048 2 4 8 256
Result of A-D conversion Theoretical A-D conversion characteristic of general 8-bit A-D converter FF16 FE16
0316 0216 0116 0016 0
VREF x 3 2048 VREF x 1 256 VREF x 2 256 VREF x 3 256 VREF x 4 256
Theoretical A-D conversion characteristic in the 8-bit mode
VREF x 254 256
VREF x 255 256
VREF
Analog input voltage
Figure 2.7.19. Theoretical A-D conversion characteristics (8-bit mode)
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A-D Converter 2.7.10 Absolute Accuracy and Differential Non-Linearity Error
• Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A-D conversion characteristics, and actual A-D conversion result. When measuring absolute accuracy, the voltage at the middle point of the width of analog input voltage (1-LSB width), that can meet the expectation of outputting an equal code based on the theoretical A-D conversion characteristics, is used as an analog input voltage. For example, if 10-bit resolution is used and if VREF (reference voltage) = 5.12 V, then 1-LSB width becomes 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ···· are used as analog input voltages. If analog input voltage is 25 mV, “absolute accuracy = ± 3LSB” refers to the fact that actual A-D conversion falls on a range from “00216” to ”00816” though an output code, “00516”, can be expected from the theoretical A-D conversion characteristics. Zero error and full-scale error are included in absolute accuracy. Also, all the output codes for analog input voltage between VREF and AVcc becomes “3FF16”.
Output code (result of A-D conversion)
00B16 00A16 00916 00816 00716 00616 00516 00416 00316 00216 –3LSB 00116 00016 0 5 10 15 20 25 30 35 40 45 50 55 +3LSB Theoretical A-D conversion characteristic
Analog input voltage (mV)
Figure 2.7.20. Absolute accuracy (10-bit resolution)
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A-D Converter
• Differential non-linearity error Differential non-linearity error refers to the difference between 1-LSB width based on the theoretical AD conversion characteristics (an analog input width that can meet the expectation of outputting an equal code) and an actually measured 1-LSB width (analog input voltage width that outputs an equal code). If 10-bit resolution is used and if VREF (reference voltage) = 5.12 V, “differential non-linearity error = ± 1LSB” refers to the fact that 1-LSB width actually measured falls on a range from 0 mV to 10 mV though 1-LSB width based on the theoretical A-D conversion characteristics is 5 mV (see 5.2 A-D converter's standard characteristics).
Output code (result of A-D conversion)
00916 00816 00716 00616 00516 00416 00316 00216 00116 Differential non-linear error 00016 0 5 10 15 20 25 30 35 40 45 1LSB width for theoretical A-D conversion characteristic
Analog input voltage (mV)
Figure 2.7.21. Differential non-linearity error (10-bit resolution)
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A-D Converter 2.7.11 Internal Equivalent Circuit of Analog Input
Figure 2.7.22 shows the internal equivalent circuit of analog input.
Vcc
Vcc
Parasitic diode
Vss
AVcc
ON resistor approx. 2k Ω
AN0
SW1
Wiring resistor approx. 0.2k Ω
ON resistor approx. 0.6k Ω
Analog input voltage
C = Approx. 3.0pF
AMP
ON resistor, approx. 5k Ω
Parasitic diode
SW2
VIN
Vss
i ladder-type switches (i = 10)
Sampling control signal
SW4
SW3
i ladder-type wiring resistors (i = 10)
AVss
Chopper-type amplifier
AN i
SW1
A-D successive conversion register
b2 b1 b0
A-D control register 0
Reference control signal
Vref
VREF
Resistor ladder
AVss
SW2
Comparison voltage
ON resistor approx. 0.6k Ω
ADT/A-D conversion interrupt request
Comparison reference voltage (Vref) generator
Sampling
Connect to Control signal for SW2
Comparison
SW1 conducts only on the ports selected for analog input. SW2 and SW3 are open when A-D conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left. SW4 conducts only when A-D conversion is not in progress.
Connect to
Connect to
Connect to
Control signal for SW3
Warning: Use only as a standard for designing this data. Mass production may cause some changes in device characteristics.
Figure 2.7.22. Internal equivalent circuit to analog input
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A-D Converter 2.7.12 Sensor’s Output Impedance under A-D Conversion
To carry out A-D conversion properly, charging the internal capacitor C shown in Figure 2.7.23 has to be completed within a specified period of time. With T as the specified time, time T is the time that switches SW2 and SW3 are connected to O in Figure 2.7.22. Let output impedance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of the A-D converter be X, and the A-D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). Vc is generally VC = VIN {1 – e And when t = T, VC=VIN –
T C (R0 + R)
–
t C (R0 + R)
}
X X VIN=VIN(1 – ) Y Y X Y X Y
e –
–
=
Hence, R0 = –
T =ln C (R0 +R) T –R X C • ln Y
With the model shown in Figure 2.7.29 as an example, when the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-(0.1/1024) VIN in time T. (0.1/1024) means that A-D precision drop due to insufficient capacitor charge is held to 0.1LSB at time of A-D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(XIN) = 10 MHz, T = 0.3 us in the A-D conversion mode with sample & hold. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. T = 0.3 µs, R = 7.8 kΩ, C = 3 pF, X = 0.1, and Y = 1024 . Hence, 0.3 X 10-6 R0 = – 3.0 X 10 –12 • ln 0.1 –7.8 X103 3.0 X 103
1024 Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A-D converter turns out to be approximately 3.0 kΩ. Tables 2.7.11 and 2.7.12 show output impedance values based on the LSB values.
Microprocessor's inside Sensor-equivalent circuit R0 VIN R (7.8k Ω)
C (3.0pF) VC
Figure 2.7.23 A circuit equivalent to the A-D conversion terminal
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A-D Converter
Tables 2.7.11. Relation between output impedance and precision (error) of A-D converter (10-bit mode) Reference value
f(Xin) (MHz) 10
Cycle 0.1
Sampling time 0.3 (3 x cycle, Sample & hold bit is enabled)
R 7.8
C (pF) 3.0
10
0.1
0.2 (2 x cycle, Sample & hold bit is disabled)
7.8
3.0
Resolution (LSB) 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
R0 3.0 4.5 5.3 5.9 6.4 6.8 7.2 7.5 7.8 8.1 0.4 0.9 1.3 1.7 2.0 2.2 2.4 2.6 2.8
Tables 2.7.12. Relation between output impedance and precision (error) of A-D converter (8-bit mode) Reference value
f(Xin) (MHz) 10
Cycle 0.1
Sampling time 0.3 (3 x cycle, Sample & hold bit is enabled)
R 7.8
C (pF) 3.0
10
0.1
0.2 (2 x cycle, Sample & hold bit is disabled)
7.8
3.0
Resolution (LSB) 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
R0 4.9 7.0 8.2 9.1 9.9 10.5 11.1 11.7 12.1 12.6 0.7 2.1 2.9 3.5 4.0 4.4 4.8 5.2 5.5 5.8
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Watchdog Timer 2.8 Watchdog Timer 2.8.1 Overview
The watchdog timer can detect a runaway program using its 15-bit timer prescaler. The following is an overview of the watchdog timer. (1) Watchdog timer start procedure When reset, the watchdog timer is in stopped state. Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start performing a down count. The watchdog timer, once started operating, cannot be stopped by any means other than stopping conditions. (2) Watchdog timer stop conditions The watchdog timer stops in any one of the following states: (a) Period in which the CPU is in stopped state (b) Period in which the CPU is in waiting state (3) Watchdog timer initialization The watchdog timer is initialized to 7FFF16 in the cases given below, and begins a down count. (a) When the watchdog timer writes to the watchdog timer start register while a count is in progress (b) When the watchdog timer underflows (4) Runaway detection When the watchdog timer underflows, a watchdog timer interrupt occurs. In writing a program, write to the watchdog timer start register before the watchdog timer underflows. The watchdog timer interrupt occurs regardless of the status of the interrupt enable flag (I flag). In processing a watchdog timer interrupt, set the software reset bit to “1” to reset software. (5) Watchdog timer cycle The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the prescaler selected.
Table 2.8.1. The watchdog timer cycle
CM07 0 0 CM06 0 0 CM17 0 0 CM16 0 1 BCLK 10MHz 5MHz WDC7 0 1 0 1 0 1 0 1 0 1 1 Invalid Invalid Invalid Invalid Invalid 1.25MHz 32kHz 0 1 Invalid Period Approx. 52.4ms (Note) Approx. 419.2ms (Note) Approx. 104.9ms (Note) Approx. 838.8ms (Note) Approx. 209.7ms (Note) Approx. 1.68s (Note) Approx. 838.8ms (Note) Approx. 6.71s (Note) Approx. 419.2ms (Note) Approx. 3.35s (Note) Approx. 2s (Note)
0 0
0 0
1 1
0 1
2.5MHz 0.625MHz
Note: An error due to the prescaler occurs.
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Watchdog Timer
(6) Registers related to the watchdog timer Figure 2.8.1 shows the memory map of watchdog timer-related registers, and Figure 2.8.2 shows watchdog timer-related registers.
000E16 000F16
Watchdog timer start register (WDTS) Watchdog timer control register (WDC)
Figure 2.8.1. Memory map of watchdog timer-related registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol WDC
Bit symbol
Address 000F16
Bit name
When reset 000XXXXX2
Function RW
High-order bit of watchdog timer
Reserved bit Reserved bit
WDC7
Must always be set to “0” Must always be set to “0”
Prescaler select bit
0 : Divided by 16 1 : Divided by 128
Watchdog timer start register
b7 b0
Symbol WDTS
Address 000E16
When reset Indeterminate
RW
Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written.
Figure 2.8.2. Watchdog timer-related registers
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Watchdog Timer 2.8.2 Operation of Watchdog Timer
The following is an operation of the watchdog timer. Figure 2.8.3 shows the operation timing, and Figure 2.8.4 shows the set-up procedure. Operation (1) Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start a down count. (2) With a count in progress, writing to the watchdog timer start register again initializes the watchdog timer to 7FFF16 and causes it to resume counting. (3) Either executing the WAIT instruction or going to the stopped state causes the watchdog timer to hold the count in progress and to stop counting. The watchdog timer resumes counting after returning from the execution of the WAIT instruction or from the stopped state. (4) If the watchdog timer underflows, it is initialized to 7FFF16 and continues counting. At this time, a watchdog timer interrupt occurs.
(1) Start count
(3) In stopped state, or WAIT instruction is executing, etc (2) Write operation
(4) Generate watchdog timer interrupt
7FFF16
000016 Write signal to the “H” watchdog timer start register “L”
Figure 2.8.3. Operation timing of watchdog timer
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Watchdog Timer
Setting watchdog timer control register
b7 b0
00
Watchdog timer control register [Address 000F16] WDC Reserved bit Must always be “0” Prescaler select bit 0 : Divided by 16 1 : Divided by 128
Setting watchdog timer start register
b7 b0
Watchdog timer start register [Address 000E16] WDTS The watchdog timer is initialized and starts counting with a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of the value written.
Generating watchdog timer interrupt
Software reset
b7 b0
1
Processor mode register 0 [Address 000416] PM0 Software reset bit The device is reset when this bit is set to “1”. The value of this bit is “0” when read.
Figure 2.8.4. Set-up procedure of watchdog timer
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Address Match Interrupt 2.9 Address Match Interrupt 2.9.1 Overview
The address match interrupt is used for correcting a ROM or for a simplified debugging-purpose monitor. The following is an overview of the address match interrupt. (1) Enabling/disabling the address match interrupt The address match interrupt enable bit can be used to enable and disable an address match interrupt. It is affected neither by the processor interrupt priority level (IPL) nor the interrupt enable flag (I flag). (2) Timing of the address match interrupt An interrupt occurs immediately before executing the instruction in the address indicated by the address match interrupt register. Set the first address of the instruction in the address match interrupt register. Setting a half address of an instruction or an address of tabulated data does not generate an address match interrupt. The first instruction of an interrupt routine does not generate an address match interrupt either. (3) Returning from an address match interrupt The return address put in the stack when an address match interrupt occurs depends on the instruction not yet executed (the instruction the address match interrupt register indicates). The return address is not put in the stack. For this reason, to return from an address match interrupt, either rewrite the content of the stack and use the REIT instruction or use the POP instruction to restore the stack to the state as it was before the interrupt occurred and return by use of a jump instruction. Figure 2.9.1 shows unexecuted instructions and corresponding the stacked addresses. • 16-bit operation code instructions • 8-bit operation code instructions given below ADD.B:S OR.B:S STNZ.B:S CMP.B:S JMPS MOV.B:S #IMM8,dest #IMM8,dest #IMM8,dest #IMM8,dest #IMM8 SUB.B:S MOV.B:S STZX.B:S PUSHM JSRS #IMM8,dest #IMM8,dest src #IMM8 AND.B:S STZ.B:S POPM #IMM8,dest #IMM8,dest dest
#IMM81,#IMM82,dest
#IMM,dest (However, dest = A0/A1)
• Instructions other than those listed above Figure 2.9.1. Unexecuted instructions and corresponding stacked addresses (4) How to determine an address match interrupt Address match interrupts can be set at two different locations. However, both location will have the same vector address. Therefore, it is necessary to determine which interrupt has occurred; address match interrupt 0 or address match interrupt 1. Using the content of the stack, etc., determine which interrupt has occurred according to the first part of the address match interrupt routine.
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Address Match Interrupt
(5) Registers related to the address match interrupt Figure 2.9.2 shows the memory map of address match interrupt-related registers, and Figure 2.9.3 shows address match interrupt-related registers.
000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616
Address match interrupt enable register (AIER)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
Figure 2.9.2. Memory map of address match interrupt-related registers
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit symbol
Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit
When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW
AIER0 AIER1
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Address match interrupt register i (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1
Address 001216 to 001016 001616 to 001416
When reset X0000016 X0000016
Function Address setting register for address match interrupt Nothing is assigned.
Values that can be set R W 0000016 to FFFFF16
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Figure 2.9.3. Address match interrupt-related registers
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Address Match Interrupt 2.9.2 Operation of Address Match Interrupt
The following is an operation of address match interrupt. Figure 2.9.4 shows the set-up procedure of address match interrupt, and Figure 2.9.5 shows the overview of the address match interrupt handling routine. Operation (1) The address match interrupt handling routine sets an address to be used to cause the address match interrupt register to generate an interrupt. (2) Setting the address match enable flag to “1” enables an interrupt to occur. (3) An address match interrupt occurs immediately before the instruction in the address indicated by the address match interrupt register as a program is executed.
Setting address match interrupt register
Address match interrupt register 0 [Address 001216 to 001016] RMAD0 Address match interrupt register 1 [Address 001616 to 001416] RMAD1
(b23) b7 (b20) (b19) b4 b3 (b16) (b15) b0 b7 (b8) b0 b7 b0
Can be set to “0000016” to “FFFFF16”
Setting address match interrupt enable register
b7 b0
Address match interrupt enable register [Address 000916] AIER Address match interrupt 0 enable bit 1: Interrupt enabled Address match interrupt 1 enable bit 1: Interrupt enabled
Figure 2.9.4. Set-up procedure of address match interrupt
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Address Match Interrupt
Address match interrupt routine [1] Storing registers [2] Determining the interrupt address No No
Address match 0? Yes Address match 0 program
Address match 1? Yes Address match 1 program
[3] Rewriting the stack Restoring registers REIT Handling an error
Explanation: [1] Storing the contents of the registers holding the main program status to be kept. [2] Determining the interrupt address Determining which factor generated the interrupt. [3] Rewriting the stack Rewriting the return address.
Figure 2.9.5. Overview of the address match interrupt handling routine
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Key-Input Interrupt
2.10 Key-Input Interrupt 2.10.1 Overview
Key-input interrupt occurs when a falling edge is input to P00 through P07. The following is an overview of the key-input interrupt: (1) Enabling/disabling the key-input interrupt The key-input interrupt can be enabled and disabled using the key-input interrupt register. The keyinput interrupt is affected by the interrupt priority level (IPL) and the interrupt enable flag (I flag). (2) Occurrence timing of the key-input interrupt With key-input interrupt acceptance enabled, pins P00 through P07, which are set to input, become _____ _____ key-input interrupt pins (KI0 through KI7). A key-input interrupt occurs when a falling edge is input to a key-input interrupt pin. At this moment, the level of other key-input interrupt pins must be “H”. No interrupt occurs when the level of other key-input interrupt pins is “L”. (3) How to determine a key-input interrupt A key-input interrupt occurs when a falling edge is input to one of eight pins, but each pin has the same vector address. Therefore, read the input level of pins P00 through P07 in the key-input interrupt routine to determine the interrupted pin. (4) Registers related to the key-input interrupt Figure 2.10.1 shows the memory map of key-input interrupt-related registers, and Figure 2.10.2 shows key-input interrupt-related registers.
004D16
Key input interrupt control register(KUPIC)
03E216
Port P0 direction register (PD0)
03FC16
Pull-up control register 0 (PUR0)
Figure 2.10.1. Memory map of key-input interrupt-related registers
318
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Key-Input Interrupt
Interrupt control register (Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol KUPIC
Address 004D16
When reset XXXXX0002
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7
R
W
ILVL1
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested 1 : Interrupt requested
(Note1)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts.
Port P0 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PD0
Address 03E216
When reset 0016
Bit symbol
PD0_0 PD0_1 PD0_2 PD0_3 PD0_4 PD0_5 PD0_6 PD0_7
Bit name
Port P00 direction register Port P01 direction register Port P02 direction register Port P03 direction register Port P04 direction register Port P05 direction register Port P06 direction register Port P07 direction register
Function
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
RW
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0
Bit symbol
PU00 PU01 PU02 PU03
Address 03FC16
Bit name
P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up
When reset 0016
Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
PU06 PU07
P30 to P33 pull-up P34 to P35 pull-up
Figure 2.10.2. key-input interrupt-related registers
319
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Key-Input Interrupt
2.10.2 Operation of Key-Input Interrupt
The following is an operation of key-input interrupt. Figure 2.10.3 shows an example of a circuit that uses the key-input interrupt, Figure 2.10.4 shows an example of operation of key-input interrupt, and Figure 2.10.5 shows the setting procedure of key-input interrupt. Operation (1) Set the direction register of the ports to be changed to key-input interrupt pins to input, and set the pull-up function. (2) Setting the key-input interrupt control register and setting the interrupt enable flag makes the interrupt-enabled state ready. _____ _____ (3) If a falling edge is input to either KI0 through KI7, the key-input interrupt request bit goes to “1”.
P30 P31 P32 P33
VREF
I/O port P00 / KI0 P01 / KI1 P02 / KI2 P03 / KI3 P04 / KI4 P05 / KI5 P06 / KI6 P07 / KI7
Figure 2.10.3. Example of circuit using the key-input interrupt
(1) Enter to stop mode (2) Cancel stop mode (3) Key scan (4) Enter to stop mode Key matrix scan
P30 output P31 output P32 output P33 output P04 to P07 input Key input
Key input interrupt processing Key OFF Key ON Key OFF Key ON
Figure 2.10.4. Example of operation of key-input interrupt
320
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Key-Input Interrupt
Setting port P10 direction register
b7 b0
Port P0 direction register [Address 03E216] PD0 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port)
Setting pull-up control register 0
b7 b0
Pull-up control register 0 [Address 03FC16] PUR0 1 : Pulled high (P00 to P03) 1 : Pulled high (P04 to P07)
Setting interrupt control register
b7 b0
0
Key input interrupt control register [Address 004D16] KUPIC Interrupt priority level select bit
b2 b1 b0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 : Level 0 (interrupt disabled) 1 : Level 1 0 : Level 2 1 : Level 3 0 : Level 4 1 : Level 5 0 : Level 6 1 : Level 7
Interrupt request bit 0 : Interrupt not requested
Figure 2.10.5. Set-up procedure of key-input interrupt
321
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control 2.11 Power Control 2.11.1 Overview
‘Power Control’ refers to the reduction of CPU power consumption by stopping the CPU and oscillators, or decreasing the operation clock. The following is a description of the three available power control modes: (1) Modes Power control is available in three modes. (a) Normal operation mode • High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK selected. Each peripheral function operates according to its assigned clock. • Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the BCLK selected. Each peripheral function operates according to its assigned clock. • Low-speed mode fc becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock. • Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 2.11.1 is the state transition diagram of the above modes.
322
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
Transition of stop mode, wait mode Reset
All oscillators stopped
WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction Interrupt
CPU operation stopped
Stop mode
All oscillators stopped
CM10 = “1” Interrupt Interrupt CM10 = “1”
Medium-speed mode (divided-by-8 mode)
Wait mode
CPU operation stopped
Stop mode
All oscillators stopped
High-speed/mediumspeed mode
Wait mode
CPU operation stopped
Stop mode
CM10 = “1” Interrupt
Low-speed/low power dissipation mode
Wait mode
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode)
CM06 = “1” BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” CM04 = “1” (Notes 1, 3) CM07 = “0” (Note 1) CM06 = “1” CM04 = “0”
Main clock is oscillating CM04 = “0” Sub clock is oscillating High-speed mode
BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0”
Medium-speed mode (divided-by-2 mode)
BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1”
Medium-speed mode (divided-by-8 mode)
BCLK : f(XIN)/8 CM07 = “0” CM06 = “1”
Main clock is oscillating Sub clock is oscillating Low-speed mode
CM07 = “0” (Note 1, 3) BCLK : f(XCIN) CM07 = “1” CM07 = “1” (Note 2)
Medium-speed mode (divided-by-4 mode)
BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0”
Medium-speed mode (divided-by-16 mode)
BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1”
CM05 = “0” CM04 = “0”
CM05 = “1”
Main clock is oscillating Sub clock is stopped
CM04 = “1”
High-speed mode
BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” CM06 = “0” (Notes 1,3)
Medium-speed mode (divided-by-2 mode)
BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1”
Main clock is stopped Sub clock is oscillating Low power dissipation mode
CM07 = “1” (Note 2) CM05 = “1” BCLK : f(XCIN) CM07 = “1” CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1”
Medium-speed mode (divided-by-4 mode)
BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0”
Medium-speed mode (divided-by-16 mode)
BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow.
Figure 2.11.1. State transition diagram of power control mode
323
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
(2) Switching the driving capacity of the oscillation circuit Both the main clock and the secondary clock have the ability to switch the driving capacity. Reducing the driving capacity after the oscillation stabilizes allows for further reduction in power consumption. (3) Clearing stop mode and wait mode The stop mode and wait mode can be cleared by generating an interrupt request, or by resetting hardware. Set the priority level of the interrupt to be used for clearing, higher than the processor interrupt priority level (IPL), and enable the interrupt enable flag (I flag). When an interrupt clears a mode, that interrupt is processed. Table 2.11.1 shows the interrupts that can be used for clearing a stop mode and wait mode. (4) BCLK in returning from wait mode or stop mode (a) Returning from wait mode The processor immediately returns to the BCLK, which was in use before entering wait mode. (b) Returning from stop mode If operation was performed in the high speed mode or medium speed mode prior to engaging the stop mode, CM06 will change to “1” when operation shifts to the stop mode. CM17, CM16 and CM07 do not change. Accordingly, when operation is restored from the stop mode, operation starts in the 8 division mode. Also, if operation was performed in the low speed mode prior to engaging the stop mode, CM06, CM17, CM16 and CM07 do not change. When operation is restored from the stop mode, operation starts in the low speed mode.
Table 2.11.1. Interrupts available for clearing stop mode and wait mode
Interrupt for clearing Key input interrupt A-D interrupt UART0 transmit interrupt UART0 receive interrupt UART1 transmit interrupt UART1 receive interrupt Timer A0 interrupt Timer B0 interrupt Timer B1 interrupt Wait mode CM02 = 0 Possible Note 3 Possible Possible Possible Possible Possible CM02 = 1(Note 4), CM07=0, CM05=0 Possible Impossible Note 1 Note 1 Impossible Impossible Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Stop mode Possible Impossible Note 1 Note 1 Impossible Impossible Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Possible Possible
Possible Possible Possible Timer X0 interrupt Possible Timer X1 interrupt Possible Timer X2 interrupt Possible Possible INT0 interrupt Possible Possible INT1 interrupt Note 1: Can be used when an external clock in clock synchronous serial I/O mode is selected. Note 2: Can be used when the external signal is being counted in event counter mode. Note 3: Can be used in one-shot mode and one-shot sweep mode. Note 4: When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with CM02 set to 1.
324
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
(5) Sequence of returning from stop mode Sequence of returning from stop mode is oscillation start-up time and interrupt sequence. When interrupt is generated in stop mode, CM10 becomes “0” and clearing stop mode. Starting oscillation and supplying BCLK execute the interrupt sequence as follow: In the interrupt sequence, the processor carries out the following in sequence given: (a) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. The interrupt request bit of the interrupt written in address 0000016 will then be set to “0”. (b) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer assignment flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (d) Saves the content of the temporary register (Note) within the CPU in the stack area. (e) Saves the content of the program counter (PC) in the stack area. (f) Sets the interrupt priority level of the accepted instruction in the IPL. Note: This register cannot be utilized by the user. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Figure 2.11.2 shows the sequence of returning from stop mode.
Writing “1” to CM10 (all clock stop control bit)
Operated by divided-by-8 mode
BCLK Address bus Data bus RD WR INTi
Stop mode Oscillation start-up Interrupt sequence approximately 20 cycle (16µ sec) (Single-chip mode, f(XIN) = 10MHz)
Address 00000
Interrupt information
Indeterminate Indeterminate Indeterminate
SP-2
SP-4
vec
vec+2
vec+2 contents
PC
SP-2 SP-4 vec contents contents contents
Figure 2.11.2. Sequence of returning from stop mode
(6) Registers related to power control Figure 2.11.3 shows the memory map of power control-related registers, and Figure 2.11.4 shows power control-related registers.
325
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
000616 000716
System clock control register 0 (CM0) System clock control register 1 (CM1)
Figure 2.11.3. Memory map of power control-related registers
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0 Bit symbol
CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07
Address 000616 Bit name
Clock output function select bit
When reset 4816 Function
b1 b0
RW
0 0 : I/O port P54 0 1 : fC output 1 0 : f8 output 1 1 : Clock divide counter output
0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8)
WAIT peripheral function clock stop bit
XCIN-XCOUT drive capacity 0 : LOW select bit (Note 2) 1 : HIGH Port XC select bit Main clock (XIN-XOUT) stop bit (Note 3,4,5) Main clock division select bit 0 (Note 7) System clock select bit (Note 6) 0 : I/O port 1 : XCIN-XCOUT generation 0 : On 1 : Off 0 : CM16 and CM17 valid 1 : Division by 8 mode 0 : XIN, XOUT 1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: Changes to “1” when shifting to stop mode and at a reset. Note 3: This bit is used to stop the main clock when placing the device in a low-power mode. If you want to operate with XIN after exiting from the stop mode, set this bit to “0”. When operating with a self-excited oscillator, set the system clock select bit (CM07) to “1” before setting this bit to “1”. Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT (“H”) via the feedback resistor. Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”. Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock oscillating before setting this bit from “1” to “0”. Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 8: fC32 is not included. Do not set to “1” when using low-speed or low power dissipation mode.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
00
0
Symbol CM1 Bit symbol
CM10
Address 000716 Bit name
All clock stop control bit (Note 4)
When reset 2016 Function
0 : Clock on 1 : All clocks off (stop mode) Always set to “0” Always set to “0” Always set to “0” Always set to “0” 0 : LOW 1 : HIGH
b7 b6
RW
Reserved bit Reserved bit Reserved bit Reserved bit CM15 CM16 CM17 XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3)
0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8. Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-impedance state.
Figure 2.11.4. Power control-related registers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control 2.11.2 Stop Mode Set-Up
Settings and operation for entering stop mode are described here. Operation (1) Enables the interrupt used for returning from stop mode. (2) Sets the interrupt enable flag (I flag) to “1”. (3) Clearing the protection and setting every-clock stop bit to “1” stops oscillation and causes the processor to go into stop mode.
(1) Setting interrupt to cancel stop mode Interrupt control register
KUPIC ADIC SiTIC(i=0, 1) SiRIC(i=0, 1) TAiIC(i=0) TXiIC(i=0 to 2) TBiIC(i=0, 1)
b7 b0
[Address 004D16] [Address 004E16] [Address 005116, 005316] [Address 005216, 005416] [Address 005516] [Address 005616 to 005816] [Address 005A16, 005B16]
b7
INTiIC(i=0, 1)
b0
[Address 005D16, 005E16]
0 Interrupt priority level select bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority(IPL) of the routine where the WAIT instruction is executed. Interrupt priority level select bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority(IPL) of the routine where the WAIT instruction is executed. Reserved bit Must be set to “0”
(2) Interrupt enable flag (I flag)
“1 ”
(3) Canceling protect
b7 b0
1
Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled
(3) Setting operation clock after returning from stop mode
(When operating with XIN after returning)
b7 b0
(When operating with XCIN after returning)
b7 b0
System clock control register
[Address 000616] CM0 Main clock (XIN-XOUT) stop bit On System clock select bit XIN, XOUT
0
0
1
1
System clock control register 0
[Address 000616] CM0 Port XC select bit XCIN-XCOUT generation
As this register becomes setting mentioned above when operating with XIN (count source of BCLK is XIN), the user does not need to set it again.
System clock select bit XCIN, XCOUT As this register becomes setting mentioned above when operating with XCIN As this register becomes setting mentioned above when operating with XCIN (count source of BCLK is XCIN), the user does not need to set it again. (count source of BCLK is XCIN), the user does not need to set it again. When operating with XIN, set port Xc select bit to “1” before setting system clock When operating with XIN, set port Xc select bit to “1” before setting system clock select bit to “1”. The both bits cannot be set at the same time. select bit to “1”. The both bits cannot be set at the same time.
(3) All clocks off (stop mode)
b7 b0
0
0
0
01
System clock control register [Address 000716] CM1 All clock stop control bit 1 : All clocks off (stop mode) Reserved bit Must be set to “0”
All clocks off (stop mode)
Figure 2.11.5. Example of stop mode set-up
327
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control 2.11.3 Wait Mode Set-Up
Settings and operation for entering wait mode are described here. Operation (1) Enables the interrupt used for returning from wait mode. (2) Sets the interrupt enable flag (I flag) to “1”. (3) Clears the protection and changes the content of the system clock control register. (4) Executes the WAIT instruction.
(1) Setting interrupt to cancel wait mode Interrupt control register
KUPIC ADIC SiTIC(i=0, 1) SiRIC(i=0, 1) TAiIC(i=0) TXiIC(i=0 to 2) TBiIC(i=0, 1)
b7 b0
[Address 004D16] [Address 004E16] [Address 005116, 005316] [Address 005216, 005416] [Address 005516] [Address 005616 to 005816] [Address 005A16, 005B16]
b7
INTiIC(i=0 , 1)
b0
[Address 005D16, 005E16]
0
Interrupt priority level select bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority (IPL) of the routine where the WAIT instruction is executed.
Interrupt priority level select bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority (IPL) of the routine where the WAIT instruction is executed.
Reserved bit Must be set to “0”
(2) Interrupt enable flag (I flag)
“1”
(3) Canceling protect
b7 b0
1
Protect register [Address 000A16] PRCR
Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled
(3) Control of CPU clock
b7 b0
0
0
0
0
System clock control register 1 [Address 000716] CM1
Reserved bit Must be set to “0”
Main clock division select bit
b7 b6
b7
b0
System clock control register 0 [Address 000616] CM0
WAIT peripheral function clock stop bit(Note 2) 0 : Do not stop f1, f8, f32 in wait mode 1 : Stop f1, f8, f32 in wait mode Port XC select bit 0 : I/O port 1 : XCIN-XCOUT generation Main clock (XIN-XOUT) stop bit 0 : On 1 : Off Main clock division select bit 0 0 : CM16 and CM17 valid 1 : Division by 8 mode System clock select bit (Note 1, Note 2) 0 : XIN, XOUT 1 : XCIN, XCOUT
0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode
Note 1: When switching the system clock, it is necessary to wait for the oscillation to stabilize. Note 2: Set the WAIT peripheral function clock stop bit to “0” when the system clock select bit is “1”.
(4) WAIT instruction
Wait mode
Figure 2.11.6. Example of wait mode set-up
328
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control 2.11.4 Precautions in Power Control
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to “1”. (3) Suggestions to reduce power consumption • Ports The processor retains the state of each programmable I/O port even when it goes to wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in input ports that float. When entering wait mode or stop mode, set non-used ports to input and stabilize the potential. (a) A-D converter A current always flows in the VREF pin. When entering wait mode or stop mode, set the Vref connection bit to “0” so that no current flows into the VREF pin. (b) Stopping peripheral functions In wait mode, stop non-used wait peripheral functions using the peripheral function clock stop bit. However, peripheral function clock fC32 does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. (c) Switching the oscillation-driving capacity Set the driving capacity to “LOW” when oscillation is stable. (d) External clock When using an external clock input for the CPU clock, set the main clock stop bit to “1”. Setting the main clock stop bit to “1” causes the XOUT pin not to operate and the power consumption goes down (when using an external clock input, the clock signal is input regardless of the content of the main clock stop bit).
329
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
2.12 Programmable I/O Ports 2.12.1 Overview
Fourty-three programmable I/O ports. I/O pins also serve as I/O pins for built-in peripheral functions. Each port has a direction register that defines the I/O direction and also has a port register for I/O data. In addition, each port has a pull-up control register that defines pull-up in terms of 4 bits. Port P1 can be set to N-channel output transistor drive capacity. The following is an overview of the programmable I/O ports: (1) Writing to a port register With the direction register set to output, the level of the written values from each relevant pin is output by writing to a port register. The output level conforms to CMOS output. Writing to the port register, with the direction register set to input, inputs a value to the port register, but nothing is output to the relevant pins. The output level remains floating. (2) Reading a port register With the direction register set to output, reading a port register takes out the content of the port register, not the content of the pin. With the direction register set to input, reading the port register takes out the content of the pin. (3) Effect of the protection register Data written to the direction register of P4 is affected by the protection register. The direction register of P4 cannot be easily rewritten. (4) Setting pull-up The pull-up control bit allows setting of the pull-up, in terms of 4 bits, either in use or not in use. For the four bits chosen, pull-up is effective only in the ports whose direction register is set to input. Pull-up is not effective in ports whose direction register is set to output. Do not set pull-up of corresponding pin when XCIN/XCOUT is set or a port is used as A-D input. (5) Drive capacity control The drive capacity of the N channel output transistor on P1 can be set between “LOW” and “HIGH” in units of 1 bit. One bit corresponds to one pin.
330
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
(6) I/O functions of built-in peripheral devices Table 2.12.1 shows relation between ports and I/O functions of built-in peripheral devices. Table 2.12.1. Relation between ports and I/O functions of built-in peripheral devices
Port P0 P40 P41 P42 P43, P44 P45 P50 to P54 P6 P70, P71
Internal peripheral device I/O pins key-input interrupt function input pins I/O pin for serial I/O communication/Timer A input pin Timer A output pin Serial I/O input pin Input pins for external interrupt/Timer X I/O pins Timer X I/O pin I/O pins for serial I/O communication/A-D converter input pins A-D converter input pins Timer B input pins
(7) Examples of working on non-used pins Table 2.12.2 contains examples of working on non-used pins. There are shown here for mere examples. In practical use, make suitable changes and perform sufficient evaluation in compliance with you application.
Table 2.12.2. Examples of working on unused pins in single-chip mode
Pin name Ports P0, P1, P3 to P7
Connection After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. (Note 1) Open Connect to VCC Connect to VSS
XOUT (Note 2) AVCC AVSS, VREF, BYTE
Note 1: If setting these pins in output mode and opening them, ports are in input mode until switched into output mode by use of software after reset. Thus the voltage levels of the pins become unstable, and there can be instances in which the power source current increases while the ports are in input mode. In view of an instance in which the contents of the direction registers change due to a runaway generated by noise or other causes, setting the contents of the direction registers periodically by use of software increases program reliability. Note 2: When an external clock is input to the XIN pin.
331
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
(8) Registers related to the programmable I/O ports Figure 2.12.1 shows the memory map of programmable I/O ports-related registers, and Figures 2.12.2 to 2.12.4 show programmable I/O ports-related registers.
03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03FC16 03FD16 03FE16
Port P0 (P0) Port P1 (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P3 (P3) Port P3 direction register (PD3) Port P4 (P4) Port P5 (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 (P6) Port P7 (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Port P1 drive control register (DRR)
Figure 2.12.1. Memory map of programmable I/O ports-related registers
332
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Port Pi direction register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PDi (i = 0 to 7)
Address 03E216, 03E316, 03E716, 03EA16, 03EB16, 03EE16, 03EF16
When reset 0016 0016
Bit symbol
PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7
Bit name
Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register
Function
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 7 except 2)
RW
Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port P4 direction register. Note 2: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to P77. These bits can either be set nor reset. When read, its contents are indeterminate.
Port Pi register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Pi (i = 0 to 7)
Address 03E016, 03E116, 03E516, 03E816, 03E916, 03EC16, 03ED16 Bit name Function
When reset Indeterminate Indeterminate RW
Bit symbol
Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7
Port Pi0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register
Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data (i = 0 to 7 except 2)
Note: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to P77. This bit can either be set nor reset. When read, its content is indeterminate.
Figure 2.12.2. Programmable I/O ports-related registers (1)
333
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0 Bit symbol
PU00 PU01 PU02 PU03
Address 03FC16 Bit name
P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up
When reset 0016 Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
PU06 PU07
P30 to P33 pull-up P34 to P35 pull-up
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1 Bit symbol
PU10 PU11 PU12 PU13 PU14 PU15 PU16
Address 03FD16 Bit name
P40 to P43 pull-up P44 to P47 pull-up P50 to P53 pull-up P54 pull-up P60 to P63 pull-up P64 to P67 pull-up P70 to P71 pull-up
When reset 0016 Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW
Port P1 drive capacity control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DRR Bit symbol
DRR0 DRR1 DRR2 DRR3 DRR4 DRR5 DRR6 DRR7
Address 03FE16 Bit name
Port P10 drive capacuty Port P11 drive capacuty Port P12 drive capacuty Port P13 drive capacuty Port P14 drive capacuty Port P15 drive capacuty Port P16 drive capacuty Port P17 drive capacuty
When reset 0016 Function
Set P1 N-channel output transistor drive capacity 0 : LOW 1 : HIGH RW
Figure 2.12.3. Programmable I/O ports-related registers (2)
334
Chapter 3
Examples of Peripheral functions Applications
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Applications Timer X Applications
This chapter presents applications in which peripheral functions built in the M16C/20 are used. They are shown here as examples. In practical use, make suitable changes and perform sufficient evaluation. For basic use, see Chapter 2 How to Use Peripheral Functions. Here follows the list of applications that appear in this chapter.
• 3.1 Long-period timers .............................................................................................................. P338 • 3.2 Variable-period variable-duty PWM output ......................................................................... P342 • 3.3 Delayed one-shot output .................................................................................................... P346 • 3.4 Buzzer output ..................................................................................................................... P350 • 3.5 Solution for external interrupt pins shortage ....................................................................... P352 • 3.6 Controlling power using stop mode .................................................................................... P354 • 3.7 Controlling power using wait mode ..................................................................................... P358
336
Mitsubishi microcomputers
M30201 Group
Timer X Applications Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
[MEMO]
337
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X Applications 3.1 Long-Period Timers
Overview In this process, Timer X0 and Timer X1 are connected to make a 16-bit timer with a 16-bit prescaler. Figure 3.1.1 shows the operation timing, Figure 3.1.2 shows the connection diagram, and Figures 3.1.3 and 3.1.4 show the set-up procedure. Use the following peripheral functions: • Timer mode of timer X • Event counter mode of timer X Specifications (1) Set timer X0 to timer mode, and set timer X1 to event counter mode. (2) Perform a count on count source f1 using timer X0 to count for 1 ms, and perform a count on timer X0 using timer X1 to count for 1 second. (3) Connect a 10-MHz oscillator to XIN. Operation (1) Setting the count start flag to “1” causes the counter to begin counting. The counter of timer X0 performs a down count on count source f1. (2) If the counter of timer X0 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer X0 interrupt request bit goes to “1”. The counter of timer X1 performs a down count on underflows in timer X0. (3) If the counter of timer X1 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer X1 interrupt request bit goes to “1”.
l = reload register content
Timer X0 counter content (hex)
FFFF16 l
(1) Start count (2) Timer X0 underflow
(3) Timer X1 underflow
000016
Timer X1 counter content (hex)
Time n = reload register content FFFF16 n 000016 Set to “1” by software Cleard “0” by software Time “1” “0” Set to “1” by software “1” “0” Start count.
Timer X0 count start flag Timer X1 count start flag
Timer X0 interrupt “1” “0” request bit Cleared to “0” when interrupt request is accepted, or cleared by software Timer X1 interrupt “1” request bit “0”
Figure 3.1.1. Operation timing of long-period timers
338
Mitsubishi microcomputers
M30201 Group
Timer X Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
f1 f8 f32 fC32
Used for timer mode Timer X0 Timer X1 Timer X0 interrupt request bit Timer X1 interrupt request bit
Used for event counter mode
Figure 3.1.2. Connection diagram of long-period timers
339
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X Applications
Setting timer X0
Selecting timer mode and functions
b7 b0
0
0
0
0
0
0
0
0
Timer X0 mode register [Address 039716] TX0MR
Selection of timer mode
Pulse output function select bit 0 : Pulse is not output (TX0INOUT pin is a normal port pin)
Gate function select bit
b4 b3
0 0 : Gate function not available (TX0INOUT pin is a normal port pin)
0 (Must always be “0” in timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1
Count source
f1 f8 f32 fC32
Count source period
f(XIN) : 10MHZ f(XcIN) : 32.768kHZ 100ns 800ns 3.2µs 976.56µs
Setting divide ratio
(b15) b7 (b8) b0 b7
b0
2716
0F16
Timer X0 register [Address 038916, 038816] TX0
Setting timer X1 Selecting event counter mode and each function
b7 b0
0
0
0
0
0
0
0
1
Timer X1 mode register [Address 039816] TX1MR
Selection of event counter mode
Pulse output function select bit] 0 : Pulse is not output (TX1INOUT pin is a normal port pin)
Count polarity select bit
0 (Must always be “0” in event counter mode)
0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type 0 (Must always be “0” in event counter mode)
Continued to the next page
Figure 3.1.3. Set-up procedure of long-period timers (1)
340
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M30201 Group
Timer X Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Setting trigger select register
b7 b0
10
Trigger select register [Address 038316] TRGSR Timer X1 event/trigger select bit
b5 b4
1 0 : TX0 overflow is selected
Setting divide ratio
(b15) b7 (b8) b0 b7
b0
0316
E716
Timer X1 register [Address 038B16, 038A16] TX1
Setting count start flag
b7 b0
1
1
Count start flag [Address 038016] TABSR Timer X0 count start flag 1 : Starts counting Timer X1 count start flag 1 : Starts counting
Start counting
Figure 3.1.4. Set-up procedure of long-period timers (2)
341
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X Applications 3.2 Variable-Period Variable-Duty PWM Output
Overview In this process, Timer X0 and A1 are used to generate variable-period, variable-duty PWM output. Figure 3.2.1 shows the operation timing, Figure 3.2.2 shows the connection diagram, and Figures 3.2.3 and 3.2.4 show the set-up procedure. Use the following peripheral functions: • Timer mode of timer X • One-shot timer mode of timer X Specifications (1) Set timer X0 in timer mode, and set timer X1 in one-shot timer mode with pulse-output function. (2) Set 1 ms, the PWM period, to timer X0. Set 500 µs, the width of PWM “H” pulse, to timer X1. Both timer X0 and timer X1 use f1 for the count source. (3) Connect a 10-MHz oscillator to XIN. Operation (1) Setting the count start flag to “1” causes the counter of timer X0 to begin counting. The counter of timer X0 performs a down count on count source f1. (2) If the counter of timer X0 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer X0 interrupt request bit gose to “1”. (3) An underflow in timer X0 triggers the counter of timer X1 and causes it to begin counting. When the counter of timer X1 begins counting, the output level of the TX1INOUT pin gose to “H”. (4) As soon as the count of the counter of timer X1 becomes “000016”, the output level of TX1INOUT pin gose to “L”, and the counter reloads the content of the reload register and stops counting. At the same time, the timer X1 interrupt request bit gose to “1”.
342
Mitsubishi microcomputers
M30201 Group
Timer X Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
l = reload register content (1) Timer X0 start count
Timer X0 counter content (hex)
FFFF16 l
(2) Timer X0 underflow
000016
Timer X1 counter content (hex)
n = reload register content FFFF16 n 000016 Set to “1” by software (3) Timer X1 start count (4) Timer X1 stop count
Time
Time
Timer X0 count start flag Timer X1 count start flag
“1” “0” “1” “0”
Set to “1” by software 1ms 500µs
PWM pulse output “H” from TX1INOUT pin “L” Timer X0 interrupt “1” request bit “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timer X1 interrupt “1” request bit “0” Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 3.2.1. Operation timing of variable-period variable-duty PWM output
f1
Used for timer mode (Set to period)
f8
Timer X0
f32 fC32
Timer X0 interrupt request bit
Timer X1
Timer X1 interrupt request bit
Used for one-shot timer mode (Set to “H” width)
Figure 3.2.2. Connection diagram of variable-period variable-duty PWM output
343
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X Applications
Setting timer X0 Selecting timer mode and functions
b7 b0
0
0
0
0
0
0
0
0
Timer X0 mode register [Address 039716 ] TX0MR Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TX0INOUT pin is a normal port pin) Gate function select bit
b4 b3
0 0 : Gate function not available (TX0INOUT pin is a normal port pin) 0 (Must always be “0” in timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Setting divide ratio
(b15) b7 (b8) b0 b7 b0
2716
0F16
Timer X0 register [Address 038916, 038816] TX0
Setting timer X1 Selecting one-shot timer mode and functions
b7 b0
0
0
0
1
0
1
1
0
Timer X1 mode register [Address 039816 ] TX1MR Selection of one-shot timer mode Pulse output function select bit (Note) 1 : Pulse is output External trigger select bit (Invalid when choosing timer's overflow as trigger) Trigger select bit 1 : Selected by event/trigger select register 0 (Must always be “0” in one-shot timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note: Set the corresponding port direction register to “1” (output mode).
Continued to the next page
Figure 3.2.3. Set-up procedure of variable-period variable-duty PWM output (1)
344
Mitsubishi microcomputers
M30201 Group
Timer X Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Setting trigger select register
b7 b0
10
Trigger select register [Address 038316] TRGSR Timer X1 event/trigger select bit
b5 b4
1 0 : TX0 overflow is selected
Setting one-shot timer's time
(b15) b7 (b8) b0 b7 b0
1316
8816
Timer X1 register [Address 038B16, 038A16] TX1
Setting count start flag
b7 b0
11
Count start flag [Address 038016] TABSR Timer X0 count start flag 1 : Starts counting Timer X1 count start flag 1 : Starts counting
Start counting
Figure 3.2.4. Set-up procedure of variable-period variable-duty PWM output (2)
345
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X Applications 3.3 Delayed One-Shot Output
Overview The following are steps of outputting a pulse only once after a specified elapse since an external trigger is input. Figure 3.3.1 shows the operation timing, Figure 3.3.2 shows the connection diagram, and Figures 3.3.3 and 3.3.4 show the set-up procedure. Use the following peripheral function: • One-shot timer mode of timer X Specifications (1) Set timer X0 in one-shot timer mode, and set timer X1 in one-shot timer mode with pulseoutput function. (2) Set 1 ms, an interval before a pulse is output, in timer X0; and set 50 µs, a pulse width, in timer X1. Both timer X0 and timer X1 use f1 for the count source. (3) Connect a 10-MHz oscillator to XIN. Operation (1) Setting the trigger select bit to “1” and setting the count start flag to “1” enables the counter of timer X0 to count. (2) If an effective edge, selected by use of the external trigger select bit, is input to the TX0INOUT pin, the counter begins a down count. The counter of timer X0 performs a down count on count source f1. (3) As soon as the counter of timer X0 becomes “000016”, the counter reloads the content of the reload register and stops counting. At this time, the timer X0 interrupt request bit gose to “1”. (4) An underflow in timer X0 triggers the counter of timer X1 and causes it to begin counting. When timer X1 begins counting, the output level of the TX1INOUT pin gose to “H”. (5) As soon as the counter of timer X1 becomes “000016”, the output level of the TX1INOUT pin gose to “L”, the counter reloads the content of the reload register, and stops counting. At this time, timer X1 interrupt request bit gose to “1”.
346
Mitsubishi microcomputers
M30201 Group
Timer X Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
l = reload register content (1) Count enabled (2) Timer X0 start count
Timer X0 counter content (hex)
FFFF16 l
(3) Timer X0 stop count
000016
Timer X1 counter content (hex)
n = reload register content FFFF16 n 000016 Set to “1” by software (4) Timer X1 start count (5) Timer X1 stop count
Time
Time
Timer X0 count start flag Timer X1 count start flag Input signal from TX0INOUT pin
“1” “0” “1” “0” “H” “L”
Set to “1” by software
1ms
50µs
PWM pulse output “H” from TX1INOUT pin “L” Timer X0 interrupt “1” “0” request bit Timer X1 interrupt request bit Cleared to “0” when interrupt request is accepted, or cleared by software “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software
Figure 3.3.1. Operation timing of delayed one-shot output
TX0INOUT pin input
f1 f8 f32 fC32
Used for one-shot timer mode Timer X0 Timer X0 interrupt request bit
Timer X1
Timer X1 interrupt request bit
Used for one-shot timer mode Figure 3.3.2. Connection diagram of delayed one-shot output
347
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X Applications
Setting timer X0 Selecting one-shot timer mode and functions
b7 b0
0
0
0
1
0
0
1
0
Timer X0 mode register [Address 039716] TX0MR Selection of one-shot timer mode Pulse output function select bit 0 : Pulse is not output External trigger select bit 0 : Falling edge of TX0INOUT pin's input signal Trigger select bit 1 : Selected by event/trigger select register 0 (Must always be “0” in one-shot timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Setting trigger select register
(Select TX0INOUT pin to input TX0 trigger)
b7 b0
0
0
Trigger select register [Address 038316] TRGSR Timer X0 event/trigger select bit
b3 b2
0 0 : Input on TX0INOUT is selected (Note)
Note: Set the corresponding port direction register to “0” (input mode).
Setting delay time
(b15) b7 (b8) b0 b7 b0
2716
1016
Timer X0 register [Address 038916, 038816] TX0
Continued to the next page
Figure 3.3.3. Set-up procedure of delayed one-shot output (1)
348
Mitsubishi microcomputers
M30201 Group
Timer X Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Continued from the previous page
Setting timer X1 Selecting one-shot timer mode and functions
b7 b0
0
0
0
1
0
1
1
0
Timer X1 mode register [Address 039816] TX1MR Selection of one-shot timer mode Pulse output function select bit (Note) 1 : Pulse is output (TX1INOUT pin is pulse output pin) External trigger select bit Invalid when choosing timer's overflow Trigger select bit 1 : Selected by event/trigger select register 0 (Must always be “0” in one-shot timer mode) Count source select bit
b7 b6
b7 b6 0 0 1 1 0 1 0 1
0 0 : f1
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
Note: Set the corresponding port direction register to “1” (output mode).
Setting trigger select register
(Set timer X0 to trigger timer X1)
b7 b0
10
Trigger select register [Address 038316] TRGSR Timer X1 event/trigger select bit
b5 b4
1 0 : TX0 overflow is selected
Setting one-shot timer's time
(b15) b7 (b8) b0 b7 b0
0116
3216
Timer X1 register [Address 038B16, 038A16] TX1
Setting count start flag
b7 b0
1
1
Count start flag [Address 038016] TABSR Timer X0 count start flag 1 : Starts counting Timer X1 count start flag 1 : Starts counting
Start counting
Figure 3.3.4. Set-up procedure of delayed one-shot output (2)
349
Mitsubishi microcomputers
M30201 Group
Timer X Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.4 Buzzer Output
Overview The timer mode is used to make the buzzer ring. Figure 3.4.1 shows the operation timing, and Figure 3.4.2 shows the set-up procedure. Use the following peripheral function: • The pulse-outputting function in timer mode of timer X. Specifications (1) Sound a 2-kHz buzz beep by use of timer X0. (2) Effect pull-up in the relevant port by use of a pull-up resistor. When the buzzer is off, set the port high-impedance, and stabilize the potential resulting from pulling up. (3) Connect a 10-MHz oscillator to XIN. Operation (1) The microcomputer begins performing a count on timer X0. Timer X0 has disabled interrupts. (2) P43 is TX0INOUT pin. Setting the port P43 direction register to “1” (output mode) and outputs 2kHz pulses. (3) The microcomputer stops outputting pulses by setting the port P43 direction register to “0” (input mode). P43 goes to an input pin, and the output from the pin becomes high-impedance.
(1) Start count
(2) Buzzer output ON
(3) Buzzer output OFF
Timer X0 overflow timing
“1”
Count start flag
“0” “1” “0”
“1”
Port P43 direction register
P43 output
“0”
High-impedance
High-impedance
Figure 3.4.1. Operation timing of buzzer output
350
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X Applications
Initialization of port P4 direction register
b7 b0
1
Protect register [Address 000A16] PRCR Enables writing to port P4 direction register 1 : Write-enabled
b7
b0
0
Port P4 direction register [Address 03EA16] PD4 Port P43 direction register 0 : Input mode
Initialization of timer X0
b7 b0 b15 b8 b7 b0
000
00
1
00
Timer X0 mode register TX0MR [Address 039716 ] Selection of timer mode Pulse output function select bit 1 : Pulse is output Gate function select bit
b4 b3
0016
b7 b0
F916
Timer X0 register TX0 [Address 038916, 038816]
0 0 : Gate function not available 0 (Must always be “0” in timer mode) Count source select bit
b7 b6
0 0 : f1
b7 b6 0 0 1 1 0 1 0 1
Count source period Count source f(XIN) : 10MHZ f(XcIN) : 32.768kHZ
f1 f8 f32 fC32 100ns 800ns 3.2µs 976.56µs
b7
b0
1
Count start flag [Address 038016] TABSR Timer X0 count start flag 1 : Starts counting
Buzzer ON
b7 b0
1
Protect register [Address 000A16] PRCR Enables writing to port P4 direction register 1 : Write-enabled
b7
b0
1
Port P4 direction register [Address 03EA16] PD4 Port P43 direction register 1 : Output mode
Buzzer OFF
b7 b0
1
Protect register [Address 000A16] PRCR Enables writing to port P4 direction register 1 : Write-enabled
b7
b0
0
Port P4 direction register [Address 03EA16] PD4 Port P43 direction register 0 : Input mode
Figure 3.4.2. Set-up procedure of buzzer output
351
Mitsubishi microcomputers
M30201 Group
Timer X Applications
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
3.5 Solution for External Interrupt Pins Shortage
Overview The following are solution for external interrupt pins shortage. Figure 3.5.1 shows the set-up procedure. Use the following peripheral function: • Event counter mode of timer X Specifications (1) Inputting a falling edge to the TX0INOUT pin generates a timer X0 interrupt. Operation (1) Set timer X0 to event counter mode, set timer to “0”, and set interrupt priority levels in timer X0. (2) Inputting a falling edge to the TX0INOUT pin generates a timer X0 interrupt.
352
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X Applications
Initialization of timer X0
b7 b0
0
0
00
0
00
1
Timer X0 mode register TX0MR [Address 039716 ] Selection of event counter mode
b15
b8
b7
b0
0016
b7 b0
0016
Timer X0 register TX0 [Address 038916, 038816]
Pulse output function select bit 0 : Pulse is not output (TX0INOUT pin is a normal port pin) Count polarity select bit 0 : Counts external signal's falling edge 0 (Must always be “0” in event counter mode) 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type 0 (Must always be “0” in event counter mode)
b7 b0
1
Count start flag [Address 038016] TABSR Timer X0 count start flag 1 : Starts counting
b0
b7
00
Trigger select register [Address 038316] TRGSR Timer X0 event/trigger select bit
b3 b2
0 0 : Input on TX0INOUT is selected
Setting interrupt priority levels in timer X0
b7 b0
Timer X0 interrupt control register [Address 005616] TX0IC Interrupt control level (set a value 1 to 7)
Initialization of port P4 direction register
b7 b0
1
Protect register [Address 000A16] PRCR Enables writing to port P4 direction register 1 : Write-enabled
b7
b0
0
Port P4 direction register [Address 03EA16] PD4 Port P43 direction register 0 : Input mode
Setting interrupt enable flag (I flag)
Figure 3.5.1. Set-up procedure of solution for a shortage of external interrupt pins
353
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Controlling Power Applications 3.6 Controlling Power Using Stop Mode
Overview The following are steps for controlling power using stop mode. Figure 3.6.1 shows the operation timing, Figure 3.6.2 shows an example of circuit, and Figures 3.6.3 and 3.6.4 show the set-up procedure. Use the following peripheral functions: • Key-input interrupts • Stop mode • Pull-up function
Specifications _____ (1) Use P30 through P33 for the scan output pins of a key matrix. Use the input pins (KI0 through _____ KI7) of the key-input interrupt function for the key-input reading pins. The pull-up function is also used. (2) If a key-input interrupt request occurs, clear the stop mode and read a key.
_____ _____
Operation (1) Enable a key-input interrupt and set the pull-up function to pins KI0 through KI7. Change the output of P30 through P33 to “L” and enter stop mode. _____ _____ (2) If a key is pressed, “L” is input to one of pins KI0 through KI7 to clear stop mode. A key-input interrupt occurs to execute the key-input interrupt handling routine. (3) Sequentially set P30 through P33 to “L” to determine which key was pressed. (4) When the process to determine the key pressed is completed, change the output from P30 through P33 to “L” again and enter stop mode.
(1) Shift to stop mode (2) Cancel a stop mode (3) Key scan (4) Shift to stop mode Key matrix scan
P30 output P31 output P32 output P33 output P00 to P07 input Key input
Key input interrupt processing CPU clock Stop mode Stop mode Key OFF Key ON Key OFF Key ON
Figure 3.6.1. Operation timing of controlling power using stop mode
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Controlling Power Applications
P30 P31 P32 P33
VREF
I/O port P00 / KI0 P01 / KI1 P02 / KI2 P03 / KI3 P04 / KI4 P05 / KI5 P06 / KI6 P07 / KI7
Figure 3.6.2. Example of circuit of controling power using stop mode
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Controlling Power Applications
Main
Initial condition
b7 b0
11
Pull-up control register 0 [Address 03FC16] PUR0 P00 to P03 pulled high P04 to P07 pulled high
b7
b0
0
0
00
00
0
0
Port P0 direction register [Address 03E216] PD0 Key scan input port
b7
b0
11
b7 b0
1
1
Port P3 direction register [Address 03E716] PD3 Key scan output port
0
00
0
Port P3 register [Address 03E516] P3 Key scan data
b7
b0
00
1
Key input interrupt control register [Address 004D16] KUPIC Interrupt priority level select bit Set higher value than the present IPL
Interrupt enable level (IPL) = 0 Interrupt enable flag (I) =0
Setting interrupt except stop mode cancel
Interrupt control register KUPIC
b7
0
ADIC SiTIC(i=0, 1) SiRIC(i=0, 1) TAiIC(i=0) b0 TXiIC(i=0 to 2) 0 0 TBiIC(i=0, 1)
[Address 004D16] [Address 004E16] [Address 005116, 005316] [Address 005216, 005416] [Address 005516] [Address 005616 to 005816] [Address 005A16, 005B16]
b7
b0
0
0
0
0
INTiIC(i=0, 1)
[Address 005D16, 005E16]
Interrupt priority level select bit 0 0 0 : Interrupt disabled
Interrupt priority level select bit 0 0 0 : Interrupt disabled Always set to “0”
Canceling protect
b7 b0
1
Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled
Setting operation clock after returning from stop mode
(When operating with XIN after returning)
b7 b0
(When operating with XCIN after returning)
b7 b0
System clock control register 0
[Address 000616] CM0 Main clock (XIN-XOUT) stop bit On System clock select bit XIN, XOUT
System clock control register 0
[Address 000616] CM0 Port XC select bit XCIN-XCOUT generation System clock select bit XCIN, XCOUT
0
0
1
1
As this register becomes setting mentioned above when operating with XIN (count source of BCLK is XIN), the user does not need to set it again.
As this register becomes setting mentioned above when operating with XCIN (count source of BCLK is XCIN), the user does not need to set it again. When operating with XIN, set port Xc select bit to “1” before setting system clock select bit to “1”. The both bits cannot be set at the same time.
Interrupt enable flag (I flag)
“1 ”
All clocks off (stop mode)
b7 b0
0
00
0
1
System clock control register 1 [Address 000716] CM1 All clock stop control bit 1 : All clocks off (stop mode) Reserved bit Always set to “0”
NOP instruction X 5
Key input interrupt request generation
Figure 3.6.3. Set-up procedure of controlling power using stop mode (1)
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Controlling Power Applications
Key-input interrupt
Store the registers
Key matrix scan
b7 b0
Port P3 register [Address 03E516] P3 Key scan data 1110, 1101, 1011, 0111
Decision of key-input data
b7
b0
0
0
0
0
Port P3 register [Address 03E5416] P3 Key scan data
Restore the registers
REIT instruction
Figure 3.6.4. Set-up procedure of controlling power using stop mode (2)
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Controlling Power Applications 3.7 Controling Power Using Wait Mode
Overview The following are steps for controling power using wait mode. Figure 3.7.1 shows the operation timing, and Figures 3.7.2 to 3.7.4 show the set-up procedure. Use the following peripheral functions: • Timer mode of timer B • Wait mode A flag named “F-WIT” is used in the set-up procedure. The purpose of this flag is to decide whether or not to clear wait mode. If F_WIT = “1” in the main program, the wait mode is entered; if F_WIT = “0”, the wait mode is cleared. Specifications (1) Connect a 32.768-kHz oscillator to XCIN to serve as the timer count source. As interrupts occur every one second, which is a count the timer reaches, the controller returns from wait mode and count the clock using a program. ________ (2) Clear wait mode if a INT0 interrupt request occurs. Operation (1) Switch the system clock from XIN to XCIN to get low-speed mode.
_______
(2) Stop XIN and enter wait mode. In this instance, enable the timer B0 interrupt and the INT0 interrupt. (3) When a timer B0 interrupt request occurs (at 1-second intervals), start supplying the BCLK from XCIN. At this time, count the clock within the routine that handles the timer B0 interrupts and enter wait mode again. _______ (4) If a INT0 interrupt occurs, start supplying the BCLK from XCIN. Start the XIN oscillation within _______ the INT0 interrupt, and switch the system clock to XIN.
(1) Shift to low-speed mode (2) Stop XIN (3) Timer B0 interrupt XOUT (4) INT0 interrupt
XCIN
Timer B0 overflow Timer B0 interrupt processing INT0 “H” “L”
BCLK High-speed Low-speed Low-speed Low-speed High-speed Low-speed
Figure 3.7.1. Operation timing of controling power using wait mode
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Controlling Power Applications
Main
Initial condition
b7 b0
0
0
1
0
System clock control register 0 [Address 000616] CM0 WAIT peripheral function clock stop bit 0 : Do not stop peripheral function clock in wait mode XCIN-XCOUT drive capacity select bit Port Xc select bit 1 : Functions as XCIN-XCOUT oscillator Main clock (XIN-XOUT) stop bit 0 : Oscillating Main clock divide ratio select bit 0 System clock select bit 0 : XIN-XOUT
b7
b0
1
1
00
Timer B0 mode register [Address 039B16] TB0MR Operation mode select bit
b1 b0
0 0 : Timer mode Count source select bit
b7 b6
1 1 : fC32 (f(XCIN) divided by 32)
b15 b8 b7 b0
0316
b7 b0
FF16
Timer B0 register [Address 039116, 039016] TB0
1
Clock prescaler reset flag [Address 038116] CPSRF Rrescaler is reset
b7
b0
1
Count start flag [Address 038016] TABSR TB0 start counting
b7
b0
0
0
1
Timer B0 interrupt control register [Address 005A16] TB0IC TB0 interrupt priority level INT0 interrupt control register [Address 005D16] INT0IC INT0 interrupt priority level
b7
b0
0
0
01
Interrupt priority level (IPL) = 0 Interrupt enable flag (I) = 0
Setting interrupt except clearing wait mode
Interrupt control register KUPIC ADIC SiTIC (i = 0, 1) SiRIC (i = 0, 1) TAiIC (i = 0) TXiIC (i = 0 to 2) TBiIC (i = 0, 1) [Address 004D16] [Address 004E16] [Address 005116, 005316] [Address 005216, 005416] [Address 005516] [Address 005616 to 005816] [Address 005A16, 005B16]
b7
b0
0
00 Interrupt priority level select bit
b2 b1 b0
0 0 0 : Interrupt disabled
Continued to the next page
Figure 3.7.2. Set-up procedure of controlling power using wait mode (1)
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Controlling Power Applications
Continued from the previous page
Canceling protect
b7 b0
1
Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (address 000616 and 000716) 1 : write-enabled
Switching system clock
b7 b0
1
System clock control register 0 [Address 000616] CM0 System clock select bit 1 : XCIN-XCOUT
Stopping main clock
b7 b0
1
System clock control register 0 [Address 000616] CM0 Main clock (XIN-XOUT) stop bit 1 : Off
Interrupt enable flag (I flag)
“1 ”
[F_WIT] = 1
WAIT instruction
NOP instruction X 5
INT0 interrupt request generated
=
[F_WIT] : 1
TB0 interrupt request generated
Starting main clock oscillator
b7 b0
0
System clock control register 0 [Address 000616] CM0 Main clock (XIN-XOUT) stop bit 0 : On
Switching system clock
b7 b0
0
System clock control register 0 [Address 000616] CM0 System clock select bit 0 : XIN-XOUT
Figure 3.7.3. Set-up procedure of controlling power using wait mode (2)
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Controlling Power Applications
INT0 interrupt
Timer B0 interrupt
Store the registers
Store the registers
[F_WIT] = 0
Counting clock
Restore the registers REIT instruction
Restore the registers REIT instruction
Figure 3.7.4. Set-up procedure of controlling power using wait mode (3)
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Controlling Power Applications
[MEMO]
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Chapter 4
Interrupt
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt 4.1 Overview of Interrupt 4.1.1 Type of Interrupts
Figure 4.1.1 lists the types of interrupts.
Software
Interrupt
Special
Hardware
Peripheral I/O (Note)
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Figure 4.1.1. Classification of interrupts
• Maskable interrupt : • Non-maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level.
364
Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction
________
Reset DBC Watchdog timer Single step Address matched
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Interrupt
4.1.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB • BRK interrupt A BRK interrupt occurs when executing the BRK instruction. • INT interrupt An INT interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
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Interrupt 4.1.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. • Reset ____________ Reset occurs if an “L” is input to the RESET pin. ________ • DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. • Watchdog timer interrupt Generated by the watchdog timer. • Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed. • Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. For address match interrupt, see 2.9 Address match Interrupt. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INI instruction uses. Peripheral I/O interrupts are maskable interrupts. • Key-input interrupt ___ A key-input interrupt occurs if an “L” is input to the KI pin. • A-D conversion interrupt This is an interrupt that the A-D converter generates. • UART0 and UART1 transmission interrupt These are interrupts that the serial I/O transmission generates. • UART0 and UART1 reception interrupt These are interrupts that the serial I/O reception generates. • Timer A0 interrupt This is an interrupt that timer A generates. • Timer B0 interrupt and timer B1 interrupt These are interrupts that timer B generates. • Timer X0 interrupt through timer X2 interrupt ________ ________ • INT0 interrupt and INT1 interrupt ______ ______ An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
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Interrupt
4.1.4 Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. • Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 4.1.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 4.1.1. Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instruction Overflow BRK instruction Address match Single step (Note) Watchdog timer ________ DBC (Note) Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use
FFFE816 to FFFEB16 FFFEC16 to FFFEF16 FFFF016 to FFFF316 FFFF416 to FFFF716 Do not use FFFF816 to FFFFB16 Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only.
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Interrupt
• Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 4.1.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Table 4.1.2. Interrupts assigned to the variable vector tables and addresses of vector tables
Software interrupt number Software interrupt number 0 Vector table address
Address (L) to address (H)
Interrupt source BRK instruction
Remarks Cannot be masked by I flag
+0 to +3 (Note)
Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14
+44 to +47 (Note) +48 to +51 (Note) +52 to +55 (Note) +56 to +59 (Note) Key input interrupt A-D
Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 to Software interrupt number 63
+68 to +71 (Note) +72 to +75 (Note) +76 to +79 (Note) +80 to +83 (Note) +84 to +87 (Note) +88 to +91 (Note) +92 to +95 (Note) +96 to +99 (Note) +100 to +103 (Note) +104 to +107 (Note) +108 to +111 (Note) +112 to +115 (Note) +116 to +119 (Note) +120 to +123 (Note) +124 to +127 (Note) +128 to +131 (Note) to +252 to +255 (Note)
UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer X0 Timer X1 Timer X2
Timer B0 Timer B1
INT0 INT1
Software interrupt
Cannot be masked by I flag
Note : Address relative to address in interrupt table register (INTB).
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Interrupt
4.2 Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Table 4.2.1 shows the memory map of the interrupt control registers, and Table 4.2.2 shows the interrupt control registers.
004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16
Key input interrupt control register(KUPIC) A-D conversion interrupt control register (ADIC)
UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control regster(S1TIC) UART1 receive interrupt control register(S1RIC) Timer A0 interrupt control register (TA0IC) Timer X0 interrupt control register (TX0IC) Timer X1 interrupt control register (TX1IC) Timer X2 interrupt control register (TX2IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC)
Table 4.2.1. Memory map of the interrupt control registers
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Interrupt
Interrupt control register (Note 2)
Symbol KUPIC ADIC SiTIC(i=0, 1) SiRIC(i=0, 1) TAiIC(i=0) TXiIC(i=0 to 2) TBiIC(i=0, 1) Address 004D16 004E16 005116, 005316 005216, 005416 005516 005616 to 005816 005A16, 005B16 When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7
R
W
ILVL1
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested 1 : Interrupt requested
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts.
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol INTiIC(i=0, 1)
Address 005D16, 005E16
When reset XX00X0002
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Always set to “0”
R
W
ILVL1
ILVL2
IR
Interrupt request bit
(Note 1)
POL
Polarity select bit
Reserved bit Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts.
Figure 4.2.2. Interrupt control registers
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Interrupt
4.2.1 Interrupt Enable Flag
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. The content is changed when the I flag is changed causes the acceptance of the interrupt request in the following timing: • When changing the I flag using the REIT instruction, the acceptance of the interrupt takes effect as the REIT instruction is executed. • When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the acceptance of the interrupt is effective as the next instruction is executed.
When changed by REIT instruction Interrupt request generated Determination whether or not to accept interrupt request Time Previous instruction REIT Interrupt sequence
(If I flag is changed from 0 to 1 by REIT instruction)
When changed by FCLR, FSET, POPC, or LDC instruction Interrupt request generated Determination whether or not to accept interrupt request Time Previous instruction FSET I Next instruction Interrupt sequence
(If I flag is changed from 0 to 1 by FSET instruction)
Figure 4.2.3. The timing of reflecting the change in the I flag to the interrupt
4.2.2 Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
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Interrupt 4.2.3 Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 4.2.1 shows the settings of interrupt priority levels and Table 4.2.2 shows the interrupt levels enabled, according to the consist of the IPL. The following are conditions under which an interrupt is accepted: · interrupt enable flag (I flag) = 1 · interrupt request bit = 1 · interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another.
Table 4.2.1. Settings of interrupt priority levels
Table 4.2.2. Interrupt levels enabled according to the contents of the IPL
IPL
IPL2 IPL1 IPL0
Interrupt priority level select bit
b2 b1 b0
Interrupt priority level
Priority order
Enabled interrupt priority levels
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Low
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled
When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt in the following timing: • When changing the IPL using the REIT instruction, the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction. • When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the instruction used. • When changing the interrupt priority level using the MOV or similar instruction, the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in the instruction used.
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Interrupt
4.2.4 Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
Example 2:
INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
Example 3:
INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
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Interrupt 4.3 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note 1) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user.
4.3.1 Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 4.3.1 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged Time
Instruction (a)
Interrupt sequence (b)
Instruction in interrupt routine
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed.
Figure 4.3.1. Interrupt response time
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Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 4.3.1. Table 4.3.1. Time required for executing the interrupt sequence
Interrupt vector address Even Even Odd (Note 2) Odd (Note 2) Stack pointer (SP) value Even Odd Even Odd
________
16-Bit bus, without wait 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1)
8-Bit bus, without wait 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1)
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK Address bus Data bus R W The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Address 0000
Interrupt information
Indeterminate Indeterminate Indeterminate
SP-2 SP-2 contents
SP-4 SP-4 contents
vec vec contents
vec+2 vec+2 contents
PC
Figure 4.3.2. Time required for executing the interrupt sequence
4.3.2 Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 4.3.2 is set in the IPL.
Table 4.3.2. Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels Watchdog timer Reset Other Value set in the IPL 7 0 Not changed
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Interrupt
4.3.3 Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 4.3.3 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address MSB
Stack area LSB
Address MSB
Stack area LSB [SP] New stack pointer value
m–4 m–3 m–2 m–1 m m+1 Content of previous stack Content of previous stack [SP] Stack pointer value before interrupt occurs
m–4 m–3 m–2 m–1 m m+1
Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH)
Content of previous stack Content of previous stack
Stack status before interrupt request is acknowledged
Stack status after interrupt request is acknowledged
Figure 4.3.3. State of stack before and after acceptance of interrupt request
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The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 4.3.4 shows the operation of the saving registers. Note: Stack pointer indicated by U flag.
(1) Stack pointer (SP) contains even number
Address Stack area Sequence in which order registers are saved
[SP] – 5 (Odd) [SP] – 4 (Even) [SP] – 3 (Odd) [SP] – 2 (Even) [SP] – 1 (Odd) [SP] (Even) Finished saving registers in two operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) (1) Saved simultaneously, all 16 bits (2) Saved simultaneously, all 16 bits
(2) Stack pointer (SP) contains odd number
Address Stack area Sequence in which order registers are saved
[SP] – 5 (Even) [SP] – 4 (Odd) [SP] – 3 (Even) [SP] – 2 (Odd) [SP] – 1 (Even) [SP] (Odd) Finished saving registers in four operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH)
(3) (4) (1) (2)
Saved simultaneously, all 8 bits
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 4.3.4. Operation of saving registers
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Interrupt 4.4 Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
4.5 Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted (see Figure 4.5.1). Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 4.5.2 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.
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INT1 Timer B0 Timer X2 Timer X0 INT0 Timer B1 Timer X1 UART1 reception UART0 reception A-D conversion Timer A0 UART1 transmission UART0 transmission Key input interrupt
High
Priority of peripheral I/O interrupts (if priority levels are same)
Low
Figure 4.5.1. Maskable interrupts priorities (peripheral I/O interrupts)
________
Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 4.5.2. Hardware interrupts priorities
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Interrupt 4.6 Multiple Interrupts
The state when control branched to an interrupt routine is described below: · The interrupt enable flag (I flag) is set to “0” (the interrupt is disabled). · The interrupt request bit of the accepted interrupt is set to “0”. · The processor interrupt priority level (IPL) is assigned to the same interrupt priority level as assigned to the accepted interrupt. Setting the interrupt enable flag (I flag) to “1” within an interrupt routine allows an interrupt request assigned a priority higher than the IPL to be accepted. Figure 4.6.1 shows the scheme of multiple interrupts. An interrupt request that is not accepted because of low priority will be held. If the condition following is met when the REIT instruction returns the IPL and the interrupt priority is determined, then the interrupt request being held is accepted. Interrupt priority level of the interrupt request being held > Returned the IPL
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Interrupt request generated
Nesting
Main routine
I=0
IPL = 0
Time
Reset
Interrupt 1
I=1
Interrupt priority level = 3
Interrupt 1
I=0
IPL = 3
Interrupt 2
Multiple interrupts
I=1
Interrupt priority level = 5
Interrupt 2
I=0
IPL = 5
Interrupt 3
REIT
Interrupt priority level = 2
I=1
IPL = 3 Interrupt 3
REIT
I=1
Not acknowledged because of low interrupt priority
IPL = 0
Main routine instructions are not executed.
Interrupt 3
I=0
IPL = 2
REIT
I=1
IPL = 0
I : Interrupt enable flag IPL : Processor interrupt priority level : Automatically executed. : Be sure to set in software.
Figure 4.6.1. Multiple interrupts
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Interrupt 4.7 Precautions for Interrupts (1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset, generating any interrupts is prohibited.
(3) External interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 _______ and INT1 regardless of the CPU operation clock. ________ _______ • When the polarity of the INT0 and INT1 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 4.7.1 shows the procedure for ______ changing the INT interrupt generate factor.
Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt enable flag to “1” (Enable interrupt)
______
Figure 4.7.1. Switching condition of INT interrupt request
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(4) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
Example 2:
INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
Example 3:
INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
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Interrupt [MEMO]
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Chapter 5
Standard Characteristics
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Standard Characteristics 5.1 Standard DC Characteristics
The standard characteristics given in this section are examples of M30201M4-XXXFP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.
5.1.1 Standard Ports Characteristics
Figures 5.1.1 through 5.1.6 show the standard ports characteristics.
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Standard Characteristics
VCC=5V
—30 Ta=—50˚C
IOH [mA]
—20 Ta=95˚C
Ta=25˚C
—10
0
1
2 VOH [V]
3
4
5
Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figure 5.1.1. IOH - VOH standard characteristics of ports P0 to P7 (VCC = 5V)
VCC=5V
30 Ta=—50˚C Ta=25˚C
IOL [mA]
20 Ta=95˚C
10
0
1
2 VOL [V]
3
4
5
Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figure 5.1.2. IOL - VOL standard characteristics of ports P0 to P7 (VCC = 5V)
VCC=5V
80 Ta=25˚C
IOL [mA]
Ta=—50˚C
40
Ta=95˚C
0
1
2 VOL [V]
3
4
5
Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figure 5.1.3. IOL - VOL standard characteristics of port P1 (VCC = 5V, HIGH POWER)
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Standard Characteristics
VCC=3V
—20
IOH [mA]
Ta=—50˚C —10 Ta=95˚C Ta=25˚C
0
1 VOH [V]
2
3
Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figure 5.1.4. IOH - VOH standard characteristics of ports P0 to P7 (VCC = 3V)
VCC=3V
20
IOL [mA]
Ta=25˚C 10
Ta=—50˚C
Ta=95˚C
0
1 VOL [V]
2
3
Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figure 5.1.5. IOL - VOL standard characteristics of ports P0 to P7 (VCC = 3V)
VCC=3V
40
IOL [mA]
Ta=—50˚C Ta=25˚C 20 Ta=95˚C
0
1 VOL [V]
2
3
Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figure 5.1.6. IOL - VOL standard characteristics of port P1 (VCC = 3V, HIGH POWER)
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Standard Characteristics 5.1.2 Standard Characteristics of ICC-f(XIN)
Figures 5.1.7 and 5.1.8 show the standard characteristics of ICC-f(XIN). The standard characteristics given in this section are examples of M30201M4-XXXFP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.
VCC=5V
• Measurement conditions : VCC = 5V, Ta = 25˚C, f(XIN) : square waveform input, single-chip mode When access to ROM and RAM without wait • Register setting condition XIN - XOUT drive capacity select bit = “1” (HIGH) Main clock (XIN - XOUT) stop bit = “0” (On) 16
14
XIN / 1 XIN / 2 XIN / 4
12
XIN / 8 XIN / 16
ICC [mA]
10
8
6
4
2
0 0
2
4
6 f(XIN) [MHz]
8
10
Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figures 5.1.7. Standard characteristics of ICC-f(XIN) (VCC = 5V)
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Standard Characteristics
• Measurement conditions : VCC = 3V, Ta = 25˚C, f(XIN) : square waveform input, single-chip mode When access to ROM and RAM without wait • Register setting condition XIN - XOUT drive capacity select bit = “1” (HIGH) = “0” (On) Main clock (XIN - XOUT) stop bit 8
VCC=3V
7
XIN / 1 XIN / 2 XIN / 4
6 XIN / 8 XIN / 16
ICC [mA]
5
4
3
2
1
0 0 2 4 5 6 8 10 f(XIN) [MHz] Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figures 5.1.8. Standard characteristics of ICC-f(XIN) (VCC = 3V)
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Standard Characteristics 5.2 Standard Characteristics of Pull-Up Resistor
Figure 5.2.1 shows an example of the standard characteristics of the pull-up resistor. The standard characteristics given in this section are examples of M30201M4-XXXFP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.
Ta=25°C
—150
II [µA]
VCC=5V —100
—50
VCC=3V
0
1
2 VI [V]
3
4
5
Note: Data described here are characteristic examples. The data values are not guaranteed.
Figure 5.2.1. Example of the standard characteristics of the pull-up resistor
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Standard Characteristics (Flash memory version) 5.3 Standard DC Characteristics (Flash memory version)
The standard characteristics given in this section are examples of M30201F6FP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.
5.3.1 Standard Ports Characteristics
Figures 5.3.1 through 5.3.3 show the standard ports characteristics.
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Standard Characteristics (Flash memory version)
VCC=5V
—30
Ta=—50˚C Ta=25˚C
IOH [mA]
—20
Ta=95˚C
—10
0
1
2 VOH [V]
3
4
5
Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figure 5.3.1. IOH - VOH standard characteristics of ports P0 to P7 (VCC = 5V)
VCC=5V
Ta=—50˚C 30 Ta=25˚C
IOL [mA]
20
Ta=95˚C
10
0
1
2 VOL [V]
3
4
5
Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figure 5.3.2. IOL - VOL standard characteristics of ports P0 to P7 (VCC = 5V)
VCC=5V
Ta=—50˚C Ta=25˚C 80
IOL [mA]
Ta=95˚C 40
0
1
2 VOL [V]
3
4
5
Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figure 5.3.3. IOL - VOL standard characteristics of port P1 (VCC = 5V, HIGH POWER)
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Standard Characteristics (Flash memory version) 5.3.2 Standard Characteristics of ICC-f(XIN)
Figure 5.3.4 shows the Characteristics of ICC-f(XIN). The standard characteristics given in this section are examples of M30201F6FP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.
VCC=5V
• Measurement conditions : VCC = 5V, Ta = 25˚C, f(XIN) : square waveform input, single-chip mode When access to ROM and RAM without wait • Register setting condition XIN - XOUT drive capacity select bit = “1” (HIGH) = “0” (On) Main clock (XIN - XOUT) stop bit 16
14
XIN / 1 XIN / 2
12
XIN / 4 XIN / 8 XIN / 16
ICC [mA]
10
8
6
4
2
0 2 4 6 f(XIN) [MHz] 8 10
Note: Data described here are characteristic examples. The data values are not guaranteed. Refer to section “Electrical characteristics” for rated values.
Figures 5.3.4. Standard characteristics of ICC-f(XIN) (VCC = 5V)
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Standard Characteristics (Flash memory version) 5.4 Standard Characteristics of Pull-Up Resistor
Figure 5.4.1 shows an example of the standard characteristics of the pull-up resistor. The standard characteristics given in this section are examples of M30201F6FP. The contents of these examples cannot be guaranteed. For standardized values, see “Electric characteristics”.
Ta=25°C
—150
II [µA]
VCC=5V —100
—50
0
1
2 VI [V]
3
4
5
Note: Data described here are characteristic examples. The data values are not guaranteed.
Figure 5.4.1. Example of the standard characteristics of the pull-up resistor
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Appendix 1 Check Sheet
Appendix 1 Check Sheet
The following check sheet was created based on items which had been the source of problems in the past. We recommend you refer to the check sheet when troubleshooting.
Checks regarding register initial settings
Has the initial setting been made in the interrupt stack pointer (ISP) at the top of the program? Has the initial setting been made in the user stack pointer (USP)? (Only if using the USP) Does the USP overlap the ISP area? (Only if using the USP) Is interrupt enabled after setting the ISP and USP? Is the top address of the variable interrupt vector table set in the interrupt table register (INTB)? Is interrupt enabled after setting the INTB? Has the initial setting been made in the frame base register (FB)? (Only if using the FB) Has the initial setting been made in the stack base register (SB)? (Only if using the SB)
Checks regarding the internal memory
Does the RAM capacity used in the program exceed the RAM capacity of the microcomputer? Does the ROM capacity used in the program exceed the ROM capacity of the microcomputer?
Checks regarding the protect register
Is writing enabled in the protect register (address 000A16) before writing in the system clock control register (addresses 000616 and 000716)? Is writing enabled in the protect register before writing in the processor mode register (addresses 000416 and 000516)? Is writing enabled in the protect register before writing in the port P4 direction register (address 03EA16)? Is writing effectuated in the port P4 direction register by the next instruction after writing is enabled in the protect register? Does not an interrupt generate between the instruction writing is enabled in the protect register and the instruction writing in the port P4 direction register?
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Appendix 1 Check Sheet
Checks regarding the timer
Is the timer started after a value is set in the timer register?
Checks regarding low power consumption
In the low power consumption mode, does not current flow from Vref when the Vref connection bit (bit 5 in address 03D716) is set? Is not voltage level of port floating in the low power consumption mode?
Checks regarding Interrupt
When rewrite the interrupt register, do so at a point that does not generate the interruput request?
Checks regarding low voltage
When using at low voltage, have you checked recommended operating conditions and changed the wait bit (address 000516, bit 7) to “1”?
Checks regarding A-D converter
Have you selected other than fAD (no dividing) for øAD when using the A-D converter at VCC = 2.7 4.0V? Have you selected no sample & hold function when using the A-D converter at VCC = 2.7 - 4.0V? Have you selected 8-bit mode when using the A-D converter at VCC = 2.7 - 4.0V?
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M30201 Group
Appendix 2 Hexadecimal instruction CODE table
D7 to D4 D3 to D0 0000 0 0000 0 BRK 0001 1 AND.B:S R0H,R0L 0001 1 MOV.B:S R0L,dsp:8[SB] 0010 2 MOV.B:S R0L,dsp:8[FB] 0011 3 MOV.B:S R0L,abs16 0100 4 NOP AND.B:S dsp:8[SB],R0L AND.B:S dsp:8[FB],R0L AND.B:S abs16,R0L AND.B:S R0L,R0H 0101 5 MOV.B:S R0H,dsp:8[SB] 0110 6 MOV.B:S R0H,dsp:8[FB] 0111 7 MOV.B:S R0H,abs16 1000 8 MOV.B:S R0H,R0L 1001 9 MOV.B:S dsp:8[SB],R0L 1010 A MOV.B:S dsp:8[FB],R0L 1011 B MOV.B:S abs16,R0L 1100 C MOV.B:S R0L,R0H 1101 D MOV.B:S dsp:8[SB],R0H 1110 E MOV.B:S dsp:8[FB],R0H 1111 F MOV.B:S abs16,R0H AND.B:S dsp:8[SB],R0H AND.B:S dsp:8[FB],R0H AND.B:S abs16,R0H OR.B:S R0H,R0L OR.B:S dsp:8[SB],R0L OR.B:S dsp:8[FB],R0L OR.B:S abs16,R0L OR.B:S R0L,R0H OR.B:S dsp:8[SB],R0H OR.B:S dsp:8[FB],R0H OR.B:S abs16,R0H 0010 2 ADD.B:S R0H,R0L ADD.B:S dsp:8[SB],R0L ADD.B:S dsp:8[FB],R0L ADD.B:S abs16,R0L ADD.B:S R0L,R0H ADD.B:S dsp:8[SB],R0H ADD.B:S dsp:8[FB],R0H ADD.B:S abs16,R0H SUB.B:S R0H,R0L SUB.B:S 0011 3 MOV.B:S R0H,A0 MOV.B:S dsp:8[SB],A0 MOV.B:S dsp:8[FB],A0 MOV.B:S abs16,A0 MOV.B:S R0Çk,A1 MOV.B:S dsp:8[SB],A1 MOV.B:S dsp:8[FB],A1 MOV.B:S abs16,A1 CMP.B:S R0H,R0L CMP.B:S 0100 4 BCLR:S 0,11[SB] BCLR:S 1,11[SB] BCLR:S 2,11[SB] BCLR:S 3,11[SB] BCLR:S 4,11[SB] BCLR:S 5,11[SB] BCLR:S 6,11[SB] BCLR:S 7,11[SB] BSET:S 0,11[SB] BSET:S 1,11[SB] BSET:S 2,11[SB] BSET:S 3,11[SB] BSET:S 4,11[SB] BSET:S 5,11[SB] BSET:S 6,11[SB] BSET:S 7,11[SB]
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
0101 5 BNOT:S 0,11[SB] BNOT:S 1,11[SB] BNOT:S 2,11[SB] BNOT:S 3,11[SB] BNOT:S 4,11[SB] BNOT:S 5,11[SB] BNOT:S 6,11[SB] BNOT:S 7,11[SB] BTST:S 0,11[SB] BTST:S 1,11[SB] BTST:S 2,11[SB] BTST:S 3,11[SB] BTST:S 4,11[SB] BTST:S 5,11[SB] BTST:S 6,11[SB] BTST:S 7,11[SB]
0110 6 JMP.S label JMP.S label JMP.S label JMP.S label JMP.S label JMP.S label JMP.S label JMP.S label JGEU/C label JGTU label JEQ/Z label JN label JLTU/NC label JLEU label JNE/JNZ label JPZ label
0111 7 MULU.B src,dest MULU.W src,dest MOV.B:G src,dest MOV.W:G src,dest CODE_74
CODE_75
CODE_76
CODE_77
MUL.B src,dest MUL.W src,dest CODE_7A
dsp:8[SB],R0L dsp:8[SB],R0L SUB.B:S dsp:8[FB],R0L SUB.B:S abs16,R0L SUB.B:S R0L,R0H SUB.B:S CMP.B:S dsp:8[FB],R0L CMP.B:S abs16,R0L CMP.B:S R0L,R0H CMP.B:S
CODE_7B
CODE_7C
CODE_7D
dsp:8[SB],R0H dsp:8[SB],R0H SUB.B:S CMP.B:S
CODE_7E
dsp:8[FB],R0H dsp:8[FB],R0H SUB.B:S abs16,R0H CMP.B:S abs16,R0H
The next instruction is arranged in each CODE. CODE_74:STE,MOV,PUSH,NEG,ROT,NOT,LDE,POP,SHL,SHA CODE_75:STE,MOV,PUSH,NEG,ROT,NOT,LDE,POP,SHL,SHA CODE_76:TST,XOR,AND,OR,ADD,SUB,ADC,SBB,CMP,DIVX,ROLC,RORC,DIVU,DIV,ADCF,ABS CODE_77:TST,XOR,AND,OR,ADD,SUB,ADC,SBB,CMP,DIVX,ROLC,RORC,DIVU,DIV,ADCF,ABS CODE_7A:XCHG,LDC CODE_7B:XCHG,STC CODE_7C:MOV Dir ,MULU,MUL,EXTS,STC,DIVU,DIV,PUSH,DIVX,DADD,DSUB,DADC,DSBB,SMOVF,SMOVB,SSTR,ADD,LDCTX,RMPA,ENTER CODE_7D:JMPI,JSRI,MULU,MUL,PUSHA,LDIPL,ADD,J Cnd ,BMCnd ,DIVU,DIV,PUSH,DIVX,DADD,DSUB,DADC,DSBB,SMOVF,SMOVB,SSTR,
STCTX,RMPA,EXITD,WAIT
CODE_7E:BTSTC,BM Cnd ,BNTST,BAND,BNAND,BOR,BNOR,BCLR,BSET,BNOT,BTST,BXOR,BNXOR CODE_EB:SHL,FSET,FCLR,MOVA,LDC,SHA,PUSHC,POPC,INT
398
Mitsubishi microcomputers
M30201 Group
Appendix 2 Hexadecimal instruction CODE table
D7 to D4 D3 to D0 0000 0 1000 8 TST.B src,dest 0001 1 TST.W src,dest 0010 2 PUSH.B:S R0L 0011 3 ADD.B:S #IMM8,R0H 0100 4 ADD.B:S #IMM8,R0L 0101 5 ADD.B:S 1001 9 AND.B:G src,dest AND.W:G src,dest POP.B:S R0L AND.B:S #IMM8,R0H AND.B:S #IMM8,R0L AND.B:S 1010 A ADD.B:G src,dest ADD.W:G src,dest MOV.W:S #IMM,A0 INC.B R0H INC.B R0L INC.B dsp:8[SB] INC.B dsp:8[FB] INC.B abs16 SUB.B:G src,dest SUB.W:G src,dest MOV.W:S #IMM,A1 DEC.B R0H DEC.B R0L DEC.B dsp:8[SB] DEC.B dsp:8[FB] DEC.B abs16 1011 B ADC.B src,dest ADC.w src,dest INC.W A0 MOV.B:Z #0,R0H MOV.B:Z #0,R0L MOV.B:Z #0,dsp:8[SB] MOV.B:Z #0,dsp:8[FB] MOV.B:Z #0,abs16 SBB.B src,dest SBB.W src,dest INC.W A1 NOT.B:S R0H NOT.B:S R0L NOT.B:S dsp:8[SB] NOT.B:S dsp:8[FB] NOT.B:S abs16 1100 C CMP.B:G src,dest CMP.W:G src,dest PUSH.W:S A0 MOV.B:S #IMM8,R0H MOV.B:S #IMM8,R0L MOV.B:S #IMM8,dsp:8[SB] MOV.B:S #IMM8,dsp:8[FB] MOV.B:S #IMM8,abs16 ADD.B:Q #IMM,dest ADD.W:Q #IMM,dest PUSH.W:S A1 STZ #IMM8,R0H STZ #IMM8,R0L STZ
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1101 D CMP.B:Q #IMM,dest CMP.W:Q #IMM,dest POP.W:S A0 STNZ #IMM8,R0H STNZ #IMM8,R0L STNZ #IMM8,dsp:8[SB] STNZ #IMM8,dsp:8[FB] STNZ #IMM8,abs16 MOV.B:Q #IMM,dest MOV.W:Q #IMM,dest POP.W:S A1 STZX #IMM8,#IMM8,R0H STZX #IMM8,#IMM8,R0L STZX
1110 E ROT.B #IMM,dest ROT.W #IMM,dest MOV.B:S #IMM,A0 CMP.B:S #IMM8,R0H CMP.B:S #IMM8,R0L CMP.B:S #IMM8,dsp:8[SB] CMP.B:S #IMM8,dsp:8[FB] CMP.B:S #IMM8,abs16 SHL.B #IMM,dest SHL.W #IMM,dest MOV.B:S #IMM,A1 CODE_EB
1111 F SHA.B #IMM,dest SHA.W #IMM,dest DEC.W A0 RTS
JMP.W label JSR.W label INTO
#IMM8,dsp:8[SB] #IMM8,dsp:8[SB] 0110 6 ADD.B:S AND.B:S
#IMM8,dsp:8[FB] #IMM8,dsp:8[FB] 0111 7 ADD.B:S #IMM8,abs16 1000 8 XOR.B src,dest 1001 9 XOR.W src,dest 1010 A PUSH.B:S R0H 1011 B SUB.B:S #IMM8,R0H 1100 C SUB.B:S #IMM8,R0L 1101 D SUB.B:S AND.B:S #IMM8,abs16 OR.B:G src,dest OR.W:G src,dest POP.B:S R0H OR.B:S #IMM8,R0H OR.B:S #IMM8,R0L OR.B:S
ADJNZ.B #IMM,dest,label ADJNZ.W #IMM,dest,label DEC.W A1 REIT
PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8
JMP.A label JSR.A label JMP.B label UND
#IMM8,dsp:8[SB] #IMM8,dsp:8[SB] 1110 E SUB.B:S OR.B:S
#IMM8,dsp:8[SB] #IMM8,#IMM8,dsp:8[SB] STZ STZX
#IMM8,dsp:8[FB] #IMM8,dsp:8[FB] 1111 F SUB.B:S #IMM8,abs16 OR.B:S #IMM8,abs16
#IMM8,dsp:8[FB] #IMM8,#IMM8,dsp:8[FB] STZ #IMM8,abs16 STZX #IMM8,#IMM8,abs16
399
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision History
Version Contents for change Pages 2, 6 internal interrupt 9 ->13 Pages 2, 6 2.7 to 5.5V (f(XIN)=7MHz with software one-wait):mask ROM version ->2.7 to 5.5V (f(XIN)=3.5MHz ):mask ROM version Page 6 Power consumption 18mA (f(XIN)=7MHz with software one-wait, VCC=3V) ->11mA (f(XIN)=3.5MHz , VCC=3V) Page 7 M30201M2-XXXSP/FP, M30201M2T-XXXSP/FP ->Delete M30201M4T-XXXSP, M30201F6T-XXXSP ->Delete M30201M6-XXXFP, M30201M6T-XXXFP ->Addition Pages 10, 11 Figures 1.7 and 1.8 are partly revised. Page 15 Figure 1.11 is partly revised. Page 17 Figure 1.14 is partly revised (Bit 7 of the processor mode register 1). Wait bit ->Reserved bit Page 18 Software wait Page 21 Figure 1.18 is partly revised (Note 8 is partly revised). Page 22 Figure 1.19 is partly revised (n=0716 : approx. 16.5kHz -> 19.5kHz). Page 34 Figure 1.24 is partly revised (Note 2 is added). Page 50 Figure 1.39 is partly revised. Page 78 Figure 1.72 is partly revised (UARTi transmit/receive mode register). Page 79 Figure 1.73 is partly revised. Page 81 Figure 1.74 is partly revised. Page 86 Figure 1.79 is partly revised. Pages 91 to 97 Figures 1.83 to 1.89 are partly revised. Pages 111 to 114, 119 to 123 Tables 1.36 to 1.39 and 1.56 to 1.71 are partly revised. Page 125 Table 1.74 is partly revised (Boot ROM area 4 K bytes -> 3.5 K bytes) . Page 143 to 169 Standard serial I/O mode 2 is added. Revision date 01.4.12
REV.C
Revision history
M30201 Group User's Manual
400
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Version
Contents for change Page 204 2.2.15 Precaution for Timer A (one-shot timer mode) (3) is partly revised. Page 219 2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode) (3) is partly revised. Page 309 Table 2.7.11 and Table 2.7.12 are partly revised. Page 320 Figure 2.10.3 is partly revised. Page 324 Table 2.11.1 is partly revised. Page 328 Figure 2.11.6 is partly revised. Page 329 2.11.4 Precautions in Power Control (b) is partly revised. Page 355 Figure 3.6.2 is partly revised. Page 359 Figure 3.7.2 is partly revised.
Revision date 01.6.8
REV.C
Revision history
M30201 Group User's Manual
401
MITSUBISHI Single-Chip Microcomputer User's Manual M30201 Group REV.C Mar. First Edition 1999 May. Second Edition 1999 Jun. Third Edition 2001 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©2001 MITSUBISHI ELECTRIC CORPORATION
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