M30290M8-XXXHP

REJ09B0101-0112 16 M16C/29 Group Hardware Manual RENESAS MCU M16C FAMILY / M16C/Tiny SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com). Rev. 1.12 Revision Date: Mar.30, 2007 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.  The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied.  The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited.  The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized.  When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems.  The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products. How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section. The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the M16C/29 Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Document Type Description Document Title Document No. M16C/29 Group This hardware Hardware manual Hardware specifications (pin assignments, Hardware Manual manual memory maps, peripheral function specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions. REJ09B0137 Software manual Description of CPU instruction set M16C/60, M16C/20, M16C/Tiny Series Software Manual Available from Renesas Application note Information on using peripheral functions and Technology Web site. application examples Sample programs Information on writing programs in assembly language and C Renesas Product specifications, updates on documents, technical update etc. 2. Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,” “bit,” or “pin” to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin Notation of Numbers The indication “2” is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication “16” is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 112 Hexadecimal: EFA016 Decimal: 1234 (2) 3. Register Notation The symbols and terms used in register diagrams are described below. XXX Register b7 b6 b5 b4 b3 b2 b1 b0 *1 Symbol XXX Address XXX After Reset 0016 0 Bit Symbol XXX0 Bit Name XXX bits b1 b0 Function 1 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX RW RW *2 XXX1 RW (b2) Nothing is assigned. If necessary, set to 0. When read, the content is undefined. *3 RW (b3) Reserved bits Set to 0. *4 XXX4 XXX bits Function varies according to the operating mode. RW XXX5 WO XXX6 0: XXX 1: XXX RW XXX7 XXX bit RO *1 Blank: Set to 0 or 1 according to the application. 0: Set to 0. 1: Set to 1. X: Nothing is assigned. *2 RW: Read and write. RO: Read only. WO: Write only. −: Nothing is assigned. *3 • Reserved bit Reserved bit. Set to specified value. *4 • Nothing is assigned Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0. • Do not set to a value Operation is not guaranteed when a value is set. • Function varies according to the operating mode. The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes. 4. List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter Equipment bus Input/Output Infrared Data Association Least Significant Bit Most Significant Bit Non-Connection Phase Locked Loop Pulse Width Modulation Special Function Registers Subscriber Identity Module Universal Asynchronous Receiver/Transmitter Voltage Controlled Oscillator All trademarks and registered trademarks are the property of their respective owners. IEBus is a registered trademark of NEC Electronics Corporation. Table of Contents Quick Reference to Pages Classified by Address _____________________ B-1 1. Overview ____________________________________________________ 1 1.1 Features ........................................................................................................................... 1 1.1.1 Applications ................................................................................................................ 1 1.1.2 Specifications ............................................................................................................. 2 1.2 Block Diagram .................................................................................................................. 4 1.3 Product List ....................................................................................................................... 6 1.4 Pin Assignments ............................................................................................................. 12 1.5 Pin Description ............................................................................................................... 18 2. Central Processing Unit (CPU) __________________________________ 21 2.1 Data Registers (R0, R1, R2 and R3) .............................................................................. 21 2.2 Address Registers (A0 and A1) ...................................................................................... 21 2.3 Frame Base Register (FB) .............................................................................................. 22 2.4 Interrupt Table Register (INTB) ....................................................................................... 22 2.5 Program Counter (PC) .................................................................................................... 22 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .......................................... 22 2.7 Static Base Register (SB) ............................................................................................... 22 2.8 Flag Register (FLG) ........................................................................................................ 22 2.8.1 Carry Flag (C Flag) .................................................................................................. 22 2.8.2 Debug Flag (D Flag) ................................................................................................. 22 2.8.3 Zero Flag (Z Flag) ................................................................................................... 22 2.8.4 Sign Flag (S Flag) .................................................................................................... 22 2.8.5 Register Bank Select Flag (B Flag) .......................................................................... 22 2.8.6 Overflow Flag (O Flag) ............................................................................................. 22 2.8.7 Interrupt Enable Flag (I Flag) ................................................................................... 22 2.8.8 Stack Pointer Select Flag (U Flag) ........................................................................... 22 2.8.9 Processor Interrupt Priority Level (IPL) .................................................................... 22 2.8.10 Reserved Area ....................................................................................................... 22 3. Memory ____________________________________________________ 23 4. Special Function Registers (SFRs) _______________________________ 24 A-1 5. Resets _____________________________________________________ 35 5.1 Hardware Reset .............................................................................................................. 35 5.1.1 Hardware Reset 1 .................................................................................................... 35 5.1.2 Brown-Out Detection Reset (Hardware Reset 2) ..................................................... 35 5.2 Software Reset ............................................................................................................... 36 5.3 Watchdog Timer Reset ................................................................................................... 36 5.4 Oscillation Stop Detection Reset .................................................................................... 36 5.5 Voltage Detection Circuit ................................................................................................ 38 5.5.1 Low Voltage Detection Interrupt ............................................................................... 41 5.5.2. Limitations on Stop Mode ........................................................................................ 43 5.5.3. Limitations on WAIT Instruction ............................................................................... 43 6. Processor Mode _____________________________________________ 44 7. Clock Generation Circuit _______________________________________ 47 7.1 Main Clock ...................................................................................................................... 54 7.2 Sub Clock ....................................................................................................................... 55 7.3 On-chip Oscillator Clock ................................................................................................. 56 7.4 PLL Clock ....................................................................................................................... 56 7.5 CPU Clock and Peripheral Function Clock ..................................................................... 58 7.5.1 CPU Clock ................................................................................................................ 58 7.5.2 Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32, fCAN0) ...... 58 7.5.3 ClockOutput Function ............................................................................................... 58 7.6 Power Control ................................................................................................................. 59 7.6.1 Normal Operation Mode ........................................................................................... 59 7.6.2 Wait Mode ................................................................................................................ 60 7.6.3 Stop Mode ............................................................................................................... 62 7.7 System Clock Protective Function .................................................................................. 66 7.8 Oscillation Stop and Re-oscillation Detect Function ....................................................... 66 7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset)........................... 67 7.8.2 Operation When CM27 bit = 1 (Oscillation Stop and Re-oscillation Detect Interrupt) . 67 7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function ............................. 68 8. Protection __________________________________________________ 69 A-2 9. Interrupts ___________________________________________________ 70 9.1 Type of Interrupts ............................................................................................................ 70 9.1.1 Software Interrupts ................................................................................................... 71 9.1.2 Hardware Interrupts ................................................................................................. 72 9.2 Interrupts and Interrupt Vector ........................................................................................ 73 9.2.1 Fixed Vector Tables .................................................................................................. 73 9.2.2 Relocatable Vector Tables ........................................................................................ 74 9.3 Interrupt Control .............................................................................................................. 75 9.3.1 I Flag ........................................................................................................................ 78 9.3.2 IR Bit ........................................................................................................................ 78 9.3.3 ILVL2 to ILVL0 Bits and IPL...................................................................................... 78 9.4 Interrupt Sequence ......................................................................................................... 79 9.4.1 Interrupt Response Time .......................................................................................... 80 9.4.2 Variation of IPL when Interrupt Request is Accepted ............................................... 80 9.4.3 Saving Registers ...................................................................................................... 81 9.4.4 Returning from an Interrupt Routine ......................................................................... 83 9.5 Interrupt Priority .............................................................................................................. 83 9.5.1 Interrupt Priority Resolution Circuit .......................................................................... 83 9.6 INT Interrupt ................................................................................................................... 85 ______ 9.7 NMI Interrupt ................................................................................................................... 86 9.8 Key Input Interrupt .......................................................................................................... 86 9.9 CAN0 Wake-up Interrupt ................................................................................................ 87 9.10 Address Match Interrupt ............................................................................................... 87 ______ 10. Watchdog Timer ____________________________________________ 89 10.1 Count Source Protective Mode ..................................................................................... 90 11. DMAC ____________________________________________________ 91 11.1 Transfer Cycles ............................................................................................................ 96 11.1.1 Effect of Source and Destination Addresses ......................................................... 96 11.1.2 Effect of Software Wait .......................................................................................... 96 11.2. DMA Transfer Cycles ................................................................................................... 98 11.3 DMA Enable .................................................................................................................. 99 11.4 DMA Request ................................................................................................................ 99 11.5 Channel Priority and DMA Transfer Timing ................................................................ 100 A-3 12. Timers ___________________________________________________ 101 12.1 Timer A ...................................................................................................................... 103 12.1.1 Timer Mode .......................................................................................................... 106 12.1.2 Event Counter Mode ............................................................................................ 107 12.1.3 One-shot Timer Mode .......................................................................................... 112 12.1.4 Pulse Width Modulation (PWM) Mode ................................................................. 114 12.2 Timer B ...................................................................................................................... 117 12.2.1 Timer Mode ......................................................................................................... 119 12.2.2 Event Counter Mode ............................................................................................ 120 12.2.3 Pulse Period and Pulse Width Measurement Mode ............................................ 121 12.2.4 A/D Trigger Mode ................................................................................................ 123 12.3 Three-phase Motor Control Timer Function ................................................................ 125 12.3.1 Position-Data-Retain Function ............................................................................. 136 12.3.2 Three-phase/Port Output Switch Function ........................................................... 138 13. Timer S __________________________________________________ 140 13.1 Base Timer ................................................................................................................. 151 13.1.1 Base Timer Reset Register(G1BTRR) ................................................................. 155 13.2 Interrupt Operation ..................................................................................................... 156 13.3 DMA Support .............................................................................................................. 156 13.4 Time Measurement Function ...................................................................................... 157 13.5 Waveform Generating Function .................................................................................. 161 13.5.1 Single-Phase Waveform Output Mode ................................................................. 162 13.5.2 Phase-Delayed Waveform Output Mode.............................................................. 164 13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode ................................. 166 13.6 I/O Port Function Select ............................................................................................. 168 13.6.1 INPC17 Alternate Input Pin Selection .................................................................. 169 ________ 13.6.2 Digital Debounce Function for Pin P17/INT5/INPC17 .......................................... 169 14. Serial I/O _________________________________________________ 170 14.1 UARTi (i=0 to 2) .......................................................................................................... 170 14.1.1 Clock Synchronous serial I/O Mode ..................................................................... 180 14.1.2 Clock Asynchronous Serial I/O (UART) Mode ..................................................... 188 14.1.3 Special Mode 1 (I2C bus mode)(UART2) ............................................................. 196 14.1.4 Special Mode 2 (UART2) ..................................................................................... 206 14.1.5 Special Mode 3 (IEBus mode)(UART2) .............................................................. 210 14.1.6 Special Mode 4 (SIM Mode) (UART2)................................................................. 212 A-4 14.2 SI/O3 and SI/O4 ........................................................................................................ 217 14.2.2 CLK Polarity Selection ........................................................................................ 220 14.2.1 SI/Oi Operation Timing ........................................................................................ 220 14.2.3 Functions for Setting an SOUTi Initial Value ....................................................... 221 15. A/D Converter _____________________________________________ 222 15.1 Operating Modes ........................................................................................................ 228 15.1.1 One-Shot Mode .................................................................................................... 228 15.1.2 Repeat mode ........................................................................................................ 230 15.1.3 Single Sweep Mode ............................................................................................ 232 15.1.4 Repeat Sweep Mode 0 ......................................................................................... 234 15.1.5 Repeat Sweep Mode 1 ......................................................................................... 236 15.1.6 Simultaneous Sample Sweep Mode .................................................................... 238 15.1.7 Delayed Trigger Mode 0 ....................................................................................... 241 15.1.8 Delayed Trigger Mode 1 ....................................................................................... 247 15.2 Resolution Select Function ......................................................................................... 253 15.3 Sample and Hold ........................................................................................................ 253 15.4 Power Consumption Reducing Function .................................................................... 253 15.5 Output Impedance of Sensor under A/D Conversion ................................................. 254 16. Multi-master I2C bus Interface _________________________________ 255 16.1 I2C0 Data Shift Register (S00 register) ....................................................................... 264 16.2 I2C0 Address Register (S0D0 register) ....................................................................... 264 16.3 I2C0 Clock Control Register (S20 register) ................................................................ 265 16.3.1 Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4) ..................................... 265 16.3.2 Bit 5: SCL Mode Specification Bit (FAST MODE) .............................................. 265 16.3.3 Bit 6: ACK Bit (ACKBIT) ...................................................................................... 265 16.3.4 Bit 7: ACK Clock Bit (ACK-CLK) .......................................................................... 265 16.4 I2C0 Control Register 0 (S1D0) ................................................................................. 267 16.4.1 Bits 0 to 2: Bit Counter (BC0–BC2) ..................................................................... 267 16.4.2 Bit 3: I2C Interface Enable Bit (ES0) .................................................................... 267 16.4.3 Bit 4: Data Format Select Bit (ALS) ..................................................................... 267 16.4.4 Bit 6: I2C bus Interface Reset Bit (IHR) ............................................................... 267 16.4.5 Bit 7: I2C bus Interface Pin Input Level Select Bit (TISS) .................................... 268 16.5 I2C0 Status Register (S10 register) ........................................................................... 269 16.5.1 Bit 0: Last Receive Bit (LRB) ............................................................................... 269 16.5.2 Bit 1: General Call Detection Flag (ADR0) .......................................................... 269 A-5 16.5.3 Bit 2: Slave Address Comparison Flag (AAS) ..................................................... 269 16.5.4 Bit 3: Arbitration Lost Detection Flag (AL) ........................................................... 269 16.5.5 Bit 4: I2C bus Interface Interrupt Request Bit (PIN) ............................................. 270 16.5.6 Bit 5: Bus Busy Flag (BB) .................................................................................... 270 16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: TRX) ....... 271 16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST) ................ 271 16.6 I2C0 Control Register 1 (S3D0 register) .................................................................... 272 16.6.1 Bit 0 : Interrupt Enable Bit by STOP Condition (SIM ) ......................................... 272 16.6.2 Bit 1: Interrupt Enable Bit at the Completion of Data Receive (WIT) .................. 272 16.6.3 Bits 2,3 : Port Function Select Bits PED, PEC .................................................... 273 16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM .................... 274 16.6.5 Bits 6,7 : I2C System Clock Select Bits ICK0, ICK1 ............................................ 274 16.6.6 Address Receive in STOP/WAIT Mode ............................................................... 274 16.7 I2C0 Control Register 2 (S4D0 Register) ................................................................... 275 16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) .......................................... 276 16.7.2 Bit1: Time-Out Detection Flag (TOF ).................................................................. 276 16.7.3 Bit2: Time-Out Detection Period Select Bit (TOSEL) .......................................... 276 16.7.4 Bits 3,4,5: I2C System Clock Select Bits (ICK2-4) ............................................... 276 16.7.5 Bit7: STOP Condition Detection Interrupt Request Bit (SCPIN).......................... 276 16.8 I2C0 START/STOP Condition Control Register (S2D0 Register) ............................... 277 16.8.1 Bit0-Bit4: START/STOP Condition Setting Bits (SSC0-SSC4) ............................ 277 16.8.2 Bit5: SCL/SDA Interrupt Pin Polarity Select Bit (SIP) .......................................... 277 16.8.3 Bit6 : SCL/SDA Interrupt Pin Select Bit (SIS) ...................................................... 277 16.8.4 Bit7: START/STOP Condition Generation Select Bit (STSPSEL) ....................... 277 16.9 START Condition Generation Method ....................................................................... 278 16.10 START Condition Duplicate Protect Function ........................................................... 279 16.11 STOP Condition Generation Method ........................................................................ 279 16.12 START/STOP Condition Detect Operation ............................................................... 281 16.13 Address Data Communication ................................................................................. 282 16.13.1 Example of Master Transmit ............................................................................. 282 16.13.2 Example of Slave Receive ................................................................................ 283 16.14 Precautions ............................................................................................................... 284 17. CAN Module ______________________________________________ 287 17.1 CAN Module-Related Registers ................................................................................. 288 17.1.1 CAN0 Message Box ............................................................................................. 289 17.1.2 Acceptance Mask Registers ................................................................................. 291 17.1.3 CAN SFR Registers ............................................................................................. 292 A-6 17.2 Operating Modes ........................................................................................................ 300 17.2.1 CAN Reset/Initialization Mode ............................................................................. 300 17.2.2 CAN Operating Mode ........................................................................................... 301 17.2.3 CAN Sleep Mode ................................................................................................. 301 17.2.4 CAN Interface Sleep Mode .................................................................................. 302 17.2.5 Bus Off State ........................................................................................................ 302 17.3 Configuration of the CAN Module System Clock ........................................................ 303 17.3.1 Bit Timing Configuration ....................................................................................... 303 17.3.2 Bit-rate .................................................................................................................. 304 17.4 Acceptance Filtering Function and Masking Function ................................................ 305 17.5 Acceptance Filter Support Unit (ASU) ........................................................................ 306 17.6 BasicCAN Mode ......................................................................................................... 307 17.7 Return from Bus off Function ...................................................................................... 308 17.8 Time Stamp Counter and Time Stamp Function ......................................................... 308 17.9 Listen-Only Mode ....................................................................................................... 308 17.10 Reception and Transmission .................................................................................... 309 17.10.1 Reception ........................................................................................................... 310 17.10.2 Transmission ...................................................................................................... 311 17.11 CAN Interrupts .......................................................................................................... 312 18. CRC Calculation Circuit _____________________________________ 313 18.1 CRC Snoop ................................................................................................................ 313 19. Programmable I/O Ports _____________________________________ 316 19.1 Port Pi Direction Register (PDi Register, i = 0 to 3, 6 to 10) ....................................... 316 19.2 Port Pi Register (Pi Register, i = 0 to 3, 6 to 10) ......................................................... 316 19.3 Pull-up Control Register 0 to 2 (PUR0 to PUR2 Registers) ........................................ 316 19.4 Port Control Register (PCR Register) ......................................................................... 316 19.5 Pin Assignment Control Register (PACR) ................................................................... 317 19.6 Digital Debounce Function ......................................................................................... 317 20. Flash Memory Version ______________________________________ 330 20.1 Flash Memory Performance ....................................................................................... 330 20.1.1 Boot Mode ........................................................................................................... 331 20.2 Memory Map ............................................................................................................... 332 20.3 Functions To Prevent Flash Memory from Rewriting .................................................. 335 20.3.1 ROM Code Protect Function ................................................................................ 335 20.3.2 ID Code Check Function ...................................................................................... 335 A-7 20.4 CPU Rewrite Mode ..................................................................................................... 337 20.4.1 EW Mode 0 .......................................................................................................... 338 20.4.2 EW Mode 1 .......................................................................................................... 338 20.5 Register Description ................................................................................................... 339 20.5.1 Flash Memory Control Register 0 (FMR0) ........................................................... 339 20.5.2 Flash Memory Control Register 1 (FMR1) ........................................................... 340 20.5.3 Flash Memory Control Register 4 (FMR4) ........................................................... 340 20.6 Precautions in CPU Rewrite Mode ............................................................................. 345 20.6.1 Operation Speed .................................................................................................. 345 20.6.2 Prohibited Instructions .......................................................................................... 345 20.6.3 Interrupts .............................................................................................................. 345 20.6.4 How to Access ...................................................................................................... 345 20.6.5 Writing in the User ROM Area .............................................................................. 345 20.6.6 DMA Transfer ....................................................................................................... 346 20.6.7 Writing Command and Data ................................................................................. 346 20.6.8 Wait Mode ............................................................................................................ 346 20.6.9 Stop Mode ............................................................................................................ 346 20.6.10 Low Power Consumption Mode and On-Chip Oscillator-Low Power Consumption Mode ... 346 20.7 Software Commands .................................................................................................. 347 20.7.1 Read Array Command (FF16)............................................................................... 347 20.7.2 Read Status Register Command (7016) ............................................................... 347 20.7.3 Clear Status Register Command (5016) ............................................................... 347 20.7.4 Program Command (4016) ................................................................................... 348 20.7.5 Block Erase .......................................................................................................... 349 20.8 Status Register ........................................................................................................... 351 20.8.1 Sequence Status (SR7 and FMR00 Bits ) ............................................................ 351 20.8.2 Erase Status (SR5 and FMR07 Bits) ................................................................... 351 20.8.3 Program Status (SR4 and FMR06 Bits) ............................................................... 351 20.8.4 Full Status Check ................................................................................................. 352 20.9 Standard Serial I/O Mode ........................................................................................... 354 20.9.1 ID Code Check Function ...................................................................................... 354 20.9.2 Example of Circuit Application in Standard Serial I/O Mode ................................ 358 20.10 Parallel I/O Mode ...................................................................................................... 360 20.10.1 ROM Code Protect Function .............................................................................. 360 20.11 CAN I/O Mode .......................................................................................................... 361 20.11.1 ID code check function ....................................................................................... 361 20.11.2 Example of Circuit Application in CAN I/O Mode ................................................ 365 A-8 21. Electrical Characteristics _____________________________________ 366 21.1 Normal version ........................................................................................................... 366 21.2 T version ..................................................................................................................... 387 21.3 V Version .................................................................................................................... 408 22. Usage Notes ______________________________________________ 421 22.1 SFRs ........................................................................................................................... 421 22.1.1 For 80-Pin Package ............................................................................................. 421 22.1.2 For 64-Pin Package ............................................................................................. 421 22.1.3 Register Setting .................................................................................................... 421 22.2 Clock Generation Circuit ............................................................................................. 422 22.2.1 PLL Frequency Synthesizer ................................................................................. 422 22.2.2 Power Control ...................................................................................................... 423 22.3 Protection ................................................................................................................... 425 22.4 Interrupts .................................................................................................................... 426 22.4.1 Reading Address 0000016 ..................................................................................................... 426 22.4.2 Setting the SP ...................................................................................................... 426 _______ 22.4.3 NMI Interrupt ....................................................................................................... 426 22.4.4 Changing the Interrupt Generate Factor .............................................................. 426 ______ 22.4.5 INT Interrupt ......................................................................................................... 427 22.4.6 Rewrite the Interrupt Control Register .................................................................. 428 22.4.7 Watchdog Timer Interrupt ..................................................................................... 428 22.5 DMAC ......................................................................................................................... 429 22.5.1 Write to DMAE Bit in DMiCON Register ............................................................... 429 22.6 Timers ......................................................................................................................... 430 22.6.1 Timer A ................................................................................................................. 430 22.6.2 Timer B ................................................................................................................. 433 22.6.3 Three-phase Motor Control Timer Function ......................................................... 434 22.7 Timer S ....................................................................................................................... 435 22.7.1 Rewrite the G1IR Register .................................................................................. 435 22.7.2 Rewrite the ICOCiIC Register ............................................................................. 436 22.7.3 Waveform Generating Function .......................................................................... 436 22.7.4 IC/OC Base Timer Interrupt .................................................................................. 436 22.8 Serial I/O ..................................................................................................................... 437 22.8.1 Clock-Synchronous Serial I/O .............................................................................. 437 22.8.2 UART Mode.......................................................................................................... 438 22.8.3 SI/O3, SI/O4 ......................................................................................................... 438 A-9 22.9 A/D Converter ............................................................................................................. 439 22.10 Multi-Master I2C bus Interface ................................................................................. 441 22.10.1 Writing to the S00 Register ................................................................................ 441 22.10.2 AL Flag ............................................................................................................... 441 22.11 CAN Module ............................................................................................................. 442 22.11.1 Reading C0STR Register ................................................................................... 442 22.11.2 CAN Transceiver in Boot Mode .......................................................................... 444 22.12 Programmable I/O Ports ........................................................................................... 445 22.13 Electric Characteristic Differences Between Mask ROM .......................................... 446 22.14 Mask ROM Version ................................................................................................... 447 22.14.1 Internal ROM Area ............................................................................................. 447 22.14.2 Reserved Bit ....................................................................................................... 447 22.15 Flash Memory Version .............................................................................................. 448 22.15.1 Functions to Inhibit Rewriting Flash Memory Rewrite ........................................ 448 22.15.2 Stop Mode .......................................................................................................... 448 22.15.3 Wait Mode .......................................................................................................... 448 22.15.4 Low PowerDissipation Mode, On-Chip Oscillator Low Power Dissipation Mode .. 448 22.15.5 Writing Command and Data ............................................................................... 448 22.15.6 Program Command ............................................................................................ 448 22.15.7 Operation Speed ................................................................................................ 448 22.15.8 Instructions Inhibited Against Use ...................................................................... 448 22.15.9 Interrupts ............................................................................................................ 449 22.15.10 How to Access .................................................................................................. 449 22.15.11 Writing in the User ROM Area .......................................................................... 449 22.15.12 DMA Transfer ................................................................................................... 449 22.15.13 Regarding Programming/Erasure Times and Execution Time ......................... 449 22.15.14 Definition of Programming/Erasure Times ....................................................... 450 22.15.15 Flash Memory Version Electrical Characteristics 10,000 E/W cycle products ( Normal: U7, U9; T-ver./V-ver.: U7) ............................................. 450 22.15.16 Boot Mode ........................................................................................................ 450 22.16 Noise ........................................................................................................................ 451 22.17 Instruction for a Device Use ..................................................................................... 452 A-10 Appendix 1. Package Dimensions ________________________________ 453 Appendix 2. Functional Comparison _______________________________ 454 Appendix 2.1 Difference between M16C/28 Group and M16C/29 Group (Normal-ver.) .... 454 Appendix 2.2 Difference between M16C/28 and M16C/29 Group (T-ver./V-ver.) ............... 455 Register Index ________________________________________________ 456 A-11 Quick Reference to Pages Classified by Address Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Register Symbol Page Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 Register CAN0 wakeup interrupt control register CAN0 successful reception interrupt control register Symbol Page 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register Oscillation stop detection register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 PM0 PM1 CM0 CM1 AIER PRCR CM2 WDTS WDC RMAD0 44 44 49 50 88 69 51 90 90 88 Address match interrupt register 1 RMAD1 88 Voltage detection register 1 Voltage detection register 2 PLL control register 0 Processor mode register 2 Low voltage detection interrupt register DMA0 source pointer VCR1 VCR2 PLC0 PM2 D4INT SAR0 41 41 53 52 42 95 DMA0 destination pointer DAR0 95 C01WKIC C0RECIC CAN0 successful transmission interrupt control regiser C0TRMIC INT3 interrupt control register INT3IC IC/OC 0 interrupt control register ICOC0IC IC/OC 1 interrupt control register, ICOC1IC I2C bus interface interrupt control register IICIC IC/OC base timer interrupt control register, BTIC SCLSDA interrupt control register SCLDAIC SI/O4 interrupt control register, S4IC INT5 interrupt control register INT5IC SI/O3 interrupt control register, S3IC INT4 interrupt control register INT4IC UART2 Bus collision detection interrupt control register BCNIC DMA0 interrupt control register DM0IC DMA1 interrupt control register DM1IC CAN0 error interrupt control register C01ERRIC A/D conversion interrupt control register ADIC Key input interrupt control register KUPIC UART2 transmit interrupt control register S2TIC UART2 receive interrupt control register S2RIC UART0 transmit interrupt control register S0TIC UART0 receive interrupt control register S0RIC UART1 transmit interrupt control register S1TIC UART1 receive interrupt control register S1RIC Timer A0 interrupt control register TA0IC Timer A1 interrupt control register TA1IC Timer A2 interrupt control register TA2IC Timer A3 interrupt control register TA3IC Timer A4 interrupt control register TA4IC Timer B0 interrupt control register TB0IC Timer B1 interrupt control register TB1IC Timer B2 interrupt control register TB2IC INT0 interrupt control register INT0IC INT1 interrupt control register INT1IC INT2 interrupt control register INT2IC DMA0 transfer counter TCR0 95 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 CAN0 message box 0: Identifier/DLC 289 DMA0 control register DM0CON 94 CAN 0 message box 0: Data field 289 DMA1 source pointer SAR1 95 CAN0 message box 0: Time stamp 289 DMA1 destination pointer DAR1 95 DMA1 transfer counter TCR1 95 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 CAN0 message box 1: Identifier/DLC 289 DMA1 control register DM1CON 94 CAN 0 message box 1: Data field 289 Note: The blank areas are reserved and cannot be accessed by users. CAN0 message box 1: Time stamp 289 B-1 Quick Reference to Pages Classified by Address Address 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16 Register Symbol Page Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 Register Symbol Page CAN0 message box 2: Identifier/DLC 289 CAN0 message box 6: Identifier/DLC 289 CAN0 message box 2: Data field 289 CAN0 message box 6: Data field 289 CAN0 message box 2: time stamp 289 CAN0 message box 6: time stamp 289 CAN0 message box 3: Identifier/DLC 289 CAN0 message box 7: Identifier/DLC 289 CAN0 message box 3: Data field 289 CAN0 message box 7: Data field 289 CAN0 message box 3: time stamp 289 CAN0 message box 7: time stamp 289 CAN0 message box 4: Identifier/DLC 289 CAN0 message box 8: Identifier/DLC 289 CAN0 message box 4: Data field 289 CAN0 message box 8: Data field 289 CAN0 message box 4: time stamp 289 CAN0 message box 8: time stamp 289 CAN0 message box 5: Identifier/DLC 289 CAN0 message box 9: Identifier/DLC 289 CAN0 message box 5: Data field 289 CAN0 message box 9: Data field 289 CAN0 message box 5: time stamp 289 CAN0 message box 9: time stamp 289 Note: The blank areas are reserved and cannot be accessed by users. B-2 Quick Reference to Pages Classified by Address Address 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A16 011B16 011C16 011D16 011E16 011F16 012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 012A16 012B16 012C16 012D16 012E16 012F16 013016 013116 013216 013316 013416 013516 013616 013716 013816 013916 013A16 013B16 013C16 013D16 013E16 013F16 Register Symbol Page Address 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A16 014B16 014C16 014D16 014E16 014F16 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A16 015B16 015C16 015D16 015E16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A16 016B16 016C16 016D16 016E16 016F16 017016 017116 017216 017316 017416 017516 017616 017716 017816 017916 017A16 017B16 017C16 017D16 017E16 017F16 Register Symbol Page CAN0 message box 10: Identifer/DLC 289 CAN0 message box 14: Identifier/DLC 289 CAN0 message box 10: Data field 289 CAN0 message box 14: Data field 289 CAN0 message box 10: time stamp 289 CAN0 message box 14: time stamp 289 CAN0 message box 11: Identifier/DLC 289 CAN0 message box 15: Identifier/DLC 289 CAN0 message box 11: Data field 289 CAN0 message box 15: Data field 289 CAN0 message box 11: time stamp 289 CAN0 message box 15: time stamp 289 CAN0 message box 12: Identifier/DLC 289 CAN0 global mask register C0GMR 291 CAN0 message box 12: Data field 289 CAN0 local mask A register C0LMAR 291 CAN0 message box 12: time stamp 289 CAN0 local mask B register C0LMBR 291 CAN0 message box 13: Identifier/DLC 289 CAN0 message box 13: Data field 289 CAN0 message box 13: time stamp 289 Note: The blank areas are reserved and cannot be accessed by users. B-3 Quick Reference to Pages Classified by Address Address 018016 018116 018216 018316 018416 018516 018616 Register Symbol Page Address 024016 024116 024216 024316 024416 024516 024616 024716 024816 024916 Register Symbol Page CAN0 acceptance filter support register C0AFS 299 01B016 01B116 01B216 01B316 01B416 01B516 01B616 01B716 01B816 01B916 01BA16 01BB16 01BC16 024A16 024C16 024D16 Flash memory control register 4 Flash memory control register 1 Flash memory control register 0 (Note 2) (Note 2) (Note 2) FMR4 FMR1 FMR0 342 341 341 024E16 024F16 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 020016 020116 020216 020316 020416 020516 020616 020716 020816 020916 020A16 020B16 020C16 020D16 020E16 020F16 021016 021116 021216 021316 021416 021516 021616 021716 021816 021916 021A16 021B16 021C16 021D16 021E16 021F16 021016 CAN0 message control register 0 CAN0 message control register 1 CAN0 message control register 2 CAN0 message control register 3 CAN0 message control register 4 CAN0 message control register 5 CAN0 message control register 6 CAN0 message control register 7 CAN0 message control register 8 CAN0 message control register 9 CAN0 message control register 10 CAN0 message control register 11 CAN0 message control register 12 CAN0 message control register 13 CAN0 message control register 14 CAN0 message control register 15 CAN0 control register CAN0 status register CAN0 slot status register CAN 0 interrupt control register CAN0 extended ID register CAN0 configuration register CAN0 receive error count register CAN0 transmit error count register CAN0 time stamp register C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0CTLR C0STR C0SSTR C0ICR C0IDR C0CONR C0RECR C0TECR C0TSR 292 292 292 292 292 292 292 292 292 292 292 292 292 292 292 292 293 294 295 296 296 297 298 298 299 Three-phase protect control register 0n-chip oscillator control register Pin assignment control register Peripheral clock select register CAN0 clock select register TPRC ROCR PACR PCLKR CCLKR 139 50 177, 326 52 53 025B16 025C16 025D16 025E16 025F16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 I2C0 data shift register I2C0 address register I2C0 control register 0 I2C0 clock control register I2C0 start/stop condition control register I2C0 control register 1 I2C0 control register 2 I2C0 status register S00 S0D0 S1D0 S20 S2D0 S3D0 S4D0 S10 258 257 259 258 263 261 262 260 02FE16 02FF16 02FE16 02FF16 Note 1: The blank areas are reserved and cannot be accessed by users. Note 2: This register is included in the flash memory version. B-4 Quick Reference to Pages Classified by Address Address 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 Register TM, WG register 0 TM, WG register 1 TM, WG register 2 TM, WG register 3 TM, WG register 4 TM, WG register 5 TM, WG register 6 TM, WG register 7 WG control register 0 WG control register 1 WG control register 2 WG control register 3 WG control register 4 WG control register 5 WG control register 6 WG control register 7 TM control register 0 TM control register 1 TM control register 2 TM control register 3 TM control register 4 TM control register 5 TM control register 6 TM control register 7 Base timer register Base timer control register 0 Base timer control register 1 TM prescale register 6 TM prescale register 7 Function enable register Function select register Base timer reset register Divider register Symbol G1TM0, G1PO0 G1TM1, G1PO1 G1TM2, G1PO2 G1TM3, G1PO3 G1TM4, G1PO4 G1TM5, G1PO5 G1TM6, G1PO6 G1TM7, G1PO7 Page 146,147 146,147 146,147 146,147 146,147 146,147 146,147 146,147 Address 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 Register Symbol Page Timer A1-1 register Timer A2-1 register Timer A4-1 register Three-phase PWM control register 0 Three-phase PWM control register 1 Three-phase output buffer register 0 Three-phase output buffer register 1 Dead time timer Position-data-retain function contol register TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 PDRF 130 130 130 127 128 129 129 129 129 137 034D16 Timer B2 interrupt occurrence frequency set counter G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1BTRR G1DV 146 146 146 146 146 146 146 146 145 145 145 145 145 145 145 145 142 142 143 145 145 148 148 144 143 Port function control register PFCR 139 Interrupt request cause select register 2 Interrupt request cause select register SI/O3 transmit/receive register SI/O3 control register SI/O3 bit rate generator SI/O4 transmit/receive register SI/O4 control register SI/O4 bit rate generator IFSR2A IFSR S3TRR S3C S3BRG S4TRR S4C S4BRG 77 77, 85 218 218 218 218 218 218 Interrupt request register Interrupt enable register 0 Interrupt enable register 1 G1IR G1IE0 G1IE1 149 150 150 UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate generator UART2 transmit buffer register U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB 179 179 178 178 175 174 174 176 177 174 037C16 UART2 transmit/receive control register 0 NMI digital debounce register P17 digital debounce register NDDR P17DDR 327 327 037D16 UART2 transmit/receive control register 1 037E16 037F16 UART2 receive buffer register Note : The blank areas are reserved and cannot be accessed by users. B-5 Quick Reference to Pages Classified by Address Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 Register Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Timer B2 special mode register UART0 bit rate generator UART0 transmit/receive mode register Symbol TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON Page 104, 118, 132 Address 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 Register A/D register 0 A/D register 1 A/D register 2 A/D register 3 A/D register 4 A/D register 5 A/D register 6 A/D register 7 Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Page 226 226 226 226 226 226 226 226 105,118 105 105,132 104 104 104 104 104 104 118 118 118 103 133 133 103 133 117 117 133 131 175 174 174 176 177 174 175 174 174 176 177 174 176 A/D trigger control register A/D convert status register 0 A/D control register 2 A/D control register 0 A/D control register 1 ADTRGCON ADSTAT0 ADCON2 ADCON0 ADCON1 225 226 224 224 224 UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 bit rate generator UART1 transmit/receive mode register Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register P0 P1 PD0 PD1 P2 P3 PD2 PD3 324 324 323 323 324 324 323 323 UART1 transmit buffer register 03AC16 UART1 transmit/receive control register 0 03AD16 UART1 transmit/receive control register 1 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 UART1 receive buffer register UART transmit/receive control register 2 Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register Port P10 direction register P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10 324 324 323 323 324 324 323 323 324 323 CRC snoop address register CRC mode register DMA0 request cause select register DMA1 request cause select register CRC data register CRC input register CRCSAR CRCMR DM0SL DM1SL CRCD CRCIN 314 314 93 94 314 314 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Pull-up control register 0 Pull-up control register 1 Pull-up control register 2 Port control register PUR0 PUR1 PUR2 PCR 325 325 325 326 Note : The blank areas are reserved and cannot be accessed by users. B-6 M16C/29 Group 1. Overview 1.1 Features SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The M16C/29 Group of single-chip control MCU incorporates the M16C/60 series CPU core, employing the high-performance silicon gate CMOS technology and sophisticated instructions for a high level of efficiency. The M16C/29 Group is housed in 64-pin and 80-pin plastic molded LQFP packages. These singlechip MCUs operate using sophisticated instructions featuring a high level of instruction efficiency. This MCU is capable of executing instructions at high speed and it has one CAN module, makes it suitable for control of cars and LAN system of FA. In addition, the CPU core boasts a multiplier and DMAC for highspeed processing to make adequate for office automation, communication devices, and other high-speed processing applications. 1.1.1 Applications Automotive body, car audio, LAN system of FA, etc. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 1 of 458 M16C/29 Group 1. Overview 1.1.2 Specifications Table 1.1 lists performance overview of M16C/29 Group 80-pin package. Table 1.2 lists performance overview of M16C/29 Group 64-pin package. Table 1.1 Performance Overview of M16C/29 Group (T-ver./V-ver.) (80-Pin Package) Item Performance CPU Number of basic instructions 91 instructions Shortest instruction 50 ns (f(BCLK) = 20MHZ, VCC = 3.0 to 5.5 V) (Normal-ver./T-ver.) excution time 100 ns(f(BCLK) = 10MHZ, VCC = 2.7 to 5.5 V) (Normal-ver.) 50 ns (f(BCLK) = 20MHZ, VCC = 4.2 to 5.5 V, -40 to 105°C) (V-ver.) 62.5 ns (f(BCLK) = 16MHZ, VCC = 4.2 to 5.5 V, -40 to 125°C) (V-ver.) Operation mode Single chip mode Address space 1 Mbyte Memory capacity ROM/RAM: See Tables 1.3 to 1.5 Peripheral Port Input/Output: 71 lines Function Multifunction timer TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels Three-phase Motor Control Timer TimerS (Input Capture/Output Compare): 16 bit base timer x 1 channel (Input/Output x 8 channels) Serial I/O 2 channels (UART, clock synchronous serial I/O) 1 channel (UART, clock synchronous serial I/O, I2C bus, or IEbus(1)) 2 channels (Clock synchronous serial I/O) 1 channel (Multi- master I2C bus) A/D converter 10 bits x 27 channels DMAC 2 channels CRC calculation circuit 2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable CAN module 1 channel, supporting CAN 2.0B specification Watchdog timer 15 bits x 1 channel (with prescaler) Interrupt 29 internal and 8 external sources, 4 software sources, interrupt priority level: 7 Clock generation circuit 4 circuits • Main clock  (These circuits contain a built-in feedback  • Sub-clock  resistor) • On-chip oscillator(main-clock oscillation stop detect function) • PLL frequency synthesizer Oscillation stop detect Function Main clock oscillation stop, re-oscillation detect function Voltage detection circuit Available (Normal-ver.) / Not available (T-ver., V-ver.) Electrical Power supply voltage VCC = 3.0 to 5.5 V (f(BCLK) = 20 MHz) (Normal-ver.) CharactVCC = 2.7 to 5.5 V (f(BCLK) = 10 MHz) eristics VCC = 3.0 to 5.5 V (T-ver.) VCC = 4.2 to 5.5 V (V-ver.) Power consumption 18 mA (VCC = 5 V, f(BCLK) = 20 MHz) 25 µA (f(XCIN) = 32 kHz on RAM) 3 µA (VCC = 5 V, f(XCIN) = 32 kHz, in wait mode) 0.8 µA (VCC = 5 V, in stop mode) Flash Program/erase supply voltage 2.7 to 5.5 V (Normal-ver.), 3.0 to 5.5V (T-ver.), 4.2 to 5.5 V (V-ver.) memory Program and erase endurance 100 times (all space) or 1,000 times (blocks 0 to 5)/ 10,000 times (blocks A and B(2)) Operating ambient temperature -20 to 85°C/-40 to 85°C(2) (Normal-ver.) -40 to 85°C (T-ver.), -40 to 125°C (V-ver.) Package 80-pin plastic mold LQFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. Refer to Table 1.6 to Table 1.8 Product code. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 2 of 458 M16C/29 Group 1. Overview Table 1.2 Performance Overview of M16C/29 Group (64-Pin Package) Item Performance CPU Number of basic instructions 91 instructions Shortest instruction 50 ns (f(BCLK) = 20MHZ, VCC = 3.0 to 5.5 V) (Normal-ver./T-ver.) excution time 100 ns(f(BCLK) = 10MHZ, VCC = 2.7 to 5.5 V) (Normal-ver.) 50 ns (f(BCLK) = 20MHZ, VCC = 4.2 to 5.5 V, -40 to 105°C) (V-ver.) 62.5 ns (f(BCLK) = 16MHZ, VCC = 4.2 to 5.5 V, -40 to 125°C) (V-ver.) Operation mode Single chip mode Address space 1 Mbytes Memory capacity ROM/RAM: See Tables 1.3 to 1.5 Peripheral Port Input/Output: 55 lines function Multifunction timer TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels Three-phase Motor Control Timer TimerS (Input Capture/Output Compare): 16bit base timer x 1 channel (Input/Output x 8 channels ) Serial I/O 2 channels (UART, clock synchronous serial I/O) 1 channel (UART, clock synchronous serial I/O, I2C bus, or IEbus(1) ) 1 channel (Clock synchronous serial I/O) 1 channel (Multi-master I2C bus) A/D converter 10 bits x 16 channels DMAC 2 channels CRC calculation circuit 2 polynomial (CRC-CCITT and CRC-16) with MSB/LSB selectable CAN module 1 channel, supporting CAN 2.0B specification Watchdog timer 15 bits x 1 channel (with prescaler) Interrupt 28 internal and 8 external sources, 4 software sources, interrupt priority level: 7 Clock generation circuit 4 circuits • Main clock  (These circuits contain a built-in feedback  • Sub-clock  resistor) • On-chip oscillator(main-clock oscillation stop detect function) • PLL frequency synthesizer Oscillation stop detect function Main clock oscillation stop, re-oscillation detect function Voltage detection circuit Available (Normal-ver.) / Not available (T-ver., V-ver.) Electrical Power supply voltage VCC = 3.0 to 5.5 V (f(BCLK) = 20 MHz) (Normal-ver.) CharactVCC = 2.7 to 5.5 V (f(BCLK) = 10 MHz) eristics VCC = 3.0 to 5.5 V (T-ver.) VCC = 4.2 to 5.5 V (V-ver.) Power consumption 18 mA (VCC = 5 V, f(BCLK) = 20 MHz) 25 µA (f(XCIN) = 32 kHz on RAM) 3 µA (VCC = 5 V, f(XCIN) = 32 kHz, in wait mode) 0.8 µA (VCC = 5 V, in stop mode) Flash Program/erase supply voltage 2.7 to 5.5 V (Normal-ver.), 3.0 to 5.5V (T-ver.), 4.2 to 5.5 V (V-ver.) memory Program and erase endurance 100 times (all space) or 1,000 times (blocks 0 to 5)/ 10,000 times (blocks A and B(2)) Operating ambient temperature -20 to 85°C/-40 to 85°C(2) (Normal-ver.) -40 to 85°C (T-ver.), -40 to 125°C (V-ver.) Package 64-pin plastic mold LQFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. Refer to Table 1.6 to Table 1.8 Product code. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 3 of 458 M16C/29 Group 1. Overview 1.2 Block Diagram Figure 1.1 is a block diagram of the M16C/29 Group, 80-pin package. 8 8 8 8 I/O Ports Internal Peripheral Functions Timer (16 bits) Output (Timer A) : 5 Input (Timer B) : 3 3-phase PWM Timer S Input capture/ Output compare Time measurement : 8 channels Waveform generating : 8 channels Port P0 Port P1 Port P2 Port P3 Port P6 8 UART/clock synchronous SI/O (8 bits x 3 channels) Clock synchronous SI/O (8 bits x 2 channels) Multi-master I2C bus CAN module (1 channel) System clock generator XIN-XOUT XCIN-XCOUT On-chip oscillator PLL frequency synthesizer CRC calculation circuit (CCITT, CRC-16) Port P7 8 ( Port P8 ) 8 M16C/60 Series CPU Core R0H R1H R0L R1L SB USP ISP INTB PC FLG Memory ROM(1) RAM(2) Port P9 A/D converter (1 0 b its x 2 7 c h a n n e ls ) R2 R3 7 Watchdog timer (15 bits) DMAC (2 channels) A0 A1 FB Port P10 Multiplier 8 NOTES: 1. The ROM capacity varies depending on each product. 2. The RAM capacity varies depending on each product. Figure 1.1 M16C/29 Group, 80-Pin Block Diagram Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 4 of 458 M16C/29 Group 1. Overview Figure 1.2 is a block diagram of the M16C/29 Group, 64-pin package. 4 3 8 4 I/O Ports Internal Peripheral Functions Timer (16 bits) Output (Timer A) : 5 Input (Timer B) : 3 3-phase PWM Timer S Input capture/ Output compare Time measurement : 8 channels Waveform generating : 8 channels Port P0 Port P1 Port P2 Port P3 Port P6 8 UART/Clock synchronous SI/O (8 bits x 3 channels) Clock synchronous SI/O (8 bits x 1 channel) Multi-master I2C bus CAN module (1 channel) System clock generator XIN-XOUT XCIN-XCOUT On-chip oscillator PLL frequency synthesizer CRC calculation circuit (CRC-CCITT, CRC16) Port P7 Port P8 8 ( ) M16C/60 Series CPU Core R0H R1H R0L R1L SB USP ISP INTB PC FLG Memory ROM(1) 8 A/D converter (10 bits x 16 channels) Watchdog timer (15 bits) DMAC (2 channels) Port P9 R2 R3 RAM(2) 4 A0 A1 FB Port P10 Multiplier 8 NOTES: 1. The ROM capacity varies depending on each product. 2. The RAM capacity varies depending on each product. Figure 1.2 M16C/29 Group, 64-Pin Block Diagram Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 5 of 458 M16C/29 Group 1. Overview 1.3 Product List Tables 1.3 to 1.5 list the M16C/29 Group products and Figure 1.3 shows the type numbers, memory sizes and packages. Tables 1.6 to 1.8 list the product code of flash memory version for M16C/29 Group. Figure 1.4 to Figure 1.6 show the marking diagram of flash memory version for M16C/29 Group. Table 1.3 Product List (1) -Normal Version Type Number M30290FAHP M30290FCHP M30291FAHP M30291FCHP M30290M8-XXXHP M30290MA-XXXHP M30290MC-XXXHP M30291M8-XXXHP M30291MA-XXXHP M30291MC-XXXHP ROM Capacity 96 K + 4 K 128 K + 4 K 96 K + 4 K 128 K + 4 K 64 K 96 K 128 K 64 K 96 K 128 K RAM Capacity 8K 12 K 8K 12 K 4K 8K 12 K 4K 8K 12 K PLQP0064KB-A (64P6Q-A) PLQP0080KB-A (80P6Q-A) Mask ROM U3, U5 Package Type PLQP0080KB-A (80P6Q-A) PLQP0064KB-A (64P6Q-A) As of March, 2007 Remarks Product Code U3, U5, U7, U9 Flash Memory Table 1.4 Product List (2) -T Version Type Number M30290FATHP M30290FCTHP M30291FATHP M30291FCTHP M30290M8T-XXXHP M30290MAT-XXXHP M30290MCT-XXXHP M30291M8T-XXXHP M30291MAT-XXXHP M30291MCT-XXXHP ROM Capacity 96 K + 4 K 128 K + 4 K 96 K + 4 K 128 K + 4 K 64 K 96 K 128 K 64 K 96 K 128 K RAM Capacity 8K 12 K 8K 12 K 4K 8K 12 K 4K 8K 12 K PLQP0064KB-A (64P6Q-A) PLQP0080KB-A (80P6Q-A) Package Type PLQP0080KB-A (80P6Q-A) PLQP0064KB-A (64P6Q-A) As of March, 2007 Remarks Product Code U3, U5, U7, U9 Flash Memory Mask ROM U0 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 6 of 458 M16C/29 Group 1. Overview Table 1.5 Product List (3) -V Version Type Number M30290FAVHP M30290FCVHP M30291FAVHP M30291FCVHP M30290M8V-XXXHP M30290MAV-XXXHP M30290MCV-XXXHP M30291M8V-XXXHP M30291MAV-XXXHP M30291MCV-XXXHP ROM Capacity 96 K + 4 K 128 K + 4 K 96 K + 4 K 128 K + 4 K 64 K 96 K 128 K 64 K 96 K 128 K RAM Capacity 8K 12 K 8K 12 K 4K 8K 12 K 4K 8K 12 K PLQP0064KB-A (64P6Q-A) PLQP0080KB-A (80P6Q-A) Package Type PLQP0080KB-A (80P6Q-A) PLQP0064KB-A (64P6Q-A) As of March, 2007 Remarks Product Code U3, U5, U7, U9 Flash Memory Mask ROM U0 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 7 of 458 M16C/29 Group 1. Overview Type No. M 3 0 2 9 0 F A T H P - U3 Product Code See Tables 1.6 and 1.9 for Normal-ver., Tables 1.7 and 1.10 for T-ver., and Tables 1.8 and 1.11 for V-ver.. Package type: HP = Package PLQP0080KB-A (80P6Q-A) Package PLQP0064KB-A (64P6Q-A) Version Blank: Normal-version T: T-version V: V-version ROM capacity /RAM capacity: 8: (64 K) bytes/4 K bytes A: (96 K+4 K) bytes(1)/8 K bytes C: (128 K+4 K) bytes(1)/12 K bytes NOTE: 1. "+4 K bytes" is needed only in flash memory version. Memory type: M: Mask ROM version F: Flash memory version Pin count 0: 80-pin package 1: 64-pin package M16C/29 Group M16C Family Figure 1.3 Type No., Memory Size, and Package Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 8 of 458 M16C/29 Group 1. Overview -M16C/29 Group, Normal-ver. Internal ROM (Data Space: Blocks A and B) Program and Erase Endurance 100 0 to 60ºC 1,000 10,000 Temperature Range 0 to 60ºC -40 to 85ºC -20 to 85ºC Operating Ambient Temperature -40 to 85ºC -20 to 85ºC -40 to 85ºC -20 to 85ºC Table 1.6 Product Codes of Flash Memory Version Product Code U3 U5 U7 U9 Lead-free Internal ROM (User Program Space: Blocks 0 to 5) Package Program and Erase Endurance 100 Temperature Range Table 1.7 Product Codes of Flash Memory Version Product Code U3 U7 Internal ROM (User Program Space: Blocks 0 to 5) Package Program and Erase Endurance 100 1,000 Temperature Range 0 to 60ºC -M16C/29 Group, T-ver. Internal ROM (Data Space: Blocks A and B) Program and Erase Endurance 100 10,000 Temperature Range -40 to 85ºC Operating Ambient Temperature Lead-free -40 to 85ºC Table 1.8 Product Codes of Flash Memory Version Product Code U3 U7 Internal ROM (User Program Space: Blocks 0 to 5) Package Program and Erase Endurance 100 1,000 Temperature Range 0 to 60ºC -M16C/29 Group, V-ver. Internal ROM (Data Space: Blocks A and B) Program and Erase Endurance 100 10,000 Temperature Range -40 to 125ºC Operating Ambient Temperature -40 to 125ºC Lead-free Table 1.9 Product Codes of Mask ROM Version Product Code U3 U5 Package Operating Ambient Temperature -40 to 85ºC -20 to 85ºC -M16C/29 Group, Normal-ver. Lead-free Table 1.10 Product Code of Mask ROM Version Product Code U0 Package Lead-free Operating Ambient Temperature -40 to 85ºC -M16C/29 Group, T-ver. Table 1.11 Product Code of Mask ROM Version Product Code U0 Package Lead-free Operating Ambient Temperature -40 to 125ºC -M16C/29 Group, V-ver. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 9 of 458 M16C/29 Group 1. Overview (1) Flash Memory Version, PLQP0080KB-A (80P6Q-A), Normal-ver. M16C M30290FAHP A U3 XXXXXXX Product Name: indicates M30290FAHP Chip Version and Product Code: A: indicates chip version The first edition is shown to be blank and continues with A and B. U3: indicates product code (see Table 1.6) Date Code (7 digits): indicates manufacturing management code (2) Flash Memory Version, PLQP0064KB-A (64P6Q-A), Normal-ver. 30291FA A U3 XXXXXXX Product Name: indicates M30291FAHP Chip Version and Product Code: A: indicates chip version The first edition is shown to be blank and continues with A and B. U3: indicates product code (see Table 1.6) Date Code (7 digits): indicates manufacturing management code Figure 1.4 Marking Diagrams of Flash Memory Version - M16C/29 Group Normal-ver. (Top View) (1) Flash Memory Version, PLQP0080KB-A (80P6Q-A), T-ver. M16C M30290FATHP A U3 XXXXXXX Product Name : indicates M30290FATHP Chip Version and Product Code: A : indicates chip version The first edition is shown to be blank and continues with A and B. U3 : indicates product code (see Table 1.7) Date Code (7 digits) : indicates manufacturing management code (2) Flash Memory Version, PLQP0064KB-A (64P6Q-A), T-ver. A U3 M30291FATHP XXXXXXX Chip Version and Product Code: A : indicates chip version The first edition is shown to be blank and continues with A and B. U3 : indicates product code (see Table 1.7) Product Name : indicates M30291FATHP Date Code (7 digits) : indicates manufacturing management code Figure 1.5 Marking Diagrams of Flash Memory Version - M16C/29 Group T-ver. (Top View) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 10 of 458 M16C/29 Group 1. Overview (1) Flash Memory Version, PLQP0080KB-A (80P6Q-A), V-ver. M16C M30290FAVHP A U3 XXXXXXX Product Name: indicates M30290FAVHP Chip Version and Product Code: A: indicates chip version The first edition is shown to be blank and continues with A and B. U3: indicates product code (see Table 1.8) Date Code (7 digits): indicates manufacturing management code (2) Flash Memory Version, PLQP0064KB-A (64P6Q-A), V-ver. A U3 M30291FAVHP XXXXXXX Chip Version and Product Code: A: indicates chip version The first edition is shown to be blank and continues with A and B. U3: indicates product code (see Table 1.8) Product Name: indicates M30291FAVHP Date Code (7 digits): indicates manufacturing management code Figure 1.6 Marking Diagrams of Flash Memory Version - M16C/29 Group V-ver. (Top View) (1) Mask ROM Version, PLQP0080KB-A (80P6Q-A), Normal-ver. M16C M30290MAXXXHP A U5 XXXXXXX Type No. M30290MAHP Chip version and product code XXX : ROM No. A : Chip version and product code(1) The first edition is shown to be blank and continues with A, B and C. U5 : Product code. (Table 1.9) Date code seven digits Manufacturing management code (2) Mask ROM Version, PLQP0064-KB-A (64P6Q-A), Normal-ver. XXXXXXX M30291MAXXXHP A U5 Date code seven digits Manufacturing management code Type No. M30291MAHP Chip version and product code XXX: ROM No. A : Chip version and product code(1) The first edition is shown to be blank and continues with A, B and C. U5 : Product code. (Table 1.9) Figure 1.7 Marking Diagrams of Mask ROM Version - M16C/29 Group Normal-ver. (Top View) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 11 of 458 M16C/29 Group 1. Overview 1.4 Pin Assignments Figures 1.7 and 1.8 show the pin assignments (top view). P17/INT5/INPC17/IDU P20/OUTC10/INPC10/SDAMM P21/OUTC11/INPC11/SCLMM P22/OUTC12/INPC12 P23/OUTC13/INPC13 P24/OUTC14/INPC14 P14 P15/INT3/ADTRG/IDV P16/INT4/IDW P25/OUTC15/INPC15 P26/OUTC16/INPC16 P27/OUTC17/INPC17 P12/AN22 P13/AN23 P60/CTS0/RTS0 P07/AN07 P10/AN20 P11/AN21 P61/CLK0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P62/RxD0 P06/AN06 P05/AN05 P04/AN04 P03/AN03 P02/AN02 P01/AN01 P00/AN00 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/AN27/SIN4 P96/AN26/SOUT4 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 P63/TXD0 P30/CLK3 P31/SIN3 P32/SOUT3 P33 P34 P35 P36 P37 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P70/TXD2/SDA2/TA0OUT/CTS1/RTS1/CTS0/CLKS1 P71/RXD2/SCL2/TA0IN/CLK1 P72/CLK2/TA1OUT/V/RxD1 P73/CTS2/RTS2/TA1IN/V/TxD1 P74/TA2OUT/W P75/TA2IN/W P76/TA3OUT M16C/29 Group (M16C/29) PLQP0080KB-A (80P6Q-A) (top view) 31 30 29 28 27 26 25 24 23 22 21 NOTE: 1.Set bits PACR2 to PACR0 in the PACR register to "0112" before signals are input or output to individual pins after reset. When the PACR register is not set, signals are not input or output for some Figure 1.8 Pin Assignment (Top View) of 80-Pin Package Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 12 of 458 P92/AN32/TB2IN/CRX P91/AN31/TB1IN P90/AN30/TB0IN/CLKOUT CNVss P87/XCIN P86/XCOUT P95/AN25/CLK4 P93/AN24/CTX RESET XOUT VSS XIN VCC P85/NMI/SD P84/INT2/ZP P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN M16C/29 Group 1. Overview Table 1.12 Pin Characteristics for 80-Pin Package Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CLKOUT CNVss XCIN XCOUT RESET XOUT Vss XIN Vcc P 85 P84 P8 3 P 82 P 81 P80 P77 P 76 P 75 P74 P73 P 72 P 71 P 70 P 67 P 66 P 65 P 64 P 37 P 36 P 35 P 34 P 33 P 32 P 31 P 30 P 63 SOUT3 SIN3 CLK3 TXD0 NMI INT2 INT1 INT0 TA4IN / U TA4OUT / U TA3IN TA3OUT TA2IN / W TA2OUT / W TA1IN / V TA1OUT / V TA0IN TA0OUT CTS2 / RTS2 / TXD1 CLK2 / RXD1 RXD2 / SCL2 / CLK1 TXD2 / SDA2 / RTS1 / CTS1 / CTS0 / CLKS1 TXD1 RX D1 CLK1 RTS1 / CTS1/ CTS0 / CLKS1 SD ZP P87 P86 Control Pin Port P95 P 93 P 92 P 91 P90 TB2IN TB1IN TB0IN Interrupt Pin Timer Pin Timer S Pin CLK4 CTX CRX UART/CAN Pin Multi-master I2C bus Pin Analog Pin AN25 AN24 AN32 AN31 AN30 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 13 of 458 M16C/29 Group 1. Overview Table 1.12 Pin Characteristics for 80-Pin Package (continued) Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 AVss 76 77 VREF 78 AVcc 79 80 P97 P96 SIN4 SOUT4 AN27 AN26 P100 AN0 Control Pin Port P62 P61 P60 P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 P107 KI3 P106 KI2 P105 KI1 P104 KI0 P103 P102 P101 AN23 AN22 AN21 AN20 AN07 AN06 AN05 AN04 AN03 AN02 AN01 AN00 AN7 AN6 AN5 AN4 AN3 AN2 AN1 INT5 INT4 INT3 IDU IDW IDV ADTRG OUTC17 / INPC17 OUTC16 / INPC16 OUTC15 / INPC15 OUTC14 / INPC14 OUTC13 / INPC13 OUTC12 / INPC12 OUTC11 / INPC11 OUTC10 / INPC10 INPC17 SCLMM SDAMM Interrupt Pin Timer Pin Timer S Pin UART/CAN Pin RXD0 CLK0 RTS0 / CTS0 Multi-master I2C bus Pin Analog Pin Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 14 of 458 M16C/29 Group 1. Overview P20/OUTC10/INPC10/SDAMM P17/INT5/INPC17/IDU P21/OUTC11/INPC11/SCLMM P24/OUTC14/INPC14 P22/OUTC12/INPC12 P25/OUTC15/INPC15 P23/OUTC13/INPC13 P26/OUTC16/INPC16 P15/INT3/ADTRG/IDV P27/OUTC17/INPC17 P16/INT4/IDW P60/CTS0/RTS0 P03/AN03 P61/CLK0 35 P62/RxD0 34 44 42 48 47 46 45 41 40 39 43 38 37 36 33 P63/TxD0 P02/AN02 P01/AN01 P00/AN00 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVCC P93/AN24/CTX P92/AN32/TB2IN/CRX 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 12 11 13 14 10 15 16 2 1 4 6 3 5 7 8 9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P30/CLK3 P31/SIN3 P32/SOUT3 P33 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TxD1 P70/TxD2/SDA2/TA0OUT/RTS1/CTS1/CTS0/CLKS1 P71/RxD2/SCL2/TA0IN/CLK1 P72/CLK2/TA1OUT/V/RxD1 P73/CTS2/RTS2/TA1IN/V/TxD1 P74/TA2OUT/W P75/TA2IN/W P76/TA3OUT P77/TA3IN M16C/29 Group (M16C/29) PLQP0064KB-A (64P6Q-A) (top view) P85/NMI/SD P84/INT2/ZP P90/AN30/TB0IN/CLKOUT P82/INT0 RESET XOUT VCC VSS P81/TA4IN/U P87/XCIN CNVSS XIN P91/AN31/TB1IN NOTES: 1.Set bits PACR2 to PACR0 in the PACR register to "0102" before signals are input or output to individual pins after reset. When the PACR register is not set, signals are not input or output for some Figure 1.9 Pin Assignment (Top View) of 64-Pin Package Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 15 of 458 P80/TA4OUT/U P86/XCOUT P83/INT1 M16C/29 Group 1. Overview Table 1.13 Pin Characteristics for 64-Pin Package Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CLKOUT CNVss XCIN XCOUT RESET XOUT Vss XIN Vcc P 85 P84 P8 3 P 82 P 81 P80 P77 P 76 P 75 P74 P73 P 72 P 71 P 70 P 67 P 66 P 65 P 64 P 33 P 32 P 31 P 30 P 63 P 62 P 61 P 60 P 27 P 26 P 25 P 24 OUTC17 / INPC17 OUTC16 / INPC16 OUTC15 / INPC15 OUTC14 / INPC14 SOUT3 SIN3 CLK3 TXD0 RXD0 CLK0 RTS0 / CTS0 NMI INT2 INT1 INT0 TA4IN / U TA4OUT / U TA3IN TA3OUT TA2IN / W TA2OUT / W TA1IN / V TA1OUT / V TA0IN TA0OUT CTS2 / RTS2 / TXD1 CLK2 / RXD1 RXD2 / SCL2 / CLK1 TXD2 / SDA2 / RTS1 / CTS1 / CTS0 / CLKS1 TXD1 RXD1 CLK1 RTS1 / CTS1/ CTS0 / CLKS1 SD ZP P87 P86 Control Pin Port P9 1 P90 Interrupt Pin Timer Pin TB1IN TB0IN Timer S Pin UART/CAN Pin Mult-master I2C bus Pin Analog Pin AN31 AN30 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 16 of 458 M16C/29 Group 1. Overview Table 1.13 Pin Characteristics for 64-Pin Package (continued) Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 AVss 60 61 VREF 62 AVcc 63 64 P93 P92 TB2IN CTX CRX AN24 AN32 P100 AN0 Control Pin Port P23 P22 P21 P20 P17 P16 P15 P03 P02 P01 P00 P107 KI3 P106 KI2 P105 KI1 P104 KI0 P103 P102 P101 INT5 INT4 INT3 IDU IDW IDV ADTRG AN03 AN02 AN01 AN00 AN7 AN6 AN5 AN4 AN3 AN2 AN1 Interrupt Pin Timer Pin Timer S Pin OUTC13 / INPC13 OUTC12 / INPC12 OUTC11 / INPC11 OUTC10 / INPC10 INPC17 SCLMM SDAMM UART/CAN Pin Multi-master I2C bus Pin Analog Pin Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 17 of 458 M16C/29 Group 1. Overview 1.5 Pin Description Table 1.14 Pin Description (64-pin and 80-pin packages) Classification Symbol Power supply VCC, VSS Analog power supply Reset input CNVSS Main clock input Main clock output Sub clock input Sub clock output Clock output ______ INT interrupt input _______ NMI interrupt input Key input interrupt KI0 to KI3 Timer A TA0OUT to TA4OUT TA0IN to TA4IN Timer B Three-phase motor control timer output Serial I/O ZP TB0IN to TB2IN ___ ___ U, U, V, V, W, W IDU, IDW, IDV, SD _________ _________ CTS0 to CTS2 RTS0 to RTS2 CLK0 to CLK3 RxD0 to RxD2 SIN3 TxD0 to TxD2 SOUT3 I2C bus Mode Multi-master I2C bus Reference voltage input A/D converter CLKS1 SDA2 SCL2 SDAMM SCLMM VREF AN0 to AN7 AN00 to AN03 AN24 AN30 to AN32 ___________ ADTRG I Input pin for an external A/D trigger _________ _________ _____ ___ _____ _____ AVCC AVSS I/O Type Function Apply 0V to the Vss pin. Apply following voltage to the Vcc pin. I 2.7 to 5.5 V (Normal), 3.0 to 5.5 V (T-ver.), 4.2 to 5.5 V (V-ver.) Supplies power to the A/D converter. Connect the AVCC pin to VCC and I I I I O I O O I I the AVSS pin to VSS ___________ The microcomputer is in a reset state when "L" is applied to the RESET pin Connect the CNVSS pin to VSS I/O pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To apply external clock, apply it to XIN and leave XOUT open. If XIN is not used (for external oscillator or external clock) connect XIN pin to VCC and leave XOUT open I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT Outputs the clock having the same frequency as f1, f8, f32, or fC ______ ________ Input pins for the INT interrupt. INT2 can be used for Timer A Z-phase function _______ _______ Input pin for the NMI interrupt. NMI cannot be used as I/O port while the threephase motor control is enabled. Apply a stable "H" to NMI after setting it's direction register to "0" when the three-phase motor control is enabled I I/O I I I O I/O I O I/O I I O O O I/O I/O I I Input pins for the key input interrupt I/O pins for the timer A0 to A4 Input pins for the timer A0 to A4 Input pin for Z-phase Input pins for the timer B0 to B2 Output pins for the three-phase motor control timer Input and output pins for the three-phase motor control timer Input pins for data transmission control Output pins for data reception control Inputs and outputs the transfer clock Inputs serial data Inputs serial data Outputs serial data Outputs serial data Output pin for transfer clock Inputs and outputs serial data Inputs and outputs the transfer clock Inputs and outputs serial data Inputs and outputs the transfer clock Applies reference voltage to the A/D converter Analog input pins for the A/D converter _______ RESET CNVSS XIN XOUT XCIN XCOUT CLKOUT ____________ ________ INT0 to INT5 NMI ________ _______ I: Input O: Output I/O: Input and output page 18 of 458 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 M16C/29 Group 1. Overview Table 1.14 Pin Description (64-pin and 80-pin packages) (Continued) Classification Timer S CAN I/O Ports Symbol I/O Type Function INPC10 to INPC17 I Input pins for the time measurement function OUTC10 to OUTC17 O Output pins for the waveform generating function CRX I Input pin for the CAN communication function CTX P00 to P03 P15 to P17 P20 to P27 P30 to P33 P60 to P67 P70 to P77 P80 to P87 P90 to P93 P100 to P107 O I/O Output pin for the CAN communication function CMOS I/O ports which have a direction register determines an individual pin is used as an input port or an output port. A pull-up resistor is selectable for every 4 input ports. I: Input O: Output I/O: Input and output Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 19 of 458 M16C/29 Group 1. Overview Table 1.14 Pin Description (80-pin packages only) (Continued) Classification Serial I/O Symbol CLK4 SIN4 I/O Type I/O I O I Function Inputs and outputs the transfer clock Inputs serial data Outputs serial data Analog input pins for the A/D converter SOUT4 A/D Converter AN04 to AN07 AN20 to AN23 AN25 to AN27 I/O Ports P04 to P07 P10 to P14 P34 to P37 P95 to P97 I/O CMOS I/O ports which have a direction register determines an individual pin is used as an input port or an output port. A pull-up resistor is selectable for every 4 input ports. I : Input O : Output I/O : Input and output Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 20 of 458 M16C/29 Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b31 b15 b8 b7 b0 R2 R3 R0H(R0's high bits) R0L(R0's low bits) R1H(R1's high bits)R1L(R1's low bits) R2 R3 A0 A1 FB b19 b15 b0 Data registers (Note) Address registers (Note) Frame base registers (Note) INTBH INTBL Interrupt table register The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL. b19 b0 PC b15 b0 Program counter USP ISP SB b15 b0 User stack pointer Interrupt stack pointer Static base register FLG b15 b8 b7 b0 Flag register Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Note: These registers comprise a register bank. There are two register banks. Figure 2.1. Central Processing Unit Register 2.1 Data Registers (R0, R1, R2 and R3) The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is the same as R2R0. 2.2 Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 21 of 458 M16C/29 Group 2. Central Processing Unit (CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. 2.7 Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. 2.8 Flag Register (FLG) FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to 0. 2.8.3 Zero Flag (Z Flag) This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0. 2.8.4 Sign Flag (S Flag) This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0. 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. 2.8.6 Overflow Flag (O Flag) This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0. 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1. The I flag is cleared to 0 when the interrupt request is accepted. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is 0; USP is selected when the U flag is 1. The U flag is cleared to 0 when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. 2.8.10 Reserved Area When write to this bit, write 0. When read, its content is undefined. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 22 of 458 M16C/29 Group 3. Memory 3. Memory Figure 3.1 is a memory map of the M16C/29 Group. M16C/29 Group provides 1-Mbyte address space from addresses 0000016 to FFFFF16. The internal ROM is allocated lower addresses beginning with address FFFFF16. For example, 64-Kbytes internal ROM is allocated addresses F000016 to FFFFF16. Two 2-Kbyte internal ROM areas, block A and block B, are available in the flash memory version. The blocks are allocated addresses F00016 to FFFF16. The fixed interrupt vector tables are allocated addresses FFFDC16 to FFFFF16. It stores the starting address of each interrupt routine. See the section on interrupts for details. The internal RAM is allocated higher addresses beginning with address 0040016. For example, 4-Kbytes internal RAM is allocated addresses 0040016 to 013FF16. Besides sotring data, it becomes stacks when the subroutines is called or an interrupt is acknowledged. SFR, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O, timers is allocated addresses 0000016 to 003FF16. All blank spaces within SFR are reserved and cannot be accessed by users. The special page vector table is allocated to the addresses FFE0016 to FFFDB16. This vector is used by the JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual. Internal RAM area Memory size 4 Kbytes 0000016 SFR Area 0040016 Internal RAM FFE0016 XXXXX16 Reserved Space 0F00016 0FFFF16 Internal ROM (data space)(1) FFFDC16 Reserved Space Special Page Vector Table 8 Kbytes 12 Kbytes XXXXX16 013FF16 023FF16 033FF16 Internal ROM area Memory size 64 Kbytes 96 Kbytes 128 Kbytes YYYYY16 F000016 E800016 E000016 Undefined Instruction Overflow BRK Instruction Address Match Single Step Watchdog Timer DBC NMI Reset YYYYY16 Internal ROM(2) (program space) FFFFF16 FFFFF16 NOTES: 1. The block A (2K bytes) and block B (2K bytes) are shown (only flash memory). 2. Do not write to the internal ROM area in Mask ROM ver.. Figure 3.1 Memory Map Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 23 of 458 M16C/29 Group 4. Special Function Registers (SFRs) 4. Special Function Registers (SFRs) SFRs (Special Function Registers) are the control registers of peripheral functions. Table 4.1 to 4.11 list the SFR address map. Table 4.1 SFR Information (1) Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Register Symbol After reset Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register Oscillation stop detection register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 (Note 2) PM0 PM1 CM0 CM1 AIER PRCR CM2 WDTS WDC RMAD0 0016 000010002 010010002 001000002 XXXXXX002 XX0000002 0X0000102 XX16 00XXXXXX2 0016 0016 X016 0016 0016 X016 000010002 0016 0001X0102 XXX000002 0016 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 00000X002 Address match interrupt register 1 RMAD1 Voltage detection register 1 Voltage detection register 2 PLL control register 0 Processor mode register 2 Low voltage detection interrupt register DMA0 source pointer (Note 3,4) (Note 3,4) VCR1 VCR2 PLC0 (Note 4) PM2 D4INT SAR0 DMA0 destination pointer DAR0 DMA0 transfer counter TCR0 DMA0 control register DM0CON DMA1 source pointer SAR1 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 00000X002 DMA1 destination pointer DAR1 DMA1 transfer counter TCR1 DMA1 control register DM1CON Note 1: The blank areas are reserved and cannot be used by users. Note 2: Bits CM20, CM21, and CM27 do not change at oscillation stop detection reset. Note 3: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset. Note 4: This registe can not use for T-ver. and V-ver. X : Undefined Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 24 of 458 M16C/29 Group Table 4.2 SFR Information (2) Address 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 4. Special Function Registers (SFRs) Register CAN0 wakeup interrupt control register CAN0 successful reception interrupt control register CAN0 successful transmission interrupt control register INT3 interrupt control register ICOC 0 interrupt control register ICOC 1 interrupt control register, I2C bus interface interrupt control register 1 ICOC base timer interrupt control register, SCL/SDA interrupt control register 2 SI/O4 interrupt control register, INT5 interrupt control register SI/O3 interrupt control register, INT4 interrupt control register UART2 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register CAN0 error interrupt control register A/D conversion interrupt control register, Key input interrupt control register (Note 2) UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register TimerA0 interrupt control register TimerA1 interrupt control register TimerA2 interrupt control register TimerA3 interrupt control register TimerA4 interrupt control register TimerB0 interrupt control register TimerB1 interrupt control register TimerB2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register CAN0 message box 0: Identifier/DLC Symbol C01WKIC C0RECIC C0TRMIC INT3IC ICOC0IC ICOC1IC,IICIC BTIC,SCLDAIC After reset XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XX00X0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XX00X0002 XX00X0002 XX00X0002 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 S4IC, INT5IC S3IC, INT4IC BCNIC DM0IC DM1IC C01ERRIC ADIC, KUPIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC CAN0 message box 0 : Data field CAN0 message box 0 : Time stamp CAN0 message box 1 : Identifier/DLC CAN0 message box 1 : Data field CAN0 message box 1 : Time stamp Note 1: The blank areas are reserved and cannot be used by users. Note 2: A/D conversion interrupt control register is effective when the bit1(Interrupt source select register ( address 35Eh IFSR2A) is set to "0". Key input interrupt control register is effective when the bit1 is set to "1". X : Undefined Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 25 of 458 M16C/29 Group Table 4.3 SFR Information (3) Address 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16 4. Special Function Registers (SFRs) Register CAN0 message box 2: Identifier/DLC Symbol CAN0 message box 2 : Data field CAN0 message box 2 : Time stamp CAN0 message box 3 : Identifier/DLC CAN0 message box 3 : Data field CAN0 message box 3 : Time stamp CAN0 message box 4: Identifier/DLC CAN0 message box 4 : Data field CAN0 message box 4 : Time stamp CAN0 message box 5 : Identifier/DLC CAN0 message box 5 : Data field CAN0 message box 5 : Time stamp After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 Note 1: The blank areas are reserved and cannot be used by users. X : Undefined Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 26 of 458 M16C/29 Group Table 4.4 SFR Information (4) Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 4. Special Function Registers (SFRs) Register CAN0 message box 6: Identifier/DLC Symbol CAN0 message box 6 : Data field CAN0 message box 6 : Time stamp CAN0 message box 7 : Identifier/DLC CAN0 message box 7 : Data field CAN0 message box 7 : Time stamp CAN0 message box 8: Identifier/DLC CAN0 message box 8: Data field CAN0 message box 8 : Time stamp CAN0 message box 9 : Identifier/DLC CAN0 message box 9 : Data field CAN0 message box 9 : Time stamp After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 Note 1: The blank areas are reserved and cannot be used by users. X : Undefined Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 27 of 458 M16C/29 Group Table 4.5 SFR Information (5) Address 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A16 011B16 011C16 011D16 011E16 011F16 012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 012A16 012B16 012C16 012D16 012E16 012F16 013016 013116 013216 013316 013416 013516 013616 013716 013816 013916 013A16 013B16 013C16 013D16 013E16 013F16 4. Special Function Registers (SFRs) Register CAN0 message box 10: Identifier/DLC Symbol CAN0 message box 10 : Data field CAN0 message box 10 : Time stamp CAN0 message box 11 : Identifier/DLC CAN0 message box 11 : Data field CAN0 message box 11 : Time stamp CAN0 message box 12: Identifier/DLC CAN0 message box 12: Data field CAN0 message box 12 : Time stamp CAN0 message box 13 : Identifier/DLC CAN0 message box 13 : Data field CAN0 message box 13 : Time stamp After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 Note 1: The blank areas are reserved and cannot be used by users. X : Undefined Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 28 of 458 M16C/29 Group Table 4.6 SFR Information (6) Address 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A16 014B16 014C16 014D16 014E16 014F16 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A16 015B16 015C16 015D16 015E16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A16 016B16 016C16 016D16 016E16 016F16 017016 017116 4. Special Function Registers (SFRs) Register CAN0 message box 14: Identifier/DLC Symbol CAN0 message box 14 : Data field CAN0 message box 14 : Time stamp CAN0 message box 15 : Identifier/DLC CAN0 message box 15 : Data field CAN0 message box 15 : Time stamp CAN0 global mask register C0GMR CAN0 local mask A register C0LMAR CAN0 local mask B register C0LMBR After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 ~ 01B316 01B416 01B516 01B616 01B716 ~ Flash memory control register 4 Flash memory control register 1 Flash memory control register 0 (Note 2) (Note 2) (Note 2) FMR4 FMR1 FMR0 0100000X2 000XXX0X2 0116 ~ ~ 01FD16 01FE16 01FF16 ~ ~ Note 1: The blank areas are reserved and cannot be used by users. Note 2: This register is included in the flash memory version. X : Undefined Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 29 of 458 M16C/29 Group Table 4.7 SFR Information (7) Address 020016 020116 020216 020316 020416 020516 020616 020716 020816 020916 020A16 020B16 020C16 020D16 020E16 020F16 021016 021116 021216 021316 021416 021516 021616 021716 021816 021916 021A16 021B16 021C16 021D16 021E16 021F16 4. Special Function Registers (SFRs) Register CAN0 message control register 0 CAN0 message control register 1 CAN0 message control register 2 CAN0 message control register 3 CAN0 message control register 4 CAN0 message control register 5 CAN0 message control register 6 CAN0 message control register 7 CAN0 message control register 8 CAN0 message control register 9 CAN0 message control register 10 CAN0 message control register 11 CAN0 message control register 12 CAN0 message control register 13 CAN0 message control register 14 CAN0 message control register 15 CAN0 control register CAN0 status register CAN0 slot status register CAN0 interrupt control register CAN0 extended ID register CAN0 configuration register CAN0 receive error count register CAN0 transmit error count register CAN0 time stamp register Symbol C0MCTL0 C0MCTL1 C0MCTL2 C0MCTL3 C0MCTL4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 C0MCTL9 C0MCTL10 C0MCTL11 C0MCTL12 C0MCTL13 C0MCTL14 C0MCTL15 C0CTLR C0STR C0SSTR C0ICR C0IDR C0CONR C0RECR C0TECR C0TSR After reset 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 X00000012 XX0X00002 0016 X00000012 0016 0016 0016 0016 0016 0016 XX16 XX16 0016 0016 0016 0016 ~ 024216 024316 ~ CAN0 acceptance filter support register C0AFS XX16 XX16 ~ ~ 025A16 025B16 025C16 025D16 025E16 025F16 ~ ~ Three-phase protect control register On-chip oscillator control register Pin assignment control register Peripheral clock select register CAN0 clock select register TPRC ROCR PACR PCLKR CCLKR 0016 000001012 0016 000000112 0016 ~ ~ 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 ~ ~ I2C0 data-shift register I2C0 address register I2C0 control register 0 I2C0 clock control register I2C0 start/stop condition control register I2C0 control register 1 I2C0 control register 2 I2C0 status register S00 S0D0 S1D0 S20 S2D0 S3D0 S4D0 S10 XX16 0016 0016 0016 000110102 001100002 0016 0001000X2 ~ 02FD16 02FE16 02FF16 ~ Note 1: The blank areas are reserved and cannot be used by users. X : Undefined Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 30 of 458 M16C/29 Group Table 4.8 SFR Information (8) Address 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 4. Special Function Registers (SFRs) Register Time measurement, Pulse generation register 0 Time measurement, Pulse generation register 1 Time measurement, Pulse generation register 2 Time measurement, Pulse generation register 3 Time measurement, Pulse generation register 4 Time measurement, Pulse generation register 5 Time measurement, Pulse generation register 6 Time measurement, Pulse generation register 7 Pulse generation control register 0 Pulse generation control register 1 Pulse generation control register 2 Pulse generation control register 3 Pulse generation control register 4 Pulse generation control register 5 Pulse generation control register 6 Pulse generation control register 7 Time measurement control register 0 Time measurement control register 1 Time measurement control register 2 Time measurement control register 3 Time measurement control register 4 Time measurement control register 5 Time measurement control register 6 Time measurement control register 7 Base timer register Base timer control register 0 Base timer control register 1 Time measurement prescale register 6 Time measurement prescale register 7 Function enable register Function select register Base timer reset register Count source division register Symbol G1TM0,G1PO0 G1TM1,G1PO1 G1TM2,G1PO2 G1TM3,G1PO3 G1TM4,G1PO4 G1TM5,G1PO5 G1TM6,G1PO6 G1TM7,G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1BTRR G1DV After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0X00XX002 0016 0016 0016 0016 0016 0016 0016 0016 XX16 XX16 0016 0016 0016 0016 0016 0016 XX16 XX16 0016 Interrupt request register Interrupt enable register 0 Interrupt enable register 1 G1IR G1IE0 G1IE1 XX16 0016 0016 NMI digital debounce register Port P17 digital debounce register NDDR P17DDR FF16 FF16 Note 1: The blank areas are reserved and cannot be used by users. X : Undefined Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 31 of 458 M16C/29 Group Table 4.9 SFR Information (9) Address 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 4. Special Function Registers (SFRs) Register Timer A1-1 register Timer A2-1 register Timer A4-1 register Three phase PWM control register 0 Three phase PWM control register 1 Three phase output buffer register 0 Three phase output buffer register 1 Dead time timer Timer B2 Interrupt occurrence frequency set counter Position - data - retain function control register Symbol TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 PDRF After reset XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 XX16 XX16 XXXX00002 Port function control register PFCR 001111112 Interrupt cause select register 2(2) Interrupt cause select register SI/O3 transmit/receive register SI/O3 control register SI/O3 bit rate register SI/O4 transmit/receive register SI/O4 control register SI/O4 bit rate register IFSR2A IFSR S3TRR S3C S3BRG S4TRR S4C S4BRG 00XXX0002 0016 XX16 010000002 XX16 XX16 010000002 XX16 UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate register UART2 transmit buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB 0016 000X0X0X2 X00000002 X00000002 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 Note 1: The blank areas are reserved and cannot be used by users. Note 2: Write 0 to the bit 0 after reset. X : Undefined Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 32 of 458 M16C/29 Group Table 4.10 SFR Information (10) Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 4. Special Function Registers (SFRs) Register Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-dowm flag Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Timer B2 special mode register UART0 transmit/receive mode register UART0 bit rate register UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 bit rate register UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register UART transmit/receive control register 2 Symbol TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON After reset 0016 0XXXXXXX2 0016 0016 0016 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 0016 00XX00002 00XX00002 00XX00002 X00000002 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 0016 XX16 XX16 XX16 000010002 000000102 XX16 XX16 X00000002 CRC snoop address register CRC mode register DMA0 request cause select register DMA1 request cause select register CRC data register CRC input register CRCSAR CRCMR DM0SL DM1SL CRCD CRCIN XX16 00XXXXXX2 0XXXXXX02 0016 0016 XX16 XX16 XX16 Note 1: The blank areas are reserved and cannot be used by users. X : Undefined Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 33 of 458 M16C/29 Group Table 4.11 SFR Information (11) Address 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 4. Special Function Registers (SFRs) A/D register 0 A/D register 1 A/D register 2 A/D register 3 A/D register 4 A/D register 5 A/D register 6 A/D register 7 Register Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 After reset XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XXXX00002 00000X002 0016 00000XXX2 0016 A/D trigger control register A/D status register 0 A/D control register 2 A/D control register 0 A/D control register 1 ADTRGCON ADSTAT0 ADCON2 ADCON0 ADCON1 Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register P0 P1 PD0 PD1 P2 P3 PD2 PD3 XX16 XX16 0016 0016 XX16 XX16 0016 0016 Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register Port P10 direction register P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10 XX16 XX16 0016 0016 XX16 XX16 0016 000X00002 XX16 0016 Pull-up control register 0 Pull-up control register 1 Pull-up control register 2 Port control register PUR0 PUR1 PUR2 PCR 0016 0016 0016 0016 Note 1: The blank areas are reserved and cannot be used by users. X : Undefined Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 34 of 458 M16C/29 Group 5. Resets 5. Resets Hardware reset 1, brown-out detection reset (hardware reset 2), software reset, watchdog timer reset, and oscillation stop detection reset are implemented to reset the MCU. 5.1 Hardware Reset Hardware reset 1 and brown-out detection reset are available as the hardware reset. 5.1.1 Hardware Reset 1 Pins, CPU, and SFRs are reset by using the RESET pin. When a low-level (“L”) signal is applied to the ____________ RESET pin while the supply voltage meets the recommended operating condition, pins, CPU, and SFRs ____________ are reset (see Table 5.1 Pin Status When RESET Pin Level is “L”). The oscillation circuit is also reset and the on-chip oscillator starts oscillating as the CPU clock. CPU and SFRs re reset when the signal applied ____________ to the RESET pin changes from “L” to high (“H”). The MCU executes a program beginning with the address indicated by the reset vector. The internal RAM is not reset. When an “L” signal is applied to the ____________ RESET pin while writing data to the internal RAM, the content of internal RAM is undefined. Figure 5.1 shows an example of the reset circuit. Figure 5.2 shows a reset sequence. Table 5.1 shows ____________ status of the other pins while the RESET pin is held “L”. Figure 5.3 shows CPU register states after reset. Refer to 4. Special Function Register (SFR) about SFR states after reset. 1. Reset on a stable supply voltage ____________ (1) Apply an “L” signal to the RESET pin (2) Wait td(ROC) or more ____________ (3) Apply an “H” signal to the RESET pin 2. Power-on reset ____________ (1) Apply an “L” signal to the RESET pin (2) Increase the supply voltage until it meets the the recommended performance condition (3) Wait for td(P-R) or more to allow the internal power supply to stabilize (4) Wait td(ROC) or more ____________ (5) Apply an “H” signal to the RESET pin ____________ 5.1.2 Brown-Out Detection Reset (Hardware Reset 2) Note Brown-out detection reset in the M16C/29 Group, T-ver. and V-ver. cannot be used. Pins, CPU, and SFR are reset by using the on-chip voltage detection circuit, which monitors the voltage applied to VCC pin. When the VC26 bit in the VCR2 register is set to 1 (reset level detection circuit enabled), pins, CPU, and SFR are reset as soon as the voltage applied to the VCC pin drops to Vdet3 or below. Then, pins, CPU, and SFR are reset as soon as the voltage applied to the VCC pin reaches Vdet3r or above. The MCU executes the program in an address determined by the reset vector. The MCU executes the program after detecting Vdet3r and waiting td(S-R) ms. The same pins and registers are reset by the hardware reset 1 and brown-out detection reset, and are also placed in the same reset state. The MCU cannot exit stop mode by brown-out detection reset. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 35 of 458 M16C/29 Group 5. Resets VCC 0V RESET VCC RESET 0V Recommended operating voltage Equal to or less than 0.2VCC Equal to or less than 0.2VCC More than td(ROC) + td(P-R) Figure 5.1 Example Reset Circuit 5.2 Software Reset The MCU resets its pins, CPU, and SFRs when the PM03 bit in the PM0 register is set to 1 (reset) and the MCU executes a program in an address indicated by the reset vector. Then the on-chip oscillator is selected as the CPU clock. The software reset does not reset some portions of the SFRs. Refer to 4. Special Function Registers (SFRs) for details. 5.3 Watchdog Timer Reset The MCU resets its pins, CPU, and SFRs when the PM12 bit in the PM1 register is set to 1 (watchdog timer reset) and the watchdog timer underflows. The MCU executes a program in an address indicated by the reset vector. Then the on-chip oscillator is selected as the CPU clock. The watchdog timer reset does not reset some portions of the SFRs. Refer to 4. Special Function Registers (SFRs) for details. 5.4 Oscillation Stop Detection Reset The MCU resets its pins, CPU, and SFRs and stops if the main clock stop is detected when the CM20 bit in the CM2 register is set to 1 (oscillation stop, re-oscillation detection function enabled) and the CM27 bit in the CM2 register is 0 (reset at oscillation stop detection). Refer to the section 7.8 oscillation stop, reoscillation detection function for details. The oscillation stop detection reset does not reset some portions of the SFRs. Refer to 4. Special Function Registers (SFRs). Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 36 of 458 M16C/29 Group 5. Resets VCC ROC td(P-R) More than td(ROC) RESET Max. 2 ms CPU clock: 28 cycles CPU clock FFFFC 16 Address FFFFE16 Content of reset vector Figure 5.2 Reset Sequence ____________ Table 5.1 Pin Status When RESET Pin Level is “L” Pin name P0 to P3, P6 to P10 Status Input port (high impedance) b15 b0 000016 000016 000016 000016 000016 000016 000016 b19 b0 Data register(R0) Data register(R1) Data register(R2) Data register(R3) Address register(A0) Address register(A1) Frame base register(FB) 0000016 Content of addresses FFFFE16 to FFFFC16 b15 b0 Interrupt table register(INTB) Program counter(PC) User stack pointer(USP) Interrupt stack pointer(ISP) Static base register(SB) b0 000016 000016 000016 b15 000016 b15 b8 b7 b0 Flag register(FLG) IPL UI OBS Z DC Figure 5.3 CPU Register Status After Reset Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 37 of 458 M16C/29 Group 5. Resets 5.5 Voltage Detection Circuit Note VCC = 5 V is assumed in 5.5 Voltage Detection Circuit. Voltage detection circuit in the M16C/29 Group, T-ver. and V-ver. cannot be used. The voltage detection circuit has the reset level detection circuit and the low voltage detection circuit. The reset level detection circuit monitors the voltage applied to the VCC pin. The MCU is reset if the reset level detection circuit detects VCC is Vdet3 or below. Use bits VC27 and VC26 in the VCR2 register to determine whether the individual circuit is enabled. Use the reset level detection circuit for brown-out detection reset. The low voltage detection circuit also monitors the voltage applied to the VCC pin. The low voltage detection circuit use the VC13 bit in the VCR1 register to detect VCC is above or below Vdet4. The low voltage detection interrupt can be used in the voltage detection circuit. VCR2 Register RESET b7 b6 1 shot Reset level detection circuit Brown-out Detect Reset (Hardware Reset 2 Release Wait Time) >T Q td(S-R) + >Vdet3 CM10 Bit=1 (Stop Mode) E Internal Reset Signal (“L” active) VCC + >Vdet4 E Low voltage detection circuit Noise Rejection Low Voltage Detect Signal VCR1 Register b3 VC13 Bit Figure 5.4 Voltage Detection Circuit Block Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 38 of 458 M16C/29 Group 5. Resets Voltage Detection Register 1 0000 b7 b6 b5 b4 b3 000 b2 b1 b0 Symbol VCR1 Bit Symbol (b2-b0) Address 001916 Bit Name Reserved bit After Reset (2) 000010002 Function Set to 0 0:VCC < Vdet4 1:VCC ≥ Vdet4 RW RW RO RW VC13 (b7-b4) Low voltage monitor flag (1) Reserved bit Set to 0 NOTES: 1. The VC13 bit is useful when the VC27 bit of VCR2 register is set to 1 (low voltage detection circuit enable). The VC13 bit is always 1 (VCC≥ Vdet4) when the VC27 bit in the VCR2 register is set to 0 (low voltage detection circuit disable). 2. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset. Voltage Detection Register 2 (1) b7 b6 b5 b4 b3 b2 b1 b0 000000 Symbol VCR2 Bit Symbol (b5-b0) Address 001A16 Bit Name Reserved bit Reset level monitor bit (2, 3, 6) After Reset (5) 0016 Function Set to 0 0: Disable reset level detection circuit 1: Enable reset level detection circuit 0: Disable low voltage detection circuit 1: Enable low voltage detection circuit RW RW RW VC26 VC27 Low voltage monitor bit (4, 6) RW NOTES: 1. Write to this register after setting the PRC3 bit in the PRCR register to 1 (write enable). 2. Set the VC26 bit to 1 to use brown-out reset. 3. VC26 bit is disabled in stop mode. (The MCU is not reset even if the voltage input to Vcc pin becomes lower than Vdet3.) 4. When the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to 1 (low voltage detection interrupt enable), set the VC27 bit to 1. 5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset. 6. The detection circuit does not start operation until td(E-A) elapses after the VC26 bit or VC27 bit is set to 1. Figure 5.5 VCR1 Register and VCR2 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 39 of 458 M16C/29 Group 5. Resets Low Voltage Detection Interrupt Register b7 b6 b5 b4 b3 b2 b1 b0 (1) After Reset 0016 Function 0 : Disab le 1 : En able 0: Disable (do not use the low voltage detection interrupt to exit stop mode) 1: Enable (use the low voltage detection interrupt to exit stop mode) Symbol D4INT Bit Symbol D40 D41 Address 001F16 Bit Name Low voltage detection interrupt enable bit (5) STOP mode deactivation control bit (4) RW RW RW D42 D43 DF0 DF1 Voltage change detection flag 0: Not detected (2) 1: Vdet4 passing detection WDT overflow detect flag Sampling clock select bit 0: Not detected 1: Detected b5b4 (3) RW (3) RW RW RW 00 : CPU clock divided by 8 01 : CPU clock divided by 16 10 : CPU clock divided by 32 11 : CPU clock divided by 64 (b7-b6) Nothing is assigned. If necessary set to 0. When read, the content is 0 NOTES: 1. Write to this register after setting the PRC3 bit in the PRCR register to 1 (write enable). 2. Useful when the VC27 bit in the VCR2 register is set to 1 (low voltage detection circuit enabled). If the VC27 bit is set to 0 (low voltage detection circuit disable), the D42 bit is set to 0 (Not detect). 3. This bit is set to 0 by writing a 0 in a program. (Writing 1 has no effect.) 4. If the low voltage detection interrupt needs to be used to get out of stop mode again after once used for that purpose, reset the D41 bit by writing a 0 and then a 1. 5. The D40 bit is effective when the VC27 bit in the VCR2 register is set to 1. To set the D40 bit to 1, follow the procedure described below. (1) Set the VC27 bit to 1. (2) Wait for td(E-A) until the detection circuit is actuated. (3) Wait for the sampling time (refer to Table 5.3 Sampling Clock Periods). (4) Set the D40 bit to 1. Figure 5.6 D4INT Register VCC Vdet4 Vdet3r Vdet3 Vdet3s VSS 5.0V 5.0V RESET Internal Reset Signal VC13 bit in VCR1 register VC26 bit in VCR2 register (1) VC27 bit in VCR2 register Undefined Set to 1 by program (reset level detect circuit enable) Undefined Set to 1 by program (low voltage detection circuit enable) Undefined NOTES : 1. VC26 bit is invalid in stop mode. (the MCU is not reset even if input voltage of VCC pin becomes lower than Vdet3). Figure 5.7 Typical Operation of Brown-Out Detection Reset (Hardware Reset 2) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 40 of 458 M16C/29 Group 5. Resets 5.5.1 Low Voltage Detection Interrupt If the D40 bit in the D4INT register is set to 1 (low voltge detection interrupt enabled), a low voltage detection interrupt request is generated when voltage applied to the VCC pin is above or below Vdet4. The low voltage detection interrupt shares the same interrupt vector with watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt. Set the D41 bit in the D4INT register to 1 (enabled) to use the low voltage detection interrupt to exit stop mode, set the D41 bit in the D4INT register to 1 (enable). The D42 bit in the D4INT register is set to 1 (above or below Vdet4 detected) as soon as voltage applied to the VCC pin goes above or below Vdet4 due to the voltage change. When the D42 bit setting changes 0 to 1, a low voltage detection interrupt is generated. Set the D42 bit to 0 (not detected) by program. However, when the D41 bit is set to 1 and the MCU is in stop mode, a low voltage detection interrupt request is generated, regardless of the D42 bit setting, if voltage applies to the VCC pin is detected to rise above or drop below Vdet4. The MCU then exits stop mode. Table 5.2 shows how a low voltage detection interrupt request is generated. Bits DF1 and DF0 in the D4INT register determine sampling period that detects voltage applied to the VCC pin rises above or drops below Vdet4. Table 5.3 shows sampling periods. Table 5.2 Voltage Detection Interrupt Request Generation Conditions Operation Mode Normal operation mode(1) Wait mode (2) Stop mode (2) 1 1 VC27 bit D40 bit D41 bit D42 bit 0 to 1 0 to 1 0 1 1 0 CM02 bit VC13 bit 0 to 1 1 to 0 0 to 1 1 to 0 0 to 1 0 to 1 (3) (3) (3) (3) – : 0 or 1 NOTES: 1. The status except the wait mode and stop mode is handled as the normal mode. (Refer to 7. Clock generating circuit) 2. Refer to 5.5.2 Limitations on stop mode and 5.5.3 Limitations on wait mode. 3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed. Refer to the Figure 5.9 for details. Table 5.3 Sampling Clock Periods CPU clock (MHz) 16 Sampling clock (µs) DF1 to DF0=00 DF1 to DF0=01 DF1 to DF0=10 DF1 to DF0=11 (CPU clock divided by 8) (CPU clock divided by 16) (CPU clock divided by 32) (CPU clock divided by 64) 3.0 6.0 12.0 24.0 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 41 of 458 M16C/29 Group 5. Resets Low voltage detection interrupt generation circuit DF1, DF0 002 Low voltage detection circuit VC27 D4INT clock(the clock with which it operates also in wait mode) 012 102 1/8 1/2 1/2 1/2 112 D42 bit is set to 0 (not detected) by writing a 0 in a program. VC27 bit is set to 0 (low voltage detection circuit disabled), the D42 bit is set to 0. VC13 VCC Vref + Noise rejection Noise rejection circuit Digital filter D42 Watchdog timer interrupt signal (Rejection wide:200 ns) Low voltage detection signal “H” when VC27 bit = 0 (disabled) CM10 D41 Low voltage detection interrupt signal Oscillation stop, re-oscillation detection interrupt signal Non-maskable interrupt signal Watchdog timer block CM02 WAIT instruction (wait mode) D43 Watchdog timer underflow signal D40 This bit is set to 0 (not detected) by writing a 0 by program. Figure 5.8 Low Voltage Detection Interrupt Generation Block VCC VC13 bit sampling sampling sampling sampling No low voltage detection interrupt signals are generated when the D42 bit is 1. Output of the digital filter (2) D42 bit Set to 0 by program (not Set to 0 by a program (not detected) detected) Low voltage detection interrupt signal NOTES: 1. D40 bit in the D4INT register is set to 1 (low voltage detection interrupt enabled). 2. Output of the digital filter shown in Figure 5.8. Figure 5.9 Low voltage Detection Interrupt Generation Circuit Operation Example Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 42 of 458 M16C/29 Group 5. Resets 5.5.2. Limitations on Stop Mode When all the conditions below are met, the low voltage detection interrupt is generated and the MCU exits stop mode as soon as the CM10 bit in the CM1 register is set to 1 (all clocks stopped). • the VC27 bit in the VCR2 register is set to 1 (low voltage detection circuit enabled) • the D40 bit in the D4INT register is set to 1 (low voltage detection interrupt enabled) • the D41 bit in the D4INT register is set to 1 (low voltage detection interrupt is used to exit stop mode) • the voltage applied to the VCC pin is higher than Vdet4 (the VC13 bit in the VCR1 register is 1) Set the CM10 bit to 1 when the VC13 bit is set to set to 0 (VCC < Vdet4), if the MCU is configured to enter stop mode when voltage applied to the VCC pin drops Vdet4 or below and to exit stop mode when the voltage applied rises to Vdet4 or above. 5.5.3. Limitations on WAIT Instruction When all the conditions below are met, the low voltage detection interrupt is generated and the MCU exits wait mode as soon as WAIT instruction is executed. • the CM02 bit in the CM0 register is set to 1 (stop peripheral function clock) • the VC27 bit in the VCR2 register is set to 1 (low voltage detection circuit enabled) • the D40 bit in the D4INT register is set to 1 (low voltage detection interrupt enabled) • the D41 bit in the D4INT register is set to 1 (low voltage detection interrupt is used to exit wait mode) • the voltage applied to the VCC pin is higher than Vdet4 (the VC13 bit in the VCR1 register is 1) Execute the WAIT instruction when the VC13 bit is set to set to 0 (VCC < Vdet4), if the MCU is configured to enter wait mode when voltage applied to the VCC pin drops Vdet4 or below and to exit wait mode when the voltage applied rises to Vdet4 or above. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 43 of 458 M16C/29 Group 6. Processor Mode 6. Processor Mode The MCU supports single-chip mode only. Figures 6.1 and 6.2 show the associated registers. Processor Mode Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 0000 000 Symbol PM0 Address 000416 After Reset 0016 Bit Symbol (b2-b0) PM03 Bit Name Reserved bit Set to 0 Function RW RW RW RW Software reset bit The MCU is reset when this bit is set to 1. When read, its content is 0. Set to 0 (b7-b4) Reserved bit NOTES: 1. Set the PM0 register after the PRC1 bit in the PRCR register is set to 1 (write enable). Processor Mode Register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 0001 0 Symbol PM1 Address 000516 After Reset 000010002 Bit Symbol PM10 (b1) PM12 (b3) (b6-b4) PM17 Bit Name Flash data block access bit (2) Reserved bit Watchdog timer function select bit Reserved bit Reserved bit Wait bit (5) Function 0: Disabled 1: Enabled (3) Set to 0 0 : Watchdog timer interrupt 1 : Watchdog timer reset (4) Set to 1 Set to 0 0 : No wait state 1 : Wait state (1 wait) RW RW RW RW RW RW RW NOTES: 1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to 1 (write enable). 2. To access the two 2K-byte data spaces in data block A and data block B, set the PM10 bit to 1. The PM10 bit is not available in mask version. 3. When the FMR01 bit in the FMR0 register is set to 1 (enables CPU rewrite mode), the PM10 bit is automatically set to 1. 4. Set the PM12 bit to 1 by program. (Writing 0 by program has no effect) 5. When the PM17 bit is set to 1 (wait state), one wait is inserted when accessing the internal RAM or the internal ROM. Figure 6.1 PM0 Register and PM1 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 44 of 458 M16C/29 Group 6. Processor Mode Processeor Mode Register 2 (1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PM2 Bit Symbol PM20 PM21 Address 001E16 Bit Name Specifying wait when accessing SFR(2) System clock protective bit(3,4) After Reset XXX00000 2 Function 0: 2 waits 1: 1 wait 0: Clock is protected by PRCR register 1: Clock modification disabled 0: CPU clock is used for the watchdog timer count source 1: On-chip oscillator clock is used for the watchdog timer count source Set to 0 0: P85 function (NMI disabled) 1: NMI function RW RW RW PM22 WDT count source protective bit(3,5) RW (b3) PM24 (b7-b5) Reserved bit P85/NMI configuration bit(6,7) RW RW Nothing is assigned. When write, set to 0. When read, thecontent is undefined NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enable). 2. The PM20 bit becomes effective when PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20 bit when the PLC07 bit is set to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz. 3. Once this bit is set to 1, it cannot be cleared to 0 by program. 4. Writting to the following bits has no effect when the PM21 bit is set to 1: CM02 bit in the CM0 register CM05 bit in the CM0 register (main clock is not halted) CM07 bit in the CM0 register (CPU clock source does not change) CM10 bit in the CM1 register (stop mode is not entered) CM11 bit in the CM1 register (CPU clock source does not change) CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change) All bits in the PLC0 register (PLL frequency synthesizer setting do not change) Do not execute WAIT instruction when the PM21 bit is set to 1. 5. Setting the PM22 bit to 1 results in the following conditions: • The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or • The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source. • The CM10 bit in the CM1 register cannnot be written. (Writing 1 has no effect, stop mode is not entered.) • The watchdog timer does not stop in wait mode. 6. For NMI function, the PM24 bit must be set to 1(NMI function). Once this bit is set to 1, it cannot be set to 0 by program. 7. SD input is valid regardless of the PM24 setting. PLL clock) (system clock of count source selected by the CM21 bit is valid) Figure 6.2 PM2 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 45 of 458 M16C/29 Group 6. Processor Mode The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and peripheral bus. Figure 6.3 shows the block diagram of the internal bus. ROM CPU address bus RAM CPU CPU data bus BIU Memory address bus Memory data bus DMAC CPU clock Timer WDT Serial I/O ADC CAN CRC . . SFR Peripheral function Peripheral address bus Periphral data bus Clock generation circuit Peripheral function I/O Figure 6.3 Bus Block Diagram The number of bus cycle varies by the internal bus. Table 6.1 lists the accessible area and bus cycle. Table 6.1 Accessible Area and Bus Cycle Accessible Area SFR ROM/RAM PM20 bit = 0 (2 waits) PM20 bit = 1 (1 wait) PM17 bit = 0 (no wait) PM17 bit = 1 (1 wait) Bus Cycle 3 CPU clock cycles 2 CPU clock cycles 1 CPU clock cycle 2 CPU clock cycles Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 46 of 458 M16C/29 Group 7. Clock Generation Circuit 7. Clock Generation Circuit The clock generation circuit contains four oscillator circuits as follows: (1) Main clock oscillation circuit (2) Sub clock oscillation circuit (3) Variable on-chip oscillators (4) PLL frequency synthesizer Table 7.1 lists the specifications of the clock generation circuit. Figure 7.1 shows the clock generation circuit. Figures 7.2 to 7.7 show clock-associated registers. Table 7.1 Clock Generation Circuit Specifications Item Use of clock PLL Frequency Sub Clock Variable On-chip Oscillator Synthesizer Oscillation Circuit - CPU clock source - CPU clock source - CPU clock source - CPU clock source - Peripheral function - Timer A, B's clock - Peripheral function clock source - Peripheral function clock source clock source source - CPU and peripheral function clock sources when the main clock stops oscillating 10 to 20 MHz 0 to 20 MHz 32.768 kHz Selectable source frequency: f1(ROC), f2(ROC), f3(ROC) Selectable divider: by 2, by 4, by 8 - Ceramic oscillator - Crystal oscillator XIN, XOUT - Crystal oscillator XCIN, XCOUT Main Clock Oscillation Circui t Clock frequency Usable oscillator Pins to connect oscillator Oscillation stop, restart function Oscillator status after reset Other Available Oscillating Available Stopped Available Oscillating Available Stopped (CPU clock source) Externally derived clock can be input Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 47 of 458 M16C/29 Group 7. Clock Generation Circuit CCLK2-CCLK0=0002 CCLK2-CCLK0=0012 CCLK2-CCLK0=0102 CCLK2-CCLK0=0112 CCLK2-CCLK0=1002 CAN module system clock divider I/O ports PCLK5=0,CM01-CM00=002 PCLK5=0,CM01-CM00=012 PCLK5=1, CM01-CM00=002 1/32 f1 Sub-clock fC CM21 Variable on-chip oscillator Oscillation stop, reoscillation detection circuit CM10=1(stop mode) SQ R Main clock CM05 Main clock generating circuit 1 0 fCAN Sub-clock generating circuit XCIN CM04 XCOUT CLKOUT PCLK5=0, CM01-CM00=102 fC32 PCLK0=1 PCLK5=0, CM01-CM00=112 f2 f8 PCLK0=0 f32 fAD f1SIO f2SIO PCLK1=1 PCLK1=0 f8SIO On-chip oscillator clock XIN XOUT PLL frequency synthesizer PLL clock CM11 CM21=1 a ebc e d fC f32SIO CM07=0 D4INT clock CPU clock CM07=1 CM21=0 BCLK CM02 S WAIT instruction R Q e a RESET Software reset NMI Interrupt request level judgment output b 1/2 1/2 1/4 1/8 CM06=1 CM06=0 CM17, CM16=102 c 1/2 1/16 CM06=0 CM17, CM16=112 1/2 1/2 1/2 1/32 d CM00, CM01, CM02, CM04, CM05, CM06, CM07: Bits in the CM0 register CM10, CM11, CM16, CM17: Bits in the CM1 register PCLK0, PCLK1, PCLK5: Bits in the PCLKR register CM21, CM27: Bits in the CM2 register CM06=0 CM17, CM16=012 CM06=0 CM17, CM16=002 Details of divider Oscillation stop, re-oscillation detection circuit Variable On-chip Oscillator f1(ROC) ROCR1, ROCR0=002 Main clock Pulse generation circuit for clock edge detection and charge, discharge control Charge, discharge circuit CM27=0 Reset generating circuit Oscillation stop detection reset Oscillation stop, re-oscillation detection signal f2(ROC) CM27=1 Oscillation stop, re-oscillation detection interrupt generating circuit ROCR1,ROCR0=012 1/2 1/2 1/2 1/2 f3(ROC) ROCR1, ROCR0=112 1/4 1/8 ROCR3, ROCR2=112 ROCR3, ROCR2=102 ROCR3, ROCR2=012 CM21 switch signal On-chip oscillator clock PLL frequency synthesizer Programmable counter Phase comparator Charge pump Main clock Voltage control oscillator (VCO) 1/2 PLL clock Internal lowpass filter Figure 7.1 Clock Generation Circuit Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 48 of 458 M16C/29 Group 7. Clock Generation Circuit System Clock Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Bit Symbol CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07 Address 000616 Bit Name Clock output function select bit After Reset 010010002 Function See Table 7.3 RW RW RW Wait Mode peripheral function 0: Do not stop peripheral function clock in wait mode clock stop bit (10) 1: Stop peripheral function clock in wait mode (8) XCIN-XCOUT drive capacity 0: LOW select bit (2) 1: HIGH 0: I/O port P8 6, P87 Port XC select bit (2) 1: XCIN-XCOUT generation function(9) Main clock stop bit (3, 10, 12, 13) RW RW RW RW RW RW 0: On 1: Off (4) (5) Main clock division select bit 0 (7, 13, 14) System clock select bit (6, 10, 11, 12) 0: CM16 and CM17 valid 1: Division by 8 mode 0: Main clock, PLL clock, or on-chip oscillator clock 1: Sub-clock NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable). 2. The CM03 bit is set to 1 (high) when the CM04 bit is set to 0 (I/O port) or the MCU goes to a stop mode. 3. This bit is provided to stop the main clock when the low power dissipation mode or on-chip oscillator low power dissipation mode is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock, the following setting is required: (1) Set the CM07 bit to 1 (Sub-clock select) or the CM21 bit in the CM2 register to 1 (on-chip oscillator select) with the subclock stably oscillating. (2) Set the CM20 bit in the CM2 register to 0 (Oscillation stop, re-oscillation detection function disabled). (3) Set the CM05 bit to 1 (Stop). 4. During external clock input, set the CM05 bit to 0 (On). 5. When CM05 bit is set to 1, the XOUT pin goes "H". Futhermore, because the internal feedback resistor remains connectes, the XIN pin is pulled "H" to the same level as XOUT via the feedback resistor. 6. After setting the CM04 bit to 1 (XCIN-XCOUT oscillator function), wait until the sub-clock oscillates stably before switching the CM07 bit from 0 to 1 (sub-clock). 7. When entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip oscillator low power mode, the CM06 bit is set to 1 (divided-by-8 mode). 8. The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to 1(peripheral clock turned off in wait mode). 9. To use a sub-clock, set this bit to 1. Also, make sure ports P86 and P87 are directed for input, with no pull-ups. 10. When the PM21 bit in the PM2 register is set to 1 (clock modification disable), writing to bits CM02, CM05, and CM07 has no effect. 11. If the PM21 bit needs to be set to 1, set the CM07 bit to 0 (main clock) before setting it. 12. To use the main clock a the clock source for the CPU clock, follow the procedure below. (1) Set the CM05 bit to 0 (oscillate). (2) Wait the main clock oscillation stabilized. (3) Set all bits CM11, CM21, and CM07 to 0. 13. When the CM21 bit is set to 0 (on-chip oscillaor turned off) and the CM05 bit is set to 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode) and the CM15 bit is fixed to 1 (drive capability High). 14. To return from on-chip oscillator mode to high-speed or middle-speed mode set both bits CM06 and CM15 to 1. Figure 7.2 CM0 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 49 of 458 M16C/29 Group 7. Clock Generation Circuit System Clock Control Register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 Symbol CM1 Bit Symbol CM10 CM11 (b4-b2) CM15 CM16 CM17 (4, 6) (6, 7) Address 0007 16 Bit Name All clock stop control bit System clock select bit 1 Reserved bit XIN-XOUT drive capacity select bit (2) Main clock division select bits (3) After Reset 00100000 2 Function 0 : Clock on 1 : All clocks off (stop mode) 0 : Main clock 1 : PLL clock (5) Set to 0 0 : LOW 1 : HIGH 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode b7 b6 RW RW RW RW RW RW RW NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable). 2. When entering stop mode from high or middle speed mode, or when the CM05 bit is set to 1 (main clock turned off) in low speed mode, the CM15 bit is set to 1 (drive capability high). 3. Effective when the CM06 bit is 0 (bits CM16 and CM17 enable). 4. If the CM10 bit is 1 (stop mode), XOUT goes “H” and the internal feedback resistor is disconnected. The XCIN and XCOUT pins are placed in the high-impedance state. When the CM11 bit is set to 1 (PLL clock), or the CM20 bit in the CM2 register is set to 1 (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to 1. 5. After setting the PLC07 bit in the PLC0 register to 1 (PLL operation), wait until tsu (PLL) elapses before setting the CM11 bit to 1 (PLL clock). 6. When the PM21 bit in the PM2 register is set to 1 (clock modification disable), writing to bits CM10, CM11 has no effect. When the PM22 bit in the PM2 register is set to 1 (watchdog timer count source is on-chip oscillator clock), writing to the CM10 bit has no effect. 7. Effective when CM07 bit is 0 and CM21 bit is 0 . Figure 7.3 CM1 Register On-chip Oscillator Control Register b7 b6 b5 b4 b3 b2 b1 b0 (1) 000 Symbol ROCR Bit Symbol ROCR0 ROCR1 ROCR2 ROCR3 (b6-b4) (b7) Reserved bit Address 025C 16 Bit Name Frequency select bits b1 b0 After Reset X0000101 2 Function 0 0: f1 (ROC) 0 1: f2 (ROC) 1 0: Do not set to this value 1 1: f3 (ROC) 0 0: Do not set to this value 0 1: divide by 2 1 0: divide by 4 1 1: divide by 8 Set to 0 b3 b2 RW RW RW RW RW RW Divider select bits Nothing is assigned. When write, set to 0. When read, its content is undefined NOTE: 1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable). Figure 7.4 ROCR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 50 of 458 M16C/29 Group 7. Clock Generation Circuit Oscillation Stop Detection Register (1) b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol CM2 Bit Symbol CM20 Address 000C 16 Bit Name (7, 9, 10, 11) After Reset 0X000010 2(11) Function 0: Oscillation stop, re-oscillation detection function disabled 1: Oscillation stop, re-oscillation detection function enabled 0: Main clock or PLL clock 1: On-chip oscillator clock (On-chip oscillator oscillating) 0: Main clock stop,or re-oscillation not detected 1: Main clock stop,or re-oscillation detected 0: Main clock oscillating 1: Main clock not oscillating Set to 0 RW RW Oscillation stop, reoscillation detection bit CM21 System clock select bit 2 (2, 3, 6, 8, 11, 12 ) RW CM22 Oscillation stop, reoscillation detection flag (4) RW CM23 (b5-b4) (b6) CM27 XIN monitor flag (5) RO RW Reserved bit Nothing is assigned. When write, set to 0. When read, its content is undefined Operation select bit 0: Oscillation stop detection reset (when an oscillation stop, 1: Oscillation stop, re-oscillation re-oscillation is detected) detection interrupt (11) RW NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable). 2. When the CM20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to 1 (oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit is automatically set to 1 (on-chip oscillator clock) if the main clock stop is detected. 3. If the CM20 bit is set to 1 and the CM23 bit is set to 1 (main clock not oscillating), do not set the CM21 bit to 0. 4. This flag is set to 1 when the main clock is detected to have stopped or when the main clock is detected to have restarted oscillating. When this flag changes state from 0 to 1, an oscillation stop, reoscillation restart detection interrupt is generated. Use this flag in an interrupt routine to discriminate the causes of interrupts between the oscillation stop, reoscillation detection interrupts and the watchdog timer interrupt. The flag is cleared to 0 by writing 0 by program. (Writing 1 has no effect. Nor is it cleared to 0 by an oscillation stop or an oscillation restart detection interrupt request acknowledged.) If when the CM22 bit is set to 1 an oscillation stoppage or an oscillation restart is detected, no oscillation stop, reoscillation restart detection interrupts are generated. 5. Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main clock status. 6. Effective when the CM07 bit in the CM0 register is set to 0. 7. When the PM21 bit in the PM2 register is 1 (clock modification disabled), writing to the CM20 bit has no effect. 8. When the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set 1 (oscillation stop, re-oscillation detection interrupt), and the CM11 bit is 1 (the CPU clock source is PLL clock), the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is set to 0 under these conditions, oscillation stop, re-oscillation detection interrupt occur at main clock stop detection; it is, therefore, necessary to set the CM21 bit to 1 (on-chip oscillator clock) inside the interrupt routine. 9. Set the CM20 bit to 0 (disable) before entering stop mode. After exiting stop mode, set the CM20 bit back to 1 (enable). 10. Set the CM20 bit to 0 (disable) before setting the CM05 bit in the CM0 register. 11. Bits CM20, CM21 and CM27 do not change at oscillation stop detection reset. 12. When the CM21 bit is set to 0 (on-chip oscillator turned off) and the CM05 bit is set to 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode) and the CM15 bit is fixed to 1 (drive capability High). Figure 7.5 CM2 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 51 of 458 M16C/29 Group 7. Clock Generation Circuit Peripheral Clock Select Register (1) b7 b6 b5 b4 b3 b2 b1 b0 00 000 Symbol PCLKR Bit Symbol Address 025E16 Bit Name Timers A, B clock select bit (Clock source for the timers A, B, the timer S, the dead timer, SI/O3, SI/O4 and multi-master I2C bus) SI/O clock select bit (Clock source for UART0 to UART2) Reserved bit Clock output function expansion select bit Reserved bit After Reset 000000112 Function RW PCLK0 0: f2 1: f1 RW PCLK1 (b4-b2) PCLK5 (b7-b6) 0: f2SIO 1: f1SIO Set to 0 Refer to Table 7.3 Set to 0 RW RW RW RW NOTE: 1. Write to this register after setting the PRC0 bit in PRCR register to 1 (write enable). Processeor Mode Register 2 (1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PM2 Bit Symbol PM20 PM21 Address 001E16 Bit Name Specifying wait when accessing SFR(2) System clock protective bit(3,4) After Reset XXX00000 2 Function 0: 2 waits 1: 1 wait 0: Clock is protected by PRCR register 1: Clock modification disabled 0: CPU clock is used for the watchdog timer count source 1: On-chip oscillator clock is used for the watchdog timer count source Set to 0 0: P85 function (NMI disabled) 1: NMI function RW RW RW PM22 WDT count source protective bit(3,5) RW (b3) PM24 (b7-b5) Reserved bit P85/NMI configuration bit(6,7) RW RW Nothing is assigned. When write, set to 0. When read, thecontent is undefined NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enable). 2. The PM20 bit becomes effective when PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20 bit when the PLC07 bit is set to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz. 3. Once this bit is set to 1, it cannot be cleared to 0 by program. 4. Writting to the following bits has no effect when the PM21 bit is set to 1: CM02 bit in the CM0 register CM05 bit in the CM0 register (main clock is not halted) CM07 bit in the CM0 register (CPU clock source does not change) CM10 bit in the CM1 register (stop mode is not entered) CM11 bit in the CM1 register (CPU clock source does not change) CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change) All bits in the PLC0 register (PLL frequency synthesizer setting do not change) Do not execute WAIT instruction when the PM21 bit is set to 1. 5. Setting the PM22 bit to 1 results in the following conditions: • The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or • The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source. • The CM10 bit in the CM1 register cannnot be written. (Writing 1 has no effect, stop mode is not entered.) • The watchdog timer does not stop in wait mode. 6. For NMI function, the PM24 bit must be set to 1(NMI function). Once this bit is set to 1, it cannot be set to 0 by program. 7. SD input is valid regardless of the PM24 setting. PLL clock) (system clock of count source selected by the CM21 bit is valid) Figure 7.6 PCLKR Register and PM2 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 52 of 458 M16C/29 Group 7. Clock Generation Circuit PLL Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 (1,2) Address 001C16 After Reset 0001X0102 001 Symbol PLC0 Bit Symbol Bit Name PLL multiplying factor (3) select bit b2 b1b0 Function 0 0 0: Do not set 0 0 1: Multiply by 2 0 1 0: Multiply by 4 0 1 1: 1 0 0: 1 0 1: Do not set 1 1 0: 1 1 1: RW RW RW RW PLC00 PLC01 PLC02 (b3) (b4) Nothing is assigned. If necessary, set to 0. When read, the content is undefined Reserved bit Set to 1 Set to 0 0: PLL Off 1: PLL On RW RW RW (b6-b5) Reserved bit PLC07 Operation enable bit (4) NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable). 2. When the PM21 bit in the PM2 register is 1 (clock modification disable), writing to this register has no effect. 3. These three bits can only be modified when the PLC07 bit is set to 0 (PLL turned off). The value once written to this bit cannot be modified. 4. Before setting this bit to 1 , set the CM07 bit to 0 (main clock), set bits CM17 to CM16 bits to 002 (main clock undivided mode), and set the CM06 bit to 0 (CM16 and CM17 bits enable). CAN0 Clock Select Register (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CCLKR 025F16 Address After Reset 0016 Bit Symbol CCLK0 CCLK1 CCLK2 CCLK3 (b7-b4) Bit Name b2 b1 b0 Function 0 0 0 No division 0 0 1: Divide-by-2 0 1 0: Divide-by-4 0 1 1: Divide-by-8 1 0 0: Divide-by-16 1 0 1: 1 1 0: Inhibited 1 1 1: 0: CAN0 CPU interface operating 1: CAN0 CPU interface in sleep RW RW RW RW RW RW CAN0 clock select bits(2) CAN0 CPU interface sleep bit(3) Nothing is assigned. If necessary, set to 0. When read, the content is 0 NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable). 2. Configuration of bits CCLK2 to CCLK0 can be done only when the Reset bit in the C0CTLR register is set to 1 (Reset/Initialization mode). 3. Before setting this bit to 1(CAN0 CPU interface in sleep), set the Sleep bit in C0CTLR register to 1 (Sleep mode). Figure 7.7 PLC0 Register and CCLKR register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 53 of 458 M16C/29 Group 7. Clock Generation Circuit The following describes the clocks generated by the clock generation circuit. 7.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The main clock oscillator circuit may also be configured by feeding an exter nally generated clock to the XIN pin. Figure 7.8 shows the examples of main clock connection circuit. The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to 1 (main clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or on-chip oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains on, XIN is pulled “H” to XOUT via the feedback resistor. During stop mode, all clocks including the main clock are turned off. Refer to “power control”. If the main clock is not used, it is recommended to connect the XIN pin to VCC to reduce power consumption during reset. MCU (Built-in Feedback Resistor) XIN Oscillator XOUT Rd(1) VSS CIN MCU (Built-in Feedback Resistor) XIN External Clock VCC VSS COUT XOUT Open NOTE: 1. Insert a damping resistor if required. Resistance value varies depending on the oscillator setting. Use resistance value recommended by the oscillator manufacturer. If the oscillator manufacturer recommends that a feedback resistor be added to the chip externally, insert a feedback resistor between XIN and XOUT. 2. The external clock should not be stopped when it is connected to the XIN pin and the main clock is selected as the CPU clock. Figure 7.8 Examples of Main Clock Connection Circuit Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 54 of 458 M16C/29 Group 7. Clock Generation Circuit 7.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 7.9 shows the examples of sub clock connection circuit. After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillator circuit. To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to 1 (sub clock) after the sub clock becomes oscillating stably. During stop mode, all clocks including the sub clock are turned off. Refer to “power control”. MCU (Built-in Feedback Resistor) XCIN Oscillator XCOUT RCd(1) VSS CCIN MCU (Built-in Feedback Resistor) XCIN External Clock VCC VSS CCOUT XCOUT Open NOTE: 1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting. Use values recommended by each oscillator manufacturer. Place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer recommends placing the resistor externally. Figure 7.9 Examples of Sub Clock Connection Circuit Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 55 of 458 M16C/29 Group 7. Clock Generation Circuit 7.3 On-chip Oscillator Clock This clock is supplied by a variable on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is 1 (on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to 10. Watchdog Timer • Count source protective mode”). After reset, the on-chip oscillator clock divided by 16 is used for the CPU clock. It can also be turned on by setting the CM21 bit in the CM2 register to 1 (on-chip oscillator clock), and is used as the clock source for the CPU and peripheral function clocks. If the main clock stops oscillating when the CM20 bit in the CM2 register is 1 (oscillation stop, re-oscillation detection function enabled) and the CM27 bit is 1 (oscillation stop, re-oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU. 7.4 PLL Clock The PLL clock is generated from the main clock by a PLL frequency synthesizer. This clock is used as the clock source for the CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthesizer is activated by setting the PLC07 bit to 1 (PLL operation). When the PLL clock is used as the clock source for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the CM11 bit in the CM1 register to 1. Before entering wait mode or stop mode, be sure to set the CM11 bit to 0 (CPU clock source is the main clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to 0 (PLL stops). Figure 7.10 shows the procedure for using the PLL clock as the clock source for the CPU. The PLL clock frequency is determined by the equation below. PLL clock frequency=f(XIN) X (multiplying factor set by bits PLC02 to PLC00 in the PLC0 register (However, 10 MHz ≤ PLL clock frequency ≤ 20 MHz) Bits PLC02 to PLC00 can be set only once after reset. Table 7.2 shows the example for setting PLL clock frequencies. Table 7.2 Example for Setting PLL Clock Frequencies XIN (MHz) 10 5 PLC02 0 0 PLC01 0 1 PLC00 1 0 Multiplying factor 2 4 PLL clock (MHz)(1) 20 NOTE: 1. 10MHz ≤ PLL clock frequency ≤ 20MHz. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 56 of 458 M16C/29 Group 7. Clock Generation Circuit START Set the CM07 bit to 0 (main clock), bits CM17 and CM16 to 002(main clock undivided), and the CM06 bit to 0 (bits CM17 and CM16 enabled). (1) Set bits PLC02 to PLC00 (multiplying factor). (To select a 16 MHz or higher PLL clock) Set the PM20 bit to 0 (2-wait states). Set the PLC07 bit to 1 (PLL operation). Wait until the PLL clock becomes stable (tsu(PLL)). Set the CM11 bit to 1 (PLL clock for the CPU clock source). END NOTE: 1. PLL operation mode can be entered from high speed mode. Figure 7.10 Procedure to Use PLL Clock as CPU Clock Source Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 57 of 458 M16C/29 Group 7. Clock Generation Circuit 7.5 CPU Clock and Peripheral Function Clock The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the peripheral functions. 7.5.1 CPU Clock This is the operating clock for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the PLL clock. If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in CM0 register and bits CM17 to CM16 in CM1 register to select the divide-by-n value. When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to 0 and bits CM17 and CM16 to 002 (undivided). After reset, the on-chip oscillator clock divided by 16 provides the CPU clock. Note that when entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to 1 (main clock turned off) in low-speed mode, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode). 7.5.2 Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32, fCAN0) These are operating clocks for the peripheral functions. Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock, or on-chip oscillator clock divided by i. The clock fi is used for Timer A, Timer B, SI/O3 and SI/O4 while fiSIO is used for UART0 to UART2. Additionally, the f1 and f2 clocks are also used for dead time timer, Timer S, multi-master I2C bus. The fAD clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the A/ D converter. The fCAN0 clock is derived from the main clock, PLL clock or on-chip oscillator clock devided by 1 (undivided), 2, 4, 8, or 16, and is used for the CAN module. When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function clock turned off during wait mode), or when the MCU is in low power dissipation mode, the fi, fiSIO, fAD, and fCAN0 clocks are turned off. (Note 1) The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can only be used when the sub clock is on. Note 1: fCAN0 clock stops at "H" in CAN0 sleep mode. 7.5.3 ClockOutput Function The f1, f8, f32 or fC clock can be output from the CLKOUT pin. Use the PCLK5 bit in the PCLKR register and bits CM01 to CM00 in the CM0 register to select. Table 7.3 shows the function of the CLKOUT pin. Table 7.3 The function of the CLKOUT pin PCLK5 0 0 0 0 1 1 1 1 CM01 0 0 1 1 0 0 1 1 CM00 0 1 0 1 0 1 0 1 page 58 of 458 The function of the CLKOUT pin I/O port P90 fC f8 f32 f1 Do not set Do not set Do not set Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 M16C/29 Group 7. Clock Generation Circuit 7.6 Power Control There are three power control modes. In this chapter, all modes other than wait and stop modes are referred to as normal operation mode. 7.6.1 Normal Operation Mode Normal operation mode is further classified into seven modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source must be in stable oscillation. If the new clock source is the main clock, sub clock or PLL clock, allow a sufficient wait time in a program until it becomes oscillating stably. Note that operation modes cannot be changed directly from low power dissipation mode to on-chip oscillator mode or on-chip oscillator low power dissipation mode. Nor can operation modes be changed directly from on-chip oscillator mode or on-chip oscillator low power dissipation mode to low power dissipation mode. When the CPU clock source is changed from the on-chip oscillator to the main clock, change the operation mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the CM06 bit in the CM0 register was set to 1) in the on-chip oscillator mode. 7.6.1.1 High-speed Mode The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the count source for timers A and B. 7.6.1.2 PLL Operation Mode The main clock multiplied by 2 or 4 provides the PLL clock, and this PLL clock serves as the CPU clock. If the sub clock is on, fC32 can be used as the count source for timers A and B. PLL operation mode can be entered from high speed mode. If PLL operation mode is to be changed to wait or stop mode, first go to high speed mode before changing. 7.6.1.3 Medium-speed Mode The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used as the count source for timers A and B. 7.6.1.4 Low-speed Mode The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral function clock when the CM21 bit is set to 0 (on-chip oscillator turned off), and the on-chip oscillator clock is used when the CM21 bit is set to 1 (on-chip oscillator oscillating). The fC32 clock can be used as the count source for timers A and B. 7.6.1.5 Low Power Dissipation Mode In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides the CPU clock. The fC32 clock can be used as the count source for timers A and B. Peripheral function clock can use only fC32. Simultaneously when this mode is selected, the CM06 bit in the CM0 register becomes 1 (divided by 8 mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium speed (divided by 8) mode is to be selected when the main clock is operated next. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 59 of 458 M16C/29 Group 7. Clock Generation Circuit 7.6.1.6 On-chip Oscillator Mode The selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, fC32 can be used as the count source for timers A and B. The on-chip oscillator frequency can be selected by bits ROCR3 to ROCR0 in the ROCR register. When the operation mode is returned to the high and medium speed modes, set the CM06 bit to 1 (divided by 8 mode). 7.6.1.7 On-chip Oscillator Low Power Dissipation Mode The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be selected as in the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the peripheral function clocks. If the sub clock is on, fC32 can be used as the count source for timers A and B. Table 7.4 Setting Clock Related Bit and Modes Modes PLL operation mode High-speed mode Mediumdivided by 2 speed divided by 4 mode divided by 8 divided by 16 Low-speed mode Low power dissipation mode divided by 1 On-chip divided by 2 oscillator divided by 4 mode(3) divided by 8 divided by 16 On-chip oscillator low power dissipation mode CM2 Register CM21 0 0 0 0 0 0 CM1 Register CM11 CM17, CM16 1 002 0 002 0 012 0 102 0 0 112 CM07 0 0 0 0 0 0 1 1 0 0 0 0 0 0 CM0 Register CM06 CM05 0 0 0 0 0 0 0 0 0 1 0 0 0 1(1) 1(1) 0 0 0 0 0 0 1 0 0 0 (2) 1 CM04 1 1 1 1 1 1 1 1 002 012 102 11 2 (2) NOTES: 1. When the CM05 bit is set to 1 (main clock turned off) in low-speed mode, the mode goes to low power dissipation mode and CM06 bit is set to 1(divided by 8 mode) simultaneously. 2. The divide-by-n value can be selected the same way as in on-chip oscillator mode. 3. On-chip oscillator frequency can be any of those described in the section 7.6.1.6 On-chip Oscillator Mode. 7.6.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. However, if the PM22 bit in the PM2 register is 1 (on-chip oscillator clock for the watchdog timer count source), the watchdog timer remains active. Because the main clock, sub clock, on-chip oscillator clock and PLL clock all are on, the peripheral functions using these clocks keep operating. 7.6.2.1 Peripheral Function Clock Stop Function When the CM02 bit is 1 (peripheral function clocks turned off during wait mode), f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, and fAD stop running in wait mode to reduce power consumption. However, fC32 remains active. 7.6.2.2 Entering Wait Mode The MCU enters wait mode by executing the WAIT instruction. When the CM11 bit is set to 1 (CPU clock source is the PLL clock), be sure to clear the CM11 bit to 0 (CPU clock source is the main clock) before going to wait mode. The power consumption of the chip can be reduced by clearing the PLC07 bit to 0 (PLL stops). Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 60 of 458 M16C/29 Group 7. Clock Generation Circuit 7.6.2.3 Pin Status During Wait Mode Table 7.5 lists pin status during wait mode. Table 7.5 Pin Status in Wait Mode Pin I/O ports When fC selected CLKOUT When f1, f8, f32 selected Status Retains status before wait mode Does not stop Does not stop when the CM02 bit is set to 0 Retains status before wait mode when the CM02 bit is set to 1 7.6.2.4 Exiting Wait Mode ______ The MCU exits from wait mode by a hardware reset, NMI interrupt, or peripheral function interrupt. ______ If wait mode is exited by a hardware reset or NMI interrupt, set the peripheral function interrupt priority bits ILVL2 to ILVL0 to 0002 (interrupts disabled) before executing the WAIT instruction. The CM02 bit affects the peripheral function interrupts. If the CM02 bit is 0 (peripheral function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit wait mode. If the CM02 bit is 1 (peripheral function clock stops during wait mode), the peripheral functions using the peripheral function clock stops operating, so that only the peripheral functions clocked by external signals can be used to exit wait mode. Table 7.6 lists the interrupts to exit wait mode. Table 7.6 Interrupts to Exit Wait Mode Interrupt NMI interrupt Serial I/O interrupt Multi-master I2C interrupt Key input interrupt A/D conversion interrupt Timer A interrupt Timer B interrupt Timer S interrupt _______ INT interrupt CAN0 wake_up interrupt CM02 = 0 Available Available when internal and external clocks are used Available Available Available in one-shot or single sweep mode Available in all modes Available in all modes Available Available in CAN sleep mode CM02 = 1 Available Available when external clock is used Do not used Available Do not use Available in event counter mode or when count source is fC32 Do not use Available Available in CAN sleep mode To use peripheral function interrupts to exit wait mode, set the followings before executing the WAIT instruction. 1. Set the interrupt priority level to the bits ILVL2 to ILVL0 in the interrupt control register of the peripheral function interrupts that are used to exit wait mode. Also, set bits ILVL2 to ILVL0 of all peripheral function interrupts that are not used to exit wait mode to 0002 (interrupt disabled). 2. Set the I flag to 1. 3. Operate the peripheral functions that are used to exit wait mode. When the peripheral function interrupts are used to exit wait mode, an interrupt routine is executed after an interrupt request is generated and the CPU is clocked. The CPU clock used when exiting wait mode by a peripheral function interrupt is the same CPU clock that is used when executing the WAIT instruction. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 61 of 458 M16C/29 Group 7. Clock Generation Circuit 7.6.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode. If the voltage applied to Vcc pin is VRAM or more, the internal RAM is retained. When applying 2.7 or less voltage to Vcc pin, make sure Vcc≥VRAM. However, the peripheral functions clocked by external signals keep operating. The following interrupts can be used to exit stop mode. ______ • NMI interrupt • Key interrupt ______ • INT interrupt • Timer A, Timer B interrupt (when counting external pulses in event counter mode) • Serial I/O interrupt (when external clock is selected) • Low voltage detection interrup (refer to "Low Voltage Detection Interrupt" for an operating condition) • CAN0 Wake_up interrupt (in CAN sleep mode) 7.6.3.1 Entering Stop Mode The MCU is placed into stop mode by setting the CM10 bit in the CM1 register to 1 (all clocks turned off). At the same time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the CM10 register is set to 1 (main clock oscillator circuit drive capability high). Before entering stop mode, set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disable). Also, if the CM11 bit is 1 (PLL clock for the CPU clock source), set the CM11 bit to 0 (main clock for the CPU clock source) and the PLC07 bit to 0 (PLL turned off) before entering stop mode. 7.6.3.2 Pin Status during Stop Mode The I/O pins retain their status held just prior to entering stop mode. 7.6.3.3 Exiting Stop Mode ______ The MCU is moved out of stop mode by a hardware reset, NMI interrupt or peripheral function interrupt. ______ If the MCU is to be moved out of stop mode by a hardware reset or NMI interrupt, set the peripheral function interrupt priority bits ILVL2 to ILVL0 to 0002 (interrupts disable) before setting the CM10 bit to 1. If the MCU is to be moved out of stop mode by a peripheral function interrupt, set up the following before setting the CM10 bit to 1. 1. In bits ILVL2 to ILVL0 of the interrupt control register, set the interrupt priority level of the peripheral function interrupt to be used to exit stop mode. Also, for all of the peripheral function interrupts not used to exit stop mode, set bits ILVL2 to ILVL0 to 0002. 2. Set the I flag to 1. 3. Enable the peripheral function whose interrupt is to be used to exit stop mode. In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an interrupt service routine is executed. Which CPU clock will be used after exiting stop mode by a peripheral function or NMI interrupt is determined by the CPU clock that was on when the MCU was placed into stop mode as follows: If the CPU clock before entering stop mode was derived from the sub clock: sub clock If the CPU clock before entering stop mode was derived from the main clock: main clock divide-by-8 If the CPU clock before entering stop mode was derived from the on-chip oscillator clock: on-chip oscillator clock divide-by-8 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 62 of 458 ______ M16C/29 Group 7. Clock Generation Circuit Figure 7.11 shows the state transition from normal operation mode to stop mode and wait mode. Figure 7.12 shows the state transition in normal operation mode. Table 7.7 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line shows state after transition. All oscillators stopped Normal operation mode CM10=1 (6) Interrupt Interrupt Stop mode CM07=0 CM06=1 CM05=0 CM11=0 CM10=1 (5) Medium-speed mode (divided-by-8 mode) WAIT instruction Interrupt WAIT instruction Interrupt CPU operation stopped Wait mode Stop mode CM10=1 (6) High-speed, mediumspeed mode (1, 2) Wait mode PLL operation mode CM10=1 (6) Stop mode Interrupt CM10=1 (6) WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction Interrupt Low-speed mode (7) Wait mode Stop mode Interrupt CM10=1 (6) CM21=0 Low power dissipation mode CM21=1 Wait mode Stop mode Interrupt (4) On-chip oscillator low power dissipation mode Wait mode On-chip oscillator mode (selectable frequency) Stop mode CM10=1(6) Interrupt (4) WAIT instruction Interrupt Wait mode On-chip oscillator mode (f 2(ROC)/16) CM05, CM06, CM07: Bits in the CM0 register CM10, CM11: Bits in the CM1 register Reset : Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown. NOTES: 1. Do not go directly from PLL operation mode to wait or stop mode. 2. PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode. 3. When the PM21 bit is set to 0 (system clock protective function unused). 4. The on-chip oscillator clock divided by 8 provides the CPU clock. 5. Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21 bit is set to 0 (on-chip oscillator turned off). When the clock generated externally is input to the XCIN pin, transit to stop mode with this process. 6. Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to 0 (oscillation stop and oscillation restart detection function disabled). 7. The CM06 bit is set to 1 (divide-by-8). Figure 7.11 State Transition to Stop Mode and Wait Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 63 of 458 M16C/29 Group 7. Clock Generation Circuit Main clock oscillation On-chip oscillator clock oscillation PLC07=1 CM11=1 (5) High-speed mode CPU clock: f(XIN) PLL operation mode CPU clock: f(PLL) CM07=0 CM06=0 CM17=0 CM16=0 Middle-speed mode (divide by 2) CPU clock: f(XIN)/2 Middle-speed mode (divide by 4) CPU clock: f(XIN)/4 Middle-speed mode Middle-speed mode (divide by 8) (divide by 16) CPU clock: f(XIN)/8 CPU clock: f(XIN)/16 On-chip oscillator mode CM21=0 (2, 6) CPU clock f(ROC) f(ROC)/2 f(ROC)/4 f(ROC)/8 f(ROC)/16 CM05=0 On-chip oscillator low power dissipation mode CPU clock f(ROC) f(ROC)/2 f(ROC)/4 f(ROC)/8 f(ROC)/16 CM07=0 CM06=0 PLC07=0 CM11=0 (5) CM17=0 CM16=0 CM07=0 CM06=0 CM17=0 CM16=1 CM07=0 CM06=0 CM17=1 CM16=0 CM07=0 CM06=1 CM07=0 CM06=0 CM17=1 CM16=1 CM21=1 CM05=1 (1) CM04=1 CM04=0 CM04=1 CM04=0 CM04=1 CM04=0 CM04=1 On-chip oscillator low power dissipation mode CM04=0 PLL operation mode CPU clock: f(PLL) CM07=0 CM06=0 CM17=0 CM16=0 PLC07=1 CM11=1 (5) High-speed mode CPU clock: f(XIN) Middle-speed mode (divide by 2) CPU clock: f(XIN)/2 Middle-speed mode (divide by 4) CPU clock: f(XIN)/4 Middle-speed mode Middle-speed mode (divide by 8) (divide by 16) CPU clock: f(XIN)/8 CPU clock: f(XIN)/16 On-chip oscillator mode CM21=0 (2, 6) CPU clock f(ROC) f(ROC)/2 f(ROC)/4 f(ROC)/8 f(ROC)/16 CM05=0 M M0 CM07=0 PLC07=0 CM11=0 (5) CM06=0 CM17=0 CM16=0 CM07=0 CM06=0 CM17=0 CM16=1 CM07=0 CM06=0 CM17=1 CM16=0 CM07=0 CM06=1 CM07=0 CM06=0 CM17=1 CM16=1 CM21=1 CPU clock f(ROC) f(ROC)/2 f(ROC)/4 f(ROC)/8 f(ROC)/16 CM05=1 (1) CM07=1 (3) Low-speed mode CPU clock: f(XCIN) CM07=1 (3) CM07=0 (2, 4) CM07=0 (4) Low-speed mode CPU clock: f(XCIN) CM21=0 CM07=0 CM21=1 CM07=0 CM05=1 (1, 7) Low power dissipation mode CPU clock: f(XCIN) CM05=0 CM07=0 CM06=1 CM15=1 Sub clock oscillation : Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown. NOTES: 1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled). Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting. 2. Wait for the main clock oscillation stabilization time before switching over. Set the CM15 bit in the CM1 register to 1 (drive capacity High) until main clock oscillation is stabilized. 3. Switch clock after oscillation of sub-clock is sufficiently stable. 4. Change bits CM17 and CM16 before changing the CM06 bit. 5. The PM20 bit in the PM2 register becomes effective when the PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20 bit when the PLC07 bit is set to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz. 6. Set the CM06 bit to 1 (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode. 7. When the CM21 bit is set to 0 (on-chip oscillator turned off) and the CM05 bit is set to 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode) and the CM15 bit is fixed to 1 (drive capability High). Figure 7.12 State Transition in Normal Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 64 of 458 M16C/29 Group 7. Clock Generation Circuit Table 7.7 Allowed Transition and Setting State after transition High-speed mode, Low-speed mode2 Low power middle-speed mode dissipation mode High-speed mode, middle-speed mode Low-speed mode2 Low power dissipation mode PLL operation mode2 On-chip oscillator mode On-chip oscillator low power dissipation mode Stop mode Wait mode PLL operation mode2 On-chip oscillator mode On-chip oscillator low power dissipation mode Stop mode Wait mode 8 (8) -(12)3 (14)4 -(18)5 (18) (9)7 -(11)1, 6 (13)3 --- (15) (8) --- ----(11)1 8 (18)5 (18) (16)1 (16)1 (16)1 -(16)1 (16)1 (17) (17) (17) -(17) (17) -- Current state (10) -(9)7 -(18) (18) ---(18) (18) ----- 8 (10) (18)5 (18) ---: Cannot transit NOTES: 1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled). Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting. 2. On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock. Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as a clock for the timers A and B. 3. PLL operation mode can only be entered from and changed to high-speed mode. 4. Set the CM06 bit to 1 (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode. 5. When exiting stop mode, the CM06 bit is set to 1 (division by 8 mode). 6. If the CM05 bit is set to 1 (main clock stop), then the CM06 bit is set to 1 (division by 8 mode). 7. A transition can be made only when sub clock is oscillating. 8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below. Sub clock oscillating No division No division Divided by 2 Divided by 4 Divided by 8 Divided by 16 Sub clock turned off Divided by 16 No division Divided by 2 Divided by 4 Divided Divided by 8 by 16 Divided by 2 (4) (4) (4) (4) -- Divided by 4 Divided by 8 (5) (5) (5) (5) --- (7) (7) (7) (7) ---(2) -- (6) (6) (6) (6) ----- (1) ----- -(1) ---(4) --- --- ----- Sub clock oscillating (3) (3) (3) (3) (2) ----- -(1) -(7) (7) (7) (1) --(5) (5) (1) (6) (6) (6) (6) No division Sub clock turned off Divided by 2 Divided by 4 Divided by 8 Divided by 16 (2) ---- (3) (3) (3) (3) (4) (4) (4) (2) --- (5) (5) (7) (2) 9. ( ) : setting method. Refer to following table. Setting Operation Sub clock turned off Sub clock oscillating CPU clock no division mode CPU clock division by 2 mode CPU clock division by 4 mode CPU clock division by 16 mode CPU clock division by 8 mode Main clock, PLL clock, or on-chip oscillator clock selected Sub clock selected Main clock oscillating Main clock turned off Main clock selected PLL clock selected Main clock or PLL clock selected On-chip oscillator clock selected Transition to stop mode Transition to wait mode Exit stop mode or wait mode --: Cannot transit (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) CM04 = 0 CM04 = 1 CM06 = 0, CM17 = 0 , CM16 = 0 CM06 = 0, CM17 = 0 , CM16 = 1 CM06 = 0, CM17 = 1 , CM16 = 0 CM06 = 0, CM17 = 1 , CM16 = 1 CM06 = 1 CM07 = 0 CM07 = 1 CM05 = 0 CM05 = 1 PLC07 = 0, CM11 = 0 PLC07 = 1, CM11 = 1 CM21 = 0 CM21 = 1 CM10 = 1 wait instruction Hardware interrupt CM04, CM05, CM06, CM07 CM10, CM11, CM16, CM17 CM20, CM21 PLC07 : Bits in the CM0 register : Bits in the CM1 register : Bits in the CM2 register : Bit in the PLC0 register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 65 of 458 M16C/29 Group 7. Clock Generation Circuit 7.7 System Clock Protective Function When the main clock is selected for the CPU clock source, this function protects the clock from modifications in order to prevent the CPU clock from becoming halted by run-away. If the PM21 bit in the PM2 register is set to 1 (clock modification disabled), the following bits are protected against writes: • Bits CM02, CM05, and CM07 in CM0 register • Bits CM10 and CM11 in CM1 register • CM20 bit in CM2 register • All bits in the PLC0 register Before the system clock protective function can be used, the following register settings must be made while the CM05 bit in the CM0 register is 0 (main clock oscillating) and CM07 bit is 0 (main clock selected for the CPU clock source): (1) Set the PRC1 bit in the PRCR register to 1 (enable writes to PM2 register). (2) Set the PM21 bit in the PM2 register to 1 (disable clock modification). (3) Set the PRC1 bit in the PRCR register to 0 (disable writes to PM2 register). Do not execute the WAIT instruction when the PM21 bit is 1. 7.8 Oscillation Stop and Re-oscillation Detect Function The oscillation stop and re-oscillation detect function detects the re-oscillation after stop of main clock oscillation circuit. When the oscillation stop and re-oscillation detection occurs, the oscillation stop detect function is reset or oscillation stop and re-oscillation detection interrupt is generated, depending on the CM27 bit set in the CM2 register. The oscillation stop detect function is enabled or disabled by the CM20 bit in the CM2 register. Table 7.8 lists a specification overview of the oscillation stop and re-oscillation detect function. Table 7.8 Specification Overview of Oscillation Stop and Re-oscillation Detect Function Item Specification Oscillation stop detectable clock and f(XIN) ≥ 2 MHz frequency bandwidth Enabling condition for oscillation stop, Set CM20 bit to 1(enable) re-oscillation detection function Operation at oscillation stop, •Reset occurs (when CM27 bit =0) re-oscillation detection •Oscillation stop, re-oscillation detection interrupt occurs(when CM27 bit =1) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 66 of 458 M16C/29 Group 7. Clock Generation Circuit 7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) When main clock stop is detected when the CM20 bit is 1 (oscillation stop, re-oscillation detection function enabled), the MCU is initialized, coming to a halt (oscillation stop reset; refer to “SFR”, “Reset”). This status is reset with hardware reset 1. Also, even when re-oscillation is detected, the MCU can be initialized and stopped; it is, however, necessary to avoid such usage. (During main clock stop, do not set the CM20 bit to 1 and the CM27 bit to 0.) 7.8.2 Operation When CM27 bit = 1 (Oscillation Stop and Re-oscillation Detect Interrupt) When the main clock corresponds to the CPU clock source and the CM20 bit is 1 (oscillation stop and reoscillation detect function enabled), the system is placed in the following state if the main clock comes to a halt: • Oscillation stop and re-oscillation detect interrupt request occurs. • The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the CPU clock and clock source for peripheral functions in place of the main clock. • CM21 bit = 1 (on-chip oscillator clock for CPU clock source) • CM22 bit = 1 (main clock stop detected) • CM23 bit = 1 (main clock stopped) When the PLL clock corresponds to the CPU clock source and the CM20 bit is 1, the system is placed in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to 1 (on-chip oscillator clock) inside the interrupt routine. • Oscillation stop and re-oscillation detect interrupt request occurs. • CM22 bit = 1 (main clock stop detected) • CM23 bit = 1 (main clock stopped) • CM21 bit remains unchanged When the CM20 bit is 1, the system is placed in the following state if the main clock re-oscillates from the stop condition: • Oscillation stop and re-oscillation detect interrupt request occurs. • CM22 bit = 1 (main clock re-oscillation detected) • CM23 bit = 0 (main clock oscillation) • CM21 bit remains unchanged Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 67 of 458 M16C/29 Group 7. Clock Generation Circuit 7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer interrupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt. • Where the main clock re-oscillated after oscillation stop, return the main clock to the CPU clock and peripheral function clock source by program. Figure 7.13 shows the procedure for switching the clock source from the on-chip oscillator to the main clock. • Simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the CM22 bit becomes 1. When the CM22 bit is set at 1, oscillation stop, re-oscillation detection interrupt are disabled. By setting the CM22 bit to 0 by program, oscillation stop, re-oscillation detection interrupt are enabled. • If the main clock stops during low speed mode where the CM20 bit is 1, an oscillation stop, re-oscillation detection interrupt request is generated. At the same time, the on-chip oscillator starts oscillating. In this case, although the CPU clock is derived from the sub clock as it was before the interrupt occurred, the peripheral function clocks now are derived from the on-chip oscillator clock. • To enter wait mode while using the oscillation stop, re-oscillation detection function, set the CM02 bit to 0 (peripheral function clocks not turned off during wait mode). • Since the oscillation stop, re-oscillation detection function is provided in preparation for main clock stop due to external factors, set the CM20 bit to 0 (Oscillation stop, re-oscillation detection function disabled) where the main clock is stopped or oscillated by program, that is where the stop mode is selected or the CM05 bit is altered. • This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit to 0. Switch to the main clock No Determine several times whether the CM23 bit is set to 0 (main clock oscillates) Yes Set the CM06 bit to 1 (divide-by-8 mode) Set the CM22 bit to 0 ("oscillatin stop, re-oscillation" not detected) Set the CM21 bit to 0 (main clock or PLL clock) CM06: Bit in the CM0 register CM23 to CM21: Bits in the CM2 register End NOTE: 1. If the clock source for CPU clock is to be changed to PLL clock, set to PLL operation mode after set to high-speed mode. Figure 7.13 Procedure to Switch Clock Source From On-chip Oscillator to Main Clock Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 68 of 458 M16C/29 Group 8. Protection 8. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by the PRCR register. • Registers protected by the PRC0 bit: CM0, CM1, CM2, PLC0, ROCR, PCLKR, and CCLKR • Registers protected by the PRC1 bit: PM0, PM1, PM2, TB2SC, INVC0, and INVC1 • Registers protected by the PRC2 bit: PD9 , PACR, S4C, and NDDR • Registers protected by the PRC3 bit: VCR2 and D4INT The PRC2 bit is set to 0 (write enabled) when data is written to the SFR area after setting the PRC2 bit to 1 (write enable). Set registers PD9, PACR, S4C and NDDR immediately after setting the PRC2 bit in the PRCR register to 1 (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to 1 and the following instruction. Bits PRC3, PRC1, and PRC0 are not set to 0 even if data is written to the SFR area. Set bits PRC3, PRC1, and PRC0 to 0 by program. Protect Register b7 b6 00 b5 b4 b3 b2 b1 b0 Symbol PRCR Bit Symbol PRC0 Address 000A16 Bit Name Protect bit 0 After Reset XX0000002 Function Enable write to register CM0, CM1, CM2, ROCR, PLC0, PCLKR, and CCLKR 0: Write protected 1: Write enabled Enable write to registers PM0, PM1, PM2, TB2SC, INVC0, and INVC1 0: Write protected 1: Write enabled RW RW PRC1 Protect bit 1 RW PRC2 Protect bit 2 Enable write to registers PD9, PACR, S4C, and NDDR 0: Write protected 1: Write enabled(1) RW PRC3 Protect bit 3 Enable write to registers VCR2 and D4INT 0: Write protected 1: Write enabled Set to 0 RW (b5-b4) (b7-b6) Reserved bit RW Nothing is assigned. If necessary, set to 0. When read, its content is undefined NOTE: 1. The PRC2 bit is set to 0 when writing into the SFR area after the PRC2 bit is set to 1. Bits PRC0, PRC1, and PRC3 are not automatically set to 0. Set them to 0 by program. Figure 8.1 PRCR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 69 of 458 M16C/29 Group 9. Interrupts 9. Interrupts Note The SI/O4 interrupt of peripheral function interrupts is not available in the 64-pin package. The low voltage detection function is not available in M16C/29 T-ver. and V-ver.. 9.1 Type of Interrupts Figure 9.1 shows types of interrupts. Software (Non-maskable interrupt) Interrupt Special (Non-maskable interrupt) Hardware Peripheral function (1) (Maskable interrupt) NOTES: 1. Peripheral function interrupts are generated by the MCU's internal functions. 2. Do not normally use this interrupt because it is provided exclusively for use by development tools. Figure 9.1 Interrupts • Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. • Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 70 of 458               Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction _______                    ________ NMI DBC (2) Watchdog timer Oscillation stop and re-oscillation detection Low voltage detection Single step (2) Address match M16C/29 Group 9. Interrupts 9.1.1 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 9.1.1.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 9.1.1.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to 1 (the operation resulted in an overflow). The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB 9.1.1.3 BRK Interrupt A BRK interrupt occurs when executing the BRK instruction. 9.1.1.4 INT Instruction Interrupt An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63 can be specified for the INT instruction. Because software interrupt Nos. 1 to 31 are assigned to peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by executing the INT instruction. In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is cleared to 0 (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state during instruction execution, and the SP then selected is used. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 71 of 458 M16C/29 Group 9. Interrupts 9.1.2 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 9.1.2.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 9.1.2.1.1 NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details _______ about the NMI interrupt, refer to the section "NMI interrupt". ________ 9.1.2.1.2 DBC Interrupt This interrupt is exclusively for debugger, do not use in any other circumstances. 9.1.2.1.3 Watchdog Timer Interrupt Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the watchdog timer. For details about the watchdog timer, refer to the section "watchdog timer". 9.1.2.1.4 Oscillation Stop and Re-oscillation Detection Interrupt Generated by the oscillation stop and re-oscillation detection function. For details about the oscillation stop and re-oscillation detection function, refer to the section "clock generating circuit". 9.1.2.1.5 Low Voltage Detection Interrupt Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to the section "voltage detection circuit". 9.1.2.1.6 Single-step Interrupt Do not normally use this interrupt because it is provided exclusively for use by development tools. 9.1.2.1.7 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMAD0 or RMAD1 register, if the corresponding enable bit (AIER0 or AIER1 bit in the AIER register) is set to 1. For details about the address match interrupt, refer to the section “address match interrupt”. 9.1.2.2 Peripheral Function Interrupts Peripheral function interrupts are maskable interrupts and generated by the MCU's internal functions. The interrupt sources for peripheral function interrupts are listed in Table 9.2 Relocatable Vector Tables. For details about the peripheral functions, refer to the description of each peripheral function in this manual. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 72 of 458 M16C/29 Group 9. Interrupts 9.2 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 9.2 shows the interrupt vector. MSB LSB Low address Mid address 0000 High address 0000 Vector address (L) Vector address (H) 0000 Figure 9.2 Interrupt Vector 9.2.1 Fixed Vector Tables The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 9.1 lists the fixed vector tables. In the flash memory version of MCU, the vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to the section "flash memory rewrite disabling function". Table 9.1 Fixed Vector Tables Vector table addresses Remarks Address (L) to address (H) Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction Overflow FFFE016 to FFFE316 Interrupt on INTO instruction If the contents of address BRK instruction FFFE416 to FFFE716 FFFE716 is FF16, program execution starts from the address shown by the vector in the relocatable vector table Address match FFFE816 to FFFEB16 Single step (1) FFFEC16 to FFFEF16 Watchdog timer FFFF016 to FFFF316 Oscillation stop and re-oscillation detection, low voltage detection ________ DBC (1) FFFF416 to FFFF716 _______ NMI FFFF816 to FFFFB16 Reset(2) FFFFC16 to FFFFF16 Interrupt source Reference M16C/60, M16C/20 serise software maual Address match interrupt Watchdog timer, clock generating circuit, voltage detection circuit _______ NMI interrupt Reset NOTE: 1. Do not normally use this interrupt because it is provided exclusively for use by development tools. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 73 of 458 M16C/29 Group 9. Interrupts 9.2.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 9.2 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses. Table 9.2 Relocatable Vector Tables Interrupt source BRK instruction (2) CAN0 wakeup (3) CAN0 receive completion CAN0 transmit completion INT3 IC/OC interrupt 0 IC/OC interrupt 1, SI/O4, INT5 (5) SI/O3, DMA0 DMA1 CAN0 state, error A/D, Key input interrupt (7) UART2 transmit, UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 INT0 INT1 INT2 Software interrupt (2) NACK2 (8) INT4 (5) UART 2 bus collision detection (6) I 2C bus interface (4) IC/OC base timer, S CL/SDA(4) Vector address (1) Address (L) to address (H) +0 to +3 (0000 16 to 0003 16) +4 to +7 (0004 16 to 0007 16) +8 to +11 (0008 16 to 000B 16) +12 to +15 (000C 16 to 000F 16 ) +16 to +19 (0010 16 to 0013 16) +20 to +23 (0014 16 to 0017 16) +24 to +27 (0018 16 to 001B 16) +28 to +31 (001C 16 to 001F 16 ) +32 to +35 (0020 16 to 0023 16) +36 to +39 (0024 16 to 0027 16) +40 to +43 (0028 16 to 002B 16) +44 to +47 (002C 16 to 002F 16 ) +48 to +51 (0030 16 to 0033 16) +52 to +55 (0034 16 to 0037 16) +56 to +59 (0038 16 to 003B 16) +60 to +63 (003C 16 to 003F 16 ) +64 to +67 (0040 16 to 0043 16) +68 to +71 (0044 16 to 0047 16) +72 to +75 (0048 16 to 004B 16) +76 to +79 (004C 16 to 004F 16 ) +80 to +83 (0050 16 to 0053 16) +84 to +87 (0054 16 to 0057 16) +88 to +91 (0058 16 to 005B 16) +92 to +95 (005C 16 to 005F 16 ) +96 to +99 (0060 16 to 0063 16) +100 to +103 (0064 16 to 0067 16) +104 to +107 (0068 16 to 006B 16) +108 to +111 (006C 16 to 006F 16) +112 to +115 (0070 16 to 0073 16) +116 to +119 (0074 16 to 0077 16) +120 to +123 (0078 16 to 007B 16) +124 to +127 (007C 16 to 007F 16) +128 to +131 (0080 16 to 0083 16) to +252 to +255 (00FC 16 to 00FF 16) Software interrupt number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 to 63 M16C/60, M16C/20 series software manual INT interrupt Timer Serial I/O INT interrupt Timer S Timer S Multi-Master I 2C bus interface INT interrupt Serial I/O Serial I/O DMAC CAN module A/D convertor, Key input interrupt CAN module Reference M16C/60, M16C/20 series software manual UART2 receive, ACK2 (8) NOTES: 1. Address relative to address in INTB. 2. These interrupts cannot be disabled using the I flag. 3. Set the IFSR22 bit in the IFSR register to 0. 4. Use bits IFSR26 and IFSR27 in the IFSR2A register to select. 5. Use bits IFSR6 and IFSR7 in the IFSR register to select. 6. Bus collision detection: In IEBus mode, this bus collision detection constitutes the cause of an interrupt. In I2C bus mode, however, a start condition or a stop condition detection constitutes the cause of an interrupt. 7. Use the IFSR21 bit in the IFSR2A register to select. 8. During I2C bus mode, NACK and ACK interrupts comprise the interrupt source. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 74 of 458 M16C/29 Group 9. Interrupts 9.3 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use I flag in the the FLG register, IPL, and bits ILVL2 to ILVL0 in the each interrupt control register to enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 9.3 shows the interrupt control registers. Also, the following interrupts share a vector and an interrupt control register. •INT4 and SIO3 ________ •INT5 and SIO4 •A/D converter and key input interrupt •IC/OC base timer and SCL/SDA •IC/OC interrupt 1 and I2C bus interface An interrupt request is set by bits IFSR6 and IFSR7 in the IFSR register and bits IFSR27, IFSR26, and IFSR21 in the IFSR2A register. Figure 9.4 shows registers IFSR register and IFSR2A. ________ Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 75 of 458 M16C/29 Group 9. Interrupts Interrupt Control Register(2) Symbol C01WKIC C0RECIC C0TRMIC ICOC0IC ICOC1IC, IICIC(3) BTIC, SCLDAIC(3) BCNIC DM0IC, DM1IC C01ERRIC ADIC, KUPIC(3) S0TIC to S2TIC S0RIC to S2RIC TA0IC to TA4IC TB0IC to TB2IC Address 004116 004216 004316 004516 004616 004716 004A16 004B16, 004C16 004D16 004E16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005916 005A16 to 005C16 After reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 RW RW RW b b4 b3 b2 b1 b0 Bit Symbol ILVL0 Bit Name Interrupt priority level select bit b2 b1 b0 Function 000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 ILVL1 ILVL2 RW RW(1) IR Interrupt request bit 0: Interrupt not requested 1: Interrupt requested (b7-b4) Nothing is assigned. If necessary, set to 0. When read, the contents are undefined NOTES: 1. This bit can only be reset by writing 0 (Do not write 1). 2. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that register. For details, refer to 22. 4 Interrupts. 3. Use the IFSR2A register to select. Symbol Address After reset INT3IC 004416 XX00X0002 b b4 b3 b2 b1 b0 S4IC, INT5IC 004816 XX00X0002 S3IC, INT4IC 004916 XX00X0002 0 INT0IC to INT2IC 005D16 to 005F16 XX00X0002 Bit Symbol ILVL0 Bit Name Interrupt priority level select bit b2 b1 b0 Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0: Selects falling edge (3, 4) 1: Selects rising edge Set to 0 RW RW ILVL1 RW ILVL2 RW RW(1) IR POL Interrupt request bit Polarity select bit Reserved bit RW RW (b5) (b7-b6) Nothing is assigned. If necessary, set to 0. When read, the contents are undefined NOTES: 1. This bit can only be reset by writing 0 (Do not write 1). 2. To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, refer to 22.4 Interrupts. 3. If the IFSRi bit in the IFSR register (i = 0 to 5) is 1 (both edges), set the POL bit in the INTiIC register to 0 (falling edge). 4. Set the POL bit in register S3IC or S4IC to 0 (falling edge) when the IFSR6 bit in the IFSR register is set to 0 (SI/O3 selected) or IFSR7 bit in the IFSR register to 0 (SI/O4 selected), respectively. Figure 9.3 Interrupt Control Registers C01WKIC, 0RECI ,C0TRMIC, OC0I ,CO 1IC, IC,BTIC,S LDAIC,B NIC,DM0IC,DM1IC, 01ER IC,ADIC,KUPIC,S0TICtoS2TIC,S0RICtoS2RIC,TA0ICtoTA4IC,TB0ICtoTB2IC,NT3IC,S4IC,NT5IC,S31C,INT4IC,NT0ICtoINT2ICRegister Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 76 of 458 M16C/29 Group 9. Interrupts Interrupt Request Cause Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Address 035F16 After Reset 0016 Bit Symbol IFSR0 IFSR1 IFSR2 IFSR3 IFSR4 IFSR5 IFSR6 IFSR7 Bit Name INT0 interrupt polarity switching bit INT1 interrupt polarity switching bit INT2 interrupt polarity switching bit INT3 interrupt polarity switching bit INT4 interrupt polarity switching bit INT5 interrupt polarity switching bit Interrupt request cause select bit Interrupt request cause select bit Function 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : SI/O3 1 : INT4 0 : SI/O4 1 : INT5 (2) (1) RW RW RW RW RW RW RW RW RW (1) (1) (1) (1) (1) (2) NOTES: 1. When setting this bit to 1 (both edges), make sure the POL bit in registers INT0IC to INT5IC is set to 0 (falling edge). 2. When setting this bit to 0 (SI/O3, SI/O4), make sure the POL bit in registers S3IC and S4IC is set to 0 (falling edge). Interrupt Request Cause Select Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol IFSR2A Bit Symbol IFSR20 IFSR21 IFSR22 (b5-b3) IFSR26 IFSR27 Address 035E 16 After reset 00XXX000 2 Bit Name Reserved bit Interrupt request cause select bit Interrupt request cause select bit Set to 0 Function RW RW RW RW 0: A/D conversion 1: Key input 0: CAN0 wakeup/error 1: Do not set Nothing is assigned. If necessary, set to 0. When read, the contents are undefined Interrupt request cause select bit Interrupt request cause select bit 0: IC/OC base timer 1: SCL/SDA 0: IC/OC interrupt 1 1: I2C bus interface RW RW Figure 9.4 IFSR Register and IFSR2A Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 77 of 458 M16C/29 Group 9. Interrupts 9.3.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (= enabled) enables the maskable interrupt. Setting the I flag to 0 (= disabled) disables all maskable interrupts. 9.3.2 IR Bit The IR bit is set to 1 (= interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to 0 (= interrupt not requested). The IR bit can be cleared to 0 in a program. Note that do not write 1 to this bit. 9.3.3 ILVL2 to ILVL0 Bits and IPL Interrupt priority levels can be set using bits ILVL2 to ILVL0. Table 9.3 shows the settings of interrupt priority levels and Table 9.4 shows the interrupt priority levels enabled by the IPL. The following are conditions under which an interrupt is accepted: · I flag = 1 · IR bit = 1 · interrupt priority level > IPL The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. In no case do they affect one another. Table 9.3 Settings of Interrupt Priority Levels ILVL2 to ILVL0 bits Interrupt priority level Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Low Priority order Table 9.4 Interrupt Priority Levels Enabled by IPL IPL 0002 0012 0102 0112 1002 1012 1102 1112 Enabled interrupt priority levels Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled 0002 0012 0102 0112 1002 1012 1102 1112 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 78 of 458 M16C/29 Group 9. Interrupts 9.4 Interrupt Sequence An interrupt sequence (the device behavior from the instant an interrupt is accepted to the instant the interrupt routine is executed) is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. The CPU behavior during the interrupt sequence is described below. Figure 9.5 shows time required for executing the interrupt sequence. (1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the address 0000016. Then it clears the IR bit for the corresponding interrupt to 0 (interrupt not requested). (2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal temporary register(Note). (3) The I, D and U flags in the FLG register become as follows: The I flag is cleared to 0 (interrupts disabled). The D flag is cleared to 0 (single-step interrupt disabled). The U flag is cleared to 0 (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is executed. (4) The CPU’s internal temporary register(1) is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the accepted interrupt is set in the IPL. (7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, the processor resumes executing instructions from the start address of the interrupt routine. NOTE: 1. This register cannot be used by user. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CPU clock Address bus Data bus RD WR(2) NOTES: 1. The undefined state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to accept instructions. 2. When the stack is in the internal RAM, the WR signal indicates the write timing by changing high-level to low-level. Address 000016 Interrupt information Undefined(1) Undefined(1) Undefined(1) SP-2 SP-2 contents SP-4 SP-4 contents vec vec contents vec+2 vec+2 contents PC Figure 9.5 Time Required for Executing Interrupt Sequence Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 79 of 458 M16C/29 Group 9. Interrupts 9.4.1 Interrupt Response Time Figure 9.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of the time from when an interrupt request is generated till when the instruction then executing is completed ((a) in Figure 9.6) and the time during which the interrupt sequence is executed ((b) in Figure 9.6). Interrupt request generated Interrupt request acknowledged Time Instruction (a) Interrupt sequence (b) Instruction in interrupt routine Interrupt response time (a) The time from when an interrupt request is generated till when the instruction then executing is completed. The length of this time varies with the instruction being executed. The DIVX instruction requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register). (b) The time during which the interrupt sequence is executed. For details, see the table below. Note, however, that the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and single-step interrupts. Interrupt vector address SP value Even Even Odd Odd Even Odd Even Odd Without wait 18 cycles 19 cycles 19 cycles 20 cycles Figure 9.6 Interrupt response time 9.4.2 Variation of IPL when Interrupt Request is Accepted When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table 9.5 is set in the IPL. Shown in Table 9.5 are the IPL values of software and special interrupts when they are accepted. Table 9.5 IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted Interrupt sources Watchdog timer, NMI, Oscillation stop and re-oscillation detection, Low volage detection Software, address match, DBC, single-step _________ _______ IPL setting 7 No change Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 80 of 458 M16C/29 Group 9. Interrupts 9.4.3 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 9.7 shows the stack status before and after an interrupt request is accepted. The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the PUSHM instruction, and all registers except SP can be saved with a single instruction. Address MSB Stack LSB Address MSB Stack LSB [SP] New SP value m–4 m–3 m–2 m–1 m m+1 Content of previous stack Content of previous stack m–4 m–3 m–2 m–1 m m+1 FLG H PCL PCM FLG L PCH [SP] SP value before interrupt request is accepted. Content of previous stack Content of previous stack Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Figure 9.7 Stack Status Before and After Acceptance of Interrupt Request Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 81 of 458 M16C/29 Group 9. Interrupts The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP(1), at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (1) is even, the FLG register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 9.8 shows the operation of the saving registers. NOTE: 1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the U flag. Otherwise, it is the ISP. (1) SP contains even number Address Stack Sequence in which order registers are saved [SP] – 5 (Odd) [SP] – 4 (Even) [SP] – 3 (Odd) [SP] – 2 (Even) [SP] – 1 (Odd) [SP] (Even) FLG H PCL PCM FLG L PCH (1) Saved simultaneously, all 16 bits (2) Saved simultaneously, all 16 bits Finished saving registers in two operations. (2) SP contains odd number Address Stack Sequence in which order registers are saved [SP] – 5 (Even) [SP] – 4 (Odd) [SP] – 3 (Even) [SP] – 2 (Odd) [SP] – 1 (Even) [SP] (Odd) Finished saving registers in four operations. FLG H PCL PCM FLG L PCH (3) (4) (1) (2) Saved, 8 bits at a time NOTE: 1. [SP] denotes the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Figure 9.8 Operation of Saving Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 82 of 458 M16C/29 Group 9. Interrupts 9.4.4 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request. Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction before executing the REIT instruction. 9.5 Interrupt Priority If two or more interrupt requests are generated while executing one instruction, the interrupt request that has the highest priority is accepted. For maskable interrupts (peripheral functions), any desired priority level can be selected using bits ILVL2 to ILVL0. However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, with the highest priority interrupt accepted. The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 9.9 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine. Reset NMI DBC Watchdog timer, oscillation stop, re-oscillation detection, low voltage detection Peripheral function Single step Address match High Low Figure 9.9 Hardware Interrupt Priority 9.5.1 Interrupt Priority Resolution Circuit The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those requested. Figure 9.10 shows the circuit that judges the interrupt priority level. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 83 of 458 M16C/29 Group 9. Interrupts Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 ICOC interrupt 1, I 2C bus interface INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 ICOC base timer, S CL/SDA ICOC interrupt 0 UART1 reception UART0 reception UART2 reception, ACK2 A/D conversion, Key input interrupt DMA1 UART 2 bus collision SI/O4, INT5 Timer A0 UART1 transmission UART0 transmission UART2 transmission, NACK2 CAN 0 error DMA0 SI/O3, INT4 CAN 0 transmission CAN 0 reception CAN 0 wakeup IPL Level 0 (initial value) Highest Priority of peripheral function interrupts (if priority levels are same) Lowest Interrupt request level resolution output to clock generating circuit (See Figure.7.1 ) I flag Address match Watchdog timer Oscillation stop and re-oscillation detection Low voltage detection DBC NMI Interrupt request accepted Figure 9.10 Interrupts Priority Select Circuit Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 84 of 458 M16C/29 Group ______ 9. Interrupts 9.6 INT Interrupt _______ INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in the IFSR register. ________ The INT5 input has an effective digital debounce function for a noise rejection. Refer to "19.6 Digital ________ Debounce function" for this detail. When using INT5 interrupt to exit stop mode, set the P17DDR register to FF16 before entering stop mode. ________ ________ ________ To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to 1 (INT4). To use the INT5 interrupt, set ________ the IFSR7 bit in the IFSR register to 1 (INT5). After modifiying bit IFSR6 or IFSR7, clear the corresponding IR bit to 0 (interrupt not requested) before enabling the interrupt. Figure 9.11 shows the IFSR registers. Interrupt Request Cause Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Address 035F16 After Reset 0016 Bit Symbol IFSR0 IFSR1 IFSR2 IFSR3 IFSR4 IFSR5 IFSR6 IFSR7 Bit Name INT0 interrupt polarity switching bit INT1 interrupt polarity switching bit INT2 interrupt polarity switching bit INT3 interrupt polarity switching bit INT4 interrupt polarity switching bit INT5 interrupt polarity switching bit Interrupt request cause select bit Interrupt request cause select bit Function 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : SI/O3 1 : INT4 0 : SI/O4 1 : INT5 (2) (1) RW RW RW RW RW RW RW RW RW (1) (1) (1) (1) (1) (2) NOTES: 1. When setting this bit to 1 (both edges), make sure the POL bit in registers INT0IC to INT5IC is set to 0 (falling edge). 2. When setting this bit to 0 (SI/O3, SI/O4), make sure the POL bit in registers S3IC and S4IC is set to 0 (falling edge). Figure 9.11 IFSR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 85 of 458 M16C/29 Group ______ 9. Interrupts 9.7 NMI Interrupt _______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the _______ ______ NMI interrupt was enabled by writing a 1 to bit 4 in the register PM2. The NMI interrupt is a non-maskable interrupt, once it is enabled. _______ The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register. _______ NMI is disabled by default after reset (the pin is a GPIO pin, P85) and can be enabled using bit 4 in the PM2 register. Once enabled, it can only be disabled by a reset signal. _______ The NMI input has a digital debounce function for noise rejection. Refer to "19.6 Digital Debounce func_______ tion" for details. When using NMI interrupt to exit stop mode, set the NDDR register to FF16 before entering stop mode. _______ 9.8 Key Input Interrupt A key input interrupt is generated when input on any of the P104 to P107 pins which has had bits PD10_7 to PD10_4 in the PD10 register set to 0 (= input) goes low. Key input interrupts can be used for a key-on wakeup function to get the MCU to exit stop or wait modes. However, if you intend to use the key input interrupt, do not use P104 to P107 as analog input ports. Figure 9.12 shows the block diagram of the key input interrupt. Note, however, that while input on any pin which has had bits PD10_7 to PD10_4 set to 0 (= input mode) is pulled low, inputs on all other pins of the port are not detected as interrupts. Pull-up transistor PU25 bit in the PUR2 register PD10_7 bit in the PD10 register PD10_7 bit in the PD10 register KUPIC register KI3 Pull-up transistor KI2 Pull-up transistor KI1 Pull-up transistor KI0 PD10_4 bit in the PD10 register PD10_5 bit in the PD10 register PD10_6 bit in the PD10 register Interrupt control circuit Key input interrupt request Figure 9.12 Key Input Interrupt Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 86 of 458 M16C/29 Group 9. Interrupts 9.9 CAN0 Wake-up Interrupt CAN0 wake-up interrupt occurs when a falling edge is input to CRX. The CAN0 wake-up interrupt is enabled when the PortEn bit is set to 1 (CTX/CRX function) and Sleep bit is set to 1(Sleep mode enabled) in the C0CTLR register. Figure 9.13 shows the block diagram of the CAN0 wake-up interrupt. C01WKIC register Sleep bit in C0CTLR register PortEn bit in C0CTLR register CRX Interrupt control circuit CAN0 wake-up interrupt request Figure 9.13 CAN0 Wake-up Interrupt Block Diagram 9.10 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi register. Use bits AIER1 and AIER0 in the AIER register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the PC that is saved to the stack area varies depending on the instruction being executed (refer to “Saving Registers”). (The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one of the methods described below to return from the address match interrupt. • Rewrite the content of the stack and then use the REIT instruction to return. • Restore the stack to its previous state before the interrupt request was accepted by using the POP or similar other instruction and then use a jump instruction to return. Table 9.6 shows the value of the PC that is saved to the stack area when an address match interrupt request is accepted. aFigure 9.14 shows registers AIER, RMAD0, and RMAD1. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 87 of 458 M16C/29 Group 9. Interrupts Table 9.6 PC Value Saved in Stack Area When Address Match Interrupt Request Is Acknowledged Instruction at the address indicated by the RMADi register • 2-byte op-code instruction • 1-byte op-code instructions which are followed: ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B #IMM8,dest STNZ.B #IMM8,dest STZX.B #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (However, dest=A0 or A1) Instructions other than the above Value of the PC that is saved to the stack area The address indicated by the RMADi register +2 The address indicated by the RMADi register +1 Value of the PC that is saved to the stack area : Refer to “Saving Registers”. Op-code is an abbreviation of Operation Code. It is a portion of instruction code. Refer to Chapter 4 Instruction Code/Number of Cycles in M16C/60, M16C/20 Series Software Manual. Op-code is shown as a bold-framed figure directly below the Syntax. Table 9.7 Relationship Between Address Match Interrupt Sources and Associated Registers Address match interrupt sources Address match interrupt enable bit Address match interrupt register Address match interrupt 0 AIER0 RMAD0 Address match interrupt 1 AIER1 RMAD1 Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit Symbol Address 000916 Bit Name Address match interrupt 0 enable bit Address match interrupt 1 enable bit After Reset XXXXXX00 2 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW RW RW AIER0 AIER1 (b7-b2) Nothing is assigned. If necessary, set to 0. When read, the content is undefined Address Match Interrupt Register i (i = 0 to 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Address 001216 to 0010 16 001616 to 0014 16 After Reset X00000 16 X00000 16 Function Address setting register for address match interrupt Nothing is assigned. If necessary, set to 0. When read, the content is undefined Setting Range 00000 16 to FFFFF 16 RW RW Figure 9.14 AIER Register, RMAD0 and RMAD1 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 88 of 458 M16C/29 Group 10. Watchdog Timer 10. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after reaching the terminal count can be selected using the PM12 bit in the PM1 register. The PM12 bit can only be set to 1 (reset). Once this bit is set to 1, it cannot be set to 0 (watchdog timer interrupt) in a program. Refer to 5.3 Watchdog Timer Reset for the details of watchdog timer reset. When the main clock source is selected for CPU clock, on-chip oscillator clock, PLL clock, the WDC7 bit in the WDC register value for prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU clock, the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calculated as given below. The period of watchdog timer is, however, subject to an error due to the prescaler. With main clock source chosen for CPU clock, on-chip oscillator clock, PLL clock Watchdog timer period = Prescaler dividing (16 or 128) X Watchdog timer count (32768) CPU clock With sub-clock chosen for CPU clock Prescaler dividing (2) X Watchdog timer count (32768) Watchdog timer period = CPU clock For example, when CPU clock is set to 16 MHz and the divide-by-N value for the prescale ris set to 16, the watchdog timer period is approx. 32.8 ms. The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start counting by writing to the WDTS register. Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the beginning of the watchdog timer interrupt routine. In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related registers. Prescaler 1/16 CPU clock CM07 = 0 WDC7 = 0 CM07 = 0 WDC7 = 1 PM12 = 0 PM22 = 0 1/128 1/2 Watchdog timer interrupt request CM07 = 1 PM22 = 1 Watchdog timer PM12 = 1 Reset On-chip oscillator clock Set to 7FFF16 Write to WDTS register Internal reset signal (low active) Figure 10.1 Watchdog Timer Block Diagram Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 89 of 458 M16C/29 Group 10. Watchdog Timer Watchdog Timer Control Register b7 b6 00 b5 b4 b3 b2 b1 b0 Symbol WDC Bit Symbol (b4-b0) (b5) (b6) WDC7 Address 000F16 Bit Name After Reset 00XXXXXX2 Function RW RO RW RW RW High-order bits of watchdog timer Reserved bit Reserved bit Prescaler select bit Set to 0 Set to 0 0 : Divided by 16 1 : Divided by 128 Watchdog Timer Start Register b7 b0 Symbol WDTS Address 000E16 Function After Reset Undefined RW WO The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to 7FFF16 regardless of whatever value is written. Figure 10.2 WDC Register and WDTS Register 10.1 Count Source Protective Mode In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer can be kept being clocked even when CPU clock stops as a result of run-away. Before this mode can be used, the following register settings are required: (1) Set the PRC1 bit in the PRCR register to 1 (enable writes to PM1 and PM2 registers). (2) Set the PM12 bit in the PM1 register to 1 (reset when the watchdog timer underflows). (3) Set the PM22 bit in the PM2 register to 1 (on-chip oscillator clock used for the watchdog timer count source). (4) Set the PRC1 bit in the PRCR register to 0 (disable writes to PM1 and PM2 registers). (5) Write to the WDTS register (watchdog timer starts counting). Setting the PM22 bit to 1 results in the following conditions • The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or PLL clock) (system clock of count source selected by the CM21 bit is valid) • The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source. Watchdog timer count (32768) Watchdog timer period = on-chip oscillator clock • The CM10 bit in the CM1 register is disabled against write. (Writing a 1 has no effect, nor is stop mode entered.) • The watchdog timer does not stop when in wait mode. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 90 of 458 M16C/29 Group 11. DMAC 11. DMAC Note Do not use SI/O4 interrupt request as a DMA request in the 64-pin package. The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address. The DMAC uses the same data bus as used by the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after a DMA request is generated. Figure 11.1 shows the block diagram of the DMAC. Table 11.1 shows the DMAC specifications. Figures 11.2 to 11.4 show the DMAC-related registers. Address bus DMA0 source pointer SAR0(20) (addresses 0022 16 to 0020 16) DMA0 destination pointer DAR0 (20) (addresses 0026 16 to 0024 16) DMA0 forward address pointer (20) DMA0 transfer counter reload register TCR0 (16) (1) DMA1 source pointer SAR1 (20) (addresses 0032 16 to 0030 16) DMA1 destination pointer DAR1 (20) (addresses 0036 16 to 0034 16) (addresses 0029 16, 0028 16) DMA0 transfer counter TCR0 (16) DMA1 transfer counter reload register TCR1 (16) DMA1 forward address pointer (20) DMA latch high-order bits (1) (addresses 0039 16, 0038 16) DMA1 transfer counter TCR1 (16) DMA latch low-order bits Data bus low-order bits Data bus high-order bits NOTE: 1. Pointer is incremented by a DMA request. Figure 11.1 DMAC Block Diagram A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0,1), as well as by an interrupt request which is generated by any function specified by the DMS and bits DSEL3 to DSEL0 in the DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer. A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register is set to 1 (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA transfer cycle, the number of transfer requests generated and the number of times data is transferred may not match. For details, refer to “DMA Requests”. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 91 of 458 M16C/29 Group 11. DMAC Table 11.1 DMAC Specifications Item No. of channels Transfer memory space Specification 2 (cycle steal method) • From any address in the 1M bytes space to a fixed address • From a fixed address to any address in the 1M bytes space • From a fixed address to a fixed address 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) ________ ________ Maximum No. of bytes transferred DMA request factors (1, 2) Falling edge of INT0 or INT1 ________ ________ Both edge of INT0 or INT1 Timer A0 to timer A4 interrupt requests Timer B0 to timer B2 interrupt requests UART0 transfer, UART0 reception interrupt requests UART1 transfer, UART1 reception interrupt requests UART2 transfer, UART2 reception interrupt requests SI/O3, SI/O4 interrupt requests A/D conversion interrupt requests Timer S(IC/OC) requests Software triggers Channel priority DMA0 > DMA1 (DMA0 takes precedence) Transfer unit 8 bits or 16 bits Transfer address direction forward or fixed (The source and destination addresses cannot both be in the forward direction) Transfer mode Single transfer Transfer is completed when the DMAi transfer counter (i = 0,1) underflows after reaching the terminal count Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value of the DMAi transfer counter reload register and a DMA transfer is con tinued with it DMA interrupt request generation timing When the DMAi transfer counter underflowed DMA startup Data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMAiCON register = 1 (enabled) DMA shutdown Single transfer • When the DMAE bit is set to 0 (disabled) • After the DMAi transfer counter underflows Repeat transfer When the DMAE bit is set to 0 (disabled) Reload timing for forward ad- When a data transfer is started after setting the DMAE bit to 1 (en dress pointer and transfer abled), the forward address pointer is reloaded with the value of the counter SARi or the DARi pointer whichever is specified to be in the forward direction and the DMAi transfer counter is reloaded with the value of the DMAi transfer counter reload register NOTES: 1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the interrupt control register. 2. The selectable causes of DMA requests differ with each channel. 3. Make sure that no DMAC-related registers (addresses 002016 to 003F16) are accessed by the DMAC. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 92 of 458 M16C/29 Group 11. DMAC DMA0 Request Cause Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL Bit Symbol DSEL0 DSEL1 DSEL2 DSEL3 (b5-b4) DMS Bit Name Address 03B816 After Reset 0016 Function RW RW DMA request cause select bit Refer to note (1) RW RW RW Nothing is assigned. When write, set to 0. When read, their content are 0 DMA request cause expansion select bit 0: Basic cause of request 1: Extended cause of request A DMA request is generated by setting this bit to 1 when the DMS bit is 0 (basic cause) and bits DSEL3 to DSEL0 are 00012 (software trigger). The value of this bit when read is 0 RW DSR Software DMA request bit RW NOTE: 1. The causes of DMA0 requests can be selected by a combination of DMS bit and bits DSEL3 to DSEL0 in the manner described below. DSEL3 to DSEL0 0 0 0 02 0 0 0 12 0 0 1 02 0 0 1 12 0 1 0 02 0 1 0 12 0 1 1 02 0 1 1 12 1 0 0 02 1 0 0 12 1 0 1 02 1 0 1 12 1 1 0 02 1 1 0 12 1 1 1 02 1 1 1 12 DMS=0(basic cause of request) Falling edge of INT0 pin Software trigger Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 UART0 transmit UART0 receive UART2 transmit UART2 receive A/D conversion UART1 transmit DMS=1(extended cause of request) IC/OC base timer – IC/OC channel 0 IC/OC channel 1 – – Two edges of INT0 pin – – – IC/OC channel 2 IC/OC channel 3 IC/OC channel 4 IC/OC channel 5 IC/OC channel 6 IC/OC channel 7 Figure 11.2 DM0SL Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 93 of 458 M16C/29 Group 11. DMAC DMA1 Request Cause Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM1SL Bit Symbol DSEL0 DSEL1 DSEL2 DSEL3 (b5-b4) DMS Bit Name Address 03BA16 After Reset 0016 Function RW RW RW RW RW DMA request cause select bit Refer to note (1) Nothing is assigned. If necessary, set to 0. When read, their contents are 0 DMA request cause expansion select bit Software DMA request bit 0: Basic cause of request 1: Extended cause of request A DMA request is generated by setting this bit to 1 when the DMS bit is 0 (basic cause) and the DSEL3 to DSEL0 bits are 0001 2 (software trigger). The value of this bit when read is 0 RW DSR RW NOTES: 1. The causes of DMA1 requests can be selected by a combination of DMS bit and bits DSEL3 to DSEL0 in the manner described below. DSEL3 to DSEL0 0 0 0 02 0 0 0 12 0 0 1 02 0 0 1 12 0 1 0 02 0 1 0 12 0 1 1 02 0 1 1 12 1 0 0 02 1 0 0 12 1 0 1 02 1 0 1 12 1 1 0 02 1 1 0 12 1 1 1 02 1 1 1 12 DMS=0(basic cause of request) Falling edge of INT1 pin Software trigger Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 UART0 transmit UART0 receive UART2 transmit UART2 receive/ACK2 A/D conversion UART1 receive DMS=1(extended cause of request) IC/OC base timer – IC/OC channel 0 IC/OC channel 1 – SI/O3 SI/O4 Two edges of INT1 – – IC/OC channel 2 IC/OC channel 3 IC/OC channel 4 IC/OC channel 5 IC/OC channel 6 IC/OC channel 7 DMAi Control Register(i=0,1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0CON DM1CON Bit Symbol DMBIT DMASL DMAS DMAE DSD DAD (b7-b6) Bit Name Address 002C16 003C16 After Reset 00000X002 00000X002 Function 0: 16 bits 1: 8 bits 0: Single transfer 1: Repeat transfer 0: DMA not requested 1: DMA requested 0: Disabled 1: Enabled 0: Fixed 1: Forward 0: Fixed 1: Forward RW RW RW RW (1) Transfer unit bit select bit Repeat transfer mode select bit DMA request bit DMA enable bit Source address direction select bit (2) Destination address direction select bit (2) RW RW RW Nothing is assigned. If necessary, set to 0. When read, their contents are 0 NOTES: 1. The DMAS bit can be set to 0 by writing 0 by program (This bit remains unchanged even if 1 is written). 2. At least one of bits DAD and DSD must be set to 0 (address direction fixed). Figure 11.3 DM1SL Register, DM0CON Register, and DM1CON Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 94 of 458 M16C/29 Group 11. DMAC DMAi Source Pointer (i = 0, 1) (1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 002216 to 0020 16 003216 to 0030 16 Setting Range After Reset Undefined Undefined RW RW Function Set the source address of transfer 00000 16 to FFFFF 16 Nothing is assigned. If necessary, set 0. When read, the contents are 0 NOTE: 1. If the DSD bit in the DMiCON register is 0 (fixed), this register can only be written to when the DMAE bit in the DMiCON register is set to 0 (DMA disabled). If the DSD bit is set to 1 (forward direction), this register can be written to at any time. If the DSD bit is set to 1 and the DMAE bit is set to 1 (DMA enabled), the DMAi forward address pointer can be read from this register. Otherwise, the value written to it can be read. DMAi Destination Pointer (i = 0, 1)(1) (b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0 Symbol DAR0 DAR1 Address 002616 to 0024 16 003616 to 0034 16 After Reset Undefined Undefined RW RW Function Set the destination address of transfer Setting Range 00000 16 to FFFFF 16 Nothing is assigned. If necessary, set 0. When read, the contents are 0 NOTE: 1. If the DAD bit in the DMiCON register is 0 (fixed), this register can only be written to when the DMAE bit in the DMiCON register is set to 0 (DMA disabled). If the DAD bit is set to 1 (forward direction), this register can be written to at any time. If the DAD bit is set to 1 and the DMAE bit is set to 1 (DMA enabled), the DMAi forward address pointer can be read from this register. Otherwise, the value written to it can be read. DMAi Transfer Counter (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol TCR0 TCR1 Address 0029 16, 0028 16 0039 16, 0038 16 After Reset Undefined Undefined Setting Range RW Function Set the transfer count minus 1. The written value is stored in the DMAi transfer counter reload register, and when the DMAE bit in the DMiCON register is set to 1 (DMA enabled) or the DMAi transfer counter underflows when the DMASL bit in the DMiCON register is 1 (repeat transfer), the value of the DMAi transfer counter reload register is transferred to the DMAi transfer counter. When read, the DMAi transfer counter is read 0000 16 to FFFF 16 RW Figure 11.4 SAR0, SAR1, DAR0, DAR1, TCR0, and TCR1 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 95 of 458 M16C/29 Group 11. DMAC 11.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer. Furthermore, the bus cycle itself is extended by a software wait. 11.1.1 Effect of Source and Destination Addresses If the transfer unit is 16 bits and the source address of transfer begins with an odd address, the source read cycle consists of one more bus cycle than when the source address of transfer begins with an even address. Similarly, if the transfer unit is 16 bits and the destination address of transfer begins with an odd address, the destination write cycle consists of one more bus cycle than when the destination address of transfer begins with an even address. 11.1.2 Effect of Software Wait For memory or SFR accesses in which one or more software wait states are inserted, the number of bus cycles required for that access increases by an amount equal to software wait states. Figure 11.5 shows the example of the cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for the source read and the destination write cycle, respectively. For example, when data is transferred in 16 bit units and when both the source address and destination address are an odd address ((2) in Figure 11.5), two source read bus cycles and two destination write bus cycles are required. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 96 of 458 M16C/29 Group 11. DMAC (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address CPU clock Address bus RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use (2) When the transfer unit is 16 bits and the source address of transfer is an odd address. CPU clock Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use (3) When the source read cycle under condition (1) has one wait state inserted CPU clock Address bus RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use (4) When the source read cycle under condition (2) has one wait state inserted CPU clock Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use NOTE: 1. The same timing changes occur with the respective conditions at the destination as at the source. Figure 11.5 Transfer Cycles for Source Read Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 97 of 458 M16C/29 Group 11. DMAC 11.2. DMA Transfer Cycles Any combination of even or odd transfer read and write adresses is possible. Table 11.2 shows the number of DMA transfer cycles. Table 11.3 shows the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 11.2 DMA Transfer Cycles Transfer unit Access address 8-bit transfers Even (DMBIT= 1) Odd 16-bit transfers Even (DMBIT= 0) Odd No. of read cycles 1 1 1 2 No. of write cycles 1 1 1 2 Table 11.3 Coefficient j, k Internal Area Internal ROM, RAM No wait j k 1 1 With wait 2 2 SFR 2 wait 1 wait (1) (1) 2 2 3 3 NOTE: 1. Depends on the set value of PM20 bit in PM2 register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 98 of 458 M16C/29 Group 11. DMAC 11.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to 1 (enabled), the DMAC operates as follows: (a) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register is 1 (forward) or the DARi register value when the DAD bit in the DMiCON register is 1 (forward). (b) Reload the DMAi transfer counter with the DMAi transfer counter reload register value. If the DMAE bit is set to 1 again while it remains set, the DMAC performs the above operation. However, if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below. (1) Write 1 to bits DMAE and DMAS in DMiCON register simultaneously. (2) Make sure that the DMAi is in an initial state as described above (a) and (b) by program. If the DMAi is not in an initial state, the above steps should be repeated. 11.4 DMA Request The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS bit and bits DSEL3 to DSEL0 in the DMiSL register (i = 0, 1) on either channel. Table 11.4 shows the timing at which the DMAS bit changes state. Whenever a DMA request is generated, the DMAS bit is set to 1 (DMA requested) regardless of whether or not the DMAE bit is set. If the DMAE bit was set to 1 (enabled) when this occurred, the DMAS bit is set to 0 (DMA not requested) immediately before a data transfer starts. This bit cannot be set to 1 by program (it can only be set to 0). The DMAS bit may be set to 1 when the DMS or the DSEL3 to DSEL0 bits change state. Therefore, always be sure to set the DMAS bit to 0 after changing the DMS or the DSEL3 to DSEL0 bits. Because if the DMAE bit is set to 1, a data transfer starts immediately after a DMA request is generated, the DMAS bit in almost all cases is 0 when read by program. Read the DMAE bit to determine whether the DMAC is enabled. Table 11.4 Timing at Which the DMAS Bit Changes State DMAS Bit in the DMiCON Register DMA Factor Timing at which the bit is set to 1 Timing at which the bit is set to 0 Software trigger Peripheral function When the DSR bit in the DMiSL register is set to 1 When the interrupt control register for the peripheral function that is selected by bits DSEL3 to DSEL0 and the DMS bit in the DMiSL register has its IR bit set to 1 • Immediately before a data transfer starts • When set by writing 0 by program Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 99 of 458 M16C/29 Group 11. DMAC 11.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of CPU clock), the DMAS bit on each channel is set to 1 (DMA requested) at the same time. In this case, the DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period. Figure 11.6 shows an example of DMA transfer effected by external factors. DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request are generated simultanelously. After one DMA0 transfer is completed, a bus arbitration is returned to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is completed, the bus arbitration is again returned to the CPU. In addition, DMA requsts cannot be counted up since each channel has one DMAS bit. Therefore, when DMA requests, as DMA1 in Figure 11.6 occurs more than one time, the DAMS bit is set to 0 as soon as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed. An example where DMA requests for external causes are detected active at the same CPU clock DMA0 DMA1 CPU INT0 DMA0 request bit INT1 DMA1 request bit Obtainment of the bus right Figure 11.6 DMA Transfer by External Factors Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 100 of 458 M16C/29 Group 12. Timers 12. Timers Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (three). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. Figures 12.1 and 12.2 show block diagrams of timer A and timer B configuration, respectively. • Main clock f1 • PLL clock • On-chip oscillator clock 1/2 1/8 f2 PCLK0 bit = 0 f1 or f2 PCLK0 bit = 1 1/4 f8 f32 XCIN Set the CPSR bit in the CPSRF register to 1 (prescaler reset) Clock prescaler 1/32 Reset fC32 f1 or f2 f8 f32 fC32 • Timer mode • One-shot timer mode • Pulse Width Measuring (PWM) mode TA0IN Noise filter Timer A0 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A0 interrupt TA1IN Noise filter Timer A1 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A1 interrupt TA2IN Noise filter Timer A2 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A2 interrupt TA3IN Noise filter Timer A3 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A3 interrupt TA4IN Noise filter Timer A4 • Event counter mode Timer A4 interrupt Timer B2 overflow or underflow Figure 12.1 Timer A Configuration Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 101 of 458 M16C/29 Group 12. Timer • Main clock f1 • PLL clock • On-chip oscillator clock 1/2 1/8 f2 PCLK0 bit = 0 f1 or f2 PCLK0 bit = 1 1/4 f8 f32 XCIN Set the CPSR bit in the CPSRF register to 1 (prescaler reset) Clock prescaler 1/32 Reset fC32 f1 or f2 f8 f32 fC32 Timer B2 overflow or underflow ( to Timer A count source) • Timer mode • Pulse width measuring mode, pulse period measuring mode TB0IN Noise filter Timer B0 • Event counter mode • Timer mode • Pulse width measuring mode, pulse period measuring mode Timer B0 interrupt TB1IN Noise filter Timer B1 • Event counter mode • Timer mode • Pulse width measuring mode, pulse period measuring mode Timer B1 interrupt TB2IN Noise filter Timer B2 interrupt Timer B2 • Event counter mode Figure 12.2. Timer B Configuration Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 102 of 458 M16C/29 Group 12. Timer A 12.1 Timer A Figure 12.3 shows a block diagram of the timer A. Figures 12.4 to 12.6 show registers related to the timer A. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function. Use bits TMOD1 to TMOD0 in the TAiMR register (i = 0 to 4) to select the desired mode. • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts pulses from an external device or overflows and underflows of other timers. • One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count 000016. • Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively. Data bus high-order bits f1 or f 2 f8 f32 fC32 Clock source selection • Timer • One shot • PWM • Timer (gate function) • Event counter Clock selection Data bus low-order bits Low-order 8 bits Reload register High-order 8 bits TAiIN (i = 0 to 4) Polarity selection Clock selection (1) (1) To external trigger circuit Decrement Counter Increment/decrement TABSR register Always counts down except in event counter mode TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 038716 - 038616 038916 - 038816 038B16 - 038A16 038D16 - 038C 16 038F 16 - 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 TB2 overflow TAj overflow (j = i – 1. however, j = 4 when i = 0) TAk overflow UDF register (k = i + 1. however, k = 0 when i = 4) TAi OUT Pulse output (i = 0 to 4) Toggle flip-flop NOTE: 1. Overflow or underflow Figure 12.3 Timer A Block Diagram Timer Ai Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0MR to TA4MR Address 0396 16 to 039A 16 After Reset 0016 Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Bit Name Operation mode select bit b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode Function varies with each operation mode RW RW RW RW RW RW RW Count source select bit Function varies with each operation mode RW RW Figure 12.4 TA0MR to TA4MR Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 103 of 458 M16C/29 Group 12. Timer A Timer Ai Register (i= 0 to 4) (1) (b15) b7 (b8) b0 b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Function Address 0387 16, 0386 16 0389 16, 0388 16 038B 16, 038A 16 038D 16, 038C 16 038F 16, 038E 16 After Reset Undefined Undefined Undefined Undefined Undefined Setting Range 000016 to FFFF16 000016 to FFFF16 000016 to FFFF16 (2, 4) Mode Timer mode Event counter mode RW RW RW WO Divide the count source by n + 1 where n = set value Divide the count source by FFFF16 – n + 1 where n = set value when counting up or by n + 1 when counting down(5) Divide the count source by n where n = set One-shot timer mode value and cause the timer to stop Pulse width Modify the pulse width as follows: modulation PWM period: (216 – 1) / fj mode High level PWM pulse width: n / fj where n = set (16-bit PWM) value, fj = count source frequency Pulse width Modify the pulse width as follows: modulation PWM period: (28 – 1) x (m + 1)/ fj High level PWM pulse width: (m + 1)n / fj where mode (8-bit PWM) n = high-order address set value, m = low-order address set value, fj = count source frequency 000016 to FFFE16 (3, 4) WO 0016 to FE16 (High-order address) WO 0016 to FF16 (Low-order address) (3, 4) NOTES: 1. The register must be accessed in 16 bit units. 2. If the TAi register is set to 000016, the counter does not work and timer Ai interrupt requests are not generated either. Furthermore, if “pulse output” is selected, no pulses are output from the TAiOUT pin. 3. If the TAi register is set to 000016, the pulse width modulator does not work, the output level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated either. The same applies when the 8 high-order bits of the timer TAi register are set to 000016 while operating as an 8-bit pulse width modulator. 4. Use the MOV instruction to write to the TAi register. 5. The timer counts pulses from an external device or overflows or underflows in other timers. Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Address 0380 16 Bit Name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag After Reset 0016 Function 0 : Stops counting 1 : Starts counting RW RW RW RW RW RW RW RW RW Up/Down Flag (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Bit Symbol TA0UD TA1UD TA2UD TA3UD TA4UD TA2P TA3P TA4P Address 038416 Bit Name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag Timer A2 two-phase pulse signal processing select bit Timer A3 two-phase pulse signal processing select bit Timer A4 two-phase pulse signal processing select bit After Reset 0016 Function 0: Down count 1: Up count Enabled by setting the MR2 bit in the TAiMR register to 0 (= switching source in UDF register) during event counter mode 0: two-phase pulse signal processing disabled 1: two-phase pulse signal processing enabled (2, 3) RW RW RW RW RW RW WO WO WO NOTES: 1. Use MOV instruction to write to this register. 2. Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set to 0 input mode. 3. When the two-phase pulse signal processing function is not used, set the corresponding bit to 0. Figure 12.5 TA0 to TA4 Registers, TABSR Register, and UDF Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 104 of 458 M16C/29 Group 12. Timer A One-shot Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol ONSF Bit Symbol TA0OS TA1OS TA2OS TA3OS TA4OS TAZIE TA0TGL Address 038216 Bit Name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag Z-phase input enable bit Timer A0 event/trigger select bit After Reset 0016 Function The timer starts counting by setting this bit to 1 while bits TMOD1 and TMOD0 in the TAiMR register (i = 0 to 4) = 10 2 (= one-shot timer mode) and the MR2 bit in the TAiMR register = 0 (=TAiOS bit enabled). When read, its content is 0 0: Z-phase input disabled 1: Z-phase input enabled b7 b6 RW RW RW RW RW RW RW RW RW TA0TGH 0 0: Input on TA0 IN is selected (1) 0 1: TB2 overflow is selected (2) 1 0: TA4 overflow is selected (2) 1 1: TA1 overflow is selected (2) NOTES: 1. Make sure the PD7_1 bit in the PD7 register is set to 0 (input mode). 2. Overflow or underflow. Trigger Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Bit Symbol TA1TGL TA1TGH TA2TGL TA2TGH TA3TGL TA3TGH TA4TGL TA4TGH Address 038316 Bit Name Timer A1 event/trigger select bit After Reset 0016 Function 0 0: Input on TA1 IN is selected (1) 0 1: TB2 is selected (2) 1 0: TA0 is selected (2) 1 1: TA2 is selected (2) 0 0: Input on TA2 IN is selected (1) 0 1: TB2 is selected (2) 1 0: TA1 is selected (2) 1 1: TA3 is selected (2) b5 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW Timer A2 event/trigger select bit Timer A3 event/trigger select bit 0 0: Input on TA3 IN is selected (1) 0 1: TB2 is selected (2) 1 0: TA2 is selected (2) 1 1: TA4 is selected (2) b7 b6 Timer A4 event/trigger select bit 0 0: Input on TA4 IN is selected (1) 0 1: TB2 is selected (2) 1 0: TA3 is selected (2) 1 1: TA0 is selected (2) NOTES: 1. Make sure the port direction bits for the TA1IN to TA4IN pins are set to 0 ( input mode). 2. Overflow or underflow. Clock Prescaler Reset Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Bit Symbol (b6-b0) CPSR Address 038116 Bit Name After Reset 0XXXXXXX 2 Function RW Nothing is assigned. If necessary, set to 0. When read, their contents are undefined Clock prescaler reset flag Setting this bit to 1 initializes the prescaler for the timekeeping clock. (When read, its content is 0 ) RW Figure 12.6 ONSF Register, TRGSR Register, and CPSRF Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 105 of 458 M16C/29 Group 12. Timer A 12.1.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.1). Figure 12.7 shows TAiMR register in timer mode. Table 12.1 Specifications in Timer Mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Specification f1, f2, f8, f32, fC32 • Decrement • When the timer underflows, it reloads the reload register contents and continues counting 1/(n+1) n: set value of TAi register (i= 0 to 4) 000016 to FFFF16 Set TAiS bit in the TABSR register to 1 (start counting) Set TAiS bit to 0 (stop counting) Timer underflow I/O port or gate input I/O port or pulse output Count value can be read by reading TAi register • When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter • When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) • Gate function Counting can be started and stopped by an input signal to TAiIN pin • Pulse output function Whenever the timer underflows, the output polarity of TAiOUT pin is inverted. When not counting, the pin outputs a low. Select function Timer Ai Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 MR0 Address 0396 16 to 039A 16 Bit Name After Reset 0016 Function RW RW RW RW Operation mode select bit Pulse output function select bit Gate function select bit 0 0: Timer mode 0: Pulse is not output (TA iOUT pin is a normal port pin) 1: Pulse is output (TA iOUT pin is a pulse output pin) 0 0: Gate function not available } (TAi IN pin functions as I/O port) 0 1: 1 0: Counts while input on the TAi IN pin is low (1) 1 1: Counts while input on the TAi IN pin is high (1) b7 b6 b4 b3 b1 b0 MR1 RW MR2 RW RW MR3 TCK0 TCK1 Set to 0 in timer mode Count source select bit 0 0: f1 or f2 0 1: f8 1 0: f32 1 1: fC32 RW RW NOTE: 1. The port direction bit for the TAi IN pin must be set to 0 ( input mode). Figure 12.7 Timer Ai Mode Register in Timer Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 106 of 458 M16C/29 Group 12. Timer A 12.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3, and A4 can count two-phase external signals. Table 12.2 lists specifications in event counter mode (when not processing two-phase pulse signal). Table 12.3 lists specifications in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4). Figure 12.8 shows TAiMR register in event counter mode (when not processing two-phase pulse signal). Figure 12.9 shows TA2MR to TA4MR registers in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4). Table 12.2 Specifications in Event Counter Mode (when not processing two-phase pulse signal) Item Specification Count source • External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected in program) • Timer B2 overflows or underflows, timer Aj (j=i-1, except j=4 if i=0) overflows or underflows, timer Ak (k=i+1, except k=0 if i=4) overflows or underflows Count operation • Increment or decrement can be selected by external signal or program • When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. Divided ratio 1/ (FFFF16 - n + 1) for increment 1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16 Count start condition Set TAiS bit in the TABSR register to 1 (start counting) Count stop condition Set TAiS bit to 0 (stop counting) Interrupt request generation timing Timer overflow or underflow TAiIN pin function I/O port or count source input TAiOUT pin function I/O port, pulse output, or up/down-count select input Read from timer Count value can be read by reading TAi register Write to timer • When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter • When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) Select function • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it • Pulse output function Whenever the timer underflows or underflows, the output polarity of TAiOUT pin is inverted . When not counting, the pin outputs a low. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 107 of 458 M16C/29 Group 12. Timer A Timer Ai Mode Register (i=0 to 4) (When not using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 b1 b0 0 01 Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 MR0 Address 0396 16 to 039A 16 After Reset 0016 Function RW RW (1) Bit Name Operation mode select bit Pulse output function select bit Count polarityselect bit (2) Up/down switching cause select bit Count operation type select bit b1 b0 0 1 : Event counter mode RW RW RW 0: Pulse is not output (TA iOUT pin functions as I/O port) 1: Pulse is output (TAi OUT pin functions as pulse output pin) MR1 MR2 MR3 TCK0 TCK1 0: Counts external signal's falling edge 1: Counts external signal's rising edge 0: UDF register 1: Input signal to TAiOUT pin(3) 0: Reload type 1: Free-run type RW RW RW RW RW Set to 0 in event counter mode Can be 0 or 1 when not using two-phase pulse signal processing NOTES: 1. During event counter mode, the count source can be selected using registers ONSF and TRGSR. 2. Effective when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are 002 (TAiIN pin input). 3. Decrement when input on TAiOUT pin is low or increment when input on that pin is high. The port direction bit for TAiOUT pin must be set to 0 (input mode). Figure 12.8 TAiMR Register in Event Counter Mode (when not using two-phase pulse signal processing) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 108 of 458 M16C/29 Group 12. Timer A Table 12.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4) Item Count source Count operation Specification • Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 2 to 4) • Increment or down-count can be selected by two-phase pulse signal • When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the timer continues counting without reloading. 1/ (FFFF16 - n + 1) for increment 1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16 Set TAiS bit in the TABSR register to 1 (start counting) Set TAiS bit to 0 (stop counting) Timer overflow or underflow Two-phase pulse input Two-phase pulse input Count value can be read by reading timer A2, A3 or A4 register • When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter • When counting (after 1st count source input) Value written to TAi register is written to reload register (Transferred to counter when reloaded next) • Normal processing operation (timer A2 and timer A3) The timer counts up rising edges or counts down falling edges on TAjIN pin when input signals on TAjOUT pin is “H”. Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Select function (Note) TAjOUT TAjIN (j=2,3) Increment Increment Increment Decrement Decrement Decrement • Multiply-by-4 processing operation (timer A3 and timer A4) If the phase relationship is such that TAkIN(k=3, 4) pin goes “H” when the input signal on TAkOUT pin is “H”, the timer counts up rising and falling edges on TAkOUT and TAkIN pins. If the phase relationship is such that TAkIN pin goes “L” when the input signal on TAkOUT pin is “H”, the timer counts down rising and falling edges on TAkOUT and TAkIN pins. TAkOUT Increment all edges Decrement all edges TAkIN (k=3,4) Increment all edges Decrement all edges • Counter initialization by Z-phase input (timer A3) The timer count value is initialized to 0 by Z-phase input. NOTE: 1. Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to multiply-by-4 processing operation. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 109 of 458 M16C/29 Group 12. Timer A Timer Ai Mode Register (i=2 to 4) (When using two-phase pulse signal processing) b6 b5 b4 b3 b2 b1 b0 010001 Symbol TA2MR to TA4MR Address 0398 16 to 039A 16 After Reset 0016 Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Bit Name Operation mode select bit b1 b0 Function 0 1: Event counter mode RW RW RW RW RW RW RW RW RW To use two-phase pulse signal processing, set this bit to 0 To use two-phase pulse signal processing, set this bit to 0 To use two-phase pulse signal processing, set this bit to 1 To use two-phase pulse signal processing, set this bit to 0 Count operation type select bit Two-phase pulse signal processing operation select bit (1)(2) 0: Reload type 1: Free-run type 0: Normal processing operation 1: Multiply-by-4 processing operation NOTES: 1. The TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in normal processing mode and x4 processing mode, respectively. 2. If two-phase pulse signal processing is desired, following register settings are required: • Set the TAiP bit in the UDF register to 1 (two-phase pulse signal processing function enabled). • Set bits TAiTGH and TAiTGL in the TRGSR register to 002 (TAiIN pin input). • Set the port direction bits for TAiIN and TAiOUT to 0 (input mode). Figure 12.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse signal processing with timer A2, A3 or A4) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 110 of 458 M16C/29 Group 12. Timer A 12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to 0 by Z-phase (counter initialization) input during twophase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal process_______ ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin. Counter initialization by Z-phase input is enabled by writing 000016 to the TA3 register and setting the TAZIE bit in ONSF register to 1 (Z-phase input enabled). Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be chosen to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse _______ width applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source. The counter is initialized at the next count timing after recognizing Z-phase input. Figure 12.10 shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase. If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3 interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this function. TA3 OUT (A phase) TA3 IN (B phase) Count source INT2 (1) (Z phase) Input equal to or greater than one clock cycle of count source Timer A3 m m+1 1 2 3 4 5 NOTE: 1. This timing diagram is for the case where the POL bit in the INT2IC register is set to 1 (rising edge). Figure 12.10 Two-phase Pulse (A phase and B phase) and the Z Phase Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 111 of 458 M16C/29 Group 12. Timer A 12.1.3 One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.4) When the trigger occurs, the timer starts up and continues operating for a given period. Figure 12.11 shows the TAiMR register in one-shot timer mode. Table 12.4 Specifications in One-shot Timer Mode Item Count source Count operation Specification f1, f2, f8, f32, fC32 • Decrement • When the counter reaches 000016, it stops counting after reloading a new value • If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : set value of TAi register 000016 to FFFF16 However, the counter does not work if the divide-by-n value is set to 000016. TAiS bit in the TABSR register is set to 1 (start counting) and one of the following triggers occurs. • External trigger input from the TAiIN pin • Timer B2 overflow or underflow, timer Aj (j=i-1, except j=4 if i=0) overflow or underflow, timer Ak (k=i+1, except k=0 if i=4) overflow or underflow • The TAiOS bit in the ONSF register is set to 1 (timer starts) • When the counter is reloaded after reaching 000016 • TAiS bit is set to 0 (stop counting) When the counter reaches 000016 I/O port or trigger input I/O port or pulse output An undefined value is read by reading TAi register • When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter • When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) • Pulse output function The timer outputs a low when not counting and a high when counting. Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Select function Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 112 of 458 M16C/29 Group 12. Timer A Timer Ai Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 0 10 Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 MR0 Bit Name Address After Reset 396 16 to 039A 16 0016 Function b1 b0 RW RW RW RW Operation mode select bit 1 0: One-shot timer mode Pulse output function select bit External trigger select bit (1) Trigger select bit 0: Pulse is not output (TAiOUT pin functions as I/O port) 1: Pulse is output (TAiOUT pin functions as a pulse output pin) 0: Falling edge of input signal to TAiIN pin (2) 1: Rising edge of input signal to TAiIN pin (2) 0: TAiOS bit is enabled 1: Selected by bits TAiTGH to TAiTGL MR1 MR2 MR3 TCK0 RW RW RW RW RW Set to 0 in one-shot timer mode b7 b6 Count source select bit TCK1 0 0: f1 or f2 0 1: f8 1 0: f32 1 1: fC32 NOTES: 1. Effective when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are 002 (TAiIN pin input). 2. The port direction bit for the TAiIN pin must be set to 0 (input mode). Figure 12.11 TAiMR Register in One-shot Timer Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 113 of 458 M16C/29 Group 12. Timer A 12.1.4 Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.5). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 12.12 shows TAiMR register in pulse width modulation mode. Figures 12.13 and 12.14 show examples of how a 16bit pulse width modulator operates and how an 8-bit pulse width modulator operates. Table 12.5 Specifications in Pulse Width Modulation Mode Item Count source Count operation Specification f1, f2, f8, f32, fC32 • Decrement (operating as an 8-bit or a 16-bit pulse width modulator) • The timer reloads a new value at a rising edge of PWM pulse and continues counting • The timer is not affected by a trigger that occurs during counting • High level width n / fj n : set value of TAi register (i=o to 4) 16-1) / fj fixed • Cycle time (2 fj: count source frequency (f1, f2, f8, f32, fC32) • High level width n x (m+1) / fj n : set value of TAi register high-order address • Cycle time (28-1) x (m+1) / fj m : set value of TAi register low-order address • TAiS bit in the TABSR register is set to 1 (= start counting) • The TAiS bit = 1 and external trigger input from the TAiIN pin • The TAiS bit = 1 and one of the following external triggers occurs • Timer B2 overflow or underflow, timer Aj (j=i-1, except j=4 if i=0) overflow or underflow, timer Ak (k=i+1, except k=0 if i=4) overflow or underflow TAiS bit is set to 0 (stop counting) PWM pulse goes “L” I/O port or trigger input Pulse output An undefined value is read by reading TAi register • When not counting and until the 1st count source is input after counting start Value written to TAi register is written to both reload register and counter • When counting (after 1st count source input) Value written to TAi register is written to only reload register (Transferred to counter when reloaded next) 16-bit PWM 8-bit PWM Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 114 of 458 M16C/29 Group 12. Timer A Timer Ai Mode Register (i= 0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Bit Name Address 039616 to 039A 16 After Reset 0016 Function RW RW RW RW RW RW RW RW RW Operation mode select bit Pulse output funcion select bit External trigger select bit (1) Trigger select bit 16/8-bit PWM mode select bit b1 b0 1 1: PWM mode 0: Pulse is not output (TAiOUT pin functions as I/O port) 1: Pulse is output (TAiOUT pin functions as a pulse output pin) 0: Falling edge of input signal to TAiIN pin(2) 1: Rising edge of input signal to TAiIN pin(2) 0: Write 1 to TAiS bit in the TASF register 1: Selected by bits TAiTGH to TAiTGL 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator b7 b6 Count source select bit 0 0: f1 or f2 0 1: f8 1 0: f32 1 1: fC32 NOTES: 1. Effective when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are 002 (TAiIN pin input). 2. The port direction bit for the TAiIN pin must be set to 0 ( input mode). Figure 12.12 TAiMR Register in Pulse Width Modulation Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 115 of 458 M16C/29 Group 12. Timer A 1 / f i X (2 16 – 1) Count source “H” “L” Input signal to TAiIN pin Trigger is not generated by this signal 1 / fj X n PWM pulse output from TA iOUT pin IR bit in the TAiIC register “H” “L” 1 0 fj : Frequency of count source (f1, f 2, f8, f 32, fC32) i = 0 to 4 Set to 0 upon accepting an interrupt request or by program NOTES: 1. n = 0000 16 to FFFE 16. 2. This timing diagram is for the case where the TAi register is 0003 16, bits TAiTGH and TAiTGL in the ONSF or TRGSR register is set to 00 2 (TAiIN pin input), the MR1 bit in the TAiMR register is set to 1 (rising edge), and the MR2 bit in the TAiMR register is set to 1 (trigger selected by TAiTGH and TAiTGL bits). Figure 12.13 Example of 16-bit Pulse Width Modulator Operation 1 / fj X (m + 1) X (2 – 1) Count source (1) 8 Input signal to TAiIN pin “H” “L” 1 / f j X (m + 1) Underflow signal of 8-bit prescaler (2) “H” “L” 1 / f j X (m + 1) X n PWM pulse output from TA iOUT pin IR bit in the TAiIC register “H” “L” 1 0 fj : Frequency of count source (f1, f 2, f8, f 32, fC32) i = 0 to 4 Set to 0 upon accepting an interrupt request or by program NOTES: 1. The 8-bit prescaler counts the count source. 2. The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. 3. m = 0016 to FF16; n = 0016 to FE16. 4. This timing diagram is for the case where the TAi register is 020216, bits TAiTGH and TAiTGL in the ONSF or TRGSR register is set to 002 (TAiIN pin input), the MR1 bit in the TAiMR register is set to 0 (falling edge), and the MR2 bit in the TAiMR register is set to 1 (trigger selected by bits TAiTGH and TAiTGL). Figure 12.14 Example of 8-bit Pulse Width Modulator Operation Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 116 of 458 M16C/29 Group 12. Timer B 12.2 Timer B Figure 12.15 shows a block diagram of the timer B. Figures 12.16 and 12.17 show registers related to the timer B. Timer B supports the following four modes. Use bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 2) to select the desired mode. • Timer mode: The timer counts the internal count source. • Event counter mode: The timer counts the external pulses or overflows and underflows of other timers. • Pulse period/pulse width measurement mode: The timer measures the pulse period or pulse width of external signal. • A/D trigger mode: The timer starts counting by one trigger until the count value becomes 000016. This mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of A/D converter to start A/D conversion. Data bus high-order bits Clock source selection Data bus low-order bits Low-order 8 bits High-order 8 bits f1 or f2 f8 f32 fC32 TBiIN (i = 0 to 2) • Timer mode • Pulse period/, pulse width measuring mode • A/D trigger mode • Event counter Polarity switching, edge pulse Can be selected in onlyevent counter mode TBj overflow (1) (j = i – 1, except j = 2 if i = 0) Reload register Clock selection Counter TABSR register Counter reset circuit TBi Timer B0 Timer B1 Timer B2 Address 039116 - 039016 039316 - 039216 039516 - 039416 TBj Timer B2 Timer B0 Timer B1 NOTE: 1. Overflow or underflow. Figure 12.15 Timer B Block Diagram Timer Bi Mode Register (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TB0MR to TB2MR Address 039B16 to 039D16 After Reset 00XX00002 Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 NOTES: 1. Timer B0. 2. Timer B1, Timer B2. Bit Name Operation mode select bit b1 b0 Function 0 0 : Timer mode or A/D trigger mode 0 1 : Event counter mode 1 0 : Pulse period measurement mode, pulse width measurement mode 1 1 : Do not set Function varies with each operation mode RW RW RW RW RW RW(1) (2) RO Count source select bit Function varies with each operation mode RW RW Figure 12.16 TB0MR to TB2MR Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 117 of 458 M16C/29 Group 12. Timer B Timer Bi Register (i=0 to 2)(1) (b15) b7 ( b8) b0 b7 b0 Symbol TB0 TB1 TB2 Address 039116, 039016 039316, 039216 039516, 039416 After Reset Undefined Undefined Undefined Mode Timer mode Event counter mode Function Divide the count source by n + 1 where n = set value Divide the count source by n + 1 where n = set value (2) Setting Rrange 0000 16 to FFFF 16 0000 16 to FFFF 16 RW RW RW RO Pulse period Measures a pulse period or width modulation mode, Pulse width modulation mode A/D trigger Divide the count source by n + 1 where n = set value and cause the timer stop mode (3) 0000 16 to FFFF 16 RW NOTES: 1.The register must be accessed in 16 bit units. 2. The timer counts pulses from an external device or overflows or underflows of other timers. 3. When this mode is used combining delayed trigger mode 0, set the larger value than the value in the timer B0 register to the timer B1 register. Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Address 038016 After Reset 0016 Bit Name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Function 0: Stops counting 1: Starts counting RW RW RW RW RW RW RW RW RW Clock Prescaler Reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Bit Symbol (b6-b0) CPSR Address 038116 After Reset 0XXXXXXX16 Bit Name Function RW Nothing is assigned. If necessary, set to 0. When read, the contents are undefined Clock prescaler reset flag Setting this bit to 1 initializes the prescaler for the timekeeping clock. (When read, the value of this bit is 0) RW Figure 12.17 TB0 to TB2 Registers, TABSR Register, CPSRF Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 118 of 458 M16C/29 Group 12. Timer B 12.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.6). Figure 12.18 shows TBiMR register in timer mode. Table 12.6 Specifications in Timer Mode Item Count source Count operation Specification f1, f2, f8, f32, fC32 • Decrement • When the timer underflows, it reloads the reload register contents and continues counting 1/(n+1) n: set value of TBi register (i= 0 to 2) 000016 to FFFF16 Set TBiS bit(1) to 1 (start counting) Set TBiS bit to 0 (stop counting) Timer underflow I/O port Count value can be read by reading TBi register • When not counting and until the 1st count source is input after counting start Value written to TBi register is written to both reload register and counter • When counting (after 1st count source input) Value written to TBi register is written to only reload register (Transferred to counter when reloaded next) Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer NOTE: 1. Bits TB0S to TB2S are assigned to the bit 7 to bit 5 in the TABSR register. Timer Bi Mode Register (i= 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TB0MR to TB2MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 Address 039B16 to 039D16 After Reset 00XX00002 Bit Name Operation mode select bit No effect in timer mode Can be set to 0 or 1 TB0MR register Set to 0 in timer mode b1 b0 Function 0 0: Timer mode or A/D trigger mode RW RW RW RW RW RW TB1MR, TB2MR registers Nothing is assigned. If necessary, set to 0. When read, its content is undefined When write in timer mode, set to 0. When read in timer mode, its content is undefined Count source select bit 0 0: f1 or f2 0 1: f8 1 0: f32 1 1: fC32 b7 b6 MR3 TCK0 TCK1 RO RW RW Figure 12.18 TBiMR Register in Timer Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 119 of 458 M16C/29 Group 12. Timer B 12.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 12.7). Figure 12.19 shows the TBiMR register in event counter mode. Table 12.7 Specifications in Event Counter Mode Specification • External signals input to TBiIN pin (i=0 to 2) (effective edge can be selected in program) • Timer Bj overflow or underflow (j=i-1, except j=2 if i=0) Count operation • Decrement • When the timer underflows, it reloads the reload register contents and continues counting Divide ratio 1/(n+1) n: set value of TBi register 000016 to FFFF16 Count start condition Set TBiS bit(1) to 1 (start counting) Count stop condition Set TBiS bit to 0 (stop counting) Interrupt request generation timing Timer underflow TBiIN pin function Count source input Read from timer Count value can be read by reading TBi register Write to timer • When not counting and until the 1st count source is input after counting start Value written to TBi register is written to both reload register and counter • When counting (after 1st count source input) Value written to TBi register is written to only reload register (Transferred to counter when reloaded next) NOTE: 1. Bits TB2S to TB0S are assigned to the bit 7 to bit 5 in the TABSR register. Item Count source Timer Bi Mode Register (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 01 Symbol TB0MR to TB2MR Address 039B16 to 039D16 After Reset 00XX00002 Bit Symbol TMOD0 TMOD1 MR0 Bit Name Operation mode select bit Count polarity select bit (1) b1 b0 Function 0 1: Event counter mode b3 b2 RW RW RW RW MR1 TB0MR register Set to 0 in timer mode 0 0: Counts external signal's falling edges 0 1: Counts external signal's rising edges 1 0: Counts external signal's falling and rising edges 1 1: Do not set RW RW MR2 TB1MR, TB2MR registers Nothing is assigned. If necessary, set to 0. When read, the content is undefined When write in event counter mode, set to 0. When read in event counter mode, its content is undefined No effect in event counter mode Can be set to 0 or 1 Event clock select 0 : Input from TBiIN pin (2) 1 : TBj overflow or underflow (j = i – 1, except j = 2 if i = 0) RO RW RW MR3 TCK0 TCK1 NOTES: 1. Effective when the TCK1 bit is set to 0 (input from TBiIN pin). If the TCK1 bit is set to 1 (TBj overflow or underflow), these bits can be set to 0 or 1. 2. The port direction bit for the TBiIN pin must be set to 0 (= input mode). Figure 12.19 TBiMR Register in Event Counter Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 120 of 458 M16C/29 Group 12. Timer B 12.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 12.8). Figure 12.20 shows the TBiMR register in pulse period and pulse width measurement mode. Figure 12.21 shows the operation timing when measuring a pulse period. Figure 12.22 shows the operation timing when measuring a pulse width. Table 12.8 Specifications in Pulse Period and Pulse Width Measurement Mode Item Count source Count operation Specification f1, f2, f8, f32, fC32 • Increment • Counter value is transferred to reload register at an effective edge of measurement pulse. The counter value is set to 000016 to continue counting. Count start condition Set TBiS (i=0 to 2) bit (3) to 1 (start counting) Count stop condition Set TBiS bit to 0 (stop counting) Interrupt request generation timing • When an effective edge of measurement pulse is input (1) • Timer overflow. When an overflow occurs, MR3 bit in the TBiMR register is set to 1 (overflowed) simultaneously. MR3 bit is cleared to 0 (no overflow) by writing to TBiMR register at the next count timing or later after MR3 bit was set to 1. At this time, make sure TBiS bit is set to 1 (start counting). TBiIN pin function Measurement pulse input Read from timer Contents of the reload register (measurement result) can be read by reading TBi register (2) Write to timer Value written to TBi register is written to neither reload register nor counter NOTES: 1. Interrupt request is not generated when the first effective edge is input after the timer started counting. 2. Value read from TBi register is undefined until the second valid edge is input after the timer starts counting. 3. Bits TB0S to TB2S are assigned to the bit 5 to bit 7 in the TABSR register . Timer Bi Mode Register (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol TB0MR to TB2MR Address 039B16 to 039D16 After Reset 00XX00002 Bit Symbol TMOD0 TMOD1 MR0 Bit Name Operation mode select bit Measurement mode select bit b1 b0 Function 1 0 : Pulse period / pulse width measurement mode b3 b2 RW RW RW RW MR1 0 0: Pulse period measurement (Measurement between a falling edge and the next falling edge of measured pulse) 0 1: Pulse period measurement (Measurement between a rising edge and the next rising edge of measured pulse) 1 0: Pulse width measurement (Measurement between a falling edge and the next rising edge of measured pulse and between a rising edge and the next falling edge) 1 1: Do not set. RW MR2 TB0MR register RW Set to 0 in pulse period and pulse width measurement mode TB1MR, TB2MR registers Nothing is assigned. If necessary, set to 0. When read, its content is undefined Timer Bi overflow flag (1) Count source select bit 0 : Timer did not overflow 1 : Timer has overflowed b7 b6 MR3 TCK0 TCK1 RO RW RW 0 0: f1 or f2 0 1: f8 1 0: f32 1 1: fC32 NOTE: 1.This flag is undefined after reset. When the TBiS bit is set to 1 (start counting), the MR3 bit is cleared to 0 (no overflow) by writing to the TBiMR register at the next count timing or later after the MR3 bit was set to 1 (overflowed). The MR3 bit cannot be set to 1 by program. Bits TB0S to TB2S are assigned to the bit 5 to bit 7 in the TABSR register. Figure 12.20 TBiMR Register in Pulse Period and Pulse Width Measurement Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 121 of 458 M16C/29 Group 12. Timer B Count source Measurement pulse “H” “L” Transfer (undefined value) Transfer (measured value) Reload register transfer timing counter (1) (1) (2) Timing at which counter reaches 000016 TBiS bit 1 0 1 0 TBiIC register's IR bit Set to 0 upon accepting an interrupt request or by program TBiMR register's MR3 bit 1 0 Bits TB0S to TB2S are assigned to the bit 5 to bit 7 in the TABSR register. i = 0 to 2 NOTES: 1. Counter is initialized at completion of measurement. 2. Timer has overflowed. 3. This timing diagram is for the case where bits MR1 and MR0 in the TBiMR register are 002 (measure the interval from falling edge to falling edge of the measurement pulse). Figure 12.21 Operation timing when measuring a pulse period Count source Measurement pulse Reload register transfer timing “H” “L” Transfer (undefined value) Transfer (measured value) Transfer (measured value) Transfer (measured value) counter (1) (1) (1) (1) (1) Timing at which counter reaches 000016 TBiS bit 1 0 TBiIC register's IR bit 1 0 1 0 The MR3 bit in the TBiMR register i = 0 to 2 Set to 0 upon accepting an interrupt request or by program Bits TB0S to TB2S are assigned to the bit 5 to bit 7 in the TABSR register. NOTES: 1. Counter is initialized at completion of measurement. 2. Timer has overflowed. 3. This timing diagram is for the case where bits MR1 to MR0 in the TBiMR register are 102 (measure the interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the measurement pulse). Figure 12.22 Operation timing when measuring a pulse width Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 122 of 458 M16C/29 Group 12. Timer B 12.2.4 A/D Trigger Mode A/D trigger mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of A/D conversion to start A/D conversion. It is used in timer B0 and timer B1 only. In this mode, the timer starts counting by one trigger until the count value becomes 000016. Figure 12.23 shows the TBiMR register in A/D trigger mode and Figure 12.24 shows the TB2SC register. Table 12.9 Specifications in A/D Trigger Mode Item Specification Count Source f1, f2, f8, f32, and fC32 Count Operation • Decrement • When the timer underflows, reload register contents are reloaded before stopping counting • When a trigger is generated during the count operation, the count is not affected Divide Ratio 1/(n+1) n: Setting value of TBi register (i=0,1) 000016-FFFF16 Count Start Condition When the TBiS (i=0,1) bit in the TABSR register is 1(count started), TBiEN(i=0,1) in TB2SC register is 1 (A/D trigger mode) and the following trigger is generated.(Selection based on bits TB2SEL in the TB2SC) • Timer B2 interrupt • Underflow of Timer B2 interrupt generation frequency counter setting Count Stop Condition • After the count value is 000016 and reload register contents are reloaded • Set the TBiS bit to 0 (count stopped) Interrupt Request Timer underflows (1) Generation Timing TBiIN Pin Function I/O port Read From Timer Count value can be read by reading TBi register Write To Timer (2) • When writing in the TBi register during count stopped. Value is written to both reload register and counter • When writing in the TBi register during count. Value is written to only reload register (Transfered to counter when reloaded next) NOTES: 1: A/D conversion is started by the timer underflow. For details refer to 15. A/D Converter. 2: When using in delayed trigger mode 0, set the larger value than the value of the timer B0 register to the timer B1 register. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 123 of 458 M16C/29 Group 12. Timer B Timer Bi Mode Register (i= 0 to 1) b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TB0MR to TB1MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 Address 039B16 to 039C16 After Reset 00XX00002 Bit Name Operation mode select bit Invalid in A/D trigger mode Either 0 or 1 is enabled TB0MR register Set to 0 in A/D trigger mode b1 b0 Function 0 0: Timer mode or A/D trigger mode RW RW RW RW RW RW TB1MR register Nothing is assigned. If necessary, set to 0. When read, its content is undefined MR3 When write in A/D trigger mode, set to 0. When read in A/D trigger mode, its content is undefined Count source select bit (1) RO RW RW TCK0 TCK1 0 0: f1 or f2 0 1: f8 1 0: f32 1 1: fC32 b7 b6 NOTE: 1. When this bit is used in delayed trigger mode 0, set the same count source to the timer B0 and timer B1. Figure 12.23 TBiMR Register in A/D Trigger Mode Timer B2 special mode register (1) b7 b6 b5 b4 b3 b2 b1 b0 00 11 Symbol TB2SC Bit Symbol PWCON Address 039E16 Bit Name Timer B2 reload timing switch bit (2) Three-phase output port SD control bit 1 (3, 4, 7) After Reset X00000002 Function 0: Timer B2 underflow 1: Timer A output at odd-numbered 0: Three-phase output forcible cutoff by SD pin input (high impedance) disabled 1: Three-phase output forcible cutoff by SD pin input (high impedance) enabled 0: Other than A/D trigger mode (5) 1: A/D trigger mode 0: Other than A/D trigger mode (5) 1: A/D trigger mode RW RW IVPCR1 RW TB0EN TB1EN TB2SEL Timer B0 operation mode select bit Timer B1 operation mode select bit Trigger select bit (6) RW RW 0: TB2 interrupt RW 1: Underflow of TB2 interrupt generation frequency setting counter [ICTB2] Set to 0 RW (b6-b5) (b7) Reserved bits Nothing is assigned. If necessary, set to 0. When read, its content is 0 NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled). 2. If the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer B2 underflow). 3. When setting the IVPCR1 bit to 1 (three-phase output forcible cutoff by SD pin input enabled), Set the PD85 bit to 0 (= input mode). 4. Related pins are U(P80), U(P81), V(P72), V(P73), W(P74), W(P75). When a high-level ("H") signal is applied to the SD pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state. If a lowlevel (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0). At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1 bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those pins is used. 5. When this bit is used in delayed trigger mode 0, set bits TB0EN and TB1EN to 1 (A/D trigger mode). 6. When setting the TB2SEL bit to 1 (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), set the INV02 bit to 1 (three-phase motor control timer function). Figure 12.24 TB2SC Register in A/D Trigger Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 124 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) 12.3 Three-phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.10 lists the specifications of the three-phase motor control timer function. Figure 12.24 shows the block diagram for three-phase motor control timer function. Also, the related registers are shown on Figures 12.26 to 12.32. Table 12.10 Three-phase Motor Control Timer Function Specifications Item Specification ___ ___ ___ Three-phase waveform output pin Six pins (U, U, V, V, W, W) _____ Forced cutoff input (1) Input “L” to SD pin Used Timers Timer A4, A1, A2 (used in the one-shot timer mode) ___ Timer A4: U- and ___ U-phase waveform control Timer A1: V- and V-phase waveform control ___ Timer A2: W- and W-phase waveform control Timer B2 (used in the timer mode) Carrier wave cycle control Dead time timer (3 eight-bit timer and shared reload register) Dead time control Output waveform Triangular wave modulation, Sawtooth wave modification Enable to output “H” or “L” for one cycle Enable to set positive-phase level and negative-phase level respectively Carrier wave cycle Triangular wave modulation: count source x (m+1) x 2 Sawtooth wave modulation: count source x (m+1) m: Setting value of TB2 register, 0 to 65535 Count source: f1, f2, f8, f32, fC32 Three-phase PWM output width Triangular wave modulation: count source x n x 2 Sawtooth wave modulation: count source x n n: Setting value of TA4, TA1 and TA2 register (of TA4, TA41, TA1, TA11, TA2 and TA21 registers when setting the INV11 bit to 1), 1 to 65535 Count source: f1, f2, f8, f32, fC32 Dead time Count source x p, or no dead time p: Setting value of DTT register, 1 to 255 Count source: f1, f2, f1 divided by 2, f2 divided by 2 Active level Eable to select “H” or “L” Positive and negative-phase concurrent Positive and negative-phases concurrent active disable function Positive and negative-phases concurrent active detect function Interrupt frequency For Timer B2 interrupt, select a carrier wave cycle-to-cycle basis through 15 times carrier wave cycle-to-cycle basis NOTE: 1. When the INV02 bit in the INVC0 register is set to 1 (three-phase motor control timer function), the _____ _____ SD function of the P85/SD pin is enabled. At this time, the P85 pin_____ cannot be used as a programmable _____ I/O port. When the SD function is not used, apply “H” to the P85/SD pin. _____ When the IVPCR1 bit in the TB2SC_____ register is set to 1 (enable three-phase output forced cutoff by SD pin input), and “L” is applied to the SD pin, the related pins enter high-impedance state regardless of the functions which are used. When the IVPCR1 bit is set to 0 (disabled three-phase output forced _____ _____ cutoff by SD pin input) and “L” is applied to the SD pin, the related pins can be selected as a programmable I/O port and the setting of the port and port direction _________ registers are ___ enable. _________ Related pins: P72/CLK2/TA1OUT/V/RXD1 P73/CTS2/RTS2/TA1IN/V/TXD1 ____ P74/TA2OUT/W P75/TA2IN/W ___ P80/TA4OUT/U P81/TA4IN/U Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 125 of 458 M16C/29 Group INV13 Interrupt occurrence set circuit b0 QD T QD T ICTB2 register n = 1 to 15 Bits 2 through 0 of Position-dataretain function control register (address 034E16) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 IDW IDV IDU INV00 INV01 INV11 Timer B2 underflow 1 0 ICTB2 counter n = 1 to 15 Timer B2 interrupt request bit b2 RESET b1 0 INV07 Trigger Trigger INV12 Reload register n = 1 to 255 IVPRC1 SQ R Timer B2 INV06 INV05 INV14 INV04 U phase output signal DQ T Signal to be written to timer B2 INV10 f1 or f2 1/2 QD T 1 Dead time timer n = 1 to 255 RESET SD SD Data Bus DQ R INV03 Figure 12.25 Three-phase Motor Control Timer Functions Block Diagram page 126 of 458 Transfer trigger (Note 1) DQ T D Q T (Timer mode) Timer Ai (i = 1, 2, 4) start trigger signal U phase output control circuit DU0 DU1 bit bit Timer A4 reload control signal PD8_0 Reverse control TA4 register TA41 register Reload U Trigger Timer A4 one-shot pulse Timer A4 counter DUB1 bit DUB0 bit U phase output signal DQ T D Q T DQ T (One-shot timer mode) TQ INV11 Three-phase output shift register (U phase) Reverse control PD8_1 Set to 0 when TA4S bit is set to 0 U PD7_2 Trigger Trigger DQ T INV06 TA11 register Dead time timer n = 1 to 255 V phase output signal Reverse control V TA1 register Reload V phase output control circuit V phase output signal PD7_3 DQ T Trigger Timer A1 counter (One-shot timer mode) Trigger Trigger Reverse control V PD7_4 DQ T TQ INV06 TA21 register INV11 Set to 0 when TA1S bit = 0 Dead time timer n = 1 to 255 W phase output signal Reverse control W TA2 register Reload W phase output control circuit Trigger Timer A2 counter W phase output signal DQ T PD7_5 Reverse control W Diagram for switching to P80, P81 and P72 - P75 is not shown. (One-shot timer mode) TQ INV11 Set to 0 when TA2S bit is set to 0 12. Timer (Three-phase Motor Control Timer Function) NOTE: 1. If the INV06 bit is set to 0 (triangular wave modulation mode), a transfer trigger is generated at only the first occurrence of a timer B2 underflow after writing to the IDB0 and IDB1 registers. M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) Three-phase PWM Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol INVC0 034816 Address After Reset 0016 Bit Symbol Bit Name Effective interrupt output polarity select bit(3) Function 0: ICTB2 counter is incremented by 1 on the rising edge of timer A1 reload control signal 1: ICTB2 counter is incremented by 1 on the falling edge of timer A1 reload control signal 0: ICTB2 counter incremented by 1 at a timer B2 underflow 1: Selected by INV00 bit 0: Three-phase motor control timer function unused 1: Three-phase motor control timer function (5) 0: Three-phase motor control timer output disabled (5) 1: Three-phase motor control timer output enabled 0: Simultaneous active output enabled 1: Simultaneous active output disabled 0: Not detected yet 1: Already detected RW INV00 RW INV01 Effective interrupt output specification bit(2, 3) RW INV02 Mode select bit(4) RW INV03 Output control bit(6) Positive and negative phases concurrent output disable bit Positive and negative phases concurrent output detect flag RW INV04 RW RW RW RW INV05 INV06 (7) 0: Triangular wave modulation mode Modulation mode select bit(8) 1: Sawtooth wave modulation mode (9) Software trigger select bit Setting this bit to 1 generates a transfer trigger. If the INV06 bit is 1, a trigger for the dead time timer is also generated. The value of this bit when read is 0 INV07 NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enable). Note also that bits INV00 to INV02, bits INV04 and INV06 can only be rewritten when timers A1, A2, A4 and B2 are idle. 2. If this bit needs to be set to 1, set any value in the ICTB2 register before writing to it. 3. Effective when the INV11 bit in the INV1 register is 1 (three-phase mode 1). If INV11 is set to 0 (three-phase mode 0), the ICTB2 counter is incremented by 1 each time the timer B2 underflows, regardless of whether the INV00 and INV01 bits are set. When setting the INV01 bit to 1, the first interrupt is generated when the timer B2 underflows n-1 times, if n is the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 underflow. 4. Setting the INV02 bit to 1 activates the dead time timer, U/V/W-phase output control circuits and ICTB2 counter. 5. When the INV02 bit is set to 1 and the INV03 bit is set to 0, U, U, V, V, W, W pins, including pins shared with other output functions, enter a high-impedance state. When INV03 is set to 1, U/V/W corresponding pins generate the three-phase PWM output. 6. The INV03 bit is set to 0 in the following cases: • When reset • When positive and negative go active (INV05 = 1) simultaneously while INV04 bit is 1 • When set to 0 by program • When input on the SD pin changes state from “H” to “L” regardless of the value of the INVCR1 bit. (The INV03 bit cannot be set to 1 when SD input is “L”.) INV03 is set to 0 when both bits INV05 and INV04 are set to 1. Item Mode Timing at which transferred from registers IDB0 to IDB1 to three-phase output shift register Timing at which dead time timer trigger is generated when INV16 bit is 0 INV13 bit INV06=0 Triangular wave modulation mode Transferred only once synchronously with the transfer trigger after writing to registers IDB0 to IDB1 Synchronous with the falling edge of timer A1, A2, or A4 one-shot pulse Effective when INV11 is set to 1 and INV06 is set to 0 INV06=1 Sawtooth wave modulation mode Transferred every transfer trigger Synchronous with the transfer trigger and the falling edge of timer A1, A2, or A4 one-shot pulse No effect Transfer trigger: Timer B2 underflow, write to the INV07 bit or write to the TB2 register when the INV10 bit is set to 1. 9: If the INV06 bit is set to 1, set the INV11 bit to 0 (three-phase mode 0) and set the PWCON bit to 0 (timer B2 reloaded by a timer B2 underflow) 10. When the PFCi (i = 0 to 5) bit in the PFCR register is set to 1 (three-phase PWM output), individual pins are enabled to output. Figure 12.26 INVC0 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 127 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) Three-phase PWM Control Register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol INVC1 034916 Address Bit Name 0016 After Reset Function 0: Timer B2 underflow 1: Timer B2 underflow and write to the TB2 register (2) Bit Symbol INV10 RW RW RW RW RO RW RW Timer A1, A2, A4 start trigger signal select bit Timer A1-1, A2-1, A4-1 control bit Dead time timer count source select bit Carrier wave detect flag (5) INV11 INV12 INV13 (3) 0: Three-phase mode 0 1: Three-phase mode 1 (4) 0: f 1 or f2 1: f 1 divided by 2 or f 2 divided by 2 0: Timer Reload control signal is set to 0 1: Timer Reload control signal is set to 1 0 : Output waveform “L” active 1 : Output waveform “H” active 0: Dead time timer enabled 1: Dead time timer disabled 0: Falling edge of timer A4, A1 or A2 one-shot pulse 1: Rising edge of three-phase output shift register (U, V or W phase) output(6) Set to 0 INV14 INV15 Output polarity control bit Dead time invalid bit INV16 Dead time timer trigger select bit RW (b7) Reserved bit RW NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enable). Note also that this register can only be rewritten when timers A1, A2, A4 and B2 are idle. 2. A start trigger is generated by writing to the TB2 register only while timer B2 stops. 3. The effects of the INV11 bit are described in the table below. Item Mode TA11, TA21, TA41 registers INV00 bit, INV01 bit INV13 bit Not Used Has no effect. ICTB2 counted every time timer B2 underflows regardless of whether bits INV00 and INV01 are set Has no effect INV11=0 Three-phase mode 0 Used Effect Effective when INV11 bit is 1 and INV06 bit is 0 INV11=1 Three-phase mode 1 4. If the INV06 bit is 1 (sawtooth wave modulation mode), set this bit to 0 (three-phase mode 0). Also, if the INV11 bit is 0, set the PWCON bit to 0 (timer B2 reloaded by a timer B2 underflow). 5. The INV13 bit is effective only when the INV06 bit is set to 0 (triangular wave modulation mode) and the INV11 bit is set to 1 (three-phase mode 1). 6. If all of the following conditions hold true, set the INV16 bit to 1 (dead time timer triggered by the rising edge of threephase output shift register output) • The INV15 bit is 0 (dead time timer enabled) • When the INV03 bit is set to 1 (three-phase motor control timer output enabled), the Dij bit and DiBj bit (i:U, V, or W, j: 0 to 1) have always different values (the positive-phase and negative-phase always output different levels during the period other than dead time). Conversely, if either one of the above conditions holds false, set the INV16 bit to 0 (dead time timer triggered by the falling edge of one-shot pulse). Figure 12.27 INVC1 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 128 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) Three-phase Output Buffer Register(i=0,1) (1) b7 b4 b3 b2 b1 b0 0 Symbol IDB0 IDB1 Address 034A16 034B16 After Reset 001111112 001111112 Bit Symbol DUi DUBi DVi DVBi DWi DWBi (b7-b6) Bit Name U phase output buffer i U phase output buffer i V phase output buffer i V phase output buffer i W phase output buffer i W phase output buffer i Function Write the output level 0: Active level 1: Inactive level When read, these bits show the three-phase output shift register value. RW RW RW RW RW RW RW RO Nothing is assigned. If necessary, set to 0. When read, these contents are 0 NOTE: 1. Registers IDB0 and IDB1 values are transferred to the three-phase shift register by a transfer trigger. The value written to the IDB0 register aftera transfer trigger represents the output signal of each phase, and the next value written to the IDB1 register at the falling edge of the timer A1, A2, or A4 one-shot pulse represents the output signal of each phase. Dead Time Timer (1, 2) b7 b0 Symbol DTT Address 034C16 After Reset Undefined Function Assuming the set value = n, upon a start trigger the timer starts counting the count souce selected by the INV12 bit and stops after counting it n times. The positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. Setting Range 1 to 255 RW WO NOTES: 1. Use MOV instruction to write to this register. 2. Effective when the INV15 bit is set to 0 (dead time timer enable). If the INV15 bit is set to 1, the dead time timer is disabled and has no effect. Timer B2 Interrupt Occurrences Frequency Set Counter b7 b6 b5 b4 b3 b0 Symbol ICTB2 Address 034D16 After Reset Undefined Setting Range 1 to 15 WO RW Function If the INV01 bit is 0 (ICTB2 counter counted every time timer B2 underflows), assuming the set value = n, a timer B2 interrupt is generated at every nth occurrence of a timer B2 underflow. If the INV01 bit is 1 (ICTB2 counter count timing selected by the INV00 bit), assuming the set value = n, a timer B2 interrupt is generated at every nth occurrence of a timer B2 underflow that meets the (1) condition selected by the INV00 bit. Nothing is assigned. When write, set to "0". When read, the content is undefined. NOTE: 1. Use MOV instruction to write to this register. If the INV01 bit is set to 1, make sure the TB2S bit also is set to 0 (timer B2 count stopped) when writing to this register. If the INV01 bit is set to 0, although this register can be written even when the TB2S bit is set to 1 (timer B2 count start), do not write synchronously with a timer B2 underflow. Figure 12.28 IDB0 Register, IDB1Register, DTT Register, and ICTB2 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 129 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) Timer Ai, Ai-1 Register (i=1, 2, 4) (1, 2, 3, 4, 5) Symbol TA1 TA2 TA4 TA11(6,7) TA21(6,7) TA41(6,7) Function Assuming the set value = n, upon a start trigger the timer starts counting the count source and stops after counting it n times. The positive and negative phases change at the same time timer A, A2 or A4 stops. Address 038916-038816 038B16-038A16 038F16-038E16 034316-034216 034516-034416 034716-034616 After reset Undefined Undefined Undefined Undefined Undefined Undefined Setting Range 000016 to FFFF16 WO RW (b15) b7 (b8) b0 b7 b0 NOTES: 1. The register must be accessed in 16 bit units. 2. When the timer Ai register is set to 000016, the counter does not operate and a timer Ai interrupt does not occur. 3. Use MOV instruction to write to these registers. 4. If the INV15 bit is 0 (dead time timer enable), the positive or negative phase whichever is going from an inactive to an active level changes at the same time the dead time timer stops. 5. If the INV11 bit is 0 (three-phase mode 0), the TAi register value is transferred to the reload register by a timer Ai (i = 1, 2 or 4) start trigger. If the INV11 bit is 1 (three-phase mode 1), the TAi1 register value is transferred to the reload register by a timer Ai start trigger first and then the TAi register value is transferred to the reload register by the next timer Ai start trigger. Thereafter, the TAi1 register and TAi register values are transferred to the reload register alternately. 6. Do not write to TAi1 registers synchronously with a timer B2 underflow In three-phase mode 1. 7. Write to the TAi1 register as follows: (1) Write a value to the TAi1 register (2) Wait for one cycle of timer Ai count source. (3) Write the same value to the TAi1 register again. Figure 12.29 TA1, TA2, TA4, TA11, TA21, and TA41 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 130 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) Timer B2 Special Mode Register (1) b7 00 b6 b5 b4 b3 b2 b1 b0 Symbol TB2SC Bit Symbol PWCON Address 039E16 Bit Name Timer B2 reload timing switch bit (2) Three-phase output port SD control bit 1 (3, 4, 7) After Reset X00000002 Function 0: Timer B2 underflow 1: Timer A output at odd-numbered 0: Three-phase output forcible cutoff by SD pin input (high impedance) disabled 1: Three-phase output forcible cutoff by SD pin input (high impedance) enabled RW RW IVPCR1 RW TB0EN TB1EN TB2SEL Timer B0 operation mode 0: Other than A/D trigger mode select bit (5) 1: A/D trigger mode Timer B1 operation mode 0: Other than A/D trigger mode select bit 1: A/D trigger mode (5) Trigger select bit (6) 0: TB2 interrupt 1: Underflow of TB2 interrupt generation frequency setting counter [ICTB2] Set to 0 RW RW RW (b6-b5) (b7) Reserved bits RW Nothing is assigned. If necessary, set to 0. When read, the content is 0. NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled). 2. If the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer B2 underflow). 3. When setting the IVPCR1 bit to 1 (three-phase output forcible cutoff by SD pin input enabled), Set the PD85 bit to 0 (= input mode). 4. Related pins are U(P80), U(P81), V(P72), V(P73), W(P74), W(P75). When a high-level ("H") signal is applied to the SD pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state. If a lowlevel (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0). At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1 bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those pins is used. 5. When this bit is used in delayed trigger mode 0, set bits TB0EN and TB1EN to 1 (A/D trigger mode). 6. When setting the TB2SEL bit to 1 (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), set the INV02 bit to 1 (three-phase motor control timer function). 7. Refer to "19.6 Digital Debounce Function" for the SD input. The effect of SD pin input is below. 1.Case of INV03 = 1(Three-phase motor control timer output enabled) IVPCR1 bit Status of U/V/W pins SD pin inputs(3) 1 (Three-phase output forcrible cutoff enable) 0 (Three-phase output forcrible cutoff disable) H L(1) H L(1) Three-phase PWM output High impedance(4) Three-phase PWM output Input/output port(2) Three-phase output forcrible cutoff Remarks NOTES: 1. When "L" is applied to the SD pin, INV03 bit is changed to 0 at the same time. 2. The value of the port register and the port direction register becomes effective. 3. When SD function is not used, set to 0 (Input) in PD85 and pullup to "H" in SD pin from outside. 4. To leave the high-impedance state and restart the three-phase PWM signal output after the three-phase PWM signal output forced cutoff, set the IVPCR1 bit to 0 after the SD pin input level becomes high (“H”). 2.Case of INV03 = 0(Three-phase motor control timer output disabled) IVPCR1 bit 1 (Three-phase output forcrible cutoff enable) 0 (Three-phase output forcrible cutoff disable) SD pin inputs H L H L Status of U/V/W pins Peripheral input/output or input/output port High impedance Peripheral input/output or input/output port Peripheral input/output or input/output port Remarks Three-phase output forcrible cutoff(1) NOTE: 1. The three-phase output forcrible cutoff function becomes effective if the INPCR1 bit is set to 1 (three-phase output forcrible cutoff function enable) even when the INV03 bit is 0 (three-phase motor control timer output disalbe) Figure 12.30 TB2SC Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 131 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) Timer B2 Register (1) (b15) b7 (b8) b0 b7 b0 Symbol TB2 Function Address 039516-039416 After Reset Undefined Setting Range 000016 to FFFF16 RW RW Divide the count source by n + 1 where n = set value. Timer A1, A2 and A4 are started at every occurrence of underflow. NOTE: 1. Access the register by 16 bit units. Trigger Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Bit Symbol TA1TGL TA1TGH TA2TGL TA2TGH TA3TGL TA3TGH Address 038316 Bit Name Timer A1 event/trigger select bit After Reset 0016 Function To use the V-phase output control circuit, set these bits to “01 2”(TB2 underflow). RW RW RW RW RW RW RW RW RW Timer A2 event/trigger select bit To use the W-phase output control circuit, set these bits to “01 2”(TB2 underflow). Timer A3 event/trigger select bit 0 0 : Input on TA3 IN is selected (1) 0 1 : TB2 is selected (2) 1 0 : TA2 is selected (2) 1 1 : TA4 is selected (2) To use the U-phase output control circuit, set these bits to “01 2”(TB2 underflow). b5 b4 TA4TGL TA4TGH Timer A4 event/trigger select bit NOTES: 1. Set the corresponding port direction bit to 0 (input mode). 2. Overflow or underflow. Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Address 038016 Bit Name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag After reset 0016 Function 0 : Stops counting 1 : Starts counting RW RW RW RW RW RW RW RW RW Figure 12.31 TB2 Register, TRGSR Register, and TABSR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 132 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) Timer Ai Mode Register b7 b6 b5 b4 b3 b2 b1 b0 01 010 Symbol TA1MR TA2MR TA4MR Address 0397 16 0398 16 039A 16 Bit Name Operation mode select bit Pulse output function select bit External trigger select bit Trigger select bit After Reset 0016 0016 0016 Function Set to 10 2 (one-shot timer mode) for the three-phase motor control timer function Set to 0 for the three-phase motor control timer function No effect for the three-phase motor control timer function Set to 1 (selected by event/trigger select register) for the three-phase motor control timer function RW RW RW RW Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 RW RW RW RW RW Set to 0 for the three-phase motor control timer function b7 b6 Count source select bit TCK1 0 0 : f1 or f2 0 1 : f8 1 0 : f32 1 1 : fC32 Timer B2 Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol TB2MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 Address 039D 16 After Reset 00XX0000 2 Bit Name Operation mode select bit Function Set to 00 2 (timer mode) for the threephase motor control timer function RW RW RW RW RW RW RO RW RW No effect for the three-phase motor control timer function. If necessary, set to 0. When read, the contents are undefined Set to 0 for the three-phase motor control timer function When write in three-phase motor control timer function, write 0. When read, the content is undefined b7 b6 Count source select bit TCK1 0 0: f1 or f2 0 1: f8 1 0: f32 1 1: fC32 Figure 12.32 TA1MR, TA2MR, TA4MR, and TB2MR Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 133 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to 1. When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated deadtime timer. Figure 12.33 shows the example of triangular modulation waveform, and Figure 12.34 shows the example of sawtooth modulation waveform. __ ___ ___ Triangular waveform as a Carrier Wave Triangular wave Signal wave TB2S bit in the TABSR register Timer B2 Start trigger signal for timer A4(1) Timer A4 one-shot pulse(1) m m n n p p Rewrite registers IDB0 and IDB1 U phase output signal (1) U phase output signal (1) U phase U phase Dead time INV14 = 1 (“H” active) U phase Dead time U phase Transfer the values to the three-phase output shift register INV14 = 0 (“L” active) INV13 (INV11=1(three-phase mode 1)) NOTE: 1. Internal signals. See Figure 12.25. The above applies under the following conditions: INVC0 = 00XX11XX2 (X varies depending on each system) and INVC1 = 010XXXX02. Examples of PWM output change are: (2)When INV11 = 0 (three-phase mode 0) (1)When INV11 = 1 (three-phase mode 1) · INV01 = 0, ICTB2 = 116 (the timer B2 interrupt is generated · INV01 = 0 and ICTB2 = 216 (the timer B2 interrupt is generated whenever timer B2 underflows) every two times the timer B2 underflows), · Default value of the timer: TA4 = m. The TA4 register is changed or INV01 = 1, INV00 = 1, and ICTB2=116 (the timer B2 interrupt is whenever the timer B2 interrupt is generated. generated at the falling edge of the timer A1 reload control signal.) First time: TA4 = m. Second tim:, TA4 = n. · Default value of the timer: TA41 = m, TA4 = m. Third time: TA4 = n. Fourth time: TA4 = p. Registers TA4 and TA41 are changed whenever the timer B2 Fifth time: TA4 = p. interrupt is generated. · Default values of registers IDB0 and IDB1: First time, TA41 = n, TA4 = n. Second time, TA41 = p, TA4 = p. DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1. · Default values of registers IDB0 and IDB1: They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0 DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1. when the sixth timer B2 interrupt is generated. They are changed to DU0 = 1, DUB0 = 0, DU1= 1 and DUB1 = 0 when the third timer B2 interrupt is generated. The value written to registers TA4 and TA41 becomes effective at the rising edge of the timer A1 reload control signal. Figure 12.33 Triangular Wave Modulation Operation Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 134 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) Sawtooth Waveform as a Carrier Wave Sawtooth wave Signal wave Timer B2 Start trigger signal for timer A4(1) Timer A4 one-shot pulse(1) Rewrite registers IDB0 and IDB1 U phase output signal (1) U phase output signal (1) U phase Dead time U phase Transfer the values to the threephase output shift register INV14 = 0 (“L” active) INV14 = 1 (“H” active) U phase Dead time U phase NOTE: 1. Internal signals. See Figure 12.25. The above applies under the following conditions: INVC0 = 01XX110X2 (X varies depending on each system) and INVC1 = 010XXX002. Examples of PWM output change are: • Default value of registers IDB0 and IDB1: DU0=0, DUB0=1, DU1=1, DUB1=1. They are changed to DU0=1, DUB0=0, DU1=1, DUB1=1 when the timer B2 interrupt is generated. Figure 12.34 Sawtooth Wave Modulation Operation Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 135 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) 12.3.1 Position-Data-Retain Function This function is used to retain the position data synchronously with the three-phase waveform output.There are three position-data input pins for U, V, and W phases. A trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected by the PDRT bit in the PDRF register. This bit selects the retain trigger to be the falling edge of each positive phase, or the rising edge of each positive phase. 12.3.1.1 Operation of the Position-data-retain Function Figure 12.35 shows a usage example of the position-data-retain function (U phase) when the retain trigger is selected as the falling edge of the positive signal. (1) At the falling edge of the U-phase waveform ouput, the state at pin IDU is transferred to the PDRU bit in the PDRF register. (2) Until the next falling edge of the Uphase waveform output,the above value is retained. 1 2 Carrier wave U-phase waveform output U-phase waveform output Pin IDU PDRU bit Transferred Transferred Transferred Transferred Note: The retain trigger is the falling edge of the positive signal. Figure 12.35 Usage Example of Position-data-retain Function (U phase ) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 136 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) 12.3.1.2 Position-data-retain Function Control Register Figure 12.36 shows the structure of the position-data-retain function contol register. Position-Data-Retain Function Control Register (1) b7 b3 b2 b1 b0 Symbol PDRF Address 034E16 After Reset XXXX 00002 Bit Symbol PDRW PDRV PDRU PDRT (b7-b4) Bit Name W-phase position data retain bit V-phase position data retain bit U-phase position data retain bit Retain-trigger polarity select bit Function Input level at pin IDW is read out. 0: "L" level 1: "H" level Input level at pin IDV is read out. 0: "L" level 1: "H" level Input level at pin IDU is read out. 0: "L" level 1: "H" level 0: Rising edge of positive phase 1: Falling edge of positive phase RW RO RO RO RW Nothing is assigned. If necessary, set to 0. When read, the contents are undefined NOTE: 1.This register is valid only in the three-phase mode. Figure 12.36 PDRF Register 12.3.1.2.1 W-phase Position Data Retain Bit (PDRW) This bit is used to retain the input level at pin IDW. 12.3.1.2.2 V-phase Position Data Retain Bit (PDRV) This bit is used to retain the input level at pin IDV. 12.3.1.2.3 U-phase Position Data Retain Bit (PDRU) This bit is used to retain the input level at pin IDU. 12.3.1.2.4 Retain-trigger Polarity Select Bit (PDRT) This bit is used to select the trigger polarity to retain the position data. When this bit is set to 0, the rising edge of each positive phase selected. When this bit is set to 1, the falling edge of each pocitive phase selected. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 137 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) 12.3.2 Three-phase/Port Output Switch Function When the INVC03 bit in the INVC0 register set to 1 (Timer output enabled for three-phase motor control) __ and setting the PFCi (i=0 to 5) in the PFCR register to 0 (I/O port), the three-phase PWM output pin (U, U, __ ___ V, V, W and W) functions as I/O port. Each bit of the PFCi bits (i=0 to 5) is applicable for each one of three-phase PWM output pins. Figure 12.37 shows the example of three-phase/port output switch function. Figure 12.38 shows the PFCR register and the three-phase protect control register. Timer B2 U phase V Phase Functions as port P72 W phase Functions as port P74 Writing PFCR register PFC0 bit: 1 PFC2 bit: 1 PFC4 bit: 0 Writing PFCR register PFC0 bit: 1 PFC2 bit: 0 PFC4 bit: 1 Figure 12.37 Usage Example of Three-phse/Port Output Switch Function Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 138 of 458 M16C/29 Group 12. Timer (Three-phase Motor Control Timer Function) Port Function Control Register (1) b7 b5 b4 b3 b2 b1 b0 Symbol PFCR Address 035816 After Reset 0011 11112 Bit Symbol PFC0 PFC1 PFC2 PFC3 PFC4 PFC5 (b7-b6) Bit Name Port P80 output function select bit Port P81 output function select bit Port P72 output function select bit Port P73 output function select bit Port P74 output function select bit Port P75 output function select bit Function 0: Input/Output port P80 1: Three-phase PWM output (U phase output) 0: Input/Output port P81 1: Three-phase PWM output (U phase output) 0: Input/Output port P72 1: Three-phase PWM output (V phase output) 0: Input/Output port P73 1: Three-phase PWM output (V phase output) 0: Input/Output port P74 1: Three-phase PWM output (W phase output) 0: Input/Output port P75 1: Three-phase PWM output (W phase output) RW RW RW RW RW RW RW Nothing is assigned. If necessary, set to 0. When read, the contents are 0 NOTE: 1. This register is valid only when the INVC03 bit in the INVC0 register is 1 (Three-phase motor control timer. Three-phase Protect Control Register b7 b3 b2 b1 b0 Symbol TPRC Address 025A16 After Reset 0016 Bit Symbol TPRC0 (b7-b1) Bit Name Three-phase protect control bit Function Enable write to PFCR register 0: Write protected 1: Write enabled RW RW Nothing is assigned. If necessary, set to 0. When read, the contents are 0 Figure 12.38 PFCR Register, and TPRC Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 139 of 458 M16C/29 Group 13. Timer S 13. Timer S The Timer S (Input Capture/Output Compare : here after, Timer S is referred to as "IC/OC".) is a highperformance I/O port for time measurement and waveform generation. The IC/OC has one 16-bit base timer for free-running operation and eight 16-bit registers for time measurement and waveform generation. Table 13.1 lists functions and channels of the IC/OC. Table 13.1 IC/OC Functions and Channels Function Time measurement (1) Digital filter Trigger input prescaler Trigger input gate Waveform generation (1) Single-phase waveform output Phase-delayed waveform output Set/Reset waveform output 8 channels 8 channels 2 channels 2 channels 8 channels Available Available Available Description NOTE: 1. The time measurement function and the waveform generating function share a pin. The time measurement function or waveform generating function can be selected for each channel. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 140 of 458 M16C/29 Group 13. Timer S Figure 13.1 shows the block diagram of the IC/OC. Main clock, PLL clock, On-chip oscillator clock 1/2 PCLK0=0 PCLK0=1 f1 or f2 Request by matching G1BTRR and base timer Request by matching G1PO0 register and base timer Request from INT1 pin Base timer reset BTS f1 or f2 Two-phase pulse input BCK1 to BCK0 11 10 (n+1) Divider register (G1DV) fBT1 Base timer Base timer over flow request Base timer reset register (G1BTRR) INPC10 Digital filter Digital filter Digital filter Digital filter Digital filter 10:fBT1 11: f1 or f2 10:fBT1 11: f1 or f2 10:fBT1 11: f1 or f2 10:fBT1 11: f1 or f2 00 Edge select CTS1 to CTS0 Edge select CTS1 to CTS0 Edge select CTS1 to CTS0 Edge select CTS1 to CTS0 Edge select CTS1 to CTS0 Edge select CTS1 to CTS0 0 0 Base timer interrupt request Base timer reset request DF1 to DF0 00 DF1 to DF0 00 DF1 to DF0 00 G1TM0, G1PO0 (Note 1) register G1TM1, G1PO1 register G1TM2, G1PO2 register G1TM3, G1PO3 register G1TM4, G1PO4 register G1TM5, G1PO5 register OUTC10 PWM output OUTC11 INPC11 INPC12 OUTC12 PWM output OUTC13 INPC13 INPC14 DF1 to DF0 00 10:fBT1 11: f1 or f2 DF1 to DF0 00 DF1 to DF0 10:fBT1 11: f1 or f2 00 OUTC14 PWM output OUTC15 INPC15 Digital filter 10:fBT1 11: f1 or f2 INPC16 Digital filter DF1 to DF0 10:fBT1 11: f1 or f2 00 Edge select Gate function 1 CTS1 to CTS0 Edge select Gate 1 function GT 0 Prescaler function 1 PR 0 1 G1TM6, G1PO6 register OUTC16 PWM output OUTC17 INPC17 Digital debounce Digital filter DF1 to DF0 CTS1 to CTS0 GT Prescaler function PR G1TM7, G1PO7 register Ch0 to ch7 interrupt request signal BCK1 to BCK0 : Bits in the G1BCR0 register BTS: Bits in the G1BCR1 register CTS1 to CTS0, DF1 to DF0, GT, PR : Bits in the G1TMCRj register (j= 0 to 7) PCLK0 : Bits in the PCLKR register Figure 13.1 IC/OC Block Diagram Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 141 of 458 M16C/29 Group 13. Timer S Figures 13.2 to 13.10 show registers associated with the IC/OC base timer, the time measurement function, and the waveform generating function. Base Timer Register b15 (b7) b8 (b0) b7 b0 (1) Symbol G1BT Address 032116 - 032016 Function After Reset Undefined Setting Range RW When the base timer is operating: When read, the value of base timer plus 1 can be read. When write, the counter starts counting from the value written. When the base timer is reset, this register is set to 000016. (2) When the base timer is reset: This register is set to 000016 but a value read is undefined. No value is written. (2) 000016 to FFFF16 RW NOTES: 1. The G1BT register reflects the value of the base timer, synchronizing with the count source fBT1 cycles. 2. This base timer stops only when bits BCK1 to BCK0 in the G1BCR0 register are set to 002 (count source clock stop). The base timer operates when bits BCK1 to BCK0 are set to other than 002. When the BTS bit in the G1BCR1 register is set to 0, the base timer is reset continuously, and remaining set to 000016. When the BTS bit is set to 1, this state is cleared and the timer starts counting. Base Timer Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol G1BCR0 Address 032216 After Reset 0016 Bit Symbol BCK0 BCK1 RST4 Bit Name b1 b0 Function 0 0 1 1 0 : Clock stop 1 : Do not set to this value 0 : Two-phase input (1) 1 : f1 or f2 (2) RW RW RW RW Count source select bit Base timer reset cause select bit 4 0: Do not reset Base timer by matching G1BTRR 1: Reset Base timer by matching G1BTRR(3) Set to 0 0: P27/OUTC17/INPC17 pin 1: P17/INT5/INPC17/IDU pin 0: Bit 15 in the base timer overflows 1: Bit 14 in the base timer overflows (b5-b3) CH7INSEL IT Reserved bit Channel 7 input select bit Base timer interrupt select bit RW RW RW NOTES: 1. This setting can be used when bits UD1 to UD0 in the G1BCR1 register are set to 102 (twophase signal processing mode). Do not set bits BCK1 and BCK0 to 102 in other modes. 2. When the PCLK0 bit in the PCLKR register is set to 0, the count source is f2 cycles. And when the PCLK0 bit is set to set to 1, the count source is f1 cycles. 3. When the RST4 bit is set to 1, set the RST1 bit in the G1BCR1 register to 0. Figure 13.2 G1BT and G1BCR0 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 142 of 458 M16C/29 Group 13. Timer S Divider Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1DV Address 032A16 After Reset 0016 Function Divide f1, f2 or two-phase pulse input by (n+1) for fBT1 clock cycles generation. n: the setting value of the G1DV register Setting range 0016 to FF16 RW RW Base Timer Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol 0 0 0 G1BCR1 Bit Symbol (b0) Bit Name Reserved bit Address 032316 After Reset 0016 Function Set to 0 0: The base timer is not reset by matching the G1PO0 register 1: The base timer is reset by matching with the G1PO0 register (1) RW RW RST1 Base timer reset cause select bit 1 RW RST2 Base timer reset cause select bit 2 Reserved bit Base timer start bit 0: The base timer is not reset by applying "L" to the INT1 pin RW 1: The base timer is reset by applying "L" to the INT1 pin Set to 0 0: Base timer is reset 1: Base timer starts counting b6 b5 (b3) BTS UD0 UD1 RW RW Counter increment/ decrement control bit 0 0: Counter increment mode RW 0 1: Counter increment/decrement mode 1 0: Two-phase pulse signal processing mode RW 1 1: Do not set to this value Set to 0 RW (b7) Reserved bit NOTS: 1. The base timer is reset two fBT1 clock cycles after the base timer matches the value set in the G1PO0 register. (See Figure 13.7 for details on the G1PO0 register) When the RST1 bit is set to 1, the value of the G1POj register (j=1 to 7) for the waveform generating function must be set to a value smaller than that of the G1PO0 register. When the RST1 bit is set to 1, set the RST4 bit in the G1BCR0 register to 0. Figure 13.3 G1DV Register and G1BCR1 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 143 of 458 M16C/29 Group 13. Timer S Base Timer Reset Register(1) b15 (b7) b8 (b0) b7 b0 Symbol G1BTRR Address 032916 - 032816 Function After Reset Undefined Setting Range 000016 to FFFF16 RW RW When enabled by the RST4 bit in the G1BCR0 register, the base timer is reset by matching the G1BTRR register setting value and the base timer setting value. NOTE: 1. The G1BTRR register reflects the value of the base timer, synchronizing with the count source fBT1 cycles. Figure 13.4 G1BTRR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 144 of 458 M16C/29 Group 13. Timer S Time Measurement Control Register j (j=0 to 7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1TMCR0 to G1TMCR3 G1TMCR4 to G1TMCR7 Address 031816, 031916, 031A16, 031B16 031C16, 031D16, 031E16, 031F16 After Reset 0016 0016 Bit Symbol CTS0 CTS1 DF0 DF1 GT GOC GSC PR Bit Name b1 b0 Function 0 0 1 1 0 0 1 1 0 : No time measurement 1 : Rising edge 0 : Falling edge 1 : Both edges 0 : No digital filter 1 : Do not set to this value 0 : fBT1 1 : f1 or f2 (1) RW RW RW RW RW RW Time measurement trigger select bit b3 b2 Digital filter function select bit Gate function select bit (2) Gate function clear select bit (2, 3, 4) Gate function clear bit (2, 3) Prescaler function select bit (2) 0: Gate function is not used 1: Gate function is used 0: Not cleared 1: The gate is cleared when the base RW timer matches the G1POk register The gate is cleared by setting the GSC bit to 1 0: Not used 1: Used RW RW NOTES: 1. When the PCLK0 bit in the PCLKR register is set to 0, the count source is f2 cycles. And when the PCLK0 bit is set to 1, the count source is f1 cycles. 2. These bits are in registers G1TMCR6 and G1TMCR7. Set all bits 4 to 7 in registers G1TMCR0 to G1TMCR5 to 0. 3. These bits are enabled when the GT bit is set to 1. 4. The GOC bit is set to 0 after the gate function is cleared. See Figure 13.7 for details on the G1POk register (k=4 when j=6 and k=5 when j=7). Time Measurement Prescale Register j (j=6,7) b7 b0 (1) Symbol Address G1TPR6 to G1TPR7 032416, 032516 After Reset 0016 Function As the setting value is n, time is measured whenever a trigger input is counted by n+1 (2) Setting Range 0016 to FF16 RW RW NOTES: 1. The G1TPR6 to G1TPR7 registers reflect the base timer value, synchronizing with the count source fBT1 cycles. 2. The first prescaler, after the PR bit in the G1TMCRj register is changed from 0 (not used) to 1 (used), may be divided by n, rather than n+1. The subsequent prescaler is divided by n+1. Figure 13.5 G1TMCR0 to G1TMCR7 Registers, and G1TPR6 to G1TPR7 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 145 of 458 M16C/29 Group 13. Timer S Waveform Generation Register j (j=0 to 7) b15 (b7) b8 (b0) b7 b0 Symbol G1TM0 to G1TM2 G1TM3 to G1TM5 G1TM6 to G1TM7 Address 030116-030016, 030316-030216, 030516-030416 030716-030616, 030916-030816, 030B16-030A16 030D16-030C16, 030F16-030E16 After Reset Indeterminte Indeterminte Indeterminte Function The base timer value is stored every measurement timing Setting Range RW RO Waveform Generation Control Register j (j=0 to 7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1POCR0 to G1POCR3 G1POCR4 to G1POCR7 Address 031016, 031116, 031216, 031316 031416, 031516, 031616, 031716 After Reset 0X00 XX002 0X00 XX002 Bit Symbol MOD0 Bit Name b1b0 Function 0 0 : Single waveform output mode 0 1 : SR waveform output mode (1) 1 0 : Phase-delayed waveform output mode 1 1 : Do not set to this value RW Operating mode select bit RW MOD1 (b3-b2) IVL RW Nothing is assigned. If necessary, set to 0. When read, their contents are undefined Output initial value select bit(4) G1POj register value reload timing select bit 0: "L" output as a default value 1: "H" output as a default value RW RLD 0: Reloads the G1POj register when value is written RW 1: Reloads the G1POj register when the base timer is reset (b6) INV Nothing is assigned. If necessary, set to 0. When read, its content is undefined Inverse output function select bit (2) 0: Output is not inversed 1: Output is inversed RW NOTES : 1. This setting is enabled only for even channels. In SR waveform output mode, values written to the corresponding odd channel (next channel after an even channel) are ignored. Even channels provide waveform output. Odd channels provide no waveform output. 2. The inverse output function is the final step in waveform generating process. When the INV bit is set to 1, and "H" signal is provided a default output by setting the IVL bit to 0, and an "L" signal is provided by setting it to 1. 3. In the SR waveform output mode, set not only the even channel but also the correspoinding even channel (next channel after the even channel). 4. To provide either "H" or "L" signal output set in the IVL bit, set the FSCj bit in the G1FS register to 0 (select waveform generating function) and IFEj bit in the G1FE register to 1 (functions for channel j enabled). Then set the IVL bit to 0 or 1. Figure 13.6 G1TM0 to G1TM7 Registers, and G1POCR0 to G1POCR7 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 146 of 458 M16C/29 Group 13. Timer S Waveform Generation Register j (j=0 to 7) b15 (b7) b8 (b0) b7 b0 Symbol G1PO0 to G1PO2 G1PO3 to G1PO5 G1PO6 to G1PO7 Address 030116-030016, 030316-030216, 030516-030416 030716-030616, 030916-030816, 030B16-030A16 030D16-030C16, 030F16-030E16 After Reset Undefined Undefined Undefined Function When the RLD bit in the G1POCRj register is set to 0, value written is immediately reloaded into the G1POj register for output, for example, a waveform output,reflecting the value. When the RLD bit is set to 1, value reloaded while the base timer is reset. The value written can be read until reloaded Setting Range RW 000016 to FFFF16 RW Figure 13.7 G1PO0 to G1PO7 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 147 of 458 M16C/29 Group 13. Timer S Function Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1FS Bit Symbol FSC0 FSC1 FSC2 FSC3 FSC4 FSC5 FSC6 FSC7 Address 032716 After Reset 0016 Bit Name Channel 0 time measurement/waveform generating function select bit Channel 1 Time Measurement/Waveform Generating Function Select Bit Channel 2 time measurement/waveform generating function select bit Channel 3 time measurement/waveform generating function select bit Channel 4 time measurement/waveform generating function select bit Channel 5 time measurement/waveform generating function select bit Channel 6 time measurement/waveform generating function select bit Channel 7 time measurement/waveform generating function select bit Function 0: Select the waveform generating function 1: Select the time measurement function RW RW RW RW RW RW RW RW RW Function Enable Register(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1FE Bit Symbol IFE0 IFE1 IFE2 IFE3 IFE4 IFE5 IFE6 IFE7 Address 032616 After Reset 0016 Bit Name Channel 0 function enable bit Channel 1 function enable bit Channel 2 function enable bit Channel 3 function enable bit Channel 4 function enable bit Channel 5 function enable bit Channel 6 function enable bit Channel 7 function enable bit Function 0 : Disable function s for channel j 1 : Enable functions for channel j (j=0 to 7) (2) RW RW RW RW RW RW RW RW RW NOTES: 1. The G1FE register reflects the base timer value, synchronizing with the count source fBT1 cycles. 2. When functions for the channel j are disabled, each pin functions as an I/O port. Figure 13.8 G1FS and G1FE Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 148 of 458 M16C/29 Group 13. Timer S Interrupt Request Register b7 b6 b5 b4 b3 b2 b1 b0 (1) Address 033016 After Reset Undefined Symbol G1IR Bit Symbol G1IR0 G1IR1 G1IR2 G1IR3 G1IR4 G1IR5 G1IR6 G1IR7 Bit Name Interrupt request, Ch0 Interrupt request, Ch1 Interrupt request, Ch2 Interrupt request, Ch3 Interrupt request, Ch4 Interrupt request, Ch5 Interrupt request, Ch6 Interrupt request, Ch7 Function 0 : No interrupt request 1 : Interrupt requested RW RW RW RW RW RW RW RW RW NOTE: 1. When writing 0 to each bit in the G1IR register, use the following instruction: AND, BCLR Figure 13.9 G1IR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 149 of 458 M16C/29 Group 13. Timer S Interrupt Enable Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1IE0 Bit Symbol G1IE00 G1IE01 G1IE02 G1IE03 G1IE04 G1IE05 G1IE06 G1IE07 Address 033116 After Reset 0016 Bit Name Interrupt enable 0, CH0 Interrupt enable 0, CH1 Interrupt enable 0, CH2 Interrupt enable 0, CH3 Interrupt enable 0, CH4 Interrupt enable 0, CH5 Interrupt enable 0, CH6 Interrupt enable 0, CH7 Function 0 : IC/OC interrupt 0 request disable 1 : IC/OC interrupt 0 request enable RW RW RW RW RW RW RW RW RW Interrupt Enable Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1IE1 Bit Symbol G1IE10 G1IE11 G1IE12 G1IE13 G1IE14 G1IE15 G1IE16 G1IE17 Address 033216 After Reset 0016 Bit Name Interrupt enable 1, CH0 Interrupt enable 1, CH1 Interrupt enable 1, CH2 Interrupt enable 1, CH3 Interrupt enable 1, CH4 Interrupt enable 1, CH5 Interrupt enable 1, CH6 Interrupt enable 1, CH7 Function 0 : IC/OC interrupt 1 request disable 1 : IC/OC interrupt 1 request enable RW RW RW RW RW RW RW RW RW Figure 13.10 G1IE0 and G1IE1 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 150 of 458 M16C/29 Group 13. Timer S 13.1 Base Timer The base timer is a free-running counter that counts an internally generated count source. Table 13.2 lists specifications of the base timer. Table 13.3 shows registers associated with the base timer. Figure 13.11 shows a block diagram of the base timer. Figure 13.12 shows an example of the base timer in counter increment mode. Figure 13.13 shows an example of the base timer in counter increment/decrement mode. Figure 13.14 shows an example of two-phase pulse signal processing mode. Table 13.2 Base Timer Specifications Item Count source(fBT1) Specification f1 or f2 divided by (n+1) , two-phase pulse input divided by (n+1) n: determined by the DIV7 to DIV0 bits in the G1DV register. n=0 to 255 However, no division when n=0 The base timer increments the counter value The base timer increments/decrements the counter value Two-phase pulse signal processing The BTS bit in the G1BCR1 register is set to 1 (base timer starts counting) The BTS bit in the G1BCR1 register is set to 0 (base timer reset) (1) The value of the base timer matches the value of the G1BTRR register (2) The value of the base timer matches the value of G1PO0 register. ________ (3) Apply a low-level signal ("L") to external interrupt pin,INT1 pin 000016 The base timer interrupt request is generated: (1) When the bit 14 or bit 15 in the base timer overflows (2) The value of the base timer value matches the value of the base timer reset register • The G1BT register indicates a counter value while the base timer is running • The G1BT register is undefined when the base timer is reset When a value is written while the base timer is running, the timer counter immediately starts counting from this value. No value can be written while the base timer is reset. • Counter increment/decrement mode The base timer starts counting from 000016. After incrementing to FFFF16, the timer counter is then decremented back to 000016. The base timer increments the counter value again when the timer counter reaches 000016. (See Figure 13.13) • Two-phase pulse processing mode Two-phase pulse signals from pins P80 and P81 are counted (See Figure 13.14) P80 Counting operation Count start condition Count stop condition Base timer reset condition Value for base timer reset Interrupt request Read from timer Write to timer Selectable function P81 The timer increments a counter on all edges The timer decrements a counter on all edges Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 151 of 458 M16C/29 Group 13. Timer S fBT1 f1 or f2 Two-phase pulse input 11 10 BCK1 to BCK0 (n+1) divider (Note 1) 0 Base timer b14 b15 Overflow signal Base timer overflow request IT BTS bit in G1BCR1 register RST4 Matched with G1BTRR RST1 Matched with G1PO0 register RST2 Input "L" to INT1 pin Base timer reset 1 NOTE: 1. Divider is reset when the BTS bit is set to 0. IT, RST4, BCK1 to BCK0: Bits in the G1BCR0 register RST2 to RST1: Bits in the G1BCR1 register Figure 13.11 Base Timer Block Diagram Table 13.3 Base Timer Associated Register Settings (Time Measurement Function, Waveform Generation Function, Communication Function) Register G1BCR0 Bit BCK1 to BCK0 RST4 IT RST2 to RST1 BTS UD1 to UD0 Function Select a count source Select base timer reset timing Select the base timer overflow Select base timer reset timing Used to start the base timer Select how to count Read or write base timer value Divide ratio of a count source G1BCR1 G1BT G1DV Set the following registers to set the RST1 bit to 1 (base timer reset by matching the base timer with the G1PO0 register) G1POCR0 MOD1 to MOD0 Set to 002 (single-phase waveform output mode) G1PO0 G1FS G1FE FSC0 IFE0 Set reset cycle Set to 0 (waveform generating function) Set to 1 (channel operation start) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 152 of 458 M16C/29 Group 13. Timer S FFFF16 C00016 800016 400016 000016 State of a counter IT=1 in the G1BCR0 register (Base timer interrupt generated by the bit 14 overflow) b14 overflow signal Base Timer interrupts 1 0 IT=0 in the G1BCR0 register (Base timer interrupt generated by the bit 15 overflow) b15 overflow signal Base Timer interrupt 1 0 The above applies to the following conditions. The RST4 bit in the G1BCR0 register is set to 0 (the base timer is not reset by matching the G1BTRR register) The RST1 bit in the G1BCR1 register is set to 0 (the base timer is not reset by matching the G1PO0 register) Bits UD1 to UD0 in the G1BCR1 register are set to 002 (counter increment mode) Figure 13.12 Counter Increment Mode FFFF16 C00016 800016 400016 000016 State of a counter IT=1 in the G1BCR0 register (Base timer interrupt generated by the bit 14 overflow) b14 overflow signal Base Timer interrupts 1 0 IT=0 in the G1BCR0 register (Base timer interrupt generated by the bit 15 overflow) b15 overflow signal Base Timer interrupt 1 0 Figure 13.13 Counter Increment/Decrement Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 153 of 458 M16C/29 Group 13. Timer S (1) When the base timer is reset while the base timer increments the counter P80 (A-phase) Input waveform P81 (B-phase) fBT1 min 1 µs min 1 µs ( When selects no division with the divider by (n+1) ) (Note 1) INT1 (Z-phase) Base timer starts counting Value of counter m m+1 Set to 0 at this timing 0 1 2 Set to 1 at this timing (2) When the base timer is reset while the base timer decrements the counter P80 (A-phase) Input waveform P81 (B-phase) fBT1 min 1 µs min 1 µs ( When selects no division with the divider by (n+1) ) (1) INT1 (Z-phase) Base timer starts counting Value of counter m m-1 0 FFFF16 FFFE16 Set to 0 at this timing NOTE: 1. 1.5 fBT1 clock cycle or more are required. Set to FFFF16 at this timing Figure 13.14 Base Timer Operation in Two-phase Pulse Signal Processing Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 154 of 458 M16C/29 Group 13. Timer S 13.1.1 Base Timer Reset Register(G1BTRR) The G1BTRR register provides the capability to reset the base timer when the base timer count value matches the value stored in the G1BTRR register. The G1BTRR register is enabled by the RST4 bit in the G1BCR0 register. This function is identical in operation to the G1PO0 base timer reset that is enabled by the RST1 bit in the G1BCR0 reigster. If the free-running operation is not selected, the channel 0 can be used for a waveform generation when the base timer is reset by the G1BTRR register. Do not enable bits RST1 and RST4 simultaneously. RST4 Base timer (Base timer reset register) m-2 m-1 m m m + 1 000016 000116 G1BTRR register Base timer interrupt Base timer overflow request (1) NOTE: 1. Following conditions are required to generate a base timer overflow request by resetting the base timer. If the IT bit is set to 0: 07FFF16 ≤ m ≤ 0FFFE16 If the IT bit is set to 1: 07FFF16 ≤ m ≤ 0FFFE16 or 0BFFF16 ≤ m ≤ 0FFFE16 Figure 13.15 Base Timer Reset operation by Base Timer Reset Register RST1 Base timer G1PO0 G1IR0 Figure 13.16 Base Timer Reset operation by G1PO0 register m-2 m-1 m m m + 1 000016 000116 RST2 Base timer P83/INT1 NOTE: ________ ________ 1. INT1 Base Timer reset does not generate a Base Timer interrupt. INT1 may generate an interrupt if enabled. _______ m-2 m-1 m m + 1 000016 000116 Figure 13.17 Base Timer Reset operation by INT1 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 155 of 458 M16C/29 Group 13. Timer S 13.2 Interrupt Operation The IC/OC interrupt contains several request causes. Figure 13.18 shows the IC/OC interrupt block diagram and Table 13.4 shows the IC/OC interrupt assignation. When either the base timer reset request or base timer overflow request is generated, the IR bit in the BTIC register corresponding to the IC/OC base timer interrupt is set to 1 (with an interrupt request). Also when an interrupt request in each eight channels (channel i) is generated, the bit i in the G1IR register is set to 1 (with an interrupt request). At this time, if the bit i in the G1IE0 register is 1 (IC/OC interrupt 0 request enabled), the IR bit in the ICOC0IC register corresponding to the IC/OC interrupt 0 is set to 1 (with an interrupt request). And if the bit i in the G1IE1 register is 1 (IC/OC interrupt 1 request enabled), the IR bit in the ICOC1IC register corresponding to the IC/OC interrupt 1 is set to 1(with an interrupt request). Additionally, because each bit in the G1IR register is not automatically set to 0 even if the interrupt is acknowledged, set to 0 by program. If these bits are left as 1, all IC/OC channel interrupt causes, which are generated after setting the IR bit to 1, will be disabled. Interrupt Select Logic DMA Requests (channel 0 to 7) Channel 0 to 7 Interrupt requests All register are read / write ENABLE G1IE0 REQUEST G1IR ENABLE G1IE1 IC/OC interrupt 1 request IC/OC interrupt 0 request Base timer reset request Base timer overflow request IC/OC base timer interrupt request Base Timer Interrupt / DMA Request Figure 13.18 IC/OC Interrupt and DMA request generation Table 13.4 Interrupt Assignment Interrupt IC/OC base timer interrupt IC/OC interrupt 0 IC/OC interrupt 1 Interrupt control register BTIC(004716) ICOC0IC(004516) ICOC0IC(004616) 13.3 DMA Support Each of the interrupt sources - the eight IC/OC channel interrupts and the one Base Timer interrupt - are capable of generating a DMA request. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 156 of 458 M16C/29 Group 13. Timer S 13.4 Time Measurement Function In synchronization with an external trigger input, the value of the base timer is stored into the G1TMj register (j=0 to 7). Table 13.5 shows specifications of the time measurement function. Table 13.6 shows register settings associated with the time measurement function. Figures 13.19 and 13.20 display operational timing of the time measurement function. Figure 13.21 shows operational timing of the prescaler function and the gate function. Table 13.5 Time Measurement Function Specifications Item Measurement channel Selecting trigger input polarity Measurement start condition Channels 0 to 7 Rising edge, falling edge, both edges of the INPC1j pin (1) The IFEj bit in the G1FE register should be set to 1 (channels j function enabled) when the FSCj bit (j=0 to 7) in the G1FS register is set to 1 (time measurement function selected). Measurement stop condition Time measurement timing The IFEj bit should be set to 0 (channel j function disabled) •No prescaler : every time a trigger signal is applied •Prescaler (for channel 6 and channel 7): every G1TPRk (k=6,7) register value +1 times a trigger signal is applied Interrupt request generation timing INPC1j pin function Selectable function (1) Specification The G1IRi bit (i=0 to 7) in the interrupt request register (See Figure 13.9) is set to 1 at time measurement timing Trigger input pin • Digital filter function The digital filter samples a trigger input signal level every f1, f2 or fBT1 cycles and passes pulse signal matching trigger input signal level three times • Prescaler function (for channel 6 and channel 7) Time measurement is executed every G1TPRk register value +1 times a trigger signal is applied • Gate function (for channel 6 and channel 7) After time measurement by the first trigger input, trigger input cannot be accepted. However, while the GOC bit in the G1TMCRk register is set to 1 (gate cleared by matching the base timer with the G1POp register (p=4 when k=6, p=5 when k=7)), trigger input can be accepted again by matching the base timer value with the G1POp register setting • Digital Debounce function (for channel7) See 13.6.2 Digital Debounce Function for P17/INT5/INPC17 and 19.6 Digital Debounce Function for details ________ NOTE: 1. The INPC10 to INPC17 pins Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 157 of 458 M16C/29 Group 13. Timer S Table 13.6 Register Settings Associated with the Time Measurement Function Register G1TMCRj Bit CTS1 to CTS0 DF1 to DF0 GT, GOC, GSC PR G1TPRk G1FS G1FE FSCj IFEj Select time measurement trigger Select the digital filter function Select the gate function Select the prescaler function Setting value of prescaler Set to 1 (time measurement function) Set to 1 (channel j function enabled) Function j = 0 to 7 k = 6, 7 Bit configurations and function varys with channels used. Registers associated with the time measurement function must be set after setting registers associated with the base timer. INPC1j pin input FFFF16 n Base timer p m 000016 G1TMj register G1IRj bit m n p When setting to 0, write 0 by program j = 0 to 7 G1IRj bit: Bits in the G1IR register The above applies to the following condition. Bits CTS1 to CTS0 in the G1TMCRj registers are set to 012 (rising edge). The PR bit is set to 0 (no prescaler used) and the GT bit is set to 0 (no gate function used). Bits RTS4, RTS2, and RTS1 in registers G1BCR0 and G1BCR1 are set to 0 (no base timer reset). Bits UD1 to UD0 bits are set to 002 (counter increment mode). Set the base timer to 000016 (setting the RST1 bit to 1, and bits RST4 and RST2 to 0), when the base timer value matches the G1PO0 register setting. The base timer is set to 000016 after it reaches the G1PO0 register value + 2. Figure 13.19 Time Measurement Function (1) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 158 of 458 M16C/29 Group 13. Timer S (a) When selecting the rising edge as a timer measurement trigger (Bits CTS1 and CTS0 in the G1TMCRj register (j=0 to 7)=012) fBT1 Base timer INPC1j pin input or trigger signal after passing the digital filter G1IRj bit (1) Delayed by 1 clock n n-2 n-1 n+1 n+2 n+3 n+4 n+5 (2) n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 write 0 by program if setting to 0 n +5 n+8 G1TMj register n NOTES : 1. Bits in the G1IR register. 2. Input pulse applied to the INPC1j pin requires 1.5 fBT1 clock cycles or more. . (b) When selecting both edges as a timer measurement trigger (Bits CTS1 and CTS0 = 112) fBT1 Base timer INPC1j pin input or trigger signal after passing the digital filter G1IRj bit (1) n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 write 0 by program if setting to 0 G1TMj register (2) n n+2 n+5 n+8 n+12 NOTES : 1. Bits in the G1IR register. 2. No interrupt is generated if the MCU receives a trigger signal when the G1IRj bit is set to 1. . However, the value of the G1TMj register is updated. (c) Trigger signal when using digital filter (Bits DF1 to DF0 in the G1TMCRj register =102 or 112) f1 or f2 or fBT1 (1) INPC1j pin Trigger signal after passing the digital filter Signals, which do not match 3 times, are stripped off Maximum 3.5 f1 or f2 or fBT1 (1) clock cycles The trigger signal is delayed by the digital filter NOTE: 1. fBT1 when bits DF1 to DF0 are set to 102, and f1 or f2 when set to 112. Figure 13.20 Time Measurement Function (2) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 159 of 458 M16C/29 Group 13. Timer S (a) With the prescaler function (When the G1TPRj register (j = 6, 7) is set to 0216, the PR bit in the G1TMCRj register (j = 6, 7) is set to 1) fBT1 Base timer INPC1j pin input or trigger signal after passing the digital filter Internal time measurement trigger Prescaler (1) n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 +12 n+13 n+14 2 1 0 2 Set 0 by program if necessary G1IRj bit (2) G1TMj register n+1 n+13 NOTES: 1. This applies to 2nd or later prescaler cycle after the PR bit in the G1TMCRj register is set to 1 (prescaler used). 2. Bits in the G1IR register. (b) With the gate function (The gate function is cleared by matching the base timer with the G1POk register(k = 4, 5), the GT bit in the G1TMCRj register is set to 1, the GOC bit is set to 1) fBT1 FFFF16 Base timer 000016 Value of the G1POk register IFEj bit in G1FE register INPC1j pin input or trigger signal after passing the digital filter Internal time measurement trigger G1POk register match signal Gate control signal Gate Gate cleared Gate This trigger input is disabled due to gate function. G1IRj bit (1) G1TMj register NOTE: 1. Bits in the G1IR register. Set 0 by program if necessary Figure 13.21 Prescaler Function and Gate Function Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 160 of 458 M16C/29 Group 13. Timer S 13.5 Waveform Generating Function Waveforms are generated when the base timer value matches the G1POj (j=0 to 7) register value. The waveform generating function has the following three modes : • Single-phase waveform output mode • Phase-delayed waveform output mode • Set/Reset waveform output (SR waveform output) mode Table 13.7 lists registers associated with the waveform generating function. Table 13.7 Registers Related to the Waveform Generating Function Settings Register G1POCRj Bit MOD1 to MOD0 IVL RLD INV FSCj IFEj Function Select output waveform mode Select default value Select G1POj register value reload timing Select inverse output Select timing to output waveform inverted Set to 0 (waveform generating function) Set to 1 (enables function on channel j) G1POj G1FS G1FE j = 0 to 7 Bit configurations and functions vary with channels used. Registers associated with the waveform generating function must be set after setting registers associated with the base timer. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 161 of 458 M16C/29 Group 13. Timer S 13.5.1 Single-Phase Waveform Output Mode Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRj (j=0 to 7) register is set to 0(output is not reversed) and the base timer value matches the G1POj (j=0 to 7) register value. The "H" signal switches to a low-level ("L") signal when the base timer reaches 000016. Table 13.8 lists specifications of single-phase waveform mode. Figure 13.22 lists an example of single-phase waveform mode operation. Table 13.8 Single-phase Waveform Output Mode Specifications Item Output waveform • Free-running operation (bits RST1, RST2, and RST4 of registers G1BCR1 and G1BCR0 are set to 0 (no reset)) Cycle 65536 fBT1 m Default output level width : fBT1 65536-m Inverse level width : fBT1 : Specification • The base timer is cleared to 000016 by matching the base timer with either following register (a) G1PO0 register (enabled by setting RST1 bit to 1, and RST4 and RST2 bits to 0), or (b) G1BTRR register (enabled by setting RST4 bit to 1, and RST2 and RST1 bits to 0) n+2 fBT1 m Default output level width : fBT1 n+2-m Inverse level width : fBT1 m : setting value of the G1POj register (j=0 to 7), 000116 to FFFD16 Cycle : n : setting value of the G1PO0 register or the G1BTRR register, 000116 to FFFD16 Waveform output start condition Waveform output stop condition Interrupt request OUTC1j pin (1) The IFEj bit in the G1FE register is set to 1 (channel j function enabled) The IFEj bit is set to 0 (channel j function disabled) The G1IRj bit in the G1IR register is set to 1 when the base timer value matches the G1POj register value (See Figure 13.22) Pulse signal output pin • Default value set function: Set starting waveform output level • Inverse output function: Waveform output signal is inversed and provided from the OUTC1j pin Selectable function NOTE: 1. Pins OUTC10 to OUTC17. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 162 of 458 M16C/29 Group 13. Timer S (1) Free-running operation (The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to 0) FFFF16 Base timer m 000016 m fBT1 65536-m fBT1 Inverse 65536 fBT1 Inverse Return to default output level OUTC1j pin G1IRj bit When setting to 0, write 0 by program j=0 to 7 m : Setting value of the G1POj register G1IRj bit : Bits in the G1IR register The above applies under the following conditions. -The IVL bit in the G1POCRj register is set to 0 ("L" output as a default value) and the INV bit is set to 0 (not inversed). -Bits UD1 to UD0 are set to 002 (counter increment mode). (2) The base timer is reset when the base timer matches either following register (a) G1PO0 (enabled by setting bit RST1 to 1, and bits RST4 and RST2 to 0), or (b) G1BTRR (enabled by setting bit RST4 to 1, and bits RST2 and RST1 to 0) FFFF16 n+2 Base timer m 000016 m fBT1 n+2-m fBT1 Inverse Inverse Inverse Return to default output level OUTC1j pin G1IRj bit n+2 fBT1 Write 0 by program if setting to 0 j=1 to 7 m : Setting value of the G1POj register n: Setting value of either G1PO0 register or G1BTRR register G1IRj bit : Bits in the G1IR register The above applies under the following conditions. -The IVL bit in the G1POCRj register is set to 0 ("L" output as a default value) and the INV bit is set to 0 (not inversed). -Bits UD1 to UD0 are set to 002 (counter increment mode). Figure 13.22 Single-phase Waveform Output Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 163 of 458 M16C/29 Group 13. Timer S 13.5.2 Phase-Delayed Waveform Output Mode Output signal level of the OUTC1j pin is inversed every time the base timer value matches the G1POj register value ( j=0 to 7). Table 13.9 lists specifications of phase-delayed waveform mode. Figure 13.23 shows an example of phase-delayed waveform mode operation. Table 13.9 Phase-delayed Waveform Output Mode Specifications Item Output waveform • Free-running operation (bits RST1, RST2, and RST4 in registers G1BCR1 and G1BCR0 are set to 0 (no reset)) Cycle "H" and "L" width : : 65536 x 2 fBT1 65536 fBT1 Specification • The base timer is cleared to 000016 by matching the base timer with either following register (a) G1PO0 register (enabled by setting RST1 bit to 1, and bits RST4 and RST2 to 0), or (b) G1BTRR register (enabled by setting RST4 bit to 1, and bits RST2 and RST1 to 0) Cycle "H" and "L" width 2(n+2) fBT1 n+2 : fBT1 : n : setting value of either G1PO0 register or G1BTRR register Waveform output start condition Waveform output stop condition Interrupt request OUTC1j pin (1) The IFEj bit in the G1FE register is set to 1 (channel j function enabled) The IFEj bit is set to 0 (channel j function disabled) The G1IRj bit in the interrupt request register is set to 1 when the base timer value matches the G1POj register value. (See Figure 13.23) Pulse signal output pin • Default value set function: Set starting waveform output level • Inverse output function : Waveform output signal is inversed and provided from the OUTC1j pin Selectable function NOTE: 1. Pins OUTC10 to OUTC17. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 164 of 458 M16C/29 Group 13. Timer S (1) Free-running operation (Bits RST4, RST2, and RST1 in the registers G1BCR0 and G1BCR1 are set to 0) FFFF16 Base timer m 000016 65536 fBT1 Inverse Write 0 by program if setting to 0 65536 fBT1 Inverse 65536X2 fBT1 OUTC1j pin G1IRj bit j=0 to 7 m : Setting value of the G1POj register G1IRj bit : Bits in the G1IR register The above applies under the following conditions. The IVL bit in the G1POCRj register is set to 0 (L output as a default value). The INV bit is set to 0 (not inversed). Bits UD1 to UD0 are set to 002 (counter increment mode). (2) Base timer is reset when the base timer matches either following register (a) G1PO0 (enabled by setting bit RST1 to 1, and bits RST4 and RST2 to 0), or (b) G1BTRR (enabled by setting bit RST4 to 1, and bits RST2 and RST1 to 0) FFFF16 Base timer n+2 m 000016 m fBT1 n+2 fBT1 Inverse Write 0 by program if setting to 0 n+2 fBT1 Inverse Inverse OUTC1j pin 2(n+2) fBT1 G1IRj bit j=1 to 7 m : Setting value of the G1POj register G1IRj bit : Bits in the G1IR register n: Setting value of either register G1PO0 or G1BTRR The above applies under the following conditions. The IVL bit in the G1POCRj register is set to 0 (L output as a default value). The INV bit is set to 0 (not inversed). Bits UD1 to UD0 are set to 002 (counter increment mode). Figure 13.23 Phase-delayed Waveform Output Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 165 of 458 M16C/29 Group 13. Timer S 13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRi (i=0 to 7) is set to 0 (output is not reversed) and the base timer value matches the G1POj register value (j=0, 2, 4, 6). The "H" signal switches to a low-level ("L") signal when the base timer value matches the G1POk (k=j+1) register value. Table 13.10 lists specifications of SR waveform mode. Figure 13.24 shows an example of the SR waveform mode operation. Table 13.10 SR Waveform Output Mode Specifications Item Output waveform • Free-running operation (the RST1, RTS2, and RST4 bits of the G1BCR1 and G1BCR0 registers are set to 0 (no reset)) 65536 fBT1 n-m Inverse level width(1) : fBT1 • The base timer is cleared to 000016 by matching the base timer with either Cycle : following register (a) G1PO0 register (enabled by setting RST1 bit to 1, and bits RST4 and RST2 to 0)(2), or (b) G1BTRR register (enabled by setting RST4 bit to 1, and bits RST2 and RST1 to 0) Cycle : p+2 fBT1 n-m fBT1 Specification Inverse level width(1) : m : setting value of the G1POj register (j=0, 2, 4, 6 ) n : setting value of the G1POk register (k=j+1) p : setting value of the G1PO0 register or G1BTRR register value range of m, n, p: 000116 to FFFD16 Waveform output start condition Waveform output stop condition Interrupt request Bits IFEj and IFEk in the G1FE register is set to 1 (channel j function enabled) Bits IFEj and IFEk are set to 0 (channel j function disabled) The G1IRj bit in the G1IR register is set to 1 when the base timer value matches the G1POj register value. The G1IRk bit in the interrupt request register is set to 1 when the base timer value matches the G1POk register value (See Figure 13.24) OUTC1j pin (3) Selectable function Pulse signal output pin • Default value set function : Set starting waveform output level • Inverse output function: Waveform output signal is inversed and provided from the OUTC1j pin NOTES: 1. The odd channel's waveform generating register must have greater value than the even channel's. 2. When the G1PO0 register resets the base timer, the channel 0 and channel 1 SR waveform generating functions are not available. 3. Pins OUTC10, OUTC12, OUTC14, OUTC16. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 166 of 458 M16C/29 Group 13. Timer S (1) Free-running operation (Bits RST2 and RST1 in the G1BCR0 register and the RST4 bit in the G1BCR1 register are set to 0) FFFF16 n Base timer m 000016 n-m fBT1 Inverse 65536-n+m fBT1 Inverse 65536 fBT1 OUTC1j pin Return to default output level G1IRj bit G1IRk bit Write 0 by program if setting to 0 inverse j=0, 2, 4, 6 k=j+1 m : Setting value of the G1POj register n: Setting value of the G1POk register G1IRj, G1IRk bits: Bits in the G1IR register The above applies under the following conditions. The IVL bit in the G1POCRj register is set to 0 (L output as a default value). The INV bit is set to 0 (not inversed). Bits UD1 and UD0 are set to 002 (counter increment mode). (2) Base timer is reset when the base timer matches either following register (a) G1PO0 (enabled by setting bit RST1 to 1, and bits RST4 and RST2 to 0), or (b) G1BTRR (enabled by setting bit RST4 to 1, and bits RST2 and RST1 to 0) FFFF16 p+2 n Base timer m 000016 n-m fBT1 p+2-n+m fBT1 Return to default output level OUTC1j pin p+2 fBT1 Write 0 by program if setting to 0 When setting to 0, write 0 by program G1IRj bit G1IRk bit j=2, 4, 6 k=j+1 m : Setting value of the G1POj register n: Setting value of the G1POk register p: Setting value of either register G1PO0 or G1BTRR G1IRj, G1IRk bits: Bits in the G1IR register The above applies under the following conditions. The IVL bit in the G1POCRj register is set to 0 (L output as a default value). The INV bit is set to 0 (not inversed). Bits UD1 and UD0 are set to 002 (counter increment mode). Figure 13.24 Set/Reset Waveform Output Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 167 of 458 M16C/29 Group 13. Timer S 13.6 I/O Port Function Select The value in the G1FE and G1FS registers decides which IC/OC pin to be an input or output pin. In SR waveform generating mode, two channels, a set of even channel and odd channel, are used every output waveform, however, the waveform is output from an even channel only. In this case, the corresponding pin to the odd channel can be used as an I/O port. Table 13.11 Pin setting for Time Measurement and Waveform Generating Functions Pin P27/INPC17/ OUTC17 IFE FSC MOD1 MOD0 Port Direction 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 X 1 0 0 0 X 1 0 0 0 X 1 0 0 0 X 1 0 0 0 X 1 0 0 0 X 1 0 0 0 X 1 0 0 0 X 1 0 0 0 X X 0 0 1 X X 0 0 1 X X 0 0 1 X X 0 0 1 X X 0 0 1 X X 0 0 1 X X 0 0 1 X X 0 0 1 X X 0 1 0 X X 0 1 0 X X 0 1 0 X X 0 1 0 X X 0 1 0 X X 0 1 0 X X 0 1 0 X X 0 1 0 Determined by PD27 Determined by PD27, Input to INPC17 is always active Single-phase Waveform Output Determined by PD27, SR waveform output mode Phase-delayed Waveform Output Determined by PD26 Determined by PD26, Input to INPC16 is always active Single-phase Waveform Output SR Waveform Output Phase-delayed Waveform Output Determined by PD25 Determined by PD25, Input to INPC15 is always active Single-phase Waveform Output Determined by PD25, SR Waveform Output mode Phase-delayed Waveform Output Determined by PD24 Determined by PD24, Input to INPC14 is always active Single-phase Waveform Output SR Waveform Output Phase-delayed Waveform Output Determined by PD23 Determined by PD23, Input to INPC13 is always active Single-phase Waveform Output Determined by PD23, SR waveform output mode Phase-delayed Waveform Output Determined by PD22 Determined by PD22, Input to INPC12 is always active Single-phase Waveform Output SR Waveform Output Phase-delayed Waveform Output Determined by PD21 Determined by PD21, Input to INPC11 is always active Single-phase Waveform Output Determined by PD21, SR waveform output mode Phase-delayed Waveform Output Determined by PD20 Determined by PD20, Input to INPC10 is always active Single-phase Waveform Output SR Waveform Output Phase-delayed Waveform Output Port Data P27 P27 or INPC17 OUTC17 P27 OUTC17 P26 P26 or INPC16 OUTC16 OUTC16 OUTC16 P25 P25 or INPC15 OUTC15 P25 OUTC15 P24 P24 or INPC14 OUTC14 OUTC14 OUTC14 P23 P23 or INPC13 OUTC13 P23 OUTC13 P22 P22 or INPC12 OUTC12 OUTC12 OUTC12 P21 P21 or INPC11 OUTC11 P21 OUTC11 P20 P20 or INPC10 OUTC10 OUTC10 OUTC10 P26/INPC16/ OUTC16 P25/INPC15/ OUTC15 P24/INPC14/ OUTC14 P23/INPC13/ OUTC13 P22/INPC12/ OUTC12 P21/INPC11/ OUTC11 P20/INPC10/ OUTC10 IFE: IFEj (j=0 to 7) bits in the G1FE register. FSC: FSCj (j=0 to 7) bits in the G1FS register. MOD2 to MOD1: Bits in the G1POCRj (j=0 to 7) register. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 168 of 458 M16C/29 Group 13. Timer S 13.6.1 INPC17 Alternate Input Pin Selection The input capture pin for IC/OC channel 7 can be assigned to one of two package pins. The CH7INSEL ________ bit in the G1BCR0 register selects IC/OC INPC17 from P27/OUTC17/INPC17 or P17/INT5/INPC17/IDU. ________ 13.6.2 Digital Debounce Function for Pin P17/INT5/INPC17 The INT5/INPC17 input from the P17/INT5/INPC17/IDU pin has an effective digital debounce function against a noise rejection. Refer to 19.6 Digital Debounce function for this detail. ________ ________ Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 169 of 458 M16C/29 Group 14.Serial I/O 14. Serial I/O Note The SI/O4 interrupt of peripheral function interrupt is not available in the 64-pin package. Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4. 14.1 UARTi (i=0 to 2) UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 14.1 shows the block diagram of UARTi. Figures 14.2 and 14.3 shows the block diagram of the UARTi transmit/receive. UARTi has the following modes: • Clock synchronous serial I/O mode • Clock asynchronous serial I/O mode (UART mode). • Special mode 1 (I2C bus mode): UART2 • Special mode 2: UART2 • Special mode 3 (Bus collision detection function, IEBus mode): UART2 • Special mode 4 (SIM mode): UART2 Figures 14.4 to 14.9 show the UARTi-related registers. Refer to tables listing each mode for register setting. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 170 of 458 M16C/29 Group 14. Serial I/O 1/2 Main clock, PLL clock, or on-chip oscillator clock f2SIO f1SIO PCLK1=0 f1SIO or f2SIO PCLK1=1 f8SIO 1/8 (UART0) RxD0 Clock source selection f1SIO or f2SIO f8SIO f32SIO CLK1 to CLK0 002 Internal CKDIR=0 012 102 External CKDIR=1 U0BRG register 1/16 UART reception Clock synchronous type 1/16 UART transmission 1/4 f32SIO TxD0 Reception control circuit Receive clock Transmit/ receive unit CKPOL CLK polarity reversing circuit Transmission control Clock synchronous circuit type Clock synchronous type (when internal clock is selected) 1/2 CKDIR=0 Clock synchronous type (when external clock is selected) CKDIR=1 Clock synchronous type (when internal clock is selected) 1 / (n0+1) Transmit clock CLK0 CTS0 / RTS0 CTS/RTS selected CRS=1 CRS=0 CTS/RTS disabled RTS0 VCC RCSP=0 CTS/RTS disabled CRD=1 CRD=0 RCSP=1 CTS0 CTS0 from UART1 (UART1) RxD1 TxD1 1/16 UART reception Clock synchronous type 1/16 UART transmission Clock synchronous type Reception control circuit Receive clock Transmit/ receive unit Clock source selection CLK1 to CLK0 002 f1SIO or f2SIO Internal CKDIR=0 012 f8SIO 102 U1BRG register f32SIO 1 / (n1+1) External CKDIR=1 Transmission control circuit Transmit clock CKPOL CLK1 CTS1 / RTS1/ CTS0/ CLKS1 CLK polarity reversing circuit Clock output pin select CLKMD1=1 CLKMD1=0 CLKMD0=0 CLKMD0=1 Clock synchronous type 1/2 (when internal clock is selected) CKDIR=0 Clock synchronous type (when external clock is selected) CKDIR=1 Clock synchronous type (when internal clock is selected) CTS/RTS selected CRS=1 CRS=0 CTS/RTS disabled RTS1 VCC CTS/RTS disabled RCSP=0 CRD=1 CRD=0 RCSP=1 CTS1 CTS0 from UART0 TxD polarity reversing circuit Transmit/ receive unit (UART2) RxD2 RxD polarity reversing circuit Clock source selection CLK1 to CLK0 002 f1SIO or f2SIO 012 Internal CKDIR=0 f8SIO 102 TxD2 1/16 UART reception Clock synchronous type Reception control circuit Receive clock U2BRG register f32SIO 1 / (n2+1) 1/16 UART transmission Clock synchronous type Transmission control circuit Transmit clock External CKDIR=1 CKPOL CLK2 CLK polarity reversing circuit CTS/RTS selected CRS=1 CRS=0 Clock synchronous type 1/2 (when internal clock is selected) CKDIR=0 Clock synchronous type (when external clock is selected) CKDIR=1 Clock synchronous type (when internal clock is selected) CTS/RTS disabled CTS2 / RTS2 RTS2 VCC CTS/RTS disabled CRD=1 CTS2 i = 0 to 2 ni: Values set to the UiBRG register SMD2 to SMD0, CKDIR: Bists in the UiMR register CLK1 to CLK0, CKPOL, CRD, CRS: Bits in the UiC0 register CLKMD0, CLKMD1, RCSP: Bits in the UCON register CRD=0 Figure 14.1 Block diagram of UARTi (i = 0 to 2) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 171 of 458 M16C/29 Group 14.Serial I/O Clock synchronous type 1SP STPS=0 PAR disabled PRYE=0 SP PAR PAR PRYE=1 enabled Clock synchronous type UART (7 bits) UART (8 bits) UART (7 bits) UARTi receive register RxDi SP 2SP STPS=1 UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16 MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16 UART (8 bits) UART (9 bits) UART (9 bits) 2SP STPS=1 SP SP STPS=0 1SP PAR enabled Clock synchronous type PRYE=1 UART PAR PRYE=0 Clock PAR disabled TxDi UART (7 bits) UART (7 bits) UART (8 bits) Clock synchronous type synchronous type UARTi transmit register 0 SP: Stop bit PAR: Parity bit SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bits in the UiMR Figure 14.2 Block diagram of UARTi (i = 0, 1) transmit/receive unit Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 172 of 458 M16C/29 Group 14. Serial I/O No reverse IOPOL=0 RxD2 RxD data reverse circuit Reverse IOPOL=1 Clock synchronous type 1SP STPS=0 SP 2SP STPS=1 SP PAR disabled PRYE=0 PAR Clock synchronous type UART (7 bits) UART (8 bits) UART(7 bits) UARTi receive register PRYE=1 PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 Logic reverse circuit + MSB/LSB conversion circuit UART2 receive buffer register Address 037E16 Address 037F16 Data bus high-order bits Data bus low-order bits Logic reverse circuit + MSB/LSB conversion circuit D8 D7 UART (8 bits) UART (9 bits) D6 D5 D4 D3 D2 D1 D0 UART2 transmit buffer register Address 037A16 Address 037B16 2SP SP SP STPS=1 STPS=0 PAR enabled PRYE=1 UART PRYE=0 Clock UART (9 bits) Clock synchronous type PAR synchronous type 1SP PAR disabled 0 UART (7 bits) UART (8 bits) Clock synchronous type UART(7 bits) UARTi transmit register U2ERE disable IOPOL No reverse =0 =0 TxD data Error signal reverse circuit output circuit IOPOL U2ERE Reverse Error signal output =1 =1 enable Error signal output TxD2 SP: Stop bit PAR: Parity bit SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bits in the U2MR register U2ERE : Bits in the U2C1 register Figure 14.3 Block diagram of UART2 transmit/receive unit Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 173 of 458 M16C/29 Group 14.Serial I/O UARTi Transmit Buffer Register (i=0 to 2)(1) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A3 16-03A2 16 03AB 16-03AA 16 037B 16-037A 16 Function After Reset Undefined Undefined Undefined RW WO Transmit data Nothing is assigned. If necessary, set to 0. When read, their contents are undefined NOTES: 1. Use MOV instruction to write to this register. UARTi Receive Buffer Register (i=0 to 2) (b15) b7 (b8) b0 b7 b0 Symbol U0RB U1RB U2RB Address 03A7 16-03A6 16 03AF 16-03AE 16 037F 16-037E 16 After Reset undefined undefined undefined Bit Symbol (b7-b0) (b8) Bit Name Function Receive data (D7 to D0) Receive data (D8) RW RO RO Nothing is assigned. If necessary, set to 0. (b10-b9) When read, their contents are undefined ABT OER FER PER SUM Arbitration lost detecting flag (2) Overrun error flag(1) Framing error flag(1) Parity error flag(1) Error sum flag (1) 0 : Not detected 1 : Detected 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found RW RO RO RO RO NOTES: 1. When the SMD2 to SMD0 bits in the UiMR register are set to 0002 (serial I/O disabled) or the RE bit in the UiC1 register is set to 0 (reception disabled), all bits SUM, PER, FER and OER are set to 0 (no error). The SUM bit is set to 0 (no error) when all of the PER, FER and OER bits are set to 0 (no error). Also, bits PER and FER are set to 0 by reading the lower byte of the UiRB register. 2. The ABT bit is set to 0 by setting to 0 by program. (Writing 1 has no effect.) Nothing is assigned at the bit 11 in the U0RB and U1RB registers. If necessary, set to 0. When read, its content is 0. UARTi Baud Rate Generation Register (i=0 to 2)(1, 2, 3) b7 b0 Symbol U0BRG U1BRG U2BRG Function Address 03A116 03A916 037916 After Reset Undefined Undefined Undefined Setting Range 0016 to FF16 RW WO Assuming that set value = n, UiBRG divides the count source by n + 1 NOTES: 1. Write to this register while serial I/O is neither transmitting nor receiving. 2. Use MOV instruction to write to this register. The transfer clock is shown below when the setting value in the UiBRG register is set as n. (1) When the CKDIR bit in the UiMR register to 0 (internal clock) • Clock synchronous serial I/O mode : fj/(2(n+1)) • Clock asynchronous serial I/O (UART) mode : fj/(16(n+1)) (2) When the CKDIR bit in the UiMR register to 1 (external clock) • Clock synchronous serial I/O mode : f EXT • Clock asynchronous serial I/O (UART) mode : f EXT/(16(n+1)) fj : f1SIO, f2SIO, f8SIO, f32SIO fEXT : Input from CLKi pin 3. Set the UiBRG register after setting bits CLK1 and CLK0 in the registers UiC0. Figure 14.4 U0TB to U2TB, U0RB to U2RB, U0BRG to U2BRG Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 174 of 458 M16C/29 Group 14. Serial I/O UARTi Transmit/receive Mode Register (i=0, 1) b7 b6 b5 b4 b3 b2 b1 b0 0 Bit Symbol SMD0 SMD1 SMD2 CKDIR STPS PRY Symbol U0MR, U1MR Bit Name Address 03A016, 03A816 After Reset 0016 Function RW RW RW RW RW RW RW RW RW Serial I/O mode select bit (2) 0 0 0 : Serial I/O disabled 0 0 1 : Clock synchronous serial I/O mode 1 0 0 : UART mode transfer data 7 bit long 1 0 1 : UART mode transfer data 8 bit long 1 1 0 : UART mode transfer data 9 bit long Do not set the value other than the above 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits b2 b1 b0 Internal/external clock select bit Stop bit length select bit (1) Odd/even parity select bit Effective when PRYE = 1 0 : Odd parity 1 : Even parity Parity enable bit Reserve bit 0 : Parity disabled 1 : Parity enabled Set to 0 PRYE (b7) NOTES: 1. Set the corresponding port direction bit for each CLKi pin to 0 (input mode). 2. To receive data, set the corresponding port direction bit for each RxDi pin to 0. UART2 Transmit/receive Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2MR Bit Symbol SMD0 SMD1 SMD2 CKDIR STPS PRY (2) Address 037816 Bit Name After Reset 0016 Function 0 0 0 : Serial I/O disabled 0 0 1 : Clock synchronous serial I/O mode 0 1 0 : I2C bus mode(3) 1 0 0 : UART mode transfer data 7 bit long 1 0 1 : UART mode transfer data 8 bit long 1 1 0 : UART mode transfer data 9 bits long Do not set the value other than the above 0 : Internal clock 1 : External clock 0 : One stop bit 1 : Two stop bits 0 : Odd parity 1 : Even parity (1) b2 b1 b0 RW RW RW RW RW RW RW RW RW Serial I/O mode select bit Internal/external clock select bit Stop bit length select bit Odd/even parity select bit Effective when PRYE = 1 Parity enable bit TxD, RxD I/O polarity reverse bit 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse PRYE IOPOL NOTES: 1. Set the corresponding port direction bit for each CLK2 pin to 0 (input mode). 2. To receive data, set the corresponding port direction bit for each RxD2 pin to 0 (input mode). 3. Set the corresponding port direction bit for SCL2 and SDA2 pins to 0 (input mode). Figure 14.5 U0MR to U2MR Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 175 of 458 M16C/29 Group 14.Serial I/O UARTi Transmit/receive Control Rregister 0 (i=0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0C0 to U2C0 Bit Symbol CLK0 CLK1 CRS Address 03A416, 03AC16, 037C16 After Reset 00001000 2 Bit Name BRG count source select bit(7) b1 b0 Function 0 0 : f1SIO or f2SIO is selected 0 1 : f8SIO is selected 1 0 : f32SIO is selected 1 1 : Do not set Effective when CRD is set to 0 0 : CTS function is selected (1) 1 : RTS function is selected 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60, P6 4 and P7 3 can be used as I/O ports)(6) RW RW RW RW CTS/RTS function select bit (3) Transmit register empty flag CTS/RTS disable bit TXEPT RO CRD RW NCH CKPOL Data output select bit(5) CLK polarity select bit 0 : TxD2/SDA2 and SCLi pins are CMOS output RW 1 : TxD2/SDA2 and SCLi pins are N-channel open-drain output(4) 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge RW RW UFORM Transfer format select bit 0 : LSB first (2) 1 : MSB first NOTES: 1. Set the corresponding port direction bit for each CTSi pin to 0 (input mode). 2. Effective when bits SMD2 to SMD0 in the UMR register to 0012 (clock synchronous serial I/O mode) or 0102 (UART mode transfer data 8 bits long). Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 1012 (I2C bus mode) and 0 when they are set to 1002. 3. CTS1/RTS1 can be used when the CLKMD1 bit in the UCON register is set to 0 (only CLK1 output) and the RCSP bit in the UCON register is set to 0 (CTS0/RTS0 not separated). 4. SDA2 and SCL2 are effective when i = 2. 5. When bits SMD2 to SMD in the UiMR regiser are set to 0002 (serial I/O disable), do not set NCH bit to 1 (TxDi/SDA2 and SCL2 pins are N-channel open-drain output). 6. When the U1MAP bit in PACR register is 1 (P73 to P70), P70 functions as CTS/RTS pin in UART1. 7. When the CLK1 and CLK0 bit settings are changed, set the UiBRG register. UART Transmit/receive Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UCON Bit Symbol U0IRS U1IRS Address 03B016 After Reset X00000002 Bit Name Function RW RW RW RW RW RW UART0 transmit interrupt 0 : Transmit buffer empty (Tl = 1) cause select bit 1 : Transmission completed (TXEPT = 1) UART1 transmit interrupt cause select 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Effective when the CLKMD1 bit is set to 1 0 : Clock output from CLK1 1 : Clock output from CLKS1 U0RRM UART0 continuous receive mode enable bit U1RRM UART1 continuous receive mode enable bit CLKMD0 UART1 CLK/CLKS select bit 0 CLKMD1 UART1 CLK/CLKS select bit 1 (1) RCSP (b7) Separate UART0 CTS/RTS bit 0 : Output from CLK1 only 1 : Transfer clock output from multiple pins function selected RW (2) 0 : CTS/RTS shared pin 1 : CTS/RTS separated (P64 pin functions as CTS0 pin ) RW Nothing is assigned. If necessary, set to 0. When read, the content is undefined NOTES: 1. When using multiple transfer clock output pins, make sure the following conditions are met:set the CKDIR bit in the U1MR register to 0 (internal clock) 2. When the U1MAP bit in PACR register is set to 1 (P73 to P70), P70 pin functions as CTS0 pin. Figure 14.6 U0C0 to U2C0 and UCON Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 176 of 458 M16C/29 Group 14. Serial I/O UARTi Transmit/receive Control Register 1 (i=0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0C1, U1C1 Address 03A516,03AD 16 After Reset 00000010 2 Bit Symbol TE TI RE RI Bit Name Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag Function 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in UiTB register 1 : No data present in UiTB register 0 : Reception disabled 1 : Reception enabled 0 : No data present in UiRB register 1 : Data present in UiRB register RW RW RO RW RO (b7-b4) Nothing is assigned. If necessary, set to 0. When read, the content is 0 UART2 Transmit/receive Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C1 Address 037D 16 After Reset 00000010 2 Bit Symbol TE TI RE RI U2IRS Bit Name Transmit enable bit Transmit buffer empty flag Receive enable bit Receive complete flag UART2 transmit interrupt cause select bit Function 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in U2TB register 1 : No data present in U2TB register 0 : Reception disabled 1 : Reception enabled 0 : No data present in U2RB register 1 : Data present in U2RB register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled RW RW RO RW RO RW RW RW RW U2RRM UART2 continuous receive mode enable bit U2LCH Data logic select bit U2ERE Error signal output enable bit Pin Assignment Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbpl PACR Address 025D 16 After Reset 0016 Bit Symbol PACR0 PACR1 PACR2 (b6-b3) Bit Name Pin enabling bit Function 010 : 64 pin 011 : 80 pin All other values are reserved. Do not use. Nothing is assigned. RW RW RW RW Reserved bits If necessary, set to 0. When read, the content is 0 RW U1MAP UART1 pin remapping bit UART1 pins assigned to 0 : P6 7 to P6 4 1 : P7 3 to P7 0 NOTE: 1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to 1(write enable). Figure 14.7 U0C1 to U2C1 Register, and PACR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 177 of 458 M16C/29 Group 14.Serial I/O UART2 Special Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol U2SMR Bit Symbol IICM ABC BBS Bit Name Address 0377 16 After Reset X0000000 2 Function RW RW RW RW (1) I2C bus mode select bit Arbitration lost detecting flag control bit Bus busy flag Reserved bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit 0 : Other than I2C bus mode 1 : I2C bus mode 0 : Update per bit 1 : Update per byte 0 : STOP condition detected 1 : START condition detected (busy) Set to 0 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Not synchronized to RxD2 1 : Synchronized to RxD2(2) (b3) ABSCS ACSE RW RW RW SSS RW (b7) Nothing is assigned. If necessary, set to 0. When read, the content is undefined NOTES: 1: The BBS bit is set to 0 by writing 0 by program. (Writing 1 has no effect). 2: When a transfer begins, the SSS bit is set to 0 (Not synchronized to RxD2). UART2 Special Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR2 Bit Symbol IICM2 CSC SWC ALS STAC SWC2 SDHI Address 0376 16 After Reset X0000000 2 Bit Name I2 C bus mode select bit 2 Clock-synchronous bit SCL2 wait output bit SDA2 output stop bit UART initialization bit SCL2 wait output bit 2 SDA2 output disable bit Refer to Table 14.13 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: Transfer clock 1: “L” output Function RW RW RW RW RW RW RW RW 0: Enabled 1: Disabled (high impedance) (b7) Nothing is assigned. If necessary, set to 0. When read, the content is undefined Figure 14.8 U2SMR and U2SMR2 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 178 of 458 M16C/29 Group 14. Serial I/O UART2 Special Mode Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Bit Symbol (b0) CKPH Address 0375 16 After Reset 000X0X0X 2 Bit Name Nothing is assigned. If necessary, set to 0. When read, the content is undefined Clock phase set bit Function RW 0 : Without clock delay 1 : With clock delay RW (b2) NODC Nothing is assigned. If necessary, set to 0. When read, the content is undefined Clock output select bit 0 : CLK2 is CMOS output 1 : CLK2 is N-channel open drain output RW (b4) DL0 Nothing is assigned. If necessary, set to 0. When read, the content is undefined SDA2 digital delay setup bit (1, 2) b7 b6 b5 DL1 DL2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Without delay 1 : 1 to 2 cycle(s) of U2BRG count source 0 : 2 to 3 cycles of U2BRG count source 1 : 3 to 4 cycles of U2BRG count source 0 : 4 to 5 cycles of U2BRG count source 1 : 5 to 6 cycles of U2BRG count source 0 : 6 to 7 cycles of U2BRG count source 1 : 7 to 8 cycles of U2BRG count source RW RW RW NOTES: 1. Bits DL2 to DL0 are used to generate a delay in SDA output by digital means during I2C bus mode. In other than I2C bus mode,set these bits to 0002 (no delay). 2. The amount of delay varies with the load on pins SCL2 and SDA2. Also, when using an external clock, the amount of delay increases by about 100 ns. UART2 Special Mode Register 4 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR4 Bit Symbol STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI SWC9 Address 0374 16 After Reset 0016 Bit Name Start condition generate bit (1) Restart condition generate bit (1) Stop condition generate bit (1) SCL2,SDA 2 output select bit ACK data bit ACK data output enable bit SCL2 output stop enable bit SCL2 wait bit 3 0 : Clear 1 : Start 0 : Clear 1 : Start 0 : Clear 1 : Start Function RW RW RW RW RW RW RW RW RW 0 : Start and stop conditions not output 1 : Start and stop conditions output 0 : ACK 1 : NACK 0 : Serial I/O data output 1 : ACK data output 0 : Disabled 1 : Enabled 0 : SCL 2 “L” hold disabled 1 : SCL 2 “L” hold enabled NOTE: 1. Set to 0 when each condition is generated. Figure 14.9 U2SMR3 and U2SMR4 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 179 of 458 M16C/29 Group 14.Serial I/O 14.1.1 Clock Synchronous serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 14.1 lists the specifications of the clock synchronous serial I/O mode. Table 14.2 lists the registers used in clock synchronous serial I/O mode and the register values set. Table 14.1 Clock Synchronous Serial I/O Mode Specifications Item Transfer data format Transfer clock Specification • Transfer data length: 8 bits • The CKDIR bit in the UiMR(i=0 to 2) register is set to 0 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16 • CKDIR bit is set to 1 (external clock ) : Input from CLKi pin _______ _______ _______ _______ • Selectable from CTS function, RTS function or CTS/RTS function disable • Before transmission can start, the following requirements must be met (1) _ The TE bit in the UiC1 register is set to 1 (transmission enabled) _ The TI bit in the UiC1 register is set to 0 (data present in UiTB register) If CTS function is selected, input on the CTSi pin is set to “L” • Before reception can start, the following requirements must be met (1) _ The RE bit in the UiC1 register is set to 1 (reception enabled) _ The TE bit in the UiC1 register is set to 1 (transmission enabled) _ The TI bit in the UiC1 register is set to 0 (data present in the UiTB register) • For transmission, one of the following conditions can be selected _ The UiIRS bit (3) is set to 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission) _ The UiIRS bit is set to 1 (transfer completed): when the serial I/O finished sending data from the UARTi transmit register • For reception When transferring data from the UARTi receive register to the UiRB register (at completion of reception) • Overrun error (2) This error occurs if the serial I/O started receiving the next data before reading the UiRB register and received the 7th bit in the the next data • CLK polarity selection Transfer data input/output can be chosen to occur synchronously with the rising or the falling edge of the transfer clock • LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected • Continuous receive mode selection Reception is enabled immediately by reading the UiRB register • Switching serial data logic (UART2) This function reverses the logic value of the transmit/receive data • Transfer clock output from multiple pins selection (UART1) The output pin can be selected in a program from two UART1 transfer clock pins that have been set _______ _______ • Separate CTS/RTS pins (UART0) _________ _________ CTS0 and RTS0 are input/output from separate pins • UART1 pin remapping selection The UART1 pin can be selected from the P67 to P64 or P73 to P70 _ _______ _______ Transmission, reception control Transmission start condition Reception start condition Interrupt request generation timing Error detection Select function NOTES: 1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0 register is set to 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. If an overrun error occurs, bits 8 to 0 in the UiRB register are undefined. The IR bit in the SiRIC register remains unchanged. 3. The U0IRS and U1IRS bits respectively are the bits 0 and 1 in the UCON register; the U2IRS bit is bit 4 in the U2C1 register. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 180 of 458 M16C/29 Group 14. Serial I/O Table 14.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register UiTB(3) UiRB(3) UiBRG UiMR(3) Bit 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL(i=2) (4) UiC0 CLK1 to CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI U2IRS (1) Function Set transmission data Reception data can be read Overrun error flag Set bit rate Set to 0012 Select the internal clock or external clock Set to 0 Select the count source for the UiBRG register Select CTS or RTS to use Transmit register empty flag _______ _______ _______ Enable or disable the CTS or RTS function Select TxDi pin output mode Select the transfer clock polarity Select the LSB first or MSB first Set this bit to 1 to enable transmission/reception Transmit buffer empty flag Set this bit to 1 to enable reception Reception complete flag Select the source of UART2 transmit interrupt Set this bit to 1 to use UART2 continuous receive mode Set this bit to 1 to use UART2 inverted data logic Set to 0 Set to 0 Set to 0 Set to 0 Select clock output mode Set to 0 Set to 0 Select the source of UART0/UART1 transmit interrupt Set this bit to 1 to use continuous receive mode Select the transfer clock output pin when CLKMD1 is set to 1 Set this bit to 1 to output UART1 transfer clock from two pins Set this bit to 1 to accept as input the UART0 CTS0 signal from the P64 pin Set to 0 _________ _______ U2RRM (1) U2LCH U2SMR U2SMR2 U2SMR3 0 to 7 0 to 7 0 to 2 NODC 4 to 7 U2SMR4 UCON 0 to 7 U0IRS, U1IRS U0RRM, U1RRM CLKMD0 CLKMD1 RCSP 7 (3) U2ERE (3) NOTES: 1. Set bits 5 and 4 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the UCON register. 2. Not all register bits are described above. Set those bits to 0 when writing to the registers in clock synchronous serial I/O mode. 3. Set bits 7 and 6 in registers U0C1 and U1C1 to 0. 4. Set the bit 7 in registers U0MR and U1MR to 0. i=0 to 2 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 181 of 458 M16C/29 Group 14.Serial I/O Table 14.3 lists pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 14.4 lists the P64 pin functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.) Table 14.3 Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)(1) Pin Name Function Method of Selection (Outputs dummy data when performing reception only) Set the PD6_2 bit and PD6_6 bit in the PD6 register, and PD7_1 bit in the PD7 register to 0 (Can be used as an input port when performing transmission only) Set the CKDIR bit in the UiMR register to 0 Set the CKDIR bit in the UiMR register to 1 Set the PD6_1 bit and PD6_5 bit in the PD6 register, and the PD7_2 bit in the PD7 register to 0 Set the CRD bit in the UiC0 register to 0 Set the CRS bit in the UiC0 register to 0 Set the PD6_0 bit and PD6_4 bit in the PD6 register is set to 0, the PD7_3 bit in the PD7 register to 0 Set the CRD bit in the UiC0 register to 0 Set the CRS bit in the UiC0 register to 1 Set the CRD bit in the UiC0 register to 1 TxDi (i = 0 to 2) Serial data output (P63, P6 7, P70) Serial data input RxDi (P6 2, P6 6, P71) CLKi Transfer clock output (P61, P6 5, P72) Transfer clock input CTSi/RTSi CTS input (P60, P6 4, P73) RTS output I/O port NOTE: 1: When the U1MAP bit in PACR register is 1 (P73 to P70), UART1 pin is assgined to P73 to P70. Table 14.4 P64 Pin Functions(1) Bit Set Value Pin Function P64 CTS1 RTS1 CTS0(2) CLKS1 U1C0 register CRS CRD 1 0 0 0 1 0 0 RCSP 0 0 0 1 UCON register CLKMD1 CLKMD0 0 0 0 0 1(3) PD6 register PD6_4 Input: 0, Output: 1 0 0 1 NOTES: 1. When the U1MAP bit in PACR register is 1 (P73 to P70), this table lists the P70 functions. 2. In addition to this, set the CRD bit in the U0C0 register to 0 (CT00/RT00 enabled) and the CRS bit in the U0C0 register to 1 (RTS0 selected). 3. When the CLKMD1 bit is set to 1 and the CLKMD0 bit is set to 0, the following logic levels are output: • High if the CLKPOL bit in the U1C0 register is set to 0 • Low if the CLKPOL bit in the U1C0 register is set to 1 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 182 of 458 M16C/29 Group 14. Serial I/O (1) Example of Transmit Timing (Internal clock is selected) Tc Transfer clock UiC1 register TE bit UiC1 register TI bit CTSi CLKi 1 0 1 0 “H” “L” Transferred from UiTB register to UARTi transmit register Write data to the UiTB register TCLK Stopped pulsing because CTSi = “H” Stopped pulsing because the TE bit = 0 TxDi UiC0 register TXEPT bit SiTIC register IR bit 1 0 1 0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D 1 D2 D3 D4 D5 D6 D7 D0 D1 D 2 D 3 D4 D5 D6 D7 Cleared to “0” when interrupt request is accepted, or cleared to 0 by program Tc = TCLK = 2(n + 1) / fj fj: frequency of UiBRG count source (f 1SIO, f2SIO, f8SIO, f32SIO) n: value set to UiBRG register i: 0 to 2 The above timing diagram applies to the case where the register bits are set as follows: • The CKDIR bit in the UiMR register is set to 0 (internal clock) • The CRD bit in the UiC0 register is set to 0 (CTS/RTS enabled); CRS bit is set to 0 (CTS selected) • The CKPOL bit in the UiC0 register is set to 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) • The UiIRS bit is set to 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the bit 0 in the UCON register U1IRS bit is the bit 1 in the UCON register, and U2IRS bit is the bit 4 in the U2C1 register. (2) Example of Receive Timing (External clock is selected) 1 0 1 0 1 0 “H” “L” UiC1 register RE bit UiC1 register TE bit UiC1 register TI bit RTSi CLKi Write dummy data to UiTB register Transferred from UiTB register to UARTi transmit register 1 / fEXT Even if the reception is completed, the RTS does not change. The RTS becomes “L” when the RI bit changes to 0 from 1. Receive data is taken in RxDi UiC1 register RI bit SiRIC register IR bit 1 0 1 0 D0 D 1 D2 D3 D4 D 5 D6 D7 Transferred from UARTi receive register to UiRB register D0 D1 D2 D3 D 4 D5 Read out from UiRB register Cleared to 0 when interrupt request is accepted, or cleared to 0 by program The above timing diagram applies to the case where the register bits are set Make sure the following conditions are met when input as follows: to the CLKi pin before receiving data is high: • The CKDIR bit in the UiMR register is set to 1 (external clock) • UiC0 register TE bit is set to 1 (transmit enabled) • The CRD bit in the UiC0 register is set to 0 (CTS/RTS enabled); • UiC0 register RE bit is set to 1 (Receive enabled) The CRS bit is set to 1 (RTS selected) • Write dummy data to the UiTB register • UiC0 register CKPOL bit is set to 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock) fEXT: frequency of external clock Figure 14.10 Typical transmit/receive timings in clock synchronous serial I/O mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 183 of 458 M16C/29 Group 14.Serial I/O 14.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below. •Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to 0 (reception disabled) (2) Set bits SMD2 to SMD0 in the UiMR register to 0002 (Serial I/O disabled) (3) Set bits SMD2 to SMD0 in the UiMR register to 0012 (Clock synchronous serial I/O mode) (4) Set the RE bit in the UiC1 register to 1 (reception enabled) •Resetting the UiTB register (i=0 to 2) (1) Set bits SMD2 to SMD0 in the UiMR register to 0002 (Serial I/O disabled) (2) Set bits SMD2 to SMD0 in the UiMR register to 0012 (Clock synchronous serial I/O mode) (3) 1 is written to TE bit in the UiC1 register (reception enabled), regardless to the TE bit. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 184 of 458 M16C/29 Group 14. Serial I/O 14.1.1.2 CLK Polarity Select Function Use the CKPOL bit in the UiC0 register (i=0 to 2) to select the transfer clock polarity. Figure 14.11 shows the polarity of the transfer clock. (1) When the CKPOL bit in the UiC0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) CLKi TXD i RX Di D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 (2) (2) When the CKPOL bit in the UiC0 register is set to 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock) CLKi TXD i RX Di D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 (3) i = 0 to 2 NOTES: 1. This applies to the case where the UFORM bit in the UiC0 register is set to 0 (LSB first) and the UiLCH bit in the UiC1 register is set to 0 (no reverse). 2. When not transferring, the CLKi pin outputs a high signal. Figure 14.11 Polarity of transfer clock 14.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i=0 to 2) to select the transfer format. Figure 14.12 shows the transfer format. (1) When the UFORM bit in the UiC0 register 0 (LSB first) CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 (2) When the UFORM bit in the UiC0 register is set to 1 (MSB first) CLKi TXDi RXDi i = 0 to 2 NOTE: 1. This applies to the case where the CKPOL bit in the UiC0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UiLCH bit in the UiC1 register 0 (no reverse). D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Figure 14.12 Transfer format Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 185 of 458 M16C/29 Group 14.Serial I/O 14.1.1.4 Continuous receive mode When the UiRRM bit (i=0 to 2) is set to 1 (continuous receive mode), the TI bit in the UiC1 register is set to 0 (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit is set to 1, do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the bit 2 and bit 3 in the UCON register, respectively, and the U2RRM bit is the bit 5 in the U2C1 register. 14.1.1.5 Serial data logic switch function (UART2) When the U2LCH bit in the U2C1 register is set to 1 (reverse), the data written to the U2TB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the U2RB register. Figure 14.13 shows serial data logic. (1) When the U2LCH bit in the U2C1 register is set to 0 (no reverse) Transfer clock TxD2 “H” “L” “H” “L” (no reverse) D0 D1 D2 D3 D4 D5 D6 D7 (2) When the U2LCH bit in the U2C1 register is set to 1 (reverse) Transfer clock TxD2 “H” “L” “H” “L” (reverse) D0 D1 D2 D3 D4 D5 D6 D7 NOTE: 1. This applies to the case where the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) and the UFORM bit is set to 0 (LSB first). Figure 14.13 Serial data logic switch timing 14.1.1.6 Transfer clock output from multiple pins function (UART1) The CLKMD1 to CLKMD0 bits in the UCON register can choose one from two transfer clock output pins. (See Figure 14.14) This function is valid when the internal clock is selected for UART1. MCU TXD1 (P6 7) CLKS 1 (P6 4) CLK1 (P6 5) IN CLK IN CLK Transfer enabled when the CLKMD0 bit in the UCON register is set to 0 Transfer enabled when the CLKMD0 bit in the UCON register is set to 1 NOTES: 1. This applies to the case where the CKDIR bit in the U1MRregister is set to 0 (internal clock) and the CLKMD1 bit in the UCON register is set to 1 (transfer clock output from multiple pins). 2. This applies to the case where U1MAP bit in PACR register is set to 0 (P67 to P64). Figure 14.14 Transfer Clock Output From Multiple Pins Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 186 of 458 M16C/29 Group _______ _______ 14. Serial I/O 14.1.1.7 CTS/RTS separate function (UART0) _______ _______ _______ _______ This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64 pin or P70 pin. To use this function, set the register bits as shown below. _______ _______ • The CRD bit in the U0C0 register is set to 0 (enables UART0 CTS/RTS) _______ • The CRS bit in the U0C0 register is set to 1 (outputs UART0 RTS) _______ _______ • The CRD bit in the U1C0 register is set to 0 (enables UART1 CTS/RTS) _______ • The CRS bit in the U1C0 register is set to 0 (inputs UART1 CTS) _______ • The RCSP bit in the UCON register is set to 1 (inputs CTS0 from the P64 pin or P70 pin) • The CLKMD1 bit in the UCON register is set to 0 (CLKS1 not used) _______ _______ _______ _______ Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be used. MCU TXD0 (P6 3) RXD0 (P6 2) CLK0 (P6 1) RTS0 (P60) CTS0 (P6 4) IN OUT CLK CTS RTS IC NOTE: 1. This applies to the case where the U1MAP bit in the PACR register is set to 0 (P67 to P64). Figure 14.15 CTS/RTS separate function usage Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 187 of 458 M16C/29 Group 14.Serial I/O 14.1.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data format. Table 14.5 lists the specifications of the UART mode. Table 14.5 UART Mode Specifications Item Transfer data format Specification • Character bit (transfer data): Selectable from 7, 8 or 9 bits • Start bit: 1 bit • Parity bit: Selectable from odd, even, or none • Stop bit: Selectable from 1 or 2 bits • The CKDIR bit in the UiMR(i=0 to 2) register is set to 0 (internal clock) : fj/ (16(n+1)) 0016 to FF16 fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register • CKDIR bit is set to 1 (external clock ) : fEXT/16(n+1) fEXT: Input from CLKi pin. n :Setting value of UiBRG register 0016 to FF16 _______ _______ _______ _______ • Selectable from CTS function, RTS function or CTS/RTS function disable • Before transmission can start, the following requirements must be met _ The TE bit in the UiC1 register is set to 1 (transmission enabled) _ The TI bit in the UiC1 register is set to 0 (data present in UiTB register) _______ _______ _ If CTS function is selected, input on the CTSi pin is set to “L” • Before reception can start, the following requirements must be met" _ The RE bit in the UiC1 register is set to 1 (reception enabled) _ Start bit detection • For transmission, one of the following conditions can be selected _ The UiIRS bit (2) is set to 0 (transmit buffer empty): when transferring data from the UiTB register to the UARTi transmit register (at start of transmission) _ The UiIRS bit is set to1 (transfer completed): when the serial I/O finished sending data from the UARTi transmit register • For reception When transferring data from the UARTi receive register to the UiRB register (at completion of reception) • Overrun error (1) This error occurs if the serial I/O started receiving the next data before reading the UiRB register and received the bit one before the last stop bit in the the next data • Framing error This error occurs when the number of stop bits set is not detected • Parity error This error occurs when if parity is enabled, the number of 1 in parity and character bits does not match the number of 1 set • Error sum flag This flag is set to 1 when any of the overrun, framing, and parity errors is encountered • LSB first, MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected • Serial data logic switch (UART2) This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed. • TXD, RXD I/O polarity switch (UART2) This function reverses the polarities of hte TXD pin output and RXD pin input. The logic levels of all I/O data is reversed. _______ _______ • Separate CTS/RTS pins (UART0) _________ _________ CTS0 and RTS0 are input/output from separate pins • UART1 pin remapping selection The UART1 pin can be selected from the P67 to P64 or P73 to P70 Transfer clock Transmission, reception control Transmission start condition Reception start condition Interrupt request generation timing Error detection Select function NOTES: 1. If an overrun error occurs, bits 8 to 0 in the UiRB register are undefined. The IR bit in the SiRIC register remains unchange. 2. Bits U0IRS and U1IRS respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 188 of 458 M16C/29 Group 14. Serial I/O Table 14.6 Registers to Be Used and Settings in UART Mode Register UiTB UiRB UiBRG UiMR Bit 0 to 8 0 to 8 0 to 7 SMD2 to SMD0 Function Set transmission data (1) Reception data can be read (1) Set bit rate Set these bits to 1002 when transfer data is 7 bits long Set these bits to 1012 when transfer data is 8 bits long Set these bits to 1102 when transfer data is 9 bits long CKDIR STPS PRY, PRYE IOPOL(i=2) (4) UiC0 CLK0, CLK1 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI U2IRS (2) U2RRM (2) UiLCH (3) UiERE UiSMR UiSMR2 UiSMR3 UiSMR4 UCON 0 to 7 0 to 7 0 to 7 0 to 7 U0IRS, U1IRS U0RRM, U1RRM CLKMD0 CLKMD1 RCSP 7 (3) OER,FER,PER,SUM Error flag Select the internal clock or external clock Select the stop bit Select whether parity is included and whether odd or even Select the TxD/RxD input/output polarity Select the count source for the UiBRG register Select CTS or RTS to use Transmit register empty flag _______ _______ _______ Enable or disable the CTS or RTS function Select TxDi pin output mode Set to 0 LSB first or MSB first can be selected when transfer data is 8 bits long. Set this bit to 0 when transfer data is 7 or 9 bits long. Set this bit to 1 to enable transmission Transmit buffer empty flag Set this bit to 1 to enable reception Reception complete flag Select the source of UART2 transmit interrupt Set to 0 Set this bit to 1 to use UART2 inverted data logic Set to 0 Set to 0 Set to 0 Set to 0 Set to 0 Select the source of UART0/UART1 transmit interrupt Set to 0 Invalid because CLKMD1 is set to 0 Set to 0 Set to 0 Set this bit to 1 to accept as input the UART0 CTS0 signal from the P64 pin _________ _______ NOTES: 1. The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bits 7 to 0 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long. 2. Set bits 5 and 4 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM and U1RRM are included in the UCON register. 3. Set bits 7 and 6 in registers U0C1 and U1C1 to 0. 4. Set the bit 7 in registers U0MR and U1MR to 0. i=0 to 2 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 189 of 458 M16C/29 Group 14.Serial I/O Table 14.7 lists the functions of the input/output pins in UART mode. Table 14.8 lists the P64 pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.) Table 14.7 I/O Pin Functions in UART mode(1) Pin Name Function Method of Selection (Outputs "H" when performing reception only) PD6_2 bit, PD6_6 bit in the PD6 register and the PD7_1 bit in the PD7 register (Can be used as an input port when performing transmission only) Set the CKDIR bit in the UiMR register to 0 Set the CKDIR bit in the UiMR register to 1 Set the PD6_1 bit and PD6_5 bit in the PD6 register to 0, PD7_2 bit in the PD7 register to 0 Set the CRD bit in the UiC0 register to 0 Set the CRS bit in the UiC0 register to 0 Set the PD6_0 bit and PD6_4 bit in the PD6 register to 0, the PD7_3 bit in the PD7 register 0 Set the CRD bit in the UiC0 register to 0 Set the CRS bit in the UiC0 register to 1 Set the CRD bit in the UiC0 register 1 TxDi (i = 0 to 2) Serial data output (P63, P67, P70) Serial data input RxDi (P62, P66, P71) Input/output port CLKi (P61, P65, P72) Transfer clock input CTS input CTSi/RTSi (P60, P64, P73) RTS output Input/output port NOTE: 1. When the U1MAP bit in PACR register is set to 1 (P73 to P70), UART1 pin is assgined to P73 to P70. Table 14.8 P64 Pin Functions in UART mode (1) Bit Set Value Pin Function P64 CTS1 RTS1 CTS0 (2) U1C0 register CRS CRD 1 0 0 0 0 1 0 UCON register CLKMD1 RCSP 0 0 0 1 0 0 0 0 PD6 register PD6_4 Input: 0, Output: 1 0 0 NOTES: 1. When the U1MAP bit in PACR register is 1 (P73 to P70), this table lists the P70 functions. 2. In addition to this, set the CRD bit in the U0C0 register to 0 (CTS0/RTS0 enabled) and the CRS bit in the U0C0 register to 1 (RTS0 selected). Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 190 of 458 M16C/29 Group 14. Serial I/O • Example of transmit timing when transfer data is 8-bit long (parity enabled, one stop bit) Tc Transfer clock UiC1 register TE bit UiC1 register TI bit 1 0 1 0 “H” “L” The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to “L”. Write data to the UiTB register Transferred from UiTB register to UARTi transmit register CTSi Start bit TxDi UiC0 register TXEPT bit SiTIC register IR bit 1 0 1 0 Parity Stop bit bit P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Stopped pulsing because the TE bit = “0” ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 Cleared to 0 when interrupt request is accepted, or cleared to 0 by program Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT The above timing diagram applies to the case where the register bits are set as follows: fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) • Set the PRYE bit in the UiMR register to 1 (parity enabled) fEXT: frequency of UiBRG count source (external clock) • Set the STPS bit in the UiMR register to 0 (1 stop bit) n: value set to UiBRG • Set the CRD bit in the UiC0 register to 0 (CTS/RTS enabled), i = 0 to 2 the CRS bit to 0 (CTS selected). • Set the UiIRS bit to 1 (an interrupt request occurs when transmit completed): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4 • Example of transmit timing when transfer data is 9-bit long (parity disabled, two stop bits) Tc Transfer clock UiC1 register TE bit UiC1 register TI bit 1 0 1 0 Write data to the UiTB register Start bit TxDi UiC0 register TXEPT bit SiTIC register IR bit 1 0 1 0 Stop Stop bit bit Transferred from UiTB register to UARTi transmit register ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 Cleared to 0 when interrupt request is accepted, or cleared to 0 by program The above timing diagram applies to the case where the register bits are set as follows: • Set the PRYE bit in the UiMR register to 0 (parity disabled) • Set the STPS bit in the UiMR register to 1 (2 stop bits) • Set the CRD bit in the UiC0 register to 1 (CTS/RTS disabled) • Set the UiIRS bit to 0 (an interrupt request occurs when transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON register bit 1, and U2IRS bit is the U2C1 register bit 4 Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO) fEXT: frequency of UiBRG count source (external clock) n: value set to UiBRG i = 0 to 2 Figure 14.16 Typical transmit timing in UART mode (UART0, UART1) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 191 of 458 M16C/29 Group 14.Serial I/O • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG count source UiC1 register RE bit RxDi 1 0 Start bit D0 Sampled “L” D1 D7 Stop bit Receive data taken in Transferred from UARTi receive register to UiRB register Read out from UiRB register Transfer clock UiC1 register RI bit RTSi SiRIC register IR bit 1 0 “H” “L” 1 0 Cleared to 0 when interrupt request is accepted, or cleared to 0 by program The above timing diagram applies to the case where the register bits are set as follows: • Set the PRYE bit in the UiMR register to 0 (parity disabled) • Set the STPS bit in the UiMR register to 0 (1 stop bit) • Set the CRD bit in the UiC0 register to 0 (CTSi/RTSi enabled), the CRS bit to 1 (RTSi selected) i = 0 to 2 Reception triggered when transfer clock is generated by falling edge of start bit Figure 14.17 Receive Operation 14.1.2.1 Bit Rates In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates. Table 14.9 lists example of bit rate and settings. Table 14.9 Example of Bit Rates and Settings Bit Rate (bps) 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200 Count Source of BRG f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 Peripheral Function Clock : 16MHz Peripheral Function Clock : 20MHz Set Value of BRG : n Actual Time (bps) Set Value of BRG : n Actual Time (bps) 103(67h) 1202 129(81h) 1202 51(33h) 2404 64(40h) 2404 25(19h) 4808 32(20h) 4735 103(67h) 9615 129(81h) 9615 68(44h) 14493 86(56h) 14368 51(33h) 19231 64(40h) 19231 34(22h) 28571 42(2Ah) 29070 31(1Fh) 31250 39(27h) 31250 25(19h) 38462 32(20h) 37879 19(13h) 50000 24(18h) 50000 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 192 of 458 M16C/29 Group 14. Serial I/O 14.1.2.2 Counter Measure for Communication Error If a communication error occurs while transmitting or receiving in UART mode, follow the procedure below. • Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to 0 (reception disabled) (2) Set the RE bit in the UiC1 register to 1 (reception enabled) • Resetting the UiTB register (i=0 to 2) (1) Set bits SMD2 to SMD0 in UiMR register 0002 (Serial I/O disabled) (2) Set bits SMD2 to SMD0 in UiMR register 0012, 1012, 1102 (3) 1 is written to TE bit in the UiC1 register (reception enabled), regardless of the TE bit 14.1.2.3 LSB First/MSB First Select Function As shown in Figure 14.18, use the UFORM bit in the UiC0 register to select the transfer format. This function is valid when transfer data is 8 bits long. (1) When the UFORM bit in the UiC0 register is set to 0 (LSB first) CLKi TXDi RXDi ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP (2) When the UFORM bit in the UiC0 register is set to 1 (MSB first) CLKi TXDi RXDi ST : Start bit P : Parity bit SP : Stop bit i = 0 to 2 NOTE: 1. This applies to the case where the CKPOL bit in the UiC0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the UiLCH bit in the UiC1 register is set to 0 (no reverse), the STPS bit in the UiMR register is set to 0 (1 stop bit) and the PRYE bit in the UiMR register is set to 1 (parity enabled). ST ST D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 P P SP SP Figure 14.18 Transfer Format Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 193 of 458 M16C/29 Group 14.Serial I/O 14.1.2.4 Serial Data Logic Switching Function (UART2) The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the U2RB register. Figure 14.19 shows serial data logic. (1) When the U2LCH bit in the U2C1 register is set to 0 (no reverse) Transfer clock TxD2 “H” “L” “H” “L” (no reverse) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP (2) When the U2LCH bit in the U2C1 register is set 1 (reverse) Transfer clock (reverse) “H” “L” “H” “L” TxD2 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP NOTE: 1. This applies to the case where the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge of the transfer clock), the UFORM bit in the U2C0 register is set to 0 (LSB first), the STPS bit in the U2MR register is set to 0 (1 stop bit) and the PRYE bit in the U2MR register is set to 1 (parity ST: Start bit P: Parity bit SP: Stop bit Figure 14.19 Serial Data Logic Switching 14.1.2.5 TxD and RxD I/O Polarity Inverse Function (UART2) This function inverses the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all input/output data (including the start, stop and parity bits) are inversed. Figure 14.20 shows the TXD pin output and RXD pin input polarity inverse. (1) When the IOPOL bit in the U2MR register is set to 0 (no reverse) Transfer clock TxD2 “H” “L” “H” (no reverse) “L” (no reverse) “L” ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP RxD2 “H” (2) When the IOPOL bit in the U2MR register is set to 1 (reverse) Transfer clock (reverse) “H” “L” “H” “L” “H” “L” TxD2 ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP (reverse) RxD2 NOTE: 1. This applies to the case where the UFORM bit in the U2C0 register is set to 0 (LSB first), the STPS bit in the U2MR register is set to 0 (1 stop bit) and the PRYE bit in the U2MR register is set to 1 (parity enabled). ST: Start bit P: Parity bit SP: Stop bit Figure 14.20 TXD and RXD I/O Polarity Inverse Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 194 of 458 M16C/29 Group _______ _______ 14. Serial I/O 14.1.2.6 CTS/RTS Separate Function (UART0) _______ _______ _______ _______ This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64 pin or P70 pin. To use this function, set the register bits as shown below. _______ _______ • The CRD bit in the U0C0 register is set to 0 (enables UART0 CTS/RTS) _______ • The CRS bit in the U0C0 register is set to 1 (outputs UART0 RTS) _______ _______ • The CRD bit in the U1C0 register is set to 0 (enables UART1 CTS/RTS) • The CRS bit in the U1C0 register is set to 0 (inputs UART1 CTS) _______ • The RCSP bit in the UCON register is set to 1 (inputs CTS0 from the P64 pin or P70 pin) • The CLKMD1 bit in the UCON register is set to 0 (CLKS1 not used) _______ _______ _______ _______ Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be used. MCU TXD0 (P6 3) RXD0 (P6 2) IN OUT _______ IC RTS0 (P60) CTS0 (P6 4) CTS RTS NOTE: 1. This applies to the case where the U1MAP bit in the PACR register is set to 0 (P67 to P64). _______ _______ Figure 14.21 CTS/RTS Separate Function Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 195 of 458 M16C/29 Group 14. Serial I/O 14.1.3 Special Mode 1 (I2C bus mode)(UART2) I2C bus mode is provided for use as a simplifed I2C bus interface compatible mode. Table 14.10 lists the specifications of the I2C bus mode. Tables 14.11 and 14.12 list the registers used in the I2C bus mode and the register values set. Table 14.13 lists the I2C bus mode fuctions. Figure 14.22 shows the block diagram for I2C bus mode. Figure 14.23 shows SCL2 timing. As shown in Table 14.13, the MCU is placed in I2C bus mode by setting bits SMD2 to SMD0 to 0102 and the IICM bit to 1. Because SDA2 transmit output has a delay circuit attached, SDA output does not change state until SCL2 goes low and remains stably low. Table 14.10 I2C bus mode Specifications Item Transfer data format Transfer clock • Transfer data length: 8 bits • During master the CKDIR bit in the U2MR register is set to 0 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value in the U2BRG register 0016 to FF16 • During slave Transmission start condition CKDIR bit is set to 1 (external clock ) : Input from SCL2 pin • Before transmission can start, the following requirements must be met (1) _ _ Specification The TE bit in the U2C1 register is set to 1 (transmission enabled) The TI bit in the U2C1 register is set to 0 (data present in U2TB register) Reception start condition _ • Before reception can start, the following requirements must be met (1) The RE bit in the U2C1 register is set to 1 (reception enabled) _ _ The TE bit in the U2C1 register is set to 1 (transmission enabled) The TI bit in the U2C1 register is set to 0 (data present in the UiTB register) Interrupt request generation timing Error detection When start or stop condition is detected, acknowledge undetected, and acknowledge detected • Overrun error (2) This error occurs if the serial I/O started receiving the next data before reading the U2RB register and received the 8th bit in the the next data • Arbitration lost Timing at which the ABT bit in the U2RB register is updated can be selected • SDA digital delay No digital delay or a delay of 2 to 8 U2BRG count source clock cycles selectable • Clock phase setting With or without clock delay selectable Select function NOTES: 1. When an external clock is selected, the conditions must be met while the external clock is in the high state. 2. If an overrun error occurs, bits 8 to 0 in the U2RB register are undefined. The IR bit in the S2RIC register remains unchange. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 196 of 458 M16C/29 Group 14. Serial I/O SDA2 Delay circuit ACKC=1 ACKD bit Start and stop condition generation block STSPSEL=1 STSPSEL=0 ACKC=0 SDHI DQ T DMA0, DMA1 request SDASTSP SCLSTSP Transmission register UART2 ALS IICM2=1 IICM=1 and IICM2=0 UART2 transmit, NACK interrupt request Arbitration IICM2=1 DMA0 Noise Filter Reception register UART2 Start condition detection IICM=1 and IICM2=0 UART2 receive, ACK interrupt request, DMA1 request S R Q Bus busy NACK Stop condition detection DQ T DQ T SCL2 Falling edge detection IICM=0 R I/O port STSPSEL=0 Q Port register (1) Internal clock CLK control ACK 9th bit Noise Filter SWC2 IICM=1UART2 STSPSEL=1 External clock R S UART2 9th bit falling edge SWC Start/stop condition detection interrupt request This diagram applies to the case where bits SMD2 to SMD0 in the U2MR register is set to 0102 and the IICM bit in the U2SMR register is set to 1. IICM: Bit in the U2SMR register IICM2, SWC, ALS, SWC2, SDHI: Bits in the U2SMR2 register STSPSEL, ACKD, ACKC: Bits in the U2SMR4 register NOTE: 1. If the IICM bit is set to 1, the pin can be read even when the PD7_1 bit is set to 1 (output mode). Figure 14.22 I2C bus mode Block Diagram Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 197 of 458 M16C/29 Group Table 14.11 Registers to Be Used and Settings in I2C bus mode (1) (Continued) Register U2TB 0 to 7 Bit Master Set transmission data Reception data can be read ACK or NACK is set in this bit Arbitration lost detection flag Overrun error flag Set bit rate Set to 0102 Set to 0 Set to 0 Select the count source for the U2BRG register Invalid because CRD = 1 Transmit buffer empty flag Set to 1 Set to 1 Set to 0 Set to 1 Set this bit to 1 to enable transmission Transmit buffer empty flag Set this bit to 1 to enable reception Reception complete flag Invalid Set to 0 Set to 1 Select the timing at which arbitration-lost is detected Bus busy flag Set to 0 Refer to Table 14.13 Set this bit to 1 to enable clock synchronization Set this bit to 1 to have SCL2 output fixed to L at the falling edge of the 9th bit of clock Set this bit to 1 to have SDA2 output stopped when arbitration-lost is detected Set to 0 Function Slave Set transmission data Reception data can be read ACK or NACK is set in this bit Invalid Overrun error flag Invalid Set to 0102 Set to 1 Set to 0 Invalid 14. Serial I/O U2RB(1) 0 to 7 8 ABT OER U2BRG 0 to 7 U2MR(1) SMD2 to SMD0 CKDIR IOPOL U2C0 CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM U2C1 TE TI RE RI U2IRS U2RRM, U2LCH, U2ERE U2SMR IICM ABC BBS 3 to 7 U2SMR2 IICM2 CSC SWC Invalid because CRD = 1 Transmit buffer empty flag Set to 1 Set to 1 Set to 0 Set to 1 Set this bit to 1 to enable transmission Transmit buffer empty flag Set this bit to 1 to enable reception Reception complete flag Invalid Set to 0 Set to 1 Invalid Bus busy flag Set to 0 Refer to Table 14.13 Set to 0 Set this bit to 1 to have SCL2 output fixed to “L” at the falling edge of the 9th bit of clock Set to 0 Set this bit to 1 to initialize UART2 at start condition detection Set this bit to 1 to have SCL2 output forcibly pulled low Set this bit to 1 to disable SDA2 output Set to 0 Set to 0 Refer to Table 14.13 Set the amount of SDA2 digital delay ALS STAC SWC2 Set this bit to 1 to have SCL2 output forcibly pulled low SDHI Set this bit to 1 to disable SDA2 output 7 Set to 0 U2SMR3 0, 2, 4 and NODC Set to 0 CKPH Refer to Table 14.13 DL2 to DL0 Set the amount of SDA2 digital delay NOTE: 1. Not all bits in the register are described above. Set those bits to 0 when writing to the registers in I2C bus mode. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 198 of 458 M16C/29 Group 14. Serial I/O Table 14.12 Registers to Be Used and Settings in I2C bus Mode (2) (Continued) Register Bit Function Master Set this bit to 1 to generate start condition Set this bit to 1 to generate restart condition Set this bit to 1 to generate stop condition Set this bit to 1 to output each condition Select ACK or NACK Set this bit to 1 to output ACK data Set this bit to 1 to have SCL2 output stopped when stop condition is detected Set to 0 Slave Set to 0 Set to 0 Set to 0 Set to 0 Select ACK or NACK Set this bit to 1 to output ACK data Set to 0 Set this bit to 1 to set the SCL2 to “L” hold at the falling edge of the 9th bit of clock U2SMR4 STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI SWC9 NOTE: 1: Not all bits in the register are described above. Set those bits to 0 when writing to the registers in I2C bus mode. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 199 of 458 M16C/29 Group Table 14.13 I2C bus mode Functions Function 14. Serial I/O Clock synchronous serial I/O I2C bus mode (SMD2 to SMD0 = 0102, IICM = 1) mode (SMD2 to SMD0 = 0012, IICM2 = 0 IICM2 = 1 IICM = 0) (NACK/ACK interrupt) (UART transmit/ receive interrupt) CKPH = 1 CKPH = 1 CKPH = 0 CKPH = 0 (Clock delay) (No clock delay) (Clock delay) (No clock delay) Start condition detection or stop condition detection (Refer to Table 14.14) No acknowledgment detection (NACK) Rising edge of SCL2 9th bit Acknowledgment detection (ACK) Rising edge of SCL2 9th bit Rising edge of SCL2 9th bit UART2 transmission UART2 transmission Rising edge of Falling edge of SCL2 SCL2 9th bit next to the 9th bit UART2 transmission Falling edge of SCL2 9th bit Falling and rising edges of SCL2 9th bit Factor of interrupt number 10 (1) (Refer to Fig.14.23) Factor of interrupt number UART2 transmission 15 (1) (Refer to Fig.14.23) Transmission started or completed (selected by U2IRS) Factor of interrupt number UART2 reception 16 (1) (Refer to Fig.14.23) When 8th bit received CKPOL = 0 (rising edge) CKPOL = 1 (falling edge) Timing for transferring data CKPOL = 0 (rising edge) from the UART reception CKPOL = 1 (falling edge) shift register to the U2RB register UART2 transmission Not delayed output delay Functions of P70 pin Functions of P71 pin Functions of P72 pin Noise filter width Read RxD2 and SCL2 pin levels Initial value of TxD2 and SDA2 outputs Initial and end values of SCL2 DMA1 factor (Refer to Fig. UART2 reception 14.23) Store received data 1st to 8th bits are stored in bits bit 7 to 0 in the U2RB register TxD2 output RxD2 input CLK2 input or output selected 15ns Falling edge of SCL2 9th bit Delayed SDA2 input/output SCL2 input/output (Cannot be used in I2C bus mode) 200ns Always possible no matter how the corresponding port direction bit is set Possible when the corresponding port direction bit =0 CKPOL = 0 (H) The value set in the port register before setting I2C bus mode (2) CKPOL = 1 (L) H L H L Acknowledgment detection (ACK) 1st to 8th bits are stored in bits bit 7 to 0 in the U2RB register UART2 reception Falling edge of SCL2 9th bit 1st to 7th bits are stored into the bit 6 to bit 0 in the U2RB register, with 8th bit stored in the bit 8 in the U2RB register 1st to 8th bits are stored in U2RB register bit 7 to bit 0 (3) Read received data U2RB register status is read directly as is Read U2RB register Bit 6 to bit 0 as bit 7 to bit 1, and bit 8 as bit 0 (4) NOTES: 1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may inadvertently be set to 1 (interrupt requested). (Refer to “Notes on interrupts” in Precautions.) . If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, . always be sure to clear the IR bit to 0 (interrupt not requested) after changing those bits Bits SMD2 to the SMD0 in the U2MR register, the IICM bit in the U2SMR register, the IICM2 bit in the U2SMR2 register, the CKPH bit in the U2SMR3 register 2. Set the initial value of SDA2 output while bits SMD2 to SMD0 in the U2MR register is set to 0002 (serial I/O disabled). 3. Second data transfer to U2RB register (Rising edge of SCL2 9th bit) 4. First data transfer to U2RB register (Falling edge of SCL2 9th bit) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 200 of 458 M16C/29 Group 14. Serial I/O (1) When the IICM2 bit is set to 0 (ACK or NACK interrupt) and the CKPH bit is set to 0 (No clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCL2 SDA2 D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) ACK interrupt (DMA request) or NACK interrupt b15 b9 ••• b8 b7 b0 Data is transferred to the U2RB register D8 D7 D6 D5 D4 D3 D 2 D1 D0 Contents of the U2RB register (2) When the IICM2 bit is set to 0 and the CKPH bit is set to 1 (clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCL2 SDA2 D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) ACK interrupt (DMA request) or NACK interrupt b15 b9 b8 b7 b0 Data is transferred to the U2RB register ••• D8 D 7 D6 D5 D4 D3 D2 D1 D0 Contents of the U2RB register (3) When the IICM2 bit is set to 1 (UART transmit or receive interrupt) and the CKPH bit is set to 0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCL2 SDA2 D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) Transmit interrupt b15 ••• b9 b8 b7 b0 Receive interrupt (DMA request) Data is transferred to the U2RB register D0 D7 D6 D 5 D4 D3 D2 D1 Contents in the U2RB register (4) When the IICM2 bit is set to 1 and the CKPH bit is set to 1 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCL2 SDA2 D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) Transmit interrupt Receive interrupt (DMA request) Data is transferred to the U2RB register b15 ••• b9 b8 b7 b0 Data is transferred to the U2RB register b15 ••• b9 b8 b7 b0 D0 D7 D6 D5 D 4 D3 D2 D1 D8 D7 D6 D5 D4 D 3 D2 D 1 D0 Contents in the U2RB register The above timing applies to the following setting : • The CKDIR bit in the U2MR register is set to 1 (slave) Contents in the U2RB register Figure 14.23 Transfer to U2RB Register and Interrupt Timing Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 201 of 458 M16C/29 Group 14. Serial I/O 14.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDA2 pin changes state from high to low while the SCL2 pin is in the high state. A stop condition-detected interrupt request is generated when the SDA2 pin changes state from low to high while the SCL2 pin is in the high state. Because the start and stop condition-detected interrupts share the interrupt control register and vector, check the BBS bit in the U2SMR register to determine which interrupt source is requesting the interrupt. 3 to 6 cycles < setup time (1) 3 to 6 cycles < hold time (1) Setup time SCL2 SDA2 (Start condition) SDA2 (Stop condition) Hold time NOTE: 1. When the PCLK1 bit in the PCLKR register is set to 1, the cycles indicates the f1SIO's generation frequency cycles; when PCLK1 bit is set to 0, the cycles indicated the f2SIO's generation frequency cycles. Figure 14.24 Detection of Start and Stop Condition 14.1.3.2 Output of Start and Stop Condition A start condition is generated by setting the STAREQ bit in the U2SMR4 register to 1 (start). A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to 1 (start). A stop condition is generated by setting the STPREQ bit in the U2SMR4 register to 1 (start). The output procedure is described below. (1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to 1 (start). (2) Set the STSPSEL bit in the U2SMR4 register to 1 (output). Make sure that no interrupts or DMA transfers will occur between (1) and (2). The function of the STSPSEL bit is shown in Table 14.14 and Figure 14.25. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 202 of 458 M16C/29 Group 14. Serial I/O Table 14.14 STSPSEL Bit Functions Function Output of SCL2 and SDA2 pins STSPSEL = 0 Output transfer clock and data/ Program with a port determines how the start condition or stop condition is output Start/stop condition are detected STSPSEL = 1 The STAREQ, RSTAREQ and STPREQ bit determine how the start condition or stop condition is output Start/stop condition generation are completed Start/stop condition interrupt request generation timing (1) In slave mode, CKDIR is set to 1 (external clock) STPSEL bit SCL2 SDA2 0 1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit Start condition detection interrupt Stop condition detection interrupt (2) In master mode, CKDIR is set to 0 (internal clock), CKPH is set to 1(clock delayed) STPSEL bit Set to 1 by program Set to 0 by program 1st 2nd 3rd 4th 5th 6th 7th 8th Set to 1 by program 9th bit Set to 0 by program SCL2 SDA2 Set STAREQ to 1 (start) Start condition detection interrupt Set STPREQ to 1 (start) Stop condition detection interrupt Figure 14.25 STSPSEL Bit Functions 14.1.3.3 Arbitration Unmatching of the transmit data and SDA2 pin input data is checked synchronously with the rising edge of SCL2. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the U2RB register is updated. If the ABC bit is set to 0 (updated bitwise), the ABT bit is set to 1 at the same time unmatching is detected during check, and is cleared to 0 when not detected. In cases when the ABC bit is set to 1, if unmatching is detected even once during check, the ABT bit is set to 1 (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated bytewise, clear the ABT bit to 0 (undetected) after detecting acknowledge in the first byte, before transferring the next byte. Setting the ALS bit in the U2SMR2 register to 1 (SDA2 output stop enabled) causes arbitration-lost to occur, in which case the SDA2 pin is placed in the high-impedance state at the same time the ABT bit is set to 1 (unmatching detected). Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 203 of 458 M16C/29 Group 14. Serial I/O 14.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 14.25. The CSC bit in the U2SMR2 register is used to synchronize the internally generated clock (internal SCL2) and an external clock supplied to the SCL2 pin. In cases when the CSC bit is set to 1 (clock synchronization enabled), if a falling edge on the SCL2 pin is detected while the internal SCL2 is high, the internal SCL2 goes low, at which time the U2BRG register value is reloaded with and starts counting in the low-level interval. If the internal SCL2 changes state from low to high while the SCL2 pin is low, counting stops, and when the SCL2 pin goes high, counting restarts. In this way, the UART2 transfer clock is comprised of the logical product of the internal SCL2 and SCL2 pin signal. The transfer clock works from a half period before the falling edge of the internal SCL2 1st bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock. The SWC bit in the U2SMR2 register allows to select whether the SCL2 pin should be fixed to or freed from low-level output at the falling edge of the 9th clock pulse. If the SCLHI bit in the U2SMR4 register is set to 1 (enabled), SCL2 output is turned off (placed in the high-impedance state) when a stop condition is detected. Setting the SWC2 bit in the U2SMR2 register is set to 1 (0 output) makes it possible to forcibly output a low-level signal from the SCL2 pin even while sending or receiving data. Clearing the SWC2 bit to 0 (transfer clock) allows the transfer clock to be output from or supplied to the SCL2 pin, instead of outputting a low-level signal. If the SWC9 bit in the U2SMR4 register is set to 1 (SCL2 hold low enabled) when the CKPH bit in the U2SMR3 register is set to 1, the SCL2 pin is fixed to low-level output at the falling edge of the clock pulse next to the ninth. Setting the SWC9 bit to 0 (SCL2 hold low disabled) frees the SCL2 pin from low-level output. 14.1.3.5 SDA Output The data written to the bit 7 to bit 0 (D7 to D0) in the U2TB register is sequentially output beginning with D7. The ninth bit (D8) is ACK or NACK. The initial value of SDA2 transmit output can only be set when IICM is set to 1 (I2C bus mode) and bits SMD2 to SMD0 in the U2MR register is set to 0002 (serial I/O disabled). Bits DL2 to DL0 in the U2SMR3 register allow to add no delays or a delay of 2 to 8 U2BRG count source clock cycles to SDA2 output. Setting the SDHI bit in the U2SMR2 register to 1 (SDA2 output disabled) forcibly places the SDA2 pin in the high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UART2 transfer clock. This is because the ABT bit may inadvertently be set to 1 (detected). 14.1.3.6 SDA Input When the IICM2 bit is set to 0, the 1st to 8th bits (D7 to D0) in the received data are stored in bits 7 to 0 in the U2RB register. The 9th bit (D8) is ACK or NACK. When the IICM2 bit is set to 1, the 1st to 7th bits (D7 to D1) in the received data are stored in the bit 6 to bit 0 in the U2RB register and the 8th bit (D0) is stored in the bit 8 in the U2RB register. Even when the IICM2 bit is set to 1, providing the CKPH bit is set to 1, the same data as when the IICM2 bit is set to 0 can be read out by reading the U2RB register after the rising edge of the corresponding clock pulse of 9th bit. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 204 of 458 M16C/29 Group 14. Serial I/O 14.1.3.7 ACK and NACK If the STSPSEL bit in the U2SMR4 register is set to 0 (start and stop conditions not generated) and the ACKC bit in the U2SMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the U2SMR4 register is output from the SDA2 pin. If the IICM2 bit is set to 0, a NACK interrupt request is generated if the SDA2 pin remains high at the rising edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDA2 pin is low at the rising edge of the 9th bit of transmit clock pulse. If ACK2 is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an acknowledge. 14.1.3.8 Initialization of Transmission/Reception If a start condition is detected while the STAC bit is set to 1 (UART2 initialization enabled), the serial I/ O operates as described below. - The transmit shift register is initialized, and the content of the U2TB register is transferred to the transmit shift register. In this way, the serial I/O starts sending data synchronously with the next clock pulse applied. However, the UART2 output value does not change state and remains the same as when a start condition was detected until the first bit in the data is output synchronously with the input clock. - The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the next clock pulse applied. - The SWC bit is set to 1 (SCL2 wait output enabled). Consequently, the SCL2 pin is pulled low at the falling edge of the ninth clock pulse. Note that when UART2 transmission/reception is started using this function, the TI does not change state. Note also that when using this function, the selected transfer clock should be an external clock. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 205 of 458 M16C/29 Group 14. Serial I/O 14.1.4 Special Mode 2 (UART2) Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 14.15 lists the specifications of Special Mode 2. Table 14.16 lists the registers used in Special Mode 2 and the register values set. Figure 14.26 shows communication control example for Special Mode 2. Table 14.15 Special Mode 2 Specifications Item Transfer data format Transfer clock • Transfer data length: 8 bits • Master mode the CKDIR bit in the U2MR register is set to 0 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value in the U2BRG register • Slave mode Transmit/receive control Transmission start condition CKDIR bit is set to 1 (external clock selected) : Input from CLK2 pin Controlled by input/output ports • Before transmission can start, the following requirements must be met (1) _ The TE bit in the U2C1 register is set to 1 (transmission enabled) The TI bit in the U2C1 register is set to 0 (data present in U2TB register) • Before reception can start, the following requirements must be met (1) _ _ _ _ Specification 0016 to FF16 Reception start condition The RE bit in the U2C1 register is set to 1 (reception enabled) The TE bit in the U2C1 register is set to 1 (transmission enabled) Interrupt request generation timing Error detection The TI bit in the U2C1 register is set to 0 (data present in the U2TB register) • For transmission, one of the following conditions can be selected _ The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty): when trans ferring data from the U2TB register to the UART2 transmit register (at start of transmission) _ The U2IRS bit is set to 1 (transfer completed): when the serial I/O finished sending data from the UART2 transmit register • For reception When transferring data from the UART2 receive register to the U2RB register (at completion of reception) • Overrun error (2) This error occurs if the serial I/O started receiving the next data before reading the U2RB register and received the 7th bit in the the next data Select function • Clock phase setting Selectable from four combinations of transfer clock polarities and phases NOTES: 1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the U2C0 register is set to 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the U2C0 register is set to 1 (transmit data output at the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state. 2. If an overrun error occurs, bits 8 to 0 in the U2RB register are undefined. The IR bit in the S2RIC register remains unchanged. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 206 of 458 M16C/29 Group 14. Serial I/O P13 P12 P93 P72(CLK2) P71(RxD2) P70(TxD2) MCU (Master) P72(CLK2) P71(RxD2) P70(TxD2) MCU (Slave) P93 P72(CLK2) P71(RxD2) P70(TxD2) MCU (Slave) Figure 14.26 Serial Bus Communication Control Example (UART2) Table 14.16 Registers to Be Used and Settings in Special Mode 2 Register U2TB(1) U2RB(1) U2BRG U2MR(1) Bit 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR IOPOL CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI U2IRS U2RRM, U2LCH, U2ERE 0 to 7 0 to 7 CKPH NODC 0, 2, 4 to 7 0 to 7 Function Set transmission data Reception data can be read Overrun error flag Set bit rate Set to 0012 Set this bit to 0 for master mode or 1 for slave mode Set to 0 Select the count source for the U2BRG register Invalid because CRD is set to 1 Transmit register empty flag Set to 1 Select TxD2 pin output format Clock phases can be set in combination with the CKPH bit in the U2SMR3 register Select the LSB first or MSB first Set this bit to 1 to enable transmission Transmit buffer empty flag Set this bit to 1 to enable reception Reception complete flag Select UART2 transmit interrupt cause Set to 0 Set to 0 Set to 0 Clock phases can be set in combination with the CKPOL bit in the U2C0 register Set to 0 Set to 0 Set to 0 U2C0 U2C1 U2SMR U2SMR2 U2SMR3 U2SMR4 NOTE: 1.Not all bits in the registers are described above. Set those bits to 0 when writing to the registers in Special Mode 2. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 207 of 458 M16C/29 Group 14. Serial I/O 14.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the U2SMR3 register and the CKPOL bit in the U2C0 register. Make sure the transfer clock polarity and phase are the same for the master and slave to communicate. 14.1.4.1.1 Master (Internal Clock) Figure 14.27 shows the transmission and reception timing in master (internal clock). 14.1.4.1.2 Slave (External Clock) Figure 14.28 shows the transmission and reception timing (CKPH=0) in slave (external clock) while Figure 14.29 shows the transmission and reception timing (CKPH=1) in slave (external clock). "H" Clock output (CKPOL=0, CKPH=0) "L" "H" Clock output (CKPOL=1, CKPH=0) "L" Clock output "H" (CKPOL=0, CKPH=1) "L" "H" Clock output (CKPOL=1, CKPH=1) "L" Data output timing "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 Data input timing Figure 14.27 Transmission and Reception Timing in Master Mode (Internal Clock) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 208 of 458 M16C/29 Group 14. Serial I/O Slave control input "H" "L" "H" Clock input (CKPOL=0, CKPH=0) "L" "H" Clock input (CKPOL=1, CKPH=0) "L" Data output timing "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 Data input timing Undefined Figure 14.28 Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock) Slave control input Clock input (CKPOL=0, CKPH=1) Clock input (CKPOL=1, CKPH=1) "H" "L" "H" "L" "H" "L" Data output timing "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 Data input timing Figure 14.29 Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 209 of 458 M16C/29 Group 14. Serial I/O 14.1.5 Special Mode 3 (IEBus mode)(UART2) In this mode, one bit in the IEBus is approximated with one byte of UART mode waveform. Table 14.17 lists the registers used in IEBus mode and the register values set. Figure 14.30 shows the functions of bus collision detect function related bits. If the TxD2 pin output level and RxD2 pin input level do not match, a UART2 bus collision detect interrupt request is generated. Table 14.17 Registers to Be Used and Settings in IEBus Mode Register U2TB U2RB(1) U2BRG U2MR Bit 0 to 8 0 to 8 OER,FER,PER,SUM 0 to 7 SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM TE TI RE RI U2IRS U2RRM, U2LCH, U2ERE 0 to 3, 7 ABSCS ACSE SSS 0 to 7 0 to 7 0 to 7 Function Set transmission data Reception data can be read Error flag Set bit rate Set to 1102 Select the internal clock or external clock Set to 0 Invalid because PRYE is set to 0 Set to 0 Select the TxD/RxD input/output polarity Select the count source for the U2BRG register Invalid because CRDis set to 1 Transmit register empty flag Set to 1 Select TxD2 pin output mode Set to 0 Set to 0 Set this bit to 1 to enable transmission Transmit buffer empty flag Set this bit to 1 to enable reception Reception complete flag Select the source of UART2 transmit interrupt Set to 0 Set to 0 Select the sampling timing at which to detect a bus collision Set this bit to 1 to use the auto clear function of transmit enable bit Select the transmit start condition Set to 0 Set to 0 Set to 0 U2C0 U2C1 U2SMR U2SMR2 U2SMR3 U2SMR4 NOTE: 1. Not all register bits are described above. Set those bits to 0 when writing to the registers in IEBus mode. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 210 of 458 M16C/29 Group 14. Serial I/O (1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select) If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Transfer clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxD2 RxD2 Input to TA0IN Timer A0 If ABSCS is set to 1, bus collision is determined when timer . A0 (one-shot timer mode) underflows (2) The ACSE bit in the U2SMR register (auto clear of transmit enable bit) Transfer clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxD2 RxD2 BCNIC register IR bit (Note) U2C1 register TE bit If ACSE bit is set to 1 automatically clear when bus collision occurs), the TE bit is cleared to 0 (transmission disabled) when the IR bit in the BCNIC register is set to 1 (unmatching detected). (3) The SSS bit in the U2SMR register (Transmit start condition select) If SSS bit is set to 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met. Transfer clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxD2 Transmission enable condition is met If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxD2 CLK2 ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxD2 RxD2 (Note 2) NOTES: 1: The falling edge of RxD2 when the IOPOL is set to 0; the rising edge of RxD2 when the IOPOL is set to 1. 2: The transmit condition must be met before the falling edge (Note 1) of RxD. . This diagram applies to the case where the IOPOL is set to 1 (reversed) Figure 14.30 Bus Collision Detect Function-Related Bits Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 211 of 458 M16C/29 Group 14. Serial I/O 14.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected. Table 14.18 lists the specifications of SIM mode. Table 14.19 lists the registers used in the SIM mode and the register values set. Table 14.18 SIM Mode Specifications Item Transfer data format Transfer clock Specification • Direct format • Inverse format • The CKDIR bit in the U2MR register is set to 0 (internal clock) : fi/ (16(n+1)) fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register 0016 to FF16 • The CKDIR bit is set to 1 (external clock ) : fEXT/16(n+1) fEXT: Input from CLK2 pin. n: Setting value of U2BRG register 0016 to FF16 • Before transmission can start, the following requirements must be met _ The TE bit in the U2C1 register is set to 1 (transmission enabled) _ The TI bit in the U2C1 register is set to 0 (data present in U2TB register) • Before reception can start, the following requirements must be met _ The RE bit in the U2C1 register is set to 1 (reception enabled) _ Start bit detection • For transmission When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit =1) • For reception When transferring data from the UART2 receive register to the U2RB register (at completion of reception) • Overrun error (1) This error occurs if the serial I/O started receiving the next data before reading the U2RB register and received the bit one before the last stop bit in the the next data • Framing error This error occurs when the number of stop bits set is not detected • Parity error During reception, if a parity error is detected, parity error signal is output from the TxD2 pin. During transmission, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs • Error sum flag This flag is set to 1 when any of the overrun, framing, and parity errors is encountered Transmission start condition Reception start condition Interrupt request generation timing (2) Error detection NOTES: 1. If an overrun error occurs, bits 8 to 0 in the U2RB register are undefined. The IR bit in the S2RIC register remains unchanged. 2. A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to 1 (transmission complete) and U2ERE bit to 1 (error signal output) after reset. Therefore, when using SIM mode, be sure to clear the IR bit to 0 (no interrupt request) after setting these bits. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 212 of 458 M16C/29 Group 14. Serial I/O Table 14.19 Registers to Be Used and Settings in SIM Mode Register U2TB(1) U2RB(1) U2BRG U2MR Bit 0 to 7 0 to 7 OER,FER,PER,SUM 0 to 7 SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM U2C1 TE TI RE RI U2IRS U2RRM U2LCH U2ERE U2SMR(1) U2SMR2 U2SMR3 U2SMR4 0 to 3 0 to 7 0 to 7 0 to 7 Function Set transmission data Reception data can be read Error flag Set bit rate Set to 1012 Select the internal clock or external clock Set to 0 Set this bit to 1 for direct format or 0 for inverse format Set to 1 Set to 0 Select the count source for the U2BRG register Invalid because CRDis set to 1 Transmit register empty flag Set to 1 Set to 0 Set to 0 Set this bit to 0 for direct format or 1 for inverse format Set this bit to 1 to enable transmission Transmit buffer empty flag Set this bit to 1 to enable reception Reception complete flag Set to 1 Set to 0 Set this bit to 0 for direct format or 1 for inverse format Set to 1 Set to 0 Set to 0 Set to 0 Set to 0 U2C0 NOTE: 1. Not all register bits are described above. Set those bits to 0 when writing to the registers in SIM mode. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 213 of 458 M16C/29 Group 14. Serial I/O (1) Transmit Timing Tc Transfer Clock TE bit in U2C1 register TI bit in U2C1 register 1 0 1 0 Data is written to the UART2 register TxD2 Parity Error Signal returned from Receiving End RxD2 pin Level (1) TXEPT bit in U2 C0 register IR bit in S2TIC register 1 0 1 0 Start bit ST D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit P SP Data is transferred from the U2TB register to the UART2 transmit register ST D0 D1 D2 D3 D4 D5 D6 D7 An "L" signal is applied from the SIM card due to a parity error P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D 6 D 7 P SP An interrupt routine detects "H" or "L" An interrupt routine detects "H" or "L" Set to 0 by an interrupt request acknowledgement or by program The above timing diagram applies to the case where data is transferred in the direct format. • U2MR register STPS bit = 0 (1 stop bit) • U2MR register PRY bit = 1 (even) • U2C0 register UFORM bit = 0 (LSB first) • U2C1 register U2LCH bit = 0 (no reverse) • U2C1 register U2IRSCH bit = 1 (transmit is completed) Tc = 16 (n + 1) / fi or 16 (n + 1) / f EXT fi : frequency of U2BRG count source (f 1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of U2BRG count source (external clock) n : value set to U2BRG (2) Receive Timing Transfer Clock RE bit in U2C1 register Transmit Waveform from the Transmitting End TxD2 RxD2 pin Level (2) RI bit in U2C1 register IR bit in S2RIC register 1 0 1 0 1 0 Start bit TC Parity Stop bit bit P SP ST D0 D1 D2 D3 D4 D5 D6 D7 TxD2 outputs "L" due to a parity error P SP ST D0 D1 D2 D3 D4 D5 D6 D7 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Read the U2RB register The above timing diagram applies to the case where data is transferred in the direct format. • U2MR register STPS bit = 0 (1 stop bit) • U2MR register PRY bit = 1 (even) • U2C0 register UFORM bit = 0 (LSB first) • U2C1 register U2LCH bit = 0 (no reverse) • U2C1 register U2IRSCH bit = 1 (transmit is completed) Set to 0 by an interrupt request acknowledgement or by program Tc = 16 (n + 1) / fi or 16 (n + 1) / f EXT fi : frequency of U2BRG count source (f 1SIO, f2SIO, f8SIO, f32SIO) fEXT : frequency of U2BRG count source (external clock) n : value set to U2BRG NOTES: 1. Because TxD2 and RxD2 are connected, this is composite waveform consisting of the TxD2 output and the parity error signal sent back from receiver. 2. Because TxD2 and RxD2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the parity error signal received. Figure 14.31 Transmit and Receive Timing in SIM Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 214 of 458 M16C/29 Group 14. Serial I/O Figure 14.32 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. MCU SIM card TxD2 RxD2 Figure 14.32 SIM Interface Connection 14.1.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in theU2C1 register to 1. • When receiving The parity error signal is output when a parity error is detected while receiving data. This is achieved by pulling the TxD2 output low with the timing shown in Figure 14.33. If the R2RB register is read while outputting a parity error signal, the PER bit is cleared to 0 and at the same time the TxD2 output is returned high. • When transmitting A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service routine. Transfer clock RxD 2 TxD2 U2C1 register RI bit “H” “L” “H” “L” “H” “L” 1 0 ST D0 D1 D2 D3 (1) D4 D5 D6 D7 P SP This timing diagram applies to the case where the direct format is implemented. NOTE: 1. The output of MCU is in the high-impedance state (pulled up externally). ST: Start bit P: Even Parity SP: Stop bit Figure 14.33 Parity Error Signal Output Timing Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 215 of 458 M16C/29 Group 14. Serial I/O 14.1.6.2 Format • Direct Format Set the PRY bit in the U2MR register to 1, the UFORM bit in U2C0 register to 0 and the U2LCH bit in U2C1 register to 0. • Inverse Format Set the PRY bit to 0, UFORM bit to 1 and U2LCH bit to 1. Figure 14.34 shows the SIM interface format. (1) Direct format Transfer clcck TxD2 “H” “L” “H” “L” D0 D1 D2 D3 D4 D5 D6 D7 P P : Even parity (2) Inverse format Transfer clcck “H” “L” TxD2 “H” “L” D7 D6 D5 D4 D3 D2 D1 D0 P P : Odd parity Figure 14.34 SIM Interface Format Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 216 of 458 M16C/29 Group 14. Serial I/O 14.2 SI/O3 and SI/O4 Note The SI/O4 interrupt of peripheral function interrupt is not available in the 64-pin package. SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os. Figure 14.35 shows the block diagram of SI/O3 and SI/O4, and Figure 14.36 shows the SI/O3 and SI/O4related registers. Table 14.20 shows the specifications of SI/O3 and SI/O4. Main clock, f1SIO PLL clock, or on-chip oscillator clock 1/2 f2SIO PCLK1=0 Clock source select SMi1 to SMi0 002 f8SIO f32SIO 012 102 Synchronous circuit Data bus 1/8 PCLK1=1 1/4 1/2 1/(n+1) SiBRG register SI/Oi interrupt request SMi4 CLKi CLK polarity reversing circuit SMi3 SMi6 SMi6 SI/O counter i SMi2 SMi3 SOUTi SINi SMi5 LSB MSB SiTRR register 8 Note: i = 3, 4. n = A value set in the SiBRG register. Figure 14.35 SI/O3 and SI/O4 Block Diagram Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 217 of 458 M16C/29 Group 14. Serial I/O SI/Oi Control Register (i = 3, 4) (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol S3C S4C Bit Symbol SMi0 SMi1 SMi2 SMi3 SMi4 SOUTi output disable bit (4) S I/Oi port select bit CLK polarity selct bit Address 036216 036616 After Reset 010000002 010000002 Bit Name Internal synchronous clock select bit (5) b1 b0 Function 0 0 : Selecting f1 or f2 0 1 : Selecting f8 1 0 : Selecting f32 1 1 : Do not set 0 : SOUTi output 1 : SOUTi output disable(high impedance) 0 : Input/output port 1 : SOUTi output, CLKi function 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge 0 : LSB first 1 : MSB first 0 : External clock (2) 1 : Internal clock (3) Effective when the SMi3 is set to 0 0 : “L” output 1 : “H” output RW RW RW RW RW RW SMi5 SMi6 SMi7 Transfer direction select bit Synchronous clock select bit SOUTi initial value set bit RW RW RW NOTES: 1. Set the S4C register by the next instruction after setting the PRC2 bit in the PRCR register to 1 (write enable). 2. Set the SMi3 bit to 1 and the corresponding port direction bit to 0 (input mode). 3. Set the SMi3 bit to 1 (SOUTi output, CLKi function) . 4. When the SMi2 bit is set to 1, the corresponding pin goes to high-impedance regardless of the function in use. 5. When the SMi1 and SMi0 bit settings are changed, set the SiBRG register . SI/Oi Bit Rate Generation Register (i = 3, 4) (1, 2, 3) b7 b0 Symbol S3BRG S4BRG Address 036316 036716 After Reset Undefined Undefined Description Assuming that set value = n, BRGi divides the count source by n+1 NOTES: 1. Write to this register while serial I/O is neither transmitting or receiving. 2. Use MOV instruction to write to this register. 3. Set the SiBRG register after setting bits SMi1 and SMi0 in the SiC register. Setting Range 0016 to FF16 RW WO SI/Oi Transmit/Receive Register (i = 3, 4) (1, 2) b7 b0 Symbol S3TRR S4TRR Address 036016 036416 After Reset Undefined Undefined RW RW Description Transmission/reception starts by writing transmit data to this register. After transmission/reception completion, reception data can be read by reading this register. NOTES: 1. Write to this register while serial I/O is neither transmitting or receiving. 2. To receive data, set the corresponding port direction bit for SINi to 0 (input mode). Figure 14.36 S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 218 of 458 M16C/29 Group 14. Serial I/O Table 14.20 SI/O3 and SI/O4 Specifications Item Transfer data format Transfer clock Specification • Transfer data length: 8 bits • The SMi6 bit in the SiC (i=3, 4) register is set to 1 (internal clock) : fj/ (2(n+1)) fj = f1SIO, f2SIO, f8SIO, f32SIO. n=Setting value of SiBRG register • SMi6 bit is set to 0 (external clock) : Input from CLKi pin (1) Transmission/reception start condition Interrupt request generation timing 0016 to FF16. • Before transmission/reception can start, the following requirements must be met Write transmit data to the SiTRR register (2, 3) • When the SMi4 bit in the SiC register is set to 0 The rising edge of the last transfer clock pulse (4) • When SMi4 is set to 1 The falling edge of the last transfer clock pulse (4) CLKi pin fucntion SOUTi pin function SINi pin function Select function I/O port, transfer clock input, transfer clock output I/O port, transmit data output, high-impedance I/O port, receive data input • LSB first or MSB first selection Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can be selected • Function for setting an SOUTi initial value set function When the SMi6 bit in the SiC register is set to 0 (external clock), the SOUTi pin output level while not tranmitting can be selected. • CLK polarity selection Whether transmit data is output/input timing at the rising edge or falling edge of transfer clock can be selected. NOTE: 1. To set the SMi6 bit in the SiC register to 0 (external clock), follow the procedure described below. • If the SMi4 bit in the SiC register is set to 0, write transmit data to the SiTRR register while input on the CLKi pin is high. The same applies when rewriting the SMi7 bit in the SiC register. • If the SMi4 bit is set to 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same applies when rewriting the SMi7 bit. • Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the transfer clock 2. Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. Therefore, do not write the next transmit data to the SiTRR register during transmission. 3. When the SMi6 bit in the SiC register is set to 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state, with the data hold time thereby reduced. 4. When the SMi6 bit in the SiC register is set to 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit is set to 0, or stops in the low state if the SMi4 bit is set to 1. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 219 of 458 M16C/29 Group 14. Serial I/O 14.2.1 SI/Oi Operation Timing Figure 14.37 shows the SI/Oi operation timing 1.5 cycle (max) (3) SI/Oi internal clock CLKi output Signal written to the SiTRR register SOUTi output SINi input "H" "L" "H" "L" "H" "L" (2) "H" "L" "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 SiIC register IR bit i= 3, 4 1 0 NOTES: 1. This diagram applies to the case where the SiC register bits are set as follows: SMi2 = 0 (SOUTi output), SMi3 = 1 (SOUTi output, CLKi function), SMi4 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock), SMi5 = 0 (LSB first) and SMi6 = 1 (internal clock) 2. When the SMi6 bit is set to 0 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer is completed. 3. If the SMi6 bit is set to 0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the SiTRR register. Figure 14.37 SI/Oi Operation Timing 14.2.2 CLK Polarity Selection The the SMi4 bit in the SiC register allows selection of the polarity of the transfer clock. Figure 14.38 shows the polarity of the transfer clock. (1) When the SMi4 bit in the SiC register is set to 0 CLKi SINi SOUTi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 (2) (2) When the SMi4 bit in the SiC register is set to 1 CLKi SINi SOUTi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 (3) i=3 and 4 NOTES: 1. This diagram applies to the case where the SiC register bits are set as follows: SMi5 = 0 (LSB first) and SMi6 = 1 (internal clock) 2. When the SMi6 bit is set to 1 (internal clock), a high level is output from the CLKi pin if not transferring data. 3 When the SMi6 bit is set to 1 (internal clock), a low level is output from the CLKi pin if not transferring data. Figure 14.38 Polarity of Transfer Clock Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 220 of 458 M16C/29 Group 14. Serial I/O 14.2.3 Functions for Setting an SOUTi Initial Value If the SMi6 bit in SiC register is set to 0 (external clock), the SOUTi pin output level can be fixed high or low when not transferring data. However, when transmitting data consecutively, the last bit (bit 0) value of the last transmitted data is retained between the sccessive data transmissions. Figure 14.39 shows the timing chart for setting an SOUTi initial value and how to set it. (Example) When “H” selected for SOUTi initial value (1) Signal written to SiTRR register Setting of the initial value of S OUT i output and starting of transmission/ reception Set the SMi3 bit to 0 (SOUTi pin functions as an I/O port) SMi7 bit SMi3 bit Set the SMi7 bit to 1 (SOUT i initial value = “H”) D0 SOUTi (internal) SOUTi pin output (i = 3, 4) Port output D Initial value = “H” (3) 0 Set the SMi3 bit to 1 (SOUTi pin functions as S OUTi output) “H” level is output from the S OUT i pin Write to the SiTRR register Serial transmit/reception starts Setting the SOUTi initial value to “H” (2) Port selection switching (I/O port SOUTi) NOTES: 1. This diagram applies to the case where the bits in the SiC register are set as follows: SMi2 = 0 (SOUTi output), SMi5 = 0 (LSB first) and SMi6 = 0 (external clock) 2. SOUTi can only be initialized when input on the CLKi pin is in the high state if the SMi4bit in the SiC register is set to 0 (transmit data output at the falling edge of the transfer clock) or in the low state if the SMi4 bit is set to 1 (transmit data output at the rising edge of the transfer clock). 3. If the SMi6 bit is set to 1 (internal clock) or if the SMi2 bit is set to 1 (SOUTi output disabled), this output goes to the high-impedance state. Figure 14.39 SOUTi Initial Value Setting Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 221 of 458 M16C/29 Group 15. A/D Converter 15. A/D Converter Note Ports P04 to P07(AN04 to AN07), P10 to P13(AN20 to AN23) and P95 to P97(AN25 to AN27) are not available in 64-pin package. Do not use port P04 to P07(AN04 to AN07), P10 to P13(AN20 to AN23) and P95 to P97(AN25 to AN27) as analog input pins in 64-pin package. The MCU contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107 (AN0 to AN7), P00 to P07 (AN00 to AN07), and P10 to P13, P93, P95 to P97 (AN20 to AN27), and P90 to P92 (AN30 to AN32). ____________ Similarly, ADTRG input shares the pin with P15. Therefore, when using these inputs, make sure the corresponding port direction bits are set to 0 (input mode). When not using the A/D converter, set the VCUT bit to 0 (Vref unconnected), so that no current will flow from the Vref pin into the resistor ladder, helping to reduce the power consumption of the chip. The A/D conversion result is stored in the ADi register bits for ANi, AN0i, AN2i (i = 0 to 7), and AN3i pins (i = 0 to 2). Table 15.1 shows the A/D converter performance. Figure 15.1 shows the A/D converter block diagram and Figures 15.2 to 15.4 show the A/D converter associated with registers. Table 15.1 A/D Converter Performance Item Performance A/D Conversion Method Successive approximation (capacitive coupling amplifier) Analog Input Voltage (1) 0V to AVCC (VCC) Operating Clock φAD (2) fAD/divided-by-2 or fAD/divided-by-3 or fAD/divided-by-4 or fAD/divided-by-6 or fAD/divided-by-12 or fAD Resolution 8-bit or 10-bit (selectable) Integral Nonlinearity Error When AVCC = Vref = 5V • With 8-bit resolution: ±2LSB • With 10-bit resolution: ±3LSB When AVCC = Vref = 3.3V • With 8-bit resolution: ±2LSB • With 10-bit resolution: ±5LSB Operating Modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1 Analog Input Pins 8 pins (AN0 to AN7) + 8 pins (AN00 to AN07) + 8 pins (AN20 to AN27) + 3 pins (AN30 to AN32) (80-pin package) 8 pins (AN0 to AN7) + 4 pins (AN00 to AN03) + 1 pin (AN24) + 3 pins (AN30 to AN32) (64-pin package) • Without sample and hold function Conversion Speed Per Pin 8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles • With sample and hold function 8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles NOTES: 1. Not dependent on use of sample and hold function. 2. Set the φAD frequency to 10 MHz or less. Without sample-and-hold function, set the φAD frequency to 250kHZ or more. With the sample and hold function, set the φAD frequency to 1MHZ or more. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 222 of 458 M16C/29 Group 15. A/D Converter CKS2=0 A/D conversion rate selection 1/2 1/2 CKS0=1 CKS0=0 CKS1=1 CKS1=0 øAD fAD 1/3 CKS2=1 VREF AVSS VCUT=0 VCUT=1 Resistor ladder Successive conversion register ADCON1 register (address 03D716) ADCON0 register (address 03D616) Addresses (03C116 to 03C016) (03C316 to 03C216) (03C516 to 03C416) (03C716 to 03C616) (03C916 to 03C816) (03CB16 to 03CA16) (03CD16 to 03CC16) (03CF16 to 03CE16) A/D register 0(16) A/D register 1(16) A/D register 2(16) A/D register 3(16) A/D register 4(16) A/D register 5(16) A/D register 6(16) A/D register 7(16) Data bus high-order Data bus low-order Decoder for A/D register ADCON2 register (address 03D416) Vref Decoder for channel selection Port P10 group AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 CH2 to CH0 =0002 =0012 =0102 =0112 =1002 =1012 =1102 =1112 Comparator 0 VIN ADGSEL1 to ADGSEL0=002 Port P0 group AN00 AN01 AN02 AN03 (Note) AN04 AN05 AN06 AN07 Port P1/Port P9 group (Note) AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 Port P9 group AN30 AN31 AN32 CH2 to CH0 =0002 =0012 =0102 =0112 =1002 =1012 =1102 =1112 CH2 to CH0 =0002 =0012 =0102 =0112 =1002 =1012 =1102 =1112 CH2 to CH0 =0002 =0012 =0102 ADGSEL1 to ADGSEL0=102 SSE = 1 CH2 to CH0=0012 ADGSEL1 to ADGSEL0=112 ADGSEL1 to ADGSEL0=012 ADGSEL1 to ADGSEL0=002 VIN1 Comparator 1 ADGSEL1 to ADGSEL0=102 ADGSEL1 to ADGSEL0=112 ADGSEL1 to ADGSEL0=012 Note: AN04 to AN07, AN20 to AN23, and AN25 to AN27, is available for only 80-pin package. Figure 15.1 A/D Converter Block Diagram Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 223 of 458 M16C/29 Group 15. A/D Converter A/D Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 Address 03D6 16 Bit Name After Reset 00000XXX 2 Function RW RW Analog input pin select bit Function varies with each operation mode RW RW b4 b3 MD0 A/D operation mode select bit 0 MD1 0 0: One-shot mode or Delayed trigger mode 0,1 0 1: Repeat mode 1 0: Single sweep mode or Simultaneous sample sweep mode 1 1: Repeat sweep mode 0 or Repeat sweep mode 1 0: Software trigger 1: Hardware trigger 0: A/D conversion disabled 1: A/D conversion started See Table 15.2 RW RW TRG ADST CKS0 Trigger select bit A/D conversion start flag Frequency select bit 0 RW RW RW NOTE: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined. A/D Control Register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON1 Bit Symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT (b7-b6) Address 03D7 16 Bit Name After Reset 00 16 Function Function varies with each operation mode 0 : Other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode See Table 15.2 0 : Vref not connected 1 : Vref connected RW RW RW RW RW RW RW A/D sweep pin select bit A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect Bit (2) Nothing is assigned. If necessary, set to 0. When read, its content is 0 NOTES: 1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined. 2. If the VCUT bit is reset from 0 (VREF unconnected) to 1 (VREF connected), wait for 1 µs or more before starting A/D conversion. A/D Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol ADCON2 Bit Symbol SMP Address 03D416 Bit Name After Reset 0016 Function 0: Without sample and hold 1: With sample and hold b2 b1 RW RW RW RW RW RW RW A/D conversion method select bit ADGSEL0 ADGSEL1 (b3) CKS2 TRG1 (b7-b6) NOTS: 0 0: Select port P10 group A/D input group select bit 0 1: Select port P9 group 1 0: Select port P0 group 1 1: Select port P1/P9 group Reserved bit Frequency select bit 2 Set to 0 See Table 15.2 Function varies with each operation mode Trigger select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined. Figure 15.2 ADCON0 to ADCON2 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 224 of 458 M16C/29 Group 15. A/D Converter A/D Trigger Control Register b7 b6 b5 b4 b3 b2 b1 b0 (1, 2) Symbol Bit Symbol SSE ADTRGCON Address 03D216 0016 After Reset Function RW RW Bit Name A/D Operation Mode Select Bit 2 0 : Other than simultaneous sample sweep mode or delayed trigger mode 0,1 1 : Simultaneous sample sweep mode or delayed trigger mode 0,1 0 : Other than delayed trigger mode 0,1 1 : Delayed trigger mode 0,1 Function varies with each operation mode Function varies with each operation mode DTE HPTRG0 HPTRG1 (b7-b4) A/D Operation Mode Select Bit 3 AN0 Trigger Select Bit AN1 Trigger Select Bit RW RW RW Nothing is assigned. If necessary, set to 0. When read, its content is 0 NOTES: 1. If the ADTRGCON register is rewritten during A/D conversion, the conversion result will be undefined. 2. Set 00 16 in this register in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. Figure 15.3 ADTRGCON Register Table 15.2 A/D Conversion Frequency Select CKS2 0 0 0 0 1 1 1 1 CKS1 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 1 0 1 fAD divided by 4 fAD divided by 2 fAD fAD divided by 12 fAD divided by 6 fAD divided by 3 ØD A NOTE: 1. Ø D frequency must be under 10 MHz. Combination of the CKS0 bit in the A ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register selects Ø D. A Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 225 of 458 M16C/29 Group 15. A/D Converter A/D Conversion Status Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Bit Symbol ADERR0 ADSTAT0 Address 03D316 After reset 0016 Bit Name AN1 trigger status flag Function 0: AN1 trigger did not occur during AN0 conversion 1: AN1 trigger occured during AN0 conversion RW RW ADERR1 Conversion termination flag 0: Conversion not terminated 1: Conversion terminated by Timer B0 underflow Nothing is assigned. If necessary, set to 0. When read, its content is 0 Delayed trigger sweep status flag AN0 conversion status flag AN1 conversion status flag AN0 conversion completion status flag AN1 conversion completion status flag 0: Sweep not in progress 1: Sweep in progress 0: AN0 conversion not in progress 1: AN0 conversion in progress 0: AN1 conversion not in progress 1: AN1 conversion in progress 0: AN0 conversion not completed 1: AN0 conversion completed 0: AN1 conversion not completed 1: AN1 conversion completed RW (b2) ADTCSF ADSTT0 ADSTT1 ADSTRT0 ADSTRT1 RO RO RO RW RW NOTE: 1. ADSTAT0 register is valid only when the DTE bit in the ADTRGCON register is set to 1. A/D Register i (i=0 to 7) Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 (b15) b7 (b8) b0 b7 Address 03C1 16 to 03C0 16 03C3 16 to 03C2 16 03C5 16 to 03C4 16 03C7 16 to 03C6 16 03C9 16 to 03C8 16 03CB 16 to 03CA 16 03CD 16 to 03CC 16 03CF 16 to 03CE 16 b0 After Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Function RW When the BITS bit in the ADCON1 When the BITS bit in the ADCON1 RW register is 0 (8-bit mode) register is 1 (10-bit mode) Eight low-order bits of A/D conversion result Two high-order bits of A/D conversion result A/D conversion result When read, its content is undefined RO RO Nothing is assigned. If necessary, set to 0. When read, its content is 0 Figure 15.4 ADSTAT0 Register and AD0 to AD7 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 226 of 458 M16C/29 Group 15. A/D Converter Timer B2 special mode register (1) b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TB2SC Bit Symbol PWCON Address 039E16 Bit Name Timer B2 reload timing switch bit (2) Three-phase output port SD control bit 1 (3, 4, 7) After Reset X00000002 Function 0: Timer B2 underflow 1: Timer A output at odd-numbered 0: Three-phase output forcible cutoff by SD pin input (high impedance) disabled 1: Three-phase output forcible cutoff by SD pin input (high impedance) enabled 0: Other than A/D trigger mode (5) 1: A/D trigger mode 0: Other than A/D trigger mode (5) 1: A/D trigger mode RW RW IVPCR1 RW TB0EN TB1EN TB2SEL Timer B0 operation mode select bit Timer B1 operation mode select bit Trigger select bit (6) RW RW 0: TB2 interrupt RW 1: Underflow of TB2 interrupt generation frequency setting counter [ICTB2] Set to 0 RW (b6-b5) (b7) Reserved bits Nothing is assigned. If necessary, set to 0. When read, its content is 0 NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled). 2. If the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer B2 underflow). 3. When setting the IVPCR1 bit to 1 (three-phase output forcible cutoff by SD pin input enabled), Set the PD85 bit to 0 (= input mode). 4. Related pins are U(P80), U(P81), V(P72), V(P73), W(P74), W(P75). When a high-level ("H") signal is applied to the SD pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state. If a lowlevel (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0). At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1 bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those pins is used. 5. When this bit is used in delayed trigger mode 0, set bits TB0EN and TB1EN to 1 (A/D trigger mode). 6. When setting the TB2SEL bit to 1 (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), set the INV02 bit to 1 (three-phase motor control timer function). Figure 15.5 TB2SC Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 227 of 458 M16C/29 Group 15. A/D Converter 15.1 Operating Modes 15.1.1 One-Shot Mode In one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. Table 15.3 shows the one-shot mode specifications. Figure 15.6 shows the operation example in one-shot mode. Figure 15.7 shows registers ADCON0 to ADCON2 in one-shot mode. Table 15.3 One-shot Mode Specifications Specification Function Bits CH2 to CH0 in the ADCON0 register and registers ADGSEL1 and ADGSEL0 in the ADCON2 register select pins. Analog voltage applied to a selected pin is once converted to a digital code A/D Conversion Start • When the TRG bit in the ADCON0 register is 0 (software trigger) Condition Set the ADST bit in the ADCON0 register to 1 (A/D conversion started) • When the TRG bit in the ADCON0 register is 1 (hardware trigger) The ADTRG pin input changes state from “H” to “L” after setting the ADST bit to 1 (A/D conversion started) A/D Conversion Stop • A/D conversion completed (If a software trigger is selected, the ADST bit is Condition set to 0 (A/D conversion halted)). • Set the ADST bit to 0 Interrupt Request Generation Timing A/D conversion completed Analog Input Pin Select one pin from AN0 to AN7, AN00 to AN07, AN20 to AN27, AN30 to AN32 Readout of A/D Conversion Result Readout one of registers AD0 to AD7 that corresponds to the selected pin Item •Example when selecting AN2 to an analog input pin (Ch2 to CH0 = 0102) A/D conversion started AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D pin input voltage sampling A/D pin conversion A/D interrupt request generated Figure 15.6 Operation Example in One-Shot Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 228 of 458 M16C/29 Group 15. A/D Converter A/D Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D616 Bit Name After Reset 00000XXX 2 Function 0 0 0: Select AN 0 0 0 1: Select AN 1 0 1 0: Select AN 2 0 1 1: Select AN 3 1 0 0: Select AN 4 1 0 1: Select AN 5 1 1 0: Select AN 6 1 1 1: Select AN 7 0 0: One-shot mode or delayed trigger mode 0,1 0: Software trigger 1: Hardware trigger (AD TRG trigger) 0: A/D conversion disabled 1: A/D conversion started See Table 15.2 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW RW RW Analog input pin select bit (2, 3) A/D operation mode select bit 0 (3) Trigger select bit A/D conversion start flag Frequency select bit 0 NOTES: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined. 2. AN0 0 to AN0 7, AN20 to AN2 7, and AN3 0 to AN3 2 can be used in the same way as AN 0 to AN 7. Use bits ADGSEL1 and ADGSEL 0 in the ADCON2 register to select the desired pin. 3. After rewriting bits MD1 and MD0, set bits CH2 to CH0 over again using an another instruction. A/D Control Register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT (b7-b6) Address 03D7 16 Bit Name After Reset 00 16 Function Invalid in one-shot mode RW RW A/D Sweep Pin Select Bit RW A/D Operation Mode Select Bit 1 8/10-Bit Mode Select Bit Frequency Select Bit 1 Vref Connect Bit (2) 0 : Any mode other than repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode Refer to Table 15.2 1 : Vref connected RW RW RW RW Nothing is assigned. If necessary, set to 0. When read, the contents are 0 NOTES: 1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined. 2. If the VCUT bit is reset from 0 (Vref unconnected) to 1 (Vref connected), wait for 1 µs or more before starting A/D conversion. A/D Control Register 2 (1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol Bit Symbol SMP ADGSEL0 ADGSEL1 (b3) CKS2 ADCON2 Address 03D4 16 0016 After Reset Function 0: Without sample and hold 1: With sample and hold b2 b1 Bit Name A/D conversion method select bit A/D input group select bit RW RW RW RW RW RW 0 0: Select port P10 group 0 1: Select port P9 group 1 0: Select port P0 group 1 1: Select port P1/P9 group Set to 0 Reserved bit Frequency select bit 2 See Table 15.2 TRG1 (b7-b6) Trigger select bit 1 Set to 0 in one-shot mode RW Nothing is assigned. If necessary, set to 0. When read, the content is 0 NOTE: 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined. Figure 15.7 ADCON0 to ADCON2 Registers in One-Shot Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 229 of 458 M16C/29 Group 15. A/D Converter 15.1.2 Repeat mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 15.4 shows the repeat mode specifications. Figure 15.8 shows the operation example in repeat mode. Figure 15.9 shows the ADCON0 to ADCON2 registers in repeat mode. Table 15.4 Repeat Mode Specifications Item Specification Function Bits CH2 to CH0 in the ADCON0 register and the ADGSEL1 to ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to a selected pin is repeatedly converted to a digital code A/D Conversion Start • When the TRG bit in the ADCON0 register is 0 (software trigger) Condition Set the ADST bit in the ADCON0 register to 1 (A/D conversion started) • When the TRG bit in the ADCON0 register is 1 (hardware trigger) The ADTRG pin input changes state from “H” to “L” after setting the ADST bit to 1 (A/D conversion started) A/D Conversion Stop Condition Set the ADST bit to 0 (A/D conversion halted) Interrupt Request Generation Timing None generated Analog Input Pin Readout of A/D Conversion Result Select one pin from AN0 to AN7, AN00 to AN07, AN20 to AN27, and AN30 to AN32 Readout one of the AD0 to AD7 registers that corresponds to the selected pin •Example when selecting AN2 to an analog input pin (Ch2 to CH0 = 0102) A/D pin input voltage sampling A/D pin conversion A/D conversion started AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Figure 15.8 Operation Example in Repeat Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 230 of 458 M16C/29 Group 15. A/D Converter A/D Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 01 Symbol ADCON0 Bit Symbol CH0 Address 03D6 16 Bit Name After Reset 00000XXX 2 Function RW RW CH1 Analog input pin select bit(2, 3) CH2 MD0 MD1 TRG ADST CKS0 A/D operation mode select bit 0 (3) Trigger select bit A/D conversion start flag Frequency select bit 0 0 0 0: Select AN0 0 0 1: Select AN1 0 1 0: Select AN2 0 1 1: Select AN3 1 0 0: Select AN4 1 0 1: Select AN5 1 1 0: Select AN6 1 1 1: Select AN7 b4 b3 b2 b1 b0 RW RW RW RW RW RW RW 0 1: Repeat mode 0: Software trigger 1: Hardware trigger (ADTRG trigger) 0: A/D conversion disabled 1: A/D conversion started See Table 15.2 NOTES: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined. 2. AN00 to AN07, AN20 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. Use bits ADGSEL1 and ADGSEL 0 in the ADCON2 register to select the desired pin. 3. After rewriting bits MD1 and MD0, set bits CH2 to CH0 over again using an another instruction. A/D Control Register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT (b7-b6) Address 03D7 16 Bit Name After Reset 00 16 Function Invalid in repeat mode RW RW RW RW RW RW RW A/D sweep pin select bit A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit (2) 0: Other than repeat sweep mode 1 0: 8-bit mode 1: 10-bit mode See Table 15.2 1: Vref connected Nothing is assigned. If necessary, set to 0. When read, the content is 0 NOTES: 1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined. 2. If the VCUT bit is reset from 0 (Vref unconnected) to 1 (Vref connected), wait for 1 µs or more before starting A/D conversion. A/D Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol ADCON2 Bit Symbol SMP Address 03D416 Bit Name After Reset 0016 Function 0: Without sample and hold 1: With sample and hold b2 b1 RW RW RW RW RW RW RW A/D conversion method select bit ADGSEL0 ADGSEL1 (b3) CKS2 TRG1 (b7-b6) NOTE: 0 0: Select port P10 group A/D input group select bit 0 1: Select port P9 group 1 0: Select port P0 group 1 1: Select port P1/P9 group Reserved bit Frequency select bit 2 Set to 0 See Table 15.2 Set to 0 in one-shot mode Trigger select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined. Figure 15.9 ADCON0 to ADCON2 Registers in Repeat Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 231 of 458 M16C/29 Group 15. A/D Converter 15.1.3 Single Sweep Mode In single sweep mode, analog voltages applied to the selected pins are converted one-by-one to a digital code. Table 15.5 shows the single sweep mode specifications. Figure 15.10 shows the operation example in single sweep mode. Figure 15.11 shows the ADCON0 to ADCON2 registers in single sweep mode. Table 15.5 Single Sweep Mode Specifications Specification Function Bits SCAN1 to SCAN0 in the ADCON1 register and bits ADGSEL1 and ADGSEL0 in the ADCON2 register select pins. Analog voltage applied to the selected pins is converted one-by-one to a digital code A/D Conversion Start Condition • When the TRG bit in the ADCON0 register is 0 (software trigger) Set the ADST bit in the ADCON0 register to 1 (A/D conversion started) • When the TRG bit in the ADCON0 register is 1 (hardware trigger) The ADTRG pin input changes state from “H” to “L” after setting the ADST bit to 1 (A/D conversion started) A/D Conversion Stop Condition • A/D conversion completed(When selecting a software trigger, the ADST bit is set to 0 (A/D conversion halted)). • Set the ADST bit to 0 Interrupt Request Generation Timing A/D conversion completed Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to AN7 (8 pins) (1) Readout of A/D Conversion Result Readout one of registers AD0 to AD7 that corresponds to the selected pin NOTE: 1. AN00 to AN07, AN 2 to AN2 7, and AN30 to AN3 2 can be used in the same way as AN0 to AN7. 0 However, all input pins need to belong to the same group. Item •Example when selecting AN0 to AN3 to A/D sweep pins (SCAN1 to SCAN0 = 012) A/D conversion started A/D pin input voltage sampling A/D pin conversion AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Figure 15.10 Operation Example in Single Sweep Mode A/D interrupt request generated Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 232 of 458 M16C/29 Group 15. A/D Converter A/D Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D6 16 Bit Name After Reset 00000XXX 2 Function RW RW Analog input pin select bit Invalid in single sweep mode RW RW A/D operation mode select bit 0 Trigger select bit A/D conversion start flag Frequency select bit 0 b4 b3 1 0: Single sweep mode or Simultaneous sample sweep mode 0: Software trigger 1: Hardware trigger (ADTRG trigger) 0: A/D conversion disabled 1: A/D conversion started See Table 15.2 RW RW RW RW RW NOTE: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined. A/D Control Register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 Address 03D7 16 Bit Name After Reset 00 16 Function When single sweep mode is selected, 0 0: AN0 to AN1 (2 pins) 0 1: AN0 to AN3 (4 pins) 1 0: AN0 to AN5 (6 pins) 1 1: AN0 to AN7 (8 pins) 0: Other than repeat sweep mode 1 0: 8-bit mode 1: 10-bit mode See Table 15.2 1: Vref connected b1 b0 RW RW A/D sweep pin select bit SCAN1 MD2 BITS CKS1 VCUT (b7-b6) A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect Bit (3) (2) RW RW RW RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 0 NOTES: 1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined. 2. AN00 to AN07, AN20 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. Use bits ADGSEL1 and ADGSEL 0 in the ADCON2 register to select the desired pin. 3. If the VCUT bit is reset from 0 (Vref unconnected) to 1 (Vref connected), wait for 1 µs or more before starting A/D conversion. A/D Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol ADCON2 Bit Symbol SMP Address 03D416 Bit Name After Reset 0016 Function 0: Without sample and hold 1: With sample and hold b2 b1 RW RW RW RW RW RW RW A/D conversion method select bit ADGSEL0 ADGSEL1 (b3) CKS2 TRG1 (b7-b6) NOTE: 0 0: Select port P10 group A/D input group select bit 0 1: Select port P9 group 1 0: Select port P0 group 1 1: Select port P1/P9 group Reserved bit Frequency select bit 2 Set to 0 See Table 15.2 Set to 0 in single sweep mode Trigger select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined. Figure 15.11 ADCON0 to ADCON2 Registers in Single Sweep Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 233 of 458 M16C/29 Group 15. A/D Converter 15.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltages applied to the selected pins are repeatedly converted to a digital code. Table 15.6 shows the repeat sweep mode 0 specifications. Figure 15.12 shows the operation example in repeat sweep mode 0. Figure 15.13 shows the ADCON0 to ADCON2 registers in repeat sweep mode 0. Table 15.6 Repeat Sweep Mode 0 Specifications Specification Bits SCAN1 and SCAN0 in the ADCON1 register and bits ADGSEL1 and ADGSEL0 in the ADCON2 register select pins. Analog voltage applied to the selected pins is repeatedly converted to a digital code A/D Conversion Start Condition • When the TRG bit in the ADCON0 register is 0 (software trigger) Set the ADST bit in the ADCON0 register to 1 (A/D conversion started) • When the TRG bit in the ADCON0 register is 1 (Hardware trigger) The ADTRG pin input changes state from “H” to “L” after setting the ADST bit to 1 (A/D conversion started) A/D Conversion Stop Condition Set the ADST bit to 0 (A/D conversion halted) Interrupt Request Generation Timing None generated Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0 to AN7 (8 pins) (1) Readout of A/D Conversion Result Readout one of registers AD0 to AD7 that corresponds to the selected pin Function NOTES: 1. AN00 to AN0 7, AN 2 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. 0 However, all input pins need to belong to the same group. Item •Example when selecting AN0 to AN3 to A/D sweep pins (SCAN1 to SCAN0 = 012) A/D conversion started A/D pin input voltage sampling A/D pin conversion AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Figure 15.12 Operation Example in Repeat Sweep Mode 0 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 234 of 458 M16C/29 Group 15. A/D Converter A/D Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D6 16 Bit Name After Reset 00000XXX 2 Function RW RW Analog input pin select bit Invalid in repeat sweep mode 0 RW RW A/D operation mode select bit 0 Trigger select bit A/D conversion start flag Frequency select bit 0 b4 b3 1 1: Repeat sweep mode 0 or repeat sweep mode 1 0: Software trigger 1: Hardware trigger (ADTRG trigger) 0: A/D conversion disabled 1: A/D conversion started See Table 15.2 RW RW RW RW RW NOTE: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined. A/D Control Register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 Address 03D7 16 Bit Name After Reset 00 16 Function When repeat sweep mode 0 is selected, 0 0: AN0 to AN1 (2 pins) 0 1: AN0 to AN3 (4 pins) 1 0: AN0 to AN5 (6 pins) 1 1: AN0 to AN7 (8 pins) 0: Other than repeat sweep mode 1 0: 8-bit mode 1: 10-bit mode See Table 15.2 1: Vref connected b1 b0 RW RW A/D sweep pin select bit SCAN1 MD2 BITS CKS1 VCUT (b7-b6) A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect Bit (3) (2) RW RW RW RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 0 NOTES: 1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined. 2. AN00 to AN07, AN20 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. Use bits ADGSEL1 and ADGSEL 0 in the ADCON2 register to select the desired pin. 3. If the VCUT bit is reset from 0 (Vref unconnected) to 1 (Vref connected), wait for 1 µs or more before starting A/D conversion. A/D Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol ADCON2 Bit Symbol SMP Address 03D416 Bit Name After Reset 0016 Function 0: Without sample and hold 1: With sample and hold b2 b1 RW RW RW RW RW RW RW A/D conversion method select bit ADGSEL0 ADGSEL1 (b3) CKS2 TRG1 (b7-b6) NOTE: 0 0: Select port P10 group A/D input group select bit 0 1: Select port P9 group 1 0: Select port P0 group 1 1: Select port P1/P9 group Reserved bit Frequency select bit 2 Set to 0 See Table 15.2 Set to 0 in repeat sweep mode 0 Trigger select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined. Figure 15.13 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 0 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 235 of 458 M16C/29 Group 15. A/D Converter 15.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage is applied to the all selected pins are converted to a digital code, with mainly used in the selected pins. Table 15.7 shows the repeat sweep mode 1 specifications. Figure 15.14 shows the operation example in repeat sweep mode 1. Figure 15.15 shows registers ADCON0 to ADCON2 in repeat sweep mode 1. Table 15.7 Repeat Sweep Mode 1 Specifications Specification Bits SCAN1 and SCAN0 in the ADCON1 register and bits ADGSEL1 and ADGSEL0 in the ADCON2 register mainly select pins. Analog voltage applied to the all selected pins is repeatedly converted to a digital code Example : When selecting AN0 Analog voltage is converted to a digital code in the following order AN0 AN1 AN0 AN2 AN0 AN3, and so on. A/D Conversion Start Condition • When the TRG bit in the ADCON0 register is 0 (software trigger) Set the ADST bit in the ADCON0 register to 1 (A/D conversion started) • When the TRG bit in the ADCON0 register is 1 (hardware trigger) The ADTRG pin input changes state from “H” to “L” after setting the ADST bit Function to 1 (A/D conversion started) A/D Conversion Stop Condition Set the ADST bit to 0 (A/D conversion halted) Interrupt Request Generation Timing None generated Analog Input Pins Mainly Select from AN0 (1 pins), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to Used in A/D Conversions AN3 (4 pins) (1) Readout of A/D Conversion Result Readout one of registers AD0 to AD7 that corresponds to the selected pin NOTES: 1. AN00 to AN07, AN 2 to AN2 7, and AN30 to AN3 2 can be used in the same way as AN0 to AN7. 0 However, all input pins need to belong to the same group. Item •Example when selecting AN0 to A/D sweep pins (SCAN1 to SCAN0 = 002) A/D pin input voltage sampling A/D pin conversion A/D conversion started AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Figure 15.14 Operation Example in Repeat Sweep Mode 1 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 236 of 458 M16C/29 Group 15. A/D Converter A/D Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D6 16 Bit Name After Reset 00000XXX 2 Function RW RW Analog input pin select bit Invalid in repeat sweep mode 1 RW RW A/D operation mode select bit 0 Trigger select bit A/D conversion start flag Frequency select bit 0 b4 b3 1 1: Repeat sweep mode 0 or repeat sweep mode 1 0: Software trigger 1: Hardware trigger (ADTRG trigger) 0: A/D conversion disabled 1: A/D conversion started See Table 15.2 RW RW RW RW RW NOTE: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined. A/D Control Register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 Address 03D7 16 Bit Name After Reset 00 16 Function When repeat sweep mode 0 is selected, 0 0: AN0 (1 pin) 0 1: AN0 to AN1 (2 pins) 1 0: AN0 to AN2 (3 pins) 1 1: AN0 to AN3 (4 pins) 1: Repeat sweep mode 1 0: 8-bit mode 1: 10-bit mode See Table 15.2 1: Vref connected b1 b0 RW RW A/D sweep pin select bit (2) SCAN1 MD2 BITS CKS1 VCUT (b7-b6) A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect Bit (3) RW RW RW RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 0 NOTES: 1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined. 2. AN00 to AN07, AN20 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. Use bits ADGSEL1 and ADGSEL 0 in the ADCON2 register to select the desired pin. 3. If the VCUT bit is reset from 0 (Vref unconnected) to 1 (Vref connected), wait for 1 µs or more before starting A/D conversion. A/D Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol ADCON2 Bit Symbol SMP Address 03D416 Bit Name After Reset 0016 Function 0: Without sample and hold 1: With sample and hold b2 b1 RW RW RW RW RW RW RW A/D conversion method select bit ADGSEL0 ADGSEL1 (b3) CKS2 TRG1 (b7-b6) NOTE: 0 0: Select port P10 group A/D input group select bit 0 1: Select port P9 group 1 0: Select port P0 group 1 1: Select port P1/P9 group Reserved bit Frequency select bit 2 Set to 0 See Table 15.2 Set to 0 in repeat sweep mode 1 Trigger select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined. Figure 15.15 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 1 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 237 of 458 M16C/29 Group 15. A/D Converter 15.1.6 Simultaneous Sample Sweep Mode In simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-byone to a digital code. The input voltages of AN0 and AN1 are sampled simultaneously using two circuits of sample and hold circuit. Table 15.8 shows the simultaneous sample sweep mode specifications. Figure 15.16 shows the operation example in simultaneous sample sweep mode. Figure 15.17 shows registers ADCON0 to ADCON2 and Figure 15.18 shows ADTRGCON registers in simultaneous sample sweep mode. Table 15.9 shows the trigger select bit setting in simultaneous sample sweep mode. In simultaneous sample sweep mode, Timer B0 underflow can be selected as a trigger by combining soft___________ ware trigger, ADTRG trigger, Timer B2 underflow, Timer B2 interrupt generation frequency setting counter underflow or A/D trigger mode of Timer B. Table 15.8 Simultaneous Sample Sweep Mode Specifications Item Specification Function Bits SCAN1 and SCAN0 in the ADCON1 register and bits ADGSEL1 and ADGSEL0 in the ADCON2 register select pins. Analog voltage applied to the selected pins is converted one-by-one to a digital code. At this time, the input voltage of AN0 and AN1 are sampled simultaneously. A/D Conversion Start Condition When the TRG bit in the ADCON0 register is 0 (software trigger) Set the ADST bit in the ADCON0 register to 1 (A/D conversion started) When the TRG bit in the ADCON0 register is 1 (hardware trigger) The trigger is selected by bits TRG1 and HPTRG0 (See Table 15.9) The ADTRG pin input changes state from “H” to “L” after setting the ADST bit to 1 (A/D conversion started) Timer B0, B2 or Timer B2 interrupt generation frequency setting counter underflow after setting the ADST bit to 1 (A/D conversion started) A/D Conversion Stop Condition A/D conversion completed (If selecting software trigger, the ADST bit is automatically set to 0 ). Set the ADST bit to 0 (A/D conversion halted) Interrupt Generation Timing A/D conversion completed Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) (1) Readout of A/D conversion result Readout one of registers AN0 to AN7 that corresponds to the selected pin pins need to belong to the same group. NOTE: 0 1. AN00 to AN07, AN 2 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input •Example when selecting AN0 to AN3 to A/D pins for sweep (SCAN1 to SCAN0 = 012) A/D pin input voltage sampling A/D pin conversion A/D conversion started AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D interrupt request generated Figure 15.16 Operation Example in Simultaneous Sample Sweep Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 238 of 458 M16C/29 Group 15. A/D Converter A/D Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D6 16 Bit Name After Reset 00000XXX 2 Function RW RW Analog input pin select bit Invalid in repeat sweep mode 0 RW RW A/D operation mode select bit 0 Trigger select bit A/D conversion start flag Frequency select bit 0 b4 b3 1 0: Single sweep mode or simultaneous sample sweep mode See Table 15.9 0: A/D conversion disabled 1: A/D conversion started See Table 15.2 RW RW RW RW RW NOTE: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined. A/D Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 Address 03D7 16 Bit Name After Reset 00 16 Function When simultaneous sample sweep mode is selected, RW RW A/D sweep pin select bit (2) 0 0: AN0 to AN1 (2 pins) SCAN1 MD2 BITS CKS1 VCUT (b7-b6) A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect Bit (3) b1 b0 0 1: AN0 to AN3 (4 pins) 1 0: AN0 to AN5 (6 pins) 1 1: AN0 to AN7 (8 pins) 0: Other than repeat sweep mode 1 0: 8-bit mode 1: 10-bit mode See Table 15.2 RW RW RW RW RW 1: Vref connected Nothing is assigned. If necessary, set to 0. When read, the content is 0 NOTES: 1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined. 2. AN00 to AN07, AN20 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. Use bits ADGSEL1 and ADGSEL 0 in the ADCON2 register to select the desired pin. 3. If the VCUT bit is reset from 0 (Vref unconnected) to 1 (Vref connected), wait for 1 µs or more before starting A/D conversion. A/D Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 0 1 Symbol ADCON2 Bit Symbol SMP Address 03D416 Bit Name After Reset 0016 Function Set to 1 in simultaneous sample sweep mode b2 b1 RW RW RW RW RW RW RW A/D conversion method select bit ADGSEL0 ADGSEL1 (b3) CKS2 TRG1 (b7-b6) NOTE: 0 0: Select port P10 group A/D input group select bit 0 1: Select port P9 group 1 0: Select port P0 group 1 1: Select port P1/P9 group Reserved bit Frequency select bit 2 Set to 0 See Table 15.2 See Table 15.9 Trigger select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined. Figure 15.17 ADCON0 to ADCON2 Registers in Simultaneous Sample Sweep Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 239 of 458 M16C/29 Group 15. A/D Converter A/D Trigger Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 0 11 Symbol ADTRGCON Bit Symbol SSE Address 03D216 Bit Name After Reset 0016 Function RW RW RW RW RW A/D operation mode select 1: Simultaneous sample sweep mode or delayed trigger mode 0, 1 bit 2 A/D operation mode select 0: Other than delayed trigger mode 0, 1 bit 3 AN0 trigger select bit AN1 trigger select bit See Table 15.9 Set to 0 in simultaneous sample sweep mode DTE HPTRG0 HPTRG1 (b7-b4) NOTE: Nothing is assigned. If necessary, set to 0. When read, the content is 0 1. If ADTRGCON is rewritten during A/D conversion, the conversion result will be undefined. Figure 15.18 ADTRGCON Register in Simultaneous Sample Sweep Mode Table 15.9 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode TRG 0 1 1 1 TRG1 0 1 HPTRG0 1 0 0 TRIGGER Software trigger Timer B0 underflow (1) ADTRG Timer B2 or Timer B2 interrupt generation frequency setting counter underflow (2) NOTES: 1. A count can be started for Timer B2, Timer B2 interrupt generation frequency setting counter underflow or the INT5 pin falling edge as count start conditions of Timer B0. 2. Select Timer B2 or Timer B2 interrupt generation frequency setting counter using the TB2SEL bit in the TB2SC register. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 240 of 458 M16C/29 Group 15. A/D Converter 15.1.7 Delayed Trigger Mode 0 In delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a digital code. The delayed trigger mode 0 used in combination with A/D trigger mode of Timer B. The Timer B0 underflow starts a single sweep conversion. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted until the Timer B1 underflow is generated. When the Timer B1 underflow is generated, the single sweep conversion is restarted with the AN1 pin. Table 15.10 shows the delayed trigger mode 0 specifications. Figure 15.19 shows the operation example in delayed trigger mode 0. Figures 15.20 and 15.21 show each flag operation in the ADSTAT0 register that corresponds to the operation example. Figure 15.22 shows registers ADCON0 to ADCON2 in delayed trigger mode 0. Figure 15.23 shows the ADTRGCON register in delayed trigger mode 0 and Table 15.11 shows the trigger select bit setting in delayed trigger mode 0. Table 15.10 Delayed Trigger Mode 0 Specifications Item Specification Function Bits SCAN1 and SCAN0 in the ADCON1 register and bits ADGSEL1 and ADGSEL0 in the ADCON2 register select pins. Analog voltage applied to the input voltage of the selected pins are converted one-by-one to the digital code. At this time, timer B0 underflow generation starts AN0 pin conversion. Timer B1 underflow generation starts conversion after the AN1 pin. (1) A/D Conversion Start AN0 pin conversion start condition •When Timer B0 underflow is generated if Timer B0 underflow is generated again before Timer B1 underflow is generated , the conversion is not affected •When Timer B0 underflow is generated during A/D conversion of pins after the AN1 pin, conversion is halted and the sweep is restarted from the AN0 pin again AN1 pin conversion start condition •When Timer B1 underflow is generated during A/D conversion of the AN0 pin, the input voltage of the AN1 pin is sampled. The AN1 conversion and the rest of the sweep start when AN0 conversion is completed. A/D Conversion Stop Condition Interrupt request generation timing Analog input pin Readout of A/D conversion result NOTES: 1. Set the larger value than the value of the timer B0 register to the timer B1 register. The count source for timer B0 and timer B1 must be the same. 2. Do not write 1 (A/D conversion started) to the ADST bit in delayed trigger mode 0. When write 1, unexpected interrupts may be generated. 3. AN00 to AN07, AN 2 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input 0 pins need to belong to the same group. •When single sweep conversion from the AN0 pin is completed •Set the ADST bit to 0 (A/D conversion halted)(2) A/D conversion completed Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) and AN0 to AN7 (8 pins)(3) Readout one of registers AN0 to AN7 that corresponds to the selected pins Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 241 of 458 M16C/29 Group 15. A/D Converter •Example when selecting AN0 to AN3 to A/D sweep pins (SCAN1 to SCAN0 = 012) •Example 1: When Timer B1 underflow is generated during AN0 pin conversion Timer B0 underflow Timer B1 underflow A/D pin input voltage sampling A/D pin conversion AN0 AN1 AN2 AN3 •Example 2: When Timer B1 underflow is generated after AN0 pin conversion Timer B0 underflow Timer B1 underflow AN0 AN1 AN2 AN3 •Example 3: When Timer B0 underflow is generated during A/D conversion of any pins except AN0 pin Timer B0 underflow Timer B0 underflow (Abort othrt pins conversion) Timer B1 underflow Timer B1 under flow AN0 AN1 AN2 AN3 •Example 4: When Timer B0 underflow is generated again before Timer B1 underflow is generated after Timer B0 underflow generation Timer B0 underflow Timrt B0 underflow (An interrupt does not affect A/D conversion) Timer B1 underflow AN0 AN1 AN2 AN3 Figure 15.19 Operation Example in Delayed Trigger Mode 0 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 242 of 458 M16C/29 Group 15. A/D Converter •Example when selecting AN0 to AN3 to A/D sweep pins (SCAN1 to SCAN0 = 012) •Example 1: When Timer B1 underflow is generated during AN0 pin conversion Timer B0 underflow Timer B1 underflow A/D pin input voltage sampling A/D pin conversion AN0 AN1 AN2 AN3 ADST flag ADERR0 flag ADERR1 flag ADTCSF flag ADSTT0 flag ADSTT1 flag ADSTRT0 flag ADSTRT1 flag IR bit in the ADIC register 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Set to 0 by an interrupt request acknowledgement or a program Set to 0 by program Do not set to 1 by program •Example 2: When Timer B1 underflow is generated after AN0 pin conversion Timer B0 underflow Timer B1 underflow AN0 AN1 AN2 AN3 ADST flag ADERR0 flag ADERR1 flag ADTCSF flag ADSTT0 flag ADSTT1 flag ADSTRT0 flag ADSTRT1 flag IR bit in the ADIC register 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Set to 0 by an interrupt request acknowledgement or a program Set to 0 by program Do not set to 1 by program ADST flag: Bit 6 in the ADCON0 register ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register Figure 15.20 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example in Delayed Trigger Mode 0 (1) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 243 of 458 M16C/29 Group 15. A/D Converter •Example 3: When Timer B0 underflow is generated during A/D pin conversion of any pins except AN0 pin Timer B0 underflow Timer B1 underflow Timer B0 underflow (Abort othrt pins conversion ) Timer B1 underflow A/D pin input voltage sampling A/D pin conversion AN0 AN1 AN2 AN3 ADST flag ADERR0 flag ADERR1 flag ADTCSF flag ADSTT0 flag ADSTT1 flag ADSTRT0 flag ADSTRT1 flag 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Set to 0 by program Do not set to 1 by program IR bit in the ADIC1 register 0 Set to 0 by interrupt request acknowledgement or a program ADST flag: Bit 6 in the ADCON0 register ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register •Example 4: After Timer B0 underflow is generated and when Timer B0 underflow is generated again before Timer B1 underflow is genetaed Timer B0 underflow Timrt B0 underflow (An interrupt does not affect A/D conversion) Timer B1 underflow A/D pin input voltage sampling A/D pin conversion AN0 AN1 AN2 AN3 ADST flag ADERR0 flag ADERR1 flag ADTCSF flag ADSTT0 flag ADSTT1 flag ADSTRT0 flag ADSTRT1 flag IR bit in the ADIC register 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Set to 0 by interrupt request acknowledgement or a program Set to 0 by program Do not set to 1 by program ADST flag: Bit 6 in the ADCON0 register ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register Figure 15.21 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example in Delayed Trigger Mode 0 (2) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 244 of 458 M16C/29 Group 15. A/D Converter A/D Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 000111 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D6 16 Bit Name After Reset 00000XXX 2 Function b2 b1 b0 RW RW RW RW Analog input pin select bit 1 1 1: Set to 111b in delayed trigger mode 0 A/D operation mode select bit 0 Trigger select bit A/D conversion start flag (2) 0 0: One-shot mode or delayed trigger mode 0,1 Refer to Table 15.11 0: A/D conversion disabled 1: A/D conversion started Refer to Table 15.2 b4 b3 RW RW RW RW RW Frequency select bit 0 NOTES: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined. 2. Do not write 1 in delayed trigger mode 0. When write, set to 0. A/D Control Register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT (b7-b6) Address 03D716 Bit Name After Reset 0016 Function When selecting delayed trigger sweep mode 0 b1 b0 RW RW A/D sweep pin select bit (2) 0 0: AN 0 to AN 1 (2 pins) 0 1: AN 0 to AN 3 (4 pins) 1 0: AN 0 to AN 5 (6 pins) 1 1: AN 0 to AN 7 (8 pins) 0: Any mode other than repeat sweep mode 1 RW RW RW RW RW A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit (3) 0: 8-bit mode 1: 10-bit mode Refer to Table 15.2 1: Vref connected Nothing is assigned. If necessary, set to 0. When read, its content is 0 NOTES: 1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined. 2. AN0 0 to AN0 7, AN2 0 to AN2 7, and AN3 0 to AN3 2 can be used in the same way as AN 0 to AN 7. Use bits ADGSEL1 and ADGSEL0 in the ADCON2 register to select the desired pin. 3. If the VCUT bit is reset from 0 (Vref unconnected) to 1 (Vref connected), wait for 1 µs or more before starting A/D conversion. A/D Control Register 2 (1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 ADCON2 Symbol 03D416 Address Bit Name After Reset 0016 Bit Symbol SMP ADGSEL0 ADGSEL1 (b3) CKS2 Function 1: With sample and hold b2 b1 RW RW RW RW RW RW A/D conversion method select bit (2) A/D input group select bit 0 0: Select port P10 group 0 1: Select port P9 group 1 0: Select port P0 group 1 1: Select port P1/P9 group Set to 0 Reserved bit Frequency select bit 2 Refer to Table 15.2 TRG1 (b7-b6) Trigger select bit 1 Refer to Table 15.11 RW Nothing is assigned. If necessary, set to 0. When read, its content is 0 NOTES: 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined. 2. Set to 1 in delayed trigger mode 0. Figure 15.22 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 0 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 245 of 458 M16C/29 Group 15. A/D Converter A/D Trigger Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 1111 Symbol ADTRGCON Bit Symbol SSE Address 03D216 Bit Name After Reset 0016 Function RW RW RW RW RW A/D operation mode select Simultaneous sample sweep mode or bit 2 delayed trigger mode 0, 1 A/D operation mode select bit 3 AN0 trigger select bit AN1 trigger select bit Delayed trigger mode 0, 1 See Table 15.11 See Table 15.11 DTE HPTRG0 HPTRG1 (b7-b4) NOTE: Nothing is assigned. If necessary, set to 0. When read, the content is 0 1. If ADTRGCON is rewritten during A/D conversion, the conversion result will be undefined. Figure 15.23 ADTRGCON Register in Delayed Trigger Mode 0 Table 15.11 Trigger Select Bit Setting in Delayed Trigger Mode 0 TRG 0 TRG1 0 HPTRG0 1 HPTRG1 1 Trigger Timer B0, B1 underflow Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 246 of 458 M16C/29 Group 15. A/D Converter 15.1.8 Delayed Trigger Mode 1 In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a ___________ digital code. When the input of the ADTRG pin (falling edge) changes state from “H” to “L”, a single sweep conversion is started. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted ___________ until the second ADTRG pin falling edge is generated. When the second ADTRG falling edge is generated, the single sweep conversion of the pins after the AN1 pin is restarted. Table 15.12 shows the delayed trigger mode 1 specifications. Figure 15.24 shows the operation example of delayed trigger mode 1. Figure 15.25 and 15.26 show each flag operation in the ADSTAT0 register that corresponds to the operation example. Figure 15.27 shows registers ADCON0 to ADCON2 in delayed trigger mode 1. Figure 15.28 shows the ADTRGCON register in delayed trigger mode 1. Table 15.13 shows the trigger select bit setting in delayed trigger mode 1. Table 15.12 Delayed Trigger Mode 1 Specifications Item Function Specification Bits SCAN1 and SCAN0 in the ADCON1 register and bits ADGSEL1 and ADGSEL0 in the ADCON2 register select pins. Analog voltages applied to the selected pins are converted one-by-one to a digital code. At this time, the ADTRG pin falling edge starts AN0 pin conversion and the second ADTRG pin falling edge starts conversion of the pins after AN1 pin ___________ ___________ A/D Conversion Start Condition AN0 pin conversion start condition ___________ The ADTRG pin input changes state from “H” to “L” (falling edge) (1) AN1 pin conversion start condition (2) ___________ The ADTRG pin input changes state from “H” to “L” (falling edge) •When the second ADTRG pin falling edge is generated during A/D conversion of ___________ the AN0 pin, input voltage of AN1 pin is sampled or after at the time of ADTRG falling edge. The conversion of AN1 and the rest of the sweep starts when AN0 conversion is completed. •When the ADTRG pin falling edge is generated again during single sweep conversion of pins after the AN1 pin, the conversion is not affected ___________ ___________ A/D Conversion Stop Condition Interrupt Request Generation Timing •A/D conversion completed •Set the ADST bit to 0 (A/D conversion halted) (3) Single sweep conversion completed Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) and AN0 to AN7 (8 pins) (4) Readout of A/D Conversion Result Readout one of registers AN0 to AN7 that corresponds to the selected pins NOTES: ___________ 1. Do not generate the next ADTRG pin falling edge after the AN1 pin conversion is started until all selected pins complete A/D conversion. When an ADTRG pin falling edge is generated again during A/D conversion, its trigger ___________ is ignored. The falling edge of ADTRG pin, which was input after all selected pins complete A/D conversion, is considered to be the next AN0 pin conversion start condition. ___________ ___________ 2. The ADTRG pin falling edge is detected synchronized with the operation clock fAD. Therefore, when the ADTRG pin falling edge is generated in shorter periods than fAD, the second ADTRG pin falling edge may not be detected. Do ___________ not generate the ADTRG pin falling edge in shorter periods than fAD. 3. Do not write 1 (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write 1,unexpected interrupts may be generated. 0 4. AN00 to AN07, AN 2 to AN27, and AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to the same group. ___________ ___________ Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 247 of 458 M16C/29 Group 15. A/D Converter •Example when selecting AN0 to AN3 to A/D sweep pins (SCAN1 to SCAN0 = 012) •Example 1: When ADTRG pin falling edge is generated during AN0 pin conversion A/D pin input voltage sampling A/D pin conversion ADTRG pin input AN0 AN1 AN2 AN3 •Example 2: When ADTRG pin falling edge is generated again after AN0 pin conversion ADTRG pin input AN0 AN1 AN2 AN3 •Example 3: When ADTRG pin falling edge is generated more than two times after AN0 pin conversion ADTRG pin input (valid after single sweep conversion) AN0 AN1 AN2 AN3 (invalid) Figure 15.24 Operation Example in Delayed Trigger Mode1 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 248 of 458 M16C/29 Group 15. A/D Converter •Example when selecting AN0 to AN3 to A/D sweep pins (SCAN1 to SCAN0 = 012) •Example 1: When ADTRG pin falling edge is generated during AN0 pin conversion A/D pin input voltage sampling A/D pin conversion ADTRG pin input AN0 AN1 AN2 AN3 ADST flag ADERR0 flag ADERR1 flag ADTCSF flag ADSTT0 flag ADSTT1 flag ADSTRT0 flag ADSTRT1 flag 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Set to 0 by program Do not set to 1 by program IR bit in the ADIC 1 register 0 Set to 0 by interrupt request acknowledgement or a program •Example 2: When ADTRG pin falling edge is generated again after AN0 pin conversion ADTRG pin input AN0 AN1 AN2 AN3 ADST flag ADERR0 flag ADERR1 flag ADTCSF flag ADSTT0 flag ADSTT1 flag ADSTRT0 flag ADSTRT1 flag IR bit in the ADIC register 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Set to 0 by interrupt request acknowledgment or a program Set to 0 by program Do not set to 1 by program ADST flag: Bit 6 in the ADCON0 register ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register Figure 15.25 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example in Delayed Trigger Mode 1 (1) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 249 of 458 M16C/29 Group 15. A/D Converter •Example 3: When ADTRG input falling edge is generated more than two times after AN0 pin conversion A/D pin input voltage sampling A/D pin conversion ADTRG pin input (valid after single sweep conversion) AN0 AN1 AN2 AN3 ADST flag ADERR0 flag ADERR1 flag ADTCSF flag ADSTT0 flag ADSTT1 flag ADSTRT0 flag ADSTRT1 flag IR bit in the ADIC register 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Do not set to 1 by program (invalid) Set to 0 by program Set to 0 when interrupt request acknowledgement or a program ADST flag: Bit 6 in the ADCON0 register ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register Figure 15.26 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example in Delayed Trigger Mode 1 (2) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 250 of 458 M16C/29 Group 15. A/D Converter A/D Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 000111 Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D616 Bit Name After Reset 00000XXX 2 Function b2 b1 b0 RW RW RW RW Analog input pin select bit 1 1 1: Set to 111b in delayed trigger mode 1 A/D operation mode select bit 0 Trigger select bit A/D conversion start flag (2) 0 0 : One-shot mode or delayed trigger mode 0,1 Refer to Table 15.13 0 : A/D conversion disabled 1 : A/D conversion started Refer to Table 15.2 b4 b3 RW RW RW RW RW Frequency select bit 0 NOTES: 1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be undefined. 2. Do not write 1 in delayed trigger mode 1. If necessary, set to 0. A/D Control Register 1 (1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit Symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT (b7-b6) Address 03D716 Bit Name After Reset 0016 Function When selecting delayed trigger mode 1 b1 b0 RW RW A/D sweep pin select bit (2) 0 0: AN 0 to AN 1 (2 pins) 0 1: AN 0 to AN 3 (4 pins) 1 0: AN 0 to AN 5 (6 pins) 1 1: AN 0 to AN 7 (8 pins) 0: Any mode other than repeat sweep mode 1 RW RW RW RW RW A/D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit (3) 0: 8-bit mode 1: 10-bit mode Refer to Table 15.2 1: Vref connected Nothing is assigned. If necessary, set to 0. When read, the content is undefined NOTES: 1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be undefined. 2. AN0 0 to AN0 7, AN20 to AN2 7, and AN3 0 to AN3 2 can be used in the same way as AN 0 to AN 7. Use bits ADGSEL1 and ADGSET0 in the ADCON2 register to select the desired pin. 3. If the VCUT bit is reset from 0 (Vref unconnected) to 1 (Vref connected), wait for 1 µs or more before starting A/D conversion. A/D Control Register 2 (1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 Symbol Bit Symbol SMP ADGSEL0 ADGSEL1 (b3) CKS2 ADCON2 03D4 16 Address 0016 After Reset Function RW RW RW RW RW RW Bit Name A/D conversion method select bit (2) A/D input group select bit 1: With sample and hold b2 b1 0 0: Select port P10 group 0 1: Select port P9 group 1 0: Select port P0 group 1 1: Select port P1/P9 group Reserved bit Frequency select bit 2 Set to 0 Refer to Table 15.2 TRG1 (b7-b6) Trigger select bit 1 Refer to Table 15.13 RW Nothing is assigned. If necessary, set to 0. When read, the content is 0 NOTES: 1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be undefined. 2. Set to 1 in delayed trigger mode 1. Figure 15.27 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 1 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 251 of 458 M16C/29 Group 15. A/D Converter A/D Trigger Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 0011 Symbol ADTRGCON Bit Symbol SSE Address 03D216 Bit Name After Reset 0016 Function RW RW RW RW RW A/D operation mode select Simultaneous sample sweep mode or delayed trigger mode 0, 1 bit 2 A/D operation mode select bit 3 AN0 trigger select bit AN1 trigger select bit Delayed trigger mode 0, 1 See Table 15.13 See Table 15.13 DTE HPTRG0 HPTRG1 (b7-b4) NOTE: Nothing is assigned. If necessary, set to 0. When read, the content is 0 1. If ADTRGCON is rewritten during A/D conversion, the conversion result will be undefined. Figure 15.28 ADTRGCON Register in Delayed Trigger Mode 1 Table 15.13 Trigger Select Bit Setting in Delayed Trigger Mode 1 TRG 0 TRG1 1 HPTRG0 0 HPTRG1 0 ADTRG Trigger Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 252 of 458 M16C/29 Group 15. A/D Converter 15.2 Resolution Select Function The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to 1 (10-bit precision), the A/D conversion result is stored into bits 0 to 9 in the ADi register (i=0 to 7). When the BITS bit is set to 0 (8-bit precision), the A/D conversion result is stored into bits 7 to 0 in the ADi register. 15.3 Sample and Hold When the SMP bit in the ADCON 2 register is set to 1 (with the sample and hold function), A/D conversion rate per pin increases to 28 φAD cycles for 8-bit resolution or 33 φAD cycles for 10-bit resolution. The sample and hold function is available in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat sweep mode 1. In these modes, start A/D conversion after selecting whether the sample and hold circuit is to be used or not. In simultaneous sample sweep mode, delayed trigger mode 0 or delayed trigger mode, set to use the Sample and Hold function before starting A/D conversion. 15.4 Power Consumption Reducing Function When the A/D converter is not used, the VCUT bit in the ADCON1 register isolates the resistor ladder of the A/D converter from the reference voltage input pin (VREF). Power consumption is reduced by shutting off any current flow into the resistor ladder from the VREF pin. When using the A/D converter, set the VCUT bit to 1 (Vref connected) before setting the ADST bit in the ADCON0 register to 1 (A/D conversion started). Do not set the ADST bit and VCUT bit to 1 simultaneously, nor set the VCUT bit to 0 (Vref unconnected) during A/D conversion. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 253 of 458 M16C/29 Group 15. A/D Converter 15.5 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 15.29 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor equivalent circuit be R0, MCU’s internal resistance be R, precision (error) of the A/D converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8bit mode). VC is generally VC = VIN{1-e And when t = T, VC=VINe 1 c(R0+R) 1 c(R0+R) t } X Y ) X Y T VIN=VIN(1X Y = Hence, 1 X T = ln Y C(R0+R) T R0 = -R C•ln X Y Figure 15.29 shows analog input pin and externalsensor equivalent circuit. When the difference between VIN and VC becomes 0.1 LSB, we find impedance R0 when voltage between pins. VC changes from 0 to VIN-(0.1/1024) VIN in timer T. (0.1/1024) means that A/D precision drop due to insufficient capacitor chage is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(XIN) = 10MHz, T=0.3µs in the A/D conversion mode with sample & hold. Output inpedance R0 for sufficiently charging capacitor C within time T is determined as follows. T = 0.3µs, R = 7.8kΩ, C = 1.5pF, X = 0.1, and Y = 1024. Hence, R0 = 0.3X10-6 0.1 1.5X10-12•ln 1024 - 7.8 X 103 ≅ 13.9 X 103 Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A/D converter turns out of be approximately 13.9kΩ. MCU Sensor equivalent circuit R0 VIN R (7.8kΩ) (1) C (1.5pF) VC (1) Sampling time 3 Sample-and-hold function enabled: φAD Sample-and-hold function disabled: 2 φAD NOTE: 1. Reference value Figure 15.29 Analog Input Pin and External Sensor Equivalent Circuit page 254 of 458 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16. Multi-master I2C bus Interface The multi-master I2C bus interface is a serial communication circuit based on Philips I2C bus data transfer format, equipped with arbitration lost detection and synchronous functions. Figure 16.1 shows a block diagram of the multi-master I2C bus interface and Table 16.1 lists the multi-master I2C bus interface functions. The multi-master I2C bus interface consists of the S0D0 register, the S00 register, the S20 register, the S3D0 register, the S4D0 register, the S10 register, the S2D0 register and other control circuits. Figures 16.2 to 16.8 show the registers associated with the multi-master I2C bus. Table 16.1 Multi-master I2C bus interface functions Item Format Function Based on Philips bus standard: 7-bit addressing format High-speed clock mode Standard clock mode Based on Philips I2C bus standard: I2C Master transmit Master receive Slave transmit Slave receive 16.1kHz to 400kHz (at VIIC (1)= 4MHz) Serial data line SDAMM(SDA) Serial clock line SDLMM(SCL) Communication mode SCL clock frequency I/O pin NOTE: 1. VIIC=I2C system clock Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 255 of 458 M16C/29 Group I2C0 Control Register 1 b7 b0 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 b7 Interrupt request signal ( S CL S DA IRQ) SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 S3D0 I2C0 address registers b0 Interrupt generation circuit ICK1 ICK0 SCLM SDAM WIT SIM I 2C bus interface Interrupt request signal (I2C IRQ) Interrupt generation circuit S0D0 Address comparator Figure 16.1 Block diagram of multi-master I2C bus interface Data control circuit b7 S00 2 I C0 data shift registers page 256 of 458 b0 b7 MST TRX B B P I N Serial Data (SDA) Noise elimination circuit b0 AL AAS AD0 LRB S2D0 AL circuit STSP SIS SEL SIP SSC4 SSC3 SSC2 SSC1 SSC0 I2C0 Internal data bus I C0 Control Registers 2 2 TOF T OE start/stop condition control register S10 I2C0 Status Registers BB circuit S4D0 ICK 4 ICK 3 ICK 2 TOSEL (SCL) ACK ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 CLK BIT MODE I C0 clock control registers 2 Serial clock Time-out detection circuit I2C0 control registers 0 b7 b0 S20 b7 TISS S1D0 b0 A L S ES0 B C 2 B C 1 B C 0 Noise elimination circuit Clock control circuit Clock division I C system clock (VIIC) 2 16. MULTI-MASTER I2C bus INTERFACE System clock select circut fIIC PCLK0=1 PCLK0=0 f1 f2 Bit counter M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE I C0 Address Register b7 b6 b5 b4 b3 b2 b1 b0 2 0 Symbol S0D0 Address 02E216 After Reset 00 16 Bit Symbol (b0) SAD0 SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 Bit Name Reserved bit Set to 0 Function RW RW RW RW Slave address Compare with received address data RW RW RW RW RW Figure 16.2 S0D0 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 257 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE I2C0 Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol S00 Address 02E016 Function After Reset XX16 RW RW(1) Transmit/receive data are stored. In master transmit mode, the start condition/stop condition are triggered by writing data to the register (refer to 16.9 START Condition Generation Method and 16.11 STOP Condition Generation Method). Start transmitting/receiving data while synchronizing with SCL NOTE: 1. Write is enabled only when the ES0 bit in the S1D0 register is 1 (I2C bus interface is enabled). Write the transmit data after the receive data is read because the S00 register is used to store both the transmit and receive data. When the S00 register is set, bits BC2 to BC0 in the S1D0 register are set to 0002, while bits LRB, AAS, and AL in the S10 register are set to 0 respectively. I 2 C0 Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol S20 Bit Symbol CCR0 CCR1 CCR2 CCR3 CCR4 FAST MODE ACKBIT ACK-CLK Bit Name Address 02E416 After Reset 00 16 Function See T able 16.3 RW RW RW RW RW RW S CL F requency Control Bits S CL M ode Specification Bit ACK Bit ACK Clock Bit 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned 1: ACK is not returned 0: No ACK clock 1: With ACK clock RW RW RW Figure 16.3 S00 and S20 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 258 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE I 2 C0 Control Register 0 b7 b3 b2 b1 b0 Symbol S1D0 Bit Symbol BC0 Address 02E316 Bit Name Bit counter (Number of transmit/receive bits) (1) b2 b1 b0 After Reset 00 16 Function 0 0 0: 8 0 0 1: 7 0 1 0: 6 0 1 1: 5 1 0 0: 4 1 0 1: 3 1 1 0: 2 1 1 1: 1 0: Disabled 1: Enabled 0: Addressing format 1: Free data format Set to 0 0: Reset release (automatic) 1: Reset 0: I2C bus input 1: SMBUS input RW RW BC1 BC2 ES0 ALS (b5) IHR TISS I2C bus interface enable bit Data format select bit Reserved bit I2C bus interface reset bit I2C bus interface pin input level select bit RW RW RW RW RW RW RW NOTE: 1.In the following status, the bit counter is set to 000 automatically •Start condition/stop condition are detected •Immediately after the completion of 1-byte data transmit •Immediately after the completion of 1-byte data receive Figure 16.4 S1D0 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 259 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE I 2 C0 Status Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol S10 Bit Symbol LRB ADR0 AAS AL PIN BB TRX MST Bit Name Last receive bit Address 02E816 After Reset 0001000X 2 Function 0: Last bit = 0 1: Last bit = 1 0: No general call detected 1: General call detected 0: No address matched 1: Address matched 0: Not detected 1: Detected 0: Interrupt request issued 1: No interrupt request issued 0: Bus free 1: Bus busy 0 : Receive mode 1: Transmit mode 0: Slave mode 1: Master mode RW RO(1) RO (1) General call detecting flag Slave address comparison flag Arbitration lost detection flag I 2 C bus interface interrupt request bit Bus busy flag Communication mode select bits 0 Communication mode select bit 1 RO (1) RO(2) RO (2) RO(1) RW(3) RW(3) NOTES: 1. This bit is read only if it is used for the status check. To write to this bit, refer to 16.9 START Condition Generation Method and 16.11 STOP Condition Generation Method. 2. Read only. If necessary, set to 0. 3. To write to these bits, refer to 16.9 START Condition Generation Method and 16.11 STOP Condition Generation Method. Figure 16.5 S10 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 260 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE I 2 C0 Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol S3D0 Bit Symbol SIM Bit Name Address 02E616 After Reset 00110000 2 Function 0: Disable the I C bus interface interrupt of STOP condition detection 1: Enable the I2C bus interface interrupt of STOP condition detection 0: Disable the I2C bus interface interrupt of data receive completion 1: Enable the I2C bus interface interrupt of data receive completion When setting NACK (ACK bit = 0), write 0 2 RW The interrupt enable bit for STOP condition detection RW WIT The interrupt enable bit for data receive completion RW PED PEC SDAM SCLM ICK0 ICK1 SDA/port function switch (1) bit SCL/port function switch (1) bit The logic value monitor bit of SDA output The logic value monitor bit of SCL output I2C bus system clock selection bits, if bits ICK4 to ICK2 in the S4D0 register is 000 2 0: SDA I/O pin 1: Port output pin 0: SCL I/O pin 1: Port output pin 0: SDA output logic value = 0 1: SDA output logic value = 1 0: SCL output logic value = 0 1: SCL output logic value = 1 b7 b6 0 0 : VIIC =1/2 fIIC 0 1 : VIIC =1/4fIIC 1 0 : VIIC =1/8 fIIC 1 1 : Reserved RW RW RO RO RW RW (2) NOTE: 1. Bits PED and PEC are enabled when the ES0 bit in the S1D0 register is set to 1 (I2C bus interface enabled). 2. When the PCLK0 bit in the PCLKR register is set to 0, fIIC=f2. When the PCLK0 bit in the PCLKR register is set to 1, fIIC=f1. Figure 16.6 S3D0 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 261 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE I 2 C0 Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol S4D0 Bit Symbol TOE TOF TOSEL ICK2 ICK3 ICK4 (b6) Reserved bit Bit Name Time out detection function enable bit Address 02E716 After Reset 00 16 Function 0: Disabled 1: Enabled 0: Not detected 1: Detected 0: Long time 1: Short time b5 b4 b3 RW RW RO RW RW RW RW Time out detection flag Time out detection time select bit I2C bus system clock select bits 0 0 0 VIIC set by ICK1 and ICK0 bits in S3D0 register 0 0 1 VIIC = 1/2.5 fIIC 0 1 0 VIIC = 1/3 fIIC 0 1 1 VIIC = 1/5 fIIC (1) 1 0 0 VIIC = 1/6 fIIC Do not set other than the above values Set to 0 0: No I2C bus interface interrupt request 1: I2C bus interface interrupt request RW SCPIN STOP condition detection interrupt request bit RW NOTE: 1. When the PCLK0 bit in the PCLKR register is set to 0, fIIC = f2. When the PCLK0 bit is set to 1, fIIC=f1. Figure 16.7 S4D0 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 262 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE I 2 C0 Start/stop Condition Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol S2D0 Bit Symbol SSC0 SSC1 SSC2 SSC3 SSC4 SIP SIS STSPSEL Bit Name Address 02E516 After Reset 00011010 2 Function RW RW Setting for detection condition of START/STOP condition. See Table 16.2 RW RW RW RW START/STOP condition setting bits(1) SCL/SDA interrupt pin polarity select bit SCL/SDA interrupt pin select bit START/STOP condition generation select bit 0: Active in falling edge 1: Active in rising edge 0: SDA enabled 1: SCL enabled 0: Short setup/hold time mode 1: Long setup/hold time mode RW RW RW NOTE: 1. Do not set 000002 or odd values. Figure 16.8 S2D0 Register Table 16.2 Recommended setting (SSC4-SSC0) start/stop condition at each oscillation frequency Oscillation I2C bus system I2C bus system SSC4-SSC0(1) SCL release Setup time Hold time f1 (MHz) clock select clock(MHz) time (cycle) (cycle) (cycle) (2) 10 1 / 2f1 5 XXX11110 6.2 µs (31) 3.2 µs (16) 3.0 µs (15) 8 1 / 2f1(2) 4 XXX11010 6.75 µs(27) 3.5 µs (14) 3.25 µs(13) XXX11000 6.25 µs(25) 3.25 µs (13) 3.0 µs (12) (2) 8 1 / 8f1 1 XXX00100 5.0 µs (5) 3.0 µs (3) 2.0 µs (2) (2) 4 1 / 2f1 2 XXX01100 6.5 µs (13) 3.5 µs (7) 3.0 µs (6) XXX01010 5.5 µs (11) 3.0 µs (6) 2.5 µs (5) 2 1 / 2f1(2) 1 XXX00100 5.0 µs (5) 3.0 µs (3) 2.0 µs (2) NOTES: 1. Do not set odd values or 000002 to START/STOP condition setting bits (SSC4 to SSC0) 2. When the PCLK0 bit in the PCLKR register is set to 1. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 263 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.1 I2C0 Data Shift Register (S00 register) The S00 register is an 8-bit data shift register to store a received data and to write a transmit data. When a transmit data is written to the S00 register, the transmit data is synchronized with a SCL clock and the data is transferred from bit 7. Then, every one bit of the data is transmitted, the register's content is shifted for one bit to the left. When the SCL clock and the data is imported into the S00 register from bit 0. Every one bit of the data is imported, the register's content is shifted for one bit to the left. Figure 16.9 shows the timing to store the receive data to the S00 register. The S00 register can be written when the ES0 bit in the S1D0 register is set to 1 (I2C0 bus interface enabled). If the S00 register is written when the ES0 bit is set to 1 and the MST bit in the S10 register is set to 1 (master mode), the bit counter is reset and the SCL clock is output. Write to the S00 register when the START condition is generatedor when an "L" signal is applied to the SCL pin. The S00 register can be read anytime regardless of the ES0 bit value. SCL SDA Internal SCL Internal SDA tdfil tdfil: Noise elimination circuit delay time 1 to 2 VIIC cycle tdsft: Shift clock delay time 1 VIIC cycle tdfil Shift clock tdsft Store data at the rising edge of shift clock Figure 16.9 The Receive Data Storing Timing of S00 Register 16.2 I2C0 Address Register (S0D0 register) The S0D0 register consists of bits SAD6 to SAD0, total of 7. At the addressing is formatted, slave address is detected automatically and the 7-bit received address data is compared with the contents of bits SAD6 to SAD0. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 264 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.3 I2C0 Clock Control Register (S20 register) The S20 register is used to set theACK control, SCL mode and the SCL frequency. 16.3.1 Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4) These bits control the SCL frequency. See Table 16.3 . 16.3.2 Bit 5: SCL Mode Specification Bit (FAST MODE) The FAST MODE bit selects SCL mode. When the FAST MODE bit is set to 0, standard clock mode is entered. When it is set to 1, high-speed clock mode is entered. When using the high-speed clock mode I2C bus standard (400 kbit/s maximum) to connect buses, set the FAST MODE bit to 1 (select SCL mode as high-speed clock mode) and use the I2C bus system clock (VIIC) at 4 MHz or more frequency. 16.3.3 Bit 6: ACK Bit (ACKBIT) The ACKBIT bit sets the SDA status when an ACK clock(1) is generated. When the ACKBIT bit is set to 0, ACK is returned and te clock applied to SDA becomes "L" when ACK clock is generated. When it is set to 1, ACK is not returned and the clock clock applied to SDA maintains "H" at ACK clock generation. When the ACKBIT bit is set to 0, the address data is received. When the slave address matches with the address data, SDA becomes "L" automatically (ACK is returned). When the slave address and the address data are not matched, SDA becomes "H" (ACK is not returned). NOTE: 1. ACK clock: Clock for acknowledgment 16.3.4 Bit 7: ACK Clock Bit (ACK-CLK) The ACK-CLK bit set a clock for data transfer acknowledgement. When the ACK-CLK bit is set to 0, ACK clock is not generated after data is transferred. When it is set to 1, a master generates ACK clock every one-bit data transfer is completed. The device, which transmits address data and control data, leave SDA pin open (apply "H" signal to SDA) when ACK clock is generated. The device which receives data, receives the generated ACKBIT bit. NOTE: 1.Do not rewrite the S20 register, other than the ACKBIT bit during data transfer. If data is written to other than the ACKBIT bit during transfer, the I2C bus clock circuit is reset and the data may not be transferred successfully. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 265 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE Table 16.3 Setting values of S20 register and SCL frequency Setting value of CCR4 to CCR0 SCL frequency (at VIIC=4MHz, unit : kHz) (1) CCR4 CCR3 CCR2 CCR1 CCR0 Standard clock mode High-speed clock mode 0 0 0 0 0 Setting disabled Setting disabled 0 0 0 0 1 Setting disabled Setting disabled 0 0 0 1 0 Setting disabled Setting disabled 0 0 0 1 1 - (2) 333 0 0 1 0 0 - (2) 250 0 0 1 0 1 100 400 (3) 0 0 1 1 0 83.3 166 500 / CCR value (3) 1000 / CCR value (3) NOTES: 1. The duty of the SCL clock output is 50 %. The duty becomes 35 to 45 % only when high-speed clock mode is selected and the CCR value = 5 (400 kHz, at VIIC = 4 MHz). “H” duration of the clock fluctuates from –4 to +2 I2C system clock cycles in standard clock mode, and fluctuates from –2 to +2 I2C system clock cycles in high-speed clock mode. In the case of negative fluctuation, the frequency does not increase because the “L” is extended instead of “H” reduction. These are the values when the SCL clock synchronization by the synchronous function is not performed. The CCR value is the decimal notation value of the CCR4 to CCR0 bits. 2. Each value of the SCL frequency exceeds the limit at VIIC = 4 MHz or more. When using these setting values, use VIIC = 4 MHz or less. Refer to Figure 16.6. 3. The data formula of SCL frequency is described below: VIIC/(8 x CCR value) Standard clock mode VIIC/(4 x CCR value) High-speed clock mode (CCR value ≠ 5) VIIC/(2 x CCR value) High-speed clock mode (CCR value = 5) Do not set 0 to 2 as the CCR value regardless of the VIIC frequency. Set 100 kHz (max.) in standard clock mode and 400 kHz (max.) in high-speed clock mode to the SCL frequency by setting the CCR4 to CCR0 bits. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 → 1 1 1 → 1 1 1 → 1 1 1 page 266 of 458 → 0 1 1 → 1 0 1 17.2 16.6 16.1 34.5 33.3 32.3 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.4 I2C0 Control Register 0 (S1D0) The S1D0 register controls data communication format. 16.4.1 Bits 0 to 2: Bit Counter (BC0–BC2) Bits BC2 to BC0 decide how many bits are in one byte data transferred next. After the selected numbers of bits are transferred successfully, I2C bus interface interrupt request is gnerated and bits BC2 to BC0 are reset to 0002. At this time, if the ACK-CLK bit in the S20 register is set to 1 (with ACK clock), one bit for ACK clock is added to the numbers of bits selected by the BC2 to BC0 bits. In addition, bits BC2 to BC0 become 0002 even though the START condition is detected and the address data is transferred in 8 bits. 16.4.2 Bit 3: I2C Interface Enable Bit (ES0) The ES0 bit enables to use the multi-master I2C bus interface. When the ES0 bit is set to 0, I2C bus interface is disabled and the SDA and SCL pins are placed in a high-h-impedance state. When the ES0 bit is set to 1, the interface is enabled. When the ES0 bit is set to 0, the process is followed. 1)The bits in the S10 register are set as MST = 0, TRX = 0, PIN = 1, BB = 0, AL = 0, AAS = 0, ADR0 = 0 2)The S00 register cannot be written. 3)The TOF bit in the S4D0 register is set to 0 (time-out detection flag is not detected) 4)The I2C system clock (VIIC) stops counting while the internal counter and flags are reset. 16.4.3 Bit 4: Data Format Select Bit (ALS) The ALS bit determines whether the salve address is recognized. When the ALS bit is set to 0, an addressing format is selected and a address data is recognized. Only if the comparison is matched between the slave address stored into the S0D0 register and the received address data or if the general call is received, the data is transferred. When the ALS bit is set to 1, the free data format is selected and the slave address is not recognized. 16.4.4 Bit 6: I2C bus Interface Reset Bit (IHR) The IHR bit is used to reset the I2C bus interface circuit when the error communication occurs. When the ES0 bit in the S1D0 register is set to 1 (I2C bus interface is enabled), the hardware is reset by writing 1 to the IHR bit. Flags are processed as follows: 1)The bits in the S10 register are set as MST = 0, TRX = 0, PIN to 1, BB = 0, AL = 0, AAS = 0, and ADR0 = 0 2)The TOF bit in the S4D0 register is set to 0 (time-out detection flag is not detected) 3)The internal counter and flags are reset. The I2C bus interface circuit is reset after 2.5 VIIC cycles or less, and the IHR bit becomes 0 automatically by writing 1 to the IHR bit. Figure 16.10 shows the reset timing. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 267 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.4.5 Bit 7: I2C bus Interface Pin Input Level Select Bit (TISS) The TISS bit selects the input level of the SCL and SDA pins for the multi-master I2C bus interface. When the TISS bit is set to 1, the P20 and P21 become the SMBus input level. Write 1 to IHR bit IHR bit A reset signal to I2C bus interface circuit 2.5 VIIC cycles Figure 16.10 The timing of reset to the I2C bus interface circuit Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 268 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.5 I2C0 Status Register (S10 register) The S10 register monitors the I2C bus interface status. When using the S10 register to check the status, use the 6 low-order bits for read only. 16.5.1 Bit 0: Last Receive Bit (LRB) The LRB bit stores the last bit value of received data. It can also be used to confirm whether ACK is received. If the ACK-CLK bit in the S20 register is set to 1 (with ACK clock) and ACK is returned when the ACK clock is generated, the LRB bit is set to 0. If ACK is not returned, the LRB bit is set to 1. When the ACK-CLK bit is set to 0 (no ACK clock), the last bit value of received data is input. When writing data to the S00 register, the LRB bit is set to 0. 16.5.2 Bit 1: General Call Detection Flag (ADR0) When the ALS bit in the S1D0 register is set to 0 (addressing format), this ADR0 flag is set to 1 by receiving the general calls(1),whose address data are all 0, in slave mode. The ADR0 flag is set to 0 when STOP or START conditions is detected or when the IHR bit in the S1D0 register is set to 1 (reset). NOTE: 1. General call: A master device transmits the general call address 0016 to all slaves. When the master device transmits the general call, all slave devices receive the controlled data after general call. 16.5.3 Bit 2: Slave Address Comparison Flag (AAS) The AAS flag indicates a comparison result of the slave address data after enabled by setting the ALS bit in the S1D0 register to 0 (addressing format). The AAS flag is set to 1 when the 7 bits of the address data are matched with the slave address stored into the S0D0 register, or when a general call is received, in slave receive mode. The AAS flag is set to 0 by writing data to the S00 register. When the ES0 bit in the S1D0 register is set to 0 (I2C bus interface disabled) or when the IHR bit in the S1D0 register is set to 1 (reset), the AAS flag is also set to 0. 16.5.4 Bit 3: Arbitration Lost Detection Flag (AL)(1) In master transmit mode, if an "L" signal is applied to the SDA pin by other than the MCU, the AL flag is set to 1 by determining that the arbitration is los and the TRX bit in the S10 register is set to 0 (receive mode) at the same time. The MST bit in the S10 register is set to 0 (slave mode) after transferring the bytes which lost the arbitration. The arbitration lost can be detected only in master transmit mode. When writing data to the S00 register, the AL flag is set to 0. When the ES0 bit in the S1D0 register is set to 0 (I2C bus interface disabled) or when the IHR bit in the S1D0 register is set to 1 (reset), the AL flag is set to 0. NOTE: 1. Arbitration lost: communication disabled as a master Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 269 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.5.5 Bit 4: I2C bus Interface Interrupt Request Bit (PIN) The PIN bit generates an I2C bus interface interrupt request signal. Every one byte data is ransferred, the PIN bit is changed from 1 to 0. At the same time, an I2C bus interface interrupt request is generated. The PIN bit is synchronized with the last clock of the internal transfer clock (when ACK-CLK=1, the last clock is the ACK clock: when the ACK-CLK=0, the last clock is the 8th clock) and it becomes 0. The interrupt request is generated on the falling edge of the PIN bit. When the PIN bit is set to 0, the clock applied to SCL maintains "L" and further clock generation is disabled. When the ACK-CLK bit is set to 1 and the WIT bit in the S3D0 register is set to 1 (enable the I2C bus interface interrupt of data receive completion). The PIN bit is synchronized with the last clock and the falling edge of the ACK clock. Then, the PIN bit is set to 0 and I2C bus interface interrupt request is generated. Figure 16.11 shows the timing of the I2C bus interface interrupt request generation. The PIN bit is set to 1 in one of the following conditions: •When data is written to the S00 register •When data is written to the S20 register (when the WIT bit is set to 1 and the internal WAIT flag is set to 1) •When the ES0 bit in the S1D0 register is set to 0 (I2C bus interface disabled) •When the IHR bit in the S1D0 register is set to 1(reset) The PIN bit is set to 0 in one of the following conditions: •With completion of 1-byte data transmit (including a case when arbitration lost is detected) •With completion of 1-byte data receive •When the ALS bit in the S1D0 register is set to 0 (addressing format) and slave address is matched or general call address is received successfully in slave receive mode •When the ALS bit is set to 1 (free format) and the address data is received successfully in slave receive mode 16.5.6 Bit 5: Bus Busy Flag (BB) The BB flag indicates the operating conditions of the bus system. When the BB flag is set to 0, a bus system is not in use and a START condition can be generated. The BB flag is set and reset based on an input signal of the SCL and SDA pins either in master mode or in slave mode. When the START condition is detected, the BB flag is set to 1. On the other hand, when the STOP condition is detected, the BB flag is set to 0. Bits SSC4 to SSC0 in the S2D0 register decide to detect between the START condition and the STOP condition. When the ES0 bit in the S1D0 register is set to 0 (I2C bus interface disabled) or when the IHR bit in the S1D0 register is set to 1 (reset), the BB flag is set to 0. Refer to 16.9 START Condition Generation Method and 16.11 STOP Condition Generation Method. SC L PIN flag I2CIRQ Figure 16.11 Interrupt request signal generation timing Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 270 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: TRX) This TRX bit decides a transfer direction for data communication. When the TRX bit is set to 0, receive mode is entered and data is received from a transmit device. When the TRX bit is set to 1, transmit mode is entered, and address data and control data are output to the SDAMM, synchronized with a clock generated in the SCLMM. The TRX bit is set to 1 automatically in the following condition: •In slave mode, when the ALS in the S1D0 register to 0(addressing format), the AAS flag is set to ___ 1 (address match) after the address data is received, and the received R/W bit is set to 1 The TRX bit is set to 0 in one of the following conditions: •When an arbitration lost is detected •When a STOP condition is detected •When a START condition is detected •When a START condition is disabled by the START condition duplicate protect function (1) •When the MST bit in the S10 register is set to 0(slave mode) and a start condition is detected •When the MST bit is set to 0 and the ACK non-return is detected •When the ES0 bit is set to 0(I2C bus interface disabled) •When the IHR bit in the S1D0 register is set to 1(reset) 16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST) The MST bit selects either master mode or slave mode for data communication. When the MST bit is set to 0, slave mode is entered and the START/STOP condition generated by a master device are received. The data communication is synchronized with the clock generted by the master. When the MST bit is set to 1, master mode is entered and the START/STOP condition is generated. Additionally, clocks required for the data communication are generated on the SCLMM. The MST bit is set to 0 in one of the following conditions. •After 1-byte data of a master whose arbtration is lost if arbitration lost is detected •When a STOP condition is detected •When a START condition is detected •When a start condition is disabled by the START condition duplicate protect function (1) •When the IHR bit in the S1D0 register is set to 1(reset) •When the ES0 bit is set to 0(I2C bus interface disabled) NOTE: 1. START condition duplicate protect function: When the START condition is generated, after confirming that the BB flag in the S1D0 register is set to 0 (bus free), all the MST, TRX and BB flags are set to 1 at the same time. However, if the BB flag is set to 1 immediately after the BB flag setting is confirmed because a START condition is generated by other master device, bits MST and TRX cannot be written. The duplicate protect function is valid from the rising edge of the BB flag until slave address is received. Refer to 16.9 START Condition Generation Method for details. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 271 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.6 I2C0 Control Register 1 (S3D0 register) The S3D0 register controls the I2C bus interface circuit. 16.6.1 Bit 0 : Interrupt Enable Bit by STOP Condition (SIM ) The SIM bit enables the I2C bus interface interrupt request by detecting a STOP condition. If the SIM bit is set to 1, the I2C bus interface interrupt request is generated by the STOP condition detect (no need to change in the PIN flag). 16.6.2 Bit 1: Interrupt Enable Bit at the Completion of Data Receive (WIT) If the WIT bit is set to 1 while the ACK-CLK bit in the S20 register is set to 1 (ACK clock), the I2C bus interface interrupt request is generated and the PIN bit is set to 1 at the falling edge of the last data bit clock. Then an "L" signal is applied to the SCLMM and the ACK clock generation is controlled. Table 16.4 and Figure 16.12 show the interrupt generation timing and the procedure of communication restart. After the communication is restarted, the PIN bit is set to 0 again, synchronized with the falling edge of the ACK clock, and the I2C bus interface interrupt request is generated. Table16.4 Timing of Interrupt Generation in Data Receive Mode I2C bus Interface Interrupt Generation Timing Procedure of Communication Restart 1) Synchronized with the falling edge of the Set the ACK bit in the S20 register. last data bit clock Set the PIN bit to 1. (Do not write to the S00 register. The ACK clock operation may be unstable.) 2) Synchronized with the falling edge of the Set the S00 register ACK clock The internal WAIT flag can be read by reading the WIT bit. The internal WAIT flag is set to 1 after writing data to the S00 register and it is set to 0 after writing to the S20 register. Consequently, the I2C bus interface interrupt request generated by the timing 1) or 2) can be determined. (See Figure 16.12) When the data is transmitted and the address data is received immediately after the START condition, the WAIT flag remains 0 regardless of the WIT bit setting, and the I2C bus interface interrupt request is only generated at the falling edge of the ACK clock. Set the WIT bit to 0 when the ACK-CLK bit in the S20 register is set to 0 (no ACK clock). Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 272 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE In receive mode, ACK bit = 1 WIT bit = 0 SCL SDA ACKBIT bit PIN flag Internal WAIT flag I2C bus interface interrupt request signal The writing signal of the S00 register 7 clock 7 bit 8 bit 8 clock ACK clock ACK bit 1 clock 1 bit In receive mode, ACK bit = 1 WIT bit = 1 SCL SDA ACKBIT bit PIN flag Internal WAIT flag I2C bus interface interrupt request signal The writing signal of the S00 register The writing signal of the S2 0 register 7 clock 7 bit 8 bit 8 clock ACK clock 1 bit 1) 2) NOTE: 1. Do not write to the I2C0 clock control register except the bit ACK-BIT. Figure 16.12 The timing of the interrupt generation at the completion of the data receive 16.6.3 Bits 2,3 : Port Function Select Bits PED, PEC If the ES0 bit in the S1D0 register is set to 1 (I2C bus interface enabled), the SDAMM functions as an output port. When the PED bit is set to 1 and the SCLMM functions as an output port when the PEC bit is set to 1. Then the setting values of bits P2_0 and P2_1 in the port P2 register are output to the I2C bus, regardless of he internal SCL/SDA output signals. (SCL/SDA pins are onnected to I2C bus interface circuit) The bus data can be read by reading the port pi direction register in input mode, regardless of the setting values of the PED and PEC bits. Table 16.5 shows the port specification. Table 16.5 Port specifications Pin Name ES9 Bit 0 P20 1 1 Pin Name ES0 Bit 0 P21 1 1 PED Bit 0 1 PEC Bit 0 1 P20 Port Direction Register 0/1 P21 Port Direction Register 0/1 Function Port I/O function SDA I/O function SDA input function, port output function Function Port I/O function SCL I/O function SCL input function, port output funcion Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 273 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM Bits SDAM/SCLM can monitor the logic value of the SDA and SCL output signals from the I 2C bus interface circuit. The SDAM bit monitors the SDA output logic value. The SCLM bit monitors the SCL output logic value. The SDAM and SCLM bits are read-only. If necessary, set them to 0. 16.6.5 Bits 6,7 : I2C System Clock Select Bits ICK0, ICK1 The ICK1 bit, ICK0 bit, bits ICK4 to ICK2 in the S4D0 register, and the PCLK0 bit in the PCLKR register can select the system clock (VIIC) of the I2C bus interface circuit. The I2C bus system clock VIIC can be selected among 1/2 fIIC, 1/2.5 fIIC, 1/3 fIIC, 1/4 fIIC, 1/5 fIIC, 1/6 fIIC and 1/8 fIIC. fIIC can be selected between f1 and f2 by the PCLK0 bit setting. Table 16.6 I2C system clock select bits I3CK4[S4D0] 0 0 0 0 0 0 1 ICK3[S4D0] 0 0 0 0 1 1 0 ICK2[S4D0] 0 0 0 1 0 1 0 ICK1[S3D0] 0 0 1 X X X X ICK0[S3D0] 0 1 0 X X X X I2C system clock VIIC = 1/2 fIIC VIIC = 1/4 fIIC VIIC = 1/8 fIIC VIIC = 1/2.5 fIIC VIIC = 1/3 fIIC VIIC = 1/5 fIIC VIIC = 1/6 fIIC ( Do not set the combination other than the above) 16.6.6 Address Receive in STOP/WAIT Mode When WAIT mode is entered after the CM02 bit in the CM0 register is set to 0 (do not stop the peripheral function clock in wait mode), the I2C bus interface circuit can receive address data in WAIT mode. However, the I2C bus interface circuit is not operated in STOP mode or in low power consumption mode, because the I2C bus system clock VIIC is not supplied. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 274 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.7 I2C0 Control Register 2 (S4D0 Register) The S4D0 register controls the error communication detection. If the SCL clock is stopped counting dring data transfer, each device is stopped, staying online. To avoid the situation, the I2C bus interface circuit has a function to detect the time-out when the SCL clock is stopped in high-level ("H") state for a specific period, and to generate an I2C bus interface interrupt request. See Figure 16.13. SCL clock stop (“H”) SCL SDA BB flag Internal counter start signal Internal counter stop, reset signal Internal counter overflow signal I2C-bus interface interrupt request signal The time of timeout detection 1 bit 1 clock 2 bit 2 clock 3 bit 3 clock Figure 16.13 The timing of time-out detection Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 275 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) The TOE bit enables the time-out detection function. When the TOE bit is set to 1, time-out is detected and the I2C bus interface interrupt request is generated when the following conditions are met. 1) the BB flag in the S10 register is set to 1 (bus busy) 2) the SCL clock stops for time-out detection period while high-level ("H") signal is maintained (see Table 16.7) The internal counter measures the time-out detection time and the TOSEL bit selects between two modes, long time and short time. When time-out is detected, set the ES0 bit to 0 (I2C bus interface disabled) and reset the counter. 16.7.2 Bit1: Time-Out Detection Flag (TOF ) The TOF flag indicates the time-out detection. If the internal counter which measures the time-out period overflows, the TOF flag is set to 1 and the I2C bus interface interrupt request is generated at the same time. 16.7.3 Bit2: Time-Out Detection Period Select Bit (TOSEL) The TOSEL bit selects time-out detection period from long time mode and short time mode. When the TOSEL bit is set to 0, long time mode is selected. When it is set to 1, short time mode is selected, respectively. The internal counter increments as a 16-bit counter in long time mode, while the counter increments as a 14-bit counter in short time mode, based on the I2C system clock (VIIC) as a counter source. Table 16.7 shows examples of time-out detection period. Table 16.7 Examples of Time-out Detection Period VIIC(MHz) 4 2 1 Long time mode 16.4 32.8 65.6 (Unit: ms) Short time mode 4.1 8.2 16.4 16.7.4 Bits 3,4,5: I2C System Clock Select Bits (ICK2-4) Bits ICK4 to ICK2, and bits ICK1 and ICK0 in the S3D0 register, and the PCLK0 bit in the PCLKR register select the system clock (VIIC) of the I2C bus interface circuit. See Table 16.6 for the setting values. 16.7.5 Bit7: STOP Condition Detection Interrupt Request Bit (SCPIN) The SCPIN bit monitors the stop condition detection interrupt. The SCPIN bit is set to 1 when the I2C bus interface interrupt is generated by detecting the STOP condition. When this bit is set to 0 by program, it becomes 0. However, no change occurs even if it is set to 1. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 276 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.8 I2C0 START/STOP Condition Control Register (S2D0 Register) The S2D0 register controls the START/STOP condition detections. 16.8.1 Bit0-Bit4: START/STOP Condition Setting Bits (SSC0-SSC4) The SCL release time and the set-up and hold times are mesured on the base of the I2C bus system clock (VIIC). Therefore, the detection conditions changes, depending on the oscillation frequency (XIN) and the I2C bus system clock select bits. It is necessary to set bits SSC4 to SSC0 to the appropriate value to set the SCL release time, the set-up and hold times by the system clock frequency (See Table 16.10). Do not set odd numbers or 000002 to bits SSC4 to SSC0. Table 16.2 shows the reference value to bits SSC4 to SSC0 at each oscillation frequency in standard clock mode. The detection of START/STOP conditions starts immediately after the ES0 bit in the S1D0 register is set to 1 (I2C bus interface enabled). 16.8.2 Bit5: SCL/SDA Interrupt Pin Polarity Select Bit (SIP) The The SIP bit detect the rising edge or the falling edge of the SCLMM or SDAMM to generate SCL/SDA interrupts. The SIP bit selects the polarity of the SCLMM or the SDAMM for interrupt. 16.8.3 Bit6 : SCL/SDA Interrupt Pin Select Bit (SIS) The SIS bit selects a pin to enable SCL/SDA interrupt. NOTE: 1. The SCL/SDA interrupt request may be set when changing the SIP, SIS and ES0 bit settings in the S1D0 register. When using the SCL/SDA interrupt, set the above bits, while the SCL/SDA interrupt is disabled. Then, enable the SCL/SDA interrupt after setting the SCL/SDA bit in the IR register to 0. 16.8.4 Bit7: START/STOP Condition Generation Select Bit (STSPSEL) The STSPSEL bit selects the set-up/hold times, based on the I2C system clock cycles, when the START/ STOP condition is generated (See Table 16.8). Set the STSPSEL bit to 1 if the I2C bus system clock frequency is over 4MHz. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 277 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.9 START Condition Generation Method Set the MST bit, TRX bit and BB flags in the S10 register to 1 and set the PIN bit and 4 low-order bits in the S10 register to 0 simultaneously, to enter START condition standby mode, when the ES0 bit in the S1D0 register is set to 1 (I2C bus interface enabled) and the BB flag is set to 0 (bus free). When the slave address is written to the S00 register next, START condition is generated and the bit counter is reset to 0002 and 1byte SCL signal is output. The START condition generation timing varies between standard clock mode and high-speed clock mode. See Figure 16.16 and Table 16.8. Interrupt disable BB=0? No Yes S10 = E016 Start condition standby status setting S00 = Data Start condition trigger generation *Data = Slave address data Interrupt enable Figure 16.14 Start condition generation flow chart Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 278 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.10 START Condition Duplicate Protect Function A START condition is generated when verifying that the BB flag in the S10 register does not use buses. However, if the BB flag is set to 1 (bus busy) by the START condition which other master device generates immediately after the BB flag is verified, the START condition is suspended by the START condition duplicate protect function. When the START condition duplicate protect function starts, it operates as follows: •Disable the start condition standby setting If the function has already been set, first exit START condition standby mode and then set bits MST and TRX in the S10 register to 0. •Writing to the S00 register is disabled. (The START condition trigger generation is disabled) •If the START condition generation is interrupted, the AL flag in the S10 register becomes 1.(arbitration lost detection) The START condition duplicate protect function is valid between the SDA falling edge of the START condition and the receive completion of the slave address. Figure16.15 shows the duration of the START condition duplicate protect function. SCL SDA BB flag 1 bit 1 clock 2 clock 2 bit 3 clock 3 bit 8 clock 8 bit ACK clock ACK bit The duration of start condition duplicate protect Figure 16.15 The duration of the start condition duplicate protect function 16.11 STOP Condition Generation Method When the ES0 bit in the S1D0 register is set to 1 (I2C bus interface enabled) and bits MST and TRX in the S10 register are set to 1 at the same time, set the BB flag, PIN bit and 4 low-order bits in the S10 register to 0 simultaneously, to enter STOP condition standby mode. When dummy data is written to the S00 register next, the STOP condition is generated. The STOP condition generation timing varies between standard clock mode and high-speed clock mode. See Figure 16.17 and Table 16.8. Until the BB flag in the S10 register becomes 0 (bus free) after an instruction to generate the STOP condition is executed, do not write data to registers S10 and S00. Otherwise, the STOP condition waveform may not be generated correctly. If an input signal level of the SCL pin is set to low ("L") after the instruction to generate the STOP condition is executed, a signal level of the SCL pin becomes high ("H"), and the BB flag is set to 0 (bus free), the MCU outputs an "L" signal to SCL pin. In that case, the MCU can stop an "L" signal output to the SCL pin by generating the STOP condition, writing 0 to the ES0 bit in the S1D0 register (disabled), or writing 1 to the IHR bit in the S1D0 register (reset release). Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 279 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE S00 register SCL SDA Setup time Hold time Figure 16.16 Start condition generation timing diagram S00 register SCL SDA Setup time Hold time Figure 16.17 Stop condition generation timing diagram Table 16.8 Start/Stop generation timing table Start/Stop Condition Generation Select Bit Setup time Hold time 0 1 0 1 Standard Clock Mode 5.0 µs (20 cycles) 13.0 µs (52 cycles) 5.0 µs (20 cycles) 13.0 µs (52 cycles) High-speed Clock Mode 2.5 µs (10 cycles) 6.5 µs (26 cycles) 2.5 µs (10 cycles) 6.5 µs (26 cycles) N OTE: 1. Actual time at the time of VIIC = 4MHz, The contents in () denote cycle numbers. As mentioned above, when bits MST and TRX are set to 1, START condition or STOP condition mode is entered by writing 1 or 0 to the BB flag in the S10 register and writing 0 to the PIN bit and 4 low-order bits in the S10 register at the same time. Then SDAMM is left open in the START condition standby mode and SDAMM is set to low-level ("L") in the STOP condition standby mode. When the S00 register is set, the START/STOP conditions are generated. In order to set bits MST and TRX to 1 without generating the START/STOP conditions, write 1 to the 4 low-order bits simultaneously. Table 16.9 lists functions along with the S10 register settings. Table 16.9 S10 Register Settings and Functions S10 Register Settings MST 1 1 0/1 TR X 1 1 0/1 BB 1 0 PIN 0 0 0 AL 0 0 1 AAS 0 0 1 AS0 0 0 1 LRB 0 0 1 Function Setting up the START condition stand by in master transmit mode Setting up the STOP condition stand by in master transmit mode Setting up each communication mode (refer to 16.5 I2C status register) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 280 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.12 START/STOP Condition Detect Operation Figure 16.18, Figure 16.19 and Table 16.10 show START/STOP condition detect operations. Bits SSC4 to SSC0 in the S2D0 register set the START/STOP conditions. The START/STOP condition can be detected only when the input signal of the SCLMM and SDAMM met the following conditions: the SCL release time, the set-up time, and the hold time (see Table 16.10). The BB flag in the S10 register is set to 1 when the START condition is detected and it is set to 0 when the STOP condition is detected. The BB flag set and reset timing varies between standard clock mode and high-speed clock mode. See Table 16.10. SCL release time SCL Setup time Hold time SDA BB flag set time BB flag Figure 16.18 Start condition detection timing diagram SCL release time SCL Setup time SDA BB flag set time BB flag Hold time Figure 16.19 Stop condition detection timing diagram Table 16.10 Start/Stop detection timing table SCL release time Setup time Hold time BB flag set/reset time Standard clock mode SSC value + 1 cycle (6.25µs) SSC value + 1 cycle < 4.0µs (3.25µs) 2 SSC value cycle < 4.0µs (3.0µs) 2 SSC value - 1 +2 cycles (3.375µs) 2 High-speed clock mode 4 cycles (1.0µs) 2 cycles (0.5µs) 2 cycles (0.5µs) 3.5 cycles (0.875µs) NOTE: 1. Unit : number of cycle for I2C system clock VIIC The SSC value is the decimal notation value of bits SSC4 to SSC0. Do not set 0 or odd numbers to the SSC setting. The values in ( ) are examples when the S2D0 register is set to 1816 at VIIC = 4 MHz. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 281 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.13 Address Data Communication This section describes data transmit control when a master transferes data or a slave receives data in 7-bit address format. Figure 16.20 (1) shows a master transmit format. (1) A master transmit device transmits data to a receive device S Slave address 7 bits R/W 0 A Data 1 - 8 bits A Data 1 - 8 bits A/A P (2) A master receive device receives data from a transmit device S Slave address 7 bits R/W 1 A Data 1 - 8 bits A Data 1 - 8 bits A P S: START condition A: ACK bit P: STOP condition R/W: Read/Write bit Figure 16.20 Address data communication format 16.13.1 Example of Master Transmit For example, a master transmits data as shown below when following conditions are met: standard clock mode, SCL clock frequency of 100kHz and ACK clock added. 1) Set s slave address to the 7 high-order bits in the S0D0 register 2) Set 8516 to the S20 register, 0002 to bits ICK4 to ICK2 in the S4D0 register and 0016 to the S3D0 registe to generate an ACK clock and set SCL clock frequency t 100 kHz (f1=8MHz, fIIC=f1) 3) Set 0016 to the S10 register to reset transmit/receive 4) Set 0816 to the S1D0 register to enable data communication 5) Confirm whether the bus is free by BB flag setting in the S10 register 6) Set E016 to the S10 register to enter START condition standby mode 7) Set the destination address in 7 high-order bits and 0 to a least significant bit in the S00 register to generate START condition. At this time, the first byte consisting of SCL and ACK clock are automatically generated 8) Set a transmit data to the S00 register. At this time, SCL and an ACK clock are automatically generated 9) When transmitting more than 1-byte control data, repeat the above step 8). 10) Set C016 in the S10 register to enter STOP condition standby mode if ACK is not returned from the slave receiver or if the transmit is completed 11) Write dummy data to the S00 regiser to generate STOP condition Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 282 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.13.2 Example of Slave Receive For example, a slave receives data as shown below when following conditions are met: high-speed clock mode, SCL frequency of 400 kHz, ACK clock added and addressing format. 1) Set a slave address in the 7 high-order bits in the S0D0 register 2) Set A516 to the S20 register, 0002 to bits ICK4 to ICK2 in the S4D0 register, and 0016 to the S3D0 register to generate an ACK clock and set SCL clock frequency at 400kHz (f1 = 8 MHz, fIIC = f1) 3) Set 0016 to the S10 register to reset transmit/receive mode 4) Set 0816 to the S1D0 register to enable data communication 5) When a START condition is received, addresses are compared 6) •When the transmitted addresses are all 0 (general call), the ADR0 bit in the S10 register is set to 1 and an I2C bus interface interrupt request signal is generated. •When the transmitted addresses match with the address set in 1), the ASS bit in the S10 register is set to 1 and an I2C bus interface interrupt request signal is generated. •In other cases, bits ADR0 and AAS are set to 0 and I2C bus interface interrupt request signal is not generated. 7) Write dummy data to the S00 register. 8) After receiving 1-byte data, an ACK-CLK bit is automatically returned and an I2C bus interface interrupt request signal is generated. 9) To determine whether the ACK should be returned depending on contents in the received data, set dummy data to the S00 register to receive data after setting the WIT bit in te S3D0 register to 1 (enable the I2C bus interface interrupt of data receive completion). Because the I2C bus interface interrupt is generated when the 1-byte data is received, set the ACKBIT bit to 1 or 0 to output a signal from the ACKBIT bit. 10) When receiving more than 1-byte control data, repeat steps 7) and 8) or 7) and 9). 11) When a STOP condition is detected, the communication is ended. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 283 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE 16.14 Precautions (1) Access to the registers of I2C bus interface circuit The following is precautions when read or write the control registers of I2C bus interface circuit •S00 register Do not rewrite the S00 register during data transfer. If the bits in the S00 register are rewritten, the bit counter for transfer is reset and data may not be transferred successfully. •S1D0 register Bits BC2 o BC0 are set to 0002 when START condition is detected or when 1-byte data transfer is completed. Do not read or write the S1D0 register at this timing. Otherwise, data may be read or written unsuccessfully. Figure 16.22 and Figure 16.23 show the bit counter reset timing. •S20 register Do not rewrite the S20 register except the ACKBIT bit during transfer. If the bits in the S20 register except ACKBIT bit are rewritten, the I2C bus clock circuit is reset and data may be transferred incompletely. •S3D0 register Rewrite bits ICK4 to ICK0 in the S3D0 register when the ES0 bit in the S1D0 register is set to 0 (I2C bus interface is disabled). When the WIT bit is read, the internal WAIT flag is read. Therefore, do not use the bit managing instruction(read-modify-write instruction) to access the S3D0 register. •S10 register Do not use the bit managing instruction (read-modify-write instruction) because all bits in the S10 register will be changed, depending on the communication conditions. Do not read/write when te communication mode select bits, bits MST and TRX, are changing their value. Otherwise, data may be read or written unsuccessfully. Figure16.21 to Figure 16.23 show the timing when bits MST and TRX change. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 284 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE SCL SDA BB flag Bit reset signal Related bits MST TRX 1.5 VIIC cycle Figure 16.21 The bit reset timing (The STOP condition detection) SCL SDA BB flag Bit reset signal Related bits BC2 - BC0 TRX (in slave mode) Figure 16.22 The bit reset timing (The START condition detection) SCL PIN bit Bit reset signal Bit set signal 2VIIC cycle The bits referring to reset BC0 - BC2 MST(When in arbitration lost) TRX(When in NACK receive in slave transmit mode) TRX(ALS=0 meanwhile the slave receive R/W bit = 1 The bits referring to set 1VIIC cycle Figure 16.23 Bit set/reset timing ( at the completion of data transfer) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 285 of 458 M16C/29 Group 16. MULTI-MASTER I2C bus INTERFACE (2) Generation of RESTART condition In order to generate a RESTART condition after 1-byte data transfer, write E016 to the S10 register, enter START condition standby mode and leave the SDAMM open. Generate a START condition trigger by setting the S00 register after inserting a sufficient software wait until the SDAMM outputs a high-level ("H") signal. Figure 16.24 shows the RESTART condition generation timing. SCL SDA 8 clocks ACK clock S10 writing signal (START condition setting standby) S00 writing signal (START condition triger generation) Insert software wait Figure 16.24 The time of generation of RESTART condition (3) Iimitation of CPU clock When the CM07 bit in the CM0 register is set to 1 (subclock), each register of the I2C bus interface circuit cannot be read or written. Read or write data when the CM07 bit is set to 0 (main clock, PLL clock, or on-chip oscillator clock). Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 286 of 458 M16C/29 Group 17. CAN Module 17. CAN Module The CAN (Controller Area Network) module for the M16C/29 Group of MCUs is a communication controller implementing the CAN 2.0B protocol. The M16C/29 Group contains one CAN module which can transmit and receive messages in both standard (11-bit) ID and extended (29-bit) ID formats. Figure 17.1 shows a block diagram of the CAN module. External CAN bus driver and receiver are required. Data Bus C0CONR Register C0CTLR Register C0GMR Register C0LMAR Register C0MCTLj Register C0LMBR Register C0IDR Register CTX Message Box slots 0 to 15 Protocol Controller Acceptance Filter slots 0 to 15 16 Bit Timer CRX C0TSR Register Message ID DLC Message Data Time Stamp Wake Up Function Interrupt Generation Function C0STR Register C0SSTR Register C0ICR Register CAN0 Successful Reception Int CAN0 Successful Transmission Int CAN0 Error Int C0RECR Register C0TECR Register Data Bus j = 0 to 15 CAN0 Wake-Up Int Figure 17.1 Block Diagram of CAN Module CTx/CRx: Protocol controller: CAN I/O pins. This controller handles the bus arbitration and the CAN protocol services, i.e. bit timing, stuffing, error status etc. Message box: This memory block consists of 16 slots that can be configured either as transmitter or receiver. Each slot contains an individual ID, data length code, a data field (8 bytes) and a time stamp. Acceptance filter: This block performs filtering operation for received messages. For the filtering operation, the C0GMR register, the C0LMAR register, or the C0LMBR register is used. 16 bit timer: Used for the time stamp function. When the received message is stored in the message memory, the timer value is stored as a time stamp. Wake-up function: CAN0 wake-up interrupt request is generated by a message from the CAN bus. Interrupt generation function: The interrupt requests are generated by the CAN module. CAN0 successful reception interrupt, CAN0 successful transmission interrupt, CAN0 error interrupt and CAN0 wake-up interrupt. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 287 of 458 M16C/29 Group 17. CAN Module 17.1 CAN Module-Related Registers The CAN0 module has the following registers. (1) CAN Message Box A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN. • Priority of the slots: The smaller the number of the slot, the higher the priority, in both transmission and reception. • A program can define whether a slot is defined as transmitter or receiver. (2) Acceptance Mask Registers A CAN module is equipped with 3 masks for the acceptance filter. • CAN0 global mask register (C0GMR register: 6 bytes) Configuration of the masking condition for acceptance filtering processing to slots 0 to 13 • CAN0 local mask A register (C0LMAR register: 6 bytes) Configuration of the masking condition for acceptance filtering processing to slot 14 • CAN0 local mask B register (C0LMBR register: 6 bytes) Configuration of the masking condition for acceptance filtering processing to slot 15 (3) CAN SFR Registers • CAN0 message control register j (C0MCTLj register: 8 bits ✕ 16) (j = 0 to 15) Control of transmission and reception of a corresponding slot • CANi control register (CiCTLR register: 16 bits) (i = 0, 1) Control of the CAN protocol • CAN0 status register (C0STR register: 16 bits) Indication of the protocol status • CAN0 slot status register (C0SSTR register: 16 bits) Indication of the status of contents of each slot • CAN0 interrupt control register (C0ICR register: 16 bits) Selection of “interrupt enabled or disabled” for each slot • CAN0 extended ID register (C0IDR register: 16 bits) Selection of ID format (standard or extended) for each slot • CAN0 configuration register (C0CONR register: 16 bits) Configuration of the bus timing • CAN0 receive error count register (C0RECR register: 8 bits) Indication of the error status of the CAN module in reception: the counter value is incremented or decremented according to the error occurrence. • CAN0 transmit error count register (C0TECR register: 8 bits) Indication of the error status of the CAN module in transmission: the counter value is incremented or decremented according to the error occurrence. • CAN0 time stamp register (C0TSR register: 16 bits) Indication of the value of the time stamp counter • CAN0 acceptance filter support register (C0AFS register: 16 bits) Decoding the received ID for use by the acceptance filter support unit Explanation of each register is given as follows. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 288 of 458 M16C/29 Group 17. CAN Module 17.1.1 CAN0 Message Box Table 17.1 shows the memory mapping of the CAN0 message box. It is possible to access to the message box in byte or word. Mapping of the message contents differs from byte access to word access. Byte access or word access can be selected by the MsgOrder bit of the C0CTLR register. Table 17.1 Memory Mapping of CAN0 Message Box Address 006016 006016 006016 006016 006016 006016 006016 006016 + + + + + + + + n n n n n n n n • • • Message content (Memory mapping) + + + + + + + + 0 1 2 3 4 5 6 7 Byte access (8 bits) SID10 to SID 6 SID5 to SID0 EID17 to EID14 EID13 to EID 6 EID5 to EID0 Data Length Code (DLC) Data byte 0 Data byte 1 • • • • • • • • • • • 16 16 16 16 16 16 16 16 Word access (16 bits) SID5 to SID0 SID10 to SID6 EID13 to EID6 EID17 to EID 14 Data Length Code (DLC) EID5 to EID0 Data byte 1 Data byte 0 • • • 006016 + n • 16 + 13 006016 + n • 16 + 14 006016 + n • 16 + 15 n = 0 to 15: the number of the slot Data byte 7 Data byte 6 Time stamp high-order byte Time stamp low-order byte Time stamp low-order byte Time stamp high-order byte Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 289 of 458 M16C/29 Group 17. CAN Module Figures 17.2 and 17.3 show the bit mapping in each slot in byte access and word access. The content of each slot remains unchanged unless transmission or reception of a new message is performed. bit 7 SID10 SID5 SID4 SID9 SID3 EID17 EID13 EID12 EID11 EID5 EID10 EID4 EID9 EID3 DLC3 Data Byte 0 Data Byte 1 SID8 SID2 EID16 EID8 EID2 DLC2 SID7 SID1 EID15 EID7 EID1 DLC1 bit 0 SID6 SID0 EID14 EID6 EID0 DLC0 Data Byte 7 Time Stamp high-order byte Time Stamp low-order byte CAN Data Frame: SID10 to 6 SID5 to 0 EID17 to 14 EID13 to 6 EID5 to 0 DLC3 to 0 Data Byte 0 Data Byte 1 Data Byte 7 NOTE: is read, the value is the one written upon the transmission slot configuration. 1. When The value is 0 when read on the reception slot configuration. Figure 17.2 Bit Mapping in Byte Access bit 15 bit 8 SID10 SID9 SID8 SID7 SID6 bit 7 bit 0 SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 Data Byte 0 Data Byte 2 Data Byte 4 Data Byte 6 Time Stamp high-order byte DLC3 DLC 2 DLC1 DLC0 Data Byte 1 Data Byte 3 Data Byte 5 Data Byte 7 Time Stamp low-order byte CAN Data Frame: SID10 to 6 SID5 to 0 EID17 to 14 EID13 to 6 EID5 to 0 DLC3 to 0 Data Byte 0 Data Byte 1 Data Byte 7 NOTE: 1. When is read, the value is the one written upon the transmission slot configuration. The value is "0" when read on the reception slot configuration. Figure 17.3 Bit Mapping in Word Access Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 290 of 458 M16C/29 Group 17. CAN Module 17.1.2 Acceptance Mask Registers Figures 17.4 and 17.5 show the C0GMR register, the C0LMAR register, and the C0LMBR register, in which bit mapping in byte access and word access are shown. bit 7 SID10 SID5 SID4 SID9 SID3 EID17 EID13 EID12 EID11 EID5 EID10 EID4 SID10 SID5 SID4 EID9 EID3 SID9 SID3 EID17 EID13 EID12 EID11 EID5 EID10 EID4 SID10 SID5 SID4 EID9 EID3 SID9 SID3 EID17 EID13 EID12 EID11 EID5 EID10 EID4 EID9 EID3 SID8 SID2 EID16 EID8 EID2 SID8 SID2 EID16 EID8 EID2 SID8 SID2 EID16 EID8 EID2 SID7 SID1 EID15 EID7 EID1 SID7 SID1 EID15 EID7 EID1 SID7 SID1 EID15 EID7 EID1 bit 0 SID6 SID0 EID14 EID6 EID0 SID6 SID0 EID14 EID6 EID0 SID6 SID0 EID14 EID6 EID0 Addresses CAN0 016016 016116 016216 016316 016416 016616 016716 016816 016916 016A16 016C16 016D16 016E16 016F16 017016 C0GMR register C0LMAR register C0LMBR register NOTES 1. is undefined. 2. These registers can be written in CAN reset/initialization mode of the CAN module. Figure 17.4 Bit Mapping of Mask Registers in Byte Access bit 15 bit 8 SID10 SID9 SID8 SID7 SID6 bit 7 bit 0 Addresses CAN0 016016 016216 016416 SID5 SID4 SID3 SID 2 SID1 SID 0 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID 2 SID1 SID 0 C0GMR register 016616 016816 016A16 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID 2 SID1 SID 0 C0LMAR register 016C16 016E16 017016 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 C0LMBR register NOTES: 1. is undefined. 2. These registers can be written in CAN reset/initialization mode of the CAN module. Figure 17.5 Bit Mapping of Mask Registers in Word Access Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 291 of 458 M16C/29 Group 17. CAN Module 17.1.3 CAN SFR Registers 17.1.3.1 C0MCTLj Register (j = 0 to 15) Figure 17.6 shows the C0MCTLj register. CAN0 message control register j ( j = 0 to 15) (4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0MCTL0 to C0MCTL15 Bit Symbol NewData Bit Name Successful reception flag Successful transmission flag Address 020016 to 020F16 After Reset 0016 Function RW RO (1) When set to reception slot 0: The content of the slot is read or still under processing by the CPU 1 The CAN module has stored new data in the slot When set to transmission slot 0: Transmission is not started or completed yet 1: Transmission is successfully completed SentData RO (1) InvalData When set to reception slot "Under reception" 0: The message is valid 1: The message is invalid flag (The message is being updated) When set to transmission slot "Under 0: Waiting for bus idle or completion of arbitration transmission" flag 1: Transmitting Overwrite flag Remote frame transmission/ reception status flag (2) Auto response lock mode select bit When set to reception slot 0: No message has been overwritten in this slot 1: This slot already contained a message, but it has been overwritten by a new one 0: Data frame transmission/reception status 1: Remote frame automatic transfer status RO TrmActive RO MsgLost RO (1) RemActive RW RspLock When set to reception remote frame slot 0: After a remote frame is received, it will be answered automatically 1: After a remote frame is received, no transmission will be started as long as this bit is set to 1 (Not responding) 0: Slot not corresponding to remote frame 1: Slot corresponding to remote frame 0: Not reception slot 1: Reception slot 0: Not transmission slot 1: Transmission slot RW Remote Remote frame corresponding slot select bit Reception slot request bit (3) Transmission slot request bit (3) RW RecReq RW TrmReq RW NOTES: 1. As for write, only writing 0 is possible. The value of each bit is written when the CAN module enters the respective state. 2. In Basic CAN mode, the slots 14 and 15 serve as data format identification flag. If the data frame is received, the RemActive bit is set to 0. If the remote frame is received, the bit is set to 1. 3. One slot cannot be defined as reception slot and transmission slot at the same time. 4. Set these registers only when the CAN module is in CAN operating mode. Figure 17.6 C0MCTLj Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 292 of 458 M16C/29 Group 17.1.3.2 C0CTLR Register Figure 17.7 shows the C0CTLR register. 17. CAN Module CAN0 Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0CTLR Bit Symbol Reset LoopBack MsgOrder BasicCAN BusErrEn Sleep PortEn (b7) Address 021016 Bit Name After reset X00000012 Function RW RW RW RW RW RW RW RW - 0: Operation mode CAN module reset bit (Note 1) 1: Reset/initialization mode Loop back mode select bit (2) Message order select bit (2) Basic CAN mode select bit (2) Bus error interrupt enable bit (2) Sleep mode select bit (2, 3) CAN port enable bit (2, 3) 0: Loop back mode disabled 1: Loop back mode enabled 0: Word access 1: Byte access 0: Basic CAN mode disabled 1: Basic CAN mode enabled 0: Bus error interrupt disabled 1: Bus error interrupt enabled 0: Sleep mode disabled 1: Sleep mode enabled; clock supply stopped 0: I/O port function 1: CTx/CRx function(4) Nothing is assigned. If necessary, set to 0. When read, the content is undefined NOTES: 1. When the Reset bit is set to 1 (CAN reset/initialization mode), check that the State_Reset bit in the C0STR register is set to 1 (Reset mode). 2. Change this bit only in the CAN reset/initialization mode. 3. When using CAN0 wake-up interrupt, set these bits to 1. 4. When the PortEn bit is set to 1, set the PD9_2 bit in the PD9 register to 0. (b15) b7 b6 b5 b4 b3 b2 b1 (b8) b0 Symbol C0CTLR Bit Symbol TSPreScale Bit1, Bit0 Address 021116 Bit Name b1 b0 After reset XX0X00002 Function RW Time stamp prescaler(3) 0 0: Period of 1 bit time 0 1: Period of 1/2 bit time 1 0: Period of 1/4 bit time 1 1: Period of 1/8 bit time RW TSReset RetBusOff (b4) Time stamp counter 0: In an idle state 1: Force reset of the time stamp counter reset bit(1) Return from bus off 0: In an idle state command bit(2) 1: Force return from bus off Nothing is assigned. If necessary, set to 0. When read, the content is undefined RW RW RW - RXOnly (b7-b6) Listen-only mode select bit (3) 0: Listen-only mode disabled 1: Listen-only mode enabled (4) Nothing is assigned. If necessary, set to 0. When read, the content is undefined NOTES: 1. When the TSReset bit is set to 1, the C0TSR register is set to 000016. After this, the bit is automatically set to 0. 2. When the RetBusOff bit is set to 1, registers C0RECR and C0TECR are set to 0016. After this, the bit is automatically set to 0. 3. Change this bit only in the CAN reset/initialization mode. 4. When the listen-only mode is selected, do not request the transmission. Figure 17.7 C0CTLR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 293 of 458 M16C/29 Group 17. CAN Module 17.1.3.3 C0STR Register Figure 17.8 shows the C0STR register. CAN0 Status Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0STR Bit Symbol Address 021216 Bit Name After Reset 0016 Function b3 b2 b1 b0 RW MBOX Active slot bits(1) 0 0 0 0: Slot 0 0 0 0 1: Slot 1 0 0. 1 0: Slot 2 . . 1 1 1 0: Slot 14 1 1 1 1: Slot 15 0: No [successful] transmission 1: The CAN module has transmitted a message successfully RO TrmSucc Successful transmission flag(1) RO RecSucc TrmState RecState Successful reception 0: No [successful] reception (1) flag 1: CAN module received a message successfully Transmission flag (Transmitter) Reception flag (Receiver) 0: CAN module is idle or receiver 1: CAN module is transmitter 0: CAN module is idle or transmitter 1: CAN module is receiver RO RO RO NOTE: 1. These bits can be changed only when a slot which an interrupt is enabled by the C0ICR register is transmitted or received successfully. (b15) b7 (b8) b0 b6 b5 b4 b3 b2 b1 Symbol C0STR Bit Symbol State_Reset State_ LoopBack State_ MsgOrder State_ BasicCAN State_ BusError State_ ErrPass State_ BusOff (b7) Address 021316 Bit Name Reset state flag Loop back state flag Message order state flag Basic CAN mode state flag Bus error state flag Error passive state flag Error bus off state flag After Reset X00000012 Function 0: Operation mode 1: Reset mode 0: Loop back mode disabled 1: Loop back mode enabled 0: Word access 1: Byte access 0: Basic CAN mode disabled 1: Basic CAN mode enabled 0: No error has occurred. 1: A CAN bus error has occurred. 0: The CAN module is not in error passive state. 1: The CAN module is in error passive state. 0: The CAN module is not in error bus off state. 1: The CAN module is in error bus off state. RW RO RO RO RO RO RO RO - Nothing is assigned. If necessary, set to 0. When read, the content is undefined Figure 17.8 C0STR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 294 of 458 M16C/29 Group 17.1.3.4 C0SSTR Register Figure 17.9 shows the C0SSTR register. 17. CAN Module CAN0 Slot Status Register (b15) b7 (b8) b0 b7 b0 Symbol C0SSTR Address 021516, 021416 After Reset 000016 Function Setting Values RW Slot status bits Each bit corresponds to the slot with the same number 0: Reception slot The message has been read. Transmission slot Transmission is not completed. 1: Reception slot The message has not been read. Transmission slot Transmission is completed RO Figure 17.9 C0SSTR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 295 of 458 M16C/29 Group 17. CAN Module 17.1.3.5 C0ICR Register Figure 17.10 shows the C0ICR register. CAN0 Interrupt Control Register (1) (b15) b7 (b8) b0 b7 b0 Symbol C0ICR Address 021716, 021616 After Reset 000016 Function Setting Values RW 0: Interrupt disabled Interrupt enable bits: 1: Interrupt enabled Each bit corresponds with a slot with the same number. Enabled/disabled of successful transmission interrupt or successful reception interrupt can be selected NOTE: 1. Set the C0ICR register only when the CAN module is in CAN operating mode. RW Figure 17.10 C0ICR Register 17.1.3.6 C0IDR Register Figure 17.11 shows the C0IDR register. CAN0 extended ID register (1) (b15) b7 (b8) b0 b7 b0 Symbol C0IDR Address 021916, 021816 After Reset 000016 Function Extended ID bits: Each bit corresponds with a slot with the same number. Selection of the ID format that each slot handles NOTE: 1. Set the C0IDR register only when the CAN module is in CAN operating mode. Setting Values RW 0: Standard ID 1: Extended ID RW Figure 17.11 C0IDR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 296 of 458 M16C/29 Group 17.1.3.7 C0CONR Register Figure 17.12 shows the C0CONR register. 17. CAN Module CAN0 Configuration Register(2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0CONR Bit symbol Address 021A16 Bit name After reset Undefined Function b3 b2 b1 b0 RW BRP Prescaler division ratio select bits 0 0 0 0: Divide-by-1 of fCAN 0 0 0 1: Divide-by-2 of fCAN 0 0 1 0: Divide-by-3 of fCAN 1 1 1 0: Divide-by-15 of fCAN 1 1 1 1: Divide-by-16 of fCAN (1) ..... RW SAM Sampling control bit 0: One time sampling 1: Three times sampling b7 b6 b5 RW PTS Propagation time segment control bits 0 0 0: 1Tq 0 0 1: 2Tq 0 1 0: 2Tq 1 1 0: 7Tq 1 1 1: 8Tq ..... RW NOTES: 1. fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bits (i = 0 to 2) in the CCLKR register. 2. Set the C0CONR register only when the CAN module is in CAN reset / initialization mode. (b15) b7 b6 b5 b4 b3 b2 b1 (b8) b0 Symbol C0CONR Bit symbol Address 021B16 Bit name After Reset Undefined Function b2 b1b0 RW PBS1 Phase buffer segment 1 control bits 0 0 0: Do not set 0 0 1: 2Tq 0 1 0: 3Tq 1 1 0: 7Tq 1 1 1: 8Tq ..... RW b5 b4 b3 PBS2 Phase buffer segment 2 control bits 0 0 0: Do not set 0 0 1: 2Tq 0 1 0: 3Tq 1 1 0: 7Tq 1 1 1: 8Tq ..... RW b7 b6 SJW Resynchronization jump width control bits 0 0 1 1 0: 1Tq 1: 2Tq 0: 3Tq 1: 4Tq RW Figure 17.12 C0CONR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 297 of 458 M16C/29 Group 17. CAN Module 17.1.3.8 C0RECR Register Figure 17.13 shows the C0RECR register. CAN0 Receive Error Count Register b7 b0 Symbol C0RECR Address 021C16 After Reset 0016 Function Reception error counting function The value is incremented or decremented according to the CAN module's error status NOTE: 1. The value is undefined in bus off state. Counter Value RW RO 0016 to FF16 (1) Figure 17.13 C0RECR Register 17.1.3.9 C0TECR Register Figure 17.14 shows the C0TECR register. CAN0 Transmit Error Count Register (1) b7 b0 Symbol C0TECR Address 021D16 After Reset 0016 Function Transmission error counting function The value is incremented or decremented according to the CAN module's error status NOTE: 1. The value is undefined in bus off state. Counter Value 0016 to FF16(1) RW RO Figure 17.14 C0TECR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 298 of 458 M16C/29 Group 17.1.3.10 C0TSR Register Figure 17.15 shows the C0TSR register. 17. CAN Module CAN0 Time Stamp Register(1) (b15) b7 (b8) b0 b7 b0 Symbol C0TSR Address 021F16, 021E16 After Reset 000016 Function Time stamp function NOTE: 1. Use a 16-bit data for reading. Counter Value RW RO 000016 to FFFF16 Figure 17.15 C0TSR Register 17.1.3.11 C0AFS Register Figure 17.16 shows the C0AFS register. CAN0 Acceptance Filter Support Register (b15) b7 (b8) b0 b7 b0 Symbol C0AFS Address 024316, 024216 After reset Undefined Function Write the content equivalent to the standard frame ID of the received message. The value is "converted standard frame ID" when read Setting Values RW Standard frame ID RW Figure 17.16 C0AFS Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 299 of 458 M16C/29 Group 17. CAN Module 17.2 Operating Modes The CAN module has the following four operating modes. • CAN Reset/Initialization Mode • CAN Operating Mode • CAN Sleep Mode • CAN Interface Sleep Mode Figure 17.17 shows transition between operating modes. MCU Reset CAN reset/initialization mode State_Reset = 1 Reset = 0 CAN operating mode Reset = 1 State_Reset = 0 Sleep = 0 Sleep = 1 TEC > 255 CCLK3 = 1 CAN interface sleep mode CCLK3 = 0 CCLK3: Bit in the CCLKR register Reset, Sleep, RetBusOff: Bits in the C0CTLR register State_Reset, tate_BusOff: Bits in the C0STR register CAN sleep mode Reset = 1 when 11 consecutive recessive bits are detected 128 times or RetBusOff = 1 Bus off state State_BusOff = 1 Figure 17.17 Transition Between Operating Modes 17.2.1 CAN Reset/Initialization Mode The CAN reset/initialization mode is activated upon MCU reset or by setting the Reset bit in the C0CTLR register to 1. If the Reset bit is set to 1, check that the State_Reset bit in the C0STR register is set to 1. Entering the CAN reset/initialization mode initiates the following functions by the module: • CAN communication is impossible. • When the CAN reset/initialization mode is activated during an ongoing transmission in operation mode, the module suspends the mode transition until completion of the transmission (successful, arbitration loss, or error detection). Then, the State_Reset bit is set to 1, and the CAN reset/ initialization mode is activated. • Registers C0MCTLj (j = 0 to 15), C0STR, C0ICR, C0IDR, C0RECR, C0TECR, and C0TSR are initialized. All these registers are locked to prevent CPU modification. • Registers C0CTLR, C0CONR, C0GMR, C0LMAR, and C0LMBR and the CAN0 message box retain their contents and are available for CPU access. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 300 of 458 M16C/29 Group 17. CAN Module 17.2.2 CAN Operating Mode The CAN operating mode is activated by setting the Reset bit in the C0CTLR register to 0. If the Reset bit is set to 0, check that the State_Reset bit in the C0STR register is set to 0. If 11 consecutive recessive bits are detected after entering the CAN operating mode, the module initiates the following functions: • The module's communication functions are released and it becomes an active node on the network and may transmit and receive CAN messages. • Release the internal fault confinement logic including receive and transmit error counters. The module may leave the CAN operating mode depending on the error counts. Within the CAN operating mode, the module may be in three different sub modes, depending on which type of communication functions are performed: • Module idle : The modules receive and transmit sections are inactive. • Module receives : The module receives a CAN message sent by another node. • Module transmits : The module transmits a CAN message. The module may receive its own message simultaneously when the LoopBack bit in the C0CTLR register = 1 (Loop back mode enabled). Figure 17.18 shows sub modes of the CAN operating mode. Module idle TrmState = 0 RecState = 0 Start transmission Finish transmission Finish reception Detect an SOF Module transmits TrmState = 1 RecState = 0 Module receives TrmState = 0 RecState = 1 Lost in arbitration TrmState, RecState: Bits in the C0STR register Figure 17.18 Sub Modes of CAN Operating Mode 17.2.3 CAN Sleep Mode The CAN sleep mode is activated by setting the Sleep bit in the C0CTLR register to 1. It should never be activated from the CAN operating mode but only via the CAN reset/initialization mode. Entering the CAN sleep mode instantly stops the clock supply to the module and thereby reduces power dissipation. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 301 of 458 M16C/29 Group 17. CAN Module 17.2.4 CAN Interface Sleep Mode The CAN interface sleep mode is activated by setting the CCLK3 bit in the CCLKR register to 1. It should never be activated but only via the CAN sleep mode. Entering the CAN interface sleep mode instantly stops the clock supply to the CPU Interface in the module and thereby reduces power dissipation. 17.2.5 Bus Off State The bus off state is entered according to the fault confinement rules of the CAN specification. When returning to the CAN operating mode from the bus off state, the module has the following two cases. In this time, the value of any CAN registers, except registers C0STR, C0RECR, and C0TECR, does not change. (1) When 11 consecutive recessive bits are detected 128 times The module enters instantly into error active state and the CAN communication becomes possible immediately. (2) When the RetBusOff bit in the C0CTLR register = 1 (Force return from buss off) The module enters instantly into error active state, and the CAN communication becomes possible again after 11 consecutive recessive bits are detected. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 302 of 458 M16C/29 Group 17. CAN Module 17.3 Configuration of the CAN Module System Clock The M16C/29 Group has a CAN module system clock select circuit. Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bit in the C0CONR register. For the CCLKR register, refer to 7. Clock Generation Circuit. Figure 17.19 shows a block diagram of the clock generation circuit of the CAN module system. f1 Divide-by-1 (undivided) Divide-by-2 Divide-by-4 Divide-by-8 Value: 1, 2, 4, 8, 16 Divide-by-16 CAN module system clock divider fCAN Prescaler 1/2 Baud rate prescaler division value :P+1 fCANCLK CCLKR register fCAN: CAN module system clock P: The value written in the BRP bit of the C0CONR register. P = 0 to 15 fCANCLK: CAN communication clock fCANCLK = fCAN/2(P + 1) CAN module Figure 17.19 Block Diagram of CAN Module System Clock Generation Circuit 17.3.1 Bit Timing Configuration The bit time consists of the following four segments: • Synchronization segment (SS) This serves for monitoring a falling edge for synchronization. • Propagation time segment (PTS) This segment absorbs physical delay on the CAN network which amounts to double the total sum of delay on the CAN bus, the input comparator delay, and the output driver delay. • Phase buffer segment 1 (PBS1) This serves for compensating the phase error. When the falling edge of the bit falls later than expected, the segment can become longer by the maximum of the value defined in SJW. • Phase buffer segment 2 (PBS2) This segment has the same function as the phase buffer segment 1. When the falling edge of the bit falls earlier than expected, the segment can become shorter by the maximum of the value defined in SJW. Figure 17.20 shows the bit timing. Bit time SS PTS PBS1 SJW Sampling point PBS2 SJW The range of each segment: Bit time = 8 to 25Tq SS = 1Tq PTS = 1Tq to 8Tq PBS1 = 2Tq to 8Tq PBS2 = 2Tq to 8Tq SJW = 1Tq to 4Tq Configuration of PBS1 and PBS2: PBS1 ≥ PBS2 PBS1 ≥ SJW PBS2 ≥ 2 when SJW = 1 PBS2 ≥ SJW when 2 ≤ SJW ≤ 4 Figure 17.20 Bit Timing Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 303 of 458 M16C/29 Group 17. CAN Module 17.3.2 Bit-rate Bit-rate depends on f1, the division value of the CAN module system clock, the division value of the baud rate prescaler, and the number of Tq of one bit. Table 17.2 shows the examples of bit-rate. Table 17.2 Examples of Bit-rate Bit-rate 20MHz 1Mbps 10Tq (1) 500kbps 10Tq (2) 20Tq (1) 125kbps 10Tq (8) 20Tq (4) 83.3kbps 10Tq (12) 20Tq (6) 33.3kbps 10Tq (30) 20Tq (15) NOTE: 1. The number in ( ) indicates a value of “fCAN division value” multiplied by “baud rate prescaler division value”. 16MHz 8Tq (1) 8Tq (2) 16Tq (1) 8Tq (8) 16Tq (4) 8Tq (12) 16Tq (6) 8Tq (30) 16Tq (15) 10MHz 10Tq (1) 10Tq (4) 20Tq (2) 10Tq (6) 20Tq (3) 10Tq (15) - 8MHz 8Tq (1) 8Tq (4) 16Tq (2) 8Tq (6) 16Tq (3) 8Tq (15) - Calculation of Bit-rate f1 2 ✕ “fCAN division value (Note 1)” ✕ “baud rate prescaler division value (Note 2)” ✕ “number of Tq of one bit” Note 1: fCAN division value = 1, 2, 4, 8, 16 fCAN division value: a value selected in the CCLKR register Note 2: Baud rate prescaler division value = P + 1 (P: 0 to 15) P: a value selected in the BRP bit in the C0CONR register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 304 of 458 M16C/29 Group 17. CAN Module 17.4 Acceptance Filtering Function and Masking Function These functions serve the users to select and receive a facultative message. The C0GMR register, the C0LMAR register, and the C0LMBR register can perform masking to the standard ID and the extended ID of 29 bits. The C0GMR register corresponds to slots 0 to 13, the C0LMAR register corresponds to slot 14, and the C0LMBR register corresponds to slot 15. The masking function becomes valid to 11 bits or 29 bits of a received ID according to the value in the corresponding slot of the C0IDR register upon acceptance filtering operation. When the masking function is employed, it is possible to receive a certain range of IDs. Figure 17.21 shows correspondence of the mask registers and slots, Figure 17.22 shows the acceptance function. C0GMR register Slot #0 Slot #1 Slot #2 Slot #3 Slot #4 Slot #5 Slot #6 Slot #7 Slot #8 Slot #9 Slot #10 Slot #11 Slot #12 Slot #13 Slot #14 Slot #15 C0LMAR register C0LMBR register Figure 17.21 Correspondence of Mask Registers to Slots ID stored in ID of the the slot received message The value of the mask register Mask Bit Values 0: ID (to which the received message corresponds) match is handled as "Don't care" 1: ID (to which the received message corresponds) match is checked Acceptance Signal Acceptance judge signal 0: The CAN module ignores the current incoming message (Not stored in any slot) 1: The CAN module stores the current incoming message in a slot of which ID matches Figure 17.22 Acceptance Function When using the acceptance function, note the following points. (1) When one ID is defined in two slots, the one with a smaller number alone is valid. (2) When it is configured that slots 14 and 15 receive all IDs with Basic CAN mode, slots 14 and 15 receive all IDs which are not stored into slots 0 to 13. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 305 of 458 M16C/29 Group 17. CAN Module 17.5 Acceptance Filter Support Unit (ASU) The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search. The IDs to receive are registered in the data table; a received ID is stored in the C0AFS register, and table search is performed with a decoded received ID. The acceptance filter support unit can be used for the IDs of the standard frame only. The acceptance filter support unit is valid in the following cases. • When the ID to receive cannot be masked by the acceptance filter. (Example) IDs to receive: 07816, 08716, 11116 • When there are too many IDs to receive; it would take too much time to filter them by software. Figure 17.23 shows the write and read of the C0AFS register in word access. bit 15 bit 8 SID10 SID9 SID8 SID7 SID6 bit 7 bit 0 SID5 SID4 SID3 SID2 SID1 SID 0 Address CAN0 24216 When write 3/8 Decoder bit 15 bit 8 bit 7 bit 0 24216 When read SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID 3 Figure 17.23 Write/read of C0AFS Register in Word Access Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 306 of 458 M16C/29 Group 17. CAN Module 17.6 BasicCAN Mode When the BasicCAN bit in the C0CTLR register is set to 1 (Basic CAN mode enabled), slots 14 and 15 correspond to Basic CAN mode. During normal operations, individual slots can select either data frame or remote frame by CPU setting. However, in Basic CAN mode, both frames can be selected. When slots 14 and 15 are defined as reception slots in Basic CAN mode, received messages are stored in slots 14 and 15 alternately. The received message data format can be determined by the RemActive bit in the C0MCTLj register (j = 0 to 15). Figure 17.24 shows the operation of slots 14 and 15 in Basic CAN mode. Slot 14 Slot 15 Empty Locked (empty) Msg n Locked (empty) Locked (Msg n) Msg n + 1 Msg n+2 (Msg n lost) Locked (Msg n+1) Msg n Msg n+1 Msg n+2 Figure 17.24 Operation of Slots 14 and 15 in Basic CAN Mode When using Basic CAN mode, note the following points. (1) Setting of Basic CAN mode has to be done in CAN reset/initialization mode. (2) Select the same ID for slots 14 and 15. Also, setting of the C0LMAR and C0LMBR register has to be the same. (3) Define slots 14 and 15 as reception slot only. (4) There is no protection available against message overwrite. A message can be overwritten by a new message. (5) Slots 0 to 13 can be used in the same way as in normal CAN operating mode. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 307 of 458 M16C/29 Group 17. CAN Module 17.7 Return from Bus off Function When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by setting the RetBusOff bit in the C0CTLR register to 1 (Force return from bus off). At this time, the error state changes from bus off state to error active state. If the RetBusOff bit is set to 1, registers C0RECR and C0TECR are initialized and the State_Reset bit in the C0STR register is set to 0 (The CAN module is not in error bus off state). However, registers of the CAN module such as C0CONR register and the content of each slot are not initialized. 17.8 Time Stamp Counter and Time Stamp Function When the C0TSR register is read, the value of the time stamp counter at the moment is read. The period of the time stamp counter reference clock is the same as that of 1 bit time that is configured by the C0CONR register. The time stamp counter functions as a free run counter. The 1 bit time period can be divided by 1 (undivided), 2, 4 or 8 to produce the time stamp counter reference clock. Use the TSPreScale bit in the C0CTLR register to select the divide-by-n value. The time stamp counter is equipped with a register that captures the counter value when the protocol controller regards it as a successful reception. The captured value is stored when a time stamp value is stored in a reception slot. 17.9 Listen-Only Mode When the RXOnly bit in the C0CTLR register is set to 1, the module enters listen-only mode. In listen-only mode, no transmission -- data frames, error frames, and ACK response -- is performed to bus. When listen-only mode is selected, do not request the transmission. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 308 of 458 M16C/29 Group 17. CAN Module 17.10 Reception and Transmission Configuration of CAN Reception and Transmission Mode Table 17.3 shows configuration of CAN reception and transmission mode. Table 17.3 Configuration of CAN Reception and Transmission Mode TrmReq RecReq Remote RspLock 0 0 1 0 1 0 0 1 0 0 Communication mode of the slot Communication environment configuration mode: configure the communication mode of the slot. Configured as a reception slot for a data frame. Configured as a transmission slot for a remote frame. (At this time the RemActive = 1.) After completion of transmission, this functions as a reception slot for a data frame. (At this time the RemActive = 0.) However, when an ID that matches on the CAN bus is detected before remote frame transmission, this immediately functions as 1 0 0 1 0 1 0 1/0 a reception slot for a data frame. Configured as a transmission slot for a data frame. Configured as a reception slot for a remote frame. (At this time the RemActive = 1.) After completion of reception, this functions as a transmission slot for a data frame. (At this time the RemActive = 0.) However, transmission does not start as long as RspLock bit remains 1; thus no automatic response. Response (transmission) starts when the RspLock bit is set to 0. TrmReq, RecReq, Remote, RspLock, RemActive, RspLock: Bits in the C0MCTLj register (j = 0 to 15) When configuring a slot as a reception slot, note the following points. (1) Before configuring a slot as a reception slot, be sure to set the C0MCTLj register (j = 0 to 15) to 0016. (2) A received message is stored in a slot that matches the condition first according to the result of reception mode configuration and acceptance filtering operation. Upon deciding in which slot to store, the smaller the number of the slot is, the higher priority it has. (3) In normal CAN operating mode, when a CAN module transmits a message of which ID matches, the CAN module never receives the transmitted data. In loop back mode, however, the CAN module receives back the transmitted data. In this case, the module does not return ACK. When configuring a slot as a transmission slot, note the following points. (1) Before configuring a slot as a transmission slot, be sure to set the C0MCTLj registers to 0016. (2) Set the TrmReq bit in the C0MCTLj register to 0 (not transmission slot) before rewriting a transmission slot. (3) A transmission slot should not be rewritten when the TrmActive bit in the C0MCTLj register is 1 (transmitting). If it is rewritten, an undefined data will be transmitted. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 309 of 458 M16C/29 Group 17. CAN Module 17.10.1 Reception Figure 17.25 shows the behavior of the module when receiving two consecutive CAN messages, that fit into the slot of the shown C0MCTLj register (j = 0 to 15) and leads to losing/overwriting of the first message. SOF ACK EOF IFS SOF ACK EOF IFS CANbus RecReq bit InvalData bit NewData bit MsgLost bit CAN0 Successful Reception Interrupt RecState bit RecSucc bit MBOX bit Receive slot No. (1) (3) (2) (5) (2) (4) (5) (5) j = 0 to 15 Figure 17.25 Timing of Receive Data Frame Sequence (1) On monitoring a SOF on the CAN bus the RecState bit in the C0STR register becomes 1 (CAN module is receiver) immediately, given the module has no transmission pending. (2) After successful reception of the message, the NewData bit in the C0MCTLj register (j = 0 to 15) of the receiving slot becomes 1 (stored new data in slot). The InvalData bit in the C0MCTLj register becomes 1 (message is being updated) at the same time and the InvalData bit becomes 0 (message is valid) again after the complete message was transferred to the slot. (3) When the interrupt enable bit in the C0ICR register of the receiving slot = 1 (interrupt enabled), the CAN0 successful reception interrupt request is generated and the MBOX bit in the C0STR register is changed. It shows the slot number where the message was stored and the RecSucc bit in the C0STR register is active. (4) Read the message out of the slot after setting the New Data bit to 0 (the content of the slot is read or still under processing by the CPU) by program. (5) If the NewData bit is set to 0 by program or the next CAN message is received successfully before the receive request for the slot is canceled, the MsgLost bit in the C0MCTLj register is set to 1 (message has been overwritten). The new received message is transferred to the slot. Generating of an interrupt request and change of the C0STR register are same as in 3). Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 310 of 458 C0STR register C0MCTLj register M16C/29 Group 17. CAN Module 17.10.2 Transmission Figure 17.26 shows the timing of the transmit sequence. SOF ACK EOF IFS SOF CTx TrmReq bit TrmActive bit SentData bit CAN0 Successful Transmission Interrupt TrmState bit TrmSucc bit MBOX bit (1) (2) (1) (4) (1) (2) (3) (3) (3) Transmission slot No. j = 0 to 15 Figure 17.26 Timing of Transmit Sequence (1) If the TrmReq bit in the C0MCTLj register (j = 0 to 15) is set to 1 (Transmission slot) in the bus idle state, the TrmActive bit in the C0MCTLj register and the TrmState bit in the C0STR register are set to 1 (Transmitting/Transmitter), and CAN module starts the transmission. (2) If the arbitration is lost after the CAN module starts the transmission, the TrmActive and TrmState bits are set to 0. (3) If the transmission has been successful without lost in arbitration, the SentData bit in the C0MCTLj register is set to 1 (Transmission is successfully completed) and TrmActive bit in the C0MCTLj register is set to 0 (Waiting for bus idle or completion of arbitration). And when the interrupt enable bits in the C0ICR register = 1 (Interrupt enabled), CAN0 successful transmission interrupt request is generated and the MBOX (the slot number which transmitted the message) and TrmSucc bit in the C0STR register are changed. (4) When starting the next transmission, set bits SentData and TrmReq to 0. And set the TrmReq bit to 1 after checking that bits SentData and TrmReq are set to 0. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 311 of 458 C0STR register C0MCTLj register M16C/29 Group 17. CAN Module 17.11 CAN Interrupts The CAN module provides the following CAN interrupts. • CAN0 Successful Reception Interrupt • CAN0 Successful Transmission Interrupt • CAN0 Error Interrupt Error Passive State Error BusOff State Bus Error (this feature can be disabled separately) • CAN0 Wake-up Interrupt When the CPU detects the CAN0 successful reception/transmission interrupt request, the MBOX bit in the C0STR register must be read to determine which slot has generated the interrupt request. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 312 of 458 M16C/29 Group 18. CRC Calculation Circuit 18. CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation detects errors in blocks of data. The MCU uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) or CRC-16 (X16 + X15 + X2 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of bytes. The code is updated in the CRC data register everytime one byte of data is transferred to a CRC input register. The data register must be initialized before use. Generation of CRC code for one byte of data is completed in two machine cycles. Figure 18.1 shows the block diagram of the CRC circuit. Figure 18.2 shows the CRC-related registers. Figure 18.3 shows the calculation example using the CRC_CCITT operation. 18.1 CRC Snoop The CRC circuit includes the ability to snoop reads and writes to certain SFR addresses. This can be used to accumulate the CRC value on a stream of data without using extra bandwidth to explicitly write data into the CRCIN register. All SFR addresses after 002016 are subject to the CRC snoop. The CRC snoop is useful to snoop the writes to a UART TX buffer, or the reads from a UART RX buffer. To snoop an SFR address, the target address is written to the CRC snoop Address Register (CRCSAR). The two most significant bits of this register enable snooping on reads or writes to the target address. If the target SFR is written to by the CPU or DMA, and the CRC snoop write bit is set (CRCSW=1), the CRC will latch the data into the CRCIN register. The new CRC code will be set in the CRCD register. Similarly, if the target SFR is read by the CRC or DMA, and the CRC snoop read bit is set (CRCSR=1), the CRC will latch the data from the target into the CRCIN register and calculate the CRC. The CRC circuit can only calculate CRC codes on data byte at a time. Therefore, if a target SFR is accessed in word (16 bit), only one low-order byte data is stored into the CRCIN register. Data bus high-order Data bus low-order Eight low-order bits CRCD register (16) Eight high-order bits (Address 03BD16, 03BC16) x 16 CRC code generating circuit + x12 + x5 + 1 OR x16 + x15 + x2 + 1 Snoop Address SnoopB lock CRC input register (8) (Address 03BE16) Equal? Snoop enable Address Bus Figure 18.1 CRC circuit block diagram Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 313 of 458 M16C/29 Group 18. CRC Calculation Circuit CRC Data Register (b15) b7 (b8) b0 b7 b0 Symbol CRCD Address 03BD16 to 03BC16 After Reset Undefined Function CRC calculation result output Setting Range RW 000016 to FFFF16 RW CRC Input Register b7 b0 Symbol CRCIN Address 03BE16 Function After Reset Undefined Setting Range RW 0016 to FF16 Data input RW CRC Mode Register b7 b0 Symbol CRCMR Bit symbol Bit Symbol CRCPS CRCPS Address 03B616 Bit name Bit Name After Reset 0XXXXXX02 Function RW RW 0: X16+X12+X5+1 (CRC-CCITT) CRC mode polynomial CRC mode polynomial selection bitbit selection 1: X16+X15+X2+1 (CRC-16) Nothing Nothing is assigned. is assigned. If necessary, set to 0. (b6-b1) Write "0" when When read, the content is undefined writing to this bit. The value is indeterminate if read. 0: LSB first CRC mode selection CRCMS CRCMS CRC mode selection bitbit 1: MSB first RW SFR Snoop Address Register (b15) b7 (b8) b0 b7 b0 Symbol CRCSAR Bit Symbol CRCSAR9-0 (b13-b10) CRCSR CRCSW Address 03B516 to 03B416 Bit Name CRC mode polynomial selection bit After Reset 00XXXXXX XXXXXXXX2 Function Function RW RW SFR address to snoop Nothing is assigned. If necessary, set to 0. When read, the content is undefined CRC snoop on read enable bit CRC snoop on write enable bit 0: Disabled 1: Enabled(1) 0: Disabled 1: Enabled(1) RW RW NOTE: 1. Set bits CRCSR and CRCSW to 0 if the PLC07 bit in the PLC0 register is set to 1 (PLL on) and the PM20 bit in the PM2 register is set to 0 (SFR access 2 wait). Figure 18.2. CRCD, CRCIN, CRCMR, CRCSAR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 314 of 458 M16C/29 Group 18. CRC Calculation Circuit b15 b0 (1) Setting 000016 (initial value) CRD data register CRCD [03BD16, 03BC16] b7 b0 (2) Setting 0116 CRC input register CRCIN [03BE16] 2 cycles After CRC calculation is complete b15 b0 118916 CRD data register CRCD [03BD16, 03BC16] Stores CRC code The code resulting from sending 0116 in LSB first mode is (10000 0000).This the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000)X16 by ( 1 0001 0000 0010 0001) in conformity with the modulo-2 operation. Modulo-2 operation is operation that complies with the law given below. 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1 MSB LSB 1 0001 0000 0010 0001 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 LSB 0000 0000 0000 0001 0001 1000 1000 0000 1 1000 0000 1000 0000 0 1 1000 MSB 9 8 1 1 Thus the CRC code becomes ( 1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary, set the CRC mode selection bit to 1. CRC data register stores CRC code for MSB first mode. b7 b0 (3) Setting 2316 CRC input register CRCIN [03BE16] After CRC calculation is complete b15 b0 0A4116 CRD data register CRCD [03BD16, 03BC16] Stores CRC code Figure 18.3. CRC Calculation Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 315 of 458 M16C/29 Group 19. Programmable I/O Ports 19. Programmable I/O Ports Note Ports P04 to P07, P10 to P14 , P34 to P37 and P95 to P97 are not available in 64-pin package. The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 71 lines P0, P1, P2, P3, P6, P7, P8, P9, P10 (except P94) for the 80-pin package, or 55 lines P00 to P03, P15 to P17, P2, P30 to P33, P6, P7, P8, P90 to P93, P10 for the 64-pin package. Each port can be set for input or output every line by using a direction register, and can also be chosen to be or not be pulled high in sets of 4 lines. Figures 19.1 to 19.4 show the I/O ports. Figure 19.5 shows the I/O pins. Each pin functions as an I/O port, a peripheral function input/output. For details on how to set peripheral functions, refer to each functional description in this manual. If any pin is used as a peripheral function input, set the direction bit for that pin to 0 (input mode). Any pin used as an output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set. 19.1 Port Pi Direction Register (PDi Register, i = 0 to 3, 6 to 10) Figure 19.6 shows the direction registers. This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port. 19.2 Port Pi Register (Pi Register, i = 0 to 3, 6 to 10) Figure 19.7 shows the Pi registers. Data input/output to and from external devices are accomplished by reading and writing to the Pi register. The Pi register consists of a port latch to hold the output data and a circuit to read the pin status. For ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data can be written to the port latch by writing to the Pi register. The data written to the port latch is output from the pin. The bits in the Pi register correspond one for one to each port. 19.3 Pull-up Control Register 0 to 2 (PUR0 to PUR2 Registers) Figure 19.8 shows registers PUR0 to PUR2. Registers PUR0 to PUR2 select whether the pins, divided into groups of four pins, are pulled up or not. The pins, selected by setting the bits in registers PUR0 to PUR2 to 1 (pull-up), are pulled up when the direction registers are set to 0 (input mode). The pins are pulled up regardless of the pins’ function. 19.4 Port Control Register (PCR Register) Figure 19.9 shows the port control register. When the P1 register is read after setting the PCR0 bit in the PCR register to 1, the corresponding port latch can be read no matter how the PD1 register is set. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 316 of 458 M16C/29 Group 19. Programmable I/O Ports 19.5 Pin Assignment Control Register (PACR) Figure 19.10 shows the PACR register. After reset, set bits PACR2 to PACR0 in the PACR register before a signal is input or output to each pin. When bits PACR2 to PACR0 are not set, some pins do not function as I/O ports. Bits PACR2 to PACR0: control pins to be used Value after reset: 0002. To select the 80-pin package, set the bits to 0112. To select the 64-pin package, set the bits to 0102. U1MAP bit: controls pin assignments for the UART1 function. _________ _________ To assign the UART1 function to P64/CTS1/RTS1, P65/CLK1, P66/RxD1, and P67/TxD1, set the U1MAP bit to 0 (P67 to P64). ________ ________ To assign the function to P70/CTS1/RTS1, P71/CLK1, P72/RxD1, and P73/TxD1, set the U1MAP bit to 1 (P73 to P70) The PRC2 bit in the PRCR protects the PACR register. Set the PACR register after setting the PRC2 bit in the PRCR register. 19.6 Digital Debounce Function Two digital debounce function circuits are provided. Level is determined when level is held, after applying either a falling edge or rising edge to the pin, longer than the programmed filter width time. This enables noise reduction. ________ _______ _____ This function is assigned to INT5/INPC17 and NMI/SD. Digital filter width is set in the NDDR register and the P17DDR register respectively. Figure 19.11 shows the NDDR register and the P17DDR register. Additionally, a digital debounce function is disabled to the port P17 input and the port P85 input. Filter width : (n+1) x 1/f8 n: count value set in the NDDR register and P17DDR register The NDDR register and the P17DDR register decrement count value with f8 as the count source. The NDDR register and the P17DDR register indicate count time. Count value is reloaded if a falling edge or a rising edge is applied to the pin. The NDDR register and the P17DDR register can be set 0016 to FF16 when using the digital debounce function. Setting to FF16 disables the digital filter. See Figure 19.12 for details. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 317 of 458 M16C/29 Group 19. Programmable I/O Ports Pull-up selection P00 to P07, (inside dotted-line included) P100 to P103 Data bus P30 to P37 (inside dotted-line not included) Direction register Port latch (1) Analog input Pull-up selection P10 to P13 (inside dotted-line included) Direction register Port P1 control register Data bus P14 (inside dotted-line not included) Port latch (1) Analog input Pull-up selection P15, P16 (inside dotted-line not included) Direction register Port P1 control register Data bus P17 (inside dotted-line included) Port latch (1) Input to respective peripheral functions INPC17/INT5 Digital debounce Pull-up selection P22 to P27, P30, P60, P61, P64, P65, P74 to P76, P80, P81 (inside dotted-line included) Data bus Direction register "1" Output Port latch (1) P32 (inside dotted-line not included) Input to respective peripheral functions NOTE: 1. symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 19.1 I/O Ports (1) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 318 of 458 M16C/29 Group 19. Programmable I/O Ports Pull-up selection P20, P21, P70 to P73 Data bus Direction register "1" Output Port latch Switching between CMOS and Nch Input to respective peripheral functions Pull-up selection Direction register (1) P82 to P84 Data bus Port latch (1) Input to respective peripheral functions Pull-up selection P31, P62, P66, P77 Data bus Direction register Port latch (1) Input to respective peripheral functions NOTE: 1. symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 19.2 I/O Ports (2) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 319 of 458 M16C/29 Group 19. Programmable I/O Ports Pull-up selection P63, P67 Direction register “1” Output Data bus Port latch (1) Switching between CMOS and Nch P85 Pull-up selection NMI Enable Direction register Data bus Port latch (1) NMI Interrupt Input NMI Enable SD Digital Debounce P91, P92, P97, P104 to P107 Pull-up selection Direction register Data bus Port latch (1) Analog input Input to respective peripheral functions NOTE: 1. symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 19.3 I/O Ports (3) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 320 of 458 M16C/29 Group 19. Programmable I/O Ports P90, P95 (inside dotted-line included) P93, P96 (inside dotted-line not included) Data bus Pull-up selection Direction register 1 Output Port latch (1) Analog input Input to respective peripheral functions Pull-up selection P87 Data bus Direction register Port latch (1) fc Rf Pull-up selection P86 Data bus Direction register Rd Port latch (1) NOTE: 1. symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 19.4 I/O Ports (4) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 321 of 458 M16C/29 Group 19. Programmable I/O Ports CNVSS CNVSS signal input (1) RESET RESET signal input (1) NOTE: 1. symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 19.5 I/O Pins Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 322 of 458 M16C/29 Group 19. Programmable I/O Ports Port Pi Direction Register (i=0 to 3, 6 to 8, and 10) (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD0 to PD3 PD6 to PD8 PD10 Bit Symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Address 03E2 16, 03E3 16, 03E6 16, 03E7 16 03EE 16, 03EF 16, 03F2 16 03F6 16 Bit Name Function After Reset 0016 0016 0016 RW RW RW RW RW RW RW RW RW Port Pi 0 direction bit Port Pi 1 direction bit Port Pi 2 direction bit Port Pi 3 direction bit Port Pi 4 direction bit Port Pi 5 direction bit Port Pi 6 direction bit Port Pi 7 direction bit 0: Input mode (Functions as an input port) 1: Output mode (Functions as an output port) (i = 0 to 3, 6 to 8, and 10) NOTE: 1. Set the PACR register. In 80-pin package, set bits PACR2, PACR1, PACR0 to 0112. In 64-pin package, set bits PACR2, PACR1, PACR0 to 0102. Port P9 Direction Register (1,2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD9 Address 03F316 Bit Name Port P9 0 direction bit Port P9 1 direction bit Port P9 2 direction bit Port P9 3 direction bit After Reset 000X00002 Function 0: Input mode (Functions as an input port) 1: Output mode (Functions as an output port) Bit Symbol PD9_0 PD9_1 PD9_2 PD9_3 (b4) PD9_5 PD9_6 PD9_7 RW RW RW RW RW Nothing is assigned. If necessary, set to 0. When read, the content is undefined Port P9 5 direction bit Port P9 6 direction bit Port P9 7 direction bit 0: Input mode (Functions as an input port) 1: Output mode (Functions as an output port) RW RW RW NOTES: 1. Make sure the PD9 register is written to by the next instruction after setting the PRC2 bit in the PRCR register to 1(write enabled). 2. Set the PACR register. In 80-pin package, set bits PACR2, PACR1, PACR0 to 0112. In 64-pin package, set bits PACR2, PACR1, PACR0 to 0102. Figure 19.6 PD0 to PD3 and PD6 to PD10 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 323 of 458 M16C/29 Group 19. Programmable I/O Ports Port Pi Register (i=0 to 3, 6 to 8 and 10)(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol P0 to P3 P6 to P8 P10 Bit Symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Address 03E016, 03E116, 03E416, 03E516 03EC16, 03ED16, 03F016 03F416 Bit Name Port Pi0 bit Port Pi1 bit Port Pi2 bit Port Pi3 bit Port Pi4 bit Port Pi5 bit Port Pi6 bit Port Pi7 bit After Reset Undefined Undefined Undefined Function RW RW RW RW RW RW RW RW RW The pin level on any I/O port which is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port which is set for output mode can be controlled by writing to the corresponding bit in this register 0: “L” level 1: “H” level (1) (i = 0 to 3, 6 to 8 and 10) NOTE: 1. Set the PACR register. In 80-pin package, set bits PACR2, PACR1, PACR0 to 0112. In 64-pin package, set bits PACR2, PACR1, PACR0 to 0102. Port P9 Register b7 b6 b5 b4 b3 b2 (1) b1 b0 Symbol P9 Bit Symbol P9_0 P9_1 P9_2 P9_3 (b4) P9_5 P9_6 P9_7 Address 03F1 16 Bit Name Port P90 bit Port P91 bit Port P92 bit Port P93 bit Nothing is assigned (2) Port P95 bit Port P96 bit Port P97 bit After Reset Undefined Function The pin level on any I/O port which is set for input mode can be read by reading the corresponding bit in this register. The pin level on any I/O port which is set for output mode can be controlled by writing to the corresponding bit in this register (except for P85) 0: “L” level 1: “H” level RW RW RW RW RW RW RW RW NOTES: 1. Set the PACR register. In 80-pin package, set bits PACR2, PACR1, PACR0 to 0112. In 64-pin package, set bits PACR2, PACR1, PACR0 to 0102. 2. Nothing is assigned. If necessary, set to 0. When read, the content is 0. Figure 19.7 P0 to P3 and P6 to P10 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 324 of 458 M16C/29 Group 19. Programmable I/O Ports Pull-up Control Register 0 (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Bit Symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 Address 03FC16 Bit Name P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up P20 to P23 pull-up P24 to P27 pull-up P30 to P33 pull-up P34 to P37 pull-up After Reset 0016 Function 0: Not pulled up 1: Pulled up (1) RW RW RW RW RW RW RW RW RW NOTE: 1. The pin for which this bit is 1 (pulled up) and the direction bit is 0 (input mode) is pulled up. Pull-up Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Bit Symbol Address 03FD16 Bit Name After Reset 0016 Function RW Nothing is assigned. If necessary, set to 0. When read, the content is 0 (b3-b0) PU14 PU15 PU16 PU17 P60 to P63 pull-up P64 to P67 pull-up P70 to P73 pull-up P74 to P77 pull-up 0: Not pulled high 1: Pulled high (1) RW RW RW RW NOTE: 1. The pin for which this bit is 1 (pulled up) and the direction bit is 0 (input mode) is pulled up. Pull-up Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR2 Bit Symbol PU20 PU21 PU22 PU23 PU24 PU25 (b7-b6) Address 03FE16 Bit Name P80 to P83 pull-up P84 to P87 pull-up P90 to P93 pull-up P95 to P97 pull-up P100 to P103 pull-up P104 to P107 pull-up After Reset 0016 Function 0: Not pulled up 1: Pulled up (1) RW RW RW RW RW RW RW Nothing is assigned. If necessary, set to 0. When read, the content is 0 NOTE: 1. The pin for which this bit is 1 (pulled up) and the direction bit is 0 (input mode) is pulled up. Figure 19.8 PUR0 to PUR2 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 325 of 458 M16C/29 Group 19. Programmable I/O Ports Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbpl PCR Address 03FF16 After Reset 0016 Bit symbol PCR0 Bit Name Port P1 control bit Function RW Operation performed when the P1 register is read 0: When the port is set for input, the input levels of P10 to P17 RW pins are read. When set for output, the port latch is read. 1: The port latch is read regardless of whether the port is set for input or output. (b7-b1) Nothing is assigned. If necessary, set to 0. When read, the content is 0 Figure 19.9 PCR Register Pin Assignment Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbpl PACR Address 025D16 After Reset 0016 Bit Symbol PACR0 PACR1 PACR2 Bit Name Pin enabling bit Function 010 : 64 pin 011 : 80 pin All other values are reserved. Do not use. Nothing is assigned. If necessary, RW RW RW RW Reserved bits (b6-b3) UART1 pin remapping bit set to 0. When read, the content is 0 UART1 pins assigned to 0 : P67 to P64 1 : P73 to P70 U1MAP RW NOTE: 1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to 1 (write enable). Figure 19.10 PACR Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 326 of 458 M16C/29 Group 19. Programmable I/O Ports NMI Digital Debounce Register (1,2) b7 b0 Symbol NDDR Address 033E16 Function After Reset FF16 Setting Range RW If the set value =n, - n = 0 to FE16; a signal with pulse width, greater than (n+1)/f8, is input into NMI / SD - n = FF16; the digital debounce filter is disabled and all signals are input 0016 to FF16 RW NOTES: 1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to 1 (write enable). 2. When using the NMI interrupt to exit from stop mode, set the NDDR registert to FF16 before entering stop mode. P17 Digital Debounce Register(1) b7 b0 Symbol P17DDR Address 033F16 Function After Reset FF16 Setting Range RW If the set value =n, - n = 0 to FE16; a signal with pulse width, greater than (n+1)/f8, is input into INPC17/ INT5 - n = FF16; the digital debounce filter is disabled and all signals are input 0016 to FF16 RW NOTE: 1. When using the INT5 interrupt to exit from stop mode, set the P17DDR registert to FF16 before entering stop mode. Figure 19.11 NDDR and P17DDR Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 327 of 458 M16C/29 Group 19. Programmable I/O Ports • Example of INT5 Digital Debounce Function (if P17DDR = 0316) Digital Debounce Filter f8 P17 Data Bus Clock Port In Reload Value (write) Signal Out Count Value (read) To INT5 Data Bus f8 Reload Value Port In Signal Out Count Value FF 03 02 01 03 02 01 00 FF FF 03 1 Reload Value (continued) Port In (continued) Signal Out (continued) Count Value (continued) FF 03 02 03 2 3 4 FF 5 01 00 FF 03 02 FF 6 7 8 9 1. (Condition after reset). P17DDR=FF16. Pin input signal will be output directly. 2. Set the P17DDR register to 0316. The P17DDR register starts decrement along the f8 as a counter source, if the pin input level (e.g.,"L") and the signal output level (e.g.,"H") are not matched. 3. The P17DDR register will stops counting when the pin input level and the signal output level are matched (e.g., both levels are "H") while counting. 4. If the pin input level (e.g.,"L") and the signal output level (e.g.,"H") are not matched the P17DDR register will start decrement again after the setting value is reloaded. 5. When the P17DDR register is underflow, it stops counting and the signal output will output the same as pin input level (e.g."L"). 6. If the pin input level (e.g.,"H") and the signal output level (e.g., "L") are not matched again, the P17DDR register will start decrement again after the setting value is reloaded. 7. When the P17DDR register is underflow, it stops counting and the signal output will output the same as pin input level (e.g."H"). 8. If the pin input level (e.g.,"H") and the signal output level (e.g., "L") are not matched again, the P17DDR register will start decrement again after the setting value is reloaded. 9. Set the P17DDR register to FF16. The P17DDR register starts counting after the setting value is reloaded. Pin input signal will be output directly. Figure 19.12 Functioning of Digital Debounce Filter Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 328 of 458 M16C/29 Group 19. Programmable I/O Ports Table 19.1 Unassigned Pin Handling in Single-chip Mode Pin Name Ports P0 to P3, P6 to P10 XOUT XIN AVCC AVSS, VREF Setting Enter input mode and connect each pin to VSS via a resistor (pull-down); or enter output mode and leave the pins open (1,2,4) Leave pin open (3) Connect pin to VCC via a resistor (pull-up) (5) Connect pin to VCC Connect pin to VSS NOTES: 1. If the port enters output mode and is left open, it is in input mode before output mode is entered by program after reset. While the port is in input mode, voltage level on the pins is indeterminate and power consumption may increase. Direction register setting may be changed by noise or failure caused by noise. Configure direction register settings regulary to increase the reliability of the program. 2. Use the shortest possible wiring to connect the MCU pins to unassigned pins (within 2 cm). 3. When the external clock is applied to the XIN pin, set the pin as written above. 4. In the 64-pin package, set bits PACR2, PACR1, and PACR0 in the PACR register to 0102. In the 80-pin package, set bits PACR2, PACR1, and PACR0 to 0112. 5. When the main clock oscillation is not used, set the CM05 bit in the CM0 register to 1 (main clock stops) to reduce power consumption. MCU Port P0 to P3, P6 to P10 (1) (Input mode) · · · (Input mode) (Output mode) · · · Open XIN XOUT AV CC Open VCC AVSS Vref VSS In single-chip mode NOTE: 1. When using the 64-pin package, set bits PACR2, PACR1, and PACR0 to 0102. When using the 80-pin package, set bits PACR2, PACR1, and PACR0 to 0112. Figure 19.13 Unassigned Pin Handling Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 329 of 458 M16C/29 Group 20. Flash Memory Version 20. Flash Memory Version 20.1 Flash Memory Performance In the flash memory version, rewrite operation to the flash memory can be performed in four modes: CPU rewrite mode, standard serial I/O mode, parallel I/O mode, and CAN I/O mode. Table 20.1 lists specifications of the flash memory version. (Refer to Table 1.1 or Table 1.2 for the items not listed in Table 20.1. Table 20.1 Flash Memory Version Specifications Item Flash memory operating mode Erase block Program method Erase method Program, erase control method Protect method Number of commands Program/Erase Endurance(1) Data Retention ROM code protection Block 0 to 5 (program area) Block A and B (data are) (2) Specification 4 modes (CPU rewrite, standard serial I/O, parallel I/O, CAN I/O)(3) See Figures 20.1 to 20.3 Flash Memory Block Diagram In units of word Block erase Program and erase controlled by software command Blocks 0 to 5 are write protected by FMR16 bit. In addition, the block 0 and block 1 are write protected by FMR02 bit 5 commands 100 times 1,000 times (See Tables 1.6 to 1.8) 100 times 10,000 times (See Tables 1.6 to 1.8) 20 years (Topr = 55ϒ C) Parallel I/O, standard serial I/O, and CAN I/O modes are supported. NOTES: 1. Program and erase endurance definition Program and erase endurance are the erase endurance of each block. If the program and erase endurance are n times (n=100,1000,10000), each block can be erased n times. For example, if a 2-Kbyte block A is erased after writing 1 word data 1024 times, each to different addresses, this is counted as one program and erasure. However, data cannot be written to the same address more than once without erasing the block. (Rewrite disabled) 2. To use the limited number of erasure efficiently, write to unused address within the block instead of rewrite. Erase block only after all possible address are used. For example, an 8-word program can be written 128 times before erase is necessary. Maintaining an equal number of erasure between Block A and B will also improve efficiency. We recommend keeping track of the number of times erasure is used. 3. The M16C/29 Group, T-ver./V-ver. does not support the CAN I/O mode. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 330 of 458 M16C/29 Group 20. Flash Memory Version Table 20.2. Flash Memory Rewrite Modes Overview Flash memory rewrite mode Function Standard serial I/O mode The user ROM area is The user ROM area rewritten when the CPU is rewritten using a excutes software dedicated serial command programmer. from the CPU. Standard serial I/O EW0 mode: mode 1: Rewrite in area other Clock synchronous than flash memory serial I/O EW1 mode: Standard serial I/O Rewrite in flash mode 2: memory UART User ROM area User ROM area Single chip mode None Boot mode Serial programmer CPU rewrite mode Parallel I/O mode The user ROM areas are rewritten using a dedicated parallel programmer. CAN I/O mode The user ROM areas is rewritten using a dedicated CAN programmer. Areas which can be rewritten Operation mode ROM programmer User ROM area Parallel I/O mode Parallel programmer User ROM area Boot mode CAN programmer 20.1.1 Boot Mode The MCU enters boot mode when a hardware reset is performed while a high-level ("H") signal is applied to pins CNVSS and P86 or while an "H" signal is applied to pins CNVSS and P16 and a low-level ("L") signal is applied to the P85. A program in the boot ROM area is executed. The boot ROM area is reserved. The boot ROM area stores the rewrite control program for a standard serial I/O mode before shipping. Do not rewrite the boot ROM area. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 331 of 458 M16C/29 Group 20. Flash Memory Version 20.2 Memory Map The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 20.1 to 20.3 show a block diagram of the flash memory. The user ROM area has space to store the MCU operation program in single-chip mode and two 2-Kbyte spaces: the block A and B. The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite, standard serial I/O, parallel I/O, or CAN I/O mode. However, to rewrite program in block 0 and 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (block 0, 1 rewrite enabled) and the FMR16 bit in the FMR1 register to 1 (blocks 0 to 5 rewrite enabled). Also, to rewrite program in blocks 2 to 5 in CPU rewrite mode, set the FMR16 bit in the FMR1 register to 1 (blocks 0 to 5 rewrite enabled). When the PM10 bit in the PM1 register is set to 1 (data space access enabled), blocks A and B can be available for use. (Data space) 00F00016 00F7FF16 00F80016 00FFFF16 Block B :2K bytes(2) Block A :2K bytes (2) (Program space) 0F000016 Block 3 : 32K bytes (5) 0F7FFF16 0F800016 Block 2 : 16K bytes Block 2 : 16K bytes (5) 0FBFFF16 0FC00016 Block 1 : 8K bytes (3) 0FDFFF16 0FE00016 Block 0 : 8K bytes (3) 0FFFFF16 User ROM area NOTES: 1. To specify a block, use the maximum even address in the block. 2. Blocks A and B are enabled to use when the PM10 bit in the PM1 register is set to 1. 3. Blocks 0 and 1 are enabled for programs and erases when the FMR02 bit in the FMR0 register is set to 1 and the FMR16 bit in the FMR1 register is set to 1. (CPU rewrite mode only) 4. The boot ROM area is reserved. Do not access. 5. Blocks 2 and 3 are enabled for programs and erases when the FMR16 bit in the FMR1 register is set to 1. (CPU rewrite mode only) 0FF00016 0FFFFF16 4K bytes(4) Boot ROM area Figure 20.1 Flash Memory Block Diagram (ROM capacity 64 Kbytes) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 332 of 458 M16C/29 Group 20. Flash Memory Version 00F00016 00F7FF16 00F80016 00FFFF16 (Data space) Block B :2K bytes (2) Block A :2K bytes (2) (Program space) 0E800016 Block 4 : 32K bytes (5) 0EFFFF16 0F000016 Block 3 : 32K bytes (5) 0F7FFF16 0F800016 Block 2 : 16K bytes Block 2 : 16K bytes (5) 0FBFFF16 0FC00016 Block 1 : 8K bytes (3) 0FDFFF16 0FE00016 Block 0 : 8K bytes (3) 0FFFFF16 User ROM area NOTES: 1. To specify a block, use the maximum even address in the block. 2. Blocks A and B are enabled for use when the PM10 bit in the PM1 register is set to 1. 3. Blocks 0 and 1 are enabled for programs and erasure when the FMR02 bit in the FMR0 register is set to 1 and the FMR16 bit in the FMR1 register is set to 1. (CPU rewrite mode only) 4. The Boot ROM area is reserved. Do not rewrite. 5. Blocks 2 to 4 are enabled for programs and erasure when the FMR16 bit in the FMR1 register is set to 1. (CPU rewrite mode only) 0FF00016 0FFFFF16 4K bytes (4) Boot ROM area Figure 20.2 Flash Memory Block Diagram (ROM capacity 96 Kbytes) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 333 of 458 M16C/29 Group 20. Flash Memory Version 00F00016 00F7FF16 00F80016 00FFFF16 (Data space) Block B :2K bytes(2) Block A :2K bytes(2) (Program space) 0E000016 Block 5 : 32K bytes(5) 0E7FFF16 0E800016 Block 4 : 32K bytes (5) 0EFFFF16 0F000016 Block 3 : 32K bytes (5) NOTES: 1. To specify a block, use the maximum even address in the block. 2. Blocks A and B are enabled to use when the PM10 bit in the PM1 register is set to 1. 3. Blocks 0 and 1 are enabled for programs and erases when the FMR02 bit in the FMR0 register is set to 1 and the FMR16 bit in the FMR1 register is set to 1. (CPU rewrite mode only) 4. The boot ROM area is reserved. Do not access. 5. Blocks 2 to 5 are enabled for programs and erases when the FMR16 bit in the FMR1 register is set to 1. (CPU rewrite mode only) 0F7FFF16 0F800016 Block 2 : 16K bytes Block 2 : 16K bytes (5) 0FBFFF16 0FC00016 Block 1 : 8K bytes(3) 0FDFFF16 0FE00016 Block 0 : 8K bytes (3) 0FFFFF16 User ROM area 0FF00016 0FFFFF16 4K bytes (Note 4) Boot ROM area Figure 20.3 Flash Memory Block Diagram (ROM capacity 128 Kbytes) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 334 of 458 M16C/29 Group 20. Flash Memory Version 20.3 Functions To Prevent Flash Memory from Rewriting The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code check function for standard input/output mode to prevent the flash memory from reading or rewriting. 20.3.1 ROM Code Protect Function The ROM code protect function disables reading or changing the contents of the on-chip flash memory in parallel I/O mode. Figure 20.4 shows the ROMCP address. The ROMCP address is located in a user ROM area. To enable ROM code protect, set the ROMCP1 bit to “002”, “012”, or “102” and set the bit 5 to bit 0 to “1111112”. To cancel ROM code protect, erase the block including the the ROMCP register in CPU rewrite mode or standard serial I/O mode. 20.3.2 ID Code Check Function Use the ID code check function in standard serial input/output mode. Unless the flash memory is blank, the ID code sent from the programmer and the 7-byte ID code written in the flash memory are compared for match. If the ID codes do not match, the commands sent from the programmer are not acknowledged. The ID code consists of 8-bit data, starting with the first byte, into addresses, 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. The flash memory must have a program with the ID code set in these addresses. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 335 of 458 M16C/29 Group 20. Flash Memory Version ROM Code Protect Control Address(5) b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 Symbol ROMCP Bit Symbol (b5-b0) ROMCP1 Address 0FFFFF16 Factory Setting FF16 (4) Bit Name Reserved Bit ROM Code Protect Level 1 Set Bit (1, 2, 3, 4) Set to 1 b7 b6 Function RW RW RW RW 00: 01: Enables protect 10: 11: Disables protect } NOTES: 1. When the ROM code protect is active by the ROMCP1 bit setting, the flash memory is protected against reading or rewriting in parallel I/O mode. 2. Set the bit 5 to bit 0 to 1111112 when the ROMCP1 bit is set to a value other than 112. When the bit 5 to bit 0 are set to values other than 1111112, the ROM code protection may not become active by setting the ROMCP1 bit to a value other than 112. 3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard serial I/O mode or CPU rewrite mode. 4. The ROMCP address is set to FF16 when a block, including the ROMCP address, is erased. 5. When a value of the ROMCP address is 0016 or FF16, the ROM code protect function is disabled. Figure 20.4 ROMCP Address Address 0FFFDF16 to 0FFFDC16 ID1 0FFFE316 to 0FFFE016 0FFFE716 to 0FFFE416 0FFFEB16 to 0FFFE816 ID3 ID2 Undefined instruction vector Overflow vector BRK instruction vector Address match vector Single step vector Watchdog timer vector DBC vector NMI vector 0FFFEF16 to 0FFFEC16 ID4 0FFFF316 to 0FFFF016 0FFFF716 to 0FFFF416 0FFFFB16 to 0FFFF816 0FFFFF16 to 0FFFFC16 ID5 ID6 ID7 ROMCP Reset vector 4 bytes Figure 20.5 Address for ID Code Stored Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 336 of 458 M16C/29 Group 20. Flash Memory Version 20.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with MCU mounted on a board without using the ROM writer. The program and block erase commands are executed only in the user ROM area. When the interrupt requests are generated during the erase operation in CPU rewirte mode, the flash memory offers an erase suspend function to suspend the erase operation and process the interrupt operation. During the erase suspend function is operated, the user ROM area can be read by program. Erase-write(EW) 0 mode and erase-write 1 mode are provided as CPU rewrite mode. Table 20.3 lists differences between EW mode 0 and EW mode 1. One wait is required for the CPU erase-write control. Table 20.3 EW Mode 0 and EW Mode 1 Item EW mode 0 Operation mode Single chip mode Areas in which a User ROM area rewrite control program can be located Areas where The rewrite control program must be rewrite control transferred to any other than the flash program can be memory (e.g., RAM) before being executed(2) executed Areas which can be User ROM area rewritten Software command Restrictions None EW mode 1 Single chip mode User ROM area The rewrite control program can be excuted in the user ROM area Mode after programming Read Status Register Mode or erasing CPU state during autoOperating write and auto-erase Flash memory status • Read the FMR00, FMR06, and detection FMR07 bits in the FMR0 register by program • Execute the read status register command to read bits SR7, SR5, and SR4. Condition for transferring Set bits FMR40 and FMR41 in to erase-suspend(3) the FMR4 register to 1 by program. NOTES: User ROM area However, this excludes blocks with the rewrite control program • Program, block erase command Cannot be executed in a block having the rewite control program • Read Status Register command Cannot be executed Read Array mode In a hold state (I/O ports retain the state before the command is excuted(1) Read the FMR00, FMR06, and FMR07 bits in the FMR0 registerby program The FMR40 bit in the FMR4 register is set to 1 and the interruput request of an acknowledged interrupt is generated 1. Do not generate a DMA transfer. 2. Block 1 and Block 0 are enabled for rewrite by setting FMR02 bit in the FMR0 register to 1 and setting FMR16 bit in the FMR1 register to 1. Block 2 to Block 5 are enabled for rewrite by setting FMR16 bit in the FMR1 register to 1. 3. The time, until entering erase suspend and reading flash is enabled, is maximum td(SR-ES) after satisfying the conditions. page 337 of 458 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 M16C/29 Group 20. Flash Memory Version 20.4.1 EW Mode 0 The MCU enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite mode enabled) and is ready to accept software commands. EW mode 0 is selected by setting the FMR11 bit in the FMR1 register to 0. To set the FMR01 bit to 1, set to 1 after first writing 0. The software commands control programming and erasing. The FMR0 register or the status register indicates whether a programming or erasing operations is completed. When entering the erase-suspend during the auto-erasing, set the FMR40 bit to 1 (erase-suspend enabled) and the FMR41 bit to 1 (suspend request). After waiting for td(SR-ES) and verifying the FMR46 bit is set to 1 (auto-erase stop), access to the user ROM area. When setting the FMR41 bit to 0 (erase restart), auto-erasing is restarted. 20.4.2 EW Mode 1 EW mode 1 is selected by setting the FMR11 bit to 1 after the FMR01 bit is set to 1 (set to 1 after first writing 0). The FMR0 register indicates whether or not a programming or an erasing operation is completed. Read status register cannot be read in EW mode 1. When an erase/program command is initiated, the CPU halts all program execution until the command operation is completed or erase-suspend request is generated. When enabling an erase-suspend function, set the FMR40 bit to 1 (erase suspend enabled) and execute block erase commands. Also, the interrupt to transfer to erase-suspend must be set enabled preliminarily. When entering erase-suspend after td(SR-ES) from an interrupt is requested, interrupts can be accepted. When an interrupt request is generated, the FMR41 bit is automatically set to 1 (suspend request) and an auto-erasing is suspended. If an auto-erasing has not completed (when the FMR00 bit is 0) after an interrupt process is completed, set the FMR41 bit to 0 (erase restart) and execute block erase commands again. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 338 of 458 M16C/29 Group 20. Flash Memory Version 20.5 Register Description Figure 20.6 shows the flash memory control register 0 and flash memory control register 1. Figure 20.7 shows the flash memory control register 4. 20.5.1 Flash Memory Control Register 0 (FMR0) •FMR 00 Bit The FMR00 bit indicates the operating state of the flash memory. Its value is 0 while the program, erase, or erase-suspend command is being executed, otherwise, it is 1. •FMR01 Bit The MCU can accept commands when the FMR01 bit is set to 1 (CPU rewrite mode). To set the FMR01 bit to 1, first set it to 0 and then 1. The FMR01 bit is set to 0 only by writing 0. •FMR02 Bit The combined settings of bits FMR02 and FMR16 enable program and erase in the user ROM area. See Table 20.4 for setting details. To set the FMR02 bit to 1, first set it to 0 and then 1. The FMR02 bit is valid only when the FMR01 bit is set to 1 (CPU rewrite mode enable). •FMSTP Bit The FMSTP bit initializes the flash memory control circuits and minimizes power consumption in the flash memory. Access to the on-chip flash memory is disabled when the FMSTP bit is set to 1. Set the FMSTP bit by program in a space other than the flash memory. Set the FMSTP bit to 1 if one of the following occurs: •A flash memory access error occurs during erasing or programming in EW mode 0 (FMR00 bit does not switch back to 1 (ready)). •Low-power consumption mode or on-chip oscillator low-power consumption mode is entered. Figure 20.10 shows a flow chart illustrating how to start and stop the flash memory before and after entering low power mode. Follow the procedure in this flow chart. When entering stop or wait mode while the CPU rewrite mode is disabled, do not set the FMR0 register because the on-chip flash memory is automatically turned off and turned back on when exiting. •FMR06 Bit The FMR06 bit is a read-only bit indicating an auto-program operation state. The FMR06 bit is set to 1 when a program error occurs; otherwise, it is set to 0. For details, refer to 20.8.4 Full Status Check. •FMR07 Bit The FMR07 bit is a read-only bit indicating an auto-erase operation status. The FMR07 bit is set to 1 when an erase error occurs; otherwise, it is set to 0. For details, refer to 20.8.4 Full Status Check. Figure 20.8 shows a EW mode 0 set/reset flowchart, Figure 20.9 shows a EW mode 1 set/reset flowchart. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 339 of 458 M16C/29 Group 20. Flash Memory Version 20.5.2 Flash Memory Control Register 1 (FMR1) •FMR11 Bit EW mode 1 is entered by setting the FMR11 bit to 1 (EW mode 1). The FMR11 bit is valid only when the FMR01 bit is set to 1. •FMR16 Bit The combined setting of bits FMR02 and FMR16 enables program and erase in the user ROM area. To set the FMR16 bit to 1, first set it to 0 and then 1. The FMR16 bit is valid only when the FMR01 bit is set to 1 (CPU rewrite mode enable). •FMR17 Bit If the FMR17 bit is set to 1 (with wait state), 1 wait state is inserted when blocks A and B are accessed, regardless of the content of the PM17 bit in the PM1 register. The PM17 bit setting is reflected to access other blocks and internal RAM, regardless of the FMR17 bit setting. Set the FMR17 bit to 1 (with wait state) to rewrite more than 100 times (U7, U9). Table 20.4 Protection using FMR16 and FMR02 FMR16 FMR02 Block A, Block B Block 0, Block 1 0 0 write enabled write disabled 0 1 write enabled write disabled 1 0 write enabled write disabled 1 1 write enabled write enabled other user block write disabled write disabled write enabled write enabled 20.5.3 Flash Memory Control Register 4 (FMR4) •FMR40 Bit The erase-suspend function is enabled when the FMR40 bit is set to 1 (enabled). •FMR41 Bit When the FMR41 bit is set to 1 by program during auto-erasing in EW mode 0, erase-suspend mode is entered. In EW mode 1, the FMR41 bit is automatically set to 1 (suspend request) to enter erasesuspend mode when an enabled interrupt request is generated. Set the FMR41 bit to 0 (erase restart) to restart an auto-erasing operation. •FMR46 Bit The FMR46 bit is set to 0 during auto-erasing. It is set to 1 in erase-suspend mode. Do not access to flash memory when the FMR46 bit is set to 0. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 340 of 458 M16C/29 Group 20. Flash Memory Version Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol FMR0 Bit Symbol FMR00 FMR01 01B7 16 Address After Reset 00000001 2 Bit Name RY/BY status flag CPU rewrite mode select bit (1) Function 0: Busy (during writing or erasing) 1: Ready 0: Disables CPU rewrite mode (Disables software command) 1: Enables CPU rewrite mode (Enables software commands) Set write protection for user ROM area (see Table 20.4 ) 0: Starts flash memory operation 1: Stops flash memory operation (Enters low-power consumption state and flash memory reset) Set to 0 (4) RW RO RW FMR02 Block 0, 1 rewrite enable bit (2) RW FMSTP Flash memory stop bit (3, 5) RW RW RO RO (b5-b4) FMR06 FMR07 Reserved bit Program status flag Erase status flag 0: Successfully completed 1: Completion error 0: Successfully completed 1: Completion error (4) NOTES: 1. Set the FMR01 bit to 1 immediately after setting it first to 0. Do not generate an interrupt or a DMA transfer between setting the bit to 0 and setting it to 1. Set this bit while the P85/NMI/SD pin is held “H” when selecting the NMI function. Set by program in a space other than the flash memory in EW mode 0. Set this bit to read alley mode and 0. 2. Set this bit to 1 immediately after setting it first to 0 while the FMR01 bit is set to 1. Do not generate an interrupt or a DMA transfer between setting this bit to 0 and setting it to 1. 3. Set this bit in a space other than the flash memory by program. When this bit is set to 1, access to flash memory will be denied. To set this bit to 0 after setting it to 1, wait for 10 usec. or more after setting it to 1. To read data from flash memory after setting this bit to 0, maintain tps wait time before accessing flash memory. 4. This bit is set to 0 by executing the clear status command. 5. This bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode). If the FMR01 bit is set to 0, this bit can be set to 1 by writing 1 to the FMR01 bit. However, the flash memory does not enter low-power consumption status and it is not initialized. Flash Memory Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol FMR1 Bit Symbol (b0) FMR11 (b3-b2) (b4) (b5) FMR16 Address 01B5 16 After Reset 000XXX0X 2 Bit Name Reserved bit EW mode 1 select bit Reserved bit (1) Function When read, the content is undefined 0: EW mode 0 1: EW mode 1 When read, the content is undefined RW RO RW RO Nothing is assigned. If necessary, set to 0. When read, the content is undefined Reserved bit Block 0 to 5 rewrite enable bit (2) Block A, B access wait bit (3) Set to 0 Set write protection for user ROM space (see Table 20.4 ) 0: Disable 1: Enable 0: PM17 enabled 1: With wait state (1 wait) RW RW FMR17 RW NOTES: 1. Set the FMR11 bit to 1 immediately after setting it first to 0 while the FMR01 bit is set to 1. Do not generate an interrupt or a DMA transfer between setting the bit to 0 and setting it to 1. Set this bit while the P85/NMI/SD pin is held "H" when the NMI function is selected. If the FMR01 bit is set to 0, the FMR01 bit and FMR11 bit are both set to 0. 2. Set this bit to 1 immediately after setting it first to 0 while the FMR01 bit is set to 1. Do not generate an interrupt or a DMA transfer between setting this bit to 0 and setting it to 1. 3. When rewriting more than 100 times, set this bit to 1 (with wait state). When the FMR17 bit is set to1(with wait state), regardless of the PM17 bit setting, 1 wait state is inserted when accessing to blocks A and B. The PM17 bit setting is enabled, regardless of the FMR17 bit setting, as to the access to other block and the internal RAM. Figure 20.6 FMR0 and FMR1 Registers Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 341 of 458 M16C/29 Group 20. Flash Memory Version Flash Memory Control Register 4 b7 b6 b5 b4 b3 b2 b1 b0 0 0000 Symbol FMR4 Bit Symbol FMR40 FMR41 (b5-b2) FMR46 (b7) Address 01B3 16 After Reset 01000000 2 Bit Name Erase suspend function enable bit (1) Erase suspend request bit (2) Reserved bit Erase status Reserved bit 0: Disabled 1: Enabled Function RW RW RW RO RO RW 0: Erase restart 1: Suspend request Set to 0 0: During auto-erase operation 1: Auto-erase stop (erase suspend mode) Set to 0 NOTES: 1. Set the FMR40 bit to 1 immediately after setting it first to 0. Do not generate any interrupt or DMA transfer between setting the bit to 0 and setting it to 1. Set by program in space other than the flash memory in EW mode 0. 2. The FMR41 bit is valid only when the FMR40 bit is set to 1. The FMR41 bit can be written only between executing an erase command and completing erase (this bit is set to 0 other than the above duration). The FMR41 bit can be set to 0 or 1 by program in EW mode 0. In EW mode 1, the FMR41 bit is automatically set to 1 when the FMR40 bit is 1 and a maskable interrupt is generated during erasing. The FMR41 bit cannot be set to 1 by program (it can be set to 0 by program). Figure 20.7 FMR4 Register Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 342 of 458 M16C/29 Group 20. Flash Memory Version EW mode 0 operation procedure Rewrite control program Single-chip mode Set the FMR01 bit to 1 after writing 0 (CPU rewrite mode enabled) (2) Set CM0, CM1, and PM1 registers (1) Execute software commands Transfer a rewrite control program to internal RAM area Execute the Read Array command (3) Jump to the rewrite control program transfered to an internal RAM area (in the following steps, use the rewrite control program internal RAM area) Write 0 to the FMR01 bit (CPU rewrite mode disabled) Jump to a specified address in the flash memory NOTES: 1. Select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and bits CM17 to 16 in the CM1 register. Also, set the PM17 bit in the PM1 register to 1 (with wait state). 2. Set the FMR01 bit to 1 immediately after setting it to 0. Do not generate an interrupt or a DMA transfer between setting the bit to 0 and setting it to 1. Set the FMR01 bit in a space other than the internal flash memory. Also, set only when the P85/NMI/SD pin is “H” at the time of the NMI function selected. 3. Disables the CPU rewrite mode after executing the read array command. Figure 20.8 Setting and Resetting of EW Mode 0 EW mode 1 operation procedure Program in ROM Single-chip mode Set CM0, CM1, and PM1 registers (1) Set the FMR01 bit to 1 (CPU rewrite mode enabled) after writing 0 Set the FMR11 bit to 1 (EW mode 1) after writing 0 (2, 3) Execute software commands Set the FMR01 bit to 0 (CPU rewrite mode disabled) NOTES: 1. Select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and bits CM17 to 16 in the CM1 register. Also, set the PM17 bit in the PM1 register to 1 (with wait state). 2. Set the FMR01 bits to 1 immediately after setting it to 0. Do not generate an interrupt or a DMA transfer between setting the bit to 0 and setting the bit to 1. Set the FMR01 bit in a space other than the internal flash memory. Set only when the P85/NMI/SD pin is “H” at the time of the NMI function selected. 3. Set the FMR11 bit to 1 immediately after setting it to 0 while the FMR01 bit is set to 1. Do not generate an interrupt or a DMA transfer between setting the FMR11 bit to 0 and setting it to 1. Figure 20.9 Setting and Resetting of EW Mode 1 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 343 of 458 M16C/29 Group 20. Flash Memory Version Low power consumption mode program Transfer a low power internal consumption mode program to RAM area Set the FMR01 bit to 1 after setting 0 (CPU rewrite mode enabled) (2) Jump to the low power consumption mode program transferred to internal RAM area. (In the following steps, use the low-power consumption mode program or internal RAM area) Set the FMSTP bit to 1 (flash memory stopped. Low power consumption state)(1) Switch the clock source of CPU clock. Turn main clock off (2) Process of low power consumption mode or on-chip oscillator low power consumption mode Start main clock wait until oscillation stabilizes oscillation switch the clock source of the CPU clock (2) Set the FMSTP bit to 0 (flash memory operation) Set the FMR01 bit to 0 (CPU rewrite mode disabled) Wait until the flash memory circuit stabilizes (tps) (3) Jump to a desired address in the flash memory NOTES: 1. Set the FMRSTP bit to 1 after setting the FMR01 bit to 1 (CPU rewrite mode). 2. Wait until the clock stabilizes to switch the clock source of the CPU clock to the main clock or the sub clock. 3. Add a tps wait time by a program. Do not access the flash memory during this wait time. Figure 20.10 Processing Before and After Low Power Dissipation Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 344 of 458 M16C/29 Group 20. Flash Memory Version 20.6 Precautions in CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. 20.6.1 Operation Speed When the CPU clock source is the main clock, set the CPU clock frequency at 10 MHz or less with the CM06 bit in the CM0 register and bits CM17 and CM16 in the CM1 register, before entering CPU rewrite mode (EW mode 0 or EW mode 1). Also, when selecting f3(ROC) of a on-chip oscillator as a CPU clock source, set bits ROCR3 and ROCR2 in the ROCR register to the CPU clock division rate at “divide-by-4” or “divide-by-8”, before entering CPU rewrite mode (EW mode 0 or EW mode 1). In both cases, set the PM17 bit in the PM1 register to 1 (with wait state). 20.6.2 Prohibited Instructions The following instructions cannot be used in EW mode 0 because the CPU tries to read data in the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction 20.6.3 Interrupts EW Mode 0 • To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM area. _______ • The NMI and watchdog timer interrupts are available since registers FMR0 and FMR1 are forcibly reset when either interrupt occurs. However, the interrupt program, which allocates the jump addresses for each interrupt routine to the fixed vector table, is needed. Flash memory rewrite _______ operation is aborted when the NMI or watchdog timer interrupt occurs. Set the FMR01 bit to 1 and execute the rewrite and erase program again after exiting the interrupt routine. • The address match interrupt can not be used since the CPU tries to read data in the flash memory. EW Mode 1 • Do not acknowledge any interrupts with vectors in the relocatable vector table or the address match interrupt during the auto program period or auto erase period with erase-suspend function disabled. 20.6.4 How to Access To set bit FMR01, FMR02, FMR11 or FMR16 to 1, write 1 immediately after setting to 0. Do not generate an interrupt or a DMA transfer between the instruction to set the bit to 0 and the instruction to set it to 1. _______ _______ _____ When the NMI function is selected, set the bit while an “H” signal is applied to the P85/NMI/SD pin. 20.6.5 Writing in the User ROM Area 20.6.5.1 EW Mode 0 • If the supply voltage drops while rewriting the block where the rewrite control program is stored, the flash memory can not be rewritten, because the rewrite control program is not correctly rewritten. If this error occurs, rewrite the user ROM area in standard serial I/O mode or parallel I/O mode. 20.6.5.2 EW Mode 1 • Do not rewrite the block where the rewrite control program is stored. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 345 of 458 M16C/29 Group 20. Flash Memory Version 20.6.6 DMA Transfer In EW mode 1, do not generate a DMA transfer while the FMR00 bit in the FMR0 register is set to 0. (during the auto-programming or auto-erasing). 20.6.7 Writing Command and Data Write the command codes and data to even addresses in the user ROM area. 20.6.8 Wait Mode When entering wait mode, set the FMR01 bit to 0 (CPU rewrite mode disabled) before executing the WAIT instruction. 20.6.9 Stop Mode When entering stop mode, the following settings are required: • Set the FMR01 bit to 0 (CPU rewrite mode disabled) and disable the DMA transfer before setting the CM10 bit to 1 (stop mode). 20.6.10 Low Power Consumption Mode and On-Chip Oscillator-Low Power Consumption Mode If the CM05 bit is set to 1 (main clock stopped), do not execute the following commands. • Program • Block erase Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 346 of 458 M16C/29 Group 20. Flash Memory Version 20.7 Software Commands Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing a command code, 8 high-order bits (D15–D8) are ignored. Table 20.5 Software Commands First bus cycle Command Read array Read status register Clear status register Program Block erase Mode Write Write Write Write Write Address X X X WA X Data (D15 to D0) xxFF16 xx7016 xx5016 xx4016 xx2016 Write Write WA BA WD xxD016 Read X SRD Mode Second bus cycle Address Data (D15 to D0) SRD: Status register data (D7 to D0) WA : Write address (However,even address) WD : Write data (16 bits) BA : Highest-order block address (However,even address) X : Any even address in the user ROM area xx : 8 high-order bits of command code (ignored) 20.7.1 Read Array Command (FF16) The read array command reads the flash memory. Read array mode is entered by writing command code xxFF16 in the first bus cycle. Content of a specified address can be read in 16-bit unit after the next bus cycle. The MCU remains in read array mode until an another command is written. Therefore, contents of multiple addresses can be read consecutively. 20.7.2 Read Status Register Command (7016) The read status register command reads the status register. By writing command code xx7016 in the first bus cycle, the status register can be read in the second bus cycle (Refer to 20.8 Status Register). Read an even address in the user ROM area. Do not execute this command in EW mode 1. 20.7.3 Clear Status Register Command (5016) The clear status register command clears the status register to 0. By writing xx5016 in the first bus cycle, and bits FMR06 to FMR07 in the FMR0 register and bits SR4 to SR5 in the status register are set to 0. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 347 of 458 M16C/29 Group 20. Flash Memory Version 20.7.4 Program Command (4016) The program command writes 2-byte data to the flash memory. Auto program operation (data program and verify) start by writing xx4016 in the first bus cycle and data to the write address specified in the second bus cycle. The address value specified in the first bus cycle must be the same even address as the write address secified in the second bus cycle. The FMR00 bit in the FMR0 register indicates whether an auto-programming operation has been completed. The FMR00 bit is set to 0 during the auto-program and 1 when the auto-program operation is completed. After the completion of auto-program operation, the FMR06 bit in the FMR0 register indicates whether or not the auto-program operation has been successfully completed. (Refer to 20.8.4 Full Status Check). Also, each block can disable programming command (Refer to Table 20.4). An address that is already written cannot be altered or rewritten. When commands other than the program command are executed immediately after executing the program command, set the same address as the write address specified in the second bus cycle of the program command, to the specified address value in the first bus cycle of the following command. In EW mode 1, do not execute this command on the blocks where the rewrite control program is allocated. In EW mode 0, the MCU enters read status register mode as soon as the auto-program operation starts and the status register can be read. The SR7 bit in the status register is set to 0 as soon as the autoprogram operation starts. This bit is set to 1 when the auto-program operation is completed. The MCU remains in read status register mode until the read array command is written. After completion of the auto-program operation, the status register indicates whether or not the auto-program operation has been successfully completed. Start Write command code xx4016 to the ( 1) write address Write data to the write address(1) FMR00=1? YES Full status check NO (2) Program completed NOTES: 1. Write the command code and data at even address. 2. Refer to Figure 20.14 . Figure 20.11 Flow Chart of Program Command Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 348 of 458 M16C/29 Group 20. Flash Memory Version 20.7.5 Block Erase Auto erase operation (erase and verify) start in the specified block by writing xx2016 in the first bus cycle and xxD016 to the highest-order even addresse of a block in the second bus cycle. The FMR00 bit in the FMR0 register indicates whether the auto-erase operation has been completed. The FMR00 bit is set to 0 (busy) during the auto-erase and 1 (ready) when the auto-erase operation is completed. When using the erase-suspend function in EW mode 0, verify whether a flash memory has entered erase suspend mode, by the FMR46 bit in the FMR4 register. The FMR46 bit is set to 0 during auto-erase operation and 1 when the auto-erase operation is completed (entering erase-suspend). After the completion of an auto-erase operation, the FMR07 bit in the FMR0 register indicates whether or not the auto-erase operation has been successfully completed. (Refer to 20.8.4 Full Status Check). Also, each block can disable erasing. (Refer to Table 20.4). Figure 20.12 shows a flow chart of the block erase command programming when not using the erasesuspend function. Figure 20.12 shows a flow chart of the block erase command programming when using an erase-suspend function. In EW mode 1, do not execute this command on the block where the rewrite control program is allocated. In EW mode 0, the MCU enters read status register mode as soon as the auto-erase operation starts and the status register can be read. The SR7 bit in the status register is set to 0 at the same time the autoerase operation starts. This bit is set to 1 when the auto-erase operation is completed. The MCU remains in read status register mode until the read array command is written. When the erase error occurs, execute the clear status register command and block erase command at leaset three times until an erase error does not occur. Start Write command code xx2016 (1) Write xxD016 to the highest-order block address (1) FMR00=1? NO YES Full status check (2,3) Block erase completed NOTES: 1. Write the command code and data at even address. 2. Refer to Figure 20.14. 3. Execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated. Figure 20.12 Flow Chart of Block Erase Command (when not using erase suspend function) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 349 of 458 M16C/29 Group 20. Flash Memory Version (EW mode 0) Start FMR40=1 Write the command code xx2016 (1) Write xxD016 to the highest-order block address (1) FMR46=1? YES Access Flash Memory FMR00=1? YES Full status check (2,4) Return (Interrupt service routine end) NO FMR41=0 NO Interrupt service routine(3) FMR41=1 Block erase completed (EW mode 1) Start FMR40=1 Write the command code xx2016 (1) Write xxD016 to the highest-order block address (1) Interrupt service routine Access Flash Memory Return (Interrupt service routine end) FMR41=0 FMR00=1? YES NO Full status check (2,4) Block erase completed NOTES: 1. Write the command code and data to even address. 2. Execute the clear status register command and block erase command at least 3 times until an erase error is not generated when an erase error is generated. 3. In EW mode 0, allocate an interrupt vector table of an interrupt, to be used, to the RAM area 4. Refer to Figure 20.14. Figure 20.13 Block Erase Command (at use erase suspend) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 350 of 458 M16C/29 Group 20. Flash Memory Version 20.8 Status Register The status register indicates the operating status of the flash memory and whether or not erase or program operation is successfully completed. Bits FMR00, FMR06, and FMR07 in the FMR0 register indicate the status of the status register. Table 20.6 lists the status register. In EW mode 0, the status register can be read in the following cases: (1) Any even address in the user ROM area is read after writing the read status register command (2) Any even address in the user ROM area is read from when the program or block erase command is executed until when the read array command is executed. 20.8.1 Sequence Status (SR7 and FMR00 Bits ) The sequence status indicates the flash memory operating status. It is set to 0 (busy) while the autoprogram and auto-erase operation is being executed and 1 (ready) as soon as these operations are completed. This bit indicates 0 (busy) in erase-suspend mode. 20.8.2 Erase Status (SR5 and FMR07 Bits) Refer to 20.8.4 Full Status Check. 20.8.3 Program Status (SR4 and FMR06 Bits) Refer to 20.8.4 Full Status Check. Table 20.6 Status Register Bits in the Bits in the Status SRD Register FMR0 Name Register Sequence status SR7 (D7) FMR00 SR6 (D6) SR5 (D5) SR4 (D4) SR3 (D3) SR2 (D2) SR1 (D1) SR0 (D0) FMR07 FMR06 Reserved Erase status Program status Reserved Reserved Reserved Reserved Contents 0 Busy Completed normally Completed normally 1 Ready Terminated by error Terminated by error - Value After Reset 1 0 0 • D7 to D0: Indicates the data bus which is read out when executing the read status register command. • The FMR07 bit (SR5) and FMR06 bit (SR4) are set to 0 by executing the clear status register command. • When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase command are not accepted. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 351 of 458 M16C/29 Group 20. Flash Memory Version 20.8.4 Full Status Check If an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating a specific error. Therefore, execution results can be comfirmed by verifying these status bits (full status check). Table 20.7 lists errors and FMR0 register state. Figure 20.14 shows a flow chart of the full status check and handling procedure for each error. Table 20.7 Errors and FMR0 Register Status FMR0 register (SRD register) status Error Error occurrence condition FMR07 FMR06 (SR5) (SR4) 1 1 Command • An incorrect commands is written sequence error • A value other than xxD016 or xxFF16 is written in the second bus cycle of the block erase command (1) • When the block erase command is executed on an protected block • When the program command is executed on protected blocks 1 0 Erase error • The block erase command is executed on an unprotected block but the program operation is not successfully completed 0 1 Program error • The program command is executed on an unprotected block but the program operation is not successfully completed Note 1: The flash memory enters read array mode by writing command code xxFF16 in the second bus cycle of these commands. The command code written in the first bus cycle becomes invalid. Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 352 of 458 M16C/29 Group 20. Flash Memory Version Full status check FMR06 =1 and FMR07=1? NO FMR07= 0? YES YES Command sequence error NO Erase error (1) Execute the clear status register command and set the status flag to 0 whether the command is entered. (2) Execute the command again after checking that the correct command is entered or the program command or the block erase command is not executed on the protected blocks. (1) Execute the clear status register command and set the erase status flag to 0. (2) Execute the block erase command again. (3) Execute (1) and (2) at least 3 times until an erase error does not occur. Note 1: If the error still occurs, the block can not be used. FMR06= 0? YES NO Program error [During programming] (1) Execute the clear status register command and set the program status flag to 0. (2) Execute the program command again. Note 2: If the error still occurs, the block can not be used. Full status check completed Note 3: If bits FMR06 or FMR07 is 1, any of the program or block erase command cannot be accepted. Execute the clear status register command before executing those commands. Figure 20.14 Full Status Check and Handling Procedure for Each Error Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 353 of 458 M16C/29 Group 20. Flash Memory Version 20.9 Standard Serial I/O Mode In standard serial I/O mode, the serial programmer supporting the M16C/29 group can be used to rewrite the flash memory user ROM area, while the MCU is mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer. Refer to the user’s manual included with your serial programmer for instruction. Table 20.8 lists pin description (flash memory standard serial input/output mode). Figures 20.15 and 20.16 show pin connections for standard serial input/output mode. 20.9.1 ID Code Check Function The ID code check function determines whether or not the ID codes sent from the serial programmer matches those written in the flash memory. (Refer to 20.3 Functions To Prevent Flash Memory from Rewriting.) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 354 of 458 M16C/29 Group 20. Flash Memory Version Table 20.8 Pin Descriptions (Flash Memory Standard Serial I/O Mode) Pin VCC,VSS CNVSS RESET XIN XOUT AVCC, AVSS VREF P00 to P07 P10 to P15, P17 P16 P20 to P27 P30 to P37 P60 to P63 P64 Name Power input CNVS Reset input Clock input Clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P1 Input port P2 Input port P3 Input port P6 BUSY output I I I I I I I O I I O I I I I I I/O I I S I/O Descriptio n Apply the voltage guaranteed for Program and Erase to Vcc pin and 0 V to Vss pin. Connect to Vcc pin. Reset input pin. While RESET pin is “L”, wait for td(ROC). Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect AVss to Vss and AVcc to Vcc, respectively. Enter the reference voltage for AD conversion. Input “H” or “L” signal or leave open. Input “H” or “L” signal or leave open. Connect this pin to Vcc while RESET pin is “L”. (2) Input "H" or “L” level signal or leave open. Input "H" or “L” level signal or leave open. Input "H" or “L” level signal or leave open. Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Monitor signal output pin for boot program operation check Standard serial I/O mode 1: Serial clock input pin Standard serial I/O mode 2: Input “L”. Serial data input pin Serial data output pin (1) Input “H” or “L” signal or leave open. Input “H” or “L” signal or leave open. Connect this pin to Vss while RESET pin is “L”. (2) Connect this pin to Vcc while RESET pin is “L”. (2) Input “H” or “L” signal or leave open. “H” signal is output for specific time. Input “H” signal or leave open. Input “H” or “L” signal or leave open. Input “H” or “L” signal or leave open. I I I O P65 P66 P67 P70 to P77 P80 to P84, P87 P85 P86 P90 to P92, P95 to P97 P93 SCLK input RxD input TxD output Input port P7 Input port P8 RP input CE input Input port P9 Input port P93 Normal-ver. T-ver./V-ver. P100 to P107 Input port P10 NOTES: ___________ 1. When using standard serial I/O mode 1, to input “H” to the TxD pin is necessary while the RESET pin is held “L”. Therefore, connect this pin to VCC via a resistor. Adjust the pull-up resistor value on a system not to affect a data transfer after reset, because this pin changes to a data-output pin 2. Set the following, either or both. _____ -Connect the CE pin to VCC. -Connect the RP pin to VSS and P16 pin to VCC. _____ Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 355 of 458 M16C/29 Group 20. Flash Memory Version P16 (1) 40 39 38 37 36 35 34 48 47 46 45 43 42 41 44 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 BUSY SCLK RxD TxD M16C/29 Group (64-pin package) (Flash memory version) (PLQP0064KB-A (64P6Q-A)) 26 25 24 23 22 21 20 19 18 17 10 12 13 14 15 16 11 1 2 3 4 5 6 7 8 9 Connect oscillator circuit Mode setup method Value Signal Vcc CNVss Reset Vss to Vcc Vcc (1) P16 Vcc (1) CE Vss (1) RP (1) RESET Vcc Vss NOTE: 1. Set the following, either or both, in serial I/O Mode, while the RESET pin is applied a low-level ("L") signal. -Connect the CE pin to Vcc. -Connect the RP pin to Vss and the P16 pin to Vcc. Figure 20.15 Pin Connections for Serial I/O Mode (1) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 356 of 458 CE RP (1) M16C/29 Group 20. Flash Memory Version (1) 60 59 58 57 56 54 53 P16 52 51 50 49 48 47 46 45 43 42 41 55 44 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 M16C/29 Group (80-pin package) (Flash memory version) (PLQP0080KB-A(80P6Q-A)) 33 32 31 30 29 28 27 26 25 24 23 22 21 BUSY RxD SCLK TxD 10 12 13 14 15 16 17 18 19 20 11 1 2 3 4 5 6 7 8 9 Connect oscillator circuit Mode setup method Signal Value CNVss Vcc Reset Vss to Vcc P16 Vcc (1) CE Vcc (1) RP Vss (1) RESET Vss Vcc RP (1) NOTE: 1. Set the following, either or both, in serial I/O Mode, while the RESET pin is applied a low-level ("L") signal. -Connect the CE pin to Vcc. -Connect the RP pin to Vss and the P16 pin to Vcc. Figure 20.16 Pin Connections for Serial I/O Mode (2) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 357 of 458 CE (1) M16C/29 Group 20. Flash Memory Version 20.9.2 Example of Circuit Application in Standard Serial I/O Mode Figure 20.17 shows an example of a circuit application in standard serial I/O mode 1 and Figure 20.18 shows an example of a circuit application in standard serial I/O mode 2. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer. MCU SCLK input TxD output BUSY output RxD input SCLK P86(CE) TXD BUSY RxD CNVss Reset input User reset singnal RESET P85(RP) P16 (1) (1) (1) (1) Controlling pins and external circuits vary with the serial programmer. For more information, refer to the user's manual included with the serial programmer. (2) In this example, a selector controls the input voltage applied to CNVss to switch between single-chip mode and standard serial I/O mode. (3) In standard serial input/output mode 1, if the user reset signal becomes “L” while the MCU is communicating with the serial programmer, break the connection between the user reset signal and the RESET pin using a jumper switch. NOTE: 1. Set the following, either or both. - Connect the CE pin to Vcc - Connect the RP pin to Vss and the P16 pin to Vcc Figure 20.17 Circuit Application in Standard Serial I/O Mode 1 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 358 of 458 M16C/29 Group 20. Flash Memory Version MCU SCLK TxD output Monitor output RxD input TxD BUSY RxD CNVss P16 (1) P86(CE) (1) P85(RP) (1) (1) In this example, a selector controls the input voltage applied to CNVss to switch between single-chip mode and standard serial I/O mode. NOTE: 1. Set the following, either or both. - Connect the CE pin to Vcc - Connect the RP pin to Vss and the P16 pin to Vcc Figure 20.18 Circuit Application in Standard Serial I/O Mode 2 Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 359 of 458 M16C/29 Group 20. Flash Memory Version 20.10 Parallel I/O Mode In parallel input/output mode, the user ROM can be rewritten by a parallel programmer supporting the M16C/29 group. Contact your parallel programmer manufacturer for more information on the parallel programmer. Refer to the user’s manual included with your parallel programmer for instructions. 20.10.1 ROM Code Protect Function The ROM code protect function prevents the flash memory from being read or rewritten. (Refer to 20.3 Functions To Prevent Flash Memory from Rewriting). Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 360 of 458 M16C/29 Group 20. Flash Memory Version 20.11 CAN I/O Mode Note The CAN I/O mode is not available in M16C/29 T-ver./V-ver. In CAN I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a CAN programmer which is applicable for the M16C/29 group. For more information about CAN programmers, contact the manufacturer of your CAN programmer. For details on how to use, refer to the user’s manual included with your CAN programmer. Table 20.9 lists pin functions for CAN I/O mode. Figures 20.19 and 20.20 show pin connections for CAN I/ O mode. 20.11.1 ID code check function This function determines whether the ID codes sent from the CAN programmer and those written in the flash memory match.(Refer to 20.3 Functions To Prevent Flash Memory from Rewriting.) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 361 of 458 M16C/29 Group 20. Flash Memory Version Table 20.9 Pin Functions for CAN I/O Mode Pin VCC,VSS CNVSS RESET XIN XOUT AVCC, AVSS VREF P00 to P07 P10 to P15, P17 P16 P20 to P27 P30 to P37 P60 to P64, P66 P65 P67 P70 to P77 P80 to P84, P87 P85 P86 P90 to P91, P95 to P97 P92 P93 P100 to P107 Name Power input CNVSS Reset input Clock input Clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P1 Input port P2 Input port P3 Input port P6 SCLK input TxD output Input port P7 Input port P8 RP input CE input Input port P9 CRX input CTX output Input port P10 I I I I I I I I O I I I I I I O I I I I O I/O Description Apply the voltage guaranteed for Program and Erase to Vcc pin and 0 V to Vss pin. Connect to Vcc pin. Reset input pin. While RESET pin is "L" level, wait for td(ROC). Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect AVss to Vss and AVcc to Vcc, respectively. Enter the reference voltage for AD from this pin. Input "H" or "L" level signal or leave open. Input "H" or "L" level signal or leave open. Connect this pin to Vcc while RESET is low. (Note 1) Input "H" or "L" level signal or leave open. Input "H" or "L" level signal or leave open. Input "H" or "L" level signal or leave open. Input "L" level signal. Input "H" level signal. Input "H" or "L" level signal or leave open. Input "H" or "L" level signal or leave open. Connect this pin to Vss while RESET is low. (Note 1) Connect this pin to Vcc while RESET is low. (Note 1) Input "H" or "L" level signal or leave open. Connect this pin to a CAN transceiver. Connect this pin to a CAN transceiver. Input "H" or "L" level signal or leave open. NOTE: 1. Set following either or both. _____ •Connect the CE pin to VCC. •Connect the RP pin to VSS and the P16 pin to VCC. _____ Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 362 of 458 M16C/29 Group 20. Flash Memory Version P16 Note 40 39 38 37 36 35 34 48 47 46 45 44 43 42 41 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 32 31 30 29 28 M16C/29 Group (64-pin package) (Flash memory version) (PLQ0064KB-A (64P6Q-A)) 27 26 25 24 23 22 21 20 19 18 17 SCLK TxD CTx CRx 63 64 10 12 13 14 15 16 11 1 2 3 4 5 6 7 8 9 Connect oscillator circuit Note RESET Vcc Vss NOTE: 1. Set following either or both in serial I/O mode while the RESET pin is held “L”. •Connect the CE pin to VCC •Connect the RP pin to VSS and the P16 pin to VCC Figure 20.19 Pin Connections for CAN I/O Mode (1) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 363 of 458 CE RP Note Mode setup method Signal Value CNVss Vcc Reset Vss to Vcc P16 Vcc (1) CE Vcc (1) RP Vss (1) SCLK Vss TxD Vcc M16C/29 Group 20. Flash Memory Version 60 59 58 57 56 54 53 P16 52 51 (1) 50 49 48 47 46 45 43 42 41 55 44 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 M16C/29 Group (80-pin package) (Flash memory version) (PLQP0080KB-A (80P6Q-A)) SCLK TxD 10 12 13 14 15 16 17 18 19 20 11 1 2 3 4 5 6 7 8 9 Connect oscillator circuit Mode setup method Signal Value CNVss Vcc Reset Vss to Vcc P16 Vcc (1) CE Vcc (1) RP Vss (1) SCLK Vss TxD Vcc Vcc RP CTx CRx RESET Vss NOTE: 1. Set following either or both in serial I/O mode while the RESET pin is held “L”. •Connect the CE pin to VCC •Connect the RP pin to VSS and the P16 pin to VCC Figure 20.20 Pin Connections for CAN I/O Mode (2) Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 364 of 458 CE (1) (1) M16C/29 Group 20. Flash Memory Version 20.11.2 Example of Circuit Application in CAN I/O Mode Figure 20.21 shows example of circuit application in CAN I/O mode. Refer to the user’s manual for CAN programmer to handle pins controlled by a CAN programmer. MCU TXD SCLK P86(CE) (Note 1) CAN transceiver CAN_H CAN_L (Note 1) P92/CRx P93/CTx P16 CNVss Reset input User reset singnal RESET P85(RP) (Note 1) (1) Control pins and external circuits vary with the CAN programmer. For more information, refer to the user's manual include with the CAN programmer. (2) In this example, a selector controls the input voltage applied to CNVss to switch between single-chip mode and CAN I/O mode. Note 1. Set following either or both. •Connect the CE pin to VCC •Connect the RP pin to VSS and the P16 pin to VCC Figure 20.21 Circuit Application in CAN I/O Mode Rev. 1.12 Mar.30, 2007 REJ09B0101-0112 page 365 of 458 M16C/29 Group 21. Electrical Characteristics (Normal-version) 21. Electrical Characteristics 21.1 Normal version Table 21.1 Absolute Maximum Ratings Symbol VCC AVCC VI Supply Voltage Analog Supply Voltage Input Voltage P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67, P70 to P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107, XIN, VREF, RESET, CNVSS Parameter Condition VCC=AVCC VCC=AVCC Value -0.3 to 6.5 -0.3 to 6.5 Unit V V -0.3 to VCC+0.3 V VO Output Voltage P00 to P07, P10 to P17, P20 to P27, P30 to P37, P60 to P67, P70 to P77, P80 to P87, P90 to P93, P95 to P97, P100 to P107, XOUT Power Dissipation during CPU operation -40