M30302MCP-XXX

PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. M16C/30P Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0088-0080 Rev.0.80 Mar 18, 2005 1. Overview The M16C/30P Group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/ logic operations. 1.1 Applications Audio, cameras, TV, home appliance, office/communications/portable/industrial equipment, etc. Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition. Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 1 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 1. Overview 1.2 Performance Outline Table 1.1 lists Performance Outline of M16C/30P Group. Table 1.1 CPU Performance Outline of M16C/30P Group Item Performance Number of Basic Instructions 91 instructions Minimum Instruction 62.5ns(f(XIN)=16MHz, VCC1=VCC2=4.2 to 5.5V, no wait) Execution Time 100ns(f(XIN)=10MHz, VCC1=VCC2=2.7 to 5.5V, no wait) Operation Mode Single-chip Memory Space 1 Mbyte Memory Capacity See Table 1.2 Product List Peripheral Port Input/Output : 87 pins, Input : 1 pin Function Multifunction Timer Timer A : 16 bits x 3 channels, Timer B : 16 bits x 3 channels Serial Interface 3 channels Clock synchronous, UART, I2C bus(1) 1 channels IEBus(2) A/D Converter 10-bit A/D converter: 1 circuit, 18 channels DMAC 2 channels CRC Calculation Circuit CCITT-CRC Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt Internal: 20 sources, External: 7 sources, Software: 4 sources, Priority level: 7 levels Clock Generating Circuit 2 circuits Main clock generation circuit (*), Subclock generation circuit (*), (*)Equipped with a built-in feedback resistor. Electric Supply Voltage VCC1=VCC2=3.0 to 5.5 V (f(XIN)=16MHz) Characteristics VCC1=VCC2=2.7 to 5.5 V (f(XIN)=10MHz, no wait) Power Consumption 10 mA (VCC1=VCC2=5V, f(XIN)=16MHz) 8 mA (VCC1=VCC2=3V, f(XIN)=10MHz) 1.8 µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode) 0.7 µA(VCC1=VCC2=3V, stop mode) Operating Ambient Temperature -20 to 85°C, -40 to 85°C Package 100-pin plastic mold QFP, LQFP NOTES: 1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. Use the M16C/30P on VCC1 = VCC2. Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 2 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 1. Overview 1.3 Block Diagram Figure 1.1 is a M16C/30P Group Block Diagram. 8 8 8 8 8 8 8 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 8 Internal peripheral functions A/D converter Timer (16-bit) Output (timer A): 3 Input (timer B): 3 (10 bits X 18 channels) UART or clock synchronous serial I/O System clock generation circuit XIN-XOUT XCIN-XCOUT Port P8 7 (3 channels) Port P8_5 CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) M16C/60 series16-bit CPU core Watchdog timer (15 bits) R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory Port P9 ROM (1) RAM (2) 8 DMAC (2 channels) Port P10 8 Multiplier NOTES : 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type. Figure 1.1 M16C/30P Group Block Diagram Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 3 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 1. Overview 1.4 Product List Table 1.2 lists the M16C/30P group products and Figure 1.2 shows the Type No., Memory Size, and Package. Table 1.2 Product List ROM Capacity RAM Capacity (D) 96 Kbytes 5 Kbytes (D) (D) 128 Kbytes (D) (D) 192 Kbytes 6 Kbytes (D) Package Type 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A As of Mar 2005 Type No. M30302MAP-XXXFP M30302MAP-XXXGP M30302MCP-XXXFP M30302MCP-XXXGP M30302MEP-XXXFP M30302MEP-XXXGP (D): Under development (P): Under planning Remarks MASK ROM version Type No. M3030 2 M E P- XXX FP Package type: FP : Package 100P6S-A GP : Package 100P6Q-A ROM No. M16C/30P Group ROM capacity: A : 96 Kbytes C : 128 Kbytes E : 192 Kbytes Memory type: M : Mask ROM version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/30 Series M16C Family Figure 1.2 Type No., Memory Size, and Package Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 4 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 1. Overview 1.5 Pin Configuration Figures 1.3 to 1.4 show the pin configurations (top view). PIN CONFIGURATION (top view) P1_0 P1_1 P1_2 P1_3 P1_4 P1_5/INT3 P1_6/INT4 P1_7 P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 VSS P3_0 VCC2 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P4_0 P4_1 P4_2 P4_3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P0_7/AN0_7 P0_6/AN0_6 P0_5/AN0_5 P0_4/AN0_4 P0_3/AN0_3 P0_2/AN0_2 P0_1/AN0_1 P0_0/AN0_0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 M16C/30P Group P4_4 P4_5 P4_6 P4_7 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/30P on VCC1=VCC2. P9_6/ANEX1 P9_5/ANEX0 P9_4 P9_3 P9_2/TB2IN P9_1/TB1IN P9_0/TB0IN BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2 P8_3/INT1 P8_2/INT0 P8_1 P8_0 P7_7 P7_6 P7_5/TA2IN P7_4/TA2OUT P7_3/CTS2/RTS2/TA1IN P7_2/CLK2/TA1OUT P7_1/RXD2/SCL2/TA0IN (1) P7_0/TXD2/SDA2/TA0OUT (1) Package : 100P6S-A Figure 1.3 Pin Configuration (Top View) Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 5 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 1. Overview PIN CONFIGURATION (top view) P1_3 P1_4 P1_5/INT3 P1_6/INT4 P1_7 P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7 VSS P3_0 VCC2 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P4_0 P4_1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P1_2 P1_1 P1_0 P0_7/AN0_7 P0_6/AN0_6 P0_5/AN0_5 P0_4/AN0_4 P0_3/AN0_3 P0_2/AN0_2 P0_1/AN0_1 P0_0/AN0_0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG P9_6/ANEX1 P9_5/ANEX0 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 M16C/30P Group 38 37 36 35 34 33 32 31 30 29 28 27 26 P4_2 P4_3 P4_4 P4_5 P4_6 P4_7 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT(1) P7_1/RXD2/SCL2/TA0IN(1) P7_2/CLK2/TA1OUT NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/30P on VCC1=VCC2. P9_4 P9_3 P9_2/TB2IN P9_1/TB1IN P9_0/TB0IN BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2 P8_3/INT1 P8_2/INT0 P8_1 P8_0 P7_7 P7_6 P7_5/TA2IN P7_4/TA2OUT P7_3/CTS2/RTS2/TA1IN Package : 100P6Q-A Figure 1.4 Pin Configuration (Top View) Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 6 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 1. Overview 1.6 Pin Description Pin Description (1) Pin Name VCC1, VCC2 VSS AVCC AVSS RESET CNVSS BYTE XIN XOUT XCIN XCOUT CLKOUT INT0 to INT4 NMI KI0 to KI3 TA0OUT to TA2OUT TA0IN to TA2IN TB0IN to TB2IN CTS0 to CTS2 RTS0 to RTS2 CLK0 to CLK2 RXD0 to RXD2 TXD0 to TXD2 CLKS1 I/O Type Description I Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is that VCC1 = VCC2. I Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. I The microcomputer is in a reset state when applying “L” to the this pin. I Connect this pin to VSS. I I O I O O I I I I/O I I I O I/O I O O I/O I/O I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To use the external clock, input the clock from XIN and leave XOUT open. I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To use the external clock, input the clock from XCIN and leave XCOUT open. The clock of the same cycle as fC, f8, or f32 is outputted. Input pins for the INT interrupt. Input pin for the NMI interrupt. Input pins for the key input interrupt. These are timer A0 to timer A2 I/O pins. (except the output of TA0OUT for the N-channel open drain output.) These are timer A0 to timer A2 input pins. These are timer B0 to timer B2 input pins. These are send control input pins. These are receive control output pins. These are transfer clock I/O pins. These are serial data input pins. These are serial data output pins. (except TXD2 for the N-channel open drain output.) This is output pin for transfer clock output from multiple pins function. These are serial data I/O pins. (except SDA2 for the N-channel open drain output.) These are transfer clock I/O pins. (except SCL2 for the N-channel open drain output.) Table 1.3 Signal Name Power supply input Analog power supply input Reset input CNVSS External data bus width select input Main clock input Main clock output Sub clock input Sub clock output Clock output INT interrupt input NMI interrupt input Key input interrupt input Timer A Timer B Serial interface I2C mode SDA0 to SDA2 SCL0 to SCL2 I : Input O : Output I/O : Input and output Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 7 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 1. Overview Table 1.4 Signal Name Reference voltage input A/D converter Pin Description (2) Pin Name VREF AN0 to AN7, AN0_0 to AN0_7 ADTRG ANEX0 ANEX1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P9_0 to P9_7, P10_0 to P10_7 P8_0 to P8_4, P8_6, P8_7 P8_5 I/O Type I I I I/O I I/O Description Applies the reference voltage for the A/D converter. Analog input pins for the A/D converter. This is an A/D trigger input pin. This is the extended analog input pin for the A/D converter, and is the output in external op-amp connection mode. This is the extended analog input pin for the A/D converter. 8-bit I/O ports in CMOS, having a direction register to select an input or output. Each pin is set as an input port or output port. An input port can be set for a pull-up or for no pull-up in 4-bit unit by program. (except P7_0 and P7_1 for the N-channel open drain output.) I/O port I/O I I/O ports having equivalent functions to P0. Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. Input port I : Input O : Output I/O : Input and output Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 8 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b31 b15 b8 b7 b0 R2 R3 R0H R1H R2 R3 A0 A1 FB R0L R1L Data Registers (1) Address Registers (1) Frame Base Registers (1) b0 b19 b15 INTBH INTBL Interrupt Table Register b19 b0 PC b15 b0 Program Counter USP ISP SB b15 b0 User Stack Pointer Interrupt Stack Pointer Static Base Register FLG b15 b8 b7 b0 Flag Register IPL UI OB S Z DC Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level Reserved Area NOTES: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 Central Processing Unit Register 2.1 Data Registers (R0, R1, R2 and R3) The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is the same as R2R0. Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 9 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 2. Central Processing Unit (CPU) 2.2 Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. 2.7 Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. 2.8 Flag Register (FLG) FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”. 2.8.3 Zero Flag (Z Flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”. 2.8.4 Sign Flag (S Flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”. 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”. 2.8.6 Overflow Flag (O Flag) This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”. 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag is cleared to “0” when the interrupt request is accepted. Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 10 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 2. Central Processing Unit (CPU) 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”. The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. 2.8.10 Reserved Area When write to this bit, write “0”. When read, its content is indeterminate. Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 11 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 3. Memory 3. Memory Figure 3.1 is a Memory Map of the M16C/30P group. The address space extends the 1M bytes from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh. The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 10-Kbyte internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users. The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual. 00000h SFR 00400h Internal RAM XXXXXh FFE00h Special page vector table FFFDCh Reserved area Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC NMI Reset Internal RAM Internal ROM Address XXXXXh Address YYYYYh YYYYYh Size Size 5 kbytes 96 kbytes 017FFh E8000h 6 kbytes 128 kbytes 01BFFh E0000h 192 kbytes D0000h FFFFFh Internal ROM FFFFFh Figure 3.1 Memory Map Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 12 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.5 list the SFR information. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh SFR Information(1) (1) Register Symbol After Reset Processor Mode Register 0 (2) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Address Match Interrupt Enable Register Protect Register PM0 PM1 CM0 CM1 AIER PRCR 00h 00XXX0XXb 01001000b 00100000b XXXXXX00b XX000000b Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 WDTS WDC RMAD0 XXh 00XXXXXXb 00h 00h X0h 00h 00h X0h Address Match Interrupt Register 1 RMAD1 DMA0 Source Pointer SAR0 XXh XXh XXh XXh XXh XXh XXh XXh DMA0 Destination Pointer DAR0 DMA0 Transfer Counter TCR0 DMA0 Control Register DM0CON 00000X00b DMA1 Source Pointer SAR1 XXh XXh XXh XXh XXh XXh XXh XXh DMA1 Destination Pointer DAR1 DMA1 Transfer Counter TCR1 DMA1 Control Register DM1CON 00000X00b NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. The PM00 and PM01 bits do not change at software reset. X : Nothing is mapped to this bit Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 13 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 4. Special Function Register (SFR) Table 4.2 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h to 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h to 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh SFR Information(2) (1) Register Symbol After Reset INT3 Interrupt Control Register UART1 BUS Collision Detection Interrupt Control Register UART0 BUS Collision Detection Interrupt Control Register INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register INT3IC U1BCNIC U0BCNIC INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC XX00X000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XX00X000b Peripheral Clock Select Register PCLKR 00000011b NOTES: 1. The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 14 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 4. Special Function Register (SFR) Table 4.3 Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh SFR Information(3) (1) Register Symbol After Reset Interrupt Factor Select Register 2 Interrupt Factor Select Register IFSR2A IFSR 00XXXXXXb 00h UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Generator UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h XXh XXh XXh 00001000b 00000010b XXh XXh NOTES: 1. The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 15 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 4. Special Function Register (SFR) Table 4.4 Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh SFR Information(4) (1) Register Count Start Flag Clock Prescaler Reset Fag One-Shot Start Flag Trigger Select Register Up-Down Flag Timer A0 Register Timer A1 Register Timer A2 Register Symbol TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 After Reset 000XX000b 0XXXXXXXb 00XXX000b XXXX0000b XX0XX000b (2) XXh XXh XXh XXh XXh XXh Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register TB0 TB1 TB2 TA0MR TA1MR TA2MR XXh XXh XXh XXh XXh XXh 00h 00h 00h Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register TB0MR TB1MR TB2MR 00XX0000b 00XX0000b 00XX0000b UART0 Transmit/Receive Mode Register UART0 Bit Rate Generator UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Generator UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register UART Transmit/Receive Control Register 2 U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh X0000000b DMA0 Request Factor Select Register DMA1 Request Factor Select Register CRC Data Register CRC Input Register DM0SL DM1SL CRCD CRCIN 00h 00h XXh XXh XXh NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. Bit 5 in the Up-down flag is “0” by reset. However, The values in these bits when read are indeterminate. X : Nothing is mapped to this bit Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 16 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 4. Special Function Register (SFR) Table 4.5 Address 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh SFR Information(5) (1) Register A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 A/D Register 5 A/D Register 6 A/D Register 7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Symbol XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh After Reset A/D Control Register 2 A/D Control Register 0 A/D Control Register 1 ADCON2 ADCON0 ADCON1 XXX000X0b 000X0XXXb 00000XXXb Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P10 Direction Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10 XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00X00000b 00h XXh 00h Pull-Up Control Register 0 Pull-Up Control Register 1 Pull-Up Control Register 2 Port Control Register PUR0 PUR1 PUR2 PCR 00h 00h 00h 00h NOTES: 1. The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.0.80 Mar 18, 2005 REJ03B0088-0080 Page 17 of 34 Under development Preliminary specification Specifications in this manual are tentative and subject to change. M16C/30P Group 5. Electrical Characteristics 5. Electrical Characteristics Table 5.1 Symbol VCC AVCC VI Analog Supply Voltage Input Voltage RESET, CNVSS, BYTE, P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, VREF, XIN P7_0, P7_1 VO Output Voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, XOUT P7_0, P7_1 Pd Topr Power Dissipation Operating Ambient Temperature When the Microcomputer is Operating −40°C development tools BCLK -> CPU clock Table 1.1 Performance Outline of M16C/30P Group Serial interface is revised. Figure 1.2 Type., Memory Size, and Package is partly revised. Table 1.4 Pin Detection (2) is partly revised. Note 2 Table 5.3 A/D Conversion Characteristics is partly revised. Symbol of Table 5.4 Power Supply Circuit Timing Characteristics is partly revised. Table 5.5 Electrical Characteristics is revised. Table 5.19 Electrical Characteristics is revised. C-1 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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