M30620SAFP

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES M16C/62 (M16C/62A, M16C/62M) Group User’s Manual http://www.infomicom.maec.co.jp/indexe.htm Before using this material, please visit the above website to confirm that this is the most current document available. Rev. 1.0 Revision date: June 18, 2001 Keep safety first in your circuit designs! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q q q q q q q q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http:// www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon ductor product distributor for further details on these materials or the products con tained therein. How to Use This Manual This user's manual is written for the M16C/62A group. The reader of this manual is expected to have the basic knowledge of electric and logic circuits and microcomputers. This manual explains a function of the following kind. • M30620M8A-XXXFP/GP • M30620MAA-XXXFP/GP • M30620MCA-XXXFP/GP • M30622M4A-XXXFP/GP • M30622M8A-XXXFP/GP • M30622MAA-XXXFP/GP • M30622MCA-XXXFP/GP • M30624MGA-XXXFP/GP • M30620SAFP/GP • M30622SAFP/GP • M30620FCAFP/GP • M30624FGAFP/GP • M30620MCM-XXXFP/GP • M30624FGMFP/GP • M30624MGM-XXXFP/GP • M30620FCMFP/GP These products have similar features except for the memories, which differ from one product to another. This manual gives descriptions of M30622MCA-XXXFP. An electric characteristic refer to data sheet responded to. Memories built-in are as shown below. Be careful when writing a program, as the memories have different capacities. ROM Size (Byte) External ROM 256K 128K 96K 64K 32K M30624MGA-XXXFP/GP M30620MCA-XXXFP/GP M30622MCA-XXXFP/GP M30620MAA-XXXFP/GP M30622MAA-XXXFP/GP M30620M8A-XXXFP/GP M30622M8A-XXXFP/GP M30622M4A-XXXFP/GP Mask ROM version ROM Size (Byte) External ROM 256K 128K 96K 64K 32K Mask ROM version Flash memory version M30624MGM-XXXFP/GP M30620MCM-XXXFP/GP M30624FGMFP/GP M30620FCMFP/GP M30620SAFP/GP M30622SAFP/GP M30624FGAFP/GP M30620FCAFP/GP Flash memory version External ROM version This manual comprises of five chapters. Use the suggested chapters as a reference for the following topics: * To understand hardware specifications ................................................... Chapter 1 Hardware * To understand the basic way of using peripheral features and the operation timing ................................ Chapter 2 Peripheral Functions Usage * To observe applications of peripheral features ........................ Chapter 3 Examples of Peripheral Functions Applications * To understand how to use external buses ....................................... Chapter 4 External Buses * To know the difference between the mask ROM Version and external ROM Version ............ Chapter 5 External ROM Version This manual includes a quick reference immediately following the Table of Contents and Table of Contents Classified by Function, indicate the page of the topic to be pursued. An index is also described at the end of this manual. * To find a page describing a peripheral function ...... Table of Contents Classified by Function * To find a page describing a specific register by the register address ............................... Quick Reference to Pages Classified by Address Extra application note explains follows, and please refer to each application note in addition to above. * I2C BUS ............................................................................... M16C/62 Group SIMPLE I2C BUS * Three-phase motor control timer function ... M16C/62 Group THREE-PHASE MOTOR CONTROL The figure of each register configuration describes its functions and attributes as follows : *1 XXX register b7 b6 b5 b4 b3 b2 b1 b0 *2 When reset 0016 0 Symbol XXX Address XXX Bit symbol XXX0 Bit name XXX select bit b1 b0 Function 1 0 : XXX 0 1 : XXX 1 0 : Must not be set 1 1 : XXX R W XXX1 Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Reserved bit Must always be set to "0" XXX4 Function varies with each operation mode XXX5 *3 XXX6 XXX7 XXX flag *1 Blank:Set to "0" or "1" according to intended use 0: Set to "0" 1: Set to "1" X: Nothing is assigned *2 R: Read O.....Possible to read X.....Impossible to read –.....Nothing is assigned Write O.....Possible to write X.....Written value is invalid When write, value can be "0" or "1" –.....Nothing is assigned W: *3 Terms to use here are explained as follows. • Nothing is assigned Nothing is assigned to the bit concerned. When write, set "0" for new function in future plan. • Must not be set Not select. The operation at having selected is not guaranteed. • Reserved bit Reserved bit. Set the specified value. • Function varies with each operation mode Bit function changes according to the mode of peripheral functions. • Invalid in A mode The bit concerned has no function in A mode. Set the specified value. • Valid when bit A="0" When bit A is "1", the bit concerned has no function. When bit A is "0", the bit concerned has function. M16C Family-related document list Usages (Microcomputer development flow) Type of document Data sheet and data book User’s manual Selection of microcomputer Contents Hardware specifications (pin assignment, memory map, specifications of peripheral functions, electrical characteristics, timing charts) Detailed description about hardware specifications, operation, and application examples (connection with peripherals, relationship with software) Method for creating programs using assembly and C languages Detailed description about operation of each instruction (assembly language) Outline design of system Detail design of system Hardware development Software development Hardware Software Programming manual Software manual System evaluation M16C Family Line-up M16C Family M16C/80 Series M16C/80 Group M16C/60 Series M16C/60 Group M16C/61 Group M16C/62 Group M16C/20 Series M16C/20 Group M16C/21 Group M16C/22 Group M16C/24 Group Table of Contents Chapter 1 Hardware ________________________________________ Description ........................................................................................................................................ 1-2 Memory ........................................................................................................................................... 1-11 Central Processing Unit (CPU) ....................................................................................................... 1-12 Reset ............................................................................................................................................... 1-15 Processor Mode .............................................................................................................................. 1-22 Bus Settings .................................................................................................................................... 1-26 Bus Control ..................................................................................................................................... 1-28 Clock Generating Circuit ................................................................................................................. 1-36 Protection ........................................................................................................................................ 1-45 Overview of Interrupt ....................................................................................................................... 1-46 Watchdog Timer .............................................................................................................................. 1-66 DMAC ............................................................................................................................................. 1-68 Timer ............................................................................................................................................... 1-78 Timer A ........................................................................................................................................... 1-80 Timer B ........................................................................................................................................... 1-90 Timers’ functions for three-phase motor control ............................................................................. 1-96 Serial I/O ....................................................................................................................................... 1-108 A-D Converter ............................................................................................................................... 1-149 D-A Converter ............................................................................................................................... 1-159 CRC Calculation Circuit ................................................................................................................ 1-161 Programmable I/O Ports ............................................................................................................... 1-163 Flash Memory Version .................................................................................................................. 1-217 Chapter 2 Peripheral Functions Usage ________________________ 2.1 Protect Usage ............................................................................................................................. 2-2 2.1.1 Overview of the protect usage ............................................................................................. 2-2 2.1.2 Protect Operation ................................................................................................................. 2-4 2.1.3 Precaution for Protect .......................................................................................................... 2-5 2.2 Timer A Usage ............................................................................................................................ 2-6 2.2.1 Overview of the timer A usage ............................................................................................. 2-6 2.2.2 Operation of Timer A (timer mode) .................................................................................... 2-12 2.2.3 Operation of Timer A (timer mode, gate function selected) ............................................... 2-14 2.2.4 Operation of Timer A (timer mode, pulse output function selected) .................................. 2-16 2.2.5 Operation of Timer A (event counter mode, reload type selected) .................................... 2-18 2.2.6 Operation of Timer A (event counter mode, free run type selected) .................................. 2-20 2.2.7 Operation of timer A (2-phase pulse signal process in event counter mode, normal mode selected) ................................................................................................................................ 2-22 2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode, multiply-by-4 mode selected) ............................................................................................................................ 2-24 2.2.9 Operation of Timer A (one-shot timer mode) ..................................................................... 2-26 2.2.10 Operation of Timer A (one-shot timer mode, external trigger selected) ........................... 2-28 2.2.11 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected) ........ 2-30 2.2.12 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected) .......... 2-32 2.2.13 Precautions for Timer A (timer mode) .............................................................................. 2-34 2.2.14 Precautions for Timer A (event counter mode) ................................................................ 2-35 2.2.15 Precautions for Timer A (one-shot timer mode) ............................................................... 2-36 2.2.16 Precautions for Timer A (pulse width modulation mode) ................................................. 2-37 2.3 Timer B Usage .......................................................................................................................... 2-38 2.3.1 Overview of the timer B usage ........................................................................................... 2-38 2.3.2 Operation of Timer B (timer mode) .................................................................................... 2-42 2.3.3 Operation of Timer B (event counter mode) ...................................................................... 2-44 2.3.4 Operation of Timer B (pulse period measurement mode) ................................................. 2-46 2.3.5 Operation of Timer B (pulse width measurement mode) ................................................... 2-48 2.3.6 Precautions for Timer B (timer mode, event counter mode) .............................................. 2-50 2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode) ......................... 2-51 2.4 Clock-Synchronous Serial I/O Usage ....................................................................................... 2-52 2.4.1 Overview of the clock-synchronous serial I/O usage ......................................................... 2-52 2.4.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode) ................... 2-60 2.4.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected) ...................................................................... 2-64 2.4.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode) ......................... 2-68 2.4.5 Precautions for Serial I/O (in clock-synchronous serial I/O) .............................................. 2-72 2.5 Clock-Asynchronous Serial I/O (UART) Usage ........................................................................ 2-74 2.5.1 Overview of the clock-asynchronous serial I/O usage ....................................................... 2-74 2.5.2 Operation of Serial I/O (transmission in UART mode) ....................................................... 2-84 2.5.3 Operation of Serial I/O (reception in UART mode) ............................................................ 2-88 2.5.4 Operation of Serial I/O (transmission used for SIM interface) ........................................... 2-92 2.5.5 Operation of Serial I/O (reception used for SIM interface) ................................................. 2-96 2.5.6 Clock Signals in used for the SIM Interface ..................................................................... 2-100 2.5.7 Error-permitted range range of transfer baud .................................................................. 2-104 2.6 SI/O3, 4 Usage ....................................................................................................................... 2-106 2.6.1 Overview of the SI/O3,4 usage ........................................................................................ 2-106 2.6.2 Operation of SI/O3,4 ........................................................................................................ 2-108 2.7 A-D Converter Usage .............................................................................................................. 2-110 2.7.1 Overview of the A-D converter usage .............................................................................. 2-110 2.7.2 Operation of A-D converter (one-shot mode) .................................................................. 2-116 2.7.3 Operation of A-D Converter (in one-shot mode, an external trigger selected) ................ 2-118 2.7.4 Operation of A-D Converter (in one-shot mode, expanded analog input pin selected) ... 2-120 2.7.5 Operation of A-D Converter (in one-shot mode, external op-amp connection mode selected) . .................................................................................................................................................. 2-122 2.7.6 Operation of A-D Converter (in repeat mode) .................................................................. 2-124 2.7.7 Operation of A-D Converter (in single sweep mode) ....................................................... 2-126 2.7.8 Operation of A-D Converter (in repeat sweep mode 0) ................................................... 2-128 2.7.9 Operation of A-D Converter (in repeat sweep mode 1) ................................................... 2-130 2.7.10 Precautions for A-D Converter ....................................................................................... 2-132 2.7.11 Method of A-D Conversion (10-bit mode) ...................................................................... 2-133 2.7.12 Method of A-D Conversion (8-bit mode) ........................................................................ 2-135 2.7.13 Absolute Accuracy and Differential Non-Linearity Error ................................................ 2-137 2.7.14 Internal Equivalent Circuit of Analog Input ..................................................................... 2-139 2.7.15 Sensor’s Output Impedance under A-D Conversion ...................................................... 2-140 2.8 D-A Converter Usage .............................................................................................................. 2-142 2.8.1 Overview of the D-A converter usage .............................................................................. 2-142 2.8.2 D-A Converter Operation ................................................................................................. 2-143 2.9 DMAC Usage .......................................................................................................................... 2-144 2.9.1 Overview of the DMAC usage ......................................................................................... 2-144 2.9.2 Operation of DMAC (one-shot transfer mode) ................................................................. 2-148 2.9.3 Operation of DMAC (repeated transfer mode) ................................................................. 2-150 2.10 CRC Calculation Circuit Usage ............................................................................................. 2-152 2.10.1 Overview of the CRC calculation circuit usage .............................................................. 2-152 2.10.2 Operation of CRC Calculation Circuit ............................................................................ 2-153 2.11 Watchdog Timer Usage ........................................................................................................ 2-154 2.11.1 Overview of the watchdog timer usage .......................................................................... 2-154 2.11.2 Operation of Watchdog Timer ........................................................................................ 2-156 2.12 Address Match Interrupt Usage ............................................................................................ 2-158 2.12.1 Overview of the address match interrupt usage ............................................................ 2-158 2.12.2 Operation of Address Match Interrupt ............................................................................ 2-160 2.13 Key-Input Interrupt Usage ..................................................................................................... 2-162 2.13.1 Overview of the key-input interrupt usage ..................................................................... 2-162 2.13.2 Operation of Key-Input Interrupt .................................................................................... 2-164 2.14 Multiple interrupts usage ....................................................................................................... 2-166 2.14.1 Overview of the Multiple interrupts usage ...................................................................... 2-166 2.14.2 Multiple Interrupts operation .......................................................................................... 2-171 2.15 Power Control Usage ............................................................................................................ 2-173 2.15.1 Overview of the power control usage ............................................................................ 2-173 2.15.2 Stop Mode Set-Up ......................................................................................................... 2-178 2.15.3 Wait Mode Set-Up ......................................................................................................... 2-179 2.15.4 Precautions in Power Control ........................................................................................ 2-180 2.16 Programmable I/O Ports Usage ............................................................................................ 2-181 2.16.1 Overview of the programmable I/O ports usage ............................................................ 2-181 Chapter 3 Examples of Peripheral functions Applications ________ 3.1 Long-Period Timers ................................................................................................................ 2-192 3.2 Variable-Period Variable-Duty PWM Output ........................................................................... 2-196 3.3 Delayed One-Shot Output ...................................................................................................... 2-200 3.4 Buzzer Output ......................................................................................................................... 2-204 3.5 Solution for External Interrupt Pins Shortage ......................................................................... 2-206 3.6 Memory to Memory DMA Transfer .......................................................................................... 2-208 3.7 Controlling Power Using Stop Mode ....................................................................................... 2-212 3.8 Controling Power Using Wait Mode ........................................................................................ 2-216 Chapter 4 External Buses ___________________________________ 4.1 Overview of External Buses .................................................................................................... 2-222 4.2 Data Access ............................................................................................................................ 2-223 4.2.1 Data Bus Width ................................................................................................................ 2-223 4.2.2 Chip Selects and Address Bus ........................................................................................ 2-224 4.2.3 Bus Types ....................................................................................................................... 2-225 4.2.4 R/W Modes ..................................................................................................................... 2-225 4.3 Connection Examples ............................................................................................................. 2-226 4.3.1 16-bit Memory to 16-bit Width Data Bus Connection Example ........................................ 2-226 4.3.2 8-bit Memory to 16-bit Width Data Bus Connection Example .......................................... 2-227 4.3.3 8-bit Memory to 8-bit Width Data Bus Connection Example ........................................... 2-229 4.3.4 Two 8-bit and 16-Bit Memory to 16-Bit Width Data Bus Connection Example ................ 2-230 4.3.5 Chip Selects and Address Bus ........................................................................................ 2-231 4.4 Connectable Memories ........................................................................................................... 2-232 4.4.1 Operation Frequency and Access Time .......................................................................... 2-232 4.4.2 Connecting Low-Speed Memory ..................................................................................... 2-236 4.4.3 Connectable Memories .................................................................................................... 2-240 __________ _________ 4.5 Releasing an External Bus (HOLD input and HLDA output) ................................................... 2-241 4.6 Precautions for External Bus .................................................................................................. 2-242 Chapter 5 External ROM Version _____________________________ 5.1 Pin Configuration .................................................................................................................... 2-245 5.2 Pin Description ........................................................................................................................ 2-247 5.3 Memory Map ........................................................................................................................... 2-249 5.4 Processor Mode ...................................................................................................................... 2-253 Table of Contents Classified by Function Protection ........................................................................................................................................ 1-45 2.1.1 Overview of the protect usage ............................................................................................. 2-2 2.1.2 Protect Operation ................................................................................................................. 2-4 2.1.3 Precaution for Protect .......................................................................................................... 2-5 Timer A ........................................................................................................................................... 1-80 2.2.1 Overview of the timer A usage ............................................................................................. 2-6 2.2.2 Operation of Timer A (timer mode) .................................................................................... 2-12 2.2.3 Operation of Timer A (timer mode, gate function selected) ............................................... 2-14 2.2.4 Operation of Timer A (timer mode, pulse output function selected) .................................. 2-16 2.2.5 Operation of Timer A (event counter mode, reload type selected) .................................... 2-18 2.2.6 Operation of Timer A (event counter mode, free run type selected) .................................. 2-20 2.2.7 Operation of timer A (2-phase pulse signal process in event counter mode, normal mode selected) ................................................................................................................................ 2-22 2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode, multiply-by-4 mode selected) ............................................................................................................................ 2-24 2.2.9 Operation of Timer A (one-shot timer mode) ..................................................................... 2-26 2.2.10 Operation of Timer A (one-shot timer mode, external trigger selected) ........................... 2-28 2.2.11 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected) ........ 2-30 2.2.12 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected) .......... 2-32 2.2.13 Precautions for Timer A (timer mode) .............................................................................. 2-34 2.2.14 Precautions for Timer A (event counter mode) ................................................................ 2-35 2.2.15 Precautions for Timer A (one-shot timer mode) ............................................................... 2-36 2.2.16 Precautions for Timer A (pulse width modulation mode) ................................................. 2-37 Timer B ........................................................................................................................................... 1-90 2.3.1 Overview of the timer B usage ........................................................................................... 2-38 2.3.2 Operation of Timer B (timer mode) .................................................................................... 2-42 2.3.3 Operation of Timer B (event counter mode) ...................................................................... 2-44 2.3.4 Operation of Timer B (pulse period measurement mode) ................................................. 2-46 2.3.5 Operation of Timer B (pulse width measurement mode) ................................................... 2-48 2.3.6 Precautions for Timer B (timer mode, event counter mode) .............................................. 2-50 2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode) ......................... 2-51 Serial I/O ....................................................................................................................................... 1-108 2.4.1 Overview of the clock-synchronous serial I/O usage ......................................................... 2-52 2.4.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode) ................... 2-60 2.4.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected) ...................................................................... 2-64 2.4.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode) ......................... 2-68 2.4.5 Precautions for Serial I/O (in clock-synchronous serial I/O) .............................................. 2-72 2.5.1 Overview of the clock-asynchronous serial I/O usage ....................................................... 2-74 2.5.2 Operation of Serial I/O (transmission in UART mode) ....................................................... 2-84 2.5.3 Operation of Serial I/O (reception in UART mode) ............................................................ 2-88 2.5.4 Operation of Serial I/O (transmission used for SIM interface) ........................................... 2-92 2.5.5 Operation of Serial I/O (reception used for SIM interface) ................................................. 2-96 2.5.6 Clock Signals in used for the SIM Interface ..................................................................... 2-100 2.5.7 Error-permitted range range of transfer baud .................................................................. 2-104 2.6.1 Overview of the SI/O3,4 usage ........................................................................................ 2-106 2.6.2 Operation of SI/O3,4 ........................................................................................................ 2-108 A-D Converter ............................................................................................................................... 1-149 2.7.1 Overview of the A-D converter usage .............................................................................. 2-110 2.7.2 Operation of A-D converter (one-shot mode) .................................................................. 2-116 2.7.3 Operation of A-D Converter (in one-shot mode, an external trigger selected) ................ 2-118 2.7.4 Operation of A-D Converter (in one-shot mode, expanded analog input pin selected) ... 2-120 2.7.5 Operation of A-D Converter (in one-shot mode, external op-amp connection mode selected) . .................................................................................................................................................. 2-122 2.7.6 Operation of A-D Converter (in repeat mode) .................................................................. 2-124 2.7.7 Operation of A-D Converter (in single sweep mode) ....................................................... 2-126 2.7.8 Operation of A-D Converter (in repeat sweep mode 0) ................................................... 2-128 2.7.9 Operation of A-D Converter (in repeat sweep mode 1) ................................................... 2-130 2.7.10 Precautions for A-D Converter ....................................................................................... 2-132 2.7.11 Method of A-D Conversion (10-bit mode) ...................................................................... 2-133 2.7.12 Method of A-D Conversion (8-bit mode) ........................................................................ 2-135 2.7.13 Absolute Accuracy and Differential Non-Linearity Error ................................................ 2-137 2.7.14 Internal Equivalent Circuit of Analog Input ..................................................................... 2-139 2.7.15 Sensor’s Output Impedance under A-D Conversion ...................................................... 2-140 D-A Converter ............................................................................................................................... 1-159 2.8.1 Overview of the D-A converter usage .............................................................................. 2-142 2.8.2 D-A Converter Operation ................................................................................................. 2-143 DMAC ............................................................................................................................................. 1-68 2.9.1 Overview of the DMAC usage ......................................................................................... 2-144 2.9.2 Operation of DMAC (one-shot transfer mode) ................................................................. 2-148 2.9.3 Operation of DMAC (repeated transfer mode) ................................................................. 2-150 CRC Calculation Circuit ................................................................................................................ 1-161 2.10.1 Overview of the CRC calculation circuit usage .............................................................. 2-152 2.10.2 Operation of CRC Calculation Circuit ............................................................................ 2-153 Watchdog Timer .............................................................................................................................. 1-66 2.11.1 Overview of the watchdog timer usage .......................................................................... 2-154 2.11.2 Operation of Watchdog Timer ........................................................................................ 2-156 Overview of Interrupt ....................................................................................................................... 1-46 2.12.1 Overview of the address match interrupt usage ............................................................ 2-158 2.12.2 Operation of Address Match Interrupt ............................................................................ 2-160 2.13.1 Overview of the key-input interrupt usage ..................................................................... 2-162 2.13.2 Operation of Key-Input Interrupt .................................................................................... 2-164 2.14.1 Overview of the Multiple interrupts usage ...................................................................... 2-166 2.14.2 Multiple Interrupts operation .......................................................................................... 2-171 Power Control ................................................................................................................................. 1-43 2.15.1 Overview of the power control usage ............................................................................ 2-173 2.15.2 Stop Mode Set-Up ......................................................................................................... 2-178 2.15.3 Wait Mode Set-Up ......................................................................................................... 2-179 2.15.4 Precautions in Power Control ........................................................................................ 2-180 Programmable I/O Ports ............................................................................................................... 1-163 2.16.1 Overview of the programmable I/O ports usage ............................................................ 2-181 Quick Reference to Pages Classified by Address Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004A16 004B16 Register Page Address 004016 004116 004216 004316 Register Page Processor mode register 0 (PM0) Processor mode register 1 (PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Chip select control register (CSR) Address match interrupt enable register (AIER) Protect register (PRCR) 1-23 1-39 1-29 1-63 1-38 004416 004516 004616 004716 004816 004916 INT3 interrupt control register (INT3IC) Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) SI/O4 interrupt control register (S4IC) INT5 interrupt control register (INT5IC) SI/O3 interrupt control register (S3IC) INT4 interrupt control register (INT4IC) Bus collision detection interrupt control register (BCNIC) Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Address match interrupt register 0 (RMAD0) 1-67 1-63 004C16 004D16 004E16 004F16 005016 005116 005216 DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) 1-52 Address match interrupt register 1 (RMAD1) 1-63 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 DMA0 source pointer (SAR0) 1-72 005F16 006016 006116 006216 Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) Timer A4 interrupt control register (TA4IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) INT2 interrupt control register (INT2IC) DMA0 destination pointer (DAR0) 1-72 006316 006416 006516 DMA0 transfer counter (TCR0) 1-72 DMA0 control register (DM0CON) 1-71 032A16 032B16 032C16 032D16 032E16 DMA1 source pointer (SAR1) 1-72 032F16 033016 033116 033216 DMA1 destination pointer (DAR1) 1-72 033316 033416 033516 033616 033716 033816 033916 DMA1 transfer counter (TCR1) 1-72 DMA1 control register (DM1CON) 1-71 033A16 033B16 033C16 033D16 033E16 033F16 Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Quick Reference to Pages Classified by Address Address 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 Register Timer B3, 4, 5 count start flag (TBSR) Timer A1-1 register (TA11) Timer A2-1 register (TA21) Timer A4-1 register (TA41) Three-phase PWM control register 0(INVC0) Three-phase PWM control register 1(INVC1) Three-phase output buffer register 0(IDB0) Three-phase output buffer register 1(IDB1) Dead time timer(DTT) Timer B2 interrupt occurrence frequency set counter(ICTB2) Page 1-91 Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 Register 1-98 Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) Timer A0 register (TA0) Timer A1 register (TA1) Timer A2 register (TA2) Timer A3 register (TA3) Timer A4 register (TA4) Timer B0 register (TB0) Timer B1 register (TB1) Timer B2 register (TB2) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) Page 1-81 1-82 1-81 1-96 1-97 1-81 Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5) 1-91 1-91 1-80 Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register (TB5MR) Interrupt request cause select register (IFSR) SI/O3 transmit/receive register (S3TRR) SI/O3 control register (S3C) SI/O3 bit rate generator (S3BRG) SI/O4 transmit/receive register (S4TRR) SI/O4 control register (S4C) SI/O4 bit rate generator (S4BRG) 039B16 1-90 1-61 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 1-90 UART0 transmit/receive mode register (U0MR) 1-113 1-112 1-114 1-115 1-112 1-113 1-112 1-114 1-115 1-112 1-116 UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) 1-146 UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON) UART2 special mode register 3 (U2SMR3) UART2 special mode register 2 (U2SMR2) UART2 special mode register (U2SMR) UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) 1-137 1-141 1-137 1-113 1-112 1-114 1-115 1-112 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 Flash memory control register 1 (FMR1) (Note 1) 1-221 Flash memory control register 0 (FMR0) (Note 1) DMA0 request cause select register (DM0SL) 1-70 DMA1 request cause select register (DM1SL) CRC data register (CRCD) CRC input register (CRCIN) 1-71 1-161 Note 1 : This register is only exist in flash memory version. Note 2 : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Quick Reference to Pages Classified by Address Address 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Register Page A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) 1-152 A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7) A-D control register 2 (ADCON2) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) D-A register 1 (DA1) D-A control register (DACON) 1-152 1-151 1-160 Port P0 register (P0) Port P1 register (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 register (P2) Port P3 register (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 register (P4) Port P5 register (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 register (P6) Port P7 register (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 register (P8) Port P9 register (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 register (P10) Port P10 direction register (PD10) 1-169 1-168 1-169 1-168 1-169 1-168 1-169 1-168 1-169 1-168 1-169 1-168 Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR) 1-170 1-171 Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Chapter 1 Hardware Mitsubishi microcomputers M16C / 62A Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description The M16C/62A group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. The M16C/62A group includes a wide range of products with different internal memory types and sizes and various package types. Features • Memory capacity .................................. ROM (See Figure 1.1.4. ROM Expansion) RAM 3K to 20K bytes • Shortest instruction execution time ...... 62.5ns (f(XIN)=16MHZ, VCC=5V) 100ns (f(XIN)=10MHZ, VCC=3V, with software one-wait) : Mask ROM, flash memory 5V version • Supply voltage ..................................... 4.2V to 5.5V (f(XIN)=16MHZ, without software wait) : Mask ROM, flash memory 5V version 2.7V to 5.5V (f(XIN)=10MHZ with software one-wait) : Mask ROM, flash memory 5V version • Low power consumption ...................... 25.5mW ( f(XIN)=10MHZ, with software one-wait, VCC = 3V) • Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt) • Multifunction 16-bit timer ...................... 5 output timers + 6 input timers • Serial I/O .............................................. 5 channels (3 for UART or clock synchronous, 2 for clock synchronous) • DMAC .................................................. 2 channels (trigger: 24 sources) • A-D converter ....................................... 10 bits X 8 channels (Expandable up to 10 channels) • D-A converter ....................................... 8 bits X 2 channels • CRC calculation circuit ......................... 1 circuit • Watchdog timer .................................... 1 line • Programmable I/O ............................... 87 lines _______ • Input port .............................................. 1 line (P85 shared with NMI pin) • Memory expansion .............................. Available (to a maximum of 1M bytes) • Chip select output ................................ 4 lines • Clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Applications Audio, cameras, office equipment, communications equipment, portable equipment ------Table of Contents-----Central Processing Unit (CPU) .................. 1-12 Reset .......................................................... 1-15 Processor Mode ......................................... 1-22 Clock Generating Circuit ............................ 1-36 Protection ................................................... 1-46 Interrupts .................................................... 1-46 Watchdog Timer ......................................... 1-66 DMAC ........................................................ 1-68 Timer .......................................................... 1-78 Serial I/O .................................................. 1-108 A-D Converter .......................................... 1-149 D-A Converter .......................................... 1-159 CRC Calculation Circuit ........................... 1-161 Programmable I/O Ports .......................... 1-163 Electrical characteristic ............................ 1-174 Flash memory version .............................. 1-217 1-2 Mitsubishi microcomputers M16C / 62A Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Configuration Figures 1.1.1 and 1.1.2 show the pin configurations (top view). PIN CONFIGURATION (top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 23 45 6 7 8 M16C/62A Group 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL/TA0IN/TB5IN (Note) P70/TXD2/SDA/TA0OUT (Note) Note: P70 and P71 are N channel open-drain output pin. Package: 100P6S-A Figure 1.1.1. Pin configuration (top view) 1-3 Mitsubishi microcomputers M16C / 62A Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (top view) P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P12/D10 P11/D9 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 12 345 67 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 M16C/62A Group P42/A18 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P70/TXD2/SDA/TA0OUT (Note) P71/RxD2/SCL/TA0IN/TB5IN (Note) P72/CLK2/TA1OUT/V P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V Note: P70 and P71 are N channel open-drain output pin. Package: 100P6Q-A Figure 1.1.2. Pin configuration (top view) 1-4 Mitsubishi microcomputers M16C / 62A Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Diagram Figure 1.1.3 is a block diagram of the M16C/62A group. 8 8 8 8 8 8 8 I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Internal peripheral functions Timer Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits) A-D converter (10 bits X 8 channels Expandable up to 10 channels) System clock generator XIN-XOUT XCIN-XCOUT Clock synchronous SI/O 8 Port P8 UART/clock synchronous SI/O (8 bits X 3 channels) CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) (8 bits X 2 channels) 7 Port P85 M16C/60 series16-bit CPU core Registers Program counter PC Memory ROM (Note 1) RAM (Note 2) Watchdog timer (15 bits) DMAC (2 channels) D-A converter (8 bits X 2 channels) R0H R0L R0H R0L R1H R1L R1H R1L R2 R2 R3 R3 A0 A0 A1 A1 FB FB SB Port P9 Stack pointer ISP USP Vector table INTB Flag register FLG 8 Port P10 Multiplier 8 Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type. Figure 1.1.3. Block diagram of M16C/62A group 1-5 Mitsubishi microcomputers M16C / 62A Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Performance Outline Table 1.1.1 is a performance outline of M16C/62A group. Table 1.1.1. Performance outline of M16C/62A group Performance 91 instructions 62.5ns(f(XIN)=16MHZ, VCC=5V) 100ns (f(XIN)=10MHZ , VCC=3V, with software one-wait) : Mask ROM, flash memory 5V version Memory ROM (See the figure 1.1.4. ROM Expansion) capacity RAM 3K to 20K bytes I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1 Input port P85 1 bit x 1 Multifunction TA0, TA1, TA2, TA3, TA4 16 bits x 5 timer TB0, TB1, TB2, TB3, TB4, TB5 16 bits x 6 Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3 SI/O3, SI/O4 A-D converter D-A converter DMAC CRC calculation circuit Watchdog timer Interrupt Clock generating circuit Supply voltage (Clock synchronous) x 2 10 bits x (8 + 2) channels 8 bits x 2 2 channels (trigger: 24 sources) CRC-CCITT 15 bits x 1 (with prescaler) 25 internal and 8 external sources, 4 software sources, 7 levels 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) 4.2V to 5.5V (f(XIN)=16MHZ, without software wait) : Mask ROM, flash memory 5V version 2.7V to 5.5V (f(XIN)=10MHZ with software one-wait) : Mask ROM, flash memory 5V version 25.5mW (f(XIN) = 10MHZ, VCC=3V with software one-wait) 5V 5mA Available (to a maximum of 1M bytes) CMOS high performance silicon gate 100-pin plastic mold QFP Item Number of basic instructions Shortest instruction execution time Power consumption I/O I/O withstand voltage characteristics Output current Memory expansion Device configuration Package 1-6 Mitsubishi microcomputers M16C / 62A Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mitsubishi plans to release the following products in the M16C/62A group: (1) Support for mask ROM version, external ROM version, and flash memory version (2) ROM capacity (3) Package 100P6S-A : Plastic molded QFP (mask ROM, and flash memory versions) 100P6Q-A : Plastic molded QFP(mask ROM, and flash memory versions) ROM Size (Byte) External ROM 256K 128K 96K 64K 32K M30624MGA-XXXFP/GP M30620MCA-XXXFP/GP M30622MCA-XXXFP/GP M30620MAA-XXXFP/GP M30622MAA-XXXFP/GP M30620M8A-XXXFP/GP M30622M8A-XXXFP/GP M30622M4A-XXXFP/GP Mask ROM version Flash memory version External ROM version M30624FGAFP/GP M30620FCAFP/GP M30620SAFP/GP M30622SAFP/GP Figure 1.1.4. ROM expansion The M16C/62A group products currently supported are listed in Table 1.1.2. Table 1.1.2. M16C/62A group Type No. M30622M4A-XXXFP M30622M4A-XXXGP M30620M8A-XXXFP M30620M8A-XXXGP M30622M8A-XXXFP M30622M8A-XXXGP M30620MAA-XXXFP M30620MAA-XXXGP M30622MAA-XXXFP M30622MAA-XXXGP M30620MCA-XXXFP M30620MCA-XXXGP M30622MCA-XXXFP M30622MCA-XXXGP M30624MGA-XXXFP M30624MGA-XXXGP M30620FCAFP M30620FCAGP M30624FGAFP M30624FGAGP M30620SAFP M30620SAGP M30622SAFP M30622SAGP **: Under development 10K byte 3K byte 256K byte 128K byte 256K byte 128K byte 5K byte 20K byte 10K byte 96K byte 5K byte 64K byte 4K byte 10K byte ROM capacity 32K byte RAM capacity 3K byte 10K byte Package type 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 10K byte 20K byte 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A June, 2001 Remarks Mask ROM version Flash memory 5V version External ROM version ** 1-7 Mitsubishi microcomputers M16C / 62A Group Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Type No. M 3 0 6 2 2 M 8 A– X X X F P Package type: FP : Package GP : 100P6S-A 100P6Q-A ROM No. Omitted for flash memory version ROM capacity: 4 : 32K bytes 8 : 64K bytes A : 96K bytes C : 128K bytes G: 256K bytes Memory type: M : Mask ROM version S : External ROM version F : Flash memory version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/62 Group M16C Family Figure 1.1.5. Type No., memory size, and package 1-8 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Pin Description Pin name VCC, VSS CNVSS Signal name Power supply input CNVSS Input I/O type Function Supply 2.7V to 5.5 V to the VCC pin. Supply 0 V to the VSS pin. This pin switches between processor modes. Connect this pin to the VSS pin when after a reset you want to start operation in single-chip mode (memory expansion mode) or the VCC pin when starting operation in microprocessor mode. A “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit.Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin selects the width of an external data bus. A 16-bit width is selected when this input is “L”; an 8-bit width is selected when this input is “H”. This input must be fixed to either “H” or “L”. Connect this pin to the VSS pin when not using external data bus. This pin is a power supply input for the A-D converter. Connect this pin to VCC. This pin is a power supply input for the A-D converter. Connect this pin to VSS. Input Input/output This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input in single-chip mode, the port can be set to have or not have a pull-up resistor in units of four bits by software. In memory expansion and microprocessor modes, selection of the internal pull-resistor is not available. When set as a separate bus, these pins input and output data (D0–D7). This is an 8-bit I/O port equivalent to P0. P15 to P17 also function as external interrupt pins as selected by software. When set as a separate bus, these pins input and output data (D8–D15). This is an 8-bit I/O port equivalent to P0. These pins output 8 low-order address bits (A0–A7). If the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (D0–D7) and output 8 low-order address bits (A0–A7) separated in time by multiplexing. If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D0–D6) and output address (A1–A7) separated in time by multiplexing. They also output address (A0). This is an 8-bit I/O port equivalent to P0. These pins output 8 middle-order address bits (A8–A15). If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D7) and output address (A8) separated in time by multiplexing. They also output address (A9–A15). This is an 8-bit I/O port equivalent to P0. These pins output A16–A19 and CS0–CS3 signals. A16–A19 are 4 highorder address bits. CS0–CS3 are chip select signals used to specify an access space. RESET XIN XOUT Reset input Clock input Clock output Input Input Output BYTE External data bus width select input Analog power supply input Analog power supply input Reference voltage input I/O port P0 Input AVCC AVSS VREF P00 to P07 D0 to D7 P10 to P17 I/O port P1 Input/output Input/output D8 to D15 P20 to P27 A0 to A7 A0/D0 to A7/D7 I/O port P2 Input/output Input/output Output Input/output A0 A1/D0 to A7/D6 P30 to P37 A8 to A15 A8/D7, A9 to A15 P40 to P47 A16 to A19, CS0 to CS3 I/O port P4 I/O port P3 Output Input/output Input/output Output Input/output Output Input/output Output Output 1-9 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Description Pin Description Pin name P50 to P57 Signal name I/O port P5 I/O type Input/output Function This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of the same frequency as XCIN as selected by software. Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control. WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses when the WRL signal is “L” and to the odd addresses when the WRH signal is “L”. Data is read when RD is “L”. WR, BHE, and RD selected Data is written when WR is “L”. Data is read when RD is “L”. Odd addresses are accessed when BHE is “L”. Use this mode when using an 8-bit external data bus. While the input level at the HOLD pin is “L”, the microcomputer is placed in the hold state. While in the hold state, HLDA outputs a “L” level. ALE is used to latch the address. While the input level of the RDY pin is “L”, the microcomputer is in the ready state. This is an 8-bit I/O port equivalent to P0. When used for input in singlechip, memory expansion, and microprocessor modes, the port can be set to have or not have a pull-up resistor in units of four bits by software. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel open-drain output). Pins in this port also function as timer A0–A3, timer B5 or UART2 I/O pins as selected by software. P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from “H” to “L”. The NMI function cannot be cancelled using software. The pull-up cannot be set for this pin. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as SI/O3, 4 I/O pins, Timer B0–B4 input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A-D converter input pins as selected by software. Furthermore, P104 –P107 also function as input pins for the key input interrupt function. WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY Output Output Output Output Output Input Output Input P60 to P67 I/O port P6 Input/output P70 to P77 I/O port P7 Input/output P80 to P84, P86, P87, P85 I/O port P8 Input/output Input/output Input/output I/O port P85 Input P90 to P97 I/O port P9 Input/output P100 to P107 I/O port P10 Input/output 1-10 Mitsubishi microcomputers M16C / 62A Group Memory SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Operation of Functional Blocks The M16C/62A group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, and I/O ports. The following explains each unit. Memory Figure 1.3.1 is a memory map of the M16C/62A group. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30622MCA-XXXFP, there is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as _______ the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30622MCA-XXXFP, 5K bytes of internal RAM is mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.6.1 to 1.6.3 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. For example, in the M30622MCA-XXXFP, the following spaces cannot be used. • The space between 0180016 and 03FFF16 (Memory expansion and microprocessor modes) • The space between D000016 and DFFFF16 (Memory expansion mode) 0000016 SFR area For details, see Figures 1.6.1 to 1.6.3 FFE0016 0040016 RAM size 3K bytes 4K bytes 5K bytes 10K bytes 20K bytes Address XXXXX16 00FFF16 013FF16 017FF16 02BFF16 053FF16 Internal RAM area XXXXX16 Internal reserved area (Note 1) Special page vector table 0400016 External area FFFDC16 Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC NMI Reset ROM size 32K bytes 64K bytes 96K bytes 128K bytes 256K bytes Address YYYYY16 F800016 F000016 E800016 E000016 C000016 D000016 YYYYY16 Internal reserved area (Note 2) Internal ROM area FFFFF16 FFFFF16 Note 1: During memory expansion and microprocessor modes, can not be used. Note 2: In memory expansion mode, can not be used. Note 3: These memory maps show an instance in which PM13 is set to 0; but in the case of products in which the internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which PM13 is set to 1. Figure 1.3.1. Memory map 1-11 Mitsubishi microcomputers M16C / 62A Group CPU Central Processing Unit (CPU) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks. b15 b8 b7 b0 R0(Note) H L b15 b8 b7 b0 b19 b0 R1(Note) H L Data registers PC Program counter b15 b0 b19 b0 R2(Note) INTB H L Interrupt table register b0 b15 b0 b15 R3(Note) USP User stack pointer b15 b0 b15 b0 A0(Note) Address registers ISP Interrupt stack pointer b15 b0 b15 b0 A1(Note) SB Static base register b15 b0 b15 b0 FB(Note) Frame base registers FLG Flag register IPL U I OBS Z DC Note: These registers consist of two register banks. Figure 1.4.1. Central processing unit register (1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3) Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1). (2) Address registers (A0 and A1) Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 1-12 Mitsubishi microcomputers M16C / 62A Group CPU SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Frame base register (FB) Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing. (4) Program counter (PC) Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed. (5) Interrupt table register (INTB) Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) Stack pointer (USP/ISP) Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG). (7) Static base register (SB) Static base register (SB) is configured with 16 bits, and is used for SB relative addressing. (8) Flag register (FLG) Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag register (FLG). The following explains the function of each flag: • Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. • Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged. • Bit 2: Zero flag (Z flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”. • Bit 3: Sign flag (S flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”. • Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”. • Bit 5: Overflow flag (O flag) This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”. • Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged. 1-13 Mitsubishi microcomputers M16C / 62A Group CPU SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed. • Bits 8 to 11: Reserved area • Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. • Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details. b15 b0 IPL U I OBSZDC Flag register (FLG) Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area Figure 1.4.2. Flag register (FLG) 1-14 Mitsubishi microcomputers M16C / 62A Group Reset Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence. 5V 4.0V VCC 0V 5V RESET 0.8V 0V Example when VCC = 5V. RESET VCC Figure 1.5.1. Example reset circuit XIN More than 20 cycles are needed Microprocessor mode BYTE = “H” RESET BCLK 24cycles BCLK Content of reset vector Address FFFFC16 FFFFD16 FFFFE16 RD WR CS0 Microprocessor mode BYTE = “L” Address FFFFC16 FFFFE16 Content of reset vector RD WR CS0 Single chip mode Address FFFFC16 FFFFE16 Content of reset vector Figure 1.5.2. Reset sequence 1-15 Mitsubishi microcomputers M16C / 62A Group Reset ____________ SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.5.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.5.3 and 1.5.4 show the internal status of the microcomputer immediately after the reset is cancelled. ____________ Table 1.5.1. Pin status when RESET pin level is “L” Status Pin name P0 P1 P2, P3, P40 to P43 P44 P45 to P47 CNVSS = VCC CNVSS = VSS BYTE = VSS Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) Data input (floating) Data input (floating) Address output (undefined) CS0 output (“H” level is output) Input port (floating) (pull-up resistor is on) WR output (“H” level is output) BHE output (undefined) RD output (“H” level is output) BCLK output BYTE = VCC Data input (floating) Input port (floating) Address output (undefined) CS0 output (“H” level is output) Input port (floating) (pull-up resistor is on) WR output (“H” level is output) BHE output (undefined) RD output (“H” level is output) BCLK output P50 P51 P52 P53 P54 Input port (floating) Input port (floating) Input port (floating) Input port (floating) Input port (floating) HLDA output (The output value HLDA output (The output value depends on the input to the depends on the input to the HOLD pin) HOLD pin) HOLD input (floating) ALE output (“L” level is output) RDY input (floating) Input port (floating) HOLD input (floating) ALE output (“L” level is output) RDY input (floating) Input port (floating) P55 P56 P57 Input port (floating) Input port (floating) Input port (floating) P6, P7, P80 to P84, P86, P87, P9, P10 Input port (floating) 1-16 Mitsubishi microcomputers M16C / 62A Group Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Processor mode register 0 (Note 1) (2) Processor mode register 1 (3) System clock control register 0 (4) System clock control register 1 (5) Chip select control register (6) Address match interrupt enable register (7) Protect register (8) Watchdog timer control register (000416)··· 0016 0 (29) UART1 receive interrupt control register (30) Timer A0 interrupt control register (31) Timer A1 interrupt control register (32) Timer A2 interrupt control register (33) Timer A3 interrupt control register (34) Timer A4 interrupt control register (35) Timer B0 interrupt control register (36) Timer B1 interrupt control register (37) Timer B2 interrupt control register (38) INT0 interrupt control register (39) INT1 interrupt control register (40) INT2 interrupt control register (41) Timer B3,4,5 count start flag (42) Three-phase PWM control register 0 (43) Three-phase PWM control register 1 (44) Three-phase output buffer register 0 (45) Three-phase output buffer register 1 (46) Timer B3 mode register (47) Timer B4 mode register (48) Timer B5 mode register (49) Interrupt cause select register (50) SI/O3 control register (51) SI/O4 control register (005416)··· (005516)··· (005616)··· (005716)··· (005816)··· (005916)··· (005A16)··· (005B16)··· (005C16)··· (005D16)··· (005E16)··· (005F16)··· ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 00?000 00?000 00?000 (000516)··· 0 0 0 0 0 (000616)··· 0 1 0 0 1 0 0 0 (000716)··· 0 0 1 0 0 0 0 0 (000816)··· 0 0 0 0 0 0 0 1 (000916)··· (000A16)··· 00 000 (000F16)··· 0 0 0 ? ? ? ? ? (001016)··· (001116)··· (001216)··· 0016 0016 (9) Address match interrupt register 0 0000 (10) Address match interrupt register 1 (001416)··· (001516)··· (001616)··· 0016 0016 (034016)··· 0 0 0 (034816)··· (034916)··· (034A16)··· (034B16)··· (035B16)··· 0 0 ? (035C16)··· 0 0 ? (035D16)··· 0 0 ? (035F16)··· (036216)··· (036616)··· (037516)··· (037616)··· 0016 0016 0016 0016 0000 0000 0000 0000 (11) DMA0 control register (12) DMA1 control register (13) INT3 interrupt control register (14) Timer B5 interrupt control register (15) Timer B4 interrupt control register (16) Timer B3 interrupt control register (17) SI/O4 interrupt control register (18) SI/O3 interrupt control register (19) Bus collision detection interrupt control register (002C16)··· 0 0 0 0 0 ? 0 0 (003C16)··· 0 0 0 0 0 ? 0 0 (004416)··· (004516)··· (004616)··· (004716)··· (004816)··· (004916)··· 00?000 ?000 ?000 ?000 00?000 00?000 0016 4016 4016 ? 0016 0016 (004A16)··· ?000 (20) DMA0 interrupt control register (004B16)··· (004C16)··· (004D16)··· (004E16)··· (004F16)··· (005016)··· (005116)··· (005216)··· (005316)··· ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 (52) UART2 special mode register 3 (Note 2) (53) UART2 special mode register 2 (21) DMA1 interrupt control register (22) Key input interrupt control register (23) A-D conversion interrupt control register (24) UART2 transmit interrupt control register (25) UART2 receive interrupt control register (26) UART0 transmit interrupt control register (27) UART0 receive interrupt control register (28)UART1 transmit interrupt control register (54) UART2 special mode register (55) UART2 transmit/receive mode register (56) UART2 transmit/receive control register 0 (57) UART2 transmit/receive control register 1 (037716)··· (037816)··· 0016 (037C16)··· 0 0 0 0 1 0 0 0 (037D16)··· 0 0 0 0 0 0 1 0 x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note 1: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset. Note 2: “0016” is read out when set bit 7 (SDDS) of the UART2 special mode register ( address 037716) to “1”. Figure 1.5.3. Device's internal status after a reset is cleared 1-17 Mitsubishi microcomputers M16C / 62A Group Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (58) Count start flag (59) Clock prescaler reset flag (60) One-shot start flag (61) Trigger select flag (62) Up-down flag (63) Timer A0 mode register (64) Timer A1 mode register (65) Timer A2 mode register (66) Timer A3 mode register (67) Timer A4 mode register (68) Timer B0 mode register (69) Timer B1 mode register (70) Timer B2 mode register (71) UART0 transmit/receive mode register (72) UART0 transmit/receive control register 0 (73) UART0 transmit/receive control register 1 (74) UART1 transmit/receive mode register (75) UART1 transmit/receive control register 0 (76) UART1 transmit/receive control register 1 (77) UART transmit/receive control register 2 (78) Flash memory control register 1 (Note2) (79) Flash memory control register 0 (Note2) (80) DMA0 cause select register (81) DMA1 cause select register (82) A-D control register 2 (83) A-D control register 0 (038016)··· (038116)··· 0 (038216)··· 0 0 (038316)··· (038416)··· (039616)··· (039716)··· (039816)··· (039916)··· (039A16)··· (039B16)··· 0 0 ? (039C16)··· 0 0 ? (039D16)··· 0 0 ? (03A016)··· 0016 (84) A-D control register 1 (85) D-A control register (03D716)··· (03DC16)··· (03E216)··· (03E316)··· (03E616)··· (03E716)··· (03EA16)··· (03EB16)··· (03EE16)··· (03EF16)··· (03F216)··· 0 0 (03F316)··· (03F616)··· (03FC16)··· 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 00000 0016 0016 0016 0016 0016 0016 000016 000016 000016 0000016 000016 000016 000016 000016 00000 0016 0016 0016 0016 0016 0016 0016 0000 0000 0000 0016 (86) Port P0 direction register (87) Port P1 direction register (88) Port P2 direction register (89) Port P3 direction register (90) Port P4 direction register (91) Port P5 direction register (92) Port P6 direction register (93) Port P7 direction register (94) Port P8 direction register (95) Port P9 direction register (96) Port P10 direction register (97) Pull-up control register 0 (03A416)··· 0 0 0 0 1 0 0 0 (03A516)··· 0 0 0 0 0 0 1 0 (03A816)··· 0016 (98) Pull-up control register 1(Note1) (03FD16)··· (99) Pull-up control register 2 (100) Port control register (101) Data registers (R0/R1/R2/R3) (102) Address registers (A0/A1) (103) Frame base register (FB) (104) Interrupt table register (INTB) (105) User stack pointer (USP) (106) Interrupt stack pointer (ISP) (107) Static base register (SB) (03FE16)··· (03FF16)··· (03AC16)··· 0 0 0 0 1 0 0 0 (03AD16)··· 0 0 0 0 0 0 1 0 (03B016)··· 0000000 (03B616)··· ? ? ? ? 0 ? ? ? (03B716)··· (03B816)··· (03BA16)··· 000001 0016 0016 0 (03D416)··· 0 0 0 0 (108) Flag register (FLG) (03D616)··· 0 0 0 0 0 ? ? ? x : Nothing is mapped to this bit ? : Undefined The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note1: When the VCC level is applied to the CNVSS pin, it is 0216 at a reset. Note2: This register is only exist in flash memory version. Figure 1.5.4. Device's internal status after a reset is cleared 1-18 Mitsubishi microcomputers M16C / 62A Group SFR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Chip select control register (CSR) Address match interrupt enable register (AIER) Protect register (PRCR) 004416 004516 004616 004716 004816 004916 004A16 004B16 INT3 interrupt control register (INT3IC) Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) SI/O4 interrupt control register (S4IC) INT5 interrupt control register (INT5IC) SI/O3 interrupt control register (S3IC) INT4 interrupt control register (INT4IC) Bus collision detection interrupt control register (BCNIC) Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Address match interrupt register 0 (RMAD0) 004C16 004D16 004E16 004F16 005016 005116 005216 DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) Address match interrupt register 1 (RMAD1) 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 DMA0 source pointer (SAR0) 005F16 006016 006116 006216 Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) Timer A4 interrupt control register (TA4IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) INT2 interrupt control register (INT2IC) DMA0 destination pointer (DAR0) 006316 006416 006516 DMA0 transfer counter (TCR0) DMA0 control register (DM0CON) 032A16 032B16 032C16 032D16 032E16 DMA1 source pointer (SAR1) 032F16 033016 033116 033216 DMA1 destination pointer (DAR1) 033316 033416 033516 033616 033716 033816 033916 DMA1 transfer counter (TCR1) DMA1 control register (DM1CON) 033A16 033B16 033C16 033D16 033E16 033F16 Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.6.1. Location of peripheral unit control registers (1) 1-19 Mitsubishi microcomputers M16C / 62A Group SFR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 Timer B3, 4, 5 count start flag (TBSR) Timer A1-1 register (TA11) Timer A2-1 register (TA21) Timer A4-1 register (TA41) Three-phase PWM control register 0(INVC0) Three-phase PWM control register 1(INVC1) Three-phase output buffer register 0(IDB0) Three-phase output buffer register 1(IDB1) Dead time timer(DTT) Timer B2 interrupt occurrence frequency set counter(ICTB2) 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) Timer A0 (TA0) Timer A1 (TA1) Timer A2 (TA2) Timer A3 (TA3) Timer A4 (TA4) Timer B0 (TB0) Timer B1 (TB1) Timer B2 (TB2) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5) Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register (TB5MR) Interrupt cause select register (IFSR) SI/O3 transmit/receive register (S3TRR) SI/O3 control register (S3C) SI/O3 bit rate generator (S3BRG) SI/O4 transmit/receive register (S4TRR) SI/O4 control register (S4C) SI/O4 bit rate generator (S4BRG) 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 UART0 transmit/receive mode register (U0MR) UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON) UART2 special mode register 3(U2SMR3) UART2 special mode register 2(U2SMR2) UART2 special mode register (U2SMR) UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 Flash memory control register 1 (FMR1) (Note1) Flash memory control register 0 (FMR0) (Note1) DMA0 request cause select register (DM0SL) DMA1 request cause select register (DM1SL) CRC data register (CRCD) CRC input register (CRCIN) Note 1: This register is only exist in flash memory version. Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.6.2. Location of peripheral unit control registers (2) 1-20 Mitsubishi microcomputers M16C / 62A Group SFR SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7) A-D control register 2 (ADCON2) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) D-A register 1 (DA1) D-A control register (DACON) Port P0 (P0) Port P1 (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 (P2) Port P3 (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 (P4) Port P5 (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 (P6) Port P7 (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 (P8) Port P9 (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 (P10) Port P10 direction register (PD10) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR) Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 1.6.3. Location of peripheral unit control registers (3) 1-21 Mitsubishi microcomputers M16C / 62A Group Software Reset Software Reset SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM are preserved. Processor Mode (1) Types of Processor Mode One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode. • Single-chip mode In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. However, after the reset has been released and the operation of shifting from the microprocessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the single-chip mode. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions. • Memory expansion mode In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the operation of shifting from the microprocessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.) • Microprocessor mode In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The internal ROM area cannot be accessed. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus width and register settings. (See “Bus Settings” for details.) (2) Setting Processor Modes The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address 000416). Do not set the processor mode bits to “102”. Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore, never change the processor mode bits when changing the contents of other bits. Do not change the processor mode bits simultaneously with other bits when changing the processor mode bits “012” or “112”. Change the processor mode bits after changing the other bits. Also do not attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area. • Applying VSS to CNVSS pin The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is selected by writing “012” to the processor mode bits. • Applying VCC to CNVSS pin The microcomputer starts to operate in microprocessor mode after being reset. 1-22 Mitsubishi microcomputers M16C / 62A Group Processor Mode Figure 1.7.1 shows the processor mode register 0 and 1. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.7.2 shows the memory maps applicable for each of the modes. Processor mode register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PM0 Address 000416 When reset 0016 (Note 2) Bit symbol PM00 PM01 PM02 PM03 Bit name Processor mode bit b1 b0 Function 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Do not set 1 1: Microprocessor mode 0 : RD,BHE,WR 1 : RD,WRH,WRL The device is reset when this bit is set to “1”. The value of this bit is “0” when read. b5 b4 RW R/W mode select bit Software reset bit PM04 PM05 Multiplexed bus space select bit 0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to entire space (Note4) PM06 Port P40 to P43 function select bit (Note 3) BCLK output disable bit 0 : Address output 1 : Port function (Address is not output) 0 : BCLK is output 1 : BCLK is not output (Pin is left floating) PM07 Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when reset is 0316. (PM00 and PM01 both are set to “1”.) Note 3: Valid in microprocessor and memory expansion modes. Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8bit width.The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. Processor mode register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 000 0 Symbol PM1 Address 000516 When reset 00000XX02 Bit symbol Reserved bit Nothing is assigned. Bit name Function Must always be set to “0” RW In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. PM13 Internal reserved area expansion bit (Note 2) 0: The internal RAM area is 15 kbytes or less and the internal ROM area is 192 kbytes or less 1: Expands the internal RAM area and internal ROM area to over 15 kbytes and to over 192 kbytes respectively. (Note 2) Reserved bit Must always be set to “0” Reserved bit Must always be set to “0” Reserved bit PM17 Wait bit Must always be set to “0” 0 : No wait state 1 : Wait state inserted Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Note 2: When the reset is revoked, this bit is set to “0”. To expand the internal area, set this bit to “1” in user program. And the top of user program must be allocated to D000016 or subsequent address. Figure 1.7.1. Processor mode register 0 and 1 1-23 Mitsubishi microcomputers M16C / 62A Group Processor Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Single-chip mode 0000016 Memory expansion mode SFR area Internal RAM area Internally reserved area Microprocessor mode SFR area Internal RAM area Internally reserved area SFR area 0040016 Internal RAM area XXXXX16 0400016 Inhibited External area Internally reserved area External area D000016 YYYYY16 Internal ROM area FFFFF16 Internal ROM area RAM size 3K bytes 4K bytes 5K bytes 10K bytes 20K bytes Address XXXXX16 00FFF16 013FF16 017FF16 02BFF16 053FF16 ROM size 32K bytes 64K bytes 96K bytes 128K bytes 256K bytes Address YYYYY16 F800016 F000016 E800016 E000016 C000016 External area : Accessing this area allows the user to access a device connected externally to the microcomputer. Note : These memory maps show an instance in which PM13 is set to 0; but in the case of products in which the internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which PM13 is set to 1. Figure 1.7.2. Memory maps in each processor mode (without memory area expansion, normal mode) Internal Reserved Area Expansion Bit (PM13) This bit expands the internal RAM area and the internal ROM area, and changes the chip select area. In M30624MGA/FGA, for example, to set this bit to “1” expands the internal RAM area and the internal ROM area to 20 Kbytes and 256 Kbytes respectively. Refer to Figure 1.7.3 for the chip select area. When the reset is revoked, this bit is set to “0”. To expand the internal area, set this bit to “1” in user program. And the top of user program must be allocated to D000016 or subsequent address. In the case of the product in which the internal ROM is 192 Kbytes or less and the internal RAM is 15 Kbytes or less, set this bit to “0” when this product is used in the memory expansion mode or the microprocessor mode. When the product is used in the single chip mode, the internal area is not expanded and any action is not affected, even if this bit is set to “1”. 1-24 Mitsubishi microcomputers M16C / 62A Group Processor Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.7.3 shows the memory maps and the chip selection areas effected by PM13 (the internal reserved area expansion bit) in each processor mode for the product having an internal RAM of more than 15K bytes and a ROM of more than 192K bytes. Internal reserved area expansion bit=“0” Memory expansion mode 0000016 0040016 Internal reserved area expansion bit=“1” (Note) Memory expansion mode 0000016 0040016 Microprocessor mode SFR area (1K bytes) Internal RAM area (15K bytes) Microprocessor mode SFR area (1K bytes) SFR area (1K bytes) Internal RAM area (15K bytes) SFR area (1K bytes) Internal RAM area (20K bytes) Internal RAM area (20K bytes) Internal reserved area 0400016 0800016 CS3(16K bytes) CS2 (128K bytes) 0540016 Internal reserved area 0600016 0800016 CS3(8K bytes) CS2 (128K bytes) 2800016 3000016 External area External area CS1(32K bytes) 2800016 3000016 External area External area CS1(32K bytes) CS0 Memory expansion mode : 640K bytes Microprocessor mode : 832K bytes BFFFF16 C000016 Internal ROM area (256K bytes) CS0 Memory expansion mode : 576K bytes Microprocessor mode : 832K bytes CFFFF16 D000016 Internal ROM area (192K bytes) FFFFF16 FFFFF16 After reset After reset, and set the Internal reserved area expansion bit to “1” Note: When the reset is revoked, this bit is set to “0”. Therefore, the top of the user program must be allocated to D000016 or subsequent address. Figure 1.7.3. Memory location and chip select area in each processor mode 1-25 Mitsubishi microcomputers M16C / 62A Group Bus Settings Bus Settings SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus settings. Table 1.8.1 shows the factors used to change the bus settings. Table 1.8.1. Factors for switching bus settings Bus setting Switching external address bus width Switching external data bus width Switching between separate and multiplex bus Switching factor Bit 6 of processor mode register 0 BYTE pin Bits 4 and 5 of processor mode register 0 (1) Selecting external address bus width The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus. (2) Selecting external data bus width The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”. (3) Selecting separate/multiplex bus The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. • Separate bus In this mode, the data and address are input and output separately. The data bus can be set using the BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16 bits and P0 and P1 are both used for the data bus. When the separate bus is used for access, a software wait can be selected. • Multiplex bus In this mode, data and address I/O are time multiplexed. With the BYTE pin = “H”, the 8 bits from D0 to D7 are multiplexed with A0 to A7. With the BYTE pin = “L”, the 8 bits from D0 to D7 are multiplexed with A1 to A8. D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the microcomputer’s even addresses (every 2nd address). To access these external devices, access the even addresses as bytes. The ALE signal latches the address. It is output from P56. Before using the multiplex bus for access, be sure to insert a software wait. If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. 1-26 Mitsubishi microcomputers M16C / 62A Group Bus Settings Table 1.8.2. Pin functions for each processor mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Processor mode Single-chip mode Memory expansion mode/microprocessor modes “01”, “10” “00” (separate bus) Memory expansion mode Multiplexed bus space select bit Either CS1 or CS2 is for multiplexed bus and others are for separate bus “11” (Note 1) multiplexed bus for the entire space 8 bit “H” I/O port Data bus width BYTE pin level P00 to P07 I/O port 8 bits “H” Data bus 16 bits “L” Data bus 8 bits “H” Data bus 16 bits “L” Data bus P10 to P17 P20 P21 to P27 P30 P31 to P37 P40 to P43 Port P40 to P43 function select bit = 1 P40 to P43 Port P40 to P43 function select bit = 0 P44 to P47 P50 to P53 P54 P55 P56 P57 I/O port I/O port I/O port I/O port I/O port I/O port I/O port Data bus I/O port Address bus Address bus Address bus Address bus I/O port Data bus Address bus Address bus Address bus Address bus I/O port I/O port Address bus /data bus Address bus /data bus A8/D7 I/O port I/O port Address bus Address bus /data bus(Note 2) Address bus /data bus(Note 2) Address bus Address bus /data bus(Note 2) Address bus /data bus(Note 2) Address bus I/O port Address bus I/O port I/O port Address bus Address bus Address bus Address bus I/O port I/O port I/O port I/O port I/O port I/O port I/O port CS (chip select) or programmable I/O port (For details, refer to “Bus control”) Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK (For details, refer to “Bus control”) HLDA HOLD ALE RDY HLDA HOLD ALE RDY HLDA HOLD ALE RDY HLDA HOLD ALE RDY HLDA HOLD ALE RDY Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. Note 2: Address bus when in separate bus mode. 1-27 Mitsubishi microcomputers M16C / 62A Group Bus Control Bus Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. The software waits are valid in all processor modes. (1) Address bus/data bus The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space. The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus. When a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed. (2) Chip select signal The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control register (address 000816) set each pin to function as a port or to output the chip select signal. The chip select control register is valid in memory expansion mode and microprocessor mode. In single-chip mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control register. _______ In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can_______ _______ celled. CS1 to CS3 function as input ports. Figure 1.9.1 shows the chip select control register. The chip select signal can be used to split the external area into as many as four blocks. Tables 1.9.1 and 1.9.2 show the external memory areas specified using the chip select signal. Table 1.9.1. External areas specified by the chip select signals (A product having an internal RAM equal to or less than 15K bytes and a ROM equal to or less than 192K bytes)(Note) Processor mode CS0 3000016 to CFFFF16 (640K bytes) 3000016 to FFFFF16 (832K bytes) Chip select signal CS1 CS2 CS3 Memory expansion mode Microprocessor mode 2800016 to 2FFFF16 (32K bytes) 0800016 to 27FFF16 (128K bytes) 0400016 to 07FFF16 (16K bytes) Note :Be sure to set bit 3 (PM13) of processor mode register 1 to “0”. 1-28 Mitsubishi microcomputers M16C / 62A Group Bus Control Table 1.9.2. External areas specified by the chip select signals SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (A product having an internal RAM of more than 15K bytes and a ROM of more than 192K bytes) Processor mode CS0 When PM13=0 3000016 to CFFFF16 (640K bytes) When PM13=1 3000016 to BFFFF16 (576K bytes) 0300016 to FFFFF16 (816K bytes) Chip select signal CS1 CS2 CS3 When PM13=0 0400016 to 07FFF16 (16K bytes) When PM13=1 0600016 to 07FFF16 (8K bytes) Memory expansion mode 2800016 to 2FFFF16 (32K bytes) 0800016 to 27FFF16 (128K bytes) Microprocessor mode Chip select control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CSR Address 000816 When reset 0116 Bit symbol CS0 CS1 CS2 CS3 CS0W CS1W CS2W CS3W Bit name CS0 output enable bit CS1 output enable bit CS2 output enable bit CS3 output enable bit CS0 wait bit CS1 wait bit CS2 wait bit CS3 wait bit Function 0 : Chip select output disabled (Normal port pin) 1 : Chip select output enabled RW 0 : Wait state inserted 1 : No wait state Figure 1.9.1. Chip select control register The timing of the chip select signal changing to “L”(active) is synchronized with the address bus. But the timing of the chip select signal changing to “H” depends on the area which will be accessed in the next cycle. Figure 1.9.2 shows the output example of the address bus and chip select signal. 1-29 Mitsubishi microcomputers M16C / 62A Group Bus Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example 1) After access the external area, both the address signal and the chip select signal change concurrently in the next cycle. In this example, after access to the external area(i), an access to the area indicated by the other chip select signal(j) will occur in the next cycle. In this case, both the address bus and the chip select signal change between the two cycles. Example 2) After access the external area, only the chip select signal changes in the next cycle (the address bus does not change). In this example, an access to the internal ROM or the internal RAM in the next cycle will occur, after access to the external area. In this case, the chip select signal changes between the two cycles, but the address does not change. Access to the Access to the Other External Area( i ) External Area( j ) Access to the External Area Internal ROM/RAM Access BCLK Read/Write signal Data bus Address bus Chip select (CS i) Chip select (CS j) Data Address BCLK Read/Write signal Data bus Address bus Chip select Data Address Example 3) After access the external area, only the address bus changes in the next cycle (the chip select signal does not change). In this example, after access to the external area(i), an access to the area indicated by the same chip select signal(i) will occur in the next cycle. In this case, the address bus changes between the two cycles, but the chip select signal does not change. Example 4) After access the external area, either the address signal and the chip select signal do not change in the next cycle. In this example, any access to any area does not occur in the next cycle (either instruction prefetch does not occur). In this case,either the address bus and chip select signal do not change between the two cycles. Access to the External Area( i ) Access to the Same External Area( i ) Access to the External Area No Access BCLK Read/Write signal Data bus Address bus Chip select (CS i) Data Address BCLK Read/Write signal Data bus Address bus Chip select Data Address Note : These examples show the address bus and chip select signal within the successive two cycles. According to the combination of these examples, the chip select can be elongated to over 2cycles. Figure 1.9.2. Output Examples about Address Bus and Chip Select Signal (Separated Bus without Wait) 1-30 Mitsubishi microcomputers M16C / 62A Group Bus Control (3) Read/write signals SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the _____ ________ ______ _____ ________ _________ combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE _____ ______ _______ pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address 000416) to “0”.) Tables 1.9.3 and 1.9.4 show the operation of these signals. _____ ______ ________ After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected. _____ _________ _________ When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 000416) has been set (Note). Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to “1”. _____ ________ _________ Table 1.9.3. Operation of RD, WRL, and WRH signals Data bus width 16-bit (BYTE = “L”) RD L H H H WRL H L H L WRH H H L L Status of external data bus Read data Write 1 byte of data to even address Write 1 byte of data to odd address Write data to both even and odd addresses _____ ______ ________ Table 1.9.4. Operation of RD, WR, and BHE signals Data bus width RD H L H L H L H L WR L H L H L H L H BHE L L H H L L Not used Not used A0 H H L L L L H/L H/L Status of external data bus Write 1 byte of data to odd address Read 1 byte of data from odd address Write 1 byte of data to even address Read 1 byte of data from even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1 byte of data Read 1 byte of data 16-bit (BYTE = “L”) 8-bit (BYTE = “H”) (4) ALE signal The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls. When BYTE pin = “H” ALE D0/A0 to D7/A7 A8 to A19 Address Data (Note 1) When BYTE pin = “L” ALE A0 D0/A1 to D7/A8 Address (Note 2) A9 to A19 Address Address Address Data (Note 1) Note 1: Floating when reading. Note 2: When multiplexed bus for the entire space is selected, these are I/O ports. Figure 1.9.3. ALE signal and address/data bus 1-31 Mitsubishi microcomputers M16C / 62A Group Bus Control ________ SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (5) The RDY signal ________ RDY is a signal that facilitates access to an external device that requires long access time. As shown in ________ Figure 1.9.4, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If ________ an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.9.5 shows the state of the microcomputer with the bus in the wait state, and Figure 1.9.4 shows an example ____ ________ in which the RD signal is prolonged by the RDY signal. ________ The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the ________ chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to ________ all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as properly as in non-using. Table 1.9.5. Microcomputer status in wait state (Note) Item Oscillation ___ _____ Status On ________ R/W signal, address bus, data bus, CS __________ ALE signal, HLDA, programmable I/O ports Internal peripheral circuits ________ Maintain status when RDY signal received On Note: The RDY signal cannot be received immediately prior to a software wait. In an instance of separate bus BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) Accept timing of RDY signal In an instance of multiplexed bus BCLK RD CSi (i=0 to 3) RDY tsu(RDY - BCLK) : Wait using RDY signal : Wait using software _____ Accept timing of RDY signal ________ Figure 1.9.4. Example of RD signal extended by RDY signal 1-32 Mitsubishi microcomputers M16C / 62A Group Bus Control (6) Hold signal SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to __________ the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status __________ __________ is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.9.6 shows the microcomputer status in the hold state. __________ Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. __________ HOLD > DMAC > CPU Figure 1.9.5. Bus-using priorities Table 1.9.6. Microcomputer status in hold state Item Oscillation ___ _____ _______ Status ON Floating Floating Maintains status when hold signal is received Output “L” ON (but watchdog timer stops) Undefined R/W signal, address bus, data bus, CS, BHE Programmable I/O ports P0, P1, P2, P3, P4, P5 P6, P7, P8, P9, P10 __________ HLDA Internal peripheral circuits ALE signal (7) External bus status when the internal area is accessed Table 1.9.7 shows the external bus status when the internal area is accessed. Table 1.9.7. External bus status when the internal area is accessed Item Address bus SFR accessed Address output Internal ROM/RAM accessed Maintain status before accessed address of external area Data bus When read When write RD, WR, WRL, WRH BHE Floating Output data RD, WR, WRL, WRH output BHE output Floating Undefined Output “H” Maintain status before accessed status of external area CS ALE Output “H” Output “L” Output “H” Output “L” 1-33 Mitsubishi microcomputers M16C / 62A Group Bus Control (8) BCLK output SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note). When set to “1”, the output floating. Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000A16) to “1”. (9) Software wait A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516) (Note) and bits 4 to 7 of the chip select control register (address 000816). A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLK cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric character________ istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register’s bits 4 to 7 must be set to “0”. When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register _______ _______ correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits default to “0” after the microcomputer has been reset. The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also, insert a software wait if using the multiplex bus to access the external memory area. Table 1.9.8 shows the software wait and bus cycles. Figure 1.9.6 shows example of bus timing when using software waits. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A16) to “1”. Table 1.9.8. Software waits and bus cycles Area SFR Internal ROM/RAM Separate bus Separate bus External memory area Separate bus Multiplex bus Multiplex bus Bus status Wait bit Invalid 0 1 0 0 1 0 1 Bits 4 to 7 of chip select control register Invalid Invalid Invalid 1 0 0 (Note) 0 0 (Note) Bus cycle 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles 2 BCLK cycles 3 BCLK cycles 3 BCLK cycles Note: When using the RDY signal, always set to “0”. 1-34 Mitsubishi microcomputers M16C / 62A Group Bus Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER < Separate bus (no wait) > Bus cycle (Note 1) Bus cycle (Note 1) BCLK Write signal Read signal Output Input Data bus Address bus (Note 2) Chip select (Note 2) Address Address < Separate bus (with wait) > Bus cycle (Note 1) Bus cycle (Note 1) BCLK Write signal Read signal Output Input Data bus Address bus (Note 2) Chip select (Note 2) Address Address < Multiplexed bus > Bus cycle (Note 1) Bus cycle (Note 1) BCLK Write signal Read signal ALE Address bus (Note 2) Address bus/ Data bus Chip select (Note 2) Address Address Data output Address Address Input Note 1: These example timing charts indicate bus cycle length. After this bus cycle sometimes come read and write cycles in succession. Note 2: The address bus and chip select may be extended depending on the CPU status such as that of the instruction queue buffer. Figure 1.9.6. Typical bus timings using software wait 1-35 Mitsubishi microcomputers M16C / 62A Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Generating Circuit The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 1.10.1. Main clock and sub-clock generating circuits Use of clock Main clock generating circuit Sub-clock generating circuit • CPU’s operating clock source • CPU’s operating clock source • Internal peripheral units’ • Timer A/B’s count clock operating clock source source Ceramic or crystal oscillator Crystal oscillator XIN, XOUT XCIN, XCOUT Available Available Oscillating Stopped Externally derived clock can be input Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset Other Example of oscillator circuit Figure 1.10.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.10.2 shows some examples of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 1.10.1 and 1.10.2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator. Microcomputer (Built-in feedback resistor) Microcomputer (Built-in feedback resistor) XIN XOUT (Note) Rd XIN XOUT Open Externally derived clock CIN COUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction. Figure 1.10.1. Examples of main clock Microcomputer (Built-in feedback resistor) Microcomputer (Built-in feedback resistor) XCIN XCOUT (Note) RCd XCIN XCOUT Open Externally derived clock CCIN CCOUT Vcc Vss Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN and XCOUT following the instruction. Figure 1.10.2. Examples of sub-clock 1-36 Mitsubishi microcomputers M16C / 62A Group Clock Generating Circuit Clock Control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.10.3 shows the block diagram of the clock generating circuit. XCIN CM04 XCOUT 1/32 fC32 f1 f1SIO2 fC fAD f8 f32 f8SIO2 f32SIO2 Sub clock CM10 “1” Write signal SQ XIN R RESET Software reset NMI Interrupt request level judgment output WAIT instruction Main clock CM02 CM05 XOUT b a c d Divider CM07=0 BCLK fC CM07=1 SQ R b a 1/2 1/2 1/2 1/2 1/2 c CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10 d CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00 CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16 Details of divider Figure 1.10.3. Clock generating circuit 1-37 Mitsubishi microcomputers M16C / 62A Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following paragraphs describes the clocks generated by the clock generating circuit. (1) Main clock The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (2) Sub-clock The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port XC select bit (bit 4 at address 000616), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting to stop mode and at a reset. When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up. (3) BCLK The BCLK is the clock that drives the CPU, and is fC or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expansion and the microprocessor modes. The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD) The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction. (5) fC32 This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts. (6) fC This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer. 1-38 Mitsubishi microcomputers M16C / 62A Group Clock Generating Circuit Figure 1.10.4 shows the system clock control registers 0 and 1. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Bit symbol CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07 Address 000616 Bit name Clock output function select bit (Valid only in single-chip mode) WAIT peripheral function clock stop bit When reset 4816 Function b1 b0 RW 0 0 : I/O port P57 0 1 : fC output 1 0 : f8 output 1 1 : f32 output 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8) XCIN-XCOUT drive capacity 0 : LOW select bit (Note 2) 1 : HIGH Port XC select bit Main clock (XIN-XOUT) stop bit (Note 3, 4, 5) Main clock division select bit 0 (Note 7) System clock select bit (Note 6) 0 : I/O port 1 : XCIN-XCOUT generation (Note 9) 0 : On 1 : Off 0 : CM16 and CM17 valid 1 : Division by 8 mode 0 : XIN, XOUT 1 : XCIN, XCOUT Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: Changes to “1” when shiffing to stop mode and at a reset. Note 3: When entering low power dissipation mode, main clock stops by using this bit. To stop the main clock, when the sub clock oscillation is stable, set system clock select bit (CM07) to “1” before setting this bit to “1”. Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT (“H”) via the feedback resistor. Note 6: Set port XC select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting this bit from “0” to “1”. Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock oscillating before setting this bit from “1” to “0”. Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 8: fC32 is not included. Do not set to “1” when using low-speed or low power dissipation mode. Note 9: When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up. System clock control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 Symbol CM1 Bit symbol CM10 Address 000716 Bit name All clock stop control bit (Note4) When reset 2016 Function 0 : Clock on 1 : All clocks off (stop mode) Must always be set to “0” Must always be set to “0” Must always be set to “0” Must always be set to “0” 0 : LOW 1 : HIGH b7 b6 RW Reserved bit Reserved bit Reserved bit Reserved bit CM15 CM16 CM17 XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3) 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8. Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn highimpedance state. Figure 1.10.4. Clock control registers 0 and 1 1-39 Mitsubishi microcomputers M16C / 62A Group Clock Generating Circuit SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock Output In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed. Stop Mode Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2), SI/O3,4 functions provided an external clock is selected. Table 1.10.2 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only a _______ hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to 0, then shift to stop mode. When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Table 1.10.2. Port status during stop mode Pin _______ _______ Memory expansion mode Microprocessor mode Retains status before stop mode Single-chip mode Address bus, data bus, CS0 to CS3, ________ BHE _____ ______ ________ _________ RD, WR, WRL, WRH __________ “H” “H” “H” Retains status before stop mode Retains status before stop mode Valid only in single-chip mode “H” Valid only in single-chip mode Retains status before stop mode HLDA, BCLK ALE Port CLKOUT When fc selected When f8, f32 selected 1-40 Mitsubishi microcomputers M16C / 62A Group Wait Mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Wait Mode When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32 does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. Table 1.10.3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must have been changed to 0. If returning by an interrupt, the clock in which the WAIT instruction executed is set to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hardware _______ reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupt to 0,then shift to wait mode. Table 1.10.3. Port status during wait mode Pin _______ _______ Memory expansion mode Microprocessor mode Retains status before wait mode Single-chip mode Address bus, data bus, CS0 to CS3, ________ BHE _____ ______ ________ _________ RD, WR, WRL, WRH __________ “H” HLDA,BCLK ALE Port CLKOUT “H” “H” Retains status before wait mode When fC selected Valid only in single-chip mode When f8, f32 selected Valid only in single-chip mode Retains status before wait mode Does not stop Does not stop when the WAIT peripheral function clock stop bit is “0”. When the WAIT peripheral function clock stop bit is “1”, the status immediately prior to entering wait mode is maintained. 1-41 Mitsubishi microcomputers M16C / 62A Group Status Transition of BCLK SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Transition of BCLK Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.10.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK. (1) Division by 2 mode The main clock is divided by 2 to obtain the BCLK. (2) Division by 4 mode The main clock is divided by 4 to obtain the BCLK. (3) Division by 8 mode The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) Division by 16 mode The main clock is divided by 16 to obtain the BCLK. (5) No-division mode The main clock is divided by 1 to obtain the BCLK. (6) Low-speed mode fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) Low power dissipation mode fC is the BCLK and the main clock is stopped. Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock. Table 1.10.4. Operating modes dictated by settings of system clock control registers 0 and 1 CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK 0 1 Invalid 1 0 Invalid Invalid 1 0 Invalid 1 0 Invalid Invalid 0 0 0 0 0 1 1 0 0 1 0 0 Invalid Invalid 0 0 0 0 0 0 1 Invalid Invalid Invalid Invalid Invalid 1 1 Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode Low-speed mode Low power dissipation mode 1-42 Mitsubishi microcomputers M16C / 62A Group Power control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Power control The following is a description of the three available power control modes: Modes Power control is available in three modes. (a) Normal operation mode • High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its assigned clock. • Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its assigned clock. • Low-speed mode fC becomes the BCLK. The CPU operates according to the fC clock. The fC clock is supplied by the subclock. Each peripheral function operates according to its assigned clock. • Low power dissipation mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fC clock is supplied by the subclock. The only peripheral functions that operate are those with the subclock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 1.10.5 is the state transition diagram of the above modes. 1-43 Mitsubishi microcomputers M16C / 62A Group Power control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Transition of stop mode, wait mode Reset All oscillators stopped WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction Interrupt CPU operation stopped Stop mode All oscillators stopped CM10 = “1” Interrupt Interrupt CM10 = “1” Medium-speed mode (divided-by-8 mode) Wait mode CPU operation stopped Stop mode All oscillators stopped High-speed/mediumspeed mode Wait mode CPU operation stopped Stop mode CM10 = “1” Interrupt Low-speed/low power dissipation mode Wait mode Normal mode (Refer to the following for the transition of normal mode.) Transition of normal mode Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode) CM06 = “1” BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” CM04 = “1” (Notes 1, 3) Main clock is oscillating CM04 = “0” Sub clock is oscillating CM07 = “0” (Note 1) CM06 = “1” CM04 = “0” High-speed mode BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1” Medium-speed mode (divided-by-8 mode) BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” Main clock is oscillating Sub clock is oscillating Low-speed mode CM07 = “0” (Note 1, 3) BCLK : f(XCIN) CM07 = “1” CM07 = “1” (Note 2) Medium-speed mode (divided-by-4 mode) BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0” Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1” CM05 = “0” CM04 = “0” CM05 = “1” Main clock is oscillating Sub clock is stopped CM04 = “1” High-speed mode BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” CM06 = “0” (Notes 1,3) Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1” Main clock is stopped Sub clock is oscillating Low power dissipation mode CM07 = “1” (Note 2) CM05 = “1” BCLK : f(XCIN) CM07 = “1” Medium-speed mode (divided-by-4 mode) BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0” Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1” CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1” Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. Figure 1.10.5. State transition diagram of Power control mode 1-44 Mitsubishi microcomputers M16C / 62A Group Protection SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Protection The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.10.6 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716), port P9 direction register (address 03F316) , SI/O3 control register (address 036216) and SI/O4 control register (address 036616) can only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to port P9. If, after “1” (write-enabled) has been written to the port P9 direction register and SI/Oi control register (i=3,4) write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”. Protect register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Bit symbol PRC0 Address 000A16 Bit name When reset XXXXX0002 Function RW Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516) Enables writing to port P9 direction register (address 03F316) and SI/Oi control register (i=3,4) (addresses 036216 and 036616) (Note) 0 : Write-inhibited 1 : Write-enabled PRC1 PRC2 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Writing a value to an address after “1” is written to this bit returns the bit to “0” . Other bits do not automatically return to “0” and they must therefore be reset by the program. Figure 1.10.6. Protect register 1-45 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of Interrupt Type of Interrupts Figure 1.11.1 lists the types of interrupts. Software Interrupt Special Hardware Peripheral I/O (Note) Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Figure 1.11.1. Classification of interrupts • Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. • Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level. 1-46                  Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset NMI ________ DBC Watchdog timer Single step Address matched _______          Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. • Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. • Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB • BRK interrupt A BRK interrupt occurs when executing the BRK instruction. • INT interrupt An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/ O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift. 1-47 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. • Reset ____________ Reset occurs if an “L” is input to the RESET pin. _______ • NMI interrupt _______ _______ An NMI interrupt occurs if an “L” is input to the NMI pin. ________ • DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. • Watchdog timer interrupt Generated by the watchdog timer. • Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed. • Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. • Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates. • DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates. • Key-input interrupt ___ A key-input interrupt occurs if an “L” is input to the KI pin. • A-D conversion interrupt This is an interrupt that the A-D converter generates. • UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt These are interrupts that the serial I/O transmission generates. • UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt These are interrupts that the serial I/O reception generates. • Timer A0 interrupt through timer A4 interrupt These are interrupts that timer A generates • Timer B0 interrupt through timer B5 interrupt These are interrupts that timer B generates. ________ ________ • INT0 interrupt through INT5 interrupt ______ ______ An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin. 1-48 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupts and Interrupt Vector Tables If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.11.2 shows the format for specifying the address. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. MSB LSB Low address Mid address 0000 0000 High address 0000 Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3 Figure 1.11.2. Format for specifying interrupt vector addresses • Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.11.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 1.11.1. Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instruction Overflow BRK instruction Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use Address match FFFE816 to FFFEB16 Single step (Note) FFFEC16 to FFFEF16 Watchdog timer FFFF016 to FFFF316 ________ DBC (Note) FFFF416 to FFFF716 Do not use _______ _______ NMI FFFF816 to FFFFB16 External interrupt by input to NMI pin Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only. 1-49 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Variable vector tables The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.11.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Table 1.11.2. Interrupts assigned to the variable vector tables and addresses of vector tables Software interrupt number Software interrupt number 0 Vector table address Address (L) to address (H) Interrupt source BRK instruction Remarks Cannot be masked I flag +0 to +3 (Note 1) Software interrupt number 4 Software interrupt number 5 Software interrupt number 6 Software interrupt number 7 Software interrupt number 8 Software interrupt number 9 Software interrupt number 10 Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14 Software interrupt number 15 Software interrupt number 16 Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 to Software interrupt number 63 +16 to +19 (Note 1) +20 to +23 (Note 1) +24 to +27 (Note 1) +28 to +31 (Note 1) +32 to +35 (Note 1) +36 to +39 (Note 1) +40 to +43 (Note 1) +44 to +47 (Note 1) +48 to +51 (Note 1) +52 to +55 (Note 1) +56 to +59 (Note 1) +60 to +63 (Note 1) +64 to +67 (Note 1) +68 to +71 (Note 1) +72 to +75 (Note 1) +76 to +79 (Note 1) +80 to +83 (Note 1) +84 to +87 (Note 1) +88 to +91 (Note 1) +92 to +95 (Note 1) +96 to +99 (Note 1) +100 to +103 (Note 1) +104 to +107 (Note 1) +108 to +111 (Note 1) +112 to +115 (Note 1) +116 to +119 (Note 1) +120 to +123 (Note 1) +124 to +127 (Note 1) +128 to +131 (Note 1) to +252 to +255 (Note 1) INT3 Timer B5 Timer B4 Timer B3 SI/O4/INT5 SI/O3/INT4 (Note 2) (Note 2) Bus collision detection DMA0 DMA1 Key input interrupt A-D UART2 transmit/NACK (Note 3) UART2 receive/ACK (Note 3) UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer B0 Timer B1 Timer B2 INT0 INT1 INT2 Software interrupt Cannot be masked I flag Note 1: Address relative to address in interrupt table register (INTB). Note 2: It is selected by interrupt request cause bit (bit 6, 7 in address 035F16 ). Note 3: When IIC mode is selected, NACK and ACK interrupts are selected. 1-50 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 1.11.3 shows the memory map of the interrupt control registers. 1-51 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt control register (Note 2) Symbol TBiIC(i=3 to 5) BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 2) Address 004516 to 004716 004A16 004B16, 004C16 004D16 004E16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005916 005A16 to 005C16 When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 R W ILVL1 ILVL2 IR Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested (Note 1) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address INTiIC(i=3) 004416 SiIC/INTjIC (i=4, 3) 004816, 004916 (j=5, 4) 004816, 004916 INTiIC(i=0 to 2) 005D16 to 005F16 When reset XX00X0002 XX00X0002 XX00X0002 XX00X0002 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Must always be set to “0” R W ILVL1 ILVL2 IR Interrupt request bit (Note 1) POL Polarity select bit Reserved bit Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. Figure 1.11.3. Interrupt control registers 1-52 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. Interrupt Request Bit The interrupt request bit is set to “1” by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to “0” by hardware. The interrupt request bit can also be set to “0” by software. (Do not set this bit to “1”). Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt levels enabled, according to the contents of the IPL. The following are conditions under which an interrupt is accepted: · interrupt enable flag (I flag) = “1” · interrupt request bit = “1” · interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 1.11.3. Settings of interrupt priority levels Interrupt priority level select bit b2 b1 b0 Table 1.11.4. Interrupt levels enabled according to the contents of the IPL IPL IPL2 IPL1 IPL0 Interrupt priority level Priority order Enabled interrupt priority levels 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Low 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled 1-53 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rewrite the interrupt control register To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET 1-54 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. After this, the corresponding interrupt request bit becomes “0”. (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user. Interrupt Response Time 'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.11.4 shows the interrupt response time. Interrupt request generated Interrupt request acknowledged Time Instruction (a) Interrupt sequence (b) Instruction in interrupt routine Interrupt response time (a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed. Figure 1.11.4. Interrupt response time 1-55 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.11.5. Table 1.11.5. Time required for executing the interrupt sequence Interrupt vector address Even Even Odd (Note 2) Odd (Note 2) Stack pointer (SP) value Even Odd Even Odd ________ 16-Bit bus, without wait 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1) 8-Bit bus, without wait 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 BCLK Address bus Data bus R W The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Address 0000 Interrupt information Indeterminate Indeterminate Indeterminate SP-2 SP-2 contents SP-4 SP-4 contents vec vec contents vec+2 vec+2 contents PC Figure 1.11.5. Time required for executing the interrupt sequence Variation of IPL when Interrupt Request is Accepted If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.11.6 is set in the IPL. Table 1.11.6. Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels _______ Value set in the IPL 7 0 Not changed Watchdog timer, NMI Reset Other 1-56 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Saving Registers In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 1.11.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP). Address MSB Stack area LSB Address MSB Stack area LSB [SP] New stack pointer value m–4 m–3 m–2 m–1 m m+1 Content of previous stack Content of previous stack [SP] Stack pointer value before interrupt occurs m–4 m–3 m–2 m–1 m m+1 Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) Content of previous stack Content of previous stack Stack status before interrupt request is acknowledged Stack status after interrupt request is acknowledged Figure 1.11.6. State of stack before and after acceptance of interrupt request 1-57 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer (Note) , at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.11.7 shows the operation of the saving registers. Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP). (1) Stack pointer (SP) contains even number Address Stack area Sequence in which order registers are saved [SP] – 5 (Odd) [SP] – 4 (Even) [SP] – 3(Odd) [SP] – 2 (Even) [SP] – 1(Odd) [SP] (Even) Finished saving registers in two operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) (1) Saved simultaneously, all 16 bits (2) Saved simultaneously, all 16 bits (2) Stack pointer (SP) contains odd number Address Stack area Sequence in which order registers are saved [SP] – 5 (Even) [SP] – 4(Odd) [SP] – 3 (Even) [SP] – 2(Odd) [SP] – 1 (Even) [SP] (Odd) Finished saving registers in four operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) (3) (4) (1) (2) Saved simultaneously, all 8 bits Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. Figure 1.11.7. Operation of saving registers 1-58 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Returning from an Interrupt Routine Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction. Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 1.11.8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine. _______ ________ Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match Figure 1.11.8. Hardware interrupts priorities Interrupt resolution circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure 1.11.9 shows the circuit that judges the interrupt priority level. 1-59 Mitsubishi microcomputers M16C / 62A Group Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 Level 0 (initial value) High Timer B4 INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 Timer B3 Timer B5 UART1 reception UART0 reception UART2 reception/ACK A-D conversion DMA1 Bus collision detection Priority of peripheral I/O interrupts (if priority levels are same) Serial I/O4/INT5 Timer A0 UART1 transmission UART0 transmission UART2 transmission/NACK Key input interrupt DMA0 Serial I/O3/INT4 Processor interrupt priority level (IPL) Low Interrupt request level judgment output to clock generating circuit (Fig.1.10.3) Interrupt enable flag (I flag) Address match Watchdog timer Interrupt request accepted DBC NMI Reset Figure 1.11.9. Maskable interrupts priorities (peripheral I/O interrupts) 1-60 Mitsubishi microcomputers ______ M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER INT Interrupt ______ INT Interrupt ________ ________ INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. ________ Of interrupt control registers, 004816 is used both as serial I/O4 and external interrupt INT5 input control ________ register, and 004916 is used both as serial I/O3 and as external interrupt INT4 input control register. Use the interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register (035F16) - to specify which interrupt request cause to select. After having set an interrupt request cause, be sure to clear the corresponding interrupt request bit before enabling an interrupt. Either of the interrupt control registers - 004816, 004916 - has the polarity-switching bit. Be sure to set this bit to “0” to select an serial I/O as the interrupt request cause. As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting “1” in the INTi interrupt polarity switching bit of the interrupt request cause select register (035F16). To select both edges, set the polarity switching bit of the corresponding interrupt control register to ‘falling edge’ (“0”). Figure 1.11.10 shows the Interrupt request cause select register. Interrupt request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Bit symbol Address 035F16 When reset 0016 Bit name INT0 interrupt polarity switching bit INT1 interrupt polarity switching bit INT2 interrupt polarity switching bit INT3 interrupt polarity switching bit INT4 interrupt polarity switching bit INT5 interrupt polarity switching bit Interrupt request cause select bit Interrupt request cause select bit Function 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : SIO3 1 : INT4 0 : SIO4 1 : INT5 RW IFSR0 IFSR1 IFSR2 IFSR3 IFSR4 IFSR5 IFSR6 IFSR7 Figure 1.11.10. Interrupt request cause select register 1-61 Mitsubishi microcomputers ________ M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER NMI Interrupt ______ NMI Interrupt ______ ______ ______ An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address 03F016). This pin cannot be used as a normal port input. Key Input Interrupt If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to P107 as A-D input ports. Figure 1.11.11 shows the block diagram of the key input interrupt. Note that if an “L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. Port P104-P107 pull-up select bit Pull-up transistor Key input interrupt control register Port P107 direction register Port P107 direction register (address 004D16) P107/KI3 Pull-up transistor Port P106 direction register Interrupt control circuit P106/KI2 Pull-up transistor Key input interrupt request Port P105 direction register P105/KI1 Pull-up transistor Port P104 direction register P104/KI0 Figure 1.11.11. Block diagram of key input interrupt 1-62 Mitsubishi microcomputers M16C / 62A Group Address Match Interrupt SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address Match Interrupt An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the value of the program counter (PC) that is saved to the stack area varies depending on the instruction being executed. Note that when using the external data bus in width of 8 bits, the address match interrupt cannot be used for external area. Figure 1.11.12 shows the address match interrupt-related registers. Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit symbol Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW AIER0 AIER1 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. Address match interrupt register i (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Address 001216 to 001016 001616 to 001416 When reset X0000016 X0000016 Function Address setting register for address match interrupt Values that can be set R W 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. Figure 1.11.12. Address match interrupt-related registers 1-63 Mitsubishi microcomputers M16C / 62A Group Precautions for Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions for Interrupts (1) Reading address 0000016 • When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Even if the address 0000016 is read out by software, “0” is set to the enabled highest priority interrupt source request bit. Therefore interrupt can be canceled and unexpected interrupt can occur. Do not read address 0000016 by software. (2) Setting the stack pointer • The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in _______ the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Concerning the first instruction immediately after reset, generat_______ ing any interrupts including the NMI interrupt is prohibited. _______ (3) The NMI interrupt _______ _______ •The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if unused. Be sure to work on it. _______ • The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time _______ when the NMI interrupt is input. _______ • Do not reset the CPU with the input to the NMI pin being in the “L” state. _______ • Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to _______ the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned down. _______ • Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to _______ the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt. _______ • Signals input to the NMI pin require an “L” level of 1 clock or more, from the operation clock of the CPU. (4) External interrupt ________ • Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0 ________ through INT5 regardless of the CPU operation clock. ________ ________ • When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to “1”. After changing the polarity, set the interrupt request bit to “0”. Figure 1.11.13 shows the procedure for ______ changing the INT interrupt generate factor. 1-64 Mitsubishi microcomputers M16C / 62A Group Precautions for Interrupts SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clear the interrupt enable flag to “0” (Disable interrupt) Set the interrupt priority level to level 0 (Disable INTi interrupt) Set the polarity select bit Clear the interrupt request bit to “0” Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request) Set the interrupt enable flag to “1” (Enable interrupt) Note: Execute the setting above individually. Don't execute two or more settings at once(by one instruction). ______ Figure 1.11.13. Switching condition of INT interrupt request (5) Rewrite the interrupt control register • To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow: Example 1: INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts. Example 2: INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts. Example 3: INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts. The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue. • When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET 1-65 Mitsubishi microcomputers M16C / 62A Group Watchdog Timer Watchdog Timer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The watchdog timer has the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the prescaler. With XIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (16 or 128) X watchdog timer count (32768) BCLK With XCIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (2) X watchdog timer count (32768) BCLK For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the prescaler, then the watchdog timer's period becomes approximately 32.8 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Figure 1.12.1 shows the block diagram of the watchdog timer. Figure 1.12.2 shows the watchdog timerrelated registers. Prescaler “CM07 = 0” “WDC7 = 0” 1/16 BCLK HOLD 1/128 “CM07 = 0” “WDC7 = 1” Watchdog timer Watchdog timer interrupt request “CM07 = 1” 1/2 Write to the watchdog timer start register (address 000E16) Set to “7FFF16” RESET Figure 1.12.1. Block diagram of watchdog timer 1-66 Mitsubishi microcomputers M16C / 62A Group Watchdog Timer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol WDC Bit symbol Address 000F16 Bit name When reset 000XXXXX2 Function RW High-order bit of watchdog timer Reserved bit Reserved bit WDC7 Must always be set to “0” Must always be set to “0” Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register b7 b0 Symbol WDTS Address 000E16 When reset Indeterminate RW Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written. Figure 1.12.2. Watchdog timer control and start registers 1-67 Mitsubishi microcomputers M16C / 62A Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAC This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.13.1 shows the block diagram of the DMAC. Table 1.13.1 shows the DMAC specifications. Figures 1.13.2 to 1.13.4 show the registers used by the DMAC. Address bus DMA0 source pointer SAR0(20) (addresses 002216 to 002016) DMA0 destination pointer DAR0 (20) (addresses 002616 to 002416) DMA0 forward address pointer (20) (Note) DMA0 transfer counter reload register TCR0 (16) DMA1 source pointer SAR1 (20) (addresses 003216 to 003016) DMA1 destination pointer DAR1 (20) (addresses 003616 to 003416) (addresses 002916, 002816) DMA0 transfer counter TCR0 (16) DMA1 transfer counter reload register TCR1 (16) DMA1 forward address pointer (20) (Note) (addresses 003916, 003816) DMA1 transfer counter TCR1 (16) DMA latch high-order bits DMA latch low-order bits Data bus low-order bits Data bus high-order bits Note: Pointer is incremented by a DMA request. Figure 1.13.1. Block diagram of DMAC Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts either. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit. 1-68 Mitsubishi microcomputers M16C / 62A Group DMAC Table 1.13.1. DMAC specifications Item No. of channels Transfer memory space SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Specification 2 (cycle steal method) • From any address in the 1M bytes space to a fixed address • From a fixed address to any address in the 1M bytes space • From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers) ________ ________ Maximum No. of bytes transferred DMA request factors (Note) Falling edge of INT0 or INT1 or both edge Timer A0 to timer A4 interrupt requests Timer B0 to timer B5 interrupt requests UART0 transfer and reception interrupt requests UART1 transfer and reception interrupt requests UART2 transfer and reception interrupt requests Serial I/O3, 4 interrpt requests A-D conversion interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode • Single transfer mode After the transfer counter underflows, the DMA enable bit turns to “0”, and the DMAC turns inactive • Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a “0” is written to the DMA enable bit. DMA interrupt request generation timing When an underflow occurs in the transfer counter Active When the DMA enable bit is set to “1”, the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive • When the DMA enable bit is set to “0”, the DMAC is inactive. • After the transfer counter underflows in single transfer mode Reload timing for forward ad- At the time of starting data transfer immediately after turning the DMAC active, the value of one of source pointer and destination pointer - the one specified for the dress pointer and transfer forward direction - is reloaded to the forward direction address pointer, and the value counter of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is “0”. Reading the register Can be read at any time. However, when the DMA enable bit is “1”, reading the register set up as the forward register is the same as reading the value of the forward address pointer. Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. 1-69 Mitsubishi microcomputers M16C / 62A Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA0 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL Address 03B816 When reset 0016 Bit symbol Bit name DMA request cause select bit b3 b2 b1 b0 Function 0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0) /two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0) Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0) Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit R W DSEL0 DSEL1 DSEL2 DSEL3 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMS DSR DMA request cause expansion select bit Software DMA request bit 0 : Normal 1 : Expanded cause If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) Figure 1.13.2. DMAC register (1) 1-70 Mitsubishi microcomputers M16C / 62A Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA1 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM1SL Address 03BA16 When reset 0016 Bit symbol Bit name DMA request cause select bit b3 b2 b1 b0 Function 0 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3(DMS=0) /serial I/O3 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0) /serial I/O4 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 receive R W DSEL0 DSEL1 DSEL2 DSEL3 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMS DSR DMA request cause expansion select bit Software DMA request bit 0 : Normal 1 : Expanded cause If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) DMAi control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMiCON(i=0,1) Address 002C16, 003C16 When reset 00000X002 Bit symbol DMBIT DMASL DMAS DMAE DSD DAD Bit name Transfer unit bit select bit Repeat transfer mode select bit DMA request bit (Note 1) DMA enable bit Source address direction select bit (Note 3) 0 : 16 bits 1 : 8 bits Function R W 0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward (Note 2) Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to “0”. Note 3: Source address direction select bit and destination address direction select bit cannot be set to “1” simultaneously. Figure 1.13.3. DMAC register (2) 1-71 Mitsubishi microcomputers M16C / 62A Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAi source pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 002216 to 002016 003216 to 003016 When reset Indeterminate Indeterminate Function • Source pointer Stores the source address Transfer address specification 0000016 to FFFFF16 RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMAi destination pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol DAR0 DAR1 Address 002616 to 002416 003616 to 003416 When reset Indeterminate Indeterminate RW Function • Destination pointer Stores the destination address Transfer address specification 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMAi transfer counter (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol TCR0 TCR1 Address 002916, 002816 003916, 003816 When reset Indeterminate Indeterminate RW Function • Transfer counter Set a value one less than the transfer count Transfer count specification 000016 to FFFF16 Figure 1.13.4. DMAC register (3) 1-72 Mitsubishi microcomputers M16C / 62A Group DMAC (1) Transfer cycle SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of BYTE pin level When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are required for reading the data and two are required for writing the data. Also, in contrast to when the CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin. (c) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 1.13.5 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 1.13.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle. 1-73 Mitsubishi microcomputers M16C / 62A Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) 8-bit transfers 16-bit transfers and the source address is even. BCLK Address bus RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use (2) 16-bit transfers and the source address is odd Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination cycles). BCLK Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use (3) One wait is inserted into the source read under the conditions in (1) BCLK Address bus RD signal WR signal Data bus CPU use Source Destination Dummy cycle CPU use CPU use Source Destination Dummy cycle CPU use (4) One wait is inserted into the source read under the conditions in (2) (When 16-bit data is transferred on an 8-bit data bus, there are two destination cycles). BCLK Address bus RD signal WR signal Data bus CPU use Source Source + 1 Destination Dummy cycle CPU use CPU use Source Source + 1 Destination Dummy cycle CPU use Note: The same timing changes occur with the respective conditions at the destination as at the source. Figure 1.13.5. Example of the transfer cycles for a source read 1-74 Mitsubishi microcomputers M16C / 62A Group DMAC (2) DMAC transfer cycles SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Any combination of even or odd transfer read and write addresses is possible. Table 1.13.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 1.13.2. No. of DMAC transfer cycles Transfer unit Memory expansion mode Bus width Access address Microprocessor mode No. of read No. of write No. of read No. of write cycles cycles cycles cycles 16-bit Even 1 1 1 1 (BYTE= “L”) Odd 1 1 1 1 8-bit Even — — 1 1 (BYTE = “H”) Odd — — 1 1 16-bit Even 1 1 1 1 (BYTE = “L”) Odd 2 2 2 2 8-bit Even — — 2 2 (BYTE = “H”) Odd — — 2 2 Single-chip mode 8-bit transfers (DMBIT= “1”) 16-bit transfers (DMBIT= “0”) Coefficient j, k Internal memory Internal ROM/RAM Internal ROM/RAM No wait With wait 1 2 SFR area 2 External memory Separate bus Separate bus No wait With wait 1 2 Multiplex bus 3 1-75 Mitsubishi microcomputers M16C / 62A Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA enable bit Setting the DMA enable bit to “1” makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting “1” to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant “1” is overwritten to the DMA enable bit. DMA request bit The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request factors for each channel. DMA request factors include the following. * Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals. For the selection of DMA request factors, see the descriptions of the DMAi factor selection register. The DMA request bit turns to “1” if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set to “1” or “0”). It turns to “0” immediately before data transfer starts. In addition, it can be set to “0” by use of a program, but cannot be set to “1”. There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to “1”. So be sure to set the DMA request bit to “0” after the DMA request factor selection bit is changed. The DMA request bit turns to “1” if a DMA transfer request signal occurs, and turns to “0” immediately before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be “0” in most cases. To examine whether the DMAC is active, read the DMA enable bit. Here follows the timing of changes in the DMA request bit. (1) Internal factors Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to “1” due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to “1” due to several factors. Turning the DMA request bit to “0” due to an internal factor is timed to be effected immediately before the transfer starts. (2) External factors _______ An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on which DMAC channel is used). _______ Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to “1” when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes _______ with the trailing edge of the input signal to each INTi pin, for example). With an external factor selected, the DMA request bit is timed to turn to “0” immediately before data transfer starts similarly to the state in which an internal factor is selected. 1-76 Mitsubishi microcomputers M16C / 62A Group DMAC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) The priorities of channels and DMA transfer timing If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently turn to “1”. If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer request signals due to external factors concurrently occur. Figure 1.13.6 An example of DMA transfer effected by external factors. An example in which DMA transmission is carried out in minimum cycles at the time when DMA transmission request signals due to external factors concurrently occur. BCLK DMA0 DMA1 CPU Obtainment of the bus right INT0 DMA0 request bit INT1 DMA1 request bit Figure 1.13.6. An example of DMA transfer effected by external factors 1-77 Mitsubishi microcomputers M16C / 62A Group Timer Timer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B (six). All these timers function independently. Figures 1.14.1 and 1.14.2 show the block diagram of timers. Clock prescaler XIN 1/8 1/4 f1 f8 f32 fC32 f1 f8 f32 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” 1/32 Reset fC32 • Timer mode • One-shot timer mode • PWM mode Timer A0 interrupt TA0IN Noise filter Timer A0 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A1 interrupt TA1IN Noise filter Timer A1 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A2 interrupt TA2IN Noise filter Timer A2 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A3 interrupt TA3IN Noise filter Timer A3 • Event counter mode • Timer mode • One-shot timer mode • PWM mode Timer A4 interrupt TA4IN Noise filter Timer A4 • Event counter mode Timer B2 overflow Note 1: The TA0IN pin (P71) is shared with RxD2 and the TB5IN pin, so be careful. Figure 1.14.1. Timer A block diagram 1-78 Mitsubishi microcomputers M16C / 62A Group Timer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock prescaler XIN f1 XCIN Clock prescaler reset flag (bit 7 at address 038116) set to “1” 1/32 Reset fC32 1/8 1/4 f8 f32 f1 f8 f32 fC32 Timer A • Timer mode • Pulse width measuring mode TB0IN Noise filter Timer B0 interrupt Timer B0 • Event counter mode • Timer mode • Pulse width measuring mode TB1IN Noise filter Timer B1 interrupt Timer B1 • Event counter mode • Timer mode • Pulse width measuring mode Timer B2 interrupt TB2IN Noise filter Timer B2 • Event counter mode • Timer mode • Pulse width measuring mode Timer B3 interrupt TB3IN Noise filter Timer B3 • Event counter mode • Timer mode • Pulse width measuring mode Timer B4 interrupt TB4IN Noise filter Timer B4 • Event counter mode • Timer mode • Pulse width measuring mode Timer B5 interrupt TB5IN Noise filter Timer B5 • Event counter mode Note 1: The TB5IN pin (P71) is shared with RxD2 and the TA0IN pin, so be careful. Figure 1.14.2. Timer B block diagram 1-79 Mitsubishi microcomputers M16C / 62A Group Timer A Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.14.3 shows the block diagram of timer A. Figures 1.14.4 to 1.14.6 show the timer A-related registers. Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts pulses from an external source or a timer over flow. • One-shot timer mode: The timer stops counting when the count reaches “000016”. • Pulse width modulation (PWM) mode: The timer outputs pulses of a given width. Data bus high-order bits Clock source selection f1 f8 f32 fC32 Polarity selection TAiIN (i = 0 to 4) • Timer • One shot • PWM • Timer (gate function) • Event counter Data bus low-order bits Low-order 8 bits Reload register (16) High-order 8 bits Counter (16) Clock selection Up count/down count Always down count except in event counter mode TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F16 038E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 Count start flag (Address 038016) Down count External trigger TB2 overflow TAj overflow (j = i – 1. Note, however, that j = 4 when i = 0) Up/down flag (Address 038416) TAk overflow (k = i + 1. Note, however, that k = 0 when i = 4) TAiOUT (i = 0 to 4) Pulse output Toggle flip-flop Figure 1.14.3. Block diagram of timer A Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TAiMR(i=0 to 4) Address When reset 039616 to 039A16 0016 Bit symbol TMOD0 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode RW TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Function varies with each operation mode Count source select bit (Function varies with each operation mode) Figure 1.14.4. Timer A-related registers (1) 1-80 Mitsubishi microcomputers M16C / 62A Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Ai register (Note 1) (b15) b7 (b8) b0 b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Function Address 038716,038616 038916,038816 038B16,038A16 038D16,038C16 038F16,038E16 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set RW • Timer mode Counts an internal count source 000016 to FFFF16 • Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow • One-shot timer mode Counts a one shot width • Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator • Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 000016 to FFFF16 (Note 2,4) 000016 to FFFE16 (Note 3,4) 0016 to FE16 (High-order address) (Low-order address) 0016 to FF16 (Note 3,4) Note 1: Read and write data in 16-bit units. Note 2: When the timer Ai register is set to “000016”, the counter does not operate and the timer Ai interrupt request is not generated. When the pulse is set to output, the pulse does not output from the TAiOUT pin. Note 3: When the timer Ai register is set to “000016”, the pulse width modulator does not operate and the output level of the TAiOUT pin remains “L” level, therefore the timer Ai interrupt request is not generated. This also occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer Ai register are set to “0016”. Note 4: Use MOV instruction to write to this register. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Function 0 : Stops counting 1 : Starts counting RW Up/down flag (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Address 038416 When reset 0016 Bit symbol TA0UD TA1UD TA2UD TA3UD TA4UD Bit name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause RW TA2P TA3P TA4P Timer A2 two-phase pulse 0 : two-phase pulse signal processing disabled signal processing select bit 1 : two-phase pulse signal processing enabled (Note 2) Timer A3 two-phase pulse signal processing select bit When not using the two-phase Timer A4 two-phase pulse pulse signal processing function, signal processing select bit set the select bit to “0” Note 1: Use MOV instruction to write to this register. Note 2: Set the TAiIN and TAiOUT pins correspondent port direction registers to “0”. Figure 1.14.5. Timer A-related registers (2) 1-81 Mitsubishi microcomputers M16C / 62A Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER One-shot start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol ONSF Address 038216 When reset 00X000002 Bit symbol TA0OS TA1OS TA2OS TA3OS TA4OS Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag Function 1 : Timer start When read, the value is “0” RW Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TA0TGL TA0TGH Timer A0 event/trigger select bit b7 b6 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Note: Set the corresponding port direction register to “0”. Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Address 038316 When reset 0016 Bit symbol TA1TGL Bit name Timer A1 event/trigger select bit Function b1 b0 RW TA1TGH TA2TGL 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 Timer A2 event/trigger select bit TA2TGH TA3TGL TA3TGH 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 TA4TGL TA4TGH Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note: Set the corresponding port direction register to “0”. Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 When reset 0XXXXXXX2 Bit symbol Bit name Function RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Figure 1.14.6. Timer A-related registers (3) 1-82 Mitsubishi microcomputers M16C / 62A Group Timer A (1) Timer mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an internally generated count source. (See Table 1.14.1.) Figure 1.14.7 shows the timer Ai mode register in timer mode. Table 1.14.1. Specifications of timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Specification f1, f8, f32, fC32 • Down count • When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) When the timer underflows Programmable I/O port or gate input Programmable I/O port or pulse output Count value can be read out by reading timer Ai register • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) • Gate function Counting can be started and stopped by the TAiIN pin’s input signal • Pulse output function Each time the timer underflows, the TAiOUT pin’s polarity is reversed Select function Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 Address When reset 039616 to 039A16 0016 Bit name Function b1 b0 RW Operation mode select bit Pulse output function select bit 0 0 : Timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) b4 b3 MR1 Gate function select bit 0 X (Note 2): Gate function not available (TAiIN pin is a normal port pin) MR2 1 0 : Timer counts only when TAiIN pin is held “L” (Note 3) 1 1 : Timer counts only when TAiIN pin is held “H” (Note 3) 0 (Must always be “0” in timer mode) Count source select bit b7 b6 MR3 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0”. Figure 1.14.7. Timer Ai mode register in timer mode 1-83 Mitsubishi microcomputers M16C / 62A Group Timer A (2) Event counter mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external signal. Table 1.14.2 lists timer specifications when counting a single-phase external signal. Figure 1.14.8 shows the timer Ai mode register in event counter mode. Table 1.14.3 lists timer specifications when counting a two-phase external signal. Figure 1.14.9 shows the timer Ai mode register in event counter mode. Table 1.14.2. Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source • External signals input to TAiIN pin (effective edge can be selected by software) • TB2 overflow, TAj overflow Count operation • Up count or down count can be selected by external signal or software • When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function • Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it • Pulse output function Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed Note: This does not apply when the free-run function is selected. Timer Ai mode register (When not using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 b1 b0 0 01 Symbol Address TAiMR(i = 0 to 4) 039616 to 039A16 Bit symbol TMOD0 TMOD1 MR0 Pulse output function select bit Bit name Operation mode select bit b1 b0 When reset 0016 Function RW 0 1 : Event counter mode (Note 1) 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4) MR1 MR2 MR3 TCK0 TCK1 Count polarity select bit (Note 3) Up/down switching cause select bit 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type 1 : Free-run type Invalid when not using two-phase pulse signal processing Can be “0” or “1” Note 1: In event counter mode, the count source is selected by the event / trigger select bit (addresses 038216 and 038316). Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”, the upcount is activated. Set the corresponding port direction register to “0”. Figure 1.14.8. Timer Ai mode register in event counter mode 1-84 Mitsubishi microcomputers M16C / 62A Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.14.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4) Item Count source Count operation Specification • Two-phase pulse signals input to TAiIN or TAiOUT pin • Up count or down count can be selected by two-phase pulse signal • When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note 1) 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) Timer overflows or underflows Two-phase pulse input (Set the TAiIN pin correspondent port direction register to “0”.) Two-phase pulse input (Set the TAiOUT pin correspondent port direction register to “0”.) Count value can be read out by reading timer A2, A3, or A4 register • When counting stopped When a value is written to timer A2, A3, or A4 register, it is written to both reload register and counter • When counting in progress When a value is written to timer A2, A3, or A4 register, it is written to only reload register. (Transferred to counter at next reload time.) • Normal processing operation (timer A2 and timer A3) The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is “H”. Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Select function (Note 2) TAiOUT TAiIN (i=2,3) Up count Up count Up Down count count Down count Down count • Multiply-by-4 processing operation (timer A3 and timer A4) If the phase relationship is such that the TAiIN pin goes “H” when the input signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer counts down rising and falling edges on the TAiOUT and TAiIN pins. TAiOUT Count up all edges Count down all edges TAiIN (i=3,4) Count up all edges Count down all edges Note 1: This does not apply when the free-run function is selected. Note 2: Timer A3 alone can be selected. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to multiply-by-4 processing operation. 1-85 Mitsubishi microcomputers M16C / 62A Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Ai mode register (When using two-phase pulse signal processing) b6 b5 b4 b3 b2 b1 b0 010001 Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016 Bit name TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 Function b1 b0 RW Operation mode select bit 0 1 : Event counter mode 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) 1 (Must always be “1” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) Count operation type select bit Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation TCK1 Note 1: This bit is valid for timer A3 mode register. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to multiply-by-4 processing operation. Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 038416) is set to “1”. Also, always be sure to set the event/trigger select bit (addresses 038216 and 038316) to “00”. Figure 1.14.9. Timer Ai mode register in event counter mode 1-86 Mitsubishi microcomputers M16C / 62A Group Timer A (3) One-shot timer mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer operates only once. (See Table 1.14.4.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.14.10 shows the timer Ai mode register in one-shot timer mode. Table 1.14.4. Timer specifications in one-shot timer mode Item Count source Count operation Specification f1, f8, f32, fC32 • The timer counts down • When the count reaches 000016, the timer stops counting after reloading a new count • If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : Set value • An external trigger is input • The timer overflows • The one-shot start flag is set (= 1) • A new count is reloaded after the count has reached 000016 • The count start flag is reset (= 0) The count reaches 000016 Programmable I/O port or trigger input Programmable I/O port or pulse output When timer Ai register is read, it indicates an indeterminate value • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 0 10 Symbol Address When reset TAiMR(i = 0 to 4) 039616 to 039A16 0016 Bit symbol TMOD0 TMOD1 MR0 Pulse output function select bit Bit name Operation mode select bit b1 b0 Function 1 0 : One-shot timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin) 0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3) RW MR1 MR2 External trigger select bit (Note 2) Trigger select bit 0 : One-shot start flag is valid 1 : Selected by event/trigger select bits MR3 TCK0 TCK1 0 (Must always be “0” in one-shot timer mode) Count source select bit b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0”. Figure 1.14.10. Timer Ai mode register in one-shot timer mode 1-87 Mitsubishi microcomputers M16C / 62A Group Timer A (4) Pulse width modulation (PWM) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer outputs pulses of a given width in succession. (See Table 1.14.5.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.14.11 shows the timer Ai mode register in pulse width modulation mode. Figure 1.14.12 shows the example of how a 16-bit pulse width modulator operates. Figure 1.14.13 shows the example of how an 8bit pulse width modulator operates. Table 1.14.5. Timer specifications in pulse width modulation mode Item Count source Count operation Specification f1, f8, f32, fC32 • The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) • The timer reloads a new count at a rising edge of PWM pulse and continues counting • The timer is not affected by a trigger that occurs when counting • High level width n / fi n : Set value • Cycle time (216-1) / fi fixed • High level width n (m+1) / fi n : values set to timer Ai register’s high-order address • Cycle time (28-1) (m+1) / fi m : values set to timer Ai register’s low-order address • External trigger is input • The timer overflows • The count start flag is set (= 1) • The count start flag is reset (= 0) PWM pulse goes “L” Programmable I/O port or trigger input Pulse output When timer Ai register is read, it indicates an indeterminate value • When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter • When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) 16-bit PWM 8-bit PWM Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 11 1 Symbol TAiMR(i=0 to 4) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 Address When reset 039616 to 039A16 0016 Function b1 b0 Bit name Operation mode select bit 1 1 : PWM mode RW 1 (Must always be “1” in PWM mode) External trigger select bit (Note 1) Trigger select bit 0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2) 0: Count start flag is valid 1: Selected by event/trigger select bits 0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator b7 b6 MR3 16/8-bit PWM mode select bit TCK0 Count source select bit TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”. Note 2: Set the corresponding port direction register to “0”. Figure 1.14.11. Timer Ai mode register in pulse width modulation mode 1-88 Mitsubishi microcomputers M16C / 62A Group Timer A SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected 1 / fi X (2 16 – 1) Count source TAiIN pin input signal “H” “L” Trigger is not generated by this signal 1 / fi X n PWM pulse output from TAiOUT pin Timer Ai interrupt request bit “H” “L” “1” “0” fi : Frequency of count source (f1, f8, f32, fC32) Cleared to “0” when interrupt request is accepted, or cleared by software Note: n = 000016 to FFFE16. Figure 1.14.12. Example of how a 16-bit pulse width modulator operates Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected 1 / fi X (m + 1) X (2 8 – 1) Count source (Note1) TAiIN pin input signal “H” “L” 1 / fi X (m + 1) “H” Underflow signal of 8-bit prescaler (Note2) “L” 1 / fi X (m + 1) X n PWM pulse output from TAiOUT pin Timer Ai interrupt request bit “H” “L” “1” “0” fi : Frequency of count source (f1, f8, f32, fC32) Cleared to “0” when interrupt request is accepted, or cleaerd by software Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FE16. Figure 1.14.13. Example of how an 8-bit pulse width modulator operates 1-89 Mitsubishi microcomputers M16C / 62A Group Timer B Timer B SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.14.14 shows the block diagram of timer B. Figures 1.14.15 and 1.14.16 show the timer B-related registers. Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts pulses from an external source or a timer overflow. • Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width. Data bus high-order bits Data bus low-order bits Low-order 8 bits High-order 8 bits Clock source selection f1 f8 f32 fC32 TBiIN (i = 0 to 5) • Timer • Pulse period/pulse width measurement Reload register (16) • Event counter Polarity switching and edge pulse Count start flag (address 038016) Counter reset circuit Can be selected in only event counter mode TBj overflow (j = i – 1. Note, however, j = 2 when i = 0, j = 5 when i = 3) TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5 Counter (16) Address 039116 039016 039316 039216 039516 039416 035116 035016 035316 035216 035516 035416 TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4 Figure 1.14.14. Block diagram of timer B Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address TBiMR(i = 0 to 5) 039B16 to 039D16 035B16 to 035D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Must not be set. R W MR0 MR1 MR2 Function varies with each operation mode (Note 1) (Note 2) MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode) Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Figure 1.14.15. Timer B-related registers (1) 1-90 Mitsubishi microcomputers M16C / 62A Group Timer B SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Bi register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TB0 TB1 TB2 TB3 TB4 TB5 Address 039116, 039016 039316, 039216 039516, 039416 035116, 035016 035316, 035216 035516, 035416 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set Function • Timer mode Counts the timer's period • Event counter mode Counts external pulses input or a timer overflow • Pulse period / pulse width measurement mode Measures a pulse period or width RW 000016 to FFFF16 000016 to FFFF16 Note: Read and write data in 16-bit units. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Function 0 : Stops counting 1 : Starts counting RW Timer B3, 4, 5 count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBSR Address 034016 When reset 000XXXXX2 Bit symbol Nothing is assigned. Bit name Function RW In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. TB3S TB4S TB5S Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag 0 : Stops counting 1 : Starts counting Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 When reset 0XXXXXXX2 Bit symbol Nothing is assigned. Bit name Function RW In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Figure 1.14.16. Timer B-related registers (2) 1-91 Mitsubishi microcomputers M16C / 62A Group Timer B (1) Timer mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an internally generated count source. (See Table 1.14.6.) Figure 1.14.17 shows the timer Bi mode register in timer mode. Table 1.14.6. Timer specifications in timer mode Item Count source Count operation Specification f1, f8, f32, fC32 • Counts down • When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows Programmable I/O port Count value is read out by reading timer Bi register • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol TBiMR(i=0 to 5) Address 039B16 to 039D16 035B16 to 035D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode R W Invalid in timer mode Can be “0” or “1” 0 (Must always be “0” in timer mode ; i = 0, 3) Nothing is assiigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. (Note 1) (Note 2) MR3 Invalid in timer mode. In an attempt to write to this bit, write “0”. The value, if read in timer mode, turns out to be indeterminate. Count source select bit b7 b6 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Figure 1.14.17. Timer Bi mode register in timer mode 1-92 Mitsubishi microcomputers M16C / 62A Group Timer B (2) Event counter mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.14.7.) Figure 1.14.18 shows the timer Bi mode register in event counter mode. Table 1.14.7. Timer specifications in event counter mode Item Count source Specification • External signals input to TBiIN pin • Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation • Counts down • When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows TBiIN pin function Read from timer Write to timer Count source input Count value can be read out by reading timer Bi register • When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter • When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 01 Symbol TBiMR(i=0 to 5) Address 039B16 to 039D16 035B16 to 035D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode select bit b1 b0 Function 0 1 : Event counter mode b3 b2 R W Count polarity select bit (Note 1) MR1 0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Must not be set. (Note 2) MR2 0 (Must always be “0” in event counter mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Invalid in event counter mode. In an attempt to write to this bit, write “0”. The value, if read in event counter mode, turns out to be indeterminate. Invalid in event counter mode. Can be “0” or “1”. Event clock select 0 : Input from TBiIN pin (Note 4) 1 : TBj overflow (j = i – 1; however, j = 2 when i = 0, j = 5 when i = 3) (Note 3) MR3 TCK0 TCK1 Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be “0” or “1”. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Note 4: Set the corresponding port direction register to “0”. Figure 1.14.18. Timer Bi mode register in event counter mode 1-93 Mitsubishi microcomputers M16C / 62A Group Timer B (3) Pulse period/pulse width measurement mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.14.8.) Figure 1.14.19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 1.14.20 shows the operation timing when measuring a pulse period. Figure 1.14.21 shows the operation timing when measuring a pulse width. Table 1.14.8. Timer specifications in pulse period/pulse width measurement mode Item Count source Count operation Specification f1, f8, f32, fC32 • Up count • Counter value “000016” is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1) • When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to “1”. The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the timer Bi mode register.) TBiIN pin function Measurement pulse input Read from timer When timer Bi register is read, it indicates the reload register’s content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer has started counting. Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol TBiMR(i=0 to 5) Address 039B16 to 039D16 035B16 to 035D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 MR0 Bit name Operation mode select bit Measurement mode select bit b1 b0 Function 1 0 : Pulse period / pulse width measurement mode b3 b2 R W MR1 0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Must not be set. (Note 2) MR2 0 (Must always be “0” in pulse period/pulse width measurement mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. (Note 3) MR3 TCK0 TCK1 Timer Bi overflow flag ( Note 1) Count source select bit 0 : Timer did not overflow 1 : Timer has overflowed b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Note 1: It is indeterminate when reset. The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the timer Bi mode register. This flag cannot be set to “1” by software. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Figure 1.14.19. Timer Bi mode register in pulse period/pulse width measurement mode 1-94 Mitsubishi microcomputers M16C / 62A Group Timer B SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When measuring measurement pulse time interval from falling edge to falling edge Count source Measurement pulse “H” “L” Transfer (indeterminate value) Transfer (measured value) Reload register transfer timing counter (Note 1) (Note 1) (Note 2) Timing at which counter reaches “000016” Count start flag “1” “0” Timer Bi interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software. Timer Bi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.14.20. Operation timing when measuring a pulse period Count source Measurement pulse “H” “L” Transfer (indeterminate value) Transfer (measured value) Transfer (measured value) Transfer (measured value) Reload register transfer timing counter (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) Timing at which counter reaches “000016” “1” “0” Count start flag Timer Bi interrupt request bit “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software. Timer Bi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 1.14.21. Operation timing when measuring a pulse width 1-95 Mitsubishi microcomputers M16C / 62A Group Timers’ functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timers’ functions for three-phase motor control Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor driving waveforms. Figures 1.15.1 to 1.15.3 show registers related to timers for three-phase motor control. Three-phase PWM control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol INVC0 Address 034816 When reset 0016 R W Bit symbol INV00 Bit name Description Effective interrupt output 0: A timer B2 interrupt occurs when the timer A1 reload control signal is “1”. polarity select bit 1: A timer B2 interrupt occurs when the timer A1 reload control signal is “0”. Effective only in three-phase mode 1 Effective interrupt output 0: Not specified. 1: Selected by the effective interrupt output specification bit polarity selection bit. (Note 4) Effective only in three-phase mode 1 Mode select bit (Note 2) Output control bit Positive and negative phases concurrent L output disable function enable bit Positive and negative phases concurrent L output detect flag 0: Normal mode 1: Three-phase PWM output mode 0: Output disabled 1: Output enabled 0: Feature disabled 1: Feature enabled INV01 INV02 INV03 INV04 INV05 INV06 INV07 0: Not detected yet 1: Already detected (Note 1) Modulation mode select 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode bit (Note 3) Software trigger bit 1: Trigger generated The value, when read, is “0”. Note 1: No value other than “0” can be written. Note 2: Selecting three-phase PWM output mode causes P80, P81, and P72 through P75 to output U, U, V, V, W, and W, and works the timer for setting short circuit prevention time, the U, V, W phase output control circuits, and the circuit for setting timer B2 interrupt frequency. Note 3: In triangular wave modulation mode: The short circuit prevention timer starts in synchronization with the falling edge of timer Ai output. The data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchronization with the transfer trigger signal after writing to the three-phase output buffer register. In sawtooth wave modulation mode: The short circuit prevention timer starts in synchronization with the falling edge of timer A output and with the transfer trigger signal. The data transfer from the three-phase output buffer register to the three-phase output shift register is made with respect to every transfer trigger. Note 4: To write “1” to bit 1 (INV01) of the three-phase PWM control register 0, set in advance the content of the timer B2 interrupt occurrences frequency set counter. Three-phase 0 PWM control register 1 Symbol INVC1 b7 b6 b5 b4 b3 b2 b1 b0 Address 034916 When reset 0016 R W Bit symbol INV10 Bit name Timer Ai start trigger signal select bit Timer A1-1, A2-1, A4-1 control bit Short circuit timer count source select bit Description 0: Timer B2 overflow signal 1: Timer B2 overflow signal, signal for writing to timer B2 0: Three-phase mode 0 1: Three-phase mode 1 0 : Must not be set. 1 : f1/2 (Note) INV11 INV12 Noting is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. Reserved bit Must always be set to “0” Noting is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note : To use three-phase PWM output mode, write “1” to INV12. Figure 1.15.1. Registers related to timers for three-phase motor control 1-96 Mitsubishi microcomputers M16C / 62A Group Timers’ functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Three-phase output buffer register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol IDB0 Bit Symbol Address 034A16 When reset 0016 Bit name U phase output buffer 0 U phase output buffer 0 V phase output buffer 0 V phase output buffer 0 W phase output buffer 0 W phase output buffer 0 Function Setting in U phase output buffer 0 Setting in U phase output buffer 0 Setting in V phase output buffer 0 Setting in V phase output buffer 0 R (Note) (Note) (Note) (Note) W DU0 DUB0 DV0 DVB0 DW0 DWB0 Setting in W phase output buffer 0 (Note) Setting in W phase output buffer 0 (Note) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note: When executing read instruction of this register, the contents of three-phase shift register is read out. Three-phase output buffer register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol IDB1 Bit Symbol Address 034B16 When reset 0016 Bit name U phase output buffer 1 U phase output buffer 1 V phase output buffer 1 V phase output buffer 1 W phase output buffer 1 W phase output buffer 1 Function Setting in U phase output buffer 1 Setting in U phase output buffer 1 Setting in V phase output buffer 1 Setting in V phase output buffer 1 R (Note) (Note) (Note) (Note) W DU1 DUB1 DV1 DVB1 DW1 DWB1 Setting in W phase output buffer 1 (Note) Setting in W phase output buffer 1 (Note) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note: When executing read instruction of this register, the contents of three-phase shift register is read out. Dead time timer (Note) b7 b0 Symbol DTT Address 034C16 When reset Indeterminate Function Set dead time timer Note: Use MOV instruction to write to this register. Values that can be set 1 to 255 RW Timer B2 interrupt occurrences frequency set counter (Note 1, 2, 3) b3 b0 Symbol ICTB2 Address 034D16 When reset Indeterminate Function Set occurrence frequency of timer B2 interrupt request Values that can be set 1 to 15 R W Note 1: In setting 1 to bit 1 (INV01) - the effective interrupt output specification bit - of threephase PWM control register 0, do not change the B2 interrupt occurrences frequency set counter to deal with the timer function for three-phase motor control. Note 2: Do not write at the timing of an overflow occurrence in timer B2. Note 3: Use MOV instruction to write to this register. Figure 1.15.2. Registers related to timers for three-phase motor control 1-97 Mitsubishi microcomputers M16C / 62A Group Timers’ functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Ai register (Note 1) (b15) b7 (b8) b0 b7 b0 Symbol TA1 TA2 TA4 TB2 Address 038916,038816 038B16,038A16 038F16,038E16 039516,039416 When reset Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set Function • Timer mode Counts an internal count source • One-shot timer mode Counts a one shot width RW 000016 to FFFF16 000016 to FFFF16 (Note 2, 3) Note 1: Read and write data in 16-bit units. Note 2: When the timer Ai register is set to "000016", the counter does not operate and a timer Ai interrupt does not occur. Note 3: Use MOV instruction to write to this register. Timer Ai-1 register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TA11 TA21 TA41 Address 034316,034216 034516,034416 034716,034616 When reset Indeterminate Indeterminate Indeterminate Values that can be set Function Counts an internal count source Note: Read and write data in 16-bit units. RW 000016 to FFFF16 Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Bit symbol TA1TGL Address 038316 Bit name Timer A1 event/trigger select bit When reset 0016 Function b1 b0 RW TA1TGH TA2TGL 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 Timer A2 event/trigger select bit TA2TGH TA3TGL 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 Timer A3 event/trigger select bit TA3TGH 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 TA4TGL Timer A4 event/trigger select bit TA4TGH 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note: Set the corresponding port direction register to “0”. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Bit symbol Address 038016 Bit name When reset 0016 Function RW TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag 0 : Stops counting 1 : Starts counting Figure 1.15.3. Registers related to timers for three-phase motor control 1-98 Mitsubishi microcomputers M16C / 62A Group Timers’ functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Three-phase motor driving waveform output mode (three-phase PWM output mode) Setting “1” in the mode select bit (bit 2 at 034816) shown in Figure 1.15.1 - causes three-phase PWM output mode that uses four timers A1, A2, A4, and B2 to be selected. As shown in Figure 1.15.4, set timers A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer B2 in timer mode using the respective timer mode registers. Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 01 010 Symbol TA1MR TA2MR TA3MR Address 039716 039816 039A16 Bit name Operation mode select bit Pulse output function select bit External trigger select bit Trigger select bit When reset 0016 0016 0016 Function b1 b0 Bit symbol TMOD0 TMOD1 MR0 RW 1 0 : One-shot timer mode 0 (Must always be “0” in three-phase PWM output mode) Invalid in three-phase PWM output mode 1 : Selected by event/trigger select register MR1 MR2 MR3 TCK0 TCK1 0 (Must always be “0” in one-shot timer mode) Count source select bit b7 b6 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Timer B2 mode register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol TB2MR Bit symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 Address 039D16 When reset 00XX00002 RW Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode Invalid in timer mode Can be “0” or “1” 0 (Must always be “0” in timer mode) Invalid in timer mode. In an attempt to write to this bit, write "0". When read in timer mode, its content is indeterminate. Count source select bit b7 b6 TCK0 TCK1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Figure 1.15.4. Timer mode registers in three-phase PWM output mode 1-99 Mitsubishi microcomputers M16C / 62A Group Timers’ functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.15.5 shows the block diagram for three-phase PWM output mode. In three-phase PWM output ___ mode, the positive-phase waveforms (U phase, V phase, and W phase) and negative waveforms (U ___ ___ phase, V phase, and W phase), six waveforms in total, are output from P80, P81, P72, P73, P74, and P75 ___ as active on the “L” level. Of the timers used in this mode, timer A4 controls the U phase and U phase, ___ ___ timer A1 controls the V phase and V phase, and timer A2 controls the W phase and W phase respectively; timer B2 controls the periods of one-shot pulse output from timers A4, A1, and A2. In outputting a waveform, dead time can be set so as to cause the “L” level of the positive waveform ___ output (U phase, V phase, and W phase) not to lap over the “L” level of the negative waveform output (U ___ ___ phase, V phase, and W phase). To set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. A value from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead time works as a one-shot timer. If a value is written to the dead time timer (034C16), the value is written to the reload register shared by the three timers for setting dead time. Any of the timers for setting dead time takes the value of the reload register into its counter, if a start trigger comes from its corresponding timer, and performs a down count in line with the clock source selected by the dead time timer count source select bit (bit 2 at 034916). The timer can receive another trigger again before the workings due to the previous trigger are completed. In this instance, the timer performs a down count from the reload register’s content after its transfer, provoked by the trigger, to the timer for setting dead time. Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger comes; it stops outputting pulses as soon as its content becomes 0016, and waits for the next trigger to come. ___ ___ The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V ___ phase, and W phase) in three-phase PWM output mode are output from respective ports by means of setting “1” in the output control bit (bit 3 at 034816). Setting “0” in this bit causes the ports to be the state of set by port direction register. This bit can be set to “0” not only by use of the applicable instruction, but _______ by entering a falling edge in the NMI terminal or by resetting. Also, if “1” is set in the positive and negative phases concurrent L output disable function enable bit (bit 4 at 034816) causes one of the pairs of U ___ ___ ___ phase and U phase, V phase and V phase, and W phase and W phase concurrently go to “L”, as a result, the port becomes the state of set by port direction register. 1-100 INV00 1 Interrupt request bit INV05 0 f1 1/2 Trigger Trigger Dead time timer setting (8) n = 1 to 255 Bit 0 at 034B16 Bit 0 at 034A16 DQ T INV06 U phase output control circuit DU0 U phase output signal 1 n = 1 to 255 INV04 INV12 (Note) Reload register RESET NMI Interrupt occurrence frequency set counter n = 1 to 15 R INV01 INV11 INV03 D Q Circuit for interrupt occurrence frequency set counter Overflow Signal to be written to B2 INV10 INV07 Timer B2 (Timer mode) U(P80) Trigger signal for timer Ai start Control signal for timer A4 reload Trigger signal for transfer DU1 D Q D Q T T Timer A4 Reload Timer A4-1 Trigger Three-phase output shift register (U phase) Timer A4 counter DUB1 U phase output signal DUB0 (One-shot timer mode) INV11 D Q D Q T T Timers’ functions for three-phase motor control TQ DQ T U(P81) To be set to “0” when timer A4 stops Trigger Trigger Dead time timer setting (8) n = 1 to 255 V phase output signal V phase output signal INV06 V phase output control circuit DQ T V(P72) Timer A1 Reload Timer A1-1 Figure 1.15.5. Block diagram for three-phase PWM output mode V(P73) DQ T For short circuit prevention Dead time timer setting (8) n = 1 to 255 W phase output signal W phase output signal DQ T DQ T Trigger Trigger INV06 Trigger Timer A1 counter (One-shot timer mode) INV11 TQ To be set to “0” when timer A1 stops W(P74) Timer A2 Reload Timer A2-1 Trigger Timer A2 counter W phase output control circuit W(P75) (One-shot timer mode) INV11 TQ To be set to “0” when timer A2 stops Diagram for switching to P80, P81, and to P72 - P75 is not shown. M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mitsubishi microcomputers Note: To use three-phase output mode, write "1" to INV12. 1-101 Mitsubishi microcomputers M16C / 62A Group Timers’ functions for three-phase motor control Triangular wave modulation SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit (bit 6 at 034816). Also, set “1” in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 034916). In this mode, each of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register’s content to the counter every time timer B2 counter’s content becomes 000016. If “0” is set to the effective interrupt output specification bit (bit 1 at 034816), the frequency of interrupt requests that occur every time the timer B2 counter’s value becomes 000016 can be set by use of the timer B2 counter (034D16) for setting the frequency of interrupt occurrences. The frequency of occurrences is given by (setting; setting ≠ 0). Setting “1” in the effective interrupt output specification bit (bit 1 at 034816) provides the means to choose which value of the timer A1 reload control signal to use, “0” or “1”, to cause timer B2’s interrupt request to occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at 034816). An example of U phase waveform is shown in Figure 1.15.6, and the description of waveform output workings is given below. Set “1” in DU0 (bit 0 at 034A16). And set “0” in DUB0 (bit 1 at 034A16). In addition, set “0” in DU1 (bit 0 at 034B16) and set “1” in DUB1 (bit 1 at 034B16). Also, set “0” in the effective interrupt output specification bit (bit 1 at 034816) to set a value in the timer B2 interrupt occurrence frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter’s content becomes 000016 as many as (setting) times. Furthermore, set “1” in the effective interrupt output specification bit (bit 1 at 034816), set “0” in the effective interrupt output polarity select bit (bit 0 at 034816) and set "1" in the interrupt occurrence frequency set counter (034D16). These settings cause a timer B2 interrupt to occur every other interval when the U phase output goes to “H”. When the timer B2 counter’s content becomes 000016, timer A4 starts outputting one-shot pulses. In this instance, the content of DU1 (bit 0 at 034B16) and that of DU0 (bit 0 at 034A16) are set in the three-phase output shift register (U phase), the content of DUB1 (bit 1 at 034B16) and that of DUB0 (bit 1 at 034A16) ___ are set in the three-phase output shift register (U phase). After triangular wave modulation mode is selected, however, no setting is made in the shift register even though the timer B2 counter’s content becomes 000016. ___ The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81) respectively. When the timer A4 counter counts the value written to timer A4 (038F16, 038E16) and when timer A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one posi___ tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for ___ setting the time over which the “L” level of the U phase waveform does not lap over the “L” level of the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the “H” level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register’s content changes from “1” to “0” by the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, "0" already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L" level. When the timer B2 counter’s content becomes 000016, the timer A4 counter starts counting the value written to timer A4-1 (034716, 034616), and starts outputting one-shot pulses. When timer A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one position, but if the three-phase output shift register’s content changes from “0” to “1” as a result of the shift, the output level changes from “L” to “H” without waiting for the timer for setting dead time to finish outputting one-shot pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the __ __ three-phase output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U 1-102 Mitsubishi microcomputers M16C / 62A Group Timers’ functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in __ which the "L" level of the U phase waveform doesn’t lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the “L” level too can be adjusted by varying the ___ ___ values of timer B2, timer A4, and timer A4-1. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with ___ the U and U phases to generate an intended waveform. A carrier wave of triangular waveform Carrier wave Signal wave Timer B2 Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m Timer B2 interrupt occurs Rewriting timer A4 and timer A4-1. Possible to set the number of overflows to generate an interrupt by use of the interrupt occurrences frequency set circuit n m n m p o Control signal for timer A4 reload The three-phase shift register shifts in synchronization with the falling edge of the timer A4 output. U phase output signal U phase output signal U phase U phase Dead time Note: Set to triangular wave modulation mode and to three-phase mode 1. Figure 1.15.6. Timing chart of operation (1) 1-103 Mitsubishi microcomputers M16C / 62A Group Timers’ functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Assigning certain values to DU0 (bit 0 at 034A16) and DUB0 (bit 1 at 034A16), and to DU1 (bit 0 at 034B16) and DUB1 (bit 1 at 034B16) allows the user to output the waveforms as shown in Figure 1.15.7, that is, to ___ ___ output the U phase alone, to fix U phase to “H”, to fix the U phase to “H,” or to output the U phase alone. Carrier wave Signal wave Timer B2 Rewriting timer A4 every timer B2 interrupt occurs. Timer B2 interrupt occurs. Rewriting three-phase buffer register. Trigger signal for timer Ai start (timer B2 overflow signal) Timer A4 output m n m n m p o U phase output signal U phase output signal U phase U phase Dead time Note: Set to triangular wave modulation mode and to three-phase mode 0. Figure 1.15.7. Timing chart of operation (2) 1-104 Mitsubishi microcomputers M16C / 62A Group Timers’ functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Sawtooth modulation To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit (bit 6 at 034816). Also, set “0” in the timers A4-1, A1-1, and A2-1 control bit (bit 1 at 034916). In this mode, the timer registers of timers A4, A1, and A2 comprise conventional timers A4, A1, and A2 alone, and reload the corresponding timer register’s content to the counter every time the timer B2 counter’s content becomes 000016. The effective interrupt output specification bit (bit 1 at 034816) and the effective interrupt output polarity select bit (bit 0 at 034816) go nullified. An example of U phase waveform is shown in Figure 1.15.8, and the description of waveform output workings is given below. Set “1” in DU0 (bit 0 at 034A16), and set “0” in DUB0 (bit 1 at 034A16). In addition, set “0” in DU1 (bit 0 at 034A16) and set “1” in DUB1 (bit 1 at 034A16). When the timber B2 counter’s content becomes 000016, timer B2 generates an interrupt, and timer A4 starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of ___ DUB1 and DUB0 are set in the three-phase output shift register (U phase). After this, the three-phase buffer register’s content is set in the three-phase shift register every time the timer B2 counter’s content becomes 000016. ___ The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81) respectively. When the timer A4 counter counts the value written to timer A4 (038F16, 038E16) and when timer A4 finishes outputting one-shot pulses, the three-phase output shift register’s content is shifted one ___ position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the U output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L” level of ___ the U phase waveform, which has the opposite phase of the former. The U phase waveform output that started from the “H” level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift register’s content changes from “1” to “0 ”by the effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the “L” level. When the timer B2 counter’s content becomes 000016, the contents of the three-phase buffer registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of ___ DUB1 and DUB0 are set in the three-phase output shift register (U phase) again. A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase ___ ___ output shift register on the U phase side is used, the workings in generating a U phase waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which the “L” level of ___ the U phase waveform doesn’t lap over that of the U phase waveform, which has the opposite phase of the U phase waveform. The width of the “L” level too can be adjusted by varying the values of timer B2 ___ ___ and timer A4. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase ___ of the former, have the corresponding timers work similarly to dealing with the U and U phases to generate an intended waveform. ___ Setting “1” both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U phase output to “H” as shown in Figure 1.15.9. 1-105 Mitsubishi microcomputers M16C / 62A Group Timers’ functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Trigger signal for timer Ai start (timer B2 overflow signal) Interrupt occurs. Rewriting the value of timer A4. Data transfer is made from the threephase buffer register to the threephase shift register in step with the timing of the timer B overflow. Timer A4 output m n o p U phase output signal U phase output signal U phase U phase The three-phase shift register shifts in synchronization with the falling edge of timer A4. Dead time Note: Set to sawtooth modulation mode and to three-phase mode 0. Figure 1.15.8. Timing chart of operation (3) 1-106 Mitsubishi microcomputers M16C / 62A Group Timers’ functions for three-phase motor control SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A carrier wave of sawtooth waveform Carrier wave Signal wave Timer B2 Interrupt occurs. Rewriting the value of timer A4. Interrupt occurs. Rewriting the value of timer A4. Trigger signal for timer Ai start (timer B2 overflow signal) Rewriting three-phase output buffer register Data transfer is made from the threephase buffer register to the threephase shift register in step with the timing of the timer B overflow. Timer A4 output m n o p The three-phase shift register shifts in synchronization with the falling edge of timer A4. U phase output signal U phase output signal U phase U phase Dead time Note: Set to sawtooth modulation mode and to three-phase mode 0. Figure 1.15.9. Timing chart of operation (4) 1-107 Mitsubishi microcomputers M16C / 62A Group Serial I/O Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4. UART0 to 2 UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.16.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.16.2 and 1.16.3 show the block diagram of the transmit/receive unit. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions. UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. Table 1.16.1 shows the comparison of functions of UART0 through UART2, and Figures 1.16.4 to 1.16.9 show the registers related to UARTi. Note: SIM : Subscriber Identity Module Table 1.16.1. Comparison of functions of UART0 through UART2 Function CLK polarity selection LSB first / MSB first selection Continuous receive mode selection Transfer clock output from multiple pins selection Serial data logic switch Sleep mode selection TxD, RxD I/O polarity switch TxD, RxD port output format Parity error signal output Bus collision detection UART0 Possible Possible Possible Impossible Impossible Possible Impossible CMOS output Impossible Impossible (Note 3) (Note 1) (Note 1) (Note 1) UART1 Possible Possible Possible Possible Impossible Possible Impossible CMOS output Impossible Impossible (Note 3) (Note 1) (Note 1) (Note 1) (Note 1) UART2 Possible Possible Possible Impossible Possible Impossible Possible N-channel open-drain output Possible Possible (Note 4) (Note 4) (Note 1) (Note 2) (Note 1) Note 1: Only when clock synchronous serial I/O mode. Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only when UART mode. Note 4: Using for SIM interface. 1-108 Mitsubishi microcomputers M16C / 62A Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (UART0) RxD0 UART reception TxD0 1/16 Clock source selection f1 f8 f32 Bit rate generator Internal (address 03A116) Clock synchronous type UART transmission Reception control circuit Receive clock Transmit/ receive unit 1 / (n0+1) External 1/16 Clock synchronous type Transmission control circuit Transmit clock Clock synchronous type 1/2 (when internal clock is selected) Clock synchronous type (when internal clock is selected) CLK0 CLK polarity reversing circuit CTS/RTS disabled CTS/RTS selected Clock synchronous type (when external clock is selected) CTS0 / RTS0 Vcc CTS/RTS disabled RTS0 CTS0 (UART1) RxD1 Clock source selection f1 f8 f32 1/16 TxD1 UART reception Reception control circuit Receive clock Bit rate generator Internal (address 03A916) Clock synchronous type UART transmission 1/16 Transmit/ receive unit 1 / (n1+1) External Clock synchronous type Clock synchronous type 1/2 (when internal clock is selected) Transmission control circuit Transmit clock CLK1 CTS1 / RTS1/ CLKS1 CLK polarity reversing circuit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CTS/RTS disabled CTS/RTS selected RTS1 CTS1 Clock output pin select switch VCC CTS/RTS disabled (UART2) RxD2 RxD polarity reversing circuit UART reception 1/16 Clock source selection f1 f8 f32 Bit rate generator Internal (address 037916) Clock synchronous type UART transmission 1/16 Reception control circuit Receive clock TxD polarity reversing circuit Transmit/ receive unit TxD2 1 / (n2+1) External Clock synchronous type Clock synchronous type 1/2 Transmission control circuit Transmit clock (when internal clock is selected) CLK2 CLK polarity reversing circuit Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) CTS/RTS selected CTS/RTS disabled CTS2 / RTS2 Vcc CTS/RTS disabled RTS2 CTS2 n0 : Values set to UART0 bit rate generator (U0BRG) n1 : Values set to UART1 bit rate generator (U1BRG) n2 : Values set to UART2 bit rate generator (U2BRG) Figure 1.16.1. Block diagram of UARTi (i = 0 to 2) 1-109 Mitsubishi microcomputers M16C / 62A Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock synchronous type UART (7 bits) UART (8 bits) 1SP PAR disabled Clock synchronous type UART (7 bits) UARTi receive register RxDi SP 2SP SP PAR PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16 MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16 UART (8 bits) UART (9 bits) UART (9 bits) Clock synchronous type 2SP SP SP 1SP PAR PAR enabled UART TxDi PAR disabled Clock synchronous type UART (7 bits) UART (7 bits) UART (8 bits) Clock synchronous type UARTi transmit register “0” SP: Stop bit PAR: Parity bit Figure 1.16.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit 1-110 Mitsubishi microcomputers M16C / 62A Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER No reverse RxD2 RxD data reverse circuit Reverse Clock synchronous type 1SP SP 2SP SP PAR PAR disabled Clock synchronous type UART (7 bits) UART (8 bits) UART(7 bits) UART2 receive register PAR enabled UART UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits) 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UART2 receive buffer register Address 037E16 Address 037F16 Logic reverse circuit + MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits Logic reverse circuit + MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UART2 transmit buffer register Address 037A16 Address 037B16 UART (8 bits) UART (9 bits) PAR enabled UART (9 bits) UART Clock synchronous type 2SP SP SP 1SP PAR PAR disabled Clock synchronous type “0” UART (7 bits) UART (8 bits) Clock synchronous type UART(7 bits) UART2 transmit register Error signal output disable No reverse Error signal output circuit Error signal output enable Reverse TxD data reverse circuit TxD2 SP: Stop bit PAR: Parity bit Figure 1.16.3. Block diagram of UART2 transmit/receive unit 1-111 Mitsubishi microcomputers M16C / 62A Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit buffer register (Note) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16 When reset Indeterminate Indeterminate Indeterminate Function RW Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Use MOV instruction to write to this register. UARTi receive buffer register (b15) b7 (b8) b0 b7 b0 Symbol U0RB U1RB U2RB Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16 When reset Indeterminate Indeterminate Indeterminate Function (During UART mode) Receive data Bit symbol Bit name Function (During clock synchronous serial I/O mode) Receive data RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. ABT OER FER PER SUM Arbitration lost detecting flag (Note 2) 0 : Not detected 1 : Detected Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found Framing error flag (Note 1) Invalid Parity error flag (Note 1) Error sum flag (Note 1) Invalid Invalid Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016, 03A816 and 037816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but “0” may be written. Nothing is assigned in bit 11 of U0RB and U1RB. When write, set “0”. The value, if read, turns out to be “0”. UARTi bit rate generator (Note 1, 2) b7 b0 Symbol U0BRG U1BRG U2BRG Address 03A116 03A916 037916 Function When reset Indeterminate Indeterminate Indeterminate Values that can be set 0016 to FF16 RW Assuming that set value = n, BRGi divides the count source by n+1 Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register. Figure 1.16.4. Serial I/O-related registers (1) 1-112 Mitsubishi microcomputers M16C / 62A Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 03A016, 03A816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 Function (During UART mode) b2 b1 b0 RW 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock 1 : External clock (Note) Invalid Odd/even parity select bit Invalid PRYE SLEP Parity enable bit Sleep select bit Invalid Must always be “0” Note : Set the corresponding port direction register to “0”. UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2MR Address 037816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Function (During UART mode) b2 b1 b0 RW Must be fixed to 001 b2 b1 b0 0 0 0 : Serial I/O invalid 0 1 0 : (Note 1) 0 1 1 : Must not be set. 1 1 1 : Must not be set. 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. Must always be “0” CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock 1 : External clock (Note 2) Invalid 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Odd/even parity select bit Invalid PRYE IOPOL Parity enable bit TxD, RxD I/O polarity reverse bit Invalid 0 : No reverse 1 : Reverse Usually set to “0” 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to “0” Note 1: Bit 2 to bit 0 are set to “0102” when I2C mode is used. Note 2: Set the corresponding port direction register to “0”. Figure 1.16.5. Serial I/O-related registers (2) 1-113 Mitsubishi microcomputers M16C / 62A Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC0(i=0,1) Bit symbol CLK0 CLK1 CRS Address When reset 03A416, 03AC16 0816 Function (During clock synchronous serial I/O mode) b1 b0 b1 b0 Bit name BRG count source select bit Function (During UART mode) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) RW 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) CTS/RTS function select bit TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge NCH Data output select bit CKPOL CLK polarity select bit Must always be “0” UFORM Transfer format select bit 0 : LSB first 1 : MSB first Must always be “0” Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. UART2 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C0 Bit symbol CLK0 CLK1 CRS CTS/RTS function select bit Address 037C16 When reset 0816 Function (During clock synchronous serial I/O mode) Function (During UART mode) b1 b0 Bit name BRG count source select bit RW b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0: TXDi pin is CMOS output open-drain output CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : TXDi pin is CMOS output open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Nothing is assigned. CKPOL : TXDi pin is N-channel 1: to be “0”. In an attempt to write to this bit, write1“0”. The value, if read, turns out TXDi pin is N-channel CLK polarity select bit Must always be “0” UFORM Transfer format select bit 0 : LSB first 1 : MSB first (Note 3) 0 : LSB first 1 : MSB first Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. Figure 1.16.6. Serial I/O-related registers (3) 1-114 Mitsubishi microcomputers M16C / 62A Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC1(i=0,1) Address 03A516,03AD16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register RW RE RI Receive enable bit Receive complete flag Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. UART2 transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C1 Address 037D16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse Must be fixed to “0” Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) Must always be "0" RW RE RI Receive enable bit Receive complete flag U2IRS UART2 transmit interrupt cause select bit U2RRM UART2 continuous receive mode enable bit U2LCH Data logic select bit U2ERE Error signal output enable bit 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled Figure 1.16.7. Serial I/O-related registers (4) 1-115 Mitsubishi microcomputers M16C / 62A Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol UCON Address 03B016 When reset X00000002 Bit symbol U0IRS Bit name UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit Function (During clock synchronous serial I/O mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Function (During UART mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) RW U1IRS 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U0RRM UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode (CLK output is CLK1 only) Must always be “0” U1RRM UART1 continuous receive mode enable bit Must always be “0” CLKMD0 CLK/CLKS select bit 0 Invalid CLKMD1 CLK/CLKS select bit 1 (Note) Must always be “0” 1 : Transfer clock output from multiple pins function selected Reserved bit Must always be set to “0” Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: • UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”. UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR Address 037716 When reset 0016 Bit symbol IICM ABC BBS LSYN ABSCS Bit name I2C mode select bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit SDA digital delay select bit (Note 2, Note 3) Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : I2C mode 0 : Update per bit 1 : Update per byte 0 : STOP condition detected 1 : START condition detected Function (During UART mode) Must always be “0” Must always be “0” RW Must always be “0” (Note1) 0 : Disabled 1 : Enabled Must always be “0” Must always be “0” 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 0 : No auto clear function 1 : Auto clear at occurrence of bus collision ACSE Must always be “0” SSS Must always be “0” 0 : Analog delay output is selected 1 : Digital delay output is selected (must always be “0” when not using I 2 C mode) 0 : Ordinary 1 : Falling edge of RXD2 Must always be “0” SDDS Note 1: Nothing but “0” may be written. Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to “000”, with the analog delay circuit selected. Also, when SDDS = “0”, the U2SMR3 register cannot be read or written to. Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. Figure 1.16.8. Serial I/O-related registers (5) 1-116 Mitsubishi microcomputers M16C / 62A Group Serial I/O SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 special mode register 2 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR2 Address 037616 When reset 0016 Function (I2C bus exclusive use) Bit symbol IICM2 CSC SWC ALS STAC SWC2 SDHI SHTC Bit name I 2C mode select bit 2 Clock-synchronous bit SCL wait output bit SDA output stop bit UART2 initialization bit SCL wait output bit 2 SDA output disable bit Start/stop condition control bit RW Refer to Table 1.16.11 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: UART2 clock 1: 0 output 0: Enabled 1: Disabled (high impedance) Set this bit to “1” in I2C mode (refer to Table 1.16.12) UART2 special mode register 3 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Address 037516 When reset Indeterminate (However, when SDDS = “1”, the initial value is “0016”) Function (I 2 C bus exclusive use register) RW Bit symbol Bit name Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1) DL0 SDA digital delay setup bit (Note 1, Note 2, Note 3, Note 4) b7 b6 b5 DL1 DL2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Analog delay is selected 1 : 1 to 2 cycle(s) of 1/f(XIN) 0 : 2 to 3 cycles of 1/f(XIN) 1 : 3 to 4 cycles of 1/f(XIN) 0 : 4 to 5 cycles of 1/f(XIN) 1 : 5 to 6 cycles of 1/f(XIN) 0 : 6 to 7 cycles of 1/f(XIN) 1 : 7 to 8 cycles of 1/f(XIN) Digital delay is selected Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit 7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3 (U2SMR3) is read after setting SDDS = “1”, the value is “0016”. When writing to UART2 special mode register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”, this register cannot be written to; when read, the value is indeterminate. Note 2: These bits are initialized to “000” when SDDS = “0”, with the analog delay circuit selected. After a reset, these bits are set to “000”, with the analog delay circuit selected. However, because these bits can be read only when SDDS = “1”, the value read from these bits when SDDS = “0” is indeterminate. Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. Note 4: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of delay increases by about 100 ns, so be sure to take this into account when using the device. Figure 1.16.9. Serial I/O-related registers (6) 1-117 Mitsubishi microcomputers M16C / 62A Group Clock synchronous serial I/O mode (1) Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.16.2 and 1.16.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.16.10 shows the UARTi transmit/receive mode register. Table 1.16.2. Specifications of clock synchronous serial I/O mode (1) Specification • Transfer data length: 8 bits • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32 • When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “1”) : Input from CLKi pin _______ _______ _______ _______ Transmission/reception control • CTS function, RTS function, CTS and RTS function invalid: selectable Transmission start condition • To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” _______ _______ _ When CTS function selected, CTS input level = “L” • Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L” Reception start condition • To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” • Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”: CLKi input level = “H” _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”: CLKi input level = “L” • When transmitting Interrupt request _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at generation timing address 037D16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed • When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection • Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change. Item Transfer data format Transfer clock 1-118 Mitsubishi microcomputers M16C / 62A Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.16.3. Specifications of clock synchronous serial I/O mode (2) Item Select function Specification • CLK polarity selection Whether transmit data is output/input timing at the rising edge or falling edge of the transfer clock can be selected • LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected • Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register • Transfer clock output from multiple pins selection (UART1) UART1 transfer clock can be chosen by software to be output from one of the two pins set • Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. • TxD, RxD I/O polarity reverse (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed. 1-119 Mitsubishi microcomputers M16C / 62A Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 0 001 Symbol UiMR(i=0,1) Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE SLEP Address 03A016, 03A816 Bit name When reset 0016 Function b2 b1 b0 RW Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note) Internal/external clock select bit Invalid in clock synchronous serial I/O mode 0 (Must always be “0” in clock synchronous serial I/O mode) Note : Set the corresponding port direction register to “0”. UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 0 001 Symbol U2MR Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL Address 037816 Bit name When reset 0016 Function b2 b1 b0 RW Serial I/O mode select bit 0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note 2) Internal/external clock select bit Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note 1) 0 : No reverse 1 : Reverse Note 1: Usually set to “0”. Note 2: Set the corresponding port direction register to “0”. Figure 1.16.10. UARTi transmit/receive mode register in clock synchronous serial I/O mode 1-120 Mitsubishi microcomputers M16C / 62A Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.16.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.16.4. Input/output pin functions in clock synchronous serial I/O mode (when transfer clock output from multiple pins is not selected) Pin name Function Method of selection (Outputs dummy data when performing reception only) Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= “0” (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “1” Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” TxDi Serial data output (P63, P67, P70) Serial data input RxDi (P62, P66, P71) CLKi Transfer clock output (P61, P65, P72) Transfer clock input CTSi/RTSi CTS input (P60, P64, P73) RTS output Programmable I/O port 1-121 Mitsubishi microcomputers M16C / 62A Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Example of transmit timing (when internal clock is selected) Tc Transfer clock “1” “0” “1” “0” Transferred from UARTi transmit buffer register to UARTi transmit register “H” Data is set in UARTi transmit buffer register Transmit enable bit (TE) Transmit buffer empty flag (Tl) CTSi “L” TCLK Stopped pulsing because CTS = “H” Stopped pulsing because transfer enable bit = “0” CLKi TxDi Transmit register empty flag (TXEPT) “1” “0” D0 D 1 D2 D3 D4 D5 D6 D7 D0 D 1 D2 D3 D4 D5 D 6 D7 D 0 D1 D2 D 3 D 4 D 5 D6 D7 Transmit interrupt “1” request bit (IR) “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • Internal clock is selected. • CTS function is selected. • CLK polarity select bit = “0”. • Transmit interrupt cause select bit = “0”. Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi • Example of receive timing (when external clock is selected) Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) RTSi “1” “0” “1” “0” “1” “0” “H” “L” Dummy data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register 1 / fEXT Receive data is taken in CLKi RxDi Receive complete “1” flag (Rl) “0” Receive interrupt request bit (IR) “1” “0” D 0 D1 D 2 D3 D 4 D5 D6 D 7 Transferred from UARTi receive register to UARTi receive buffer register D0 D 1 D 2 D3 D4 D5 Read out from UARTi receive buffer register Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • External clock is selected. • RTS function is selected. • CLK polarity select bit = “0”. fEXT: frequency of external clock Meet the following conditions are met when the CLK input before data reception = “H” • Transmit enable bit “1” • Receive enable bit “1” • Dummy data write to UARTi transmit buffer register Figure 1.16.11. Typical transmit/receive timings in clock synchronous serial I/O mode 1-122 Mitsubishi microcomputers M16C / 62A Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (a) Polarity select function As shown in Figure 1.16.12, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows selection of the polarity of the transfer clock. • When CLK polarity select bit = “0” CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Note 1: The CLKi pin level when not transferring data is “H”. • When CLK polarity select bit = “1” CLKi TXDi R XD i D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Note 2: The CLKi pin level when not transferring data is “L”. Figure 1.16.12. Polarity of transfer clock (b) LSB first/MSB first select function As shown in Figure 1.16.13, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16, 037C16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”. • When transfer format select bit = “0” CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 LSB first D7 • When transfer format select bit = “1” CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 MSB first D0 Note: This applies when the CLK polarity select bit = “0”. Figure 1.16.13. Transfer format 1-123 Mitsubishi microcomputers M16C / 62A Group Clock synchronous serial I/O mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.16.14.) The multiple pins function is valid only when the internal clock is selected for UART1. Microcomputer TXD1 (P67) CLKS1 (P64) CLK1 (P65) IN CLK IN CLK Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode. Figure 1.16.14. The transfer clock output from the multiple pins function usage (d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. (e) Serial data logic switch function (UART2) When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure 1.16.15 shows the example of serial data logic switch timing. •When LSB first Transfer clock TxD2 “H” “L” “H” (no reverse) “L” D0 D1 D2 D3 D4 D5 D6 D7 TxD2 “H” (reverse) “L” D0 D1 D2 D3 D4 D5 D6 D7 Figure 1.16.15. Serial data logic switch timing 1-124 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode (2) Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 1.16.5 and 1.16.6 list the specifications of the UART mode. Figure 1.16.16 shows the UARTi transmit/receive mode register. Table 1.16.5. Specifications of UART Mode (1) Item Transfer data format Specification • Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected • Start bit: 1 bit • Parity bit: Odd, even, or nothing as selected • Stop bit: 1 bit or 2 bits as selected • When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32 • When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) : fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2) _______ _______ _______ _______ Transfer clock Transmission/reception control • CTS function, RTS function, CTS and RTS function invalid: selectable Transmission start condition • To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1” - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0” _______ _______ - When CTS function selected, CTS input level = “L” Reception start condition • To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1” - Start bit detection Interrupt request • When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed • When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection • Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out • Framing error This error occurs when the number of stop bits set is not detected • Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set • Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change. 1-125 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode Table 1.16.6. Specifications of UART Mode (2) Item Select function SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Specification • Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave microcomputers • Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. • TXD, RXD I/O polarity switch (UART2) This function is reversing TXD port output and RXD port input. All I/O data level is reversed. 1-126 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit / receive mode registers b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 03A016, 03A816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY Bit name Serial I/O mode select bit b2 b1 b0 Function 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected RW Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit Sleep select bit PRYE SLEP Note : Set the corresponding port direction register to “0”. UART2 transmit / receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2MR Address 037816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY Bit name Serial I/O mode select bit b2 b1 b0 Function 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long Must always be “0” 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse RW Internal / external clock select bit Stop bit length select bit Odd / even parity select bit Parity enable bit TxD, RxD I/O polarity reverse bit (Note) PRYE IOPOL Note: Usually set to “0”. Figure 1.16.16. UARTi transmit/receive mode register in UART mode 1-127 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.16.7 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the Nchannel open-drain is selected, this pin is in floating state.) Table 1.16.7. Input/output pin functions in UART mode Pin name Function TxDi Serial data output (P63, P67, P70) RxDi Serial data input (P62, P66, P71) CLKi Programmable I/O port (P61, P65, P72) Transfer clock input Method of selection Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= “0” (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0” Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1” Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = “0” (Do not set external clock for UART2) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0” Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = “0” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0” CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1” CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1” CTSi/RTSi CTS input (P60, P64, P73) RTS output Programmable I/O port 1-128 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) The transfer clock stops momentarily as CTS is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to “L”. Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UARTi transmit buffer register. Transferred from UARTi transmit buffer register to UARTi transmit register “H” CTSi “L” Start bit TxDi “1” Transmit register empty flag (TXEPT) “0” “1” “0” Parity bit P Stop bit SP Stopped pulsing because transmit enable bit = “0” ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Transmit interrupt request bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • CTS function is selected. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi • Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi “1” Transmit register empty flag (TXEPT) “0” “1” “0” Stop bit Stop bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP Transmit interrupt request bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is disabled. • Two stop bits. • CTS function is disabled. • Transmit interrupt cause select bit = “0”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Figure 1.16.17. Typical transmit timings in UART mode(UART0,UART1) 1-129 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UART2 transmit buffer register Note Transferred from UART2 transmit buffer register to UARTi transmit register Start bit ST D0 D1 TxD2 Parity bit D2 D 3 D4 D 5 D6 D7 P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP “1” Transmit register empty flag (TXEPT) “0” Transmit interrupt request bit (IR) “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Figure 1.16.18. Typical transmit timings in UART mode(UART2) 1-130 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) BRGi count source Receive enable bit RxDi “1” “0” Start bit Sampled “L” Receive data taken in Transfer clock Receive complete flag RTSi Receive interrupt request bit Reception triggered when transfer clock “1” is generated by falling edge of start bit “0” “H” “L” “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software The above timing applies to the following settings : •Parity is disabled. •One stop bit. •RTS function is selected. Transferred from UARTi receive register to UARTi receive buffer register Stop bit D0 D1 D7 Figure 1.16.19. Typical receive timing in UART mode (a) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”. (b) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 1.16.20 shows the example of timing for switching serial data logic. • When LSB first, parity enabled, one stop bit Transfer clock TxD2 (no reverse) “H” “L” “H” “L” “H” “L” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxD2 (reverse) ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST : Start bit P : Even parity SP : Stop bit Figure 1.16.20. Timing for switching serial data logic 1-131 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (c) TxD, RxD I/O polarity reverse function (UART2) This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for usual use. (d) Bus collision detection function (UART2) This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.16.21 shows the example of detection timing of a bus collision (in UART mode). Transfer clock “H” “L” TxD2 “H” “L” ST SP RxD2 Bus collision detection interrupt request signal Bus collision detection interrupt request bit “H” “L” “1” “0” “1” “0” ST SP ST : Start bit SP : Stop bit Figure 1.16.21. Detection timing of a bus collision (in UART mode) 1-132 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Clock-asynchronous serial I/O mode (used for the SIM interface) The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 1.16.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface). Table 1.16.8. Specifications of clock-asynchronous serial I/O mode (used for the SIM interface) Item Transfer data format Specification • Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”) • One stop bit (bit 4 of address 037816 = “0”) • With the direct format chosen Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively) Set data logic to “direct” (bit 6 of address 037D16 = “0”). Set transfer format to LSB (bit 7 of address 037C16 = “0”). • With the inverse format chosen Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively) Set data logic to “inverse” (bit 6 of address 037D16 = “1”) Set transfer format to MSB (bit 7 of address 037C16 = “1”) • With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32 (Do not set external clock) _______ _______ Transfer clock Transmission / reception control • Disable the CTS and RTS function (bit 4 of address 037C16 = “1”) Other settings • The sleep mode select function is not available for UART2 • Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”) Transmission start condition • To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = “1” - Transmit buffer empty flag (bit 1 of address 037D16) = “0” Reception start condition • To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = “1” - Detection of a start bit Interrupt request • When transmitting generation timing When data transmission from the UART2 transmit register is completed (bit 4 of address 037D16 = “1”) • When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection • Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2) • Framing error (see the specifications of clock-asynchronous serial I/O) • Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an “L” level is output from the TXD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs • The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART2 bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UART2 receive interrupt request bit does not change. 1-133 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Tc Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI) “1” “0” “1” “0” Data is set in UART2 transmit buffer register Note 1 Transferred from UART2 transmit buffer register to UART2 transmit register Start bit Parity bit D 1 D2 D3 D 4 D5 D 6 D 7 P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxD2 RxD2 ST D0 An “L” level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 2) “1” Transmit register empty flag (TXEPT) “0” “1” “0” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 The level is detected by the interrupt routine. P SP The level is detected by the interrupt routine. Transmit interrupt request bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Tc Transfer clock Receive enable bit (RE) “1” “0” Start bit Parity bit P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RxD2 TxD2 ST D0 D1 D2 D3 D4 D5 D6 D7 An “L” level returns from TxD2 due to the occurrence of a parity error. Signal conductor level (Note 2) Receive complete flag (RI) Receive interrupt request bit (IR) “1” “0” “1” “0” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Read to receive buffer Read to receive buffer Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “0”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note 2: Equal in waveform because TxD2 and RxD2 are connected. Figure 1.16.22. Typical transmit/receive timing in UART mode (used for the SIM interface) 1-134 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (a) Function for outputting a parity error signal During reception, with the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you can output an “L” level from the TXD2 pin when a parity error is detected. And during transmission, comparing with the case in which the error signal output enable bit (bit 7 of address 037D16) is assigned “0”, the transmission completion interrupt occurs in the half cycle later of the transfer clock. Therefore parity error signals can be detected by a transmission completion interrupt program. Figure 1.16.23 shows the output timing of the parity error signal. • LSB first Transfer clock RxD2 TxD2 Receive complete flag “H” “L” “H” “L” “H” “L” “1” “0” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Hi-Z ST : Start bit P : Even Parity SP : Stop bit Figure 1.16.23. Output timing of the parity error signal (b) Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and output from TxD2. Figure 1.16.24 shows the SIM interface format. Transfer clcck TxD2 (direct) TxD2 (inverse) D0 D1 D2 D3 D4 D5 D6 D7 P D7 D6 D5 D4 D3 D2 D1 D0 P P : Even parity Figure 1.16.24. SIM interface format 1-135 Mitsubishi microcomputers M16C / 62A Group Clock asynchronous serial I/O (UART) mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.16.25 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. Microcomputer SIM card TxD2 RxD2 Figure 1.16.25. Connecting the SIM interface 1-136 Mitsubishi microcomputers M16C / 62A Group UART2 Special Mode Register UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The UART2 special mode register (address 037716) is used to control UART2 in various ways. Figure 1.16.26 shows the UART2 special mode register. Bit 0 of the UART2 special mode register (037716) is used as the I2C mode select bit. Setting “1” in the I2C mode select bit (bit 0) goes the circuit to achieve the I2C bus (simplified I2C bus) interface effective. Table 1.16.9 shows the relation between the I2C mode select bit and respective control workings. Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode. UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR Address 037716 When reset 0016 Bit symbol IICM ABC BBS LSYN ABSCS I2C Bit name mode select bit Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : I2C mode 0 : Update per bit 1 : Update per byte 0 : STOP condition detected 1 : START condition detected Function (During UART mode) Must always be “0” Must always be “0” RW Arbitration lost detecting flag control bit Bus busy flag SCL L sync output enable bit Bus collision detect sampling clock select bit Must always be “0” (Note1) 0 : Disabled 1 : Enabled Must always be “0” Must always be “0” 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 0 : No auto clear function 1 : Auto clear at occurrence of bus collision ACSE Auto clear function select bit of transmit enable bit Transmit start condition select bit SDA digital delay select bit (Note 2, Note 3) Must always be “0” SSS Must always be “0” 0 : Analog delay output is selected 1 : Digital delay output is selected (must always be “0” when not using I 2 C mode) 0 : Ordinary 1 : Falling edge of RxD2 Must always be “0” SDDS Note 1: Nothing but “0” may be written. Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to “000”, with the analog delay circuit selected. Also, when SDDS = “0”, the U2SMR3 register cannot be read or written to. Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. UART2 special mode register 3 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR3 Address 037516 When reset Indeterminate (However, when SDDS = “1”, the initial value is “0016”) Function (I 2 C bus exclusive use register) RW Bit symbol Bit name Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1) DL0 SDA digital delay setup bit (Note 1, Note 2, Note 3, Note 4) b7 b6 b5 DL1 DL2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Analog delay is selected 1 : 1 to 2 cycle(s) of 1/f(XIN) 0 : 2 to 3 cycles of 1/f(XIN) 1 : 3 to 4 cycles of 1/f(XIN) 0 : 4 to 5 cycles of 1/f(XIN) 1 : 5 to 6 cycles of 1/f(XIN) 0 : 6 to 7 cycles of 1/f(XIN) 1 : 7 to 8 cycles of 1/f(XIN) Digital delay is selected Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit 7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3 (U2SMR3) is read after setting SDDS = “1”, the value is “0016”. When writing to UART2 special mode register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”, this register cannot be written to; when read, the value is indeterminate. Note 2: These bits are initialized to “000” when SDDS = “0”, with the analog delay circuit selected. After a reset, these bits are set to “000”, with the analog delay circuit selected. However, because these bits can be read only when SDDS = “1”, the value read from these bits when SDDS = “0” is indeterminate. Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. Note 4: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of delay increases by about 100 ns, so be sure to take this into account when using the device. Figure 1.16.26. UART2 special mode register 1-137 Mitsubishi microcomputers M16C / 62A Group UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P70 through P72 conforming to the simplified I 2C bus P70/TxD2/SDA Timer Selector UART2 I/O SDDS=0 or DL=000 IICM=1 (SDDS=0) or DL=000 (SDDS=1) UART2 Analog delay IICM=0 or DL≠000 (SDDS=1) Transmission register IICM=0 or IICM2=1 IICM=1 and IICM2=0 UART2 transmission/ NACK interrupt request To DMA0, DMA1 Digital delay (Divider) SDDS=1 and DL≠000 SDHI ALS DQ T Noize Filter Arbitration Timer IICM=1 Reception register IICM=0 UART2 IICM=0 or IICM2=1 To DMA0 UART2 reception/ACK interrupt request, DMA1 request Start condition detection S Q IICM=1 and IICM2=0 Stop condition detection Falling edge detection P71/RxD2/SCL L-synchronous output enabling bit R Q R Bus busy NACK D T Q I/O DQ Data bus T ACK (Port P7 1 output data latch) Selector Internal clock UART2 IICM=1 SWC2 Noize Filter Noize Filter 9th pulse IICM=1 CLK control Bus collision/start, stop condition detection interrupt request IICM=1 Bus collision detection UART2 IICM=0 External clock IICM=0 Falling edge of 9 bit SWC Port reading UART2 P72/CLK2 IICM=0 * With IICM set to 1, the port terminal is to be readable Selector even if 1 is assigned to P7 1 of the direction register. I/O Timer Figure 1.16.27. Functional block diagram for I2C mode Table 1.16.9. Features in I2C mode Function 1 2 3 4 5 6 7 8 9 Factor of interrupt number 10 (Note 2) Factor of interrupt number 15 (Note 2) Factor of interrupt number 16 (Note 2) UART2 transmission output delay P70 at the time when UART2 is in use P71 at the time when UART2 is in use P72 at the time when UART2 is in use DMA1 factor at the time when 1 1 0 1 is assigned to the DMA request factor selection bits Noise filter width Normal mode Bus collision detection UART2 transmission UART2 reception Not delayed TxD2 (output) RxD2 (input) CLK2 UART2 reception 15ns Reading the terminal when 0 is assigned to the direction register H level (when 0 is assigned to the CLK polarity select bit) I2C mode (Note 1) Start condition detection or stop condition detection No acknowledgment detection (NACK) Acknowledgment detection (ACK) Delayed SDA (input/output) (Note 3) SCL (input/output) P72 Acknowledgment detection (ACK) 50ns Reading the terminal regardless of the value of the direction register The value set in latch P70 when the port is selected 10 Reading P71 11 Initial value of UART2 output Note 1: Make the settings given below when I2C mode is in use. Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register. Disable the RTS/CTS function. Choose the MSB First function. Note 2: Follow the steps given below to switch from a factor to another. 1. Disable the interrupt of the corresponding number. 2. Switch from a factor to another. 3. Reset the interrupt request flag of the corresponding number. 4. Set an interrupt level of the corresponding number. Note 3: Set an initial value of SDA transmission output when serial I/O is invalid. 1-138 Mitsubishi microcomputers M16C / 62A Group UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.16.27 shows the functional block diagram for I2C mode. Setting “1” in the I2C mode select bit (IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock inputoutput terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output, so the SDA output changes after SCL fully goes to “L”. The SDA digital delay select bit (bit 7 at address 037716) can be used to select between analog delay and digital delay. When digital delay is selected, the amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using UART2 special mode register 3 (at address 037516). Delay circuit select conditions are shown in Table 1.16.10. Table 1.16.10. Delay circuit select conditions Register value Contents IICM Digital delay is selected SDDS 1 1 1 DL 001 to 111 000 (000) (000) When digital delay is selected, no analog delay is added. Only digital delay is effective. When DL is set to “000”, analog delay is selected no matter what value is set in SDDS. When SDDS is set to “0”, DL is initialized, so that DL =“000”. Analog delay is selected 1 0 No delay 0 0 When IICM = “0”, no delay circuit is selected. When IICM = “0”, however, always make sure SDDS = “0”. An attempt to read Port P71 (SCL) results in getting the terminal’s level regardless of the content of the port direction register. The initial value of SDA transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment nondetection interrupt, and acknowledgment detection interrupt respectively. The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the start condition detection, and set to “0” by the stop condition detection. The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the interrupt that occurs when SDA terminal’s level is detected already went to “L” at the 9th transmission clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA1 request factor select bits provides the means to start up the DMA transfer by the effect of acknowledgment detection. Bit 1 of the UART2 special mode register (037716) is used as the arbitration lost detecting flag control bit. Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 11 of the UART2 reception buffer register (037F16, 037E16), and “1” is set in this flag when nonconformity is detected. Use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to “1” at the falling edge of the 9th transmission clock. If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after completing the first byte acknowledge detect and before starting the next one byte transmission. Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting this bit to “1” goes the P71 data register to “0” in synchronization with the SCL terminal level going to “L”. 1-139 Mitsubishi microcomputers M16C / 62A Group UART2 Special Mode Register SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Some other functions added are explained here. Figure 1.16.28 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The bus collision detect interrupt occurs when the RXD2 level and TXD2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. If this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising edge of the transfer clock. Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus collision detect interrupt request bit (nonconformity). Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal. 1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register) 0: Rising edges of the transfer clock CLK TxD/RxD 1: Timer A0 overflow Timer A0 2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register) CLK TxD/RxD Bus collision detect interrupt request bit Transmit enable bit 3. Transmit start condition select bit (Bit 6 of the UART2 special mode register) 0: In normal state CLK TxD Enabling transmission With "1: falling edge of RxD2" selected CLK TxD RxD Figure 1.16.28. Some other functions added 1-140 Mitsubishi microcomputers M16C / 62A Group UART2 Special Mode Register 2 UART2 Special Mode Register 2 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART2 special mode register 2 (address 037616) is used to further control UART2 in I2C mode. Figure 1.16.29 shows the UART2 special mode register 2. UART2 special mode register 2 (I 2 C bus exclusive use register) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR2 Address 037616 When reset 0016 Bit symbol IICM2 CSC SWC ALS STAC SWC2 SDHI SHTC Bit name I 2C mode select bit 2 Clock-synchronous bit SCL wait output bit SDA output stop bit UART2 initialization bit SCL wait output bit 2 SDA output disable bit Start/stop condition control bit Function Refer to Table 1.16.11 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: UART2 clock 1: 0 output 0: Enabled 1: Disabled (high impedance) Set this bit to “1” in I2C mode (refer to Table 1.16.12) RW Figure 1.16.29. UART2 special mode register 2 1-141 Mitsubishi microcomputers M16C / 62A Group UART2 Special Mode Register 2 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I2C mode select bit 2. Table 1.16.11 shows the types of control to be changed by I2C mode select bit 2 when the I2C mode select bit is set to “1”. Table 1.16.12 shows the timing characteristics of detecting the start condition and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to “1” in I2C mode. Table 1.16.11. Functions changed by I2C mode select bit 2 Function 1 Factor of interrupt number 15 2 Factor of interrupt number 16 IICM2 = 0 No acknowledgment detection (NACK) Acknowledgment detection (ACK) IICM2 = 1 UART2 transmission (the rising edge of the final bit of the clock) UART2 reception (the falling edge of the final bit of the clock) UART2 reception (the falling edge of the final bit of the clock) The falling edge of the final bit of the reception clock The falling edge of the final bit of the reception clock 3 DMA1 factor at the time when 1 1 0 1 Acknowledgment detection (ACK) is assigned to the DMA request factor selection bits 4 Timing for transferring data from the UART2 reception shift register to the reception buffer. 5 Timing for generating a UART2 reception/ACK interrupt request The rising edge of the final bit of the reception clock The rising edge of the final bit of the reception clock Table 1.16.12. Timing characteristics of detecting the start condition and the stop condition (Note 1) 3 to 6 cycles < duration for setting-up (Note 2) 3 to 6 cycles < duration for holding (Note 2) Note 1 : When the start/stop condition control bit SHTC is “1” . Note 2 : “Cycles” is in terms of the input oscillation frequency f(XIN) of the main clock. Duration for setting up SCL SDA Duration for holding (Start condition) SDA (Stop condition) 1-142 Mitsubishi microcomputers M16C / 62A Group UART2 Special Mode Register 2 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P70 through P7 2 conforming to the simplified I 2C bus P70/TxD2/SDA Timer I/O Selector UART2 SDDS=0 or DL=000 IICM=1 (SDDS=0) or DL=000 (SDDS=1) Analog delay IICM=0 or DL≠000 (SDDS=1) To DMA0, DMA1 UART2 Transmission register IICM=0 or IICM2=1 IICM=1 and IICM2=0 UART2 transmission/ NACK interrupt request Digital delay (Divider) SDDS=1 and DL≠000 DQ T SDHI ALS Arbitration To DMA0 IICM=1 Reception register IICM=0 UART2 IICM=1 and IICM2=0 S Q Noize Filter Timer IICM=0 or IICM2=1 UART2 reception/ACK interrupt request, DMA1 request Start condition detection Stop condition detection Falling edge detection P71/RxD2/SCL I/O Q R R Bus busy NACK D T D T Q L-synchronous output enabling bit Q ACK Data bus Selector (Port P7 1 output data latch) Internal clock UART2 IICM=1 SWC2 9th pulse IICM=1 Bus collision/start, stop condition detection interrupt request Noize Filter Noize Filter IICM=1 Bus collision CLK control detection UART2 Falling edge of 9 bit SWC IICM=0 External clock IICM=0 UART2 Port reading * With IICM set to 1, the port terminal is to be readable P72/CLK2 IICM=0 Selector even if 1 is assigned to P7 1 of the direction register. I/O Timer Figure 1.16.30. Functional block diagram for I2C mode Functions available in I2C mode are shown in Figure 1.16.30 — a functional block diagram. Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting this bit to “1” causes an arbitration loss to occur, and the SDA pin turns to high-impedance state at the instant when the arbitration lost detecting flag is set to “1”. Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit. With this bit set to “1” at the time when the internal SCL is set to “H”, the internal SCL turns to “L” if the falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting within the “L” interval. When the internal SCL changes from “L” to “H” with the SCL pin set to “L”, stops counting the baud rate generator, and starts counting it again when the SCL pin turns to “H”. Due to this function, the UART2 transmission-reception clock becomes the logical product of the signal flowing through the internal SCL and that flowing through the SCL pin. This function operates over the period from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the ninth bit. To use this function, choose the internal clock for the transfer clock. Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to “1” causes the SCL pin to be fixed to “L” at the falling edge of the ninth bit of the clock. Setting this bit to “0” frees the output fixed to “L”. 1-143 Mitsubishi microcomputers M16C / 62A Group UART2 Special Mode Register 2 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit. Setting this bit to “1”, and when the start condition is detected, the microcomputer operates as follows. (1) The transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. This starts transmission by dealing with the clock entered next as the first bit. The UART2 output value, however, doesn’t change until the first bit data is output after the entrance of the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) The SCL wait output bit turns to “1”. This turns the SCL pin to “L” at the falling edge of the ninth bit of the clock. Starting to transmit/receive signals to/from UART2 using this function doesn’t change the value of the transmission buffer empty flag. To use this function, choose the external clock for the transfer clock. Bit 5 of the UART2 special mode register 2 (037616) is used as the SCL pin wait output bit 2. Setting this bit to “1” with the serial I/O specified allows the user to forcibly output an “1” from the SCL pin even if UART2 is in operation. Setting this bit to “0” frees the “L” output from the SCL pin, and the UART2 clock is input/output. Bit 6 of the UART2 special mode register 2 (037616) is used as the SDA output disable bit. Setting this bit to “1” forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detecting flag is turned on. 1-144 Mitsubishi microcomputers M16C / 62A Group S I/O3, 4 S I/O3, 4 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER S I/O3 and S I/O4 are exclusive clock-synchronous serial I/Os. Figure 1.16.31 shows the S I/O3, 4 block diagram, and Figure 1.16.32 shows the S I/O3, 4 related register. Table 1.16.13 shows the specifications of S I/O3, 4. f1 f8 f32 SMi1 SMi0 Data bus Synchronous circuit SMi3 SMi6 SMi6 1/2 1/(ni+1) Bit rate generator (8) S I/O counter i (3) P90/CLK3 (P95/CLK4) SMi2 SMi3 S I/Oi interrupt request P92/SOUT3 (P96/SOUT4) P91/SIN3 (P97/SIN4) SMi5 LSB MSB S I/Oi transmission/reception register (8) 8 Note: i = 3, 4. ni = A value set in the S I/O i bit rate generator (036316, 036716). Figure 1.16.31. S I/O3, 4 block diagram 1-145 Mitsubishi microcomputers M16C / 62A Group S I/O3, 4 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER S I/Oi control register (i = 3, 4) (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol SiC Bit symbol SMi0 SMi1 SMi2 SMi3 Address 036216, 036616 Bit name When reset 4016 Description b1 b0 RW Internal synchronous clock select bit 0 0 : Selecting f1 0 1 : Selecting f8 1 0 : Selecting f32 1 1 : Must not be set. 0 : SOUTi output 1 : SOUTi output disable(high impedance) 0 : Input-output port 1 : SOUTi output, CLK function SOUTi output disable bit S I/Oi port select bit (Note 2) Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. SMi5 SMi6 SMi7 Transfer direction select bit Synchronous clock select bit (Note 2) SOUTi initial value set bit 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock Effective when SMi3 = 0 0 : L output 1 : H output Note 1: Set “1” in bit 2 of the protection register (000A16) in advance to write to the S I/Oi control register (i = 3, 4). Note 2: When using the port as an input/output port by setting the SI/Oi port select bit (i = 3, 4) to “0”, be sure to set the sync clock select bit to “1”. SI/Oi bit rate generator (Note 1, 2) b7 b0 Symbol S3BRG S4BRG Address 036316 036716 When reset Indeterminate Indeterminate Values that can be set 0016 to FF16 RW Indeterminate Assuming that set value = n, BRGi divides the count source by n + 1 Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register. SI/Oi transmit/receive register (Note) b7 b0 Symbol S3TRR S4TRR Address 036016 036416 Indeterminate When reset Indeterminate Indeterminate RW Transmission/reception starts by writing data to this register. After transmission/reception finishes, reception data is input. Note: Write a value to this register while transmit/receive halts. Figure 1.16.32. S I/O3, 4 related register 1-146 Mitsubishi microcomputers M16C / 62A Group S I/O3, 4 Table 1.16.13. Specifications of S I/O3, 4 Item Transfer data format Transfer clock SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Conditions for transmission/ reception start Specifications • Transfer data length: 8 bits • With the internal clock selected (bit 6 of 036216, 036616 = “1”): f1/2(ni+1), f8/2(ni+1), f32/2(ni+1) (Note 1) • With the external clock selected (bit 6 of 036216, 036616 = 0):Input from the CLKi terminal (Note 2) • To start transmit/reception, the following requirements must be met: - Select the synchronous clock (use bit 6 of 036216, 036616). Select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 036216, 036616). - SOUTi initial value set bit (use bit 7 of 036216, 036616)= 1. - S I/Oi port select bit (bit 3 of 036216, 036616) = 1. - Select the transfer direction (use bit 5 of 036216, 036616) -Write transfer data to SI/Oi transmit/receive register (036016, 036416) • To use S I/Oi interrupts, the following requirements must be met: - Clear the SI/Oi interrupt request bit before writing transfer data to the SI/Oi transmit/receive register (bit 3 of 004916, 004816) = 0. • Rising edge of the last transfer clock. (Note 3) • LSB first or MSB first selection Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be selected. • Function for setting an SOUTi initial value selection When using an external clock for the transfer clock, the user can choose the SOUTi pin output level during a non-transfer time. For details on how to set, see Figure 1.16.33. • Unlike UART0–2, SI/Oi (i = 3, 4) is not divided for transfer register and buffer. Therefore, do not write the next transfer data to the SI/Oi transmit/receive register (addresses 036016, 036416) during a transfer. • When the internal clock is selected for the transfer clock, SOUTi holds the last data for a 1/2 transfer clock period after it finished transferring and then goes to a highimpedance state. However, if the transfer data is written to the SI/Oi transmit/ receive register (addresses 036016, 036416) during this time, SOUTi is placed in the high-impedance state immediately upon writing and the data hold time is thereby reduced. Interrupt request generation timing Select function Precaution Note 1: n is a value from 0016 through FF16 set in the S I/Oi bit rate generator (i = 3, 4). Note 2: With the external clock selected: • Before data can be written to the SI/Oi transmit/receive register (addresses 036016, 036416), the CLKi pin input must be in the high state. Also, before rewriting the SI/Oi Control Register (addresses 036216, 036616)’s bit 7 (SOUTi initial value set bit), make sure the CLKi pin input is held high. • The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it, so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected, automatically stops. Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the “H” state. 1-147 Mitsubishi microcomputers M16C / 62A Group S I/O3, 4 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Functions for setting an SOUTi initial value When using an external clock for the transfer clock, the SOUTi pin output level during a non-transfer time can be set to the high or the low state. Figure 1.16.33 shows the timing chart for setting an SOUTi initial value and how to set it. (Example) With “H” selected for SOUTi: S I/Oi port select bit SMi3 = 0 Signal written to the S I/Oi transmit/receive register SOUTi's initial value set bit (SMi7) SOUTi initial value select bit SMi7 = 1 (SOUTi: Internal “H” level) S I/Oi port select bit (SMi3) S I/Oi port select bit SMi3 = 0 1 (Port select: Normal port SOUTi) D0 SOUTi (internal) SOUTi terminal = “H” output Port output SOUTi terminal output D0 Initial value = “H” (Note) Signal written to the S I/Oi register =“L” “H” “L” (Falling edge) (i = 3, 4) Setting the SOUTi initial value to H Port selection (normal port SOUTi) Note: The set value is output only when the external clock has been selected. When initializing SOUTi, make sure the CLKi pin input is held “H” level. If the internal clock has been selected or if SOUT output disable has been set, this output goes to the high-impedance state. SOUTi terminal = Outputting stored data in the S I/Oi transmission/ reception register Figure 1.16.33. Timing chart for setting SOUTi’s initial value and how to set it S I/Oi operation timing Figure 1.16.34 shows the S I/Oi operation timing 1.5 cycle (max) SI/Oi internal clock Transfer clock (Note 1) Signal written to the S I/Oi transmit/receive register S I/Oi output SOUTi (i= 3, 4) "H" "L" "H" "L" "H" "L" Note2 "H" "L" "H" "L" Hiz D0 D1 D2 D3 D4 D5 D6 D7 Hiz S I/Oi input SINi (i= 3, 4) SI/Oi interrupt request (i= 3, 4) bit "1" "0" Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/Oi control register. (i=3,4) (No frequency division, 8-division frequency, 32-division frequency.) Note 2: With the internal clock selected for the transfer clock, the SOUTi (i = 3, 4) pin becomes to the high-impedance state after the transfer finishes. Note 3: Shown above is the case where the SOUTi (i = 3, 4) port select bit =“1”. Figure 1.16.34. S I/Oi operation timing chart 1-148 Mitsubishi microcomputers M16C / 62A Group A-D Converter A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.17.1 shows the performance of the A-D converter. Figure 1.17.1 shows the block diagram of the A-D converter, and Figures 1.17.2 and 1.17.3 show the A-D converter-related registers. Table 1.17.1. Performance of A-D converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVCC (VCC) Operating clock φAD (Note 2) VCC = 5V fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) VCC = 3V divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision VCC = 5V • Without sample and hold function ±3LSB • With sample and hold function (8-bit resolution) ±2LSB • With sample and hold function (10-bit resolution) AN0 to AN7 input : ±3LSB ANEX0 and ANEX1 input (including mode in which external operation amp is connected) : ±7LSB VCC = 3V • Without sample and hold function (8-bit resolution) ±2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1) A-D conversion start condition • Software trigger A-D conversion starts when the A-D conversion start flag changes to “1” • External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is “1” and the ___________ ADTRG/P97 input changes from “H” to “L” Conversion speed per pin • Without sample and hold function 8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles • With sample and hold function 8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Divide the frequency if f(XIN) exceeds 10MHZ, and make φAD frequency equal to or less than 10MHz. Without sample and hold function, set the φAD frequency to 250kHZ min. With the sample and hold function, set the φAD frequency to 1MHZ min. 1-149 Mitsubishi microcomputers M16C / 62A Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CKS1=1 fAD 1/2 1/2 CKS0=1 CKS1=0 φAD A-D conversion rate selection CKS0=0 V REF VCUT=0 Resistor ladder AV SS VCUT=1 Successive conversion register A-D control register 1 (address 03D716) A-D control register 0 (address 03D616) Addresses (03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16) A-D register 0(16) A-D register 1(16) A-D register 2(16) A-D register 3(16) A-D register 4(16) A-D register 5(16) A-D register 6(16) A-D register 7(16) VIN Comparator Vref Decoder Data bus high-order Data bus low-order AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 OPA1, OPA0 OPA1,OPA0=0,0 OPA1,OPA0=1,1 OPA0=1 0 0 1 1 0 : Normal operation 1 : ANEX0 0 : ANEX1 1 : External op-amp mode ANEX0 OPA1,OPA0=0,1 ANEX1 OPA1=1 Figure 1.17.1. Block diagram of A-D converter 1-150 Mitsubishi microcomputers M16C / 62A Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 Bit symbol CH0 Address 03D616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH1 CH2 MD0 MD1 TRG ADST CKS0 Trigger select bit A-D conversion start flag Frequency select bit 0 A-D operation mode select bit 0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 (Note 2) 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected (Note 2) Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A-D sweep pin select bit 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 When repeat sweep mode 1 is selected b1 b0 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 0 : Vref not connected 1 : Vref connected b7 b6 BITS CKS1 VCUT OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.17.2. A-D converter-related registers (1) 1-151 Mitsubishi microcomputers M16C / 62A Group A-D Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D control register 2 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON2 Address 03D416 When reset 0000XXX02 000 Bit symbol SMP Reserved bit Bit name A-D conversion method select bit Function 0 : Without sample and hold 1 : With sample and hold Must always be set to “0” RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D register i (b15) b7 (b8) b0 b7 Symbol ADi(i=0 to 7) Address When reset 03C016 to 03CF16 Indeterminate b0 Function Eight low-order bits of A-D conversion result • During 10-bit mode Two high-order bits of A-D conversion result • During 8-bit mode When read, the content is indeterminate Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. RW Figure 1.17.3. A-D converter-related registers (2) 1-152 Mitsubishi microcomputers M16C / 62A Group A-D Converter (1) One-shot mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 1.17.2 shows the specifications of one-shot mode. Figure 1.17.4 shows the A-D control register in one-shot mode. Table 1.17.2. One-shot mode specifications Item Function Start condition Stop condition Specification The pin selected by the analog input pin select bit is used for one A-D conversion Writing “1” to A-D conversion start flag • End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected) • Writing “0” to A-D conversion start flag End of A-D conversion One of AN0 to AN7, as selected Read A-D register corresponding to selected pin Interrupt request generation timing Input pin Reading of result of A-D converter A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol ADCON0 Bit symbol CH0 Address 03D616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH1 CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 (Note 2) (Note 2) 0 0 : One-shot mode 0 : Software trigger 1 : ADTRG trigger A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started Frequency select bit 0 0: fAD/4 is selected 1: fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0 OPA1 Address 03D716 Bit name When reset 0016 Function Invalid in one-shot mode RW A-D sweep pin select bit A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit1 Vref connect bit External op-amp connection mode bit Set to “0” when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.17.4. A-D conversion register in one-shot mode 1-153 Mitsubishi microcomputers M16C / 62A Group A-D Converter (2) Repeat mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.17.3 shows the specifications of repeat mode. Figure 1.17.5 shows the A-D control register in repeat mode. Table 1.17.3. Repeat mode specifications Item Function Star condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pin selected by the analog input pin select bit is used for repeated A-D conversion Writing “1” to A-D conversion start flag Writing “0” to A-D conversion start flag None generated One of AN0 to AN7, as selected Read A-D register corresponding to selected pin (at any time) A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 01 Symbol ADCON0 Bit symbol CH0 CH1 Address 03D616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 (Note 2) (Note 2) 0 1 : Repeat mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. A-D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 SCAN1 MD2 BITS CKS1 VCUT OPA0 OPA1 Address 03D716 Bit name When reset 0016 Function Invalid in repeat mode RW A-D sweep pin select bit A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit Set to “0” when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 1.17.5. A-D conversion register in repeat mode 1-154 Mitsubishi microcomputers M16C / 62A Group A-D Converter (3) Single sweep mode SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.17.4 shows the specifications of single sweep mode. Figure 1.17.6 shows the A-D control register in single sweep mode. Table 1.17.4. Single sweep mode specifications Item Specification Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Writing “1” to A-D converter start flag Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”, except when external trigger is selected) • Writing “0” to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converter Read A-D register corresponding to selected pin A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D616 Bit name When reset 00000XXX2 Function Invalid in single sweep mode RW Analog input pin select bit A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 b4 b3 1 0 : Single sweep mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A-D sweep pin select bit SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) Set to “0” when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 MD2 BITS CKS1 VCUT OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit. Figure 1.17.6. A-D conversion register in single sweep mode 1-155 Mitsubishi microcomputers M16C / 62A Group A-D Converter (4) Repeat sweep mode 0 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.17.5 shows the specifications of repeat sweep mode 0. Figure 1.17.7 shows the A-D control register in repeat sweep mode 0. Table 1.17.5. Repeat sweep mode 0 specifications Item Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pins selected by the A-D sweep pin select bit are used for repeat A-D conversion Writing “1” to A-D conversion start flag Writing “0” to A-D conversion start flag None generated AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Read A-D register corresponding to selected pin (at any time) A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol ADCON0 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Address 03D616 Bit name When reset 00000XXX2 Function Invalid in repeat sweep mode 0 RW Analog input pin select bit A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 b4 b3 1 1 : Repeat sweep mode 0 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A-D sweep pin select bit SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2) 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) Set to “0” when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 MD2 BITS CKS1 VCUT OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Neither “01” nor “10” can be selected with the external op-amp connection mode bit. Figure 1.17.7. A-D conversion register in repeat sweep mode 0 1-156 Mitsubishi microcomputers M16C / 62A Group A-D Converter (5) Repeat sweep mode 1 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.17.6 shows the specifications of repeat sweep mode 1. Figure 1.17.8 shows the A-D control register in repeat sweep mode 1. Table 1.17.6. Repeat sweep mode 1 specifications Item Function Specification All pins perform repeat A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Writing “1” to A-D conversion start flag Writing “0” to A-D conversion start flag None generated With emphasis on these pins ; AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Read A-D register corresponding to selected pin (at any time) Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter A-D control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol ADCON0 Address 03D616 When reset 00000XXX2 Bit symbol CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0 Bit name Analog input pin select bit Function Invalid in repeat sweep mode 1 RW A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0 b4 b3 1 1 : Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 1 1 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When repeat sweep mode 1 is selected b1 b0 RW A-D sweep pin select bit SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 BITS Set to “1” when this mode is selected 0 : 8-bit mode 1 : 10-bit mode CKS1 VCUT OPA0 OPA1 Frequency select bit 1 Vref connect bit External op-amp connection mode bit (Note 2) 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected b7 b6 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: Neither ‘01’ nor ‘10’ can be selected with the external op-amp connection mode bit. Figure 1.17.8. A-D conversion register in repeat sweep mode 1 1-157 Mitsubishi microcomputers M16C / 62A Group A-D Converter (a) Sample and hold SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φAD cycle is achieved with 8-bit resolution and 33 φAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used. (b) Extended analog input pins In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can also be converted from analog to digital. When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is converted from analog to digital. The result of conversion is stored in A-D register 0. When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is converted from analog to digital. The result of conversion is stored in A-D register 1. (c) External operation amp connection mode In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can be amplified together by just one operation amp and used as the input for A-D conversion. When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7 is output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the corresponding A-D register. The speed of A-D conversion depends on the response of the external operation amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.17.9 is an example of how to connect the pins in external operation amp mode. Resistor ladder Successive conversion register Analog input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANEX0 ANEX1 Comparator External op-amp Figure 1.17.9. Example of external op-amp connection mode 1-158 Mitsubishi microcomputers M16C / 62A Group D-A Converter D-A Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the target port to output mode if D-A conversion is to be performed. When the D-A output is enabled, the pullup function of the corresponding port is automatically disabled. Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register. V = VREF X n/ 256 (n = 0 to 255) VREF : reference voltage Table 1.18.1 lists the performance of the D-A converter. Figure 1.18.1 shows the block diagram of the D-A converter. Figure 1.18.2 shows the D-A control register. Figure 1.18.3 shows the D-A converter equivalent circuit. Table 1.18.1. Performance of D-A converter Item Conversion method Resolution Analog output pin Performance R-2R method 8 bits 2 channels Data bus low-order bits D-A register 0 (8) (Address 03D816) D-A0 output enable bit R-2R resistor ladder P93/DA0 D-A register 1 (8) (Address 03DA16) D-A1 output enable bit R-2R resistor ladder P94/DA1 Figure 1.18.1. Block diagram of D-A converter 1-159 Mitsubishi microcomputers M16C / 62A Group D-A Converter SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D-A control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DACON Bit symbol DA0E DA1E Address 03DC16 Bit name D-A0 output enable bit D-A1 output enable bit When reset 0016 Function 0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0” D-A register b7 b0 Symbol DAi (i = 0,1) Address 03D816, 03DA16 When reset Indeterminate Function Output value of D-A conversion RW RW Figure 1.18.2. D-A control register D-A0 output enable bit “0” R R R R R R R 2R DA0 “1” 2R MSB D-A register 0 2R 2R 2R 2R 2R 2R 2R LSB “0” “1” AVSS VREF Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16. Note 2: The same circuit as this is also used for D-A1. Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016 so that no current flows in the resistors Rs and 2Rs. Figure 1.18.3. D-A converter equivalent circuit 1-160 Mitsubishi microcomputers M16C / 62A Group CRC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CRC Calculation Circuit The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC code is set in a CRC data register each time one byte of data is transferred to a CRC input register after writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed in two machine cycles. Figure 1.19.1 shows the block diagram of the CRC circuit. Figure 1.19.2 shows the CRC-related registers. Figure 1.19.3 shows the calculation example using the CRC calculation circuit. Data bus high-order bits Data bus low-order bits Eight low-order bits CRC data register (16) Eight high-order bits (Addresses 03BD16, 03BC16) CRC code generating circuit x16 + x12 + x5 + 1 CRC input register (8) (Address 03BE16) Figure 1.19.1. Block diagram of CRC circuit CRC data register (b15) b7 (b8) b0 b7 b0 Symbol CRCD Address 03BD16, 03BC16 When reset Indeterminate Values that can be set 000016 to FFFF16 Function CRC calculation result output register RW CRC input register b7 b0 Symbo CRCIN Function Data input register Address 03BE16 When reset Indeterminate Values that can be set 0016 to FF16 RW Figure 1.19.2. CRC-related registers 1-161 Mitsubishi microcomputers M16C / 62A Group CRC SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER b15 b0 (1) Setting 000016 CRC data register CRCD [03BD16, 03BC16] b7 b0 (2) Setting 0116 CRC input register CRCIN [03BE16] 2 cycles After CRC calculation is complete b15 b0 118916 CRC data register CRCD [03BD16, 03BC16] Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. LSB 1000 1000 1 0001 0000 0010 0001 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 LSB 8 1 0000 0000 0000 0001 0001 1 0000 1 1000 0000 1000 0000 0 1 1000 MSB MSB Modulo-2 operation is operation that complies with the law given below. 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1 9 Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data. b7 b0 (3) Setting 2316 CRC input register CRCIN [03BE16] After CRC calculation is complete b15 b0 0A4116 CRC data register CRCD [03BD16, 03BC16] Stores CRC code Figure 1.19.3. Calculation example using the CRC calculation circuit 1-162 Mitsubishi microcomputers M16C / 62A Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Programmable I/O Ports There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is an input-only port and has no built-in pull-up resistance. Figures 1.20.1 to 1.20.4 show the programmable I/O ports. Figure 1.20.5 shows the I/O pins. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) Direction registers Figure 1.20.6 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. In memory expansion and microprocessor mode, the contents of corresponding direction register of pins _______ _______ _____ ________ ______ ________ _______ _______ __________ _________ A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Note: There is no direction register bit for P85. (2) Port registers Figure 1.20.7 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin. In memory expansion and microprocessor mode, the contents of corresponding port register of pins A0 to _______ ________ _____ ________ ______ ________ ________ _______ __________ _________ A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. (3) Pull-up control registers Figure 1.20.8 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. However, in memory expansion mode and microprocessor mode, the pull-up control register of P0 to P3, P40 to P43, and P5 is invalid. The contents of register can be changed, but the pull-up resistance is not connected. (4) Port control register Figure 1.20.9 shows the port control register. The bit 0 of port control register is used to read port P1 as follows: 0 : When port P1 is input port, port input level is read. When port P1 is output port , the contents of port P1 register is read. 1 : The contents of port P1 register is read always. This register is valid in the following: • External bus width is 8 bits in microprocessor mode or memory expansion mode. • Port P1 can be used as a port in multiplexed bus for the entire space. 1-163 Mitsubishi microcomputers M16C / 62A Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection Direction register P00 to P07, P20 to P27, P30 to P37, P40 to P47, P50 to P54, P56 Data bus Port latch (Note) Pull-up selection P10 to P14 Direction register Port P1 control register Data bus Port latch (Note) Pull-up selection P15 to P17 Direction register Port P1 control register Data bus Port latch (Note) Input to respective peripheral functions Pull-up selection P57, P60, P61, P64, P65, P72 to P76, P80, P81, P90, P92 Data bus Direction register "1" Output Port latch (Note) Input to respective peripheral functions Note :1 symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Figure 1.20.1. Programmable I/O ports (1) 1-164 Mitsubishi microcomputers M16C / 62A Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection P82 to P84 Direction register Data bus Port latch (Note1) Input to respective peripheral functions Pull-up selection Direction register P55, P62, P66, P77, P91, P97 Data bus Port latch (Note1) Input to respective peripheral functions Pull-up selection P63, P67 Direction register "1" Data bus Port latch Output (Note1) P85 Data bus NMI interrupt input (Note1) P70, P71 Direction register "1" Port latch Output (Note2) Data bus Input to respective peripheral functions Note :1 Note :2 symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. symbolizes a parasitic diode. Figure 1.20.2. Programmable I/O ports (2) 1-165 Mitsubishi microcomputers M16C / 62A Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P100 to P103 (inside dotted-line not included) P104 to P107 (inside dotted-line included) Pull-up selection Direction register Data bus Port latch (Note) Analog input Input to respective peripheral functions Pull-up selection D-A output enabled P93, P94 Direction register Data bus Port latch (Note) Input to respective peripheral functions Analog output D-A output enabled Pull-up selection Direction register P96 "1" Data bus Port latch Output (Note) Analog input Pull-up selection Direction register P95 "1" Data bus Port latch Output (Note) Input to respective peripheral functions Analog input Note : symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Figure 1.20.3. Programmable I/O ports (3) 1-166 Mitsubishi microcomputers M16C / 62A Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up selection Direction register P87 Data bus Port latch (Note) fc Rf Pull-up selection P86 Direction register "1" Data bus Port latch Output (Note) Rd Note : symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each port. Figure 1.20.4. Programmable I/O ports (4) BYTE BYTE signal input (Note 2) (Note 1) CNVSS CNVSS signal input (Note 2) (Note 1) RESET RESET signal input (Note 1) Note 1: symbolizes a parasitic diode. Do not apply a voltage higher than Vcc to each pin. Note 2: A parasitic diode on the VCC side is added to the mask ROM version. Do not apply a voltage higher than Vcc to each pin. Figure 1.20.5. I/O pins 1-167 Mitsubishi microcomputers M16C / 62A Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi direction register (Note 1, 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PDi (i = 0 to 10, except 8) Address 03E216, 03E316, 03E616, 03E716, 03EA16 03EB16, 03EE16, 03EF16, 03F316, 03F616 When reset 0016 Bit symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Bit name Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 10 except 8) RW Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port P9 direction register. Note 2: In memory expansion and microprocessor mode, the contents of corresponding port Pi direction register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Port P8 direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD8 Address 03F216 When reset 00X000002 Bit symbol PD8_0 PD8_1 PD8_2 PD8_3 Bit name Port P80 direction register Port P81 direction register Port P82 direction register Port P83 direction register Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) RW PD8_4 Port P84 direction register Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. PD8_6 PD8_7 Port P86 direction register Port P87 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Figure 1.20.6. Direction register 1-168 Mitsubishi microcomputers M16C / 62A Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi register (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Pi (i = 0 to 10, except 8) Address 03E016, 03E116, 03E416, 03E516, 03E816 03E916, 03EC16, 03ED16, 03F116, 03F416 When reset Indeterminate Indeterminate Bit symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Bit name Port Pi0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data (Note 1) (i = 0 to 10 except 8) RW Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance. Note 2: In memory expansion and microprocessor mode, the contents of corresponding port Pi register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Port P8 register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P8 Address 03F016 When reset Indeterminate Bit symbol P8_0 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6 P8_7 Bit name Port P80 register Port P81 register Port P82 register Port P83 register Port P84 register Port P85 register Port P86 register Port P87 register Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P85) 0 : “L” level data 1 : “H” level data RW Figure 1.20.7. Port register 1-169 Mitsubishi microcomputers M16C / 62A Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Bit symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 Address 03FC16 Bit name P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up P20 to P23 pull-up P24 to P27 pull-up P30 to P33 pull-up P34 to P37 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW Note : In memory expansion and microprocessor mode, the content of this register can be changed, but the pull-up resistance is not connected. Pull-up control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Bit symbol PU10 PU11 PU12 PU13 PU14 PU15 PU16 Address 03FD16 Bit name When reset 0016 (Note 2) Function RW P40 to P43 pull-up (Note 3) The corresponding port is pulled high with a pull-up resistor P44 to P47 pull-up 0 : Not pulled high P50 to P53 pull-up (Note 3) 1 : Pulled high P54 to P57 pull-up P60 to P63 pull-up P64 to P67 pull-up P72 to P73 pull-up (Note 1) PU17 P74 to P77 pull-up Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them. Note 2: When the VCC level is being impressed to the CNVSS terminal, this register becomes to 0216 when reset (PU11 becomes to “1”). Note 3: In memory expansion and microprocessor mode, the content of these bits can be changed, but the pull-up resistance is not connected. Pull-up control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR2 Bit symbol PU20 PU21 PU22 PU23 PU24 PU25 Address 03FE16 Bit name P80 to P83 pull-up P84 to P87 pull-up (Except P85) P90 to P93 pull-up P94 to P97 pull-up P100 to P103 pull-up P104 to P107 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Figure 1.20.8. Pull-up control register 1-170 Mitsubishi microcomputers M16C / 62A Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port control register b7 b6 b5 b4 b3 b2 b1 b0 Symbpl PCR Address 03FF16 When reset 0016 Bit symbol PCR0 Bit name Port P1 control register Function 0 : When input port, read port input level. When output port, read the contents of port P1 register. 1 : Read the contents of port P1 register though input/output port. RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Figure 1.20.9. Port control register 1-171 Mitsubishi microcomputers M16C / 62A Group Programmable I/O Port SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.20.1. Example connection of unused pins in single-chip mode Pin name Ports P0 to P10 (excluding P85) XOUT (Note) NMI AVCC AVSS, VREF, BYTE Connection After setting for input mode, connect every pin to VSS via a resistor (pull-down); or after setting for output mode, leave these pins open. Open Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS Note: With external clock input to XIN pin. Table 1.20.2. Example connection of unused pins in memory expansion mode and microprocessor mode Pin name Ports P6 to P10 (excluding P85) P45 / CS1 to P47 / CS3 Connection After setting for input mode, connect every pin to VSS via a resistor (pull-down); or after setting for output mode, leave these pins open. Set ports to input mode, set output enable bits of CS1 through CS3 to 0, and connect to Vcc via resistors (pull-up). Open BHE, ALE, HLDA, XOUT (Note 1), BCLK (Note 2) HOLD, RDY, NMI AVCC AVSS, VREF Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS Note 1: With external clock input to XIN pin. Note 2: When the BCLK output disable bit (bit 7 at address 000416) is set to “1”, connect to VCC via a resistor (pull-up). Microcomputer Port P0 to P10 (except for P85) (Input mode) · · · (Input mode) (Output mode) · · · Microcomputer Port P6 to P10 (except for P85) (Input mode) · · · (Input mode) (Output mode) · · · Open Open NMI XOUT AVCC BYTE AVSS VREF Open VCC Port P45 / CS1 to P47 / CS3 NMI BHE HLDA ALE XOUT BCLK (Note) Open VCC HOLD RDY AVCC AVSS VREF VSS VSS In single-chip mode In memory expansion mode or in microprocessor mode Note : When the BCLK output disable bit (bit 7 at address 000416) is set to “1”, connect to VCC via a resistor (pull-up). Figure 1.20.10. Example connection of unused pins 1-172 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Items to be submitted when ordering masked ROM version Please submit the following when ordering masked ROM products: (1) Mask ROM confirmation form (2) Mark specification sheet (3) ROM data : Floppy disks * *: 3.5-inch double-sided high-density disk (IBM format) is required per pattern. 1-173 Mitsubishi microcomputers M16C / 62A Group Electrical characteristics Table 1.23.1. Absolute maximum ratings Symbol Vcc AVcc Supply voltage Analog supply voltage RESET, CNVSS, BYTE, Input P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, VREF, XIN P70, P71 Output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37,P40 to P47, P50 to P57, SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Parameter Condition VCC=AVCC VCC=AVCC Rated value -0.3 to 6.5 -0.3 to 6.5 Unit V V -0.3 to Vcc+0.3 VI V -0.3 to 6.5 V VO P60 to P67,P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, XOUT P70, P71 Power dissipation Operating ambient temperature Storage temperature -0.3 to Vcc+0.3 V Pd Topr Tstg Topr=25 C -0.3 to 6.5 300 -20 to 85 / -40 to 85 (Note) -65 to 150 V mW C C Note : Specify a product of -40°C to 85°C to use it. 1-174 Mitsubishi microcomputers M16C / 62A Group Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.23.2. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3) unless otherwise specified) Standard Symbol Unit Parameter Typ. Min Max. Vcc AVcc Vss AVss Supply voltage Analog supply voltage Supply voltage Analog supply voltage HIGH input P31 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, voltage XIN, RESET, CNVSS, BYTE P70 , P71 P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion and microprocessor modes) 2.7 5.0 Vcc 0 0 5.5 V V V V V V V V V V V mA VIH 0.8Vcc 0.8Vcc 0.8Vcc 0.5Vcc 0 0 0 Vcc 6.5 Vcc Vcc 0.2Vcc 0.2Vcc 0.16Vcc -10.0 LOW input voltage VIL P31 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVSS, BYTE P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion and microprocessor modes) HIGH peak output I OH (peak) current HIGH average output current I OH (avg) LOW peak output I OL (peak) current I OL (avg) LOW average output current f (XIN) Main clock input oscillation frequency P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 Mask ROM version, Vcc=4.2V to 5.5V No wait Flash memory 5V Vcc=2.7V to 4.2V version (Note 5) -5.0 mA 10.0 5.0 0 0 0 0 32.768 16 mA mA MHz With wait Flash memory 5V version (Note 5) Mask ROM version, Vcc=4.2V to 5.5V Vcc=2.7V to 4.2V 7.33 X Vcc MHz -14.791 MHz 16 4 X Vcc -0.8 50 MHz kHz f (XcIN) Subclock oscillation frequency Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be 80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max. Note 3: Specify a product of -40°C to 85°C to use it. Note 4: Relationship between main clock oscillation frequency and supply voltage. Main clock input oscillation frequency (Mask ROM, Flash memory 5V version, No wait) Operating maximum frequency [MHZ] Main clock input oscillation frequency (Mask ROM, Flash memory 5V version, With wait) Operating maximum frequency [MHZ] 16.0 7.33 X VCC - 14.791MHZ 16.0 4 X VCC - 0.8MHZ 10.0 5.0 0.0 2.7 4.2 Supply voltage[V] 0.0 2.7 4.2 Supply voltage[V] 5.5 5.5 (BCLK: no division) (BCLK: no division) Note 5: Execute case without wait, program / erase of flash memory by VCC=4.2V to 5.5V and f(BCLK) ≤ 6.25 MHz. Execute case with wait, program / erase of flash memory by VCC=4.2V to 5.5V and f(BCLK) ≤ 12.5 MHz. 1-175 Mitsubishi microcomputers M16C / 62A Group Electrical characteristics (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Table 1.23.3. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 2.7V to 5.5V, Vss = AVSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 4) unless otherwise specified) Symbol Resolution Absolute accuracy Sample & hold function not available Sample & hold function available(10bit) Parameter Measuring condition VREF = VCC V REF = VCC = 5V AN0 to AN 7 input V REF =VCC ANEX0, ANEX1 input, = 5V External op-amp connection mode V REF = VCC = 5V Standard Min. Typ. Max. 10 ±3 ±3 ±7 ±2 ±2 40 Unit Bits LSB LSB LSB LSB LSB kΩ µs µs µs µs Sample & hold function available(8bit) Sample & hold function not available(8bit) V REF = VCC = 3V, Ø AD = fAD/2 RLADDER tCONV tCONV tCONV tSAMP VREF VIA Ladder resistance Conversion time(10bit), Sample & hold function available Conversion time(8bit), Sample & hold function available Conversion time(8bit), Sample & hold function not available VREF = VCC V REF = VCC = 5V, ØAD =10MHz V REF = VCC = 5V, ØAD =10MHz V REF = VCC = 3V, ØAD = fAD/2 = 5MHz 10 3.3 2.8 9.8 0.3 Sampling time Reference voltage Analog input voltage 2.7 0 VCC VREF V V Note 1: Do f(X IN) in range of main clock input oscillation frequency prescribed with recommended operating conditions of table 1.23.2. Divide the f AD if f(X IN) exceeds 10MHz, and make AD operation clock frequency (ØAD) equal to or lower than 10MHz. And divide the f AD if V CC is less than 4.2V, and make AD operation clock frequency (ØAD) equal to or lower than f AD/2. Note 2: A case without sample & hold function turn AD operation clock frequency (ØAD) into 250 kHz or more in addition to a limit of Note 1. A case with sample & hold function turn AD operation clock frequency (ØAD) into 1MHz or more in addition to a limit of Note 1. Note 3: Connect AV CC pin to V CC pin and apply the same electric potential. Note 4: Specify a product of -40°C to 85°C to use it. Table 1.23.4. D-A conversion characteristics (referenced to VCC = VREF = 2.7V to 5.5V, VSS = AVSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 2) unless otherwise specified) Symbol Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Measuring condition Min. Standard Typ. Max. 8 1.0 3 20 1.5 Unit Bits % µs kΩ mA (Note 1) Note 1: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when D-A register contents are not “00 16”, the current I VREF always flows even though Vref may have been set to be unconnected by the A-D control register. Note 2: Specify a product of -40°C to 85°C to use it. tsu RO IVREF 4 10 Table 1.23.5. Flash memory version electrical characteristics (referenced to VCC = 4.2V to 5.5V, at Topr =0 to 60oC unless otherwise specified) Parameter Page program time Block erase time Erase all unlocked blocks time Lock bit program time Min. Standard Typ. 6 50 50 X n (Note) 6 Max 120 600 600 X n (Note) 120 Unit ms ms ms ms Note : n denotes the number of block erases. 1-176 Mitsubishi microcomputers M16C / 62A Group Electrical characteristics (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Table 1.23.6. Electrical characteristics (referenced to VCC = 4.2V to 5.5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 2), f(XIN) = 16MHZ unless otherwise specified) Symbol VOH Parameter Measuring condition Standard Min Typ. Max. 3 .0 Unit HIGH output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IOH = -5mA P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 HIGH output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IOH = -200µA P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 HIGHPOWER IOH = -1mA HIGH output XOUT voltage LOWPOWER IOH = -0.5mA HIGH output voltage V VOH 4 .7 V 3 .0 3 .0 3.0 1 .6 V V VOH XCOUT HIGHPOWER LOWPOWER With no load applied With no load applied VOL LOW output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 LOW output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 LOW output voltage LOW output voltage Hysteresis IOL = 5mA 2 .0 V VOL IOL = 200µA 0.45 V VOL XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER IOL = 1mA IOL = 0.5mA With no load applied With no load applied 2 .0 2.0 0 0 V V VT+-VT- HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL, SDA, CLK0 to CLK4,TA2OUT to TA4OUT, KI0 to KI3, RxD0 to RxD2, SIN3, SIN4 0 .2 1.0 V VT+-VT- Hysteresis RESET 0 .2 1 .8 V II H HIGH input P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, current P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE LOW input current VI = 5 V 5 .0 µA I IL P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 VI = 0 V -5.0 µA RPULLUP Pull-up resistance VI = 0 V 30.0 50.0 167.0 kΩ RfXIN RfXCIN Feedback resistance XIN Feedback resistance XCIN RAM retention voltage In single-chip mode, the output pins are open and other pins are VSS When clock is stopped Mask ROM version 1.0 6 .0 MΩ MΩ V RAM 2 .0 30.0 32.5 V 50.0 50.0 f(XIN) = 16MHz Square wave, no division mA mA Flash memory 5V version Mask ROM version f(XIN) = 16MHz Square wave, no division f(XCIN) = 32kHz Square wave 90.0 90.0 2.2 25 28 10 (Topr = 25°C) 1.0 µA µA mA mA mA Flash memory 5V version Flash memory 5V version f(XCIN) = 32kHz Square wave, in RAM f(XCIN) = 32kHz Square wave, in flash memory Icc Power supply current Flash memory 5V version, Program Flash memory 5V version, Erase f(XIN) = 16MHz Square wave, Division by 4 f(XIN) = 16MHz Square wave, Division by 4 f(XCIN) = 32kHz When a WAIT instruction is executed (Note 1) 4.0 µA Topr = 25°C when clock is stopped Topr = 85°C when clock is stopped Note 1: With one timer operated using fC32. Note 2: Specify a product of -40°C to 85°C to use it. µA 20.0 1-177 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40°C to 85°C to use it. Table 1.23.7. External clock input Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Standard Min. Max. 62.5 25 25 15 15 Unit ns ns ns ns ns Table 1.23.8. Memory expansion and microprocessor modes Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(BCLK -RDY) th(BCLK-HOLD ) td(BCLK-HLDA ) Parameter Data input access time (no wait) Data input access time (with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time Standard Max. Min. (Note) (Note) (Note) 40 30 40 0 0 0 40 Unit ns ns ns ns ns ns ns ns ns ns Note: Calculated according to the BCLK frequency as follows: tac1(RD – DB) = tac2(RD – DB) = tac3(RD – DB) = 10 9 – 45 f(BCLK) X 2 3 X 10 – 45 f(BCLK) X 2 3 X 10 – 45 f(BCLK) X 2 9 9 [ns] [ns] [ns] 1-178 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40°C to 85°C to use it. Table 1.23.9. Timer A input (counter input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 100 40 40 Unit ns ns ns Table 1.23.10. Timer A input (gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 400 200 200 Unit ns ns ns Table 1.23.11. Timer A input (external trigger input in one-shot timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Min. Standard Max. Unit ns ns ns 200 100 100 Table 1.23.12. Timer A input (external trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 100 100 Unit ns ns Table 1.23.13. Timer A input (up/down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 2000 1000 1000 400 400 Unit ns ns ns ns ns 1-179 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Timing requirements (referenced to VCC = 5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40°C to 85°C to use it. Table 1.23.14. Timer B input (counter input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns Table 1.23.15. Timer B input (pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns Table 1.23.16. Timer B input (pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns Table 1.23.17. A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns Table 1.23.18. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Parameter Standard Min. 200 100 100 80 0 30 90 Max. Unit ns ns ns ns ns ns ns Table 1.23.19. External interrupt INTi inputs Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 250 250 Max. Unit ns ns 1-180 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15 = “1” unless otherwise specified) Table 1.23.20. Memory expansion mode and microprocessor mode (no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) 10 9 – 40 f(BCLK) X 2 Measuring condition Standard Min. Max. 25 4 0 0 25 4 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.23.1 –4 25 0 25 0 40 4 (Note1) 0 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. Note 3: Specify a product of -40°C to 85°C to use it. R DBi C P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30pF Figure 1.23.1. Port P0 to P10 measurement circuit 1-181 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15 = “1” unless otherwise specified) Table 1.23.21. Memory expansion mode and microprocessor mode (with wait, accessing external memory) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) 10 9 f(BCLK) Measuring condition Standard Min. Max. 25 4 0 0 25 4 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.23.1 –4 25 0 25 0 40 4 (Note1) 0 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = – 40 [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. Note 3: Specify a product of -40°C to 85°C to use it. R DBi C 1-182 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 2), CM15 = “1” unless otherwise specified) Table 1.23.22. Memory expansion mode and microprocessor mode (with wait, accessing external memory, multiplex bus area selected) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (Address standard) ALE signal output hold time (Adderss standard) Post-address RD signal output delay time Post-address WR signal output delay time Address output floating start time 10 9 f(BCLK) X 2 10 f(BCLK) X 2 10 9 f(BCLK) X 2 10 f(BCLK) X 2 10 X 3 – 40 f(BCLK) X 2 10 f(BCLK) X 2 10 9 – 25 f(BCLK) X 2 9 9 9 9 Measuring condition Standard Min. Max. 25 4 (Note1) (Note1) Unit ns ns ns ns 25 4 (Note1) (Note1) ns ns ns ns ns ns ns ns ns ns ns 25 Figure 1.23.1 0 25 0 40 4 (Note1) (Note1) 25 –4 (Note1) ns ns ns ns ns ns 30 0 0 8 ns ns Note 1: Calculated according to the BCLK frequency as follows: th(RD – AD) = [ns] th(WR – AD) = [ns] th(RD – CS) = [ns] th(WR – CS) = [ns] td(DB – WR) = [ns] th(WR – DB) = [ns] td(AD – ALE) = [ns] Note 2: Specify a product of -40°C to 85°C to use it. 1-183 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN–UP) tsu(UP–TIN) TAiIN input (When count on rising edge is selected) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C–Q) RxDi tw(INL) INTi input tw(INH) tsu(D–C) th(C–D) th(C–Q) Figure 1.23.2. VCC = 5V timing diagram (1) 1-184 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 5V Memory Expansion Mode and Microprocessor Mode (Valid only with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY–BCLK) th(BCLK–RDY) (Valid with or without wait) BCLK tsu(HOLD–BCLK) th(BCLK–HOLD) HOLD input HLDA output td(BCLK–HLDA) td(BCLK–HLDA) Hi–Z P0, P1, P2, P3, P4, P50 to P52 Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin and bit (PM06) of processor mode register 0 selects the function of ports P40 to P43. Measuring conditions : • VCC=5V • Input timing voltage : Determined with VIL=1.0V, VIH=4.0V • Output timing voltage : Determined with VOL=2.5V, VOH=2.5V Figure 1.23.3. VCC = 5V timing diagram (2) 1-185 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (With no wait) Read timing VCC = 5V BCLK td(BCLK–CS) 25ns.max th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min td(BCLK–AD) 25ns.max th(BCLK–AD) 4ns.min ADi BHE ALE RD td(BCLK–ALE) th(BCLK–ALE) 25ns.max –4ns.min th(RD–AD) 0ns.min td(BCLK–RD) 25ns.max th(BCLK–RD) 0ns.min tac1(RD–DB) DB Hi–Z tSU(DB–RD) 40ns.min th(RD–DB) 0ns.min Write timing BCLK td(BCLK–CS) 25ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE ALE td(BCLK–ALE) th(BCLK–ALE) 25ns.max th(WR–AD) 0ns.min th(BCLK–WR) 0ns.min –4ns.min td(BCLK–WR) WR,WRL, WRH DB 25ns.max td(BCLK–DB) 40ns.max Hi-Z td(DB–WR) th(BCLK–DB) 4ns.min th(WR–DB) 0ns.min (tcyc/2–40)ns.min Figure 1.23.4. VCC = 5V timing diagram (3) 1-186 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait) Read timing BCLK td(BCLK–CS) 25ns.max VCC = 5V th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min td(BCLK–AD) 25ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) 25ns.max th(RD–AD) 0ns.min th(BCLK–ALE) –4ns.min td(BCLK–RD) RD DB 25ns.max th(BCLK–RD) 0ns.min tac2(RD–DB) Hi–Z tSU(DB–RD) 40ns.min th(RD–DB) 0ns.min Write timing BCLK td(BCLK–CS) 25ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) 25ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) 25ns.max th(WR–AD) 0ns.min th(BCLK–ALE) –4ns.min td(BCLK–WR) WR,WRL, WRH DBi td(DB–WR) (tcyc–40)ns.min 25ns.max th(BCLK–WR) 0ns.min td(BCLK–DB) 40ns.max th(BCLK–DB) 4ns.min th(WR–DB) 0ns.min Measuring conditions : • VCC=5V • Input timing voltage : Determined with: VIL=0.8V, VIH=2.5V • Output timing voltage : Determined with: VOL=0.8V, VOH=2.0V Figure 1.23.5. VCC = 5V timing diagram (4) 1-187 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 5V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode Read timing BCLK td(BCLK–CS) 25ns.max tcyc VCC = 5V (When accessing external memory area with wait, and select multiplexed bus) th(RD–CS) (tcyc/2)ns.min th(BCLK–CS) 4ns.min CSi ADi /DBi td(AD–ALE) (tcyc/2-25)ns.min Address th(ALE–AD) 30ns.min Data input tac3(RD–DB) Address tdz(RD–AD) 8ns.max th(RD–DB) tSU(DB–RD) 40ns.min 0ns.min td(AD–RD) 0ns.min td(BCLK–AD) 25ns.max th(BCLK–AD) 4ns.min ADi BHE ALE RD td(BCLK–ALE) 25ns.max th(BCLK–ALE) –4ns.min th(RD–AD) (tcyc/2)ns.min th(BCLK–RD) 0ns.min 25ns.max td(BCLK–RD) Write timing BCLK td(BCLK–CS) 25ns.max tcyc th(BCLK–CS) th(WR–CS) (tcyc/2)ns.min 4ns.min CSi td(BCLK–DB) 40ns.max th(BCLK–DB) 4ns.min Data output Address ADi /DBi Address td(AD–ALE) (tcyc/2–25)ns.min td(DB–WR) (tcyc*3/2–40)ns.min th(WR–DB) (tcyc/2)ns.min th(BCLK–AD) 4ns.min td(BCLK–AD) 25ns.max ADi BHE ALE td(BCLK–ALE) 25ns.max th(BCLK–ALE) –4ns.min td(AD–WR) 0ns.min th(WR–AD) (tcyc/2)ns.min th(BCLK–WR) 0ns.min td(BCLK–WR) WR,WRL, WRH 25ns.max Measuring conditions : • VCC=5V • Input timing voltage : Determined with VIL=0.8V, VIH=2.5V • Output timing voltage : Determined with VOL=0.8V, VOH=2.0V Figure 1.23.6. VCC = 5V timing diagram (5) 1-188 Mitsubishi microcomputers M16C / 62A Group Electrical characteristics (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Table 1.23.23. Electrical characteristics (referenced to VCC = 2.7 to 3.3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 1), f(XIN) = 10MHZ (Note 2) with wait unless otherwise specified) Symbol VOH Parameter Measuring condition Standard Min Typ. Max. 2 .5 Unit V HIGH output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IOH = -1mA P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 HIGH output voltage XOUT HIGHPOWER LOWPOWER IOH = -0.1mA IOH = -50µA With no load applied With no load applied 2 .5 2.5 3 .0 1.6 V V VOH HIGH output voltage XCOUT HIGHPOWER LOWPOWER VOL LOW output P00 to P07 ,P10 to P17, P20 to P27, voltage P30 to P37, P40 to P47, P50 to P57, IO L = 1 m A P60 to P67, P70 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 HIGHPOWER 0 .5 V VOL LOW output voltage XOUT LOW output voltage XCOUT Hysteresis IOL = 0.1mA IO L = 5 0 µ A With no load applied With no load applied 0 0 0 .5 0 .5 V V LOWPOWER HIGHPOWER LOWPOWER VT+-VT- HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL, SDA CLK0 to CLK4,TA2OUT to TA4OUT, KI0 to KI3, RxD0 to RxD2, SIN3, SIN4 RESET 0.2 0.8 V VT+-VT- Hysteresis 0.2 1.8 V IIH HIGH input P00 to P07, P10 to P17, P20 to P27, current P30 to P37, P40 to P47 ,P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE LOW input current P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97 ,P100 to P107 VI = 3V 4.0 µA I IL VI = 0 V -4.0 µA R PULLUP Pull-up resistance VI = 0V 66.0 120.0 500.0 kΩ MΩ MΩ V mA mA µA µA µA R fXIN R fXCIN V RAM Feedback resistance XIN Feedback resistance XCIN RAM retention voltage In single-chip mode, the output pins are open and other pins are VSS When clock is stopped Mask ROM version Flash memory 5V version Mask ROM version Flash memory 5V version Flash memory 5V version f(XIN) = 10MHz Square wave, no division 3.0 10.0 2.0 8 .5 12.0 40.0 40.0 800 21.25 21.25 f(XIN) = 10MHz Square wave, no division f(XCIN) = 32kHz Square wave f(XCIN) = 32kHz Square wave, in RAM f(XCIN) = 32kHz Square wave, in flash memory Icc Power supply current f(XCIN) = 32kHz When a WAITinstruction is executed. Oscillation capacity High (Note 3) 2 .8 10 (Topr = 25°C) µA f(XCIN) = 32kHz When a WAIT instruction is executed. Oscillation capacity Low (Note 3) 0 .9 10 (Topr = 25°C) 1 .0 µA Topr = 25°C when clock is stopped Topr = 85°C when clock is stopped Note 1: Specify a product of -40°C to 85°C to use it. Note 2: 10 MHz for the mask ROM version and flash memory 5V version. Note 3: With one timer operated using fC32. µA 20.0 1-189 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40°C to 85°C to use it. Table 1.23.24. External clock input Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Mask ROM, Flash memory 5V version Mask ROM, Flash memory 5V version Mask ROM, Flash memory 5V version Standard Min. Max. 100 40 40 18 18 Unit ns ns ns ns ns Table 1.23.25. Memory expansion and microprocessor modes Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(BCLK -RDY) th(BCLK-HOLD ) td(BCLK-HLDA) Parameter Data input access time (no wait) Data input access time (with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time 10 9 – 90 f(BCLK) X 2 3 X 10 – 90 f(BCLK) X 2 3 X 10 9 – 90 f(BCLK) X 2 9 Standard Min. Max. (Note) (Note) (Note) 80 60 80 0 0 0 100 Unit ns ns ns ns ns ns ns ns ns ns Note: Calculated according to the BCLK frequency as follows: tac1(RD – DB) = tac2(RD – DB) = tac3(RD – DB) = [ns] [ns] [ns] 1-190 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40°C to 85°C to use it. Table 1.23.26. Timer A input (counter input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 150 60 60 Unit ns ns ns Table 1.23.27. Timer A input (gating input in timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns Table 1.23.28. Timer A input (external trigger input in one-shot timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 300 150 150 Unit ns ns ns Table 1.23.29. Timer A input (external trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 150 150 Unit ns ns Table 1.23.30. Timer A input (up/down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 3000 1500 1500 600 600 Unit ns ns ns ns ns 1-191 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Timing requirements (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40°C to 85°C to use it. Table 1.23.31. Timer B input (counter input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 150 60 60 300 160 160 Max. Unit ns ns ns ns ns ns Table 1.23.32. Timer B input (pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns Table 1.23.33. Timer B input (pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. Max. 600 300 300 Unit ns ns ns Table 1.23.34. A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1500 200 Max. Unit ns ns Table 1.23.35. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Parameter Standard Min. 300 150 150 160 0 50 90 Max. Unit ns ns ns ns ns ns ns Table 1.23.36. External interrupt INTi inputs Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 380 380 Max. Unit ns ns 1-192 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15=“1” unless otherwise specified) Table 1.23.37. Memory expansion and microprocessor modes (with no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Standard Min. Max. 60 4 0 0 60 4 60 —4 Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) Measuring condition Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.23.7 60 0 60 0 80 4 (Note1) 0 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = 10 f(BCLK) X 2 9 – 80 [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. Note 3: Specify a product of -40°C to 85°C to use it. R DBi C P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30pF Figure 1.23.7. Port P0 to P10 measurement circuit 1-193 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15=“1” unless otherwise specified) Table 1.23.38. Memory expansion and microprocessor modes (when accessing external memory area with wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) Measuring condition Figure 1.23.7 Standard Min. Max. 60 4 0 0 60 4 60 –4 60 0 60 0 80 4 (Note1) 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = 10 f(BCLK) 9 – 80 [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. Note 3: Specify a product of -40°C to 85°C to use it. R DBi C 1-194 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 2), CM15=“1” unless otherwise specified) Table 1.23.39. Memory expansion and microprocessor modes (when accessing external memory area with wait, and select multiplexed bus) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (Address standard) ALE signal output hold time(Address standard) Post-address RD signal output delay time Post-address WR signal output delay time Address output floating start time Measuring condition Standard Min. Max. 60 4 (Note1) (Note1) 60 4 (Note1) (Note1) 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.23.7 0 60 0 80 4 (Note1) (Note1) 60 –4 (Note1) 50 0 0 8 ns ns ns ns ns ns ns Note: Calculated according to the BCLK frequency as follows: th(RD – AD) = 10 f(BCLK) X 2 10 9 f(BCLK) X 2 th(RD – CS) = 10 f(BCLK) X 2 10 9 f(BCLK) X 2 td(DB – WR) = 10 X 3 – 80 f(BCLK) X 2 10 9 f(BCLK) X 2 td(AD – ALE) = 10 9 f(BCLK) X 2 – 45 [ns] 9 9 9 [ns] th(WR – AD) = [ns] [ns] th(WR – CS) = [ns] [ns] th(WR – DB) = [ns] Note 2: Specify a product of -40°C to 85°C to use it. 1-195 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) th(TIN–UP) tsu(UP–TIN) TAiIN input (When count on rising edge is selected) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C–Q) RxDi tw(INL) INTi input tw(INH) tsu(D–C) th(C–D) th(C–Q) Figure 1.23.8. VCC = 3V timing diagram (1) 1-196 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Memory Expansion Mode and Microprocessor Mode (Valid only with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY–BCLK) th(BCLK–RDY) (Valid with or without wait) BCLK tsu(HOLD–BCLK) HOLD input th(BCLK–HOLD) HLDA output td(BCLK–HLDA) P0, P1, P2, P3, P4, P50 to P52 Hi–Z td(BCLK–HLDA) Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin and bit (PM06) of processor mode register 0 selects the function of ports P40 to P43. Measuring conditions : • VCC=3V • Input timing voltage : Determined with VIL=0.6V, VIH=2.4V • Output timing voltage : Determined with VOL=1.5V, VOH=1.5V Figure 1.23.9. VCC = 3V timing diagram (2) 1-197 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (With no wait) Read timing BCLK td(BCLK–CS) 60ns.max VCC = 3V th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min td(BCLK–AD) 60ns.max th(BCLK–AD) 4ns.min ADi BHE ALE RD td(BCLK–ALE) th(BCLK–ALE) –4ns.min 60ns.max th(RD–AD) 0ns.min th(BCLK–RD) 0ns.min td(BCLK–RD) 60ns.max tac1(RD–DB) DB Hi–Z th(RD–DB) tSU(DB–RD) 80ns.min 0ns.min Write timing BCLK td(BCLK–CS) 60ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) 60ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) th(BCLK–ALE) 60ns.max –4ns.min th(WR–AD) 0ns.min WR,WRL, WRH DB td(BCLK–WR) 60ns.max td(BCLK–DB) 80ns.max Hi–Z th(BCLK–WR) 0ns.min th(BCLK–DB) 4ns.min th(WR–DB) td(DB–WR) (tcyc/2–80)ns.min 0ns.min Figure 1.23.10. VCC = 3V timing diagram (3) 1-198 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait) Read timing BCLK td(BCLK–CS) 60ns.max VCC = 3V th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min td(BCLK–AD) 60ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) 60ns.max th(RD–AD) 0ns.min th(BCLK–ALE) –4ns.min td(BCLK–RD) 60ns.max th(BCLK–RD) 0ns.min RD tac2(RD–DB) DB Hi–Z th(RD–DB) 0ns.min tSU(DB–RD) 80ns.min Write timing BCLK td(BCLK–CS) 60ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) 60ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) 60ns.max th(WR–AD) 0ns.min th(BCLK–ALE) –4ns.min td(BCLK–WR) 60ns.max th(BCLK–WR) 0ns.min WR,WRL, WRH DBi td(BCLK–DB) 80ns.max th(BCLK–DB) 4ns.min td(DB–WR) (tcyc–80)ns.min th(WR–DB) 0ns.min Measuring conditions : • VCC=3V • Input timing voltage : Determined with VIL=0.48V, VIH=1.5V • Output timing voltage : Determined with VOL=1.5V, VOH=1.5V Figure 1.23.11. VCC = 3V timing diagram (4) 1-199 Mitsubishi microcomputers M16C / 62A Group Timing (Vcc = 3V) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait, and select multiplexed bus) Read timing BCLK td(BCLK–CS) 60ns.max tcyc th(BCLK–CS) th(RD–CS) (tcyc/2)ns.min 4ns.min CSi td(AD–ALE) (tcyc/2–45)ns.min ADi /DBi Address tdz(RD–AD) 8ns.max Data input tac3(RD–DB) Address th(ALE–AD) 50ns.min th(RD–DB) tSU(DB–RD) 80ns.min 0ns.min td(BCLK–AD) ADi BHE ALE RD 60ns.max td(AD–RD) 0ns.min th(BCLK–AD) 4ns.min td(BCLK–ALE) 60ns.max th(BCLK–ALE) –4ns.min th(RD–AD) (tcyc/2)ns.min th(BCLK–RD) 0ns.min 60ns.max td(BCLK–RD) Write timing BCLK td(BCLK–CS) 60ns.max tcyc th(WR–CS) (tcyc/2)ns.min th(BCLK–CS) 4ns.min CSi td(BCLK–DB) 80ns.max th(BCLK–DB) 4ns.min Address ADi /DBi Address Data output td(AD–ALE) (tcyc/2–60)ns.min td(BCLK–AD) ADi BHE ALE 60ns.max td(DB–WR) (tcyc*3/2–80)ns.min th(WR–DB) (tcyc/2)ns.min th(BCLK–AD) 4ns.min td(BCLK–ALE) th(BCLK–ALE) 60ns.max –4ns.min td(AD–WR) 0ns.min th(WR–AD) (tcyc/2)ns.min th(BCLK–WR) 0ns.min td(BCLK–WR) WR,WRL, WRH 60ns.max Measuring conditions : • VCC=3V • Input timing voltage : Determined with VIL=0.48V,VIH=1.5V • Output timing voltage : Determined with VOL=1.5V,VOH=1.5V Figure 1.23.12. VCC = 3V timing diagram (5) 1-200 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-36B Mask ROM number Date : Note : Please complete all items marked ❈ . ) Receipt MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30620M8A-XXXFP/GP MASK ROM CONFIRMATION FORM Section head signature Supervisor signature ❈ Customer Date issued ❈1. Check sheet Date : Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : M30620M8A-XXXFP M30620M8A-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit) ❈2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30620M8A-XXXFP, submit the 100P6S mark specification sheet. For the M30620M8A-XXXGP, submit the 100P6Q mark specification sheet. ❈3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XIN) = MHZ Quartz-crystal oscillator Other ( ) Issuance signature Company name TEL ( Submitted by Supervisor 1-201 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-36B Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30620M8A-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XCIN) = kHZ Quartz-crystal oscillator Other ( ) (3) Which operation mode do you use? Single-chip mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) 2.4 2.7 3.0 3.3 3.5 3.8 4.0 4.2 4.5 4.7 5.0 5.3 5.5 5.7 Memory expansion mode (V) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. ❈4. Special item (Indicate none if there is not specified item) 1-202 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-37B Mask ROM number Date : Note : Please complete all items marked ❈ . ) Receipt MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30620MAA-XXXFP/GP MASK ROM CONFIRMATION FORM Section head signature Supervisor signature ❈ Customer Date issued ❈1. Check sheet Date : Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : M30620MAA-XXXFP M30620MAA-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit) ❈2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30620MAA-XXXFP, submit the 100P6S mark specification sheet. For the M30620MAA-XXXGP, submit the 100P6Q mark specification sheet. ❈3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XIN) = MHZ Quartz-crystal oscillator Other ( ) Issuance signature Company name TEL ( Submitted by Supervisor 1-203 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-37B Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30620MAA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XCIN) = kHZ Quartz-crystal oscillator Other ( ) (3) Which operation mode do you use? Single-chip mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) 2.4 2.7 3.0 3.3 3.5 3.8 4.0 4.2 4.5 4.7 5.0 5.3 5.5 5.7 Memory expansion mode (V) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. ❈4. Special item (Indicate none if there is not specified item) 1-204 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-28B Mask ROM number Date : Note : Please complete all items marked ❈ . ) Receipt MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30620MCA-XXXFP/GP MASK ROM CONFIRMATION FORM Section head signature Supervisor signature ❈ Customer Date issued ❈1. Check sheet Date : Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : M30620MCA-XXXFP M30620MCA-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit) ❈2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30620MCA-XXXFP, submit the 100P6S mark specification sheet. For the M30620MCA-XXXGP, submit the 100P6Q mark specification sheet. ❈3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XIN) = MHZ Quartz-crystal oscillator Other ( ) Issuance signature Company name TEL ( Submitted by Supervisor 1-205 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-28B Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30620MCA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XCIN) = kHZ Quartz-crystal oscillator Other ( ) (3) Which operation mode do you use? Single-chip mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) 2.4 2.7 3.0 3.3 3.5 3.8 4.0 4.2 4.5 4.7 5.0 5.3 5.5 5.7 Memory expansion mode (V) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. ❈4. Special item (Indicate none if there is not specified item) 1-206 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-40B Mask ROM number Date : Note : Please complete all items marked ❈ . ) Receipt MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30622M4A-XXXFP/GP MASK ROM CONFIRMATION FORM Section head signature Supervisor signature ❈ Customer Date issued ❈1. Check sheet Date : Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : M30622M4A-XXXFP M30622M4A-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit) ❈2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30622M4A-XXXFP, submit the 100P6S mark specification sheet. For the M30622M4A-XXXGP, submit the 100P6Q mark specification sheet. ❈3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XIN) = MHZ Quartz-crystal oscillator Other ( ) Issuance signature Company name TEL ( Submitted by Supervisor 1-207 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-40B Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30622M4A-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XCIN) = kHZ Quartz-crystal oscillator Other ( ) (3) Which operation mode do you use? Single-chip mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) 2.4 2.7 3.0 3.3 3.5 3.8 4.0 4.2 4.5 4.7 5.0 5.3 5.5 5.7 Memory expansion mode (V) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. ❈4. Special item (Indicate none if there is not specified item) 1-208 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-38B Mask ROM number Date : Note : Please complete all items marked ❈ . ) Receipt MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30622M8A-XXXFP/GP MASK ROM CONFIRMATION FORM Section head signature Supervisor signature ❈ Customer Date issued ❈1. Check sheet Date : Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : M30622M8A-XXXFP M30622M8A-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit) ❈2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30622M8A-XXXFP, submit the 100P6S mark specification sheet. For the M30622M8A-XXXGP, submit the 100P6Q mark specification sheet. ❈3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XIN) = MHZ Quartz-crystal oscillator Other ( ) Issuance signature Company name TEL ( Submitted by Supervisor 1-209 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-38B Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30622M8A-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XCIN) = kHZ Quartz-crystal oscillator Other ( ) (3) Which operation mode do you use? Single-chip mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) 2.4 2.7 3.0 3.3 3.5 3.8 4.0 4.2 4.5 4.7 5.0 5.3 5.5 5.7 Memory expansion mode (V) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. ❈4. Special item (Indicate none if there is not specified item) 1-210 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-34B Mask ROM number Date : Note : Please complete all items marked ❈ . ) Receipt MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30622MAA-XXXFP/GP MASK ROM CONFIRMATION FORM Section head signature Supervisor signature ❈ Customer Date issued ❈1. Check sheet Date : Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : M30622MAA-XXXFP M30622MAA-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit) ❈2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30622MAA-XXXFP, submit the 100P6S mark specification sheet. For the M30622MAA-XXXGP, submit the 100P6Q mark specification sheet. ❈3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XIN) = MHZ Quartz-crystal oscillator Other ( ) Issuance signature Company name TEL ( Submitted by Supervisor 1-211 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-34B Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30622MAA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XCIN) = kHZ Quartz-crystal oscillator Other ( ) (3) Which operation mode do you use? Single-chip mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) 2.4 2.7 3.0 3.3 3.5 3.8 4.0 4.2 4.5 4.7 5.0 5.3 5.5 5.7 Memory expansion mode (V) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. ❈4. Special item (Indicate none if there is not specified item) 1-212 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-39B Mask ROM number Date : Note : Please complete all items marked ❈ . ) Receipt MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30622MCA-XXXFP/GP MASK ROM CONFIRMATION FORM Section head signature Supervisor signature ❈ Customer Date issued ❈1. Check sheet Date : Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : M30622MCA-XXXFP M30622MCA-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit) ❈2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30622MCA-XXXFP, submit the 100P6S mark specification sheet. For the M30622MCA-XXXGP, submit the 100P6Q mark specification sheet. ❈3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XIN) = MHZ Quartz-crystal oscillator Other ( ) Issuance signature Company name TEL ( Submitted by Supervisor 1-213 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-39B Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30622MCA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XCIN) = kHZ Quartz-crystal oscillator Other ( ) (3) Which operation mode do you use? Single-chip mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) 2.4 2.7 3.0 3.3 3.5 3.8 4.0 4.2 4.5 4.7 5.0 5.3 5.5 5.7 Memory expansion mode (V) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. ❈4. Special item (Indicate none if there is not specified item) 1-214 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-30B Mask ROM number Date : Note : Please complete all items marked ❈ . ) Receipt MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30624MGA-XXXFP/GP MASK ROM CONFIRMATION FORM Section head signature Supervisor signature ❈ Customer Date issued ❈1. Check sheet Date : Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : M30624MGA-XXXFP M30624MGA-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit) ❈2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30624MGA-XXXFP, submit the 100P6S mark specification sheet. For the M30624MGA-XXXGP, submit the 100P6Q mark specification sheet. ❈3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XIN) = MHZ Quartz-crystal oscillator Other ( ) Issuance signature Company name TEL ( Submitted by Supervisor 1-215 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-30B Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30624MGA-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XCIN) = kHZ Quartz-crystal oscillator Other ( ) (3) Which operation mode do you use? Single-chip mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) 2.4 2.7 3.0 3.3 3.5 3.8 4.0 4.2 4.5 4.7 5.0 5.3 5.5 5.7 Memory expansion mode (V) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. ❈4. Special item (Indicate none if there is not specified item) 1-216 Mitsubishi microcomputers M16C / 62A Group Description (Flash Memory Version) Outline Performance SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.25.1 shows the outline performance of the M16C/62A (flash memory version). Table 1.25.1. Outline performance of the M16C/62A (flash memory version) Item Flash memory operation mode Erase block division User ROM area Boot ROM area Performance Three modes (parallel I/O, standard serial I/O, CPU rewrite) See Figure 1.25.1 One division (8 Kbytes) (Note) In units of pages (in units of 256 bytes) Collective erase/block erase Program/erase control by software command Protected for each block by lock bit 8 commands 100 times 10 years Parallel I/O and standard serial I/O modes are supported. Program method Erase method Program/erase control method Protect method Number of commands Program/erase count Data retantion ROM code protect Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode. 1-217 Mitsubishi microcomputers M16C / 62A Group Description (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Flash Memory The M16C/62A (flash memory version) contains the flash memory that can be rewritten with a single voltage. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. The flash memory is divided into several blocks as shown in Figure 1.25.1, so that memory can be erased one block at a time. Each block has a lock bit to enable or disable execution of an erase or program operation, allowing for data in each block to be protected. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode. 0C000016 Block 6 : 64K byte 0D000016 Block 5 : 64K byte 0E000016 Block 4 : 64K byte Note 1: The boot ROM area can be rewritten in only parallel input/output mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use the maximum address in the block that is an even address. 0F000016 Flash memory size 256Kbytes 128Kbytes Flash memory start address 0C000016 0E000016 0F800016 0FA00016 0FC00016 0FFFFF16 Block 3 : 32K byte Block 2 : 8K byte Block 1 : 8K byte Block 0 : 16K byte User ROM area 0FE00016 0FFFFF16 8K byte Boot ROM area Figure 1.25.1. Block diagram of flash memory version 1-218 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER CPU Rewrite Mode In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the user ROM area shown in Figure 1.25.1 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM area and each block area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to any area other than the internal flash memory before it can be executed. Microcomputer Mode and Boot Mode The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 1.25.1 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the user ROM area. When the microcomputer is reset by pulling the P55 pin low, the CNVSS pin high, and the P50 pin high, the CPU starts operating using the control program in the boot ROM area. This mode is called the “boot” mode. The control program in the boot ROM area can also be used to rewrite the user ROM area. Block Address Block addresses refer to the maximum even address of each block. These addresses are used in the block erase command, lock bit program command, and read lock status command. 1-219 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Outline Performance (CPU Rewrite Mode) In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. Operations must be executed from a memory other than the internal flash memory, such as the internal RAM. When the CPU rewrite mode select bit (bit 1 at address 03B716) is set to “1”, transition to CPU rewrite mode occurs and software commands can be accepted. In the CPU rewrite mode, write to and read from software commands and data into even-numbered address (“0” for byte address A0) in 16-bit units. Always write 8-bit software commands into even-numbered address. Commands are ignored with odd-numbered addresses. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 1.26.1 shows the flash memory control register 0 and the flash memory control register 1. _____ Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is “0”. Otherwise, it is “1”. Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is entered by setting this bit to “1”, so that software commands become acceptable. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area other _______ than the internal flash memory. Also only when NMI pin is "H" level. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. The bit can be set to “0” by only writing a “0” . Bit 2 of the flash memory control register 0 is a lock bit disable select bit. By setting this bit to “1”, it is possible to disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable select bit only disables the lock bit function; it does not change the lock data bit value. However, if an erase operation is performed when this bit =“1”, the lock bit data that is “0” (locked) is set to “1” (unlocked) after erasure. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. This bit can be manipulated only when the CPU rewrite mode select bit = “1”. Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control circuit. To release the reset, it is necessary to set this bit to “0”. Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot mode. If this bit is set to “1” in boot mode, the area to be accessed is switched from the boot ROM area to the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to “1”. Note that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of whether the CPU rewrite mode is on or off. Write to this bit only when executing out of an area other than the internal flash memory. Bit 3 of the flash memory control register 1 turns power supply to the internal flash memory on/off. When this bit is set to “1”, power is not supplied to the internal flash memory, thus power consumption can be reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit to “1”, it is necessary to write “0” and then write “1” in succession. Use this bit mainly in the low speed mode (when XCIN is the count source of BCLK). When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut off. It is reconnected automatically when CPU operation is restored. Therefore, it is not particularly necessary to set flash memory control register 1. 1-220 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Figure 1.26.2 shows a flowchart for setting/releasing the CPU rewrite mode. Figure 1.26.3 shows a flowchart for shifting to the low speed mode. Always perform operation as indicated in these flowcharts. Flash memory control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR0 Bit symbol Address 03B716 When reset XX0000012 0 Bit name RY/BY status flag Function 0: Busy (being written or erased) 1: Ready 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) 0: Block lock by lock bit data is enabled 1: Block lock by lock bit data is disabled 0: Normal operation 1: Reset Must always be set to “0” RW RW FMR00 FMR01 CPU rewrite mode select bit (Note 1) FMR02 Lock bit disable select bit (Note 2) FMR03 Flash memory reset bit (Note 3) Reserved bit FMR05 User ROM area select bit ( Note 4) (Effective in only boot mode) 0: Boot ROM area is accessed 1: User ROM area is accessed Nothing is assigned. When write, set "0". When read, values are indeterminate. Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of an area other than the internal flash memory. Also only when NMI pin is “H” level. Clear this bit to “0” after read array command. Note 2: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession when the CPU rewrite mode select bit = “1”. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently after setting it to 1 (reset). Note 4: Write to this bit only when executing out of an area other than the internal flash memory. Flash memory control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol FMR1 Bit symbol Address 03B616 When reset XXXX0XXX2 0 0 0 0 0 0 0 Bit name Function Must always be set to “0” RW RW Reserved bit FMR13 Flash memory power supply-OFF bit (Note) 0: Flash memory power supply is connected 1: Flash memory power supply-off Must always be set to “0” Reserved bit Note : For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. During parallel I/O mode,programming,erase or read of flash memory is not controlled by this bit,only by external pins. Write to this bit only when executing out of an area other than the internal flash memory. Figure 1.26.1. Flash memory control registers 1-221 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Program in ROM Start Program in RAM *1 Single-chip mode, memory expansion mode, or boot mode (Boot mode only) Set user ROM area select bit to “1” Set processor mode register (Note 1) Set CPU rewrite mode select bit to “1” (by writing “0” and then “1” in succession)(Note 2) Transfer CPU rewrite mode control program to internal RAM Using software command execute erase, program, or other operation (Set lock bit disable bit as required) Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Execute read array command or reset flash memory by setting flash memory reset bit (by writing “1” and then “0” in succession) (Note 3) *1 Write “0” to CPU rewrite mode select bit (Boot mode only) Write “0” to user ROM area select bit (Note 4) End Note 1: During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bits (bit 6 at address 000616 and bits 6 and 7 at address 000716): 6.25 MHz or less when wait bit (bit 7 at address 000516) = “0” (without internal access wait state) 12.5 MHz or less when wait bit (bit 7 at address 000516) = “1” (with internal access wait state) Note 2: For CPU rewrite mode select bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of an area other than the internal flash memory. Also only when NMI pin is “H” level. Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. Note 4: “1” can be set. However, when this bit is “1”, user ROM area is accessed. Figure 1.26.2. CPU rewrite mode set/reset flowchart Program in ROM Start Program in RAM *1 Transfer the program to be executed in the low speed mode, to the internal RAM. Set flash memory power supply-OFF bit to “1” (by writing “0” and then “1” in succession)(Note 1) Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM) Switch the count source of BCLK. XIN stop. (Note 2) *1 Process of low speed mode XIN oscillating Wait until the XIN has stabilized Switch the count source of BCLK (Note 2) Set flash memory power supply-OFF bit to “0” Wait time until the internal circuit stabilizes (Set NOP instruction about twice) End Note 1: For flash memory power supply-OFF bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 2: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Figure 1.26.3. Shifting to the low speed mode flowchart 1-222 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Precautions on CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716): 6.25 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state) 12.5 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state) (2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use The address match interrupt cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be _______ used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts can be used because the flash memory conterol register 0 and 1 is forcibly initialized and return to normal mode when each interrupt occurs. But it is needed that the jump addresses for each interrupt are set in the fixed vector table and there is an interrupt program. Since the rewrite operation is halted when _______ the NMI and watchdog timer interrupts occur, it is needed that CPU rewriting mode select bit is set to “1” and the erase/program operation is performed over again. (4) Internal reserved area expansion bit (Bit 3 at address 000516) The reserved area of the internal memory can be changed by using the internal reserved area expansion bit (bit 3 at address 000516). However, if the CPU rewrite mode select bit (bit 1 at address 03B716) is set to 1, the internal reserved area expansion bit (bit 3 at address 000516) also is set to 1 automatically. Similarly, if the CPU rewrite mode select bit (bit 1 at address 03B716) is set to 0, the internal reserved area expansion bit (bit 3 at address 000516) also is set to 0 automatically. The precautions above apply to the products which RAM size is over 15 Kbytes or flash memory size is over 192 Kbytes. (5) Reset Reset input is always accepted. After a reset, the addresses 0C000016 through 0CFFFF16 are made a reserved area and cannot be accessed. Therefore, if your product has this area in the user ROM area, do not write any address of this area to the reset vector. This area is made accessible by changing the internal reserved area expansion bit (bit 3 at address 000516) in a program. (6) Access disable Write CPU rewrite mode select bit, flash memory power supply-OFF bit and user ROM area select bit only when executing out of an area other than the internal flash memory. (7) How to access For CPU rewrite mode select bit, lock bit disable select bit, and flash memory power supply-OFF bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Write CPU rewrite mode select bit only when executing out of an area other than the internal flash _______ memory. Also only when NMI pin is “H” level. 1-223 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (8) Writing in the user ROM area If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode, those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O mode to rewrite these blocks. (9) Using the lock bit To use the CPU rewrite mode, use a boot program that can set and cancel the lock command. 1-224 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Software Commands Table 1.26.1 lists the software commands available with the M16C/62A (flash memory version). After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored. The content of each software command is explained below. Table 1.26.1. List of software commands (CPU rewrite mode) First bus cycle Command Read array Read status register Clear status register Page program Block erase Erase all unlock block Lock bit program Read lock bit status (Note 3) Second bus cycle Mode Address Data (D0 to D7) Third bus cycle Data Mode Address (D0 to D7) Mode Write Write Write Write Write Write Write Write Address X (Note 6) Data (D0 to D7) FF16 7016 5016 4116 2016 A716 7716 7116 X X X X X X X Read X SRD (Note 2) Write Write Write Write Read WA0 (Note 3) WD0 (Note 3) Write BA (Note 4) WA1 WD1 D016 D016 D016 D6 (Note 5) X BA BA Note 1: When a software command is input, the high-order byte of data (D8 to D15) is ignored. Note 2: SRD = Status Register Data Note 3: WA = Write Address, WD = Write Data WA and WD must be set sequentially from 0016 to FE16 (byte address; however, an even address). The page size is 256 bytes. Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.) Note 5: D6 corresponds to the block lock status. Block not locked when D6 = 1, block locked when D6 = 0. Note 6: X denotes a given address in the user ROM area (that is an even address). Read Array Command (FF16) The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D0–D15), 16 bits at a time. The read array mode is retained intact until another command is written. Read Status Register Command (7016) When the command code “7016” is written in the first bus cycle, the content of the status register is read out at the data bus (D0–D7) by a read in the second bus cycle. The status register is explained in the next section. Clear Status Register Command (5016) This command is used to clear the bits SR3 to 5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code “5016” in the first bus cycle. 1-225 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Page Program Command (4116) Page program allows for high-speed programming in units of 256 bytes. Page program operation starts when the command code “4116” is written in the first bus cycle. In the second bus cycle through the 129th bus cycle, the write data is sequentially written 16 bits at a time. At this time, the addresses A0-A7 need to be incremented by 2 from “0016” to “FE16.” When the system finishes loading the data, it starts an auto write operation (data program and verify operation). Whether the auto write operation is completed can be confirmed by reading the status register or the flash memory control register 0. At the same time the auto write operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the auto write operation starts and is returned to 1 upon completion of the auto write operation. In this case, the read status register mode remains active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the flash memory is reset using its reset bit. ____ The RY/BY status flag of the flash memory control register 0 is 0 during auto write operation and 1 when the auto write operation is completed as is the status register bit 7. After the auto write operation is completed, the status register can be read out to know the result of the auto write operation. For details, refer to the section where the status register is detailed. Figure 1.26.4 shows an example of a page program flowchart. Each block of the flash memory can be write protected by using a lock bit. For details, refer to the section where the data protect function is detailed. Additional writes to the already programmed pages are prohibited. Start Write 4116 n=0 Write address n and data n NO n=n+2 n = FE16 YES RY/BY status flag = 1? YES Check full status Page program completed NO Figure 1.26.4. Page program flowchart 1-226 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Erase Command (2016/D016) By writing the command code “2016” in the first bus cycle and the confirmation command code “D016” in the second bus cycle that follows to the block address of a flash memory block, the system initiates an auto erase (erase and erase verify) operation. Whether the auto erase operation is completed can be confirmed by reading the status register or the flash memory control register 0. At the same time the auto erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned to 1 upon completion of the auto erase operation. In this case, the read status register mode remains active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the flash memory is reset using its reset bit. ____ The RY/BY status flag of the flash memory control register 0 is 0 during auto erase operation and 1 when the auto erase operation is completed as is the status register bit 7. After the auto erase operation is completed, the status register can be read out to know the result of the auto erase operation. For details, refer to the section where the status register is detailed. Figure 1.26.5 shows an example of a block erase flowchart. Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer to the section where the data protect function is detailed. Start Write 2016 Write D016 Block address RY/BY status flag = 1? YES Check full status check(Note) NO Error Erase error Block erase completed Note: Refer to Figure 1.26.8. Figure 1.26.5. Block erase flowchart 1-227 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Erase All Unlock Blocks Command (A716/D016) By writing the command code “A716” in the first bus cycle and the confirmation command code “D016” in the second bus cycle that follows, the system starts erasing blocks successively. Whether the erase all unlock blocks command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for block erase. Also, the status register can be read out to know the result of the auto erase operation. When the lock bit disable select bit of the flash memory control register 0 = 1, all blocks are erased no matter how the lock bit is set. On the other hand, when the lock bit disable select bit = 0, the function of the lock bit is effective and only nonlocked blocks (where lock bit data = 1) are erased. Lock Bit Program Command (7716/D016) By writing the command code “7716” in the first bus cycle and the confirmation command code “D016” in the second bus cycle that follows to the block address of a flash memory block, the system sets the lock bit for the specified block to 0 (locked). Figure 1.26.6 shows an example of a lock bit program flowchart. The status of the lock bit (lock bit data) can be read out by a read lock bit status command. Whether the lock bit program command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for page program. For details about the function of the lock bit and how to reset the lock bit, refer to the section where the data protect function is detailed. Start Write 7716 Write D016 block address RY/BY status flag = 1? YES SR4 = 0? NO NO Lock bit program in error YES Lock bit program completed Figure 1.26.6. Lock bit program flowchart 1-228 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Lock Bit Status Command (7116) By writing the command code “7116” in the first bus cycle and then the block address of a flash memory block in the second bus cycle that follows, the system reads out the status of the lock bit of the specified block on to the data bus(D6). Figure 1.26.7 shows an example of a read lock bit program flowchart. Start Write 7116 Enter block address (Note) NO D6 = 0? YES Blocks locked Blocks not locked Note: Data bus bit 6. Figure 1.26.7. Read lock bit status flowchart 1-229 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Data Protect Function (Block Lock) Each block in Figure 1.25.1 has a nonvolatile lock bit to specify that the block be protected (locked) against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of each block can be read out using the read lock bit status command. Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash memory control register 0’s lock bit disable select bit is set. (1) When the lock bit disable select bit = “0”, a specified block can be locked or unlocked by the lock bit status (lock bit data). Blocks whose lock bit data = “0” are locked, so they are disabled against erase/write. On the other hand, the blocks whose lock bit data = “1” are not locked, so they are enabled for erase/write. (2) When the lock bit disable select bit = “1”, all blocks are nonlocked regardless of the lock bit data, so they are enabled for erase/write. In this case, the lock bit data that is “0” (locked) is set to “1” (nonlocked) after erasure, so that the lock bit-actuated lock is removed. Status Register The status register indicates the operating status of the flash memory and whether an erase or program operation has terminated normally or in an error. The content of this register can be read out by only writing the read status register command (7016). Table 1.26.2 details the status register. The status register is cleared by writing the Clear Status Register command (5016). After a reset, the status register is set to “8016.” Each bit in this register is explained below. Write state machine (WSM) status (SR7) After power-on, the write state machine (WSM) status is set to “1”. The write state machine (WSM) status indicates the operating status of the device, as for output on the ____ RY/BY pin. This status bit is set to “0” during auto write or auto erase operation and is set to “1” upon completion of these operations. Erase status (SR5) The erase status informs the operating status of auto erase operation to the CPU. When an erase error occurs, it is set to “1”. The erase status is reset to “0” when cleared. 1-230 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Program status (SR4) The program status informs the operating status of auto write operation to the CPU. When a write error occurs, it is set to “1”. The program status is reset to “0” when cleared. When an erase command is in error (which occurs if the command entered after the block erase command (2016) is not the confirmation command (D016), both the program status and erase status (SR5) are set to “1”. When the program status or erase status = “1”, only the following flash commands will be accepted: Read Array, Read Status Register, and Clear Status Register. Also, in one of the following cases, both SR4 and SR5 are set to “1” (command sequence error): (1) When the valid command is not entered correctly (2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase (2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is entered, read array is assumed and the command that has been set up in the first bus cycle is canceled. Block status after program (SR3) If excessive data is written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), “1” is set for the program status after-program at the end of the page write operation. In other words, when writing ends successfully, “8016” is output; when writing fails, “9016” is output; and when excessive data is written, “8816” is output. Table 1.26.2. Definition of each bit in status register Each bit of SRD SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Definition Status name Write state machine (WSM) status Reserved Erase status Program status Block status after program Reserved Reserved Reserved "1" Ready Terminated in error Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally Terminated normally - 1-231 Mitsubishi microcomputers M16C / 62A Group CPU Rewrite Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 1.26.8 shows a full status check flowchart and the action to be taken when each error occurs. Read status register YES SR4=1 and SR5 =1 ? NO SR5=0? YES SR4=0? YES NO NO Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. Block erase error Program error (page or lock bit) Execute the read lock bit status command (7116) to see if the block is locked. After removing lock, execute write operation in the same way. If the error still occurs, the page in error cannot be used. After erasing the block in error, execute write operation one more time. If the same error still occurs, the block in error cannot be used. SR3=0? YES NO Program error (block) End (block erase, program) Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. Execute the clear status register command (5016) before executing these commands. Figure 1.26.8. Full status check flowchart and remedial procedure for errors 1-232 Mitsubishi microcomputers M16C / 62A Group Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version) Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ROM code protect function The ROM code protect function is used to prohibit reading out or modifying the contents of the flash memory during parallel I/O mode and is set by using the ROM code protect control address register (0FFFFF16). Figure 1.27.1 shows the ROM code protect control address (0FFFFF16). (This address exists in the user ROM area.) If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the contents of the flash memory version can be read out or modified. Once ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/ O or some other mode to rewrite the contents of the ROM code protect reset bits. ROM code protect control address b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol ROMCP Address 0FFFFF16 When reset FF16 Bit symbol Bit name Function Always set this bit to 1. b3 b2 Reserved bit ROMCP2 ROM code protect level 2 set bit (Note 1, 2) 00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled b5 b4 ROMCR ROM code protect reset bit (Note 3) 00: Protect removed 01: Protect set bit effective 10: Protect set bit effective 11: Protect set bit effective b7 b6 ROMCP1 ROM code protect level 1 set bit (Note 1) 00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be changed in parallel input/ output mode, they need to be rewritten in serial input/output or some other mode. Figure 1.27.1. ROM code protect control address 1-233 Mitsubishi microcomputers M16C / 62A Group Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Write a program which has had the ID code preset at these addresses to the flash memory. Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector 4 bytes Figure 1.27.2. ID code store addresses 1-234 Mitsubishi microcomputers M16C / 62A Group Appendix Parallel I/O Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Parallel I/O Mode The parallel I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is parallel. Use an exclusive programer supporting M16C/62A (flash memory version). Refer to the instruction manual of each programer maker for the details of use. User ROM and Boot ROM Areas In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.25.1 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its blocks are shown in Figure 1.25.1. The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0FE00016 through 0FFFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area. 1-235 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode (Flash Memory Version) Pin functions (Flash memory standard serial I/O mode) Pin VCC,VSS CNVSS RESET XIN XOUT BYTE AVCC, AVSS VREF P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P51 to P54, P56, P57 P50 P55 P60 to P63 P64 Name Power input CNVSS Reset input I I I/O Description Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin. Connect to Vcc pin. Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect this pin to VSS or VCC. Connect AVSS to VSS and AVCC to VCC, respectively. I I I I I I I I I I O Enter the reference voltage for AD from this pin. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" level signal. Input "L" level signal. Input "H" or "L" level signal or open. Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Monitors the boot program operation check signal output pin. Standard serial I/O mode 1: Serial clock input pin Standard serial I/O mode 2: Input "L". Serial data input pin Serial data output pin Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Connect this pin to Vcc. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock input Clock output BYTE Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 Input port P5 CE input EPM input Input port P6 BUSY output I O I P65 P66 P67 P70 to P77 P80 to P84, P86, P87 P85 P90 to P97 P100 to P107 SCLK input RxD input TxD output Input port P7 Input port P8 NMI input Input port P9 Input port P10 I I O I I I I I 1-236 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 1 2345 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 M16C/62A Group (Flash memory version) P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 CE EPM BUSY SCLK RxD TxD Vss P96/ANEX1/SOUT4 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL/TA0IN/TB5IN P70/TXD2/SDA/TA0OUT Vcc Mode setup method Value Signal CNVss Vcc EPM Vss RESET Vss to Vcc CE Vcc RESET CNVss Connect oscillator circuit. Package: 100P6S-A Figure 1.29.1. Pin connections for serial I/O mode (1) 1-237 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P12/D10 P11/D9 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 M16C/62A Group (Flash memory version) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P42/A18 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CTS0/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P70/TXD2/SDA/TA0OUT P71/RxD2/SCL/TA0IN/TB5IN P72/CLK2/TA1OUT/V CE EPM BUSY SCLK RXD TXD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT VSS VCC Mode setup method Signal Value CNVss Vcc EPM Vss RESET Vss to Vcc CE Vcc RESET CNVSS Connect oscillator circuit. Package: 100P6Q-A Figure 1.29.2. Pin connections for serial I/O mode (2) 1-238 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Standard serial I/O mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re_____ ________ leased, which is done when the P50 (CE) pin is "H" level, the P55 (EPM) pin "L" level and the CNVss pin "H" level. (In the ordinary command mode, set CNVss pin to "L" level.) This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figures 1.29.1 and 1.29.2 show the pin connections for the standard serial I/O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/ O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of CLK1 pin when the reset is released. To use standard serial I/O mode 1 (clock synchronized), set the CLK1 pin to "H" level and release the reset. The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). The CLK1 pin is the transfer clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output. The RTS1 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts. To use standard serial I/O mode 2 (clock asynchronized), set the CLK1 pin to "L" level and release the reset. The operation uses the two UART1 pins RxD1 and TxD1. In the standard serial I/O mode, only the user ROM area indicated in Figure 1.29.19 can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit are not accepted unless the ID code matches. 1-239 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of standard serial I/O mode 1 (clock synchronized) In standard serial I/O mode 1, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART1). Standard serial I/O mode 1 is engaged by releasing the reset with the P65 (CLK1) pin "H" level. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the CLK1 pin, and are then input to the MCU via the RxD1 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD1 pin. The TxD1 pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the RTS1 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the RTS1 (BUSY) pin is "L" level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc. 1-240 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Software Commands Table 1.29.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Software commands are explained here below. Table 1.29.1. Software commands (Standard serial I/O mode 1) Control command 1 Page read 1st byte transfer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output Address (middle) Address (middle) 3rd byte Address (high) Address (high) Address (high) SRD1 output Address (high) Address (high) 4th byte 5th byte 6th byte Data output Data input D016 Data output Data input Data output Data input Data output to 259th byte Data input to 259th byte FF16 When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Not acceptable Not acceptable Not acceptable 2 Page program 4116 3 4 5 6 7 Block erase Erase all unlocked blocks Read status register Clear status register Read lock bit status 2016 A716 7016 5016 7116 Lock bit data output D016 8 9 Lock bit program Lock bit enable 7716 7A16 7516 10 Lock bit disable 11 ID check function 12 Download function Address (middle) Size FA16 Size (low) (high) F516 Version data output Address (middle) Version data output Address (high) Check data (high) Address (low) Address (high) Checksum Version data output Data output 13 Version data output function FB16 ID1 To Data required input number of times Version Version data data output output Data output Data output ID size To ID7 Acceptable Not acceptable 14 Boot ROM area output function 15 Read check data FC16 Version data output to 9th byte Data output to 259th byte Acceptable Not acceptable Not acceptable Check FD16 data (low) Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank. 1-241 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the fall of the clock. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FF16 A8 to A15 A16 to A23 data0 data255 Figure 1.29.3. Timing for page read Read Status Register Command This command reads status information. When the “7016” command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7016 SRD output SRD1 output Figure 1.29.4. Timing for reading the status register 1-242 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clear Status Register Command This command clears the bits (SR3–SR5) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 5016 Figure 1.29.5. Timing for clearing the status register Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “4116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the page program can be known by reading the status register. For more information, see the section on the status register. Each block can be write-protected with the lock bit. For more information, see the section on the data protection function. Additional writing is not allowed with already programmed pages. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 4116 A8 to A15 A16 to A23 data0 data255 Figure 1.29.6. Timing for the page program 1-243 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the “2016” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A8 to A23. When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 2016 A8 to A15 A16 to A23 D016 Figure 1.29.7. Timing for block erasing 1-244 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Transfer the “A716” command code with the 1st byte. (2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the erase operation can be known by reading the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) A716 D016 Figure 1.29.8. Timing for erasing all unlocked blocks Lock Bit Program Command This command writes “0” (lock) for the lock bit of the specified block. Execute the lock bit program command as explained here following. (1) Transfer the “7716” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, “0” is written for the lock bit of the specified block. Write the highest address of the specified block for addresses A8 to A23. When writing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. Lock bit status can be read with the read lock bit status command. For information on the lock bit function, reset procedure and so on, see the section on the data protection function. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7716 A8 to A15 A16 to A23 D016 Figure 1.29.9. Timing for the lock bit program 1-245 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following. (1) Transfer the “7116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. The lock bit data is the 6th bit(D6) of the output data. Write the highest address of the specified block for addresses A8 to A23. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7116 A8 to A15 A16 to A23 D6 Figure 1.29.10. Timing for reading lock bit status Lock Bit Enable Command This command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. The command code “7A16” is sent with the 1st byte of the serial transmission. This command only enables the lock bit function; it does not set the lock bit itself. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7A16 Figure 1.29.11. Timing for enabling the lock bit 1-246 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Lock Bit Disable Command This command disables the lock bit. The command code “7516” is sent with the 1st byte of the serial transmission. This command only disables the lock bit function; it does not set the lock bit itself. However, if an erase command is executed after executing the lock bit disable command, “0” (locked) lock bit data is set to “1” (unlocked) after the erase operation ends. In any case, after the reset is cancelled, the lock bit is enabled. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) 7516 Figure 1.29.12. Timing for disabling the lock bit Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FA16 Data size (low) Check sum Program data Program data Data size (high) Figure 1.29.13. Timing for download 1-247 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the “FB16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FB16 'V' 'E' 'R' 'X' Figure 1.29.14. Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the “FC16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the fall of the clock. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) FC16 A8 to A15 A16 to A23 data0 data255 Figure 1.29.15. Timing for boot ROM area output 1-248 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the “F516” command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) RTS1(BUSY) F516 DF16 FF16 0F16 ID size ID1 ID7 Figure 1.29.16. Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses. Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector 4 bytes Figure 1.29.17. ID code storage addresses 1-249 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. The check data is the result of CRC operation of write data. CLK1 RxD1 (M16C reception data) TxD1 (M16C transmit data) FD16 Check data (low) RTS1(BUSY) Check data (high) Figure 1.29.18. Timing for the read check data 1-250 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Data Protection (Block Lock) Each of the blocks in Figure 1.29.19 have a nonvolatile lock bit that specifies protection (block lock) against erasing/writing. A block is locked (writing “0” for the lock bit) with the lock bit program command. Also, the lock bit of any block can be read with the read lock bit status command. Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock bit disable and lock enable bit commands. (1) After the reset has been cancelled and the lock bit enable command executed, the specified block can be locked/unlocked using the lock bit (lock bit data). Blocks with a “0” lock bit data are locked and cannot be erased or written in. On the other hand, blocks with a “1” lock bit data are unlocked and can be erased or written in. (2) After the lock bit disable command has been executed, all blocks are unlocked regardless of lock bit data status and can be erased or written in. In this case, lock bit data that was “0” (locked) before the block was erased is set to “1” (unlocked) after erasing, therefore the block is actually unlocked with the lock bit. 0C000016 Block 6 : 64K byte 0D000016 Block 5 : 64K byte 0E000016 Block 4 : 64K byte 0F000016 Flash memory size 256Kbytes 128Kbytes Flash memory start address 0C000016 0E000016 Block 3 : 32K byte Block 2 : 8K byte Block 1 : 8K byte Block 0 : 16K byte User ROM area 0F800016 0FA00016 0FC00016 0FFFFF16 Figure 1.29.19. Blocks in the user area 1-251 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Register (SRD) The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (7016). Also, the status register is cleared by writing the clear status register command (5016). Table 1.29.2 gives the definition of each status register bit. After clearing the reset, the status register outputs “8016”. Table 1.29.2. Status register (SRD) SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Write state machine (WSM) status Reserved Erase status Program status Block status after program Reserved Reserved Reserved Definition "1" Ready Terminated in error Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally Terminated normally - Write State Machine (WSM) Status (SR7) The write state machine (WSM) status indicates the operating status of the flash memory. When power is turned on, “1” (ready) is set for it. The bit is set to “0” (busy) during an auto write or auto erase operation, but it is set back to “1” when the operation ends. Erase Status (SR5) The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to “1”. When the erase status is cleared, it is set to “0”. Program Status (SR4) The program status reports the operating status of the auto write operation. If a write error occurs, it is set to “1”. When the program status is cleared, it is set to “0”. Block Status After Program (SR3) If excessive data is written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), “1” is set for the block status after-program at the end of the page write operation. In other words, when writing ends successfully, “8016” is output; when writing fails, “9016” is output; and when excessive data is written, “8816” is output. If “1” is written for any of the SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked blocks and lock bit program commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. 1-252 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Status Register 1 (SRD1) Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 1.29.3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and the flag status is maintained even after the reset. Table 1.29.3. Status register 1 (SRD1) SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) Status name Boot update completed bit Reserved Reserved Check sum match bit ID check completed bits Definition "1" Update completed "0" Not update Mismatch Not verified Verification mismatch Reserved Verified Normal operation - Match 00 01 10 11 Time out - SR9 (bit1) SR8 (bit0) Data receive time out Reserved Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. Check Sum Match Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Receive Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. 1-253 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Full Status Check Results from executed erase and program operations can be known by running a full status check. Figure 1.29.20 shows a flowchart of the full status check and explains how to remedy errors which occur. Read status register YES SR4=1 and SR5 =1 ? NO SR5=0? YES SR4=0? YES NO NO Command sequence error Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used. Block erase error Program error (page or lock bit) Execute the read lock bit status command (7116) to see if the block is locked. After removing lock, execute write operation in the same way. If the error still occurs, the page in error cannot be used. After erasing the block in error, execute write operation one more time. If the same error still occurs, the block in error cannot be used. SR3=0? YES NO Program error (block) End (block erase, program) Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. Execute the clear status register command (5016) before executing these commands. Figure 1.29.20. Full status check flowchart and remedial procedure for errors 1-254 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example Circuit Application for The Standard Serial I/O Mode 1 The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information. Clock input BUSY output Data input Data output CLK1 RTS1(BUSY) RXD1 TXD1 M16C/62A Group (Flash memory version) CNVss NMI P50(CE) P55(EPM) (1) Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. (2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch. Figure 1.29.21. Example circuit application for the standard serial I/O mode 1 1-255 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Overview of standard serial I/O mode 2 (clock asynchronized) In standard serial I/O mode 2, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART1). Standard serial I/O mode 2 is engaged by releasing the reset with the P65 (CLK1) pin "L" level. The TxD1 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After the reset is released, connections can be established at 9,600 bps when initial communications (Figure 1.29.22) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by executing software commands. However, communication errors may occur because of the oscillation frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. Data and status registers in memory can be read after transmitting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained initial communications with peripheral units, how frequency is identified and software commands. Initial communications with peripheral units After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation frequency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (Figure 1.29.22). (1) Transmit "B016" from a peripheral unit. If the oscillation frequency input by the main clock is 10 or 16 MHz, the MCU with internal flash memory outputs the "B016" check code. If the oscillation frequency is anything other than 10 or 16 MHz, the MCU does not output anything. (2) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (3) The MCU with internal flash memory outputs the "B016" check code and initial communications end successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. *1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock. Peripheral unit MCU with internal flash memory Reset (1) Transfer "B016" (2) Transfer "0016" 16 times At least 15ms transfer interval 15 th 16th "B016" "B016" 1st 2nd "0016" "0016" "0016" "0016" "B016" (3) Transfer check code "B016" If the oscillation frequency input by the main clock is 10 or 16 MHz, the MCU outputs "B016". If other than 10 or 16 MHz, the MCU does not output anything. The bit rate generator setting completes (9600bps) Figure 1.29.22. Peripheral unit and initial communication 1-256 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER How frequency is identified When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 16 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 1.29.4 gives the operation frequency and the baud rate that can be attained for. Table 1.29.4 Operation frequency and the baud rate Operation frequency (MHZ) 16MHZ 12MHZ 11MHZ 10MHZ 8MHZ 7.3728MHZ 6MHZ 5MHZ 4.5MHZ 4.194304MHZ 4MHZ 3.58MHZ 3MHZ 2MHZ Baud rate 9,600bps Baud rate 19,200bps Baud rate 38,400bps Baud rate 57,600bps √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ – √ √ √ – – √ – – √ √ √ – – √ √ – – √ – – √ – √ √ – √ – – √ : Communications possible – : Communications not possible 1-257 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Software Commands Table 1.29.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and reading are controlled by transferring software commands via the RxD1 pin. Standard serial I/O mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software commands of standard serial I/O mode 1. Software commands are explained here below. Table 1.29.5. Software commands (Standard serial I/O mode 2) Control command 1 2 Page read Page program 1st byte transfer SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output Address (middle) Address (middle) 3rd byte Address (high) Address (high) Address (high) SRD1 output Address (high) Address (high) 4th byte 5th byte 6th byte Data output Data input D016 Data output Data input Data output Data input Data output to 259th byte Data input to 259th byte FF16 4116 When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable Not acceptable Not acceptable Not acceptable Not acceptable 3 4 5 6 7 8 9 Block erase Erase all unlocked blocks Read status register Clear status register Read lock bit status Lock bit program Lock bit enable 2016 A716 7016 5016 7116 7716 7A16 7516 Lock bit data output D016 10 Lock bit disable 11 ID check function 12 Download function Address (middle) Size FA16 Size (low) (high) F516 Version data output Address (middle) Version data output Address (high) Check data (high) Address (low) Address (high) Checksum Version data output Data output 13 Version data output function FB16 ID1 To Data required input number of times Version Version data data output output Data output Data output ID size To ID7 Acceptable Not acceptable 14 Boot ROM area output function 15 Read check data FC16 Version data output to 9th byte Data output to 259th byte Acceptable Not acceptable Not acceptable Check FD16 data (low) 16 Baud rate 9600 17 Baud rate 19200 18 Baud rate 38400 19 Baud rate 57600 B016 B116 B216 B316 B016 B116 B216 B316 Acceptable Acceptable Acceptable Acceptable Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank. 1-258 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the “FF16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first. RxD1 (M16C reception data) TxD1 (M16C transmit data) FF16 A8 to A15 A16 to A23 data0 data255 Figure 1.29.23. Timing for page read Read Status Register Command This command reads status information. When the “7016” command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7016 SRD output SRD1 output Figure 1.29.24. Timing for reading the status register 1-259 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clear Status Register Command This command clears the bits (SR3–SR5) which are set when the status register operation ends in error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. RxD1 (M16C reception data) TxD1 (M16C transmit data) 5016 Figure 1.29.25. Timing for clearing the status register Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the “4116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. The result of the page program can be known by reading the status register. For more information, see the section on the status register. Each block can be write-protected with the lock bit. For more information, see the section on the data protection function. Additional writing is not allowed with already programmed pages. RxD1 (M16C reception data) TxD1 (M16C transmit data) 4116 A8 to A15 A16 to A23 data0 data255 Figure 1.29.26. Timing for the page program 1-260 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the “2016” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the highest address of the specified block for addresses A8 to A23. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register. Each block can be erase-protected with the lock bit. For more information, see the section on the data protection function. RxD1 (M16C reception data) TxD1 (M16C transmit data) 2016 A8 to A15 A16 to A23 D016 Figure 1.29.7. Timing for block erasing 1-261 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Erase All Unlocked Blocks Command This command erases the content of all blocks. Execute the erase all unlocked blocks command as explained here following. (1) Transfer the “A716” command code with the 1st byte. (2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. The result of the erase operation can be known by reading the status register. Each block can be eraseprotected with the lock bit. For more information, see the section on the data protection function. RxD1 (M16C reception data) TxD1 (M16C transmit data) A716 D016 Figure 1.29.28. Timing for erasing all unlocked blocks Lock Bit Program Command This command writes “0” (lock) for the lock bit of the specified block. Execute the lock bit program command as explained here following. (1) Transfer the “7716” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, “0” is written for the lock bit of the specified block. Write the highest address of the specified block for addresses A8 to A23. Lock bit status can be read with the read lock bit status command. For information on the lock bit function, reset procedure and so on, see the section on the data protection function. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7716 A8 to A15 A16 to A23 D016 Figure 1.29.29. Timing for the lock bit program 1-262 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Lock Bit Status Command This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following. (1) Transfer the “7116” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) The lock bit data of the specified block is output with the 4th byte. The lock bit data is the 6th bit(D6) of the output data. Write the highest address of the specified block for addresses A8 to A23. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7116 A8 to A15 A16 to A23 D6 Figure 1.29.30. Timing for reading lock bit status Lock Bit Enable Command This command enables the lock bit in blocks whose bit was disabled with the lock bit disable command. The command code “7A16” is sent with the 1st byte of the serial transmission. This command only enables the lock bit function; it does not set the lock bit itself. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7A16 Figure 1.29.31. Timing for enabling the lock bit 1-263 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Lock Bit Disable Command This command disables the lock bit. The command code “7516” is sent with the 1st byte of the serial transmission. This command only disables the lock bit function; it does not set the lock bit itself. However, if an erase command is executed after executing the lock bit disable command, “0” (locked) lock bit data is set to “1” (unlocked) after the erase operation ends. In any case, after the reset is cancelled, the lock bit is enabled. RxD1 (M16C reception data) TxD1 (M16C transmit data) 7516 Figure 1.29.32. Timing for disabling the lock bit Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the “FA16” command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM. RxD1 (M16C reception data) TxD1 (M16C transmit data) FA16 Data size (low) Check sum Program data Program data Data size (high) Figure 1.29.33. Timing for download 1-264 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the “FB16” command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters. RxD1 (M16C reception data) TxD1 (M16C transmit data) FB16 'V' 'E' 'R' 'X' Figure 1.29.34. Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the “FC16” command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first. RxD1 (M16C reception data) TxD1 (M16C transmit data) FC16 A8 to A15 A16 to A23 data0 data255 Figure 1.29.35. Timing for boot ROM area output 1-265 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the “F516” command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code. RxD1 (M16C reception data) TxD1 (M16C transmit data) F516 DF16 FF16 0F16 ID size ID1 ID7 Figure 1.29.36. Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses. Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector 4 bytes Figure 1.29.37. ID code storage addresses 1-266 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. The check data is the result of CRC operation of write data. RxD1 (M16C reception data) TxD1 (M16C transmit data) FD16 Check data (low) Check data (high) Figure 1.29.38. Timing for the read check data Baud Rate 9600 This command changes baud rate to 9,600 bps. Execute it as follows. (1) Transfer the "B016" command code with the 1st byte. (2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B016 B016 Figure 1.29.39. Timing of baud rate 9600 1-267 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Baud Rate 19200 This command changes baud rate to 19,200 bps. Execute it as follows. (1) Transfer the "B116" command code with the 1st byte. (2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B116 B116 Figure 1.29.40. Timing of baud rate 19200 Baud Rate 38400 This command changes baud rate to 38,400 bps. Execute it as follows. (1) Transfer the "B216" command code with the 1st byte. (2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B216 B216 Figure 1.29.41. Timing of baud rate 38400 Baud Rate 57600 This command changes baud rate to 57,600 bps. Execute it as follows. (1) Transfer the "B316" command code with the 1st byte. (2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps. RxD1 (M16C reception data) TxD1 (M16C transmit data) B316 B316 Figure 1.29.42. Timing of baud rate 57600 1-268 Mitsubishi microcomputers M16C / 62A Group Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example Circuit Application for The Standard Serial I/O Mode 2 The below figure shows a circuit application for the standard serial I/O mode 2. CLK1 Monitor output Data input Data output BUSY RXD1 TXD1 M16C/62A Group (Flash memory version) CNVss NMI P50(CE) P55(EPM) (1) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch. Figure 1.29.43. Example circuit application for the standard serial I/O mode 2 1-269 Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 100P6S-A MMP JEDEC Code – HD D Weight(g) 1.58 Lead Material Alloy 42 Plastic 100pin 14✕20mm body QFP MD e EIAJ Package Code QFP100-P-1420-0.65 1 80 b2 100 81 I2 Recommended Mount Pad Symbol HE E 30 51 31 50 A L1 A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME F b A1 e y x M L Detail F Dimension in Millimeters Min Nom Max 3.05 – – 0.1 0.2 0 2.8 – – 0.25 0.3 0.4 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.65 – – 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 – – – – 0.13 0.1 – – 0° 10° – 0.35 – – 1.3 – – 14.6 – – 20.6 – – A2 100P6Q-A MMP JEDEC Code – Weight(g) 0.63 Lead Material Cu Alloy c Plastic 100pin 14✕14mm body LQFP MD e EIAJ Package Code LQFP100-P-1414-0.50 D 100 76 1 75 b2 HD l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp A3 25 51 26 50 A e F L1 x y b2 I2 MD ME M Detail F Lp 1-270 c b x y L Dimension in Millimeters Min Nom Max 1.7 – – 0.1 0.2 0 1.4 – – 0.13 0.18 0.28 0.105 0.125 0.175 13.9 14.0 14.1 13.9 14.0 14.1 0.5 – – 15.8 16.0 16.2 15.8 16.0 16.2 0.3 0.5 0.7 1.0 – – 0.45 0.6 0.75 – 0.25 – – – 0.08 0.1 – – 0° 10° – 0.225 – – 0.9 – – 14.4 – – – – 14.4 HE E A2 A1 A3 ME ME Mitsubishi microcomputers M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Differences between M16C/62A and M16C/62 Item Memory area 1 Mbyte fixed M16C/62A M16C/62 Memory expansion 1.2 Mbytes mode 4 Mbytes mode CTS/RTS separate function Serial I/O No CTS/RTS separate function IIC bus mode Analog or digital delay is selected as SDA delay Only analog delay is selected as SDA delay EPROM / one time PROM version None Have Flash memory version Standard serial I/O mode (clock asynchronized ) is supported Clock synchronized only Differences in SFR between M16C/62A and M16C/62 Address 000516 Register name Processor mode register 1 (PM1) b5,b4 M16C/62A Reserved bits b5,b4 M16C/62 Memory area expansion bits 000B16 03B016 Data bank register (DBR) UART transmit/receive register 2 (UCON) UART2 special mode register 3 (U2SMR3) UART2 special mode register (U2SMR) Reserved register b6 Reserved bit Have b6 CTS/RTS separation bit 037516 Have None 037716 b7 SDA digital delay select bit b7 Reserved bit 1-271 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Description The M16C/62M group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, low voltage (2.2V to 3.6V), they are capable of executing instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. The M16C/62M group includes a wide range of products with different internal memory types and sizes and various package types. Features • Memory capacity .................................. ROM (See Figure 1.30.4. ROM Expansion) RAM 10K to 20K bytes • Shortest instruction execution time ...... 100ns (f(XIN)=10MHZ, VCC=2.7V to 3.6V) 142.9ns (f(XIN)=7MHZ, VCC=2.2V to 3.6V with software one-wait) • Supply voltage ..................................... 2.7V to 3.6V (f(XIN)=10MHZ, without software wait) 2.4V to 2.7V (f(XIN)=7MHZ, without software wait) 2.2V to 2.4V (f(XIN)=7MHZ with software one-wait) • Low power consumption ...................... 28.5mW (VCC = 3V, f(XIN)=10MHZ, without software wait) • Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software interrupt sources; 7 levels (including key input interrupt) • Multifunction 16-bit timer ...................... 5 output timers + 6 input timers • Serial I/O .............................................. 5 channels (3 for UART or clock synchronous, 2 for clock synchronous) • DMAC .................................................. 2 channels (trigger: 24 sources) • A-D converter ....................................... 10 bits X 8 channels (Expandable up to 10 channels) • D-A converter ....................................... 8 bits X 2 channels • CRC calculation circuit ......................... 1 circuit • Watchdog timer .................................... 1 line • Programmable I/O ............................... 87 lines _______ • Input port .............................................. 1 line (P85 shared with NMI pin) • Memory expansion .............................. Available (to a maximum of 1M bytes) • Chip select output ................................ 4 lines • Clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) Applications Audio, cameras, office equipment, communications equipment, portable equipment 1-272 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin Configuration Figures 1.30.1 and 1.30.2 show the pin configurations (top view). PIN CONFIGURATION (top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 P42/A18 P43/A19 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 23 45 M16C/62M group (Low voltage version) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL/TA0IN/TB5IN P70/TXD2/SDA/TA0OUT Package: 100P6S-A Figure 1.30.1. Pin configuration (top view) 1-273 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (top view) P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 P20/A0(/D0/-) P21/A1(/D1/D0) P22/A2(/D2/D1) P23/A3(/D3/D2) P24/A4(/D4/D3) P25/A5(/D5/D4) P26/A6(/D6/D5) P27/A7(/D7/D6) Vss P30/A8(/-/D7) Vcc P31/A9 P32/A10 P33/A11 P34/A12 P35/A13 P36/A14 P37/A15 P40/A16 P41/A17 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P12/D10 P11/D9 P10/D8 P07/D7 P06/D6 P05/D5 P04/D4 P03/D3 P02/D2 P01/D1 P00/D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 12 34567 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 M16C/62M group (Low voltage version) P42/A18 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P52/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P70/TXD2/SDA/TA0OUT P71/RxD2/SCL/TA0IN/TB5IN P72/CLK2/TA1OUT/V P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V Package: 100P6Q-A Figure 1.30.2. Pin configuration (top view) 1-274 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Block Diagram Figure 1.30.3 is a block diagram of the M16C/62M group. 8 8 8 8 8 8 8 I/O ports Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Internal peripheral functions Timer Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits) A-D converter (10 bits X 8 channels Expandable up to 10 channels) System clock generator XIN-XOUT XCIN-XCOUT Clock synchronous SI/O 8 Port P8 UART/clock synchronous SI/O (8 bits X 3 channels) CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) (8 bits X 2 channels) 7 Port P85 M16C/60 series16-bit CPU core Registers Program counter PC Vector table INTB Stack pointer ISP USP Flag register FLG R0H R0L R0H R0L R1H R1L R1H R1L R2 R2 R3 R3 A0 A0 A1 A1 FB FB SB Memory ROM (Note 1) RAM (Note 2) Watchdog timer (15 bits) Port P9 8 DMAC (2 channels) Port P10 D-A converter (8 bits X 2 channels) Multiplier 8 Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type. Figure 1.30.3. Block diagram of M16C/62M group 1-275 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Performance Outline Table 1.30.1 is a performance outline of M16C/62M group. Table 1.30.1. Performance outline of M16C/62M group Performance 91 instructions 100ns(f(XIN)=10MHZ, VCC=2.7V to 3.6V) 142.9ns (f(XIN)=7MHZ, VCC=2.2V to 3.6V with software one-wait) Memory ROM (See the figure 1.30.4. ROM Expansion) capacity RAM 10K to 20K bytes I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1 Input port P85 1 bit x 1 Multifunction TA0, TA1, TA2, TA3, TA4 16 bits x 5 timer TB0, TB1, TB2, TB3, TB4, TB5 16 bits x 6 Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3 SI/O3, SI/O4 (Clock synchronous) x 2 A-D converter D-A converter DMAC CRC calculation circuit Watchdog timer Interrupt Clock generating circuit Supply voltage 10 bits x (8 + 2) channels 8 bits x 2 2 channels (trigger: 24 sources) CRC-CCITT 15 bits x 1 (with prescaler) 25 internal and 8 external sources, 4 software sources, 7 levels 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) 2.7V to 3.6V (f(XIN)=10MHZ, without software wait) 2.4V to 2.7V (f(XIN)=7MHZ, without software wait) 2.2V to 2.4V (f(XIN)=7MHZ with software one-wait) 28.5mW (f(XIN) =10MHZ, VCC=3V without software wait) 3V 1mA Available (to a maximum of 1M bytes) CMOS high performance silicon gate 100-pin plastic mold QFP Item Number of basic instructions Shortest instruction execution time Power consumption I/O I/O withstand voltage characteristics Output current Memory expansion Device configuration Package 1-276 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Mitsubishi plans to release the following products in the M16C/62M group: (1) Support for mask ROM version and Flash memory version (2) ROM capacity (3) Package 100P6S-A : Plastic molded QFP (mask ROM and flash memory versions) 100P6Q-A : Plastic molded QFP (mask ROM and flash memory versions) ROM Size (Byte) External ROM 256K 128K 96K 64K 32K Mask ROM version Flash memory version M30624MGM-XXXFP/GP M30620MCM-XXXFP/GP M30624FGMFP/GP M30620FCMFP/GP Figure 1.30.4. ROM expansion The M16C/62M group products currently supported are listed in Table 1.30.2. Table 1.30.2. M16C/62M group Type No M30620MCM-XXXFP M30620MCM-XXXGP M30624MGM-XXXFP M30624MGM-XXXGP M30620FCMFP M30620FCMGP M30624FGMFP M30624FGMGP 256K byte 20K byte ROM capacity 128K byte 256K byte 128K byte RAM capacity 10K byte 20K byte Package type 100P6S-A 100P6Q-A 100P6S-A 100P6Q-A 100P6S-A 10K byte 100P6Q-A 100P6S-A 100P6Q-A Flash memory 3V version mask ROM version June, 2001 Remarks 1-277 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Description SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Type No. M 3 0 6 2 0 M C M – X X X F P Package type: FP : Package GP : 100P6S-A 100P6Q-A ROM No. Omitted for blank flash memory version ROM capacity: C : 128K bytes G : 256K bytes Memory type: M : Mask ROM version F : Flash memory version Shows RAM capacity, pin count, etc (The value itself has no specific meaning) M16C/62 Group M16C Family Figure 1.30.5. Type No., memory size, and package 1-278 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.31.1. Absolute maximum ratings Symbol Vcc AVcc Supply voltage Analog supply voltage Input voltage VI RESET, CNVSS, BYTE, P00 to P07, P10 to P17, P20 to P27, P30 to P37,P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, VREF, XIN P70, P71 Output voltage VO P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107, XOUT Topr=25 C Parameter Condition VCC=AVCC VCC=AVCC Rated value - 0.3 to 4.6 - 0.3 to 4.6 Unit V V - 0.3 to Vcc + 0.3 V - 0.3 to 4.6 V - 0.3 to Vcc + 0.3 V Pd P70, P71 Power dissipation - 0.3 to 4.6 300 - 20 to 85 / -40 to 85 (Note) - 65 to 150 Operating ambient temperature Topr Storage temperature Tstg Note : Specify a product of -40°C to 85°C to use it. V mW C C 1-279 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.31.2. Recommended operating conditions (referenced to VCC = 2.2V to 3.6V at Topr = –20°C to 85oC / – 40°C to 85oC (Note 3) unless otherwise specified) Symbol Vcc AVcc Vss AVss Parameter Supply voltage Analog supply voltage Supply voltage Analog supply voltage HIGH input voltage P31 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVSS, BYTE P70, P71 P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion and microprocessor modes) Min. 2.2 Standard Typ. 3.0 Vcc 0 0 Max. 3.6 Unit V V V V 0.8Vcc 0.8Vcc 0.8Vcc 0.5Vcc 0 0 0 Vcc 4.6 Vcc Vcc 0.2Vcc 0.2Vcc 0.16Vcc - 10.0 V V V V V V V mA VIH LOW input voltage VIL P31 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVSS, BYTE P00 to P07, P10 to P17, P20 to P27, P30 (during single-chip mode) P00 to P07, P10 to P17, P20 to P27, P30 (data input function during memory expansion and microprocessor modes) HIGH peak output I OH (peak) current I OH (avg) I OL (peak) I OL (avg) P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86, P87, P90 to P97, P100 to P107 HIGH average output P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, current P80 to P84, P86, P87, P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, LOW peak output P40 to P47, P50 to P57, P60 to P67, P70 to P77, current P80 to P84, P86, P87, P90 to P97, P100 to P107 P00 to P07, P10 to P17, P20 to P27, P30 to P37, LOW average P40 to P47, P50 to P57, P60 to P67, P70 to P77, output current P80 to P84, P86, P87, P90 to P97, P100 to P107 Vcc=2.7V to 3.6V 0 0 0 0 0 32.768 - 5.0 mA 10.0 mA 5.0 10 10 X Vcc - 17 17.5 X Vcc - 35 10 6 X Vcc - 6.2 50 mA MHz MHz MHz MHz MHz kHz f (XIN) No wait Main clock input oscillation frequency Vcc=2.4V to 2.7V Vcc=2.2V to 2.4V Vcc=2.7V to 3.6V with wait Vcc=2.2V to 2.7V f (XcIN) Subclock oscillation frequency Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be 80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max. Note 3: Specify a product of -40°C to 85°C to use it. Note 4: Relationship between main clock oscillation frequency and supply voltage. Main clock input oscillation frequency (No wait) Operating maximum frequency [MHZ] Main clock input oscillation frequency (With wait) Operating maximum frequency [MHZ] Flash memory version program voltage and read operation voltage characteristics 10.0 10 X VCC –17MHZ 10.0 6 X VCC –6.2MHZ Flash program voltage 7.0 Flash read operation voltage VCC=2.4V to 3.6V VCC=2.2V to 2.4V 7.0 17.5 X VCC –35MHZ VCC=2.7V to 3.6V VCC=2.7V to 3.4V 3.5 0.0 2.2 2.4 2.7 3.6 Supply voltage[V] 0.0 2.2 2.4 2.7 3.6 Supply voltage[V] (BCLK: no division) (BCLK: no division) Note 5: Execute case without wait, program / erase of flash memory by VCC=2.7V to 3.6V and f(BCLK) ≤ 6.25 MHz. Execute case with wait, program / erase of flash memory by VCC=2.7V to 3.6V and f(BCLK) ≤ 10.0 MHz. 1-280 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.31.3. Electrical characteristics (referenced to VCC = 2.7V to 3.6V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 1), f(XIN) = 10MHZ without wait unless otherwise specified) Symbol VOH HIGH output voltage HIGH output voltage Parameter P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86,P87, P90 to P97, P100 to P107 XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER Measuring condition Min 2.5 2.5 2.5 Standard Typ. Max. Unit IOH=–1mA IOH=–0.1mA IOH=–50µA With no load applied With no load applied V V 3.0 1 .6 V VOH HIGH output voltage LOW output voltage VOL P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P84, P86,P87, P90 to P97, P100 to P107 XOUT HIGHPOWER LOWPOWER IOL=1mA IOL=0.1mA IOL=50µA With no load applied With no load applied 0.5 0.5 0.5 0 0 V LOW output voltage V V VOL LOW output voltage Hysteresis XCOUT HIGHPOWER LOWPOWER HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, SCL, SDA, CLK0 to CLK4, TA2OUT to TA4OUT, KI0 to KI3, RxD0 to RxD2, SIN3, SIN4 VT+–VT– 0.2 0.8 V VT+–VT– IIH Hysteresis HIGH input current RESET P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, XIN, RESET, CNVss, BYTE P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P84, P86,P87, P90 to P97, P100 to P107 XIN XCIN 0.2 1.8 V VI=3V 4.0 µA IIL LOW input current VI=0V –4.0 µA RPULLUP RfXIN RfXCIN VRAM Pull-up resistance VI=0V 20 75 3 .0 10.0 330 kΩ MΩ MΩ Feedback resistance Feedback resistance RAM retention voltage When clock is stopped Mask ROM version In single-chip mode, the output pins are open and other pins are VSS 2.0 9.5 21.25 V mA f(XIN)=10MHz Square wave, no division Flash memory 3V version f(XIN)=10MHz Square wave, no division 12.0 21.25 mA Mask ROM version, f(XCIN)=32kHz flash memory Square wave 3V version Flash memory 3V version program Flash memory 45.0 µA f(XIN)=10MHz Square wave, division by 2 14.0 mA f(XIN)=10MHz Square wave, division by 2 ICC Power supply current 3V version erase 17.0 mA Mask ROM version, f(XCIN)=32kHz When a WAIT instruction flash memory is executed. 3V version Oscillation capacity High (Note 2) 2.8 µA f(XCIN)=32kHz When a WAIT instruction is executed. Oscillation capacity Low (Note 2) 0.9 µA When clock is stopped Topr=25°C When clock is stopped Topr=85°C 1.0 µA 20.0 Note 1: Specify a product of -40°C to 85°C to use it. Note 2: With one timer operated using fC32. 1-281 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Electrical characteristics SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 1.31.4. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 2.4V to 3.6V, VSS = AVSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 2), f(XIN)=10MHZ unless otherwise specified) Standard Symbol Parameter Measuring condition Unit Min. Typ. Max – – Resolution Absolute accuracy Sample & hold function not available (8 bit) VREF =VCC VREF =VCC=3V, fAD=fAD/2 10 ±2 Bits LSB RLADDER tCONV VREF Ladder resistance Conversion time(8bit) VREF =VCC 10 9.8 40 kΩ µs Reference voltage 2.4 0 VCC VREF V V VIA Analog input voltage Note 1: Connect AVCC pin to VCC pin and apply the same electric potential. Note 2: Specify a product of –40°C to 85°C to use it. Table 1.31.5. D-A conversion characteristics (referenced to VCC = 2.4V to 3.6V, VSS = AVSS = 0V, VREF=3V, at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 2), f(XIN)=10MHZ unless otherwise specified) Symbol – – tsu RO IVREF Resolution Absolute accuracy Setup time Output resistance Reference power supply input current (Note1) Parameter Measuring condition Standard Min. Typ. Max 8 1.0 3 20 1.0 Unit Bits % µs kΩ mA 4 10 Note 1: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to “0016”. The A-D converter's ladder resistance is not included. Also, when D-A register contents are not “0016”, the current IVREF always flows even though Vref may have been set to be “unconnected” by the A-D control register. Note 2: Specify a product of –40°C to 85°C to use it. Table 1.31.6. Flash memory version electrical characteristics (referenced to VCC = 2.7V to 3.6V, at Topr = 0oC to 60oC unless otherwise specified) Parameter Page program time Block erase time Erase all unlocked blocks time Lock bit program time Min. Standard Typ. 6 50 50 X n (Note) 6 Max 120 600 600 X n (Note) 120 Unit ms ms ms ms Note : n denotes the number of block erases. Table 1.31.7. Flash memory version program voltage and read operation voltage characteristics (Topr = 0oC to 60oC) Flash program voltage VCC=2.7V to 3.6V VCC=2.7V to 3.4V Flash read operation voltage VCC=2.4V to 3.6V VCC=2.2V to 2.4V 1-282 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 3V, VSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of -40°C to 85°C to use it. Table 1.31.8. External clock input Standard Symbol tc tw(H) tw(L) tr tf Parameter External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time Min. 100 40 40 Max. Unit ns ns ns 18 18 ns ns Table 1.31.9. Memory expansion and microprocessor modes Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK ) tsu(HOLD-BCLK ) th(RD-DB) th(BCLK -RDY) th(BCLK-HOLD ) td(BCLK-HLDA) Parameter Data input access time (no wait) Data input access time (with wait) Data input access time (when accessing multiplex bus area) Data input setup time RDY input setup time HOLD input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time 10 9 – 90 f(BCLK) X 2 3 X 10 – 90 f(BCLK) X 2 3 X 10 9 – 90 f(BCLK) X 2 9 Standard Min. Max. (Note) (Note) (Note) 80 60 80 0 0 0 Unit ns ns ns ns ns ns ns ns ns 100 ns Note: Calculated according to the BCLK frequency as follows: tac1(RD – DB) = tac2(RD – DB) = tac3(RD – DB) = [ns] [ns] [ns] 1-283 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 3V, VSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of –40°C to 85°C to use it. Table 1.31.10. Timer A input (counter input in event counter mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. 150 60 60 Max. Unit ns ns ns Table 1.31.11. Timer A input (gating input in timer mode) Standard Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Min. 600 300 300 Max. Unit ns ns ns Table 1.31.12. Timer A input (external trigger input in one-shot timer mode) Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 300 150 150 Unit ns ns ns Table 1.31.13. Timer A input (external trigger input in pulse width modulation mode) Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 150 150 Unit ns ns Table 1.31.14. Timer A input (up/down input in event counter mode) Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 3000 1500 1500 600 600 Unit ns ns ns ns ns 1-284 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timing requirements (referenced to VCC = 3V, VSS = 0V, at Topr = – 20oC to 85oC / – 40oC to 85oC (*) unless otherwise specified) * : Specify a product of –40°C to 85°C to use it. Table 1.31.15. Timer B input (counter input in event counter mode) Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Min. Standard Max. Unit ns ns ns ns ns ns 150 60 60 300 160 160 Table 1.31.16. Timer B input (pulse period measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. ns ns ns Unit Table 1.31.17. Timer B input (pulse width measurement mode) Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. Max. 600 300 300 Unit ns ns ns Table 1.31.18. A-D trigger input Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. Max. 1500 200 Unit ns ns Table 1.31.19. Serial I/O Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time _______ Parameter Standard Min. 300 150 150 160 0 50 90 Max. Unit ns ns ns ns ns ns ns Table 1.31.20. External interrupt INTi inputs Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. 380 380 Max. Unit ns ns 1-285 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15 = “1” unless otherwise specified) Table 1.31.21. Memory expansion and microprocessor modes (with no wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) Measuring condition Figure 1.31.1 Standard Min. Max. 60 4 0 0 60 4 60 –4 60 0 60 0 80 4 (Note1) 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = 10 9 f(BCLK) X 2 – 80 [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. Note 3: Specify a product of –40°C to 85°C to use it. R DBi C P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 30pF Figure 1.31.1. Port P0 to P10 measurement circuit 1-286 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 3), CM15 = “1” unless otherwise specified) Table 1.31.22. Memory expansion and microprocessor modes (when accessing external memory area with wait) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) ALE signal output delay time ALE signal output hold time RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard)(Note2) Measuring condition Standard Min. Max. 60 4 0 0 60 4 60 –4 60 0 60 0 80 4 (Note1) 0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.31.1 Note 1: Calculated according to the BCLK frequency as follows: td(DB – WR) = 10 f(BCLK) 9 – 80 [ns] Note 2: This is standard value shows the timing when the output is off, and doesn't show hold time of data bus. Hold time of data bus is different by capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = –CR X ln (1 – VOL / VCC) by a circuit of the right figure. For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time of output “L” level is t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC) = 6.7ns. Note 3: Specify a product of –40°C to 85°C to use it. R DBi C 1-287 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20oC to 85oC / – 40oC to 85oC (Note 2), CM15 = “1” unless otherwise specified) Table 1.31.23. Memory expansion and microprocessor modes (when accessing external memory area with wait, and select multiplexed bus) Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) td(AD-RD) td(AD-WR) tdZ(RD-AD) Standard Min. Max. 60 4 (Note 1) (Note 1) 60 4 (Note 1) (Note 1) 60 0 60 0 80 4 (Note 1) (Note 1) 60 –4 (Note 1) 40 0 0 8 Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard) Address output hold time (WR standard) Chip select output delay time Chip select output hold time (BCLK standard) Chip select output hold time (RD standard) Chip select output hold time (WR standard) RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (BCLK standard) Data output hold time (BCLK standard) Data output delay time (WR standard) Data output hold time (WR standard) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (Address standard) ALE signal output hold time(Address standard) Post-address RD signal output delay time Post-address WR signal output delay time Address output floating start time Measuring condition Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 1.31.1 Note 1: Calculated according to the BCLK frequency as follows: th(RD – AD) = 10 9 f(BCLK) X 2 th(WR – AD) = 10 9 [ns] f(BCLK) X 2 10 9 f(BCLK) X 2 [ns] th(RD – CS) = [ns] th(WR – CS) = 10 9 f(BCLK) X 2 10 9 [ns] td(DB – WR) = X3 – 80 f(BCLK) X 2 th(WR – DB) = 10 9 [ns] f(BCLK) X 2 10 9 [ns] – 45 td(AD – ALE) = f(BCLK) X 2 [ns] Note 2: Specify a product of –40°C to 85°C to use it. 1-288 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) th(TIN–UP) tsu(UP–TIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tc(CK) tw(CKH) CLKi tw(CKL) th(C–Q) TxDi td(C–Q) RxDi tw(INL) INTi input tw(INH) tsu(D–C) th(C–D) Figure 1.31.2. VCC=3V timing diagram (1) 1-289 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Memory Expansion Mode and Microprocessor Mode (Valid only with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY–BCLK) th(BCLK–RDY) (Valid with or without wait) BCLK tsu(HOLD–BCLK) HOLD input th(BCLK–HOLD) HLDA output td(BCLK–HLDA) P0, P1, P2, P3, P4, P50 to P52 Hi–Z td(BCLK–HLDA) Note: The above pins are set to high-impedance regardless of the input level of the BYTE pin and bit (PM06) of processor mode register 0 selects the function of ports P40 to P43. Measuring conditions : • VCC=3V • Input timing voltage : Determined with VIL=0.6V, VIH=2.4V • Output timing voltage : Determined with VOL=1.5V, VOH=1.5V Figure 1.31.3. VCC=3V timing diagram (2) 1-290 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Memory Expansion Mode and Microprocessor Mode (With no wait) Read timing BCLK td(BCLK–CS) 60ns.max th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min th(BCLK–AD) 4ns.min td(BCLK–AD) ADi BHE ALE RD 60ns.max td(BCLK–ALE) th(BCLK–ALE) 60ns.max –4ns.min th(RD–AD) 0ns.min th(BCLK–RD) 0ns.min td(BCLK–RD) 60ns.max tac1(RD–DB) DB Hi–Z th(RD–DB) tSU(DB–RD) 80ns.min 0ns.min Write timing BCLK td(BCLK–CS) 60ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) 60ns.max th(BCLK–AD) 4ns.min ADi BHE ALE td(BCLK–ALE) th(BCLK–ALE) 60ns.max –4ns.min th(WR–AD) 0ns.min WR,WRL, WRH DB td(BCLK–WR) 60ns.max td(BCLK–DB) 80ns.max Hi–Z th(BCLK–WR) 0ns.min th(BCLK–DB) 4ns.min td(DB–WR) (tcyc/2–80)ns.min th(WR–DB) 0ns.min Figure 1.31.4. VCC=3V timing diagram (3) 1-291 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait) Read timing BCLK td(BCLK–CS) 60ns.max VCC = 3V th(BCLK–CS) 4ns.min CSi tcyc th(RD–CS) 0ns.min td(BCLK–AD) ADi BHE ALE td(BCLK–RD) 60ns.max 60ns.max th(BCLK–AD) 4ns.min td(BCLK–ALE) 60ns.max th(RD–AD) 0ns.min th(BCLK–ALE) –4ns.min th(BCLK–RD) 0ns.min RD tac2(RD–DB) DB Hi–Z th(RD–DB) tSU(DB–RD) 80ns.min 0ns.min Write timing BCLK td(BCLK–CS) 60ns.max th(BCLK–CS) 4ns.min CSi tcyc th(WR–CS) 0ns.min td(BCLK–AD) ADi BHE ALE td(BCLK–WR) WR,WRL, WRH td(BCLK–DB) 80ns.max 60ns.max 60ns.max th(BCLK–AD) 4ns.min td(BCLK–ALE) 60ns.max th(WR–AD) 0ns.min th(BCLK–ALE) –4ns.min th(BCLK–WR) 0ns.min th(BCLK–DB) 4ns.min DBi th(WR–DB) td(DB–WR) (tcyc–80)ns.min 0ns.min Measuring conditions : • VCC=3V • Input timing voltage : Determined with VIL=0.48V, VIH=1.5V • Output timing voltage : Determined with VOL=1.5V, VOH=1.5V Figure 1.31.5. VCC=3V timing diagram (4) 1-292 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) Timing SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER VCC = 3V Memory Expansion Mode and Microprocessor Mode (When accessing external memory area with wait, and select multiplexed bus) Read timing BCLK td(BCLK–CS) 60ns.max tcyc th(BCLK–CS) th(RD–CS) (tcyc/2)ns.min 4ns.min CSi td(AD–ALE) (tcyc/2–45)ns.min ADi /DBi Address tdz(RD–AD) 8ns.max tac3(RD–DB) Data input Address th(ALE–AD) 40ns.min th(RD–DB) tSU(DB–RD) 80ns.min 0ns.min td(AD–RD) 0ns.min td(BCLK–AD) ADi BHE ALE RD 60ns.max th(BCLK–AD) 4ns.min td(BCLK–ALE) 60ns.max th(BCLK–ALE) –4ns.min th(RD–AD) (tcyc/2)ns.min th(BCLK–RD) 0ns.min td(BCLK–RD) 60ns.max Write timing BCLK td(BCLK–CS) 60ns.max tcyc th(BCLK–CS) th(WR–CS) (tcyc/2)ns.min 4ns.min CSi td(BCLK–DB) 80ns.max th(BCLK–DB) 4ns.min Data output Address ADi /DBi Address td(AD–ALE) (tcyc/2–60)ns.min td(BCLK–AD) ADi BHE ALE 60ns.max td(DB–WR) (tcyc*3/2–80)ns.min th(WR–DB) (tcyc/2)ns.min th(BCLK–AD) 4ns.min td(BCLK–ALE) th(BCLK–ALE) 60ns.max –4ns.min td(AD–WR) 0ns.min th(WR–AD) (tcyc/2)ns.min th(BCLK–WR) 0ns.min td(BCLK–WR) WR,WRL, WRH 60ns.max Measuring conditions : • VCC=3V • Input timing voltage : Determined with VIL=0.48V,VIH=1.5V • Output timing voltage : Determined with VOL=1.5V,VOH=1.5V Figure 1.31.6. VCC=3V timing diagram (5) 1-293 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-95B Mask ROM number Date : Note : Please complete all items marked ❈ . ) Receipt MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30620MCM-XXXFP/GP MASK ROM CONFIRMATION FORM Section head signature Supervisor signature ❈ Customer Date issued ❈1. Check sheet Date : Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : M30620MCM-XXXFP M30620MCM-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit) ❈2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30620MCM-XXXFP, submit the 100P6S mark specification sheet. For the M30620MCM-XXXGP, submit the 100P6Q mark specification sheet. ❈3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XIN) = MHZ Quartz-crystal oscillator Other ( ) 1-294 Issuance signature Company name TEL ( Submitted by Supervisor Mitsubishi microcomputers M16C / 62M Group (Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-95B Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30620MCM-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XCIN) = kHZ Quartz-crystal oscillator Other ( ) (3) Which operation mode do you use? Single-chip mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) 2.2 2.4 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Memory expansion mode (V) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. ❈4. Special item (Indicate none if there is not specified item) 1-295 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-48B Mask ROM number Date : Note : Please complete all items marked ❈ . ) Receipt MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30624MGM-XXXFP/GP MASK ROM CONFIRMATION FORM Section head signature Supervisor signature ❈ Customer Date issued ❈1. Check sheet Date : Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk. Microcomputer type No. : M30624MGM-XXXFP M30624MGM-XXXGP File code : (hex) Mask file name : .MSK (alpha-numeric 8-digit) ❈2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30624MGM-XXXFP, submit the 100P6S mark specification sheet. For the M30624MGMXXXGP, submit the 100P6Q mark specification sheet. ❈3. Usage Conditions For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XIN) = MHZ Quartz-crystal oscillator Other ( ) 1-296 Issuance signature Company name TEL ( Submitted by Supervisor Mitsubishi microcomputers M16C / 62M Group (Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER GZZ-SH13-48B Mask ROM number MITSUBISHI ELECTRIC-CHIP 16-BIT MICROCOMPUTER M30624MGM-XXXFP/GP MASK ROM CONFIRMATION FORM (2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do not use? f(XCIN) = kHZ Quartz-crystal oscillator Other ( ) (3) Which operation mode do you use? Single-chip mode Microprocessor mode (4) Which operating supply voltage do you use? (Circle the operating voltage range of use) 2.2 2.4 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Memory expansion mode (V) (5) Which operating ambient temperature do you use? (Circle the operating temperature range of use) -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 (°C) (6) Do you use I2C (Inter IC) bus function? Not use Use (7) Do you use IE (Inter Equipment) bus function? Not use Use Thank you cooperation. ❈4. Special item (Indicate none if there is not specified item) 1-297 Mitsubishi microcomputers M16C / 62M Group (Low voltage version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER [ MEMO ] 1-298 Chapter 2 Peripheral Functions Usage Mitsubishi microcomputers M16C / 62A Group Protect SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.1 Protect Usage 2.1.1 Overview of the protect usage 'Protect' is a function that causes a value held in a register to be unchanged even when a program runs away. The following is an overview of the protect usage: (1) Registers affected by the protect function The registers affected by the protect function are: (a) System clock control registers 0, 1 (addresses 000616 and 000716) (b) Processor mode registers 0, 1 (addresses 000416 and 000516) (c) Port P9 direction register (address 03F316), SI/Oi control register (i=3,4)(addresses 036216 and 036616) The values in registers (1) through (3) cannot be changed in write-protect state. To change values in the registers, put the individual registers in write-enabled state. (2) Protect register Figure 2.1.1 shows protect register. 2-2 Mitsubishi microcomputers Protect M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Protect register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Bit symbol PRC0 Address 000A16 Bit name When reset XXXXX0002 Function RW Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516) Enables writing to port P9 direction register (address 03F316) and SI/Oi control register (i=3,4) (addresses 036216 and 036616) (Note) 0 : Write-inhibited 1 : Write-enabled PRC1 PRC2 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Writing a value to an address after “1” is written to this bit returns the bit to “0” . Other bits do not automatically return to “0” and they must therefore be reset by the program. Figure 2.1.1. Protect register 2-3 Mitsubishi microcomputers M16C / 62A Group Protect SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.1.2 Protect Operation The following explains the protect operation. Figure 2.1.2 shows the set-up procedure. Operation (1) Setting “1” in the write-enable bit of system clock control registers 0 and 1 causes system clock control register 0 and system clock control register 1 to be in write-enabled state. (2) The contents of system clock control register 0 and that of system clock control register 1 are changed. (3) Setting “0” in the write-enable bit of system control registers 0 and 1 causes system clock control register 0 and system control register 1 to be in write-inhibited state. (4) To change the contents of processor mode register 0 and that of processor mode register 1, follow the same steps as in dealing with system clock control registers. (5) The write-enable bit of port 9 direction register and SI/Oi control register (i=3,4) goes to “0” when the next write instruction is executed after write-enabled state is readied. Make changes in input/output and SI/Oi control register (i=3,4) immediately after the instruction that sets “ 1 ” i n the write-enable bit of port P9 direction register and S I/Oi control register (i=3,4)(avoid causing an interrupt). Also take measures to prevent DMA transfer from being executed. 2-4 Mitsubishi microcomputers Protect M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Clearing the protect (set to write-enabled state) b7 b0 1 Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled Enables writing to port P9 direction register (address 03F316) and SI/Oi control register (i=3,4) (addresses 036216 and 036616) 0 : Write-inhibited 1 : Write-enabled (2) Setting system clock control register i (i = 0, 1) (3) Setting the protect (set to write-inhibited state) b7 b0 0 Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 0 : Write-inhibited Enables writing to port P9 direction register (address 03F316) and SI/Oi control register (i=3,4) (addresses 036216 and 036616) 0 : Write-inhibited 1 : Write-enabled (4) Clearing the protect (set to write-enabled state) b7 b0 1 Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 0 : Write-inhibited 1 : Write-enabled Enables writing to port P9 direction register (address 03F316) and SI/Oi control register ( i=3,4) (addresses 036216 and 036616) 1 : Write-enabled (5) Changes in port P9 or changes in SI/Oi control register (i=3,4) Figure 2.1.2. Set-up procedure for protect function 2.1.3 Precaution for Protect (1) The write-enable bit of port 9 direction register and SI/Oi control register (i=3,4) goes to “0” when the next write instruction is executed after write-enabled state is readied. Make changes in input/output and SI/Oi control register (i=3,4) immediately after the instruction that sets “ 1 ” i n the write-enable bit of port P9 direction register and S I/Oi control register (i=3,4)(avoid causing an interrupt). Also take measures to prevent DMA transfer from being executed. 2-5 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2 Timer A Usage 2.2.1 Overview of the timer A usage Timer A is a 16-bit timer. The following is an overview of the timer A usage. (1) Mode Timer A operates in one of the four modes: (a) Timer mode In this mode, the internal count source is counted. Two functions can be selected: the pulse output function that reverses output from a port every time an overflow occurs, or the gate function which controls the count start/stop according to the input signal from a port. • Timer mode operation ............................................................................................................. P2-12 • Timer mode, gate function operation ....................................................................................... P2-14 • Timer mode, pulse output function operation .......................................................................... P2-16 (b) Event counter mode This mode counts the pulses from the outside and the number of overflows in other timers. The freerun type, in which nothing is reloaded from the reload register, can be selected when an underflow occurs. The pulse output function can also be selected. Please refer to the timer mode explanation for details, as the operation is identical. • Event counter mode operation ................................................................................................ P2-18 • Event counter mode, free run type operation .......................................................................... P2-20 Furthermore, Timer A has a 2-phase pulse signal processing function which generates an up count or down count in the event counter mode, depending on the phase of the two input signals. • Operation of the 2-phase pulse signal processing function in normal event counter mode .... P2-22 • Operation of the 2-phase pulse signal processing function in 4-multiplication mode .............. P2-24 (c) One-shot timer mode In this mode, the timer is started by the trigger and stops when the timer goes to “0”. The trigger can be selected from the following 3 types: an external input signal, an overflow of the timer, or a software trigger. The pulse output function can also be selected. Please refer to the timer mode explanation for details, as the operation is identical. • Operation in one-shot timer mode effected by software .......................................................... P2-26 • Operation in one-shot timer mode effected by an external trigger .......................................... P2-28 (d) Pulse width modulation (PWM) mode In this mode, the arbitrary pulses are successively output. Either a 16-bit fixed-period PWM mode or 8-bit variable-period mode can be selected. The trigger for initiating output can also be selected. Please refer to the one-shot timer mode explanation for details, as the operation is identical. • 16-bit PWM mode operation .................................................................................................... P2-30 • 8-bit PWM mode operation ...................................................................................................... P2-32 2-6 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) Count source The internal count source can be selected from f1, f8, f32, and fC32. Clocks f1, f8, and f32 are derived by dividing the CPU's main clock by 1, 8, and 32 respectively. Clock fC32 is derived by dividing the CPU's secondary clock by 32. (3) Count value In timer mode or pulse width modulation mode, [the value set in the timer register + 1] becomes the count value. In event counter mode, [the set value + 1] becomes the count value when a down count is performed, or [FFFF16 - the set value + 1] becomes the count value when an up count is performed. In one-shot timer mode, the value set in the timer register becomes the count value. The counter overflows (or underflows) when a count source equal to a count value is input, and an interrupt occurs. For the pulse output function, the output from the port varies (the value in the port register does not vary). (4) Reading the timer Either in timer mode or in event counter mode, reading the timer register takes out the count at that moment. Read it in 16-bit units. The data either in one-shot timer mode or in pulse width modulation mode is indeterminate. (5) Writing to the timer To write to the timer register when a count is in progress, the value is written only to the reload register. When writing to the timer register when a count is stopped, the value is written both to the reload register and to the counter. Write a value in 16-bit units. (6) Relation between the input/output to/from the timer and the direction register With the output function of the timer, pulses are output regardless of the direction register of the relevant port. To input an external signal to the timer, set the direction register of the relevant port to input. (7) Pins related to timer A (a) TA0IN, TA1IN, TA2IN, TA3IN, TA4IN (b) TA0OUT, TA1OUT, TA2OUT, TA3OUT, TA4OUT Input pins to timer A. Output pins from timer A. They become input pins to timer A when event counter mode is active. (8) Registers related to timer A Figure 2.2.1 shows the memory map of timer A-related registers. Figures 2.2.2 through 2.2.5 show timer A-related registers. 2-7 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 005516 005616 005716 005816 005916 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039616 039716 039816 039916 039A16 Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) Timer A4 interrupt control register (TA4IC) Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) Timer A0 register (TA0) Timer A1 register (TA1) Timer A2 register (TA2) Timer A3 register (TA3) Timer A4 register (TA4) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Figure 2.2.1. Memory map of timer A-related registers Timer Ai mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TAiMR(i=0 to 4) Address When reset 039616 to 039A16 0016 Bit symbol TMOD0 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode RW TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 Function varies with each operation mode Count source select bit (Function varies with each operation mode) Figure 2.2.2. Timer A-related registers (1) 2-8 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Ai register (Note 1) (b15) b7 (b8) b0 b7 b0 Symbol TA0 TA1 TA2 TA3 TA4 Function Address 038716,038616 038916,038816 038B16,038A16 038D16,038C16 038F16,038E16 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set RW • Timer mode Counts an internal count source 000016 to FFFF16 • Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow • One-shot timer mode Counts a one shot width • Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator • Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 000016 to FFFF16 (Note 2,4) 000016 to FFFE16 (Note 3,4) 0016 to FE16 (High-order address) (Low-order address) 0016 to FF16 (Note 3,4) Note 1: Read and write data in 16-bit units. Note 2: When the timer Ai register is set to “000016”, the counter does not operate and the timer Ai interrupt request is not generated. When the pulse is set to output, the pulse does not output from the TAiOUT pin. Note 3: When the timer Ai register is set to “000016”, the pulse width modulator does not operate and the output level of the TAiOUT pin remains “L” level, therefore the timer Ai interrupt request is not generated. This also occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer Ai register are set to “0016”. Note 4: Use MOV instruction to write to this register. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Function 0 : Stops counting 1 : Starts counting RW Figure 2.2.3. Timer A-related registers (2) 2-9 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Up/down flag (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Address 038416 When reset 0016 Bit symbol Bit name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag Function RW TA0UD TA1UD TA2UD TA3UD TA4UD TA2P TA3P TA4P 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause Timer A2 two-phase pulse 0 : two-phase pulse signal processing disabled signal processing select bit 1 : two-phase pulse signal processing enabled (Note 2) Timer A3 two-phase pulse signal processing select bit When not using the two-phase Timer A4 two-phase pulse pulse signal processing function, signal processing select bit set the select bit to “0” Note 1: Use MOV instruction to write to this register. Note 2: Set the TAiIN and TAiOUT pins correspondent port direction registers to “0”. One-shot start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol ONSF Address 038216 When reset 00X000002 Bit symbol TA0OS TA1OS TA2OS TA3OS TA4OS Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag Function 1 : Timer start When read, the value is “0” RW Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. TA0TGL TA0TGH Timer A0 event/trigger select bit b7 b6 0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected Note: Set the corresponding port direction register to “0”. Figure 2.2.4. Timer A-related registers (3) 2-10 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Trigger select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Address 038316 When reset 0016 Bit symbol TA1TGL Bit name Timer A1 event/trigger select bit Function b1 b0 RW TA1TGH TA2TGL 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected b3 b2 Timer A2 event/trigger select bit TA2TGH TA3TGL TA3TGH 0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected b5 b4 Timer A3 event/trigger select bit 0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected b7 b6 TA4TGL TA4TGH Timer A4 event/trigger select bit 0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected Note: Set the corresponding port direction register to “0”. Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 When reset 0XXXXXXX2 Bit symbol Bit name Function RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Figure 2.2.5. Timer A-related registers (4) 2-11 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.2 Operation of Timer A (timer mode) In timer mode, choose functions from those listed in Table 2.2.1. Operations of the circled items are described below. Figure 2.2.6 shows the operation timing, and Figure 2.2.7 shows the set-up procedure. Table 2.2.1. Choosed functions Item Count source Pulse output function O O Set-up Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output Gate function O No gate function Performs count only for the period in which the TAiIN pin is at “L” level Performs count only for the period in which the TAiIN pin is at “H” level Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Ai interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. n = reload register content Counter content (hex) FFFF16 (1) Start count (2) Underflow (3) Stop count n Start count again 000016 Time Set to “1” by software Cleared to “0” by software Set to “1” by software Count start flag “1 ” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timer Ai interrupt request bit “1 ” “0” Figure 2.2.6. Operation timing of timer mode 2-12 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting timer mode and functions b7 b0 0 0 0 0 0 Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) Gate function select bit b4 b3 00: 01: Gate function not available (TAiIN pin is a normal port pin) 0 (Must always be “0” in timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Setting counter value (b15) b7 (b8) b0 b7 b0 Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register [Address 038716, 038616] TA0 [Address 038916, 038816] TA1 [Address 038B16, 038A16] TA2 [Address 038D16, 038C16] TA3 [Address 038F16, 038E16] TA4 Can be set to 000016 to FFFF16 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) b7 b0 Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2.2.7. Set-up procedure of timer mode 2-13 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.3 Operation of Timer A (timer mode, gate function selected) In timer mode, choose functions from those listed in Table 2.2.2. Operations of the circled items are described below. Figure 2.2.8 shows the operation timing, and Figure 2.2.9 shows the set-up procedure. Table 2.2.2. Choosed functions Item Count source Pulse output function O O Set-up Internal count source(f1 / f8 / f32 / fc32) No pulses output Pulses output Gate function No gate function Performs count only for the period in which the TAiIN pin is at “L” level O Performs count only for the period in which the TAiIN pin is at “H” level Operation (1) When the count start flag is set to “1” and the TAiIN pin inputs at “H” level, the counter performs a down count on the count source. (2) When the TAiIN pin inputs at “L” level, the counter holds its value and stops. (3) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer Ai interrupt request bit goes to “1”. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Note • Make the pulse width of the signal input to the TAiIN pin not less than two cycles of the count source. n = reload register content FFFF16 n Counter content (hex) (1) Start count (3) Underflow (2) Stop count (4) Stop count Start count again. 000016 Set to “1” by software Cleared to “0” by software Time Set to “1” by software Count start flag “1” “0” “H” “L ” Cleared to “0” when interrupt request is accepted, or cleared by software TAiIN pin input signal Timer Ai interrupt request bit “1” “0” Figure 2.2.8. Operation timing of timer mode, gate function selected 2-14 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting timer mode and functions b7 b0 0 1 1 0 0 0 Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) Gate function select bit b4 b3 1 1 : Timer counts only when TAiIN pin is held “H” (Note) 0 (Must always be “0” in timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Note: Set the corresponding port direction register to “0”. Setting counter value (b15) b7 (b8) b0 b7 b0 Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register [Address 038716, 038616] TA0 [Address 038916, 038816] TA1 [Address 038B16, 038A16] TA2 [Address 038D16, 038C16] TA3 [Address 038F16, 038E16] TA4 Can be set to 000016 to FFFF16 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) b7 b0 Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2.2.9. Set-up procedure of timer mode, gate function selected 2-15 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.4 Operation of Timer A (timer mode, pulse output function selected) In timer mode, choose functions from those listed in Table 2.2.3. Operations of the circled items are described below. Figure 2.2.10 shows the operation timing, and Figure 2.2.11 shows the set-up procedure. Table 2.2.3. Choosed functions Item Count source Pulse output function O Gate function O O Internal count source(f1 / f8 / f32 / fc32) No pulses output Pulses output No gate function Performs count only for the period in which the TAiIN pin is at “L” level Performs count only for the period in which the TAiIN pin is at “H” level Set-up Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded and the count continues. At this time, the timer Ai interrupt request bit goes to “1”. Also, the output polarity of the TAiOUT pin reverses. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TAiOUT pin outputs an “L” level. n = reload register content FFFF16 (1) Start count (2) Underflow (3) Stop count Counter content (hex) n Start count again 000016 Time Set to “1” by software Cleared to “0” by software Set to “1” by software Count start flag “1” “0” Pulse output from “H” TAiOUT pin “L” Cleared to “0” when interrupt request is accepted, or cleared by software Timer Ai interrupt request bit “1” “0” Figure 2.2.10. Operation timing of timer mode, pulse output function selected 2-16 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting timer mode and functions b7 b0 0 0 1 0 0 Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Selection of timer mode 1 : Pulse is output (Note) (TAiOUT pin is a pulse output pin) Gate function select bit b4 b3 00: 01: Gate function not available (TAiIN pin is a normal port pin) 0 (Must always be “0” in timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Note: The settings of the corresponding port register and port direction register are invalid. Setting counter value (b15) b7 (b8) b0 b7 b0 Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register [Address 038716, 038616] TA0 [Address 038916, 038816] TA1 [Address 038B16, 038A16] TA2 [Address 038D16, 038C16] TA3 [Address 038F16, 038E16] TA4 Can be set to 000016 to FFFF16 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) b7 b0 Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2.2.11. Set-up procedure of timer mode, pulse output function selected 2-17 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.5 Operation of Timer A (event counter mode, reload type selected) In event counter mode, choose functions from those listed in Table 2.2.4. Operations of the circled items are described below. Figure 2.2.12 shows the operation timing, and Figure 2.2.13 shows the set-up procedure. Table 2.2.4. Choosed functions Item Count source O Set-up Input signal to TAiIN (counting falling edges) Input signal to TAiIN (counting rising edges) Timer overflow (TB2/TAj overflow) Item Pulse output function O Set-up No pulses output Pulses output Count operation type O Reload type Free-run type Factor for switching between up and down O Content of up/down flag Input signal to TAiOUT Note: j = i – 1, but j = 4 when i = 0. Operation (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Ai interrupt request bit goes to “1”. (3) If switching from an up count to a down count or vice versa while a count is in progress, the switch takes effect from the next effective edge of the count source. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. (5) If an overflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Ai interrupt request bit goes to “1”. n = reload register content FFFF16 (3) Switch count (1) Start count n (2) Underflow (5) Overflow Counter content (hex) (4) Stop count Start count again 000016 Set to “1” by software Cleared to “0” by software Set to “1” by software Time Count start flag Up/down flag “1” “0” “1” “0” Set to “1” by software Cleared to “0” when interrupt request is accepted, or cleared by software Timer Ai interrupt “1” request bit “0” Figure 2.2.12. Operation timing of event counter mode, reload type selected 2-18 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting event counter mode and functions b7 b0 0 0 0 0 0 0 1 Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) Count polarity select bit 0 : Counts external signal's falling edge Up/down switching cause select bit 0 : Up/down flag's content 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type Invalid in event counter mode (i = 0, 1) Invalid when not using two-phase pulse signal processing(i = 2 to 4) Setting up/down flag b7 b0 0 0 0 Up/down flag [Address 038416] UDF Timer A0 up/down flag 0 : Down count Timer A1 up/down flag 0 : Down count Timer A2 up/down flag 0 : Down count Timer A3 up/down flag 0 : Down count Timer A4 up/down flag 0 : Down count When not using the 2-phase pulse signal processing function, set the select bit to “0”. Setting one-shot start flag and trigger select register b7 b0 b7 b0 One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit b7 b6 Trigger select register [Address 038316] TRGSR Timer A1 event/trigger select bit b1 b0 0 0 : Input on TA0IN is selected (Note) 0 0 : Input on TA1IN is selected (Note) Timer A2 event/trigger select bit b3 b2 0 0 : Input on TA2IN is selected (Note) Timer A3 event/trigger select bit b5 b4 0 0 : Input on TA3IN is selected (Note) Timer A4 event/trigger select bit b7 b6 Note: Set the corresponding port direction register to “0”. 0 0 : Input on TA4IN is selected (Note) Setting counter value (b15) b7 (b8) b0 b7 b0 Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register [Address 038716, 038616] TA0 [Address 038916, 038816] TA1 [Address 038B16, 038A16] TA2 [Address 038D16, 038C16] TA3 [Address 038F16, 038E16] TA4 Can be set to 000016 to FFFF16 Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2.2.13. Set-up procedure of event counter mode, reload type selected 2-19 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.6 Operation of Timer A (event counter mode, free run type selected) In event counter mode, choose functions from those listed in Table 2.2.5. Operations of the circled items are described below. Figure 2.2.14 shows the operation timing, and Figure 2.2.15 shows the set-up procedure. Table 2.2.5. Choosed functions Item Count source O Set-up Input signal to TAiIN (counting falling edges) Input signal to TAiIN (counting rising edges) Timer overflow (TB2/TAj overflow) Item Pulse output function O Set-up No pulses output Pulses output Count operation type O Factor for switching between up and down O Reload type Free-run type Content of up/down flag Input signal to TAiOUT Note: j = i – 1, but j = 4 when i = 0 Operation (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer Ai interrupt request bit goes to “1”. (3) If switching from an up count to a down count or vice versa while a count is in progress, the switch takes effect from the next effective edge of the count source. (4) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer Ai interrupt request bit goes to “1”. n = reload register content (2) Underflow (3) Switch count (4) Overflow FFFF16 Counter content (hex) (1) Start count n 000016 Time Set to “1” by software Count start flag “1” “0” Set to “1” by software Up/down flag “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timer Ai interrupt request bit “1” “0” Figure 2.2.14. Operation timing of event counter mode, free run type selected 2-20 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting event counter mode and functions b7 b0 1 0 0 0 0 0 1 Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TAiOUT pin is a normal port pin) Count polarity select bit 0 : Counts external signal's falling edge Up/down switching cause select bit 0 : Up/down flag's content 0 (Must always be “0” in event counter mode) Count operation type select bit 1 : Free-run type Invalid in event counter mode (i = 0, 1) Invalid when not using two-phase pulse signal processing(i = 2 to 4) Setting up/down flag b7 b0 0 0 0 Up/down flag [Address 038416] UDF Timer A0 up/down flag 0 : Down count Timer A1 up/down flag 0 : Down count Timer A2 up/down flag 0 : Down count Timer A3 up/down flag 0 : Down count Timer A4 up/down flag 0 : Down count When not using the 2-phase pulse signal processing function, be sure to set the select bit to “0”. Setting one-shot start flag and trigger select register b7 b0 One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit b7 b6 b7 b0 Trigger select register [Address 038316] TRGSR Timer A1 event/trigger select bit b1 b0 0 0 : Input on TA0IN is selected (Note) 0 0 : Input on TA1IN is selected (Note) Timer A2 event/trigger select bit b3 b2 0 0 : Input on TA2IN is selected (Note) Timer A3 event/trigger select bit b5 b4 0 0 : Input on TA3IN is selected (Note) Note: Set the corresponding port direction register to “0”. Timer A4 event/trigger select bit b7 b6 0 0 : Input on TA4IN is selected (Note) Setting counter value (b15) b7 (b8) b0 b7 b0 Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register [Address 038716, 038616] TA0 [Address 038916, 038816] TA1 [Address 038B16, 038A16] TA2 [Address 038D16, 038C16] TA3 [Address 038F16, 038E16] TA4 Can be set to 000016 to FFFF16 Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2.2.15. Set-up procedure of event counter mode, free run type selected 2-21 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.7 Operation of timer A (2-phase pulse signal process in event counter mode, normal mode selected) In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table 2.2.6. Operations of the circled items are described below. Figure 2.2.16 shows the operation timing, and Figure 2.2.17 shows the set-up procedure. Table 2.2.6. Choosed functions Item Count operation type O 2-phase pulses process (Note) O Reload type Free run type Normal processing 4-multiplication processing Set-up Note: Timer A3 alone can be selected. Timer A2 is solely used for normal processes, and timer A4 is solely used for 4 multiplication processes. Operation (1) Setting the count start flag to “1” causes the counter to count effective edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer Ai interrupt request bit goes to “1”. (3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the timer Ai interrupt request bit goes to “1”. Note • The up count or down count conditions are as follows: If a rising edge is present at the TAiIN pin when the input signal level to the TAiOUT pin is “H”, an up count is performed. If a falling edge is present at the TAiIN pin when the input signal level to the TAiOUT pin is “H”, a down count is performed. (1) Start count Input pulse TAiOUT TAiIN “H” “L” “H” “L” (2) Underflow (3) Overflow Counter content (hex) FFFF16 000016 Set to “1” by software “1” “0” Time Count start flag Timer Ai interrupt “1” request bit “0” Cleared to “0” when interrupt request is accepted, or cleared by software Figure 2.2.16. Operation timing of 2-phase pulse signal process in event counter mode, normal mode selected 2-22 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting event counter mode and functions b7 b0 0 1 0 1 0 0 0 1 Timer Ai mode register (i= 2, 3) [Address 039816, 039916] TAiMR (i= 2, 3) Selection of event counter mode 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) 1 (Must always be “1” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) Count operation type select bit 1 : Free-run type Two-phase pulse signal processing operation select bit (Note 1) 0 : Normal processing operation Note 1: This bit is valid for timer A3 mode register. For timer A2 mode register, this bit can be “0” or “1”. Setting two-phase pulse signal processing select bit b7 b0 Up/down flag [Address 038416] UDF Timer A2 two-phase pulse signal processing select bit (Note 2) 1 : Two-phase pulse signal processing enabled Timer A3 two-phase pulse signal processing select bit (Note 2) 1 : Two-phase pulse signal processing enabled Note 2: Set the TAiIN, TAiOUT corresponding port direction register to “0”. Setting trigger select register b7 b0 Trigger select register [Address 038316] TRGSR Timer A2 event/trigger select bit b3 b2 0 0 : Input on TA2IN is selected (Note 3) Timer A3 event/trigger select bit b5 b4 0 0 : Input on TA3IN is selected (Note 3) Note 3: Set the corresponding port direction register to “0”. Setting counter value (b15) b7 (b8) b0 b7 b0 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Can be set to 000016 to FFFF16 Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer A2 count start flag Timer A3 count start flag Start count Figure 2.2.17. Set-up procedure of 2-phase pulse signal process in event counter mode, normal mode selected 2-23 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.8 Operation of timer A (2-phase pulse signal process in event counter mode, multiply-by-4 mode selected) In processing 2-phase pulse signals in event counter mode, choose functions from those listed in Table 2.2.7. Operations of the circled items are described below. Figure 2.2.18 shows the operation timing, and Figure 2.2.19 shows the set-up procedure. Table 2.2.7. Choosed functions Item Count operation type O Set-up Reload type Free run type Item Processing 2 phase pulses (Note) Set-up Normal processing O 4-multiplication processing Note: Timer A3 alone can be selected. Timer A2 is solely used for normal processes, and timer A4 is solely used for 4multiplication processes. Operation (1) Setting the count start flag to “1” causes the counter to count effective edges of the count source. (2) Even if an underflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the interrupt request bit goes to “1”. (3) Even if an overflow occurs, the content of the reload register is not reloaded, but the count continues. At this time, the interrupt request bit goes to “1”. Note • The up count or down count conditions are as follows: Table 2.2.8. The up count or down count conditions Input signal to the TAiOUT pin Up count “H” level “L” level Rising Falling Input signal to the TAiIN pin Rising Falling “L” level “H” level Down count Input signal to the TAiOUT pin “H” level “L” level Rising Falling Input signal to the TAiIN pin Falling Rising “H” level “L” level (1) Start count Input pulse TAiOUT TAiIN “H” “L” “H” “L” Counter content (hex) FFFF16 000016 Set to “1” by software (2) Underflow Count start flag “1” Cleared to “0” when interrupt request is accepted, or cleared by software “0” Timer Ai interrupt “1” request bit “0” Time (3) Overflow Figure 2.2.18. Operation timing of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected 2-24 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting event counter mode and functions b7 b0 1 1 0 1 0 0 0 1 Timer Ai mode register (i= 3, 4) [Address 039916, 039A16] TAiMR (i= 3, 4) Selection of event counter mode 0 (Must always be “0” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) 1 (Must always be “1” when using two-phase pulse signal processing) 0 (Must always be “0” when using two-phase pulse signal processing) Count operation type select bit 1 : Free-run type Two-phase pulse signal processing operation select bit (Note 1) 1 : Multiply-by-4 processing operation Note 1: This bit is valid for timer A3 mode register. For timer A4 mode register, this bit can be “0” or “1”. Setting two-phase pulse signal processing select bit b7 b0 Up/down flag [address 038416] UDF Timer A3 two-phase pulse signal processing select bit (Note 2) 1 : Two-phase pulse signal processing enabled Timer A4 two-phase pulse signal processing select bit (Note 2) 1 : Two-phase pulse signal processing enabled Note 2: Set the TAiIN, TAiOUT corresponding port direction register to “0”. Setting trigger select register b7 b0 Trigger select register [Address 038316] TRGSR Timer A3 event/trigger select bit b5 b4 0 0 : Input on TA3IN is selected (Note 3) Timer A4 event/trigger select bit b7 b6 0 0 : Input on TA4IN is selected (Note 3) Note 3: Set the corresponding port direction register to “0”. Setting counter value (b15) b7 (b8) b0 b7 b0 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Can be set to 000016 to FFFF16 Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer A3 count start flag Timer A4 count start flag Start count Figure 2.2.19. Set-up procedure of 2-phase pulse signal process in event counter mode, multiply-by-4 mode selected 2-25 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.9 Operation of Timer A (one-shot timer mode) In one-shot timer mode, choose functions from those listed in Table 2.2.9. Operations of the circled items are described below. Figure 2.2.20 shows the operation timing, and Figure 2.2.21 shows the set-up procedure. Table 2.2.9. Choosed functions Item Count source Pulse output function O Count start condition O Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output External trigger input (falling edge of input signal to the TAiIN pin) External trigger input (rising edge of input signal to the TAiIN pin) Timer overflow (TB2/TAj/TAk overflow) O Writing “1” to the one-shot start flag Set-up Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. Operation (1) Setting the one-shot start flag to “1” with the count start flag set to “1” causes the counter to perform a down count on the count source. At this time, the TAiOUT pin outputs an “H” level. (2) The instant the value of the counter becomes “000016”, the TAiOUT pin outputs an “L” level, and the counter reloads the content of the reload register and stops counting. At this time, the timer Ai interrupt request bit goes to “1”. (3) If a trigger occurs while a count is in progress, the counter reloads the value in the reload register again and continues counting. The reload timing is in step with the next count source input after the trigger. (4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the reload register. Also, the TAiOUT pin outputs an “L” level. At this time, the timer Ai interrupt request bit goes to “1”. Note • When the timer Ai register is set to “000016”, the counter does not operate and the timer Ai interrupt request is not generated. When the pulse is set to output, the pulse does not output from the TAiOUT pin. n = reload register content Counter content (hex) FFFF16 n (1) Start count (2) Stop count (3) Start count Start count (4) Stop count Reload Reload Reload 000116 Set to “1” by software Count start flag Write signal to one-shot start flag One-shot pulse output “H” from TAiOUT pin “L” Timer Ai interrupt request bit “1” “0” “1” “0” Cleared to “0” by software Time 1 / fi X (n) 1 / fi X (n+1) Cleared to “0” when interrupt request is accepted, or cleared by software Figure 2.2.20. Operation timing of one-shot mode 2-26 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting one-shot timer mode and functions b7 b0 0 0 1 1 0 Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Selection of one-shot timer mode Pulse output function select bit 1 : Pulse is output External trigger select bit When internal trigger is selected, this bit can be “1” or “0” Trigger select bit 0 : When the one-shot start flag is set “1” 0 (Must always be “0” in one-shot timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Clearing timer Ai interrupt request bit b7 b0 Refer to 'Precaution for Timer A (one shot timer mode)' 0 Timer Ai interrupt control register [Address 005516 to 005916] TAiIC (i=0 to 4) Interrupt request bit Setting one-shot timer's time (b15) b7 (b8) b0 b7 b0 Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register [Address 038716, 038616] TA0 [Address 038916, 038816] TA1 [Address 038B16, 038A16] TA2 [Address 038D16, 038C16] TA3 [Address 038F16, 038E16] TA4 Can be set to 000116 to FFFF16 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) b7 b0 Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Setting one-shot start flag b7 b0 One-shot start flag [Address 038216] ONSF Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag Start count Figure 2.2.21. Set-up procedure of one-shot mode 2-27 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.10 Operation of Timer A (one-shot timer mode, external trigger selected) In one-shot timer mode, choose functions from those listed in Table 2.2.10. Operations of the circled items are described below. Figure 2.2.22 shows the operation timing, and Figure 2.2.23 shows the set-up procedure. Table 2.2.10. Choosed functions Item Count source Pulse output function O Count start condition O O Set-up Internal count source (f1 / f8 / f32 / fc32) No pulses output Pulses output External trigger input (falling edge of input signal to the TAiIN pin) External trigger input (rising edge of input signal to the TAiIN pin) Timer overflow (TB2/TAj/TAk overflow) Writing “1” to the one-shot start flag Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. Operation (1) If the TAiIN pin input level changes from “L” to “H” with the count start flag set to “1”, the counter performs a down count on the count source. At this time, the TAiOUT pin output level goes to “H” level. (2) If the value of the counter becomes “000016”, the TAiOUT pin outputs an “L” level, and the counter reloads the content of the reload register and stops counting. At this time, the timer Ai interrupt request bit goes to “1”. (3) If a trigger occurs while a count is in progress, the counter reloads the value of the reload register again and continues counting. The reload timing is in step with the next count source input after the trigger. (4) Setting the count start flag to “0” causes the counter to stop and to reload the content of the reload register. Also, the TAiOUT pin outputs an “L” level. At this time, the timer Ai interrupt request bit goes to “1”. Note • When the timer Ai register is set to “000016”, the counter does not operate and the timer Ai interrupt request is not generated. When the pulse is set to output, the pulse does not output from the TAiOUT pin. FFFF16 n = reload register content (1) Start count (2) Stop count (3) Start count Counter content (hex) Start count (4) Stop count n Reload Reload Reload 000116 Set to “1” by software Count start flag TAiIN pin input signal “1” “0” “H” “L” 1 / fi X (n) One-shot pulse output “H” from TAiOUT pin “L ” Timer Ai interrupt request bit “1” “0” Cleared to “0” by software Time Trigger during count 1 / fi X (n+1) Cleared to “0” when interrupt request is accepted, or cleared by software Figure 2.2.22. Operation timing of one-shot mode, external trigger selected 2-28 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting one-shot timer mode and functions b7 b0 0 1 1 1 1 0 Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Selection of one-shot timer mode Pulse output function select bit 1 : Pulse is output External trigger select bit 1 : Rising edge of TAiIN pin's input signal Trigger select bit 1 : Selected by event/trigger select register 0 (Must always be “0” in one-shot timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Clearing timer Ai interrupt request bit b7 b0 Refer to 'Precaution for Timer A (one shot timer mode)' 0 Timer Ai interrupt control register [Address 005516 to 005916] TAiIC (i=0 to 4) Interrupt request bit Setting event/trigger select bit b7 b0 b7 b0 One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit b7 b6 Trigger select register [Address 038316] TRGSR Timer A1 event/trigger select bit b1 b0 0 0 : Input on TA0IN is selected (Note) 0 0 : Input on TA1IN is selected (Note) Timer A2 event/trigger select bit b3 b2 0 0 : Input on TA2IN is selected (Note) Timer A3 event/trigger select bit b5 b4 0 0 : Input on TA3IN is selected (Note) Timer A4 event/trigger select bit Note: Set the corresponding port direction register to “0”. b7 b6 0 0 : Input on TA4IN is selected (Note) Setting one-shot timer's time (b15) b7 (b8) b0 b7 b0 Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register [Address 038716, 038616] TA0 [Address 038916, 038816] TA1 [Address 038B16, 038A16] TA2 [Address 038D16, 038C16] TA3 [Address 038F16, 038E16] TA4 Can be set to 000116 to FFFF16 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) b7 b0 Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2.2.23. Set-up procedure of one-shot mode, external trigger selected 2-29 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.11 Operation of Timer A (pulse width modulation mode, 16-bit PWM mode selected) In pulse width modulation mode, choose functions from those listed in Table 2.2.11. Operations of the circled items are described below. Figure 2.2.24 shows the operation timing, and Figure 2.2.25 shows the set-up procedure. Table 2.2.11. Choosed functions Item Count source PWM mode O O Set-up Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM Count start condition O External trigger input (falling edge of input signal to the TAiIN pin) External trigger input (rising edge of input signal to the TAiIN pin) Timer overflow (TB2/TAj/TAk overflow) Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. Operation (1) If the TAiIN pin input level changes from “L” to “H” with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TAiOUT pin outputs an “H” level. (2) The TAiOUT pin output level changes from “H” to “L” when a set time period elapses. At this time, the timer Ai interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TAiOUT outputs an “L” level. Note • The period of PWM pulses becomes (216 – 1)/fi, and the “H” level pulse width becomes n/fi. If the timer Ai register is set to “000016”, the pulse width modulator does not work, and the TAiOUT pin outputs “L” level, therefore the timer Ai interrupt request is not generated. (fi : frequency of the count source f1, f8, f32, fC32; n : value of the timer) Conditions: Reload register = 000316, external trigger (rising edge of TAiIN pin input signal) is selected 1 / fi X (2 Count source “H” “L” Trigger is not generated by this signal Set to “1” by software Count start flag “1” “0” (1) Start count (2) Output level “H” to “L” 1 / fi X n PWM pulse output from TAiOUT pin “H” “L” “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software (3) One period is complete (4) Stop count Cleared to “0” by software 16 –1) TAiIN pin input signal Timer Ai interrupt request bit Note: n = 000016 to FFFE16 Figure 2.2.24. Operation timing of pulse width modulation mode, 16-bit PWM mode selected 2-30 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting PWM mode and functions b7 b0 0 1 1 1 1 1 Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Selection of PWM mode 1 (Must always be “1” in PWM mode) External trigger select bit 1 : Rising edge of TAiIN pin's input signal (Note 1) Trigger select bit 1 : Selected by event/trigger select register 16/8-bit PWM mode select bit 0 : Functions as a 16-bit pulse width modulator Count source select bit b7 b6 Note 1: Set the corresponding port direction register to “0”. b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 0 1 : f8 1 0 : f32 11 : fC32 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Clearing timer Ai interrupt request bit b7 b0 Refer to 'Precaution for Timer A (pulse width modulation mode)' 0 Timer Ai interrupt control register [Address 005516 to 005916] TAiIC (i=0 to 4) Interrupt request bit Setting event/trigger select bit b7 b0 b7 b0 One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit b7 b6 Trigger select register [Address 038316] TRGSR Timer A1 event/trigger select bit b1 b0 0 0 : Input on TA0IN is selected (Note 2) 0 0 : Input on TA1IN is selected (Note 2) Timer A2 event/trigger select bit b3 b2 0 0 : Input on TA2IN is selected (Note 2) Timer A3 event/trigger select bit b5 b4 0 0 : Input on TA3IN is selected (Note 2) Note 2: Set the corresponding port direction register to “0”. Timer A4 event/trigger select bit b7 b6 0 0 : Input on TA4IN is selected (Note 2) Setting PWM pulse's “H” level width (b15) b7 (b8) b0 b7 b0 Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register [Address 038716, 038616] TA0 [Address 038916, 038816] TA1 [Address 038B16, 038A16] TA2 [Address 038D16, 038C16] TA3 [Address 038F16, 038E16] TA4 Can be set to 000016 to FFFE16 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) b7 b0 Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Setting count starts flag b7 b0 Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2.2.25. Set-up procedure of pulse width modulation mode, 16-bit PWM mode selected 2-31 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.12 Operation of Timer A (pulse width modulation mode, 8-bit PWM mode selected) In pulse width modulation mode, choose functions from those listed in Table 2.2.12. Operations of the circled items are described below. Figure 2.2.26 shows the operation timing, and Figure 2.2.27 shows the set-up procedure. Table 2.2.12. Choosed functions Item Count source PWM mode O Count start condition O O Set-up Internal count source (f1 / f8 / f32 / fc32) 16-bit PWM 8-bit PWM External trigger input (falling edge of input signal to the TAiIN pin) External trigger input (rising edge of input signal to the TAiIN pin) Timer overflow (TB2/TAj/TAk overflow) Note: j = i – 1, but j = 4 when i = 0; k = i + 1, but k = 0 when i = 4. Operation (1) If the TAiIN pin input level changes from “H” to “L” with the count start flag set to “1”, the counter performs a down count on the count source. Also, the TAiOUT pin outputs an “H” level. (2) The TAiOUT pin output level changes from “H” to “L” when a set time period elapses. At this time, the timer Ai interrupt request bit goes to “1”. (3) The counter reloads the content of the reload register every time PWM pulses are output for one cycle, and continues counting. (4) Setting the count start flag to “0” causes the counter to hold its value and to stop. Also, the TAiOUT pin outputs an “L” level. • The period of PWM pulses becomes (m + 1) X (28 – 1) / fi, and the “H” level pulse width becomes n X (m + 1) / fi. If “0016” is set in the eight higher-order bits of the timer Ai register, the pulse width modulator does not work, and the TAiOUT pin outputs “L” level, therefore the timer Ai interrupt request is not generated. (fi : frequency of the count source f1, f8, f32, fC32; n : value of the timer) • When a trigger is generated, the TAiout pin outputs “L” level of same amplitude as “H” level of the set PWM pulse, after which it starts PWM pulse output. Conditions: Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected 1 / fi X (m + 1) X (2 – 1) Count source (Note 1) 8 Note (4) Stop count Count start flag TAiIN pin input “1” “0” “H” “L” (1) Start count (2) Output level “H” to “L” (3) One period is complete Underflow signal of 8-bit “H” prescaler (Note 2) “L” PWM pulse output from TAiOUT pin Timer Ai interrupt request bit “H” “L” “1” “0” 1 / fi X (m+1) 1 / fi X (m + 1) X n Cleared to “0” when interrupt request is accepted, or cleared by software Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FE16. Figure 2.2.26. Operation timing of pulse width modulation mode, with 8-bit PWM mode selected 2-32 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting PWM mode and function b7 b0 1 1 0 1 1 1 Timer Ai mode register (i=0 to 4) [Address 039616 to 039A16] TAiMR (i=0 to 4) Selection of PWM mode 1 (Must always be “1” in PWM mode) External trigger select bit 0 : Falling edge of TAiIN pin's input signal (Note1) Trigger select bit 1 : Selected by event/trigger select register 16/8-bit PWM mode select bit 1: Functions as an 8-bit pulse width modulator Count source select bit b7 b6 Note 1: Set the corresponding port direction register to “0”. b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Clearing timer Ai interrupt request bit b7 b0 Refer to 'Precaution for Timer A (pulse width modulation mode)' 0 Timer Ai interrupt control register [Address 005516 to 005916] TAiIC (i=0 to 4) Interrupt request bit Setting event/trigger select bit b7 b0 b7 b0 One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit b7 b6 Trigger select register [Address 038316] TRGSR Timer A1 event/trigger select bit b1 b0 0 0 : Input on TA0IN is selected (Note 2) 0 0 : Input on TA1IN is selected (Note 2) Timer A2 event/trigger select bit b3 b2 0 0 : Input on TA2IN is selected (Note 2) Timer A3 event/trigger select bit b5 b4 0 0 : Input on TA3IN is selected (Note 2) Timer A4 event/trigger select bit Note 2: Set the corresponding port direction register to “0”. b7 b6 0 0 : Input on TA4IN is selected (Note 2) Setting PWM pulse's period and “H” level width (b15) b7 (b8) b0 b7 Timer A0 register [Address 038716, 038616] TA0 Timer A1 register [Address 038916, 038816] TA1 Timer A2 register [Address 038B16, 038A16] TA2 Timer A3 register [Address 038D16, 038C16] TA3 Timer A4 register [Address 038F16, 038E16] TA4 Can be set to 0016 to FF16 b0 Can be set to 0016 to FE16 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) b7 b0 Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Start count Figure 2.2.27. Set-up procedure of pulse width modulation mode, 8-bit PWM mode selected 2-33 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.13 Precautions for Timer A (timer mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing shown in Figure 2.2.28 gets “FFFF16”. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. Reload Counter value (Hex.) 2 1 0 n n–1 Read value (Hex.) 2 1 0 FFFF n–1 Time n = reload register content Figure 2.2.28. Reading timer Ai register 2-34 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.14 Precautions for Timer A (event counter mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing shown in Figure 2.2.29 gets “FFFF16” by underflow or “000016” by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (3) Please note the standards for the differences between the 2 pulses used in the 2-phase pulse signals input signals to the TAiIN pin and TAiOUT pin (i = 2, 3, 4), as shown in Figure 2.2.30. (4) When free run type is selected, if count is stopped, set a value in the timer Ai register again. (1) Down count Reload (2) Up count R eload Counter value (Hex.) Read value (Hex.) 2 1 0 n n–1 Counter value (Hex.) Read value (Hex.) FFFD FFFE FFFF n n+1 2 1 0 FFFF n – 1 Time FFFD FFFE FFFF 0000 n + 1 Time n = reload register content n = reload register content Figure 2.2.29. Reading timer Ai register T1 TA2IN TA3IN TA4IN TA2OUT TA3OUT TA4OUT Vcc = 5V, f(XIN) = 16MHz T1 (Min.) 800ns T2, T3 (Min.) 200ns Vcc = 3V, f(XIN) = 10MHz, one-wait T2 T3 T1 (Min.) 2µs T2, T3 (Min.) 500ns Figure 2.2.30. Standard of 2-phase pulses 2-35 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.15 Precautions for Timer A (one-shot timer mode) (1) At reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) Setting the count start flag to “0” while a count is in progress causes as follows: • The counter stops counting and a content of reload register is reloaded. • The TAiOUT pin outputs “L” level. • The interrupt request generated and the timer Ai interrupt request bit goes to “1”. (3) The output from the one-shot timer synchronizes with the count source generated internally. Therefore, when an external trigger has been selected, a delay of one cycle of the maximum count source occurs between the trigger input to the TAiIN pin and the one-shot timer output. (4) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the following procedures: • Selecting one-shot timer mode after reset. • Changing operation mode from timer mode to one-shot timer mode. • Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. (5) If a trigger occurs while a count is in progress, after the counter performs one down count following the reoccurrence of a trigger, the reload register contents are reloaded, and the count continues. To generate a trigger while a count is in progress, generate the second trigger after an elapse longer than one cycle of the timer's count source after the previous trigger occurred. TAiIN pin input signal “H” “L” Trigger input Count source One-shot pulse output from TAiOUT pin Start one-shot pulse output Note: The above applies when an external trigger (falling edge of TAiIN pin input signal) is selected. Figure 2.2.31. One-shot timer delay 2-36 Mitsubishi microcomputers Timer A M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.2.16 Precautions for Timer A (pulse width modulation mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Ai register, then set the flag to “1”. (2) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with any of the following procedures: • Selecting PWM mode after reset. • Changing operation mode from timer mode to PWM mode. • Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the above listed changes have been made. (3) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer Ai interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes “1”. 2-37 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.3 Timer B Usage 2.3.1 Overview of the timer B usage Timer B is a 16-bit timer. The following is an overview of the timer B usage. (1) Mode Timer B operates in one of three modes: (a) Timer mode The internal count source is counted. • Operation in timer mode .......................................................................................................... P2-42 (b) Event counter mode The number of pulses coming from outside and the number of the timer overflows are counted. • Operation in event counter mode ............................................................................................ P2-44 (c) Pulse period measurement/pulse width measurement mode External pulse period or external pulse widths are measured. If pulse period measurement mode is selected, the periods of input pulses are continuously measured. If pulse width measurement mode is selected, widths of “H” level pulses and those of “L” level pulses are continuously measured. • Operation in pulse period measurement mode ....................................................................... P2-46 • Operation in pulse width measurement mode ......................................................................... P2-48 (2) Count source An internal count source can be selected from f1, f8, f32, and fC32. f1, f8, and f32 are clocks obtained by dividing the CPU main clock by 1, 8, and 32 respectively. fC32 is the clock obtained by dividing the CPU secondary clock by 32. (3) Count value The count value equals [the value set in the timer register + 1]. The counter underflows when a count source equal to a count value is input, and an interrupt request occurs. (4) Reading the timer In timer mode or event counter mode, the count value at the time of reading the timer register will be read. Read the register in 16-bit increments. In both the pulse period measurement mode and pulse width measurement mode, an indeterminate value is read until the second effective edge is input after a count is started, otherwise, the measurement results are read. (5) Writing to the timer When writing to the timer register while a count is in progress, the value is written only to the reload register. When writing to the timer register while a count has stopped, the value is written both to the reload register and the count. Write the value in 16-bit increments. The timer register cannot be written to in either the pulse period measurement mode or the pulse width measurement mode. 2-38 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (6) Input to the timer and the direction register To input an external signal to the timer, set the direction register of the relevant port to input. (7) Pins related to timer B (a) TB0IN, TB1IN, TB2IN, TB3IN, TB4IN, TB5IN:Input pins to timer B. (8) Registers related to timer B Figure 2.3.1 shows the memory map of timer B-related registers. Figures 2.3.2 and 2.3.3 show timer B-related registers. 004516 004516 004716 034016 005A16 005B16 005C16 035016 035116 035216 035316 035416 035516 035B16 035C16 035D16 038016 038116 039016 039116 039216 039316 039416 039516 039B16 039C16 039D16 Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) Timer B3,4,5 count start flag (TBSR) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5) Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register (TB5MR) Count start flag (TABSR) Clock prescaler reset flag (CPSRF) Timer B0 register (TB0) Timer B1 register (TB1) Timer B2 register (TB2) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) Figure 2.3.1. Memory map of timer B-related registers 2-39 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Bi mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address TBiMR(i = 0 to 5) 039B16 to 039D16 035B16 to 035D16 When reset 00XX00002 00XX00002 Bit symbol TMOD0 TMOD1 Bit name Operation mode select bit b1 b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Must not be set. R W MR0 MR1 MR2 Function varies with each operation mode (Note 1) (Note 2) MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode) Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5. Figure 2.3.2. Timer B-related registers (1) 2-40 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Timer Bi register (Note) (b15) b7 (b8) b0 b7 b0 Symbol TB0 TB1 TB2 TB3 TB4 TB5 Address 039116, 039016 039316, 039216 039516, 039416 035116, 035016 035316, 035216 035516, 035416 When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Values that can be set Function • Timer mode Counts the timer's period • Event counter mode Counts external pulses input or a timer overflow • Pulse period / pulse width measurement mode Measures a pulse period or width RW 000016 to FFFF16 000016 to FFFF16 Note: Read and write data in 16-bit units. Count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 038016 When reset 0016 Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit name Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag Function 0 : Stops counting 1 : Starts counting RW Timer B3, 4, 5 count start flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBSR Address 034016 When reset 000XXXXX2 Bit symbol Nothing is assigned. Bit name Function RW In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. TB3S TB4S TB5S Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag 0 : Stops counting 1 : Starts counting Clock prescaler reset flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol CPSRF Address 038116 When reset 0XXXXXXX2 Bit symbol Nothing is assigned. Bit name Function RW In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Figure 2.3.3. Timer B-related registers (2) 2-41 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.3.2 Operation of Timer B (timer mode) In timer mode, choose functions from those listed in Table 2.3.1. Operations of the circled items are described below. Figure 2.3.4 shows the operation timing, and Figure 2.3.5 shows the set-up procedure. Table 2.3.1. Choosed functions Item Count source O Set-up Internal count source (f1 / f8 / f32 / fc32) Operation (1) Setting the count start flag to “1” causes the counter to perform a down count on the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the counter continues counting. At this time, the timer Bi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. n = reload register content Counter content (hex) FFFF16 (1) Start count (2) Underflow (3) Stop count n Start count again 000016 Time Set to “1” by software Cleared to “0” by software Set to “1” by software Count start flag “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timer Bi interrupt “1” request bit “0” Figure 2.3.4. Operation timing of timer mode 2-42 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting timer mode and functions b7 b0 0 0 Timer Bi mode register (i=0 to 5) [Address 039B16 to 039D16, 035B16 to 035D16] TBiMR (i=0 to 5) Selection of timer mode Invalid in timer mode Can be “0” or “1” Fixed to “0” in timer mode ( i = 0, 3) In an attempt to write to this bit, write “0” (i = 1, 2, 4, 5) Invalid in timer mode Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Setting counter value (b15) b7 (b8) b0 b7 b0 Timer B0 register Timer B1 register Timer B2 register Timer B3 register Timer B4 register Timer B5 register [Address 039116, 039016] [Address 039316, 039216] [Address 039516, 039416] [Address 035116, 035016] [Address 035316, 035216] [Address 035516, 035416] TB0 TB1 TB2 TB3 TB4 TB5 Can be set to 000016 to FFFF16 Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) b7 b0 Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag b7 b0 Timer B3,4,5 count start flag [Address 034016] TBSR Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag Start count Figure 2.3.5. Set-up procedure of timer mode 2-43 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.3.3 Operation of Timer B (event counter mode) In event counter mode, choose functions from those listed in Table 2.3.2. Operations of the circled items are described below. Figure 2.3.6 shows the operation timing, and Figure 2.3.7 shows the set-up procedure. Table 2.3.2. Choosed functions Item Count source O Set-up Input signal to the TBiIN pin (counting falling edges) Input signal to the TBiIN pin (counting rising edges) Input signal to the TBiIN pin (counting rising edges and falling edges) Timer overflow(TBj overflow) Note: j = i – 1, but j = 2 when i = 0, j = 5 when i = 3 Operation (1) Setting the count start flag to “1” causes the counter to count the falling edges of the count source. (2) If an underflow occurs, the content of the reload register is reloaded, and the count continues. At this time, the timer Bi interrupt request bit goes to “1”. (3) Setting the count start flag to “0” causes the counter to hold its value and to stop. n = reload register content FFFF16 (1) Start count (2) Underflow (3) Stop count Counter content (hex) n Start count again 000016 Time Set to “1” by software “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timer Bi interrupt “1” request bit “0” Cleared to “0” by software Set to “1” by softwar Count start flag Figure 2.3.6. Operation timing of event counter mode 2-44 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting event counter mode and functions b7 b0 0 0 0 0 1 Timer Bi mode register (i=0 to 5) [Address 039B16 to 039D16, 035B16 to 035D16] TBiMR (i=0 to 5) Selection of event counter mode Count polarity select bit b3 b2 0 0 : Counts external signal falling edges Fixed to “0” in event counter mode ( i = 0, 3) In an attempt to write to this bit, write “0” (i = 1, 2, 4, 5) Invalid in event counter mode Event clock select 0 : Input from TBiIN pin (Note) Note: Set the corresponding port direction register to “0”. Setting counter value (b15) b7 (b8) b0 b7 b0 Timer B0 register Timer B1 register Timer B2 register Timer B3 register Timer B4 register Timer B5 register [Address 039116, 039016] [Address 039316, 039216] [Address 039516, 039416] [Address 035116, 035016] [Address 035316, 035216] [Address 035516, 035416] TB0 TB1 TB2 TB3 TB4 TB5 Can be set to 000016 to FFFF16 (n) Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag b7 b0 Timer B3,4,5 count start flag [Address 034016] TBSR Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag Start count Figure 2.3.7. Set-up procedure of event counter mode 2-45 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.3.4 Operation of Timer B (pulse period measurement mode) In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.3. Operations of the circled items are described below. Figure 2.3.8 shows the operation timing, and Figure 2.3.9 shows the set-up procedure. Table 2.3.3. Choosed functions Item Count source Measurement mode O Internal count source (f1 / f8 / f32 / fc32) O Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) Set-up Operation (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If a measurement pulse changes from “H” to “L”, the value of the counter goes to “000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Bi interrupt request does not generate. (3) If a measurement pulse changes from “H” to “L” again, the value of the counter is transferred to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the value of the counter becomes “000016”, and the measurement is started again. Note • The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine. • The value of the counter at the beginning of a count is indeterminate. Therefore, the timer Bi overflow flag may go to “1” and timer Bi interrupt request may be generated during the interval between a count start and an effective edge input. • The timer Bi overflow flag is indeterminate after reset. The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software. Measurement of pulse time interval from falling edge to falling edge (1) Start count Count source Measurement pulse (2) Start measurement (3) Start measurement again “H” “L” Transfer (indeterminate value) Reload register ← counter transfer timing Transfer (measured value) (Note 1) Timing at which counter reaches “000016” Count start flag Timer Bi interrupt request bit (Note 1) (Note 2) “1” “0” “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timer Bi overflow flag “1” “0” Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 2.3.8. Operation timing of pulse period measurement mode 2-46 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting pulse period / pulse width measurement mode and functions b7 b0 0 0 1 0 Timer Bi mode register (i=0 to 5) [Address 039B16 to 039D16, 035B16 to 035D16] TBiMR (i=0 to 5) Selection of pulse period / pulse width measurement mode Measurement mode select bit b3 b2 0 0 : Pulse period measurement (Interval between measurement pulse falling edge to falling edge) Fixed to “0” in pulse period/pulse width measurement mode (i = 0, 3) In an attempt to write to this bit, write “0” (i = 1, 2, 4, 5) Timer Bi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) b7 b0 Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag b7 b0 Timer B3,4,5 count start flag [Address 034016] TBSR Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag Start count Clearing overflow flag b7 b0 0 Timer Bi mode register (i=0 to 5) [Address 039B16 to 039D16, 035B16 to 035D16] TBiMR (i=0 to 5) Timer Bi overflow flag 0 : Timer did not overflow Figure 2.3.9. Set-up procedure of pulse period measurement mode 2-47 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.3.5 Operation of Timer B (pulse width measurement mode) In pulse period/pulse width measurement mode, choose functions from those listed in Table 2.3.4. Operations of the circled items are described below. Figure 2.3.10 shows the operation timing, and Figure 2.3.11 shows the set-up procedure. Table 2.3.4. Choosed functions Item Count source Measurement mode O Internal count source (f1 / f8 / f32 / fc32) Pulse period measurement (interval between measurement pulse falling edge to falling edge) Pulse period measurement (interval between measurement pulse rising edge to rising edge) O Pulse width measurement (interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) Set-up Operation (1) Setting the count start flag to “1” causes the counter to start counting the count source. (2) If an effective edge of a pulse to be measured is input, the value of the counter goes to “000016”, and measurement is started. In this instance, an indeterminate value is transferred to the reload register. The timer Bi interrupt request does not generate. (3) If an effective edge of a pulse to be measured is input again, the value of the counter is transferred to the reload register, and the timer Bi interrupt request bit goes to “1”. Then the value of the counter becomes “000016”, and measurement is started again. Note • The timer Bi interrupt request bit goes to “1” when an effective edge of a pulse to be measured is input or timer Bi is overflows. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine. • The value of the counter at the beginning of a count is indeterminate. Therefore, the timer Bi overflow flag may go to “1” and timer Bi interrupt request may be generated during the interval between a count start and an effective edge input. • The timer Bi overflow flag is indeterminate after reset. The timer Bi overflow flag goes to “0” if timer Bi mode register is written to when the count start flag is “1”. This flag cannot be set to “1” by software. (1) Start count (3) Start measurement again (2) Start measurement Count source Measurement pulse Reload register ← counter transfer timing Timing at which counter reaches “000016” Count start flag Timer Bi interrupt request bit “1 ” “0 ” “1 ” “0 ” Timer Bi overflow flag “1 ” “0” Cleared to “0” when interrupt request is accepted, or cleared by software “H” “L” Transfer (indeterminate value) Transfer(measured value) (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed. Figure 2.3.10. Operation timing of pulse width measurement mode 2-48 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting pulse period / pulse width measurement mode and functions b7 b0 1 0 1 0 Timer Bi mode register (i=0 to 5) [Address 039B16 to 039D16, 035B16 to 035D16] TBiMR (i=0 to 5) Selection of pulse period / pulse width measurement mode Measurement mode select bit b3 b2 1 0 : Pulse width measurement (Interval between measurement pulse falling edge to rising edge, and between rising edge to falling edge) Fixed to “0” in pulse period/pulse width measurement mode (i = 0, 3) In an attempt to write to this bit, write “0” (i = 1, 2, 4, 5) Timer Bi overflow flag 0 : Timer did not overflow 1 : Timer has overflowed Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC32 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Setting clock prescaler reset flag (This function is effective when fC32 is selected as the count source. Reset the prescaler for generating fC32 by dividing the XCIN by 32.) b7 b0 Clock prescaler reset flag [Address 038116] CPSRF Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is “0”) Setting count start flag b7 b0 Count start flag [Address 038016] TABSR Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag b7 b0 Timer B3,4,5 count start flag [Address 034016] TBSR Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag Start count Clearing overflow flag b7 b0 0 Timer Bi mode register (i=0 to 5) [Address 039B16 to 039D16, 035B16 to 035D16] TBiMR (i=0 to 5) Timer Bi overflow flag 0 : Timer did not overflow Figure 2.3.11. Set-up procedure of pulse width measurement mode 2-49 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.3.6 Precautions for Timer B (timer mode, event counter mode) (1) To clear reset, the count start flag is set to “0”. Set a value in the timer Bi register, then set the flag to “1”. (2) Reading the timer Bi register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing shown in Figure 2.3.12 gets “FFFF16”. Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value. Reload Counter value (Hex.) 2 1 0 n n–1 Read value (Hex.) 2 1 0 FFFF n–1 Time n = reload register content Figure 2.3.12. Reading timer Bi register 2-50 Mitsubishi microcomputers Timer B M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode) (1) The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the timer Bi overflow flag within the interrupt routine. (2) If the timer overflow occurs simultaneously with the input of a measurement pulse, and if the interrupt factor cannot be determined from the timer Bi overflow flag, connect the timers and count the number of overflows. (3) When reset, the timer Bi overflow flag goes to “1”. This flag can be set to “0” by writing to the timer Bi mode register when the count start flag is “1”. (4) Use the timer Bi interrupt request bit to detect only overflows. Use the timer Bi overflow flag only to determine the interrupt factor within the interrupt routine. (5) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. (6) The value of the counter is indeterminate at the beginning of a count. Therefore, the timer Bi overflow flag may go to “1” and timer Bi interrupt request may be generated during the interval between a count start and an effective edge input. (7) If changing the measurement mode select bits are set after a count is started, the timer Bi interrupt request bit goes to “1”. Note that the timer Bi interrupt request bit does not change if the same value as before is written to the measurement mode select bits. (8) If the input signal to the TBiIN pin is affected by noise, precise measurement may not be performed in some cases. It is recommended to see that measurements fall within a specific range by use of software. (9) For pulse width measurement, pulse widths are successively measured. Use software to check whether the measurement result is an “H” level width or an “L” level width. 2-51 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.4 Clock-Synchronous Serial I/O Usage 2.4.1 Overview of the clock-synchronous serial I/O usage Clock-synchronous serial I/O carries out 8-bit data communications in synchronization with the clock. The following is an overview of the clock-synchronous serial I/O usage. (1) Transmission/reception format 8-bit data (2) Transfer rate If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit rate generator division, becomes the transfer rate. The bit rate generator count source can be selected from the following: f1, f8, and f32. Clocks f1, f8, and f32 are derived by dividing the CPU’s main clock by 1, 8, and 32 respectively. Furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the CLK pin becomes the transfer rate. (3) Error detection Only overrun error can be detected. Overrun error is an error that occurs when the next data is made ready before the reception buffer register is read. (4) How to deal with an error When receiving data, read an error flag and reception data simultaneously to determine which error has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer register, then receive the data again. To initialize the UARTi receive buffer register 1. Set the receive enable bit to “0” (disable reception). 2. Set the serial I/O mode select bit to “0002” (invalid serial I/O). 3. Set the serial I/O mode select bit. 4. Set the receive enable bit to “1” again (enable reception). To transmit data again due to an error on the reception side, set the UARTi transmit buffer register again, then transmit the data again. To set the UARTi transmit buffer register again 1. Set the serial I/O mode select bits to “0002” (invalidate serial I/O). 2. Set the serial I/O mode select bits again. 3. Set the transmit enable bit to “1” (enable transmission), then set transmission data in the UARTi transmit buffer register. (5) Function selection For clock-synchronous serial I/O, the following functions can be selected: _______ _______ (a) CTS/RTS function _______ In the CTS function, an external IC can start transmission/reception by inputting an “H” level to the _______ _______ CTS pin. The CTS pin input level is detected when transmission/reception starts. Therefore, if the level is set to “L” during transmission/reception, it will stop from the next data. _______ _______ _______ The RTS function informs an external IC that RTS is reception-ready and has changed to “L”. RTS goes to “H” at the falling edge of the transfer clock. 2-52 Mitsubishi microcomputers Clock-Synchronous Serial I/O _______ _______ M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The clock-synchronous serial I/O has three types of CTS/RTS functions to choose from: _______ _______ _______ _______ • CTS/RTS functions disabled CTS/RTS pin is a programmable I/O port. _______ _______ _______ _______ • CTS function only enabled CTS/RTS pin performs the CTS function. _______ _______ _______ _______ • RTS function only enabled CTS/RTS pin performs the RTS function. (b) Function for choosing polarity This function switches the polarity of the transfer clock. The following operations are available: • Data is input at the falling edge of the transfer clock, and is output at the rising edge. • Data is input at the rising edge of the transfer clock, and is output at the falling edge. (c) Function for choosing which bit to transmit first This function is to choose whether to transmit data from bit 0 or from bit 7. Choose either of the following: • LSB first Data is transmitted from bit 0. • MSB first Data is transmitted from bit 7. (d) Function for choosing successive reception mode Successive reception mode is a mode in which reading the receive buffer register makes the reception-enabled status ready. In this mode, there is no need to write dummy data to the transmit buffer register so as to make the reception-enabled status ready. But at the time of starting reception, read the receive buffer register into a dummy manner. • Normal mode Writing dummy data to the transmit buffer register makes the reception enabled status ready. Reading the reception buffer register makes the reception-enabled • Successive reception mode status ready. (e) Function for outputting transfer clock to multiple pins This function is to switch among pins to output the transfer clock. This function is effective only when selecting the internal clock. Switching among pins for outputting the transfer clock allows data transmission to two external ICs in a time-sharing manner. (f) Data logic select function This function is to reserve data when writing to transmit buffer register or reading from receive buffer register. (g) Function for choosing a transmission interrupt factor The timing to generate a transmission interrupt can be selected from the following: the instant the transmission buffer is emptied or the instant the transmission register is emptied. When transmission buffer empty timing is selected, an interrupt occurs when transmitted data is moved from the transmission buffer to the transmission register. Therefore, data can be transmitted in succession. When transmission register empty timing is selected, an interrupt occurs when data transmission is complete. (h) TxD, RxD I/O polarity reverse function This function is to reserve a polarity of TxD port output level and a polarity of RxD port input level. 2-53 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Following are some examples in which various functions (a) through (g) are selected: _______ • Transmission Operation WITH: CTS function, transmission at falling edge of transfer clock, LSB First, interrupt at instant transmission buffer is emptied; WITHOUT transfer clock output to multiple pins function ........................................................................................................................... P2-60 _______ _______ • Transmission Operation WITH: CTS/RTS function disabled, transmission at falling edge of transfer clock, LSB First, interrupt at instant transmission is completed; WITH transfer clock output to multiple pins function (UART0 selection available) ...................................................................... P2-64 _______ • Reception WITH: RTS function, reception at falling edge of transfer clock, LSB First, successive reception mode disabled; WITHOUT transfer clock output to multiple pins function ............. P2-68 (6) Input to the serial I/O and the direction register To input an external signal to the serial I/O, set the direction register of the relevant port to input. (7) Pins related to the serial I/O _______ ________ ________ _______ • CTS0, CTS1, CTS2 pins Input pins for the CTS function ________ ________ ________ _______ • RTS0, RTS1, RTS2 pins Output pins for the RTS function Input/output pins for the transfer clock • CLK0, CLK1, CLK2 pins • RxD0, RxD1, RxD2 pins Input pins for data • TxD0, TxD1, TxD2 pins Output pins for data (Since TXD2 pin is N-channel open drain, this pin needs pull-up resistor.) • CLKS1 pin Output pin for transfer clock. Can be used as transfer clock output pin in the transfer clock output to multiple pins function. (8) Registers related to the serial I/O Figure 2.4.1 shows the memory map of serial I/O-related registers, and Figures 2.4.2 to 2.4.6 show serial I/O-related registers. 004F16 005016 005116 005216 005316 005416 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 UART2 UART2 UART0 UART0 UART1 UART1 transmit interrupt control register (S2TIC) receive interrupt control register (S2RIC) transmit interrupt control register (S0TIC) receive interrupt control register (S0RIC) transmit interrupt control regster(S1TIC) receive interrupt control register(S1RIC) UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) UART0 transmit/receive mode register (U0MR) UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON) Figure 2.4.1. Memory map of serial I/O-related registers 2-54 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit buffer register (Note) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16 When reset Indeterminate Indeterminate Indeterminate Function Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Use MOV instruction to write to this register. RW UARTi receive buffer register (b15) b7 (b8) b0 b7 b0 Symbol U0RB U1RB U2RB Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16 When reset Indeterminate Indeterminate Indeterminate Function (During UART mode) Receive data Bit symbol Bit name Function (During clock synchronous serial I/O mode) Receive data RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. ABT Arbitration lost detecting flag (Note 2) 0 : Not detected 1 : Detected Invalid OER FER PER SUM Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Framing error flag (Note 1) Invalid Parity error flag (Note 1) Error sum flag (Note 1) Invalid Invalid Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016, 03A816 and 037816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but “0” may be written. Nothing is assigned in bit 11 of U0RB and U1RB. When write, set “0”. The value, if read, turns out to be “0”. UARTi bit rate generator (Note 1, 2) b7 b0 Symbol U0BRG U1BRG U2BRG Address 03A116 03A916 037916 Function When reset Indeterminate Indeterminate Indeterminate Values that can be set 0016 to FF16 RW Assuming that set value = n, BRGi divides the count source by n+1 Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register. Figure 2.4.2. Serial I/O-related registers (1) 2-55 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 03A016, 03A816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 Function (During UART mode) b2 b1 b0 RW 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock 1 : External clock (Note) Invalid Odd/even parity select bit Invalid PRYE SLEP Parity enable bit Sleep select bit Invalid Must always be “0” Note : Set the corresponding port direction register to “0”. UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2MR Address 037816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Function (During UART mode) b2 b1 b0 RW Must be fixed to 001 b2 b1 b0 0 0 0 : Serial I/O invalid 0 1 0 : (Note 1) 0 1 1 : Must not be set. 1 1 1 : Must not be set. 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. Must always be “0” CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock 1 : External clock (Note 2) Invalid 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity Odd/even parity select bit Invalid PRYE IOPOL Parity enable bit TxD, RxD I/O polarity reverse bit Invalid 0 : No reverse 1 : Reverse Usually set to “0” 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to “0” Note 1: Bit 2 to bit 0 are set to “0102” when I2C mode is used. Note 2: Set the corresponding port direction register to “0”. Figure 2.4.3. Serial I/O-related registers (2) 2-56 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC0(i=0,1) Address When reset 03A416, 03AC16 0816 Bit symbol CLK0 CLK1 CRS Bit name BRG count source select bit Function (During clock synchronous serial I/O mode) b1 b0 b1 b0 Function (During UART mode) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) RW 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) CTS/RTS function select bit TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge NCH Data output select bit CKPOL CLK polarity select bit Must always be “0” UFORM Transfer format select bit 0 : LSB first 1 : MSB first Must always be “0” Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. UART2 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C0 Address 037C16 When reset 0816 Bit symbol CLK0 CLK1 CRS Bit name BRG count source select bit Function (During clock synchronous serial I/O mode) b1 b0 b1 b0 Function (During UART mode) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) RW 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) CTS/RTS function select bit TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0: TXDi pin is CMOS output open-drain output CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : TXDi pin is CMOS output open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Nothing is assigned. CKPOL 1: to be “ is In an attempt to write to this bit, write1“:0TXDi pin is N-channel turns out TXDi pin0”. N-channel ”. The value, if read, CLK polarity select bit Must always be “0” UFORM Transfer format select bit 0 : LSB first 1 : MSB first (Note 3) 0 : LSB first 1 : MSB first Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. Figure 2.4.4. Serial I/O-related registers (3) 2-57 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC1(i=0,1) Address 03A516,03AD16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register RW RE RI Receive enable bit Receive complete flag Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. UART2 transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C1 Address 037D16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse Must be fixed to “0” Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) Must always be "0" RW RE RI Receive enable bit Receive complete flag U2IRS UART2 transmit interrupt cause select bit U2RRM UART2 continuous receive mode enable bit U2LCH Data logic select bit U2ERE Error signal output enable bit 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled Figure 2.4.5. Serial I/O-related registers (4) 2-58 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol UCON Address 03B016 When reset X00000002 Bit symbol U0IRS Bit name UART0 transmit interrupt cause select bit Function (During clock synchronous serial I/O mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Function (During UART mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) RW U1IRS UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U0RRM UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode (CLK output is CLK1 only) Must always be “0” U1RRM UART1 continuous receive mode enable bit Must always be “0” CLKMD0 CLK/CLKS select bit 0 Invalid CLKMD1 CLK/CLKS select bit 1 (Note) Must always be “0” 1 : Transfer clock output from multiple pins function selected Reserved bit Must always be set to “0” Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: • UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”. UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR Address 037716 When reset 0016 Bit symbol Bit name Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : I2C mode 0 : Update per bit 1 : Update per byte 0 : STOP condition detected 1 : START condition detected Function (During UART mode) RW IICM ABC BBS LSYN ABSCS I2C mode select bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit Must always be “0” Must always be “0” Must always be “0” (Note1) 0 : Disabled 1 : Enabled Must always be “0” 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 Must always be “0” ACSE Must always be “0” 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RXD2 SSS Must always be “0” SDDS SDA digital delay select bit (Note 2, Note 3) 0 : Analog delay output is selected 1 : Digital delay output is selected (must always be “0” when not using I 2 C mode) Must always be “0” Note 1: Nothing but “0” may be written. Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to “000”, with the analog delay circuit selected. Also, when SDDS = “0”, the U2SMR3 register cannot be read or written to. Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. Figure 2.4.6. Serial I/O-related registers (5) 2-59 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.4.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode) In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.4.1. Operations of the circled items are described below. Figure 2.4.7 shows the operation timing, and Figures 2.4.8 and 2.4.9 show the set-up procedures. Table 2.4.1. Choosed functions Item Transfer clock source CTS function O Set-up Internal clock (f1 / f8 / f32) External clock (CLKi pin) O CTS function enabled CTS function disabled CLK polarity O Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock Transfer clock O LSB first MSB first Item Transmission interrupt factor Output transfer clock to multiple pins (Note 1) Data logic select function (Note 2) TXD, RXD I/O polarity reverse bit (Note 2) O Set-up Transmission buffer empty Transmission complete O Not selected Selected O No reverse Reverse O No reverse Reverse Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is _______ _______ _______ _______ selected, UART1 CTS/RTS function can not be utilized. Set the UART1 CTS/RTS disable bit to “1”. Note 2: UART2 only. Operation (1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit buffer register makes data transmissible status ready. ________ _______ (2) When input to the CTSi pin goes to “L” level, transmission starts (the CTSi pin must be controlled on the reception side). (3) In synchronization with the first falling edge of the transfer clock, transmission data held in the UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the UARTi transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is transmitted from the TxDi pin. Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges. (4) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”, which indicates that transmission is completed. The transfer clock stops at “H” level. (5) If the next transmission data is set in the UARTi transmit buffer register while transmission is in progress (before the eighth bit has been transmitted), the data is transmitted in succession. 2-60 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example of wiring (Note) Microcomputer CLKi TXDi CTSi Receiver side IC CLK RXD Port Note : Since TXD2 pin is N-channel open drain, this pin needs pull-up resistor. Example of operation (1) Transmission enabled (2) Confirming CTS (3) Start transmission Tc Transfer clock (4) Transmission is complete (5) Transmit next data Transmit enable bit (TE) Transmit buffer empty flag (Tl) CTSi “1” “0” “1” “0” Transferred from UARTi transmit buffer register to UARTi transmit register “H” “L” TCLK Stopped pulsing because CTSi = “H” Stopped pulsing because transfer enable bit = “0” Data is set to UARTi transmit buffer register CLKi TxDi Transmit register “1” empty flag “0” (TXEPT) “1” Transmit interrupt request “0” bit (IR) D0 D 1 D2 D3 D4 D5 D6 D7 D0 D 1 D2 D3 D4 D5 D 6 D7 D 0 D1 D2 D 3 D 4 D 5 D6 D7 Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • Internal clock is selected. • CTS function is selected. • CLK polarity select bit = “0”. • Transmit interrupt cause select bit = “0”. Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi Figure 2.4.7. Operation timing of transmission in clock-synchronous serial I/O mode 2-61 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting UARTi transmit/receive mode register (i=0 to 2) b7 b0 UART0 transmit/receive mode register U0MR [Address 03A016] b7 b0 0 0 0 0 1 0 0 0 0 1 UART2 transmit/receive mode register U2MR [Address 037816] UART1 transmit/receive mode register U1MR [Address 03A816] Must be fixed to “001” Internal/external clock select bit 0 : Internal clock Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must always be “0” in clock synchronous I/O mode Must be fixed to “001” Internal/external clock select bit 0 : Internal clock Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode TXD, RXD I/O polarity reverse bit Usually set to “0” Setting UARTi transmit/receive control register 0 (i=0 to 2) b7 b0 00 0 0 UART0 transmit/receive control register 0 U0C0 [Address 03A416] UART1 transmit/receive control register 0 U1C0 [Address 03AC16] BRG count source select bit b1 b0 b7 b0 0 0 0 0 UART2 transmit/receive control register 0 U2C0 [Address 037C16] BRG count source select bit b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set CTS/RTS function select bit (Valid when bit 4 = “0”) 0 : CTS function is selected (Note) Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CTS/RTS disable bit 0 : CTS/RTS function enabled Data output select bit 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 : LSB first Note: Set the corresponding port direction register to “0” . 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set CTS/RTS function select bit (Valid when bit 4 = “0”) 0 : CTS function is selected (Note) Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CTS/RTS disable bit 0 : CTS/RTS function enabled CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 : LSB first Setting UART transmit/receive control register 2 and UART2 transmit/receive control register 1 b7 b0 0 0 0 0 UART transmit/receive control register 2 UCON [Address 03B016] UART0 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) Valid when bit 5 = “1” CLK/CLKS select bit 1 0 : Normal mode (CLK output is CLK1 only) Reserved bit Must always be set to “0” b7 b0 0 0 UART2 transmit/receive control register 1 U2C1 [Address 037D16] UART2 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) Data logic select bit 0 : No reverse Error signal output enable bit Must always be “0” in clock synchronous I/O mode Continued to the next page Figure 2.4.8. Set-up procedure of transmission in clock-synchronous serial I/O mode (1) 2-62 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Setting UARTi bit rate generator (i = 0 to 2) b7 b0 UARTi bit rate generator (i = 0 to 2) [Address 03A116, 03A916, 037916] UiBRG (i = 0 to 2) Can be set to 0016 to FF16 (Note) Note: Write to UARTi bit rate generator when transmission/reception is halted. Transmission enabled b7 b0 UART0 transmit/receive control register 1 U0C1 [Address 03A516] 1 UART1 transmit/receive control register 1 U1C1 [Address 03AD16] Transmit enable bit 1 : Transmission enabled b7 b0 UART2 transmit/receive control register 1 1 U2C1 [Address 037D16] Transmit enable bit 1 : Transmission enabled Writing transmit data (b15) b7 (b8) b0 b7 b0 UART0 receive buffer register [Address 03A316, 03A216] U0TB UART1 receive buffer register [Address 03AB16, 03AA16] U1TB UART2 receive buffer register [Address 037B16, 037A16] U2TB Setting transmission data When CTSi input level = “L” Start transmission Checking the status of UARTi transmit /receive control register (i = 0 to 2) b7 b0 UART0 transmit/receive control register 1 U0C1 [Address 03A516] UART1 transmit/receive control register 1 U1C1 [Address 03AD16] Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled) b7 b0 UART2 transmit/receive control register 1 U2C1 [Address 037D16] Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled) Writing next transmit data (b15) b7 (b8) b0 b7 b0 UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB UART2 transmit buffer register [Address 037B16, 037A16] U2TB Setting transmission data Transmission is complete Figure 2.4.9. Set-up procedure of transmission in clock-synchronous serial I/O mode (2) 2-63 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.4.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected) In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.4.2. Operations of the circled items are described below. Figure 2.4.10 shows the operation timing, and Figures 2.4.11 and 2.4.12 show the set-up procedures. Table 2.4.2. Choosed functions Item Transfer clock source CTS function O CLK polarity O O Set-up Internal clock (f1 / f8 / f32) External clock (CLKi pin) CTS function enabled CTS function disabled Output transmission data at the falling edge of the transfer clock Output transmission data at the rising edge of the transfer clock Transfer clock O LSB first MSB first Item Transmission interrupt factor Output transfer clock to multiple pins (Note 1) Data logic select function (Note 2) TXD, RXD I/O polarity reverse bit (Note 2) Set-up Transmission buffer empty O Transmission complete Not selected O O Selected No reverse Reverse O No reverse Reverse Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is _______ _______ _______ _______ selected, UART1 CTS/RTS function can not be utilized. Set the UART1 CTS/RTS disable bit to “1”. Note 2: UART2 only. Operation (1) Setting the transmit enable bit to “1” makes data transmissible status ready. (2) When transmission data is written to the UART1 transmit buffer register, transmission data held in the UART1 transmit buffer register is transmitted to the UART1 transmit register in synchronization with the first falling edge of the transfer clock. At this time, the first bit of the transmission data is transmitted from the TxD1 pin. Then the data is transmitted bit by bit from the lower order in synchronization with the falling edges of the transfer clock. (3) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”, which indicates that the transmission is completed. The transfer clock stops at “H” level. At this time, the UART1 transmit interrupt request bit goes to “1”. (4) Setting CLK/CLKS select bit 1 to “1” and setting CLK/CLKS select bit 0 to “1” causes the CLKS1 pin to go to the transfer clock output pin. Change the transfer clock output pin when transmission is halted. 2-64 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example of wiring Microcomputer TXD1 (P67) CLKS1 (P64) CLK1 (P65) IN CLK IN CLK Note: This applies when performing only transmission with an internal clock selected in the clock synchronous serial I/O mode. Example of operation (1) Transmission enabled (2) Start transmission Transfer clock (TE) (3) Transmission is complete (4) Clock switched Transmit enable bit (TI) “1” “0” “1” “0” “1” “0” “1” “0” Transmit buffer empty flag (CLKMD1) CLK, CLKS select bit 1 (CLKMD0) CLK, CLKS select bit 0 CLK1 CLKS1 TxD1 D 0 D1 D 2 D 3 D 4 D5 D6 D 7 D 0 D1 D 2 D 3 D 4 D5 D6 D 7 “1” UART1 Transmit interrupt request bit “0” (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Figure 2.4.10. Operation timing of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected 2-65 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting UART1 transmit/receive mode register b7 b0 0 0 0 0 1 UART1 transmit/receive mode register [Address 03A816] U1MR Must be fixed to “001” Internal/external clock select bit 0 : Internal clock Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must always be “0” in clock synchronous I/O mode Setting UART1 transmit/receive control register 0 b7 b0 0 0 1 UART1 transmit/receive control register 0 [Address 03AC16] U1C0 BRG count source select bit b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set Valid when bit 4 = “0” Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CTS/RTS disable bit 1 : CTS/RTS function disabled Data output select bit 0 : TXDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 : LSB first Setting UART transmit/receive control register 2 b7 b0 0 1 1 UART transmit/receive control register 2 [Address 03B016] UCON UART0 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) CLK/CLKS select bit 0 0 : Clock output to CLK1 1 : Clock output to CLKS1 CLK/CLKS select bit 1 1 : Transfer clock output from multiple pins function selected Reserved bit Must always be set to “0” Continued to the next page Figure 2.4.11. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected (1) 2-66 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Setting UART1 bit rate generator b7 b0 UART1 bit rate generator [Address 03A916] U1BRG Can be set to 0016 to FF16 (Note) Note: Write to UART1 bit rate generator when transmission/reception is halted. Transmission enabled b7 b0 1 UART1 transmit/receive control register 1 [Address 03AD16] U1C1 Transmit enable bit 1 : Transmission enabled Writing transmit data (b15) b7 (b8) b0 b7 b0 UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data Start transmission Checking the status of UART1 transmit/receieve control register b7 b0 UART1 transmit/receive control register 1 [Address 03AD16] U1C1 Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled) Writing next transmit data (b15) b7 (b8) b0 b7 b0 UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB Setting transmission data Transmission is complete Figure 2.4.12. Set-up procedure of transmission in clock-synchronous serial I/O mode, transfer clock output from multiple pins function selected (2) 2-67 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.4.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode) In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.4.3. Operations of the circled items are described below. Figure 2.4.13 shows the operation timing, and Figures 2.4.14 and 2.4.15 show the set-up procedures. Table 2.4.3. Choosed functions Item Transfer clock source RTS function Set-up Internal clock (f1 / f8 / f32) O O External clock (CLKi pin) RTS function enabled RTS function disabled CLK polarity O Input reception data at the rising edge of the transfer clock Input reception data at the falling edge of the transfer clock Transfer clock O LSB first MSB first Item Continuous receive mode Output transfer clock to multiple pins (Note 1) Data logic select function (Note 2) TXD, RXD I/O polarity reverse bit (Note 2) O Set-up Disabled Enabled O Not selected Selected O No reverse Reverse O No reverse Reverse Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is _______ _______ _______ _______ selected, UART1 CTS/RTS function can not be utilized. Set the UART1 CTS/RTS disable bit to “1”. Note 2: UART2 only. Operation (1) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”, and the transmit enable bit to “1”, makes the data receivable status ready. At this time, the ________ output from the RTSi pin goes to “L” level, which informs the transmission side that the data receivable status is ready (output the transfer clock from the IC on the transmission side after _______ checking that the RTS output has gone to “L” level). (2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting right the content of the UARTi reception data in synchronization with the rising edges of the transfer clock. (3) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive register is transmitted to the UARTi receive buffer register. The transfer clock stops at “H” level. At this time, the receive complete flag and the UARTi receive interrupt request bit goes to “1”. (4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register is read. 2-68 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example of wiring Microcomputer CLKi RXDi RTSi Transmitter side IC CLK TXD Port Example of operation (1) Reception enabled (2) Start reception (3) Reception is complete (4) Read of reception data Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) “1” “0” “1” “0” “1” “0” “H” Dummy data is set in UARTi transmit buffer register Transferred from UARTi transmit buffer register to UARTi transmit register RTSi “L” CLKi Reception data is taken in 1 / fEXT RxDi Receive complete “1” flag (Rl) “0” Receive interrupt request bit (IR) “1” “0” D0 D1 D2 D3 D4 D5 D6 Transferred from UARTi receive register to UARTi receive buffer register D7 D0 D1 D2 D3 D4 D5 Read out from UARTi receive buffer register Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: • External clock is selected. • RTS function is selected. • CLK polarity select bit = “0”. fEXT: frequency of external clock Make sure that the following conditions are met when the CLKi pin input =“H” before data reception • Transmit enable bit → “1” • Receive enable bit → “1” • Dummy data write to UARTi transmit buffer register Figure 2.4.13. Operation timing of reception in clock-synchronous serial I/O mode 2-69 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting UARTi transmit/receive mode register (i=0 to 2) b7 b0 0 1001 UART0 transmit/receive mode register U0MR [Address 03A016] UART1 transmit/receive mode register U1MR [Address 03A816] b7 b0 0 1001 UART2 transmit/receive mode register U2MR [Address 037816] Must be fixed to “001” Internal/external clock select bit 1 : External clock Must be fixed to “001” Internal/external clock select bit 1 : External clock Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode TXD, RXD I/O polarity reverse bit Usually set to “0” Invalid in clock synchronous I/O mode Invalid in clock synchronous I/O mode Sleep select bit Must always be “0” in clock synchronous I/O mode Setting UARTi transmit/receive control register 0 (i=0 to 2) b7 b0 00 0 1 UART0 transmit/receive control register 0 U0C0 [Address 03A416] UART1 transmit/receive control register 0 U1C0 [Address 03AC16] b7 b0 00 0 1 UART2 transmit/receive control register 0 U2C0 [Address 037C16] BRG count source select bit b1 b0 BRG count source select bit b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set CTS/RTS function select bit (Valid when bit 4 = “0”) 1 : RTS function is selected Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CTS/RTS disable bit 0 : CTS/RTS function enabled 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set CTS/RTS function select bit (Valid when bit 4 = “0”) 1 : RTS function is selected Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CTS/RTS disable bit 0 : CTS/RTS function enabled CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Data output select bit 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output CLK polarity select bit 0 : Transmission data is output at falling edge of transfer clock and reception data is input at rising edge Transfer format select bit 0 : LSB first Transfer format select bit 0 : LSB first Setting UART transmit/receive control register 2 and UART2 transmit/receive control register 1 b7 b0 00 00 UART transmit/receive control register 2 UCON [Address 03B016] UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled b7 b0 000 UART2 transmit/receive control register 1 U2C1 [Address 037D16] UART2 continuous receive mode enable bit 0 : Continuous receive mode disabled Data logic select bit 0 : No reverse Error signal output enable bit Must always be “0” in clock synchronous I/O mode UART1 continuous receive mode enable bit 0 : Continuous receive mode disabled Valid when bit 5 = “1” CLK/CLKS select bit 1 0 : Normal mode (CLK output is CLK1 only) Reserved bit Must always be set to “0” Continued to the next page Figure 2.4.14. Set-up procedure of reception in clock-synchronous serial I/O mode (1) 2-70 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Reception enabled b7 b0 1 1 UART0 transmit/receive control register 1 [Address 03A516] U0C1 UART1 transmit/receive control register 1 [Address 03AD16] U1C1 Transmit enable bit 1 : Transmission enabled b7 b0 1 1 UART2 transmit/receive control register 1 [Address 037D16] U2C1 Transmit enable bit 1 : Transmission enabled Receive enable bit 1 : Reception enabled Receive enable bit 1 : Reception enabled Writing dummy data (b15) b7 (b8) b0 b7 b0 UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB UART2 transmit buffer register [Address 037B16, 037A16] U2TB Setting dummy data Start reception Checking completion of reception b7 b0 UART0 transmit/receive control register 1 b7 [Address 03A516] U0C1 UART1 transmit/receive control register 1 [Address 03AD16] U1C1 Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register b0 UART2 transmit/receive control register 1 [Address 037D16] U2C1 Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register Checking error (b15) b7 (b8) b0 b7 b0 UART0 receive buffer register [Address 03A716, 03A616]U0RB UART1 receive buffer register [Address 03AF16, 03AE16]U1RB UART2 receive buffer register [Address 037F16, 037E16]U2RB Receive data Overrun error flag 0 : No overrun error 1 : Overrun error found Processing after reading out reception data Figure 2.4.15. Set-up procedure of reception in clock-synchronous serial I/O mode (2) 2-71 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.4.5 Precautions for Serial I/O (in clock-synchronous serial I/O) Transmission/reception _______ ________ (1) With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmis________ sion side that the reception has become ready. The output level of the RTSi pin goes to “H” ________ ________ when reception starts. So if the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can transmission and reception data with consistent timing. With the internal _______ clock, the RTS function has no effect. Figure 2.4.16 shows an example of wiring. Transmitter side IC Receiver side IC TxDi RxDi TxDi RxDi CLKi CTSi CLKi RTSi Figure 2.4.16. Example of wiring 2-72 Mitsubishi microcomputers Clock-Synchronous Serial I/O M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Transmission (1) With an external clock selected, perform the following set-up procedure with the CLKi pin input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the CLK polarity select bit = “1”: 1. Set the transmit enable bit (to “1”) 2. Write transmission data to the UARTi transmit buffer register ________ _______ 3. “L” level input to the CTSi pin (when the CTS function is selected) Reception (1) In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings for transmission even when using the device only for reception. Dummy data is output to the outside from the TxDi pin (transmission pin) when receiving data. (2) With the internal clock selected, setting the transmit enable bit to “1” (transmission-enabled status) and setting dummy data in the UARTi transmission buffer register generates a shift clock. With the external clock selected, a shift clock is generated when the transmit enable bit is set to “1”, dummy data is set in the UARTi transmit buffer register, and the external clock is input to the CLKi pin. (3) In receiving data in succession, an overrun error occurs when the next reception data is made ready in the UARTi receive register with the receive complete flag set to “1” (before the content of the UARTi receive buffer register is read), and overrun error flag is set to “1”. In this instance, the next data is written to the UARTi receive buffer register, so handle with this problem by writing programs on transmission side and reception side so that the previous data is transmitted again. If an overrun error occurs, the UARTi receive interrupt request bit does not change. (4) To receive data in succession, set dummy data in the lower-order byte of the UARTi transmit buffer register every time reception is made. (5) With an external clock selected, perform the following set-up procedure with the CLKi pin input level = “H” if the CLK polarity select bit = “0” or with the CLKi pin input level = “L” if the CLK polarity select bit = “1”: 1. Set receive enable bit (to “1”) 2. Set transmit enable bit (to “1”) 3. Write dummy data to the UARTi transmit buffer register _______ (6) Output from the RTS pin goes to “L” level as soon as the receive enable bit is set to “1”. This is not related to the content of the transmit buffer empty flag or the content of the transmit enable bit. _______ Output from the RTS pin goes to “H” level when reception starts, and goes to “L” level when reception is completed. This is not related to the content of the transmit buffer empty flag or the content of the receive complete flag. 2-73 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.5 Clock-Asynchronous Serial I/O (UART) Usage 2.5.1 Overview of the clock-asynchronous serial I/O usage UART handles communications by means of character-by-character synchronization. The transmission side and the reception side are independent of each other, so full-duplex communication is possible. The following is an overview of the clock-asynchronous serial I/O usage. (1) Transmission/reception format Figure 2.5.1 shows the transmission/reception format, and Table 2.5.1 shows the names and functions of transmission data. Transfer data length : 7 bits 1ST – 7DATA 1ST – 7DATA 1ST – 7DATA – 1PAR – 1ST – 7DATA – 1PAR – 1ST – 8DATA 1ST – 8DATA 1ST – 8DATA – 1PAR – 1ST – 8DATA – 1PAR – 1ST – 9DATA 1ST – 9DATA 1ST – 9DATA – 1PAR – 1ST – 9DATA – 1PAR – ST DATA PAR SP 1SP 2SP 1SP 2SP 1SP 2SP 1SP 2SP 1SP 2SP 1SP 2SP Transfer data length : 8 bits Transfer data length : 9 bits : Start bit : Character bit (Transfer data) : Parity bit : Stop bit Figure 2.5.1. Transmission/reception format Table 2.5.1. Transmission data names and functions Name ST (start bit) DATA (character bits) PAR (parity bit) Function A 1-bit “L” signal to be added immediately before character bits. This bit signals the start of data transmission. Transmission data set in the UARTi transmit buffer register. A signal to be added immediately after character bits so as to increase data reliability. The level of this signal so varies that the total number of 1's in character bits and this bit always becomes even or odd depending on which parity is chosen, even or odd. Either 1-bit or 2-bit “H” signal to be added immediately after character bits (after the parity bit if parity is checked). This / they signals the end of data transmission. SP (stop bit) 2-74 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) Transfer rate The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the transfer rate. The count source for the transfer rate register can be selected from f1, f8, f32, and the input from the CLK pin. Clocks f1, f8, f32 are derived by dividing the CPU’s main clock by 1, 8, and 32 respectively. Table 2.5.2. Example of baud rate setting Baud rate (bps) 600 1200 2400 4800 9600 14400 19200 28800 31250 BRG's count source f8 f8 f8 f1 f1 f1 f1 f1 f1 System clock : 16MHz BRG's set value : n 207 (CF16) 103 (6716) 51 (3316) 207 (CF16) 103 (6716) 68 (4416) 51 (3316) 34 (2216) 33 (2116) Actual time (bps) 601 1202 2404 4808 9615 14493 19231 28571 31250 System clock : 7.3728MHz BRG's set value : n 95 (5F16) 47 (2F16) 23 (1716) 95 (5F16) 47 (2F16) 31 (1F16) 23 (1716) 15 (F16) Actual time (bps) 600 1200 2400 4800 9600 14400 19200 28800 (3) An error detection In clock-asynchronous serial I/O mode, detect errors are shown in Table 2.5.3. Table 2.5.3. Error detection Type of error Overrun error Description • This error occurs when the next data lines up before the content of the UARTi receive buffer register is read. • The next data is written to the UARTi receive buffer register. • The UARTi receive interrupt request bit does not change. • This error occurs when the stop bit falls short of the set number of stop bits. • With parity enabled, this error occurs when the total number of 1's in character bits and the parity bit is different from the specified number. • This flag turns on when any error (overrun, framing, or parity) is detected. When the flag turns on How to clear the flag • Set the serial I/O mode select bits to “0002”. • Set the receive enable bit to “0”. Framing error Parity error The error is detected • Set the serial I/O mode select when data is bits to ”0002”. transferred from the UARTi receive register • Set the receive enable bit to “0”. to the UARTi receive • Read the lower-order byte of buffer register. the UARTi receive buffer register. Error-sum flag • When all error (overrun, framing, and parity) are removed, the flag is cleared. 2-75 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (4) How to deal with an error When receiving data, read an error flag and reception data simultaneously to determine which error has occurred. If the data read is erroneous, initialize the error flag and the UARTi receive buffer register, then receive the data again. To initialize the UARTi receive buffer register 1. Set the receive enable bit to “0” (disable reception). 2. Set the receive enable bit to “1” again (enable reception). To transmit data again due to an error on the reception side, set the UARTi transmit buffer register again, then transmit the data again. To set the UARTi transmit buffer register again 1. Set the serial I/O mode select bits to “0002” (invalidate serial I/O). 2. Set the serial I/O mode select bits again. 3. Set the transmit enable bit to “1” (enable transmission), then set transmission data in the UARTi transmit buffer register. (5) Functions selection In operating UART, the following functions can be used: _______ _______ (a) CTS/RTS function _______ CTS function is a function in which an external IC can start transmission/reception by means of _______ _______ inputting an “L” level to the CTS pin. The CTS pin input level is detected when transmission/reception starts, so if the level is gone to“ H” while transmission/reception is in progress, transmission/reception stops at the next data. _______ _______ RTS function is a function to inform an external IC that RTS pin output level has changed to “L” when _______ reception is ready. RTS regoes to “H” at the falling edge of the transfer clock. _______ _______ When using clock-asynchronous serial I/O, choose one of three types of CTS/RTS functions. _______ _______ _______ _______ • CTS/RTS functions disabled CTS/RTS pin is a programmable I/O port. _______ _______ _______ _______ • CTS function only enabled CTS/RTS pin performs the CTS function. _______ _______ _______ _______ • RTS function only enabled CTS/RTS pin performs the RTS function. (b) Sleep mode Sleep mode is a mode in which data is transferred to a particular microcomputer among those connected by use of clock-asynchronous serial I/O devices. (c) Data logic select function This function is to reserve data when writing to transmit buffer register or reading from receive buffer register. (d) TxD, RxD I/O polarity reverse function This function receive a polarity of TxD port output level and a polarity of RxD port input level. (e) Bus collision detection function This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. 2-76 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following are examples in which functions (a) to (e) are chosen: _______ • Transmission WITH: CTS function, WITHOUT: other functions .............................................. P2-84 _______ • Reception WITH: RTS function, WITHOUT: other functions ................................................... P2-88 Also, the SIM interface is used by adding some extra settings in UART2's clock-asynchronous serial I/O mode. Direct or inverse format is selected by connecting SIM card. • Transmission WITH: direct format ........................................................................................... P2-92 • Reception WITH: direct format ................................................................................................ P2-96 (6) Input to the serial I/O and the direction register To input an external signal to the serial I/O, set the direction register of the relevant port to input. (7) Pins related to the serial I/O _________ _________ __________ _______ • CTS0, CTS1, CTS2 pins :Input pins for the CTS function _________ _________ _________ _______ • RTS0, RTS1, RTS2 pins :Output pins for the RTS function • CLK0, CLK1 pins :Input pins for the transfer clock :Input pins for data • RxD0, RxD1, RxD2 pins • TxD0, TxD1, TxD2 pins :Output pins for data Since TxD2 pin is N-channel open drain, this pin needs pull-up resistor. 2-77 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (8) Registers related to the serial I/O Figure 2.5.2 shows the memory map of serial I/O-related registers, and Figures 2.5.3 to 2.5.7 show UARTi-related registers. 004A16 004F16 005016 005116 005216 005316 005416 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 Bus collision detection interrupt control register (BCNIC) UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control regster(S1TIC) UART1 receive interrupt control register(S1RIC) UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) UART0 transmit/receive mode register (U0MR) UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON) Figure 2.5.2. Memory map of UARTi-related registers 2-78 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit buffer register (Note) (b15) b7 (b8) b0 b7 b0 Symbol U0TB U1TB U2TB Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16 When reset Indeterminate Indeterminate Indeterminate Function RW Transmit data Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note: Use MOV instruction to write to this register. UARTi receive buffer register (b15) b7 (b8) b0 b7 b0 Symbol U0RB U1RB U2RB Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16 When reset Indeterminate Indeterminate Indeterminate Function (During UART mode) Receive data Bit symbol Bit name Function (During clock synchronous serial I/O mode) Receive data RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. ABT OER FER PER SUM Arbitration lost detecting flag (Note 2) 0 : Not detected 1 : Detected Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found Framing error flag (Note 1) Invalid Parity error flag (Note 1) Error sum flag (Note 1) Invalid Invalid Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016, 03A816 and 037816) are set to “0002” or the receive enable bit is set to “0”. (Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but “0” may be written. Nothing is assigned in bit 11 of U0RB and U1RB. When write, set “0”. The value, if read, turns out to be “0”. UARTi bit rate generator (Note 1, 2) b7 b0 Symbol U0BRG U1BRG U2BRG Address 03A116 03A916 037916 Function When reset Indeterminate Indeterminate Indeterminate Values that can be set 0016 to FF16 RW Assuming that set value = n, BRGi divides the count source by n+1 Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register. Figure 2.5.3. UARTi-related registers (1) 2-79 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiMR(i=0,1) Address 03A016, 03A816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 Function (During UART mode) b2 b1 b0 RW 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock 1 : External clock (Note) Invalid Odd/even parity select bit Invalid PRYE SLEP Parity enable bit Sleep select bit Invalid Must always be “0” Note : Set the corresponding port direction register to “0”. UART2 transmit/receive mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2MR Address 037816 When reset 0016 Bit symbol SMD0 SMD1 SMD2 Bit name Serial I/O mode select bit Function (During clock synchronous serial I/O mode) Must be fixed to 001 b2 b1 b0 Function (During UART mode) b2 b1 b0 RW 0 0 0 : Serial I/O invalid 0 1 0 : (Note 1) 0 1 1 : Must not be set. 1 1 1 : Must not be set. 1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set. 0 1 1 : Must not be set. 1 1 1 : Must not be set. CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit 0 : Internal clock 1 : External clock (Note 2) Must always be “0” 0 : One stop bit 1 : Two stop bits Invalid Odd/even parity select bit Invalid Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to “0” PRYE IOPOL Parity enable bit TxD, RxD I/O polarity reverse bit Invalid 0 : No reverse 1 : Reverse Usually set to “0” Note 1: Bit 2 to bit 0 are set to “0102” when I2C mode is used. Note 2: Set the corresponding port direction register to “0”. Figure 2.5.4. UARTi-related registers (2) 2-80 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC0(i=0,1) Bit symbol CLK0 CLK1 CRS Address When reset 03A416, 03AC16 0816 Function (During clock synchronous serial I/O mode) b1 b0 b1 b0 Bit name BRG count source select bit Function (During UART mode) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) RW 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) CTS/RTS function select bit TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge NCH Data output select bit CKPOL CLK polarity select bit Must always be “0” UFORM Transfer format select bit 0 : LSB first 1 : MSB first Must always be “0” Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. UART2 transmit/receive control register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C0 Bit symbol CLK0 CLK1 CRS CTS/RTS function select bit Address 037C16 When reset 0816 Function (During clock synchronous serial I/O mode) Function (During UART mode) b1 b0 Bit name BRG count source select bit RW b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set. Valid when bit 4 = “0” 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2) TXEPT 0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0: TXDi pin is CMOS output open-drain output CRD CTS/RTS disable bit 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : TXDi pin is CMOS output open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge Nothing is assigned. CKPOL 1: to be “ is In an attempt to write to this bit, write1“:0TXDi pin is N-channel turns out TXDi pin0”. N-channel ”. The value, if read, CLK polarity select bit Must always be “0” UFORM Transfer format select bit 0 : LSB first 1 : MSB first (Note 3) 0 : LSB first 1 : MSB first Note 1: Set the corresponding port direction register to “0”. Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid. Figure 2.5.5. UARTi-related registers (3) 2-81 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UARTi transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol UiC1(i=0,1) Address 03A516,03AD16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register RW RE RI Receive enable bit Receive complete flag Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. UART2 transmit/receive control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2C1 Address 037D16 When reset 0216 Bit symbol TE TI Bit name Transmit enable bit Transmit buffer empty flag Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse Must be fixed to “0” Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) Must always be "0" RW RE RI Receive enable bit Receive complete flag U2IRS UART2 transmit interrupt cause select bit U2RRM UART2 continuous receive mode enable bit U2LCH Data logic select bit U2ERE Error signal output enable bit 0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled Figure 2.5.6. UARTi-related registers (4) 2-82 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER UART transmit/receive control register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol UCON Address 03B016 When reset X00000002 Bit symbol U0IRS Bit name UART0 transmit interrupt cause select bit Function (During clock synchronous serial I/O mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) Function (During UART mode) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) RW U1IRS UART1 transmit interrupt cause select bit 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) U0RRM UART0 continuous receive mode enable bit 0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode (CLK output is CLK1 only) Must always be “0” U1RRM UART1 continuous receive mode enable bit Must always be “0” CLKMD0 CLK/CLKS select bit 0 Invalid CLKMD1 CLK/CLKS select bit 1 (Note) Must always be “0” 1 : Transfer clock output from multiple pins function selected Reserved bit Must always be set to “0” Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: • UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”. UART2 special mode register b7 b6 b5 b4 b3 b2 b1 b0 Symbol U2SMR Address 037716 When reset 0016 Bit symbol Bit name Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : I2C mode 0 : Update per bit 1 : Update per byte 0 : STOP condition detected 1 : START condition detected Function (During UART mode) RW IICM ABC BBS LSYN ABSCS I2C mode select bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit Must always be “0” Must always be “0” Must always be “0” (Note1) 0 : Disabled 1 : Enabled Must always be “0” 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 Must always be “0” ACSE Must always be “0” 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RXD2 SSS Must always be “0” SDDS SDA digital delay select bit (Note 2, Note 3) 0 : Analog delay output is selected 1 : Digital delay output is selected (must always be “0” when not using I 2 C mode) Must always be “0” Note 1: Nothing but “0” may be written. Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA digital delay setup bits) are initialized to “000”, with the analog delay circuit selected. Also, when SDDS = “0”, the U2SMR3 register cannot be read or written to. Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected, only the digital delay value is effective. Figure 2.5.7. UARTi-related registers (5) 2-83 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.5.2 Operation of Serial I/O (transmission in UART mode) In transmitting data in UART mode, choose functions from those listed in Table 2.5.4. Operations of the circled items are described below. Figure 2.5.8 shows the operation timing, and Figures 2.5.9 and 2.5.10 show the set-up procedures. Table 2.5.4. Choosed functions Item Transfer clock source (Note 1) CTS function O Set-up Internal clock (f1 / f8 / f32) External clock (CLKi pin) O CTS function enabled CTS function disabled Transmission interrupt factor O Transmission buffer empty Transmission complete Item Sleep mode (Note 1) Data logic select function (Note 2) TXD, RXD I/O polarity reverse bit (Note 2) Bus collision detection function (Note 2) O Set-up Sleep mode off Sleep mode selected O No reverse Reverse O No reverse Reverse O Not selected Selected Note 1: UART0, UART1 only. Note 2: UART2 only. Operation (1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit buffer register readies the data transmissible status. ________ ________ (2) When input to the CTSi pin goes to “L”, transmission starts (the CTSi pin needs to be controlled on the reception side). (3) Transmission data held in the UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the first bit (the start bit) of the transmission data is transmitted from the TxDi pin. Then, data is transmitted, bit by bit, in sequence: LSB, ····, MSB, parity bit, and stop bit(s). (4) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which indicates that transmission is completed. At this time, the UARTi transmit interrupt request bit goes to “1”. The transfer clock stops at “H” level. (5) If the transmission condition of the next data is ready when transmission is completed, a start bit is generated following to stop bit(s), and the next data is transmitted. 2-84 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example of wiring (Note) Microcomputer Receiver side IC TXDi CTSi RXD Port Note: Since TXD2 pin is N-channel open drain, this pin needs pull-up resistor. Example of operation Tc Transfer clock (1) Transmission enabled (2) Confirme CTS (3) Start transmission Transmit enable bit (TE) “1” “0” Data is set in UARTi transmit buffer register (4) Confirme stop bit (5) Start transmission When confirming stop bit, stopped transfer clock once because CTS = “H” Started transfer clock again to start transmitting immediately after confirming CTS = “L” Transmit buffer “1” empty flag (Tl) “0” Transferred from UARTi transmit buffer register to UARTi transmit register “H ” CTSi “L” Start bit TxDi Transmit register empty flag (TXEPT) “1” “0” Parity Stop bit bit P SP Stopped pulsing because transfer enable bit = “0” P SP ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 ST D0 D1 D2 D3 D4 D5 D6 D7 Transmit “1” interrupt request “0” bit (IR) Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • CTS function is selected. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi Figure 2.5.8. Operation timing of transmission in UART mode 2-85 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting UARTi transmit/receive mode register (i=0 to 2) b7 b0 0 10 0 0 10 1 UART0 transmit/receive mode register U0MR [Address 03A016] UART1 transmit/receive mode register U1MR [Address 03A816] Serial I/O mode select bit b2 b1 b0 b7 b0 0 1 0 00 1 0 1 UART2 transmit/receive mode register U2MR [Address 037816] Serial I/O mode select bit b2 b1 b0 1 0 1 : Transfer data 8 bits long Internal/external clock select bit 0 : Internal clock Stop bit length select bit 0 : One stop bit Odd/even parity select bit (Valid when bit 6 = “1”) 0 : Odd parity Parity enable bit 1 : Parity enabled Sleep select bit 0 : Invalid 1 0 1 : Transfer data 8 bits long Must always be “0” in UART mode Stop bit length select bit Stop bit length select bit 0 : One stop bit 0 : One stop bit Odd/even parity select bit (Valid when bit 6 = “1”) 0 : Odd parity Parity enable bit Parity enable bit 1 : Parity enabled 1 : Parity enabled TXD, RXD I/O polarity reverse bit Usually set to “0” Setting UARTi transmit/receive control register 0 (i = 0 to 2) b7 b0 0 0 0 0 UART0 transmit/receive control register 0 U0C0 [Address 03A416] UART1 transmit/receive control register 0 U1C0 [Address 03AC16] BRG count source select bit b1 b0 b7 b0 0 0 0 0 UART2 transmit/receive control register 0 U2C0 [Address 037C16] BRG count source select bit b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set CTS/RTS function select bit (Valid when bit 4 = “0”) 0 : CTS function is selected Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CTS/RTS disable bit 0 : CTS/RTS function enabled Data output select bit 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output Must always be “0” in UART mode Must always be “0” in UART mode 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set CTS/RTS function select bit (Valid when bit 4 = “0”) 0 : CTS function is selected Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CTS/RTS disable bit 0 : CTS/RTS function enabled Must always be “0” in UART mode Transfer format select bit 0 : LSB first Setting UART transmit/receive control register 2 and UART2 transmit/receive control register 1 b7 b0 0 0 0 0 UART transmit/receive control register 2 UCON [Address 03B016] UART0 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) UART1 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) Must always be “0” in UART mode Must always be “0” in UART mode Invalid in UART mode Must always be “0” in UART mode Reserved bit Must always be set to “0” b7 b0 00 0 UART2transmit/receive control register 1 UCON [Address 037D16] UART0 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) Must always be “0” in UART mode Data logic select bit 0 : No reverse Error signal output enable bit 0 : output enabled Continued to the next page Figure 2.5.9. Set-up procedure of transmission in UART mode (1) 2-86 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Setting UARTi bit rate generator (i = 0 to 2) b7 b0 UARTi bit rate generator (i = 0 to 2) [Address 03A116, 03A916, 037916] UiBRG (i = 0 to 2) Can be set to 0016 to FF16 (Note) Note: Write to UARTi bit rate generator when transmission/reception is halted. Transmission enabled b7 b0 UART0 transmit/receive control register 1 U0C1 [Address 03A516] 1 UART1 transmit/receive control register 1 U1C1 [Address 03AD16] Transmit enable bit 1 : Transmission enabled b7 b0 UART2 transmit/receive control register 1 1 U2C1 [Address 037D16] Transmit enable bit 1 : Transmission enabled Writing transmit data (b15) b7 (b8) b0 b7 b0 UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB UART2 transmit buffer register [Address 037B16, 037A16] U2TB Setting transmission data When CTSi input level = “L” Start transmission Checking the status of UARTi transmit/receive control (i = 0 to 2) b7 b0 UART0 transmit/receive control register 1 U0C1 [Address 03A516] UART1 transmit/receive control register 1 U1C1 [Address 03AD16] Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled) b7 b0 UART2 transmit/receive control register 1 U2C1 [Address 037D16] Transmit buffer empty flag 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register (Writing next transmit data enabled) Writing next transmit data (b15) b7 (b8) b0 b7 b0 UART0 transmit buffer register [Address 03A316, 03A216] U0TB UART1 transmit buffer register [Address 03AB16, 03AA16] U1TB UART2 transmit buffer register [Address 037B16, 037A16] U2TB Setting transmission data Transmission is complete Figure 2.5.10. Set-up procedure of transmission in UART mode (2) 2-87 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.5.3 Operation of Serial I/O (reception in UART mode) In receiving data in UART mode, choose functions from those listed in Table 2.5.5. Operations of the circled items are described below. Figure 2.5.11 shows the operation timing, and Figures 2.5.12 and 2.5.13 show the set-up procedures. Table 2.5.5. Choosed functions Item Transfer clock source (Note 1) RTS function O Set-up Internal clock (f1 / f8 / f32) External clock (CLKi pin) O RTS function enabled RTS function disabled Sleep mode (Note 1) O Sleep mode off Sleep mode selected Item Data logic select function (Note 2) TXD, RXD I/O polarity reverse bit (Note 2) Bus collision detection function (Note 2) O Set-up No reverse Reverse O No reverse Reverse O Not selected Selected Note 1: UART0, UART1 only. Note 2: UART2 only. Operation (1) Setting the receive enable bit to “1” readies data-receivable status. At this time, output from ________ the RTSi pin goes to “L” level to inform the transmission side that the receivable status is ready. (2) When the first bit (the start bit) of reception data is received from the RxDi pin, output from the _______ RTS goes to “H” level. Then, data is received, bit by bit, in sequence: LSB, ····, MSB, and stop bit(s). (3) When the stop bit(s) is (are) received, the content of the UARTi receive register is transmitted to the UARTi receive buffer register. At this time, the receive complete flag goes to “1” to indicate that the reception is completed, the _______ UARTi receive interrupt request bit goes to “1”, and output from the RTS pin goes to “H” level. (4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register is read. 2-88 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example of wiring Microcomputer Transmitter side IC RXDi RTSi TXD Port Example of operation (4) Data is read (1) Reception enabled (2) Start reception BRGi's count source Receive enable bit (RE) RxDi “1” “0” (3) Receiving is completed Start bit Sampled “L” D0 D1 D7 Stop bit Receive data taken in Transfer clock Reception started when transfer clock is generated by falling edge of start bit Transferred from UARTi receive register to UARTi receive buffer register Receive complete flag (RI) RTSi Receive interrupt request bit (IR) “1” “0” “H” “L” “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timing of transfer data 8 bits long applies to the following settings : •Transfer data length is 8 bits. •Parity is disabled. •One stop bit •RTS function is selected. Figure 2.5.11. Operation timing of reception in UART mode 2-89 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting UARTi transmit/receive mode register (i=0 to 2) b7 b0 UART0 transmit/receive mode register U0MR [Address 03A016] b7 b0 0 0 0 0 1 01 UART1 transmit/receive mode register U1MR [Address 03A816] Serial I/O mode select bit b2 b1 b0 00 0 0 10 1 UART2 transmit/receive mode register U2MR [Address 037816] Serial I/O mode select bit b2 b1 b0 1 0 1 : Transfer data 8 bits long Internal/external clock select bit 0 : Internal clock Stop bit length select bit 0 : One stop bit Valid when bit 6 = “1” Parity enable bit 0 : Parity diabled Sleep select bit 0 : Sleep mode deselected 1 0 1 : Transfer data 8 bits long Must always be “0” in UART mode Stop bit length select bit 0 : One stop bit Valid when bit 6 = “1” Parity enable bit 0 : Parity diabled TXD,RXD I/O polarity reverse bit Usually set to “0” Setting UARTi transmit/receive control register 0 (i=0 to 2) b7 b0 0 00 0 1 UART0 transmit/receive control register 0 U0C0 [Address 03A416] UART1 transmit/receive control register 0 U1C0 [Address 03AC16] BRG count source select bit b1 b0 b7 b0 0 0 0 1 UART2 transmit/receive control register 0 U2C0 [Address 037C16] BRG count source select bit b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set CTS/RTS function select bit (Valid when bit 4 = “0”) 1 : RTS function is selected Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CTS/RTS disable bit 0 : CTS/RTS function enabled Data output select bit 0 : TxDi pin is CMOS output 1 : TxDi pin is N-channel open-drain output Must always be “0” in UART mode Must always be “0” in UART mode 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set CTS/RTS function select bit (Valid when bit 4 = “0”) 1 : RTS function is selected Transmit register empty flag 0 : Data present in transmit Transmit register empty flag register (during transmission) 0 : Data present in transmit register 1(during transmission) transmit register : No data present in (transmission completed) 1 : No data present in transmit register (transmission completed) CTS/RTS disable bit 0 : CTS/RTS function enabled Must be fixed to “0” in UART mode Must always be “0” in UART mode Transfer format select bit 0 : LSB first Setting UART transmit/receive control register 2 and UART2 transmit/receive control register 1 b7 b0 0 0 0 0 UART transmit/receive control register 2 UCON [Address 03B016] Must always be “0” in UART mode Must always be “0” in UART mode Invalid in UART mode Must always be “0” in UART mode Reserved bit Must always be set to “0” b7 b0 0 00 UART2 transmit/receive control register 1 U2C1 [Address 037D16] Must always be “0” in UART mode Data logic select bit 0 : No reverse Error signal output enable bit 0 : Output disabled Continued to the next page Figure 2.5.12. Set-up procedure of reception in UART mode (1) 2-90 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Setting UARTi bit rate generator(i = 0 to 2) b7 b0 UARTi bit rate generator (i = 0 to 2) [Address 03A116, 03A916, 037916] UiBRG (i = 0 to 2) Can be set to 0016 to FF16 (Note) Note: Write to UARTi bit rate generator when transmission/reception is halted. Reception enabled b7 b0 1 UART0 transmit/receive control register 1 U0C1 [Address 03A516] UART1 transmit/receive control register 1 U1C1 [Address 03AD16] Receive enable bit 1 : Reception enabled b7 b0 1 UART2 transmit/receive control register 1 U2C1 [Address 037D16] Receive enable bit 1 : Reception enabled Start reception Checking completion of reception b7 b0 UART0 transmit/receive control register 1 U0C1 [Address 03A516] UART1 transmit/receive control register 1 U1C1 [Address 03AD16] Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register b7 b0 UART2 transmit/receive control register 1 U2C1 [Address 037D16] Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register Checking error (b15) b7 (b8) b0 b7 b0 UART0 receive buffer register [Address 03A716, 03A616]U0RB UART1 receive buffer register [Address 03AF16, 03AE16]U1RB UART2 receive buffer register [Address 037F16, 037E16]U2RB Receive data Overrun error flag 0 : No overrun error 1 : Overrun error found Framing error flag 0 : No framing error 1 : Framing error found Parity error flag 0 : No parity error 1 : Parity error found Error sum flag 0 : No error 1 : Error found Processing after reading out reception data Figure 2.5.13. Set-up procedure of reception in UART mode (2) 2-91 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.5.4 Operation of Serial I/O (transmission used for SIM interface) In transmitting data in UART mode (used for SIM interface), choose functions from those listed in Table 2.5.6. Operations of the circled items are described below. Figure 2.5.14 shows the operation timing, and Figures 2.5.15 and 2.5.16 show the set-up procedures. Table 2.5.6. Choosed functions Item Transfer data format O Set-up Direct format Inverse format Operation (1) Setting the transmit enable bit and receive enable bit to “1” and writing transmission data to the UART2 transmit buffer register readies the data transmissible status. Set UART2 transfer interrupt is enabled. (2) Transmission data held in the UART2 transmit buffer register is transmitted to the UART2 transmit register. At this time, the first bit (the start bit) of the transmission data is transmitted from the TxD2 pin. Then, data is transmitted, bit by bit, in sequence: LSB, ····, MSB, parity bit, and stop bit(s). (3) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which indicates that transmission is completed. At this time, the UART2 transmit interrupt request bit goes to “1”. The transfer clock stops at “H” level. (4) If the transmission condition of the next data is ready when transmission is completed, a start bit is generated following to stop bit(s), and the next data is transmitted. (5) If a parity error occurs, an L is output from the SIM card, and the RxD2 terminal turns to the "L" level. Check the RxD2 terminal's level within the UART2 transmission interrupt routine, and if it is found to be at the "L" level, then handle the error. Note • The parity error level is determined within a UART2 transmission interrupt. When a transmission interrupt request occurs, set the priority level of the transmission interrupt higher than those of other interrupts so that the interrupt routine can be immediately carried out. Either in the main routine or in an interrupt routine, the interrupt inhibition time has to be made as short as possible. • Set the RxD2 terminal's direction register to input. 2-92 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example of wiring Microcomputer SIM card TxD2 RxD2 Example of operation (when direct format) (1) Transmission enabled (2) Start transmission (3) Confirme stop bit (4) Start transmission (5) Dispose parity error Tc Transfer clock Transmit enable bit (TE) Transmit buffer empty flag (Tl) “1” “0” “1” “0” (Note 1) Data is set in UART2 transmit buffer register Transferred from UART2 transmit buffer register to UART2 transmit register Start bit Parity Stop bit bit P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TXD2 (Note 2) RXD2 (Note 2) ST D0 D1 D2 D3 D4 D5 D6 D7 Since a parity error occurred, the “L” level returns from TxD2 Signal line level (Note 2) Transmit buffer empty flag (TEXPT) Transmit interrupt request bit (IR) “1” “0” “1” “0” ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Detects the level using an interrupt routine Detects the level using an interrupt routine Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Note 2: TxD2 and RxD2 are connected in the manner of wired OR as shown in the connection diagram. So TxD2 and RxD2 ought to become the same signal from the logical standpoint, but the output signals turn complex, so they are shown separately. Also, the signal level resulting from connecting TxD2 and RxD2 is shown as a signal line level. Figure 2.5.14. Operation timing of transmission in UART mode (used for SIM interface) 2-93 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting UART2 transmit/receive mode register b7 b0 0 11 00 1 0 1 UARTi transmit/receive mode register [Address 037816] U2MR Serial I/O mode select bit b2 b1 b0 1 0 1 : Transfer data 8 bits long Must always be “0” in UART mode Stop bit length select bit 0 : One stop bit Odd/even parity select bit (Valid when bit 6 = “1”) Must be “1” (even parity) in direct format Parity enable bit 1 : Parity enabled TXD, RXD I/O polarity reverse bit Usually set to “0” Setting UART2 transmit/receive control register 0 b7 b0 0 0 1 UART2 transmit/receive control register 0 [Address 037C16] U2C0 BRG count source select bit b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set Valid when bit 4 = “0” Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CTS/RTS disable bit 1 : CTS/RTS function disabled Must always be “0” in UART mode Transfer format select bit Must be “0” (LSB first) in direct format Setting UART2 transmit/receive control register 1 b7 b0 1 00 1 UART2 transmit/receive control register 1 [Address 037D16] U2C1 UART2 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) Must always be “0” in UART mode Data logic select bit Must be “0” (no reverse) in direct format Error signal output enable bit 1 : Output enabled Continued to the next page Figure 2.5.15. Set-up procedure of transmission in UART mode (used for SIM interface) (1) 2-94 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Setting UART2 bit rate generator b7 b0 UART2 bit rate generator [Address 037916] U2BRG Can be set to 0016 to FF16 (Note) Note: Write to UARTi bit rate generator when transmission/reception is halted. Transmit enabled b7 b0 1 1 UART2 transmit/receive control register 1 [Address 037D16] U2C1 Transmit enable bit 1 : Transmission enabled Receive enable bit 1 : Reception enabled Writing transmit data (b15) b7 (b8) b0 b7 b0 UART2 transmit buffer register [Address 037B16, 037A16] U2TB Setting transmission data UART2 transmit interrupt Confirm RXD2 pin level b7 b0 Port P7 register [Address 03ED16] P7 Port P71 register 0 : "L" level 1 : "H" level REIT instruction Figure 2.5.16. Set-up procedure of transmission in UART mode (used for SIM interface) (2) 2-95 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.5.5 Operation of Serial I/O (reception used for SIM interface) In receiving data in UART mode (used for SIM interface), choose functions from those listed in Table 2.5.7. Operations of the circled items are described below. Figure 2.5.17 shows the operation timing, and Figures 2.5.18 and 2.5.19 show the set-up procedures. Figure 2.5.7. Choosed functions Item Transfer data format O Set-up Direct format Inverse format Operation (1) Setting the transmit enable bit and receive enable bit to “1” readies data-receivable status. (2) When the first bit (the start bit) of reception data is received from the RxD2 pin, data is received, bit by bit, in sequence: LSB, ····, MSB, and stop bit(s). (3) When the stop bit(s) is (are) received, the content of the UART2 receive register is transmitted to the UART2 receive buffer register. At this time, the receive complete flag goes to “1” to indicate that the reception is completed, _______ the UART2 receive interrupt request bit goes to “1”, and output from the RTS pin goes to “H” level. (4) The receive complete flag goes to “0” when the lower-order byte of the UART2 buffer register is read. (5) When the parity error is occurred, TXD2 pin goes to “L” level. 2-96 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Example of wiring Microcomputer SIM card TxD2 RxD2 Example of operation (when direct format) (1) Reception enabled (2) Start reception (3) Receiving is completed (4) Data is read (5) Parity error occurred Tc Transfer clock Receive enable bit(RE) “1” “0” Start bit Parity bit P Stop bit SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RXD2 (Note) TXD2 (Note) Signal line level (Note) Receive complete flag(RI) Receive interrupt request bit(IR) “1” “0” “1 ” “0 ” ST D0 D1 D2 D3 D4 D5 D6 D7 Since a parity error occurred, the “L” level returns from TxD2 ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Read to receive buffer Read to receive buffer Cleared to “0” when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : • Parity is enabled. • One stop bit. • Transmit interrupt cause select bit = “1”. Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2 Note: TxD2 and RxD2 are connected in the manner of wired OR as shown in the connection diagram. So TxD2 and RxD2 ought to become the same signal from the logical standpoint, but the output signals turn complex, so they are shown separately. Also, the signal level resulting from connecting TxD2 and RxD2 is shown as a signal line level. Figure 2.5.17. Operation timing of reception in UART mode (used for SIM interface) 2-97 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting UART2 transmit/receive mode register b7 b0 0 1 10 01 0 1 UART2 transmit/receive mode register [Address 037816] U2MR Serial I/O mode select bit b2 b1 b0 1 0 1 : Transfer data 8 bits long Must always be “0” in UART mode Stop bit length select bit 0 : One stop bit Odd/even parity select bit (Valid when bit 6 = “1”) Must always be “1” (odd parity) in direct format Parity enable bit 1 : Parity enabled TXD, RXD I/O polarity reverse bit Usually set to “0” Setting UART2 transmit/receive control register 0 b7 b0 0 0 1 UART2 transmit/receive control register 0 [Address 037C16] U2C0 BRG count source select bit b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set Valid when bit 4 = “0” Transmit register empty flag 0 : Data present in transmit register (during transmission) 1 : No data present in transmit register (transmission completed) CTS/RTS disable bit 1 : CTS/RTS function disabled Must always be “0” in UART mode Transfer format select bit Must always be “0” (LSB first) in direct format Setting UART2 transmit/receive control register 1 b7 b0 100 1 UART2 transmit/receive control register 1 [Address 037D16] U2C1 UART2 transmit interrupt cause select bit 1 : Transmission completed (TXEPT = 1) Must always be “0” in UART mode Data logic select bit Must always be “0” (no reverse) in direct format Error signal output enable bit 1 : Output enabled Continued to the next page Figure 2.5.18. Set-up procedure of reception in UART mode (used for SIM interface) (1) 2-98 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Setting UART2 bit rate generator b7 b0 UART2 bit rate generator [Address 037916] U2BRG Can be set to 0016 to FF16 (Note) Note: Write to UART2 bit rate generator when transmission/reception is halted. Transmit enabled b7 b0 1 1 UART2 transmit/receive control register 1 [Address 037D16] U2C1 Transmit enable bit 1 : Transmission enabled Receive enable bit 1 : Reception enabled Start reception Checking completion of reception b7 b0 UART2 transmit/receive control register 1 [Address 037D16] U2C1 Receive complete flag 0 : No data present in receive buffer register 1 : Data present in receive buffer register Checking error (b15) b7 (b8) b0 b7 b0 UART2 receive buffer register [Address 037F16, 037E16] U2RB Receive data Overrun error flag 0 : No overrun error 1 : Overrun error found Framing error flag 0 : No framing error 1 : Framing error found Parity error flag 0 : No parity error 1 : Parity error found Error sum flag 0 : No error 1 : Error found Processing after reading out reception data Figure 2.5.19. Set-up procedure of reception in UART mode (used for SIM interface)(2) 2-99 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.5.6 Clock Signals in used for the SIM Interface In conforming to the SIM interface, the UART clock signal within the SIM card needs to conform to the UART2 clock signal within the microprocessor. Two examples are given here as means of generating a UART2 clock signal within the microprocessor. * In the case of setting a value equal to or less than (1/256 X 1/16) in the division rate of UART2 clock Choose f1 for the UART’s source clock signal and set an optional value in the bit rate generator. * In the case of setting a value equal to or greater than (1/256 X 1/16) in the division rate of UART2 clock Set the bit rate generator to "0", turn the source clock signal to timer output and set an optional value in the timer. In order to maintain the synchronization, the serial I/O mode select bits must be reset to “0002”, then the UART2 transmit/receive mode register is set back to the original setting at every one byte transmission. Let F be the clock signal within the SIM card and D be the bit rate adjustment factor, then the formula for the UART clock signal becomes as follows. Figure 2.5.20 shows an example of connection. • In the case of setting a value equal to or less than (1/256 X 1/16) in the division rate of UART2 clock UART2 clock signal within microprocessor = UART clock within SIM card f1 x 1 Bit rate generator + 1 x 1 16 = f1 x 1 x flip-flop x F/D Timer Ai counter + 1 1 Let XIN = 16 MHz, timer Ai counter = 1, F = 372, and D = 1, then the value to be set in the bit rate generator becomes 16 x 1 Bit rate generator + 1 x 1 16 =16 x 1 1 1 x x 2 372/1 2 Bit rate generator = 92 Table 2.5.8 shows an example of setting in the UART2 bit rate generator. • In the case of setting a value equal to or greater than (1/256 X 1/16) in the division rate of UART2 clock UART2 clock signal within microprocessor = UART clock within SIM card 1 1 x flip-flop x Timer Aj counter + 1 Bit rate generator + 1 1 1 = f1 x x flip-flop x F/D Bit rate generator + 1 f1 x x 1 16 Let XIN= 16 MHz, timer Ai counter = 3, bit rate generator = 0, F = 1860, and D = 1, then the value to be set in the timer Aj counter becomes 16 x 1 1 1 1 x 2 x 0 + 1 x 16 Timer Aj counter + 1 =16 x 1 3+1 x 1 x 2 1 1860/1 Timer Aj counter = 464 Table 2.5.9 shows an example of setting in the timer Aj counter. 2-100 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock generator XIN TAiOUT TAjOUT SIM CARD Timer Ai counter flip-flop CLK Timer Aj counter f1 flip-flop 1 F/D SIM card internal clock frequency division ratio External clock CLK2 UART clock UART2 bit rate generator UART 1/16 UART2 clock RxD2 UART TxD2 Figure 2.5.20. Example of connection 2-101 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 2.5.8. UART2 bit rate adjustment factor SIM card internal clock F(Hz) 372 Bit rate D 1 2 4 8 16 1/2 1/4 1/8 1/16 1/32 1/64 F/D 372 186 93 UART2 bit rate generator set value 92 SIM card internal clock F(Hz) 1116 Bit rate D 1 2 4 8 16 F/D 1116 558 279 UART2 bit rate generator set value 744 1488 2976 5952 11904 23808 558 279 185 1/2 1/4 1/8 1/16 1/32 1/64 1488 1 2 4 8 16 2232 4464 8928 17856 35712 71424 1488 744 372 186 93 2976 5952 11904 23808 47616 95232 1860 930 465 185 92 558 1 2 4 8 16 1/2 1/4 1/8 1/16 1/32 1/64 1116 2232 4464 8928 17856 35712 744 372 186 93 1488 2976 5952 11904 23808 47616 Combination impossible 185 92 1860 1/2 1/4 1/8 1/16 1/32 1/64 1 2 4 8 16 1/2 1/4 1/8 1/16 1/32 744 1 2 4 8 16 1/2 1/4 1/8 1/16 1/32 1/64 3720 7440 14880 29760 59520 1/64 119040 Combination in which the F/D itself does not become an integer Setting example under the following conditions. f(XIN)=16MHz Timer Ai counter set value = 1 2-102 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 2.5.9. TimerAi register adjustment factor SIM card internal clock F(Hz) 372 Bit rate D 1 2 4 8 16 1/2 1/4 1/8 1/16 1/32 1/64 Timer Ai value F/D 372 186 93 92 SIM card internal clock F(Hz) 1116 Bit rate D 1 2 4 8 16 Timer Aj value F/D 1116 558 279 278 744 1488 2976 5952 11904 23808 558 279 185 371 743 1487 2975 5951 1488 1/2 1/4 1/8 1/16 1/32 1/64 1 2 4 8 16 2232 4464 8928 17856 35712 71424 1488 744 372 186 93 2976 5952 11904 23808 47616 95232 1860 930 465 557 1115 2231 4463 8927 17855 371 185 92 558 1 2 4 8 16 1/2 1/4 1/8 1/16 1/32 1/64 1116 2232 4464 8928 17856 35712 744 372 186 93 1488 2976 5952 11904 23808 47616 278 557 1115 2231 4463 8927 185 92 1860 1/2 1/4 1/8 1/16 1/32 1/64 1 2 4 8 16 743 1487 2975 5951 11903 23807 464 744 1 2 4 8 16 1/2 1/4 1/8 1/16 1/32 1/64 371 743 1487 2975 5951 11903 1/2 1/4 1/8 1/16 1/32 1/64 3720 7440 14880 29760 59520 119040 929 1859 3719 7439 14879 29759 Combination impossible Combination in which the F/D itself does not become an integer Setting example under the following conditions. f(XIN)=16MHz Timer Ai counter set value = 3, UART2 bit rate generator set value = 0 2-103 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.5.7 Error-permitted range range of transfer baud During reception, the receive data input to the RXDi pin is taken at the rising edge of the transfer clock. Accordingly, in order to receive data correctly, the stop bit must be input when the transfer clock of oneset receive data rises last. Figure 2.5.21 shows the relationship between the transfer clock and receive data. When the transfer rate of the receive data is faster than the rate of the transfer clock on the receiver side When the transfer rate of the receive data is slower than the rate of the transfer clock on the receiver side Transfer clock (Receiver side) 1 clock 8 clocks 9.5 clocks ∗ 1 period of BRGi's count source (Maximum) ••• According to the condition of the input timing, a maximum of this period (∗) can be omitted. ST : Start bit SP : Stop bit ST ST D0 D0 D7 D7 SP SP SP must be detected at this last rising edge of the transfer clock. RxDi (Receive data) At the falling edge of ST, the transfer clock is generated, and reception starts. ∗ 1 clock Figure 2.5.21 Relationship between transfer clock and receive data 2-104 Mitsubishi microcomputers UART M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Accordingly, the transfer rate of the receiver and transmitter sides must satisfy the following fomula in order to receive data correctly. 1 Bt 1 Br 1 Bt x (b – 1) + 1 F < x (b – 0.5) + 1 F < xb Br : Transfer rate on receiver side (bps) Bt : Transfer rate on transmitter side (bps) F : BRGi's count source frequency on receiver side (Hz) b : Entire bit number of one-set data (ex : 12 bits in the case of 1ST-8DATA-1PAR-2SP; See Figure 2.5.1) Be sure to satisfy the above formula, and set the timing with enough margin. Also, the user shall make sufficient evaluation before actually using it. 2-105 Mitsubishi microcomputers SI/O3, 4 M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.6 SI/O3, 4 Usage 2.6.1 Overview of the SI/O3,4 usage SI/O3, 4 carries out 8-bit data communications in synchronization with the clock. The following is an overview of the SI/O3, 4 usage. (1) Transmission/reception format 8-bit data (2) Transfer rate If the internal clock is selected as the transfer clock, the divide-by-2 frequency, resulting from the bit rate generator division, becomes the transfer rate. The bit rate generator count source can be selected from the following: f1, f8, and f32. Clocks f1, f8, and f32 are derived by dividing the CPU’s main clock by 1, 8, and 32 respectively. Furthermore, if an external clock is selected as the transfer clock, the clock frequency input to the CLK pin becomes the transfer rate. (3) Function selection For SI/O3, 4, the following functions can be selected: (a) Function for choosing which bit to transmit first This function is to choose whether to transmit data from bit 0 or from bit 7. Choose either of the following: • LSB first Data is transmitted from bit 0. • MSB first Data is transmitted from bit 7. (b) Choosing output level when not transferring • Internal clock High-impedance output. • External clock "H" or "L" output level is selected. (6) Input to the serial I/O and the direction register To input an external signal to the serial I/O, set the direction register of the relevant port to input. (7) Pins related to the SI/O3, 4 • CLK3, CLK4 pins Input/output pins for the transfer clock • SIN3, SIN4 pins Input pins for data • SOUT3, SOUT4 pins Output pins for data (8) Registers related to the SI/O3, 4 Figure 2.6.1 shows the memory map of SI/O3, 4-related registers, and Figures 2.6.2 show SI/O3, 4related registers. 004816 004916 036016 036116 036216 036316 036416 036516 036616 036716 SI/O4 interrupt control register (S4IC) SI/O3 interrupt control register (S3IC) SI/O3 transmit/receive register (S3TRR) SI/O3 transmit/receive control register (S3C) SI/O3 bit rate generator (S3BRG) SI/O4 transmit/receive register (S4TRR) SI/O4 control register (S4C) SI/O4 bit rate generator (S4BRG) Figure 2.6.1. Memory map of serial I/O3, 4-related registers 2-106 Mitsubishi microcomputers SI/O3, 4 M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER S I/Oi control register (i = 3, 4) (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol SiC Bit symbol SMi0 SMi1 SMi2 SMi3 Address 036216, 036616 Bit name When reset 4016 Description b1 b0 RW Internal synchronous clock select bit 0 0 : Selecting f1 0 1 : Selecting f8 1 0 : Selecting f32 1 1 : Must not be set. 0 : SOUTi output 1 : SOUTi output disable(high impedance) 0 : Input-output port 1 : SOUTi output, CLK function SOUTi output disable bit S I/Oi port select bit (Note 2) Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”. SMi5 SMi6 SMi7 Transfer direction select bit Synchronous clock select bit (Note 2) SOUTi initial value set bit 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock Effective when SMi3 = 0 0 : L output 1 : H output Note 1: Set “1” in bit 2 of the protection register (000A16) in advance to write to the S I/Oi control register (i = 3, 4). Note 2: When using the port as an input/output port by setting the SI/Oi port select bit (i = 3, 4) to “0”, be sure to set the sync clock select bit to “1”. SI/Oi bit rate generator (Note 1, 2) b7 b0 Symbol S3BRG S4BRG Address 036316 036716 When reset Indeterminate Indeterminate Values that can be set 0016 to FF16 RW Indeterminate Assuming that set value = n, BRGi divides the count source by n + 1 Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register. SI/Oi transmit/receive register (Note) b7 b0 Symbol S3TRR S4TRR Address 036016 036416 Indeterminate When reset Indeterminate Indeterminate RW Transmission/reception starts by writing data to this register. After transmission/reception finishes, reception data is input. Note: Write a value to this register while transmit/receive halts. Figure 2.6.2. Serial I/O3, 4-related registers 2-107 Mitsubishi microcomputers SI/O3, 4 M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.6.2 Operation of SI/O3,4 In transmitting data in this mode, choose functions from those listed in Table 2.6.1. Operations of the circled items are described below. Figure 2.6.3 shows the operation timing, and Figures 2.6.4 and 2.6.5 show the set-up procedures. Table 2.6.1. Choosed functions Item Transfer clock source Transfer clock O Set-up Internal clock (f1 / f8 / f32) External clock (CLKi pin) O LSB first MSB first Item SOUTi initial value set function O Set-up Not used Used Operation (1) Transfer begins upon writing the SI/Oi transmit data. The transmit data is sent out from the SOUTi pin synchronously with falling edges of the transfer clock. (2) When SOUT finishes sending one byte of data, the interrupt request bit is set to 1. (3) After the transfer is completed, SOUT holds the last data for a 1/2 transfer clock period before going to a high-impedance state. Note • Do not write data to the SI/Oi transmit/receive register (i = 3, 4; addresses 036016, 036416) during a transfer. • Data can only be written to the SI/Oi transmit/receive register when the device is idle neither sending nor receiving data. Example of wiring Microcomputer CLKi SOUTi Receiver side IC CLK SIN Example of operation (1) Transmission enabled 1.5 TCLK (Max) (2) Transmission is complete (3) Highimpedance Internal clock SI/Oi transmit/receive register write signal TCLK SI/Oi output SOUTi CLKi SI/Oi input SINi SI/Oi interrupt request bit (i = 3, 4) Cleared to “0” when interrupt request is accepted, or cleared by software "1" "0" D0 D1 D2 D3 D4 D5 D6 D7 Hi-Z TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to SiBRG Figure 2.6.3. Operation timing of transmission in SI/O3, 4 mode 2-108 Mitsubishi microcomputers SI/O3, 4 M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clearing the protect (set to write-enabled state) b7 b0 1 Protect register [Address 000A16] PRCR Enables writing to port P9 direction register (address 03F316) and SI/Oi control register (i=3,4) (addresses 036216 and 036616) 1 : Write-enabled Setting SI/Oi transmit/receive control register (i=3, 4) b7 b0 10 10 SI/Oi transmit/receive control register (i=3,4) [Address 036216, 036616] SiC(i=3,4) Internal synchronous clock select bit b1 b0 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set SOUTi output disable bit 0 : SOUTi output SI/Oi port select bit 1 : SOUTi output, CLK function Transfer format select bit 0 : LSB first Synchronous clock select bit 1 : Internal clock SOUTi initial value set bit(Effective when SMi3=0) 0 : L output 1 : H output Note 1: Be sure to set the protect register and SI/Oi control register successively. Setting SI/Oi bit rate generator (i = 3, 4) b7 b0 SI/Oi bit rate generator (i = 3, 4) [Address 036316, 036716] SiBRG (i = 3, 4) Can be set to 0016 to FF16 (Note 2) Note 2: Write to SI/Oi bit rate generator when transmission/reception is halted. Writing transmit data b7 b0 SI/Oi transmit/receive register (i=3, 4) [Address 036016, 036416] SiTRR (i=3, 4) Setting transmission data (Note 3) Note 3: Write to SI/Oi transmit/receive register when transmission/reception is halted. SI/Oi interrupt request bit 1 0 Wait for a 1/2 transfer clock period Transfer the next data Figure 2.6.4. Set-up procedure of transmission in SI/O3, 4 mode 2-109 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7 A-D Converter Usage 2.7.1 Overview of the A-D converter usage The A-D converter used in the M16C/62A group operates on a successive conversion basis. The following is an overview of the A-D converter usage. (1) Mode The A-D converter operates in one of five modes: (a) One-shot mode Carries out A-D conversion on input level of one specified pin only once. (b) Repetition mode Repeatedly carries out A-D conversion on input level of one specified pin. (c) One-shot sweep mode Carries out A-D conversion on input level of two or more specified pins only once. (d) Repeated sweep mode 0 Repeatedly carries out A-D conversion on input level of two or more pins. (e) Repeated sweep mode 1 Repeatedly carries out A-D conversion on input level of two or more pins. This mode is different from the repeated sweep mode 0 in that weights can be assigned to specifing pins control the number of conversion times. (2) Operation clock The operation clock in 5 V operation can be selected from the following: fAD, divide-by-2 fAD, and divide-by-4 fAD. In 3 V operation, the selection is divide-by-2 fAD or divide-by-4. The fAD frequency is equal to that of the CPU’s main clock. (3) Conversion time Number of conversion for A-D convertor varies depending on resolution as given. Table 2.7.1 shows relation between the A-D converter operation clock and conversion time. Sample & Hold function selected: 33 φ cycles for 10-bit resolution, or 28 φ cycles for 8-bit resolution AD AD No Sample & Hold function: 59 φ cycles for 10-bit resolution, or 49 φ cycles for 8-bit resolution AD AD Table 2.7.1. Conversion time every operation clock Frequency selection bit 1 Frequency selection bit 0 A-D converter's operation clock Min. conversion cycles (Note 1) Min. conversion time (Note 2) 8-bit mode 10-bit mode 8-bit mode 10-bit mode 11.2µs 13.2µs φAD = 0 fAD 4 28 X φAD 33 X φAD 5.6µs 6.6µs 2.8µs 3.3µs φAD = 0 1 fAD 2 1 Invalid φAD = fAD Note 1: The number of conversion cycles per one analog input pin. Note 2: The conversion time per one analog input pin (when fAD = f(XIN) = 10 MHz) 2-110 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (4) Functions selection (a) Sample & Hold function Sample & Hold function samples input voltage when A-D conversion starts and carries out A-D conversion on the voltage sampled. When A-D conversion starts, input voltage is sampled for 3 cycles of the operation clock. When the Sample & Hold function is selected, set the operation clock for A-D conversion to 1 MHz or higher. (b) 8-bit A-D to 10-bit A-D switching function Either 8-bit resolution or 10-bit resolution can be selected. When 8-bit resolution is selected, the 8 higher-order bits of the 10-bit A-D are subjected to A-D conversion. The equations for 10-bit resolution and 8-bit resolution are given below: 10-bit resolution (Vref X n / 210 ) – (Vref X 0.5 / 210 ) (n = 1 to 1023), 0 (n = 0) 8-bit resolution (Vref X n / 28 ) – (Vref X 0.5 / 210 ) (n = 1 to 255), 0 (n = 0) (c) A-D conversion by external trigger The user can select software or an external pin input to start A-D conversion. (d) External operation amplifier connection function The selected A-D convertor pin input voltage can be output from the ANEX0 pin. By connecting an operation amplifier between the ANEX1 pin and ANEX0 pin when using this function, the input voltage to all A-D conversion pins can be amplified with one operation amplifier. (e) Expanded analog input pins function A-D conversion can be done for voltage input from either the ANEX0 pin or the ANEX1 pin. (f) Connecting or cutting Vref Cutting Vref allows decrease of the current flowing into the A-D converter. To decrease the microcomputer's power consumption, cut Vref. To carry out A-D conversion, start A-D conversion 1 µs or longer after connecting Vref. The following are exsamples in which functions (a) through (f) are selected: • One-shot mode ...................................................................................................................... P2-116 ___________ • One-shot mode, trigger by ADTRG ............................................................................................................... P2-118 • One-shot mode, software trigger, expanded analog input ..................................................... P2-120 • One-shot mode, software trigger, external operation amplifier connected ............................ P2-122 • Repeat mode, software trigger .............................................................................................. P2-124 • One-shot sweep mode, software trigger ................................................................................ P2-126 • Repeated sweep mode 0, software trigger ............................................................................ P2-128 • Repeated sweep mode 1, software trigger ............................................................................ P2-130 2-111 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (5) Input to A-D converter and direction register To use the A-D converter, set the direction register of the relevant port to input. (6) Pins related to A-D converter (a) AN0 pin through AN7 pin (b) AVcc pin (c) VREF pin (d) AVss pin (e) ANEX0 pin and ANEX1 pin ___________ (f) ADTRG pin Input pins of the A-D converter Power source pin of the analog section Input pin of reference voltage GND pin of the analog section Expanded input pins of the A-D converter Trigger input pin of the A-D converter (7) A-D converter and related registers Figure 2.7.1 shows the memory map of A-D converter-related registers, and Figures 2.7.2 through 2.7.4 show A-D converter-related registers. 004E16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D416 03D516 03D616 03D716 A-D conversion interrupt control register (ADIC) A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7) A-D control register 2 (ADCON2) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) Figure 2.7.1. Memory map of A-D converter-related registers 2-112 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON0 Bit symbol CH0 Address 03D616 Bit name When reset 00000XXX2 Function b2 b1 b0 RW Analog input pin select bit CH1 CH2 MD0 MD1 TRG ADST CKS0 Trigger select bit A-D conversion start flag Frequency select bit 0 A-D operation mode select bit 0 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected b4 b3 (Note 2) 0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected (Note 2) Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again. Figure 2.7.2. A-D converter-related registers (1) 2-113 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D control register 1 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON1 Bit symbol SCAN0 Address 03D716 Bit name When reset 0016 Function When single sweep and repeat sweep mode 0 are selected b1 b0 RW A-D sweep pin select bit 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 When repeat sweep mode 1 is selected b1 b0 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit External op-amp connection mode bit 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 0 : Vref not connected 1 : Vref connected b7 b6 BITS CKS1 VCUT OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted 1 1 : External op-amp connection mode Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Figure 2.7.3. A-D converter-related registers (2) 2-114 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER A-D control register 2 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol ADCON2 Address 03D416 When reset 0000XXX02 000 Bit symbol SMP Reserved bit Bit name A-D conversion method select bit Function 0 : Without sample and hold 1 : With sample and hold Must always be set to “0” RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. A-D register i (b15) b7 (b8) b0 b7 Symbol ADi(i=0 to 7) Address When reset 03C016 to 03CF16 Indeterminate b0 Function Eight low-order bits of A-D conversion result • During 10-bit mode Two high-order bits of A-D conversion result • During 8-bit mode When read, the content is indeterminate Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. RW Figure 2.7.4. A-D converter-related registers (3) 2-115 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.2 Operation of A-D converter (one-shot mode) In one-shot mode, choose functions from those listed in Table 2.7.2. Operations of the circled items are described below. Figure 2.7.5 shows the operation timing, and Figure 2.7.6 shows the set-up procedure. Table 2.7.2. Choosed functions Item Operation clock φAD Resolution Analog input pin Trigger for starting A-D conversion O Set-up Divided-by-4 fAD / dividedby-2 fAD / fAD Item Expanded analog input pin O Set-up Not used Either ANEX0 pin or ANEX1 pin External operation amplifier connection mode Sample & Hold O Not activated Activated O 8-bit / 10-bit O One of AN0 pin to AN7 pin O Software trigger Trigger by ADTRG Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to begin operating. (2) After A-D conversion is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register i. At this time, the A-D conversion interrupt request bit goes to “1”. Also, the A-D conversion start flag goes to “0”, and the A-D converter stops operating. (1) Start A-D conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (2) A-D conversion is complete φAD Set to “1” by software A-D conversion start flag “1 ” “0 ” A-D register i Result A-D conversion interrupt request “1 ” “0 ” Cleared to “0” when interrupt request is accepted, or cleared by software Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. Figure 2.7.5. Operation timing of one-shot mode 2-116 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting Sample and hold b7 b0 1 A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 b7 b0 b7 b0 0 0 0 0 A-D control register 0 [Address 03D616] ADCON0 Analog input pin select bit (Note) b2 b1 b0 0 0 1 0 A-D control register 1 [Address 03D716] ADCON1 Invalid in one-shot mode A-D operation mode select bit 1 (Note) 0 (Must always be “0” in one-shot mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected External op-amp connection mode bit b7 b6 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected One-shot mode is selected (Note) Trigger select bit 0 : Software trigger A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected Note: Rewrite to analog input pin select bit after changing A-D operation mode. 0 0 : ANEX0 and ANEX1 are not used Setting A-D conversion start flag b7 b0 1 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Start A-D conversion Stop A-D conversion Reading conversion result (b15) b7 (b8) b0 b7 b0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 [Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Figure 2.7.6. Set-up procedure of one-shot mode 2-117 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.3 Operation of A-D Converter (in one-shot mode, an external trigger selected) In one-shot mode, choose functions from those listed in Table 2.7.3. Operations of the circled items are described below. Figure 2.7.7 shows timing chart, and Figure 2.7.8 shows the set-up procedure. Table 2.7.3. Choosed functions Item Operation clock φAD Resolution Analog input pin Trigger for starting A-D conversion O Set-up Divided-by-4 fAD / dividedby-2 fAD / fAD Item Expanded analog input pin O Set-up Not used Either ANEX0 pin or ANEX1 pin External operation amplifier connection mode Sample & Hold O Not activated Activated O 8-bit / 10-bit O One of AN0 pin to AN7 pin Software trigger O Trigger by ADTRG ___________ Operation (1) If the level of the ADTRG changes from “H” to “L” with the A-D conversion start flag set to “1”, the A-D converter begins operating. (2) After A-D conversion is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register i. At this time, the A-D conversion interrupt request bit goes to “1”. Also the A-D converter stops operating. ___________ (3) If the level of the ADTRG pin changes from “H” to “L”, the A-D converter carries out conversion ___________ from step (1) again. If the level of the ADTRG pin changes from “H” to “L” while conversion is in progress, the A-D converter stops the A-D conversion in process, and carries out conversion from step (1) again. (1) Start A-D conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (2) A-D conversion is complete (3) Start A-D conversion φAD Set to “1” by software A-D conversion start flag “1” “0” “H” ADTRG “L” Result A-D register i A-D conversion “1” interrupt request “0” Cleared to “0” when interrupt request is accepted, or cleared by software Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. Figure 2.7.7. Operation timing of one-shot mode, with an external trigger selected 2-118 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting sample and hold b7 b0 1 A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 b7 b0 0 1 0 0 A-D control register 0 [Address 03D616] ADCON0 Analog input pin select bit (Note) b2 b1 b0 b7 b0 0 01 0 A-D control register 1 [Address 03D716] ADCON1 Invalid in one-shot mode A-D operation mode select bit 1 (Note) 0 (Must always be “0” in one-shot mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected External op-amp connection mode bit b7 b6 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : AN0 is selected 1 : AN1 is selected 0 : AN2 is selected 1 : AN3 is selected 0 : AN4 is selected 1 : AN5 is selected 0 : AN6 is selected 1 : AN7 is selected One-shot mode is selected (Note) Trigger select bit 1 : ADTRG trigger A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected Note: Rewrite to analog input pin select bit after changing A-D operation mode. 0 0 : ANEX0 and ANEX1 are not used Setting A-D conversion start flag b7 b0 1 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started When ADTRG pin level becomes from “H” to “L” Start A-D conversion Reading conversion result (b15) b7 (b8) b0 b7 b0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 [Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Setting A-D conversion start flag b7 b0 0 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled Stop A-D conversion Figure 2.7.8. Set-up procedure of one-shot mode, with an external trigger selected 2-119 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.4 Operation of A-D Converter (in one-shot mode, expanded analog input pin selected) In one-shot mode, choose functions from those listed in Table 2.7.4. Operations of the circled items are described below. Figure 2.7.9 shows timing chart, and Figure 2.7.10 shows the set-up procedure. Table 2.7.4. Choosed functions Item Operation clock φAD Set-up Divided-by-4 fAD / dividedO by-2 fAD / fAD O 8-bit / 10-bit O One of AN0 pin to AN7 pin O Software trigger Trigger by ADTRG Item Expanded analog input pin O Set-up Not used Either ANEX0 pin or ANEX1 pin External operation amplifier connection mode Resolution Analog input pin Trigger for starting A-D conversion Sample & Hold O Not activated Activated Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the ANEXi pin. (2) After the A-D conversion of voltage input to the ANEXi pin is completed, the content of the successive comparison register (conversion result) is transmitted to the A-D register. At the same time, the A-D conversion interrupt request bit goes to “1”. Also, the A-D conversion start flag goes to “0”, and the A-D converter stops operating. (1) Start A-D conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles φAD Set to “1” by software A-D conversion “1” start flag “0” A-D register i A-D conversion “1” interrupt request “0” (2) A-D convesion is complete Result Cleared to “0” when interrupt request is accepted, or cleared by software Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. Figure 2.7.9. Operation timing of one-shot mode, with expanded analog input pin selected 2-120 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting sample and hold b7 b0 1 A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 b7 b0 b7 b0 0 0 00 A-D control register 0 [Address 03D616] ADCON0 Analog input pin select bit (Note) b2 b1 b0 1 0 A-D control register 1 [Address 03D716] ADCON1 Invalid in one-shot mode A-D operation mode select bit 1 (Note) 0 (Must always be “0” in one-shot mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected External op-amp connection mode bit b7 b6 0 0 0 : AN0 is selected(ANEX0) 0 0 1 : AN1 is selected(ANEX1) One-shot mode is selected (Note) Trigger select bit 0 : Software trigger A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected Note: Rewrite to analog input pin select bit after changing A-D operation mode. 0 1 : ANEX0 input is A-D converted 1 0 : ANEX1 input is A-D converted Setting A-D conversion start flag b7 b0 1 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Start A-D conversion Stop A-D conversion Reading conversion result (b15) b7 (b8) b0 b7 b0 A-D register 0 A-D register 1 [Address 03C116, 03C016] [Address 03C316, 03C216] AD0 AD1 Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Figure 2.7.10. Set-up procedure of one-shot mode, with expanded analog input pin selected 2-121 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.5 Operation of A-D Converter (in one-shot mode, external op-amp connection mode selected) In one-shot mode, choose functions from those listed in Table 2.7.5. Operations of the circled items are described below. Figure 2.7.11 shows timing chart, and Figure 2.7.12 shows the set-up procedure. Table 2.7.5. Choosed functions Item Operation clock φAD Resolution Analog input pin Trigger for starting A-D conversion Set-up Divided-by-4 fAD / dividedO by-2 fAD / fAD O 8-bit / 10-bit O One of AN0 pin to AN7 pin O Software trigger Trigger by ADTRG Sample & Hold O O Item Expanded analog input pin Set-up Not used Either ANEX0 pin or ANEX1 pin External operation amplifier connection mode Not activated Activated Operation (1) Setting the A-D conversion start flag to “1” causes voltage input to the ANi pin to be output from the ANEX0 pin. The A-D conversion is carried out on voltage input to the ANEX1 pin (connect an operation amplifier between the ANEX0 pin and the ANEX1 pin). (2) After the A-D conversion is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register i corresponding to the ANi pin. At this time, the A-D conversion interrupt request bit goes to “1”. Example of wiring Example of operation (1) Start A-D conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (2) A-D conversion is complete Microcomputer Input voltage Input voltage φAD AN0 AN1 A-D conversion start flag “1” “0” Set to “1” by software Op-amp A-D register i Result ANEX0 ANEX1 A-D conversion “1” interrupt request “0” Cleared to “0” when interrupt request is accepted, or cleared by software Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. Figure 2.7.11. Operation timing of one-shot mode, with external op-amp connection mode selected 2-122 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting Sample and hold b7 b0 1 A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 b7 b0 b7 b0 0 0 00 A-D control register 0 [Address 03D616] ADCON0 Analog input pin select bit (Note) b2 b1 b0 1 1 1 0 A-D control register 1 [Address 03D716] ADCON1 Invalid in one-shot mode 0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected One-shot mode is selected (Note) Trigger select bit 0 : Software trigger A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected Note: Rewrite to analog input pin select bit after changing A-D operation mode. A-D operation mode select bit 1 (Note) 0 (Must always be “0” in one-shot mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected External op-amp connection mode bit b7 b6 1 1 : External op-amp connection mode Setting A-D conversion start flag b7 b0 1 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Start A-D conversion Stop A-D conversion Reading conversion result (b15) b7 (b8) b0 b7 b0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 [Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Figure 2.7.12. Set-up procedure of one-shot mode, with external op-amp connection mode selected 2-123 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.6 Operation of A-D Converter (in repeat mode) In repeat mode, choose functions from those listed in Table 2.7.6. Operations of the circled items are described below. Figure 2.7.13 shows timing chart, and Figure 2.7.14 shows the set-up procedure. Table 2.7.6. Choosed functions Item Operation clock φAD Resolution Analog input pin Trigger for starting A-D conversion O O O O Set-up Divided-by-4 fAD / dividedby-2 fAD / fAD 8-bit / 10-bit One of AN0 pin to AN7 pin Software trigger Trigger by ADTRG Sample & Hold O Item Expanded analog input pin O Set-up Not used Either ANEX0 pin or ANEX1 pin External operation amplifier connection mode Not activated Activated Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start operating. (2) After the first conversion is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register i. The A-D conversion interrupt request bit does not go to “1”. (3) The A-D converter continues operating until the A-D conversion start flag is set to “0” by software. The conversion result is transmitted to A-D register i every time a conversion is completed. (1) Start A-D conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (2) Conversion result is transferred to the A-D register (3) A-D conversion 8-bit resolution : 28 φAD cycles is complete 10-bit resolution : 33 φAD cycles φAD Set to “1” by software A-D conversion “1” start flag “0” Cleared to “0” by software A-D register i Result Result A-D conversion Stop Convert Convert Convert Stop Note: When φAD frequency is less than 1MHz, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. Figure 2.7.13. Operation timing of repeat mode 2-124 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting Sample and hold b7 b0 1 A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 b7 b0 b7 b0 0 0 0 1 A-D control register 0 [Address 03D616] ADCON0 Analog input pin select bit (Note) b2 b1 b0 00 1 0 A-D control register 1 [Address 03D716] ADCON1 Invalid in Repeat mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : AN0 is selected 1 : AN1 is selected 0 : AN2 is selected 1 : AN3 is selected 0 : AN4 is selected 1 : AN5 is selected 0 : AN6 is selected 1 : AN7 is selected A-D operation mode select bit 1 (Note) 0 (Must always be “0” in repeat mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected External op-amp connection mode bit b7 b6 Repeat mode is selected (Note) Trigger select bit 0 : Software trigger A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected 0 0 : ANEX0 and ANEX1 are not used Note: Rewrite to analog input pin select bit after changing A-D operation mode. Setting A-D conversion start flag b7 b0 1 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Repeatedly carries out A-D conversion on pins Start A-D conversion selected through the analog input pin select bit Transmitting conversion result to A-D register i (b15) b7 (b8) b0 b7 b0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 [Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Setting A-D conversion start flag b7 b0 0 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled Stop A-D conversion Figure 2.7.14. Set-up procedure of repeat mode 2-125 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.7 Operation of A-D Converter (in single sweep mode) In single sweep mode, choose functions from those listed in Table 2.7.7. Operations of the circled items are described below. Figure 2.7.15 shows timing chart, and Figure 2.7.16 shows the set-up procedure. Table 2.7.7. Choosed functions Item Operation clock AD Set-up O O Divided-by-4 fAD / dividedby-2 fAD / fAD 8-bit / 10-bit Item Trigger for starting AD conversion Expanded analog input pin O Set-up Software trigger Trigger by ADTRG O Not used External ope-amp connection mode Not activated O Activated Resolution Analog input pin O AN0 and AN1 (2 pins) / AN0 to AN3 (4 pins) / AN0 to AN5 (6 pins) / AN0 to AN7 (8 pins) Sample & Hold Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0 pin. (2) After the A-D conversion of voltage input to the AN0 pin is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register 0. The A-D converter converts all analog input pins selected by the user. The conversion result is transmitted to A-D register i corresponding to each pin, every time conversion on one pin is completed. (3) When the A-D conversion on all the analog input pins selected is completed, the A-D conversion interrupt request bit goes to “1”. At this time, the A-D conversion start flag goes to “0”. The A-D converter stops operating. (1) Start A-D conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (2) After A-D conversion on AN0 pin is complete, A-D converter begins converting all pins selected 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (3) A-D conversion is complete φAD Set to “1” by software A-D conversion “1” start flag “0” A-D register 0 Result A-D register 1 Result A-D register i A-D conversion “1” interrupt request “0” bit Result Cleared to “0” when interrupt request is accepted, or cleared by software Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. Figure 2.7.15. Operation timing of single sweep mode 2-126 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting Sample and hold b7 b0 1 A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 b7 b0 b7 b0 0 0 10 A-D control register 0 [Address 03D616] ADCON0 Invalid in single sweep mode 0 0 1 0 A-D control register 1 [Address 03D716] ADCON1 A-D sweep pin select bit (Note) b1 b0 Single sweep mode is selected (Note) Trigger select bit 0 : Software trigger A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) A-D operation mode select bit 1 (Note) 0 (Must always be “0” in Single sweep mode) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected External op-amp connection mode bit b7 b6 Note: Rewrite to analog input pin select bit after changing A-D operation mode. 0 0 : ANEX0 and ANEX1 are not used Setting A-D conversion start flag b7 b0 1 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Start A-D conversion Stop A-D conversion Reading conversion result (b15) b7 (b8) b0 b7 b0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 [Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Figure 2.7.16. Set-up procedure of single sweep mode 2-127 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.8 Operation of A-D Converter (in repeat sweep mode 0) In repeat sweep 0 mode, choose functions from those listed in Table 2.7.8. Operations of the circled items are described below. Figure 2.7.17 shows timing chart, and Figure 2.7.18 shows the set-up procedure. Table 2.7.8. Choosed functions Item Operation clock AD O O Set-up Divided-by-4 fAD / dividedby-2 fAD / fAD 8-bit / 10-bit Item Trigger for starting A-D conversion Expanded analog input pin O Set-up Software trigger Trigger by ADTRG O Not used External ope-amp connection mode Not activated O Activated Resolution Analog input pin O AN0 and AN1 (2 pins) / AN0 to AN3 (4 pins) / AN0 to AN5 (6 pins) / AN0 to AN7 (8 pins) Sample & Hold Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0 pin. (2) After the A-D conversion of voltage input to the AN0 pin is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register 0. (3) The A-D converter converts all pins selected by the user. The conversion result is transmitted to A-D register i corresponding to each pin every time A-D conversion on the pin is completed. The A-D conversion interrupt request bit does not go to “1”. (4) The A-D converter continues operating until the A-D conversion start flag is set to “0” by software. (1) Start A-D conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (2) AN1 conversion begins after AN0 conversion is complete 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (3) Consecutive conversion (4) A-D conversion is complete φAD Set to “1” by software. A-D conversion start flag A-D register 0 “1” “0” Result Cleared to “0” by software A-D register 1 Result A-D register i Result Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. Figure 2.7.17. Operation timing of repeat sweep 0 mode 2-128 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting Sample and hold b7 b0 1 A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 and A-D control register 1 b7 b0 b7 b0 0 0 1 1 A-D control register 0 [Address 03D616] ADCON0 Invalid in repeat sweep mode 0 Repeat sweep mode 0 is selected (Note) Trigger select bit 0 : Software trigger A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected 0 0 1 0 A-D control register 1 [Address 03D716] ADCON1 A-D sweep pin select bit (Note) b1 b0 0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) A-D operation mode select bit 1 (Note) 0 (Must always be “0” in repeat sweep mode 0) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected External op-amp connection mode bit b7 b6 Note: Rewrite to analog input pin select bit after changing A-D operation mode. 0 0 : ANEX0 and ANEX1 are not used Setting A-D conversion start flag b7 b0 1 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Repeatedly carries out A-D conversion on pins selected through the A-D sweep pin select bit. Start A-D conversion Transmitting conversion result to A-D register i (b15) b7 (b8) b0 b7 b0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 [Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Setting A-D conversion start flag b7 b0 0 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled Stop A-D conversion Figure 2.7.18. Set-up procedure of repeat sweep 0 mode 2-129 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.9 Operation of A-D Converter (in repeat sweep mode 1) In repeat sweep 1 mode, choose functions from those listed in Table 2.7.9. Operations of the circled items are described below. Figure 2.7.19 shows ANi pin's sweep sequence, Figure 2.7.20 shows timing chart, and Figure 2.7.21 shows the set-up procedure. Table 2.7.9. Choosed functions Item Operation clock φAD O O O Set-up Divided-by-4 fAD / dividedby-2 fAD / fAD 8-bit / 10-bit An0 (1 pin) / AN0 and AN1 (2 pins) / AN0 to AN2 (3 pins) / AN0 to AN3 (4 pins) Item Trigger for starting A-D conversion Expanded analog input pin O Set-up Software trigger Trigger by ADTRG O Not used External ope-amp connection mode Not activated O Activated Resolution Analog input pin Sample & Hold Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion on voltage input to the AN0 pin. (2) After the A-D conversion on voltage input to the AN0 pin is completed, the content of the successive comparison register (conversion result) is transmitted to A-D register 0. (3) Every time the A-D converter carries out A-D conversion on a selected analog input pin, the A-D converter carries out A-D conversion on only one unselected pin, and then the A-D converter carries out A-D conversion from the AN0 pin again. (See Figure 2.7.19.) The conversion result is transmitted to A-D register i every time conversion on a pin is completed. The A-D conversion interrupt request bit does not go to “1”. (4) The A-D converter continues operating until software goes the A-D conversion start flag to “0”. When AN0 is selected When AN0, AN1 are selected When AN0 to AN2 are selected When AN0 to AN3 are selected Converted analog input pin Converted analog input pin Converted analog input pin 0 1 0 0 0 0 0 0 0 1 0 2 3 4 5 6 7 2 0 . . . 0 1 2 0 1 0 1 0 1 0 1 0 1 0 1 2 0 . . . 0 1 2 3 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 0 . . . Converted analog input pin Time Time Time Time 0 1 2 3 4 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 4 0 . . . 3 4 5 6 7 4 5 6 7 5 6 7 Figure 2.7.19. ANi pin's sweep sequence in repeat sweep mode (2) Conversion result is transfered to A-D conversion register 0 (1) Start AN0 pin conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles φAD Set to “1” by software A-D conversion start flag A-D register 0 A-D register 1 A-D register 2 “1” “0” Result Result Result Cleared to “0” by software 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (3) Consecutive conversion 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles 8-bit resolution : 28 φAD cycles 10-bit resolution : 33 φAD cycles (4) A-D conversion is complete Result Note: When φAD frequency is less than 1MHz, sample and hold function cannot be selected. Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution. Figure 2.7.20. Operation timing of repeat sweep 1 mode 2-130 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Selecting Sample and hold b7 b0 1 A-D control register 2 [Address 03D416] ADCON2 A-D conversion method select bit 1 : With sample and hold Setting A-D control register 0 andA-D control register 1 b7 b0 b7 b0 00 1 1 A-D control register 0 [Address 03D616] ADCON0 Invalid in repeat sweep mode 1 Repeat sweep mode 1 is selected (Note) Trigger select bit 0 : Software trigger A-D conversion start flag 0 : A-D conversion disabled Frequency select bit 0 0 : fAD/4 is selected 1 : fAD/2 is selected 0 0 1 1 A-D control register 1 [Address 03D716] ADCON1 A-D sweep pin select bit (Note) b1 b0 0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) A-D operation mode select bit 1 (Note) 0 (Must always be “0” in repeat sweep mode 1) 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode Frequency select bit 1 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected Vref connect bit 1 : Vref connected External op-amp connection mode bit b7 b6 Note: Rewrite to analog input pin select bit after changing A-D operation mode. 0 0 : ANEX0 and ANEX1 are not used Setting A-D conversion start flag b7 b0 1 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 1 : A-D conversion started Converts non-selected pin after converting pins selected through the A-D sweep pin select bit. Start A-D conversion Transmitting conversion result to A-D register i (b15) b7 (b8) b0 b7 b0 A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7 [Address 03C116, 03C016] [Address 03C316, 03C216] [Address 03C516, 03C416] [Address 03C716, 03C616] [Address 03C916, 03C816] [Address 03CB16, 03CA16] [Address 03CD16, 03CC16] [Address 03CF16, 03CE16] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Eight low-order bits of A-D conversion result During 10-bit mode Two high-order bits of A-D conversion result During 8-bit mode When read, the content is indeterminate Setting A-D conversion start flag b7 b0 0 A-D control register 0 [Address 03D616] ADCON0 A-D conversion start flag 0 : A-D conversion disabled Stop A-D conversion Figure 2.7.21. Set-up procedure of repeat sweep 1 mode 2-131 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.10 Precautions for A-D Converter (1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from 0 to 1, start A-D conversion after an elapse of 1 µs or longer. (2) To reduce conversion error due to noise, connect a voltage to the AVcc pin and to the Vref pin from an independent source. It is recommended to connect a capacitor between the AVss pin and the AVcc pin, between the AVss pin and the Vref pin, and between the AVss pin and the analog input pin (ANi). Figure 2.7.22 shows the an example of connecting the capacitors to these pins. Microcomputer VCC AVCC VREF C1 C2 AVSS C3 Note 1: C1≥0.47 µF, C2≥0.47 µF, C3≥100 pF (for reference) Note 2: Use thick and shortest possible wiring to connect capacitors. ANi Figure 2.7.22. Use of capacitors to reduce noise (3) Set the direction register of the following ports to input: the port corresponding to a pin to be used as an analog input pin and external trigger input pin (P97). (4) In using a key-input interrupt, none of the 4 pins (AN4 through AN7) can be used as an A-D conversion port (if the A-D input voltage goes to “L” level, a key-input interrupt occurs). (5) If using the A-D converter with Vcc = 2.7V to 4.0 V: Use only a divided frequency for fAD (undivided fAD is not allowed). Select without the Sample & Hold feature. Select 8-bit mode. (6) Rewrite to analog input pin select bits after changing A-D operation mode. (7) When using the one-shot or single sweep mode Confirm that A-D conversion is complete before reading the A-D register. (Note: When A-D conversion interrupt request bit is set, it shows that A-D conversion is completed.) (8) When using the repeat mode or repeat sweep mode 0 or 1 Use the undivided main clock as the internal CPU clock. (9) Use AD under 10 MHz. When XIN is over 10 MHz, divide it. 2-132 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.11 Method of A-D Conversion (10-bit mode) (1) The A-D converter compares the reference voltage (Vref) generated internally based on the contents of the successive comparison register with the analog input voltage (VIN) input from the analog input pin. Each bit of the comparison result is stored in the successive comparison register until analog-to-digital conversion (successive comparison method) is complete. If a trigger occurs, the A-D converter carries out the following: 1. Fixes bit 9 of the successive comparison register. Compares Vref with VIN: [In this instance, the contents of the successive comparison register are “10000000002” (default).] Bit 9 of the successive comparison register varies depending on the comparison result as follows. If Vref < VIN, then “1” is assigned to bit 9. If Vref > VIN, then “0” is assigned to bit 9. 2. Fixes bit 8 of the successive comparison register. Sets bit 8 of the successive comparison register to “1”, then compares Vref with VIN. Bit 8 of the successive comparison register varies depending on the comparison result as follows: If Vref < VIN, then “1” is assigned to bit 8. If Vref > VIN, then “0” is assigned to bit 8. 3. Fixes bit 7 through bit 0 of the successive comparison register. Carries out step 2 above on bit 7 through bit 0. After bit 0 is fixed, the contents of the successive comparison register (conversion result) are transmitted to A-D register i. Vref is generated based on the latest content of the successive comparison register. Table 2.7.10 shows the relationship of the successive comparison register contents and Vref. Table 2.7.11 shows how the successive comparison register and Vref vary while A-D conversion is in progress. Figure 2.7.23 shows theoretical A-D conversion characteristics. Table 2.7.10. Relationship of the successive comparison register contents and Vref Successive approximation register : n 0 1 to1023 VREF 1024 x Vref (V) 0 n – VREF 2048 2-133 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 2.7.11. Variation of the successive comparison register and Vref while A-D conversion is in progress (10-bit mode) Successive approximation register b9 A-D converter stopped b0 Vref change VREF [V] 2 VREF VREF [V] – 2048 2 VREF VREF VREF [V] n9 = 0 – ± 2 2048 4 n9 = 1 1000000000 1000000000 n9 1 0 0 0 0 0 0 0 0 1st comparison result 1st comparison 2nd comparison 3rd comparison + n9 n8 1 0 0 0 0 0 0 0 2nd comparison result VREF ± VREF ± VREF – VREF [V] n8 = 0 2 4 8 2048 VREF 4 – VREF 4 + n8 = 1 – VREF 8 VREF 8 10th comparison Conversion complete n9 n8 n7 n6 n5 n4 n3 n2 n1 0 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 This data transfers to the bit 0 to bit 9 of A-D register i. VREF VREF VREF VREF VREF [V] ± ...... ± – ± ± 4 8 2 1024 2048 Result of A-D conversion Theoretical A-D conversion characteristic 3FF16 3FE16 00316 00216 00116 00016 0 VREF x 0.5 1024 VREF x 1 1024 VREF x 2 1024 VREF x 3 1024 Ideal A-D conversion characteristic VREF x 1021 VREF x 1022 VREF x 1023 1024 1024 1024 VREF Analog input voltage Figure 2.7.23. Theoretical A-D conversion characteristics (10-bit mode) 2-134 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.12 Method of A-D Conversion (8-bit mode) (1) In 8-bit mode, 8 higher-order bits of the 10-bit successive comparison register becomes A-D conversion result. Hence, if compared to a result obtained by using an 8-bit A-D converter, the voltage compared is different by 3 VREF/2048 (see what are underscored in Table 2.7.12), and differences in stepping points of output codes occur as shown in Figure 2.7.24. Table 2.7.12. The comparison voltage in 8-bit mode compared to 8-bit A-D converter 8-bit mode n=0 Comparison voltage Vref n = 1 to 255 VREF 28 xn 0 – VREF 210 x 0.5 VREF 28 x 8-bit A-D converter 0 n– VREF 28 x 0.5 Optimal conversion characteristics of 8-bit A-D converter (VREF = 5.12 V) Output code (Result of A-D conversion) 02 01 00 10 30 Analog input voltage (mV) Optimal conversion characteristics in 8-bit mode (VREF = 5.12 V) Output code (Result of A-D conversion) 8-bit mode 10-bit mode 09 08 07 06 05 04 03 02 01 00 (Note) 10bit-mode 02 01 00 8bit-mode 17.5 37.5 Analog input voltage (mV) Note: Differences in stepping points of output code for analog input voltage. Figure 2.7.24. The level conversion characteristics of 8-bit mode and 8-bit A-D converter 2-135 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 2.7.13. Variation of the successive comparison register and Vref while A-D conversion is in progress (8-bit mode) Successive approximation register b9 A-D converter stopped b0 Vref change VREF [V] 2 VREF VREF [V] – 2048 2 VREF VREF VREF [V] – ± 2 2048 4 n9 = 1 n9 = 0 1000000000 1000000000 n9 1 0 0 0 0 0 0 0 0 1st comparison result 1st comparison 2nd comparison 3rd comparison + n9 n8 1 0 0 0 0 0 0 0 2nd comparison result VREF VREF VREF VREF [V] – ± ± 4 8 2048 2 n8 = 0 VREF 4 VREF – 4 n8 = 1 + – VREF 8 VREF 8 8th comparison Conversion complete n9 n8 n7 n6 n5 n4 n3 1 0 0 n9 n8 n7 n 6 n 5 n 4 n 3 n 2 0 0 This data transfers to bit 0 to bit 7 of A-D register i. VREF VREF VREF VREF VREF [V] ± ± ± ...... ± – 2048 2 4 8 256 Result of A-D conversion Theoretical A-D conversion characteristic of general 8-bit A-D converter FF16 FE16 0316 0216 0116 0016 0 VREF x 3 2048 VREF x 1 256 Theoretical A-D conversion characteristic in the 8-bit mode VREF x 2 256 VREF x 3 256 VREF x 4 256 VREF x 254 256 VREF x 255 256 VREF Analog input voltage Figure 2.7.25. Theoretical A-D conversion characteristics (8-bit mode) 2-136 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.13 Absolute Accuracy and Differential Non-Linearity Error • Absolute accuracy Absolute accuracy is the difference between output code based on the theoretical A-D conversion characteristics, and actual A-D conversion result. When measuring absolute accuracy, the voltage at the middle point of the width of analog input voltage (1-LSB width), that can meet the expectation of outputting an equal code based on the theoretical A-D conversion characteristics, is used as an analog input voltage. For example, if 10-bit resolution is used and if VREF (reference voltage) = 5.12 V, then 1-LSB width becomes 5 mV, and 0 mV, 5 mV, 10 mV, 15 mV, 20 mV, ···· are used as analog input voltages. If analog input voltage is 25 mV, “absolute accuracy = ± 3LSB” refers to the fact that actual A-D conversion falls on a range from “00216” to ”00816” though an output code, “00516”, can be expected from the theoretical A-D conversion characteristics. Zero error and full-scale error are included in absolute accuracy. Also, all the output codes for analog input voltage between VREF and AVcc becomes “3FF16”. Output code (result of A-D conversion) 00B16 00A16 00916 00816 00716 00616 00516 00416 00316 00216 +3LSB Theoretical A-D conversion characteristic –3LSB 00116 00016 0 5 10 15 20 25 30 35 40 45 50 55 Analog input voltage (mV) Figure 2.7.26. Absolute accuracy (10-bit resolution) 2-137 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • Differential non-linearity error Differential non-linearity error refers to the difference between 1-LSB width based on the theoretical AD conversion characteristics (an analog input width that can meet the expectation of outputting an equal code) and an actually measured 1-LSB width (analog input voltage width that outputs an equal code). If 10-bit resolution is used and if VREF (reference voltage) = 5.12 V, “differential non-linearity error = ± 1LSB” refers to the fact that 1-LSB width actually measured falls on a range from 0 mV to 10 mV though 1-LSB width based on the theoretical A-D conversion characteristics is 5 mV. Output code (result of A-D conversion) 00916 00816 00716 00616 00516 00416 00316 00216 00116 Differential non-linear error 00016 0 5 10 15 20 25 30 35 40 45 1LSB width for theoretical A-D conversion characteristic Analog input voltage (mV) Figure 2.7.27. Differential non-linearity error (10-bit resolution) 2-138 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.14 Internal Equivalent Circuit of Analog Input Figure 2.7.28 shows the internal equivalent circuit of analog input. Vcc Vcc Vss Parasitic diode AVcc ON resistor approx. 2k Ω AN0 SW1 Wiring resistor approx. 0.2k Ω ON resistor approx. 0.6k Ω Analog input voltage C = Approx. 3.0pF AMP ON resistor, approx. 5k Ω Parasitic diode SW2 VIN Vss i ladder-type switches (i = 10) Sampling control signal SW4 SW3 i ladder-type wiring resistors (i = 10) AVss Chopper-type amplifier AN i SW1 A-D successive conversion register b2 b1 b0 A-D control register 0 Reference control signal Vref VREF Resistor ladder AVss SW2 Comparison voltage ON resistor approx. 0.6k Ω ADT/A-D conversion interrupt request Comparison reference voltage (Vref) generator Sampling Connect to Control signal for SW2 Comparison SW1 conducts only on the ports selected for analog input. SW2 and SW3 are open when A-D conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left. SW4 conducts only when A-D conversion is not in progress. Connect to Connect to Connect to Control signal for SW3 Warning: Use only as a standard for designing this data. Mass production may cause some changes in device characteristics. Figure 2.7.28. Internal equivalent circuit to analog input 2-139 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.7.15 Sensor’s Output Impedance under A-D Conversion To carry out A-D conversion properly, charging the internal capacitor C shown in Figure 2.7.29 has to be completed within a specified period of time. With T as the specified time, time T is the time that switches SW2 and SW3 are connected to O in Figure 2.7.28. Let output impedance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of the A-D converter be X, and the A-D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). Vc is generally VC = VIN {1 – e And when t = T, VC=VIN – T C (R0 + R) – t C (R0 + R) } X X VIN=VIN(1 – ) Y Y X Y X Y e – – = Hence, R0 = – T =ln C (R0 +R) T –R X C • ln Y With the model shown in Figure 2.7.29 as an example, when the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-(0.1/1024) VIN in time T. (0.1/1024) means that A-D precision drop due to insufficient capacitor charge is held to 0.1LSB at time of A-D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(XIN) = 10 MHz, T = 0.3 µs in the A-D conversion mode with sample & hold. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. T = 0.3 µs, R = 7.8 kΩ, C = 3 pF, X = 0.1, and Y = 1024 . Hence, 0.3 X 10-6 R0 = – 3.0 X 10 –12 • ln 0.1 –7.8 X103 3.0 X 103 1024 Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A-D converter turns out to be approximately 3.0 kΩ. Tables 2.7.14 and 2.7.15 show output impedance values based on the LSB values. Microprocessor's inside Sensor-equivalent circuit R0 VIN R (7.8k Ω) C (3.0pF) VC Figure 2.7.29 A circuit equivalent to the A-D conversion terminal 2-140 Mitsubishi microcomputers A-D Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Tables 2.7.14. Relation between output impedance and precision (error) of A-D converter (10-bit mode) Reference value f(Xin) (MHz) 10 Cycle (µs) Sampling time (µs) (kΩ) R 0.1 0.3 (3 x cycle, Sample & hold bit is enabled) 7.8 C (pF) 3.0 10 0.1 0.2 (2 x cycle, Sample & hold bit is disabled) 7.8 3.0 Resolution (LSB) 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 (kΩ) R0 3.0 4.5 5.3 5.9 6.4 6.8 7.2 7.5 7.8 8.1 0.4 0.9 1.3 1.7 2.0 2.2 2.4 2.6 2.8 Tables 2.7.15. Relation between output impedance and precision (error) of A-D converter (8-bit mode) Reference value f(Xin) (MHz) 10 Cycle (µs) Sampling time (µs) R (kΩ) 0.1 0.3 (3 x cycle, Sample & hold bit is enabled) 7.8 C (pF) 3.0 10 0.1 0.2 (2 x cycle, Sample & hold bit is disabled) 7.8 3.0 Resolution (LSB) 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 R0 (kΩ) 4.9 7.0 8.2 9.1 9.9 10.5 11.1 11.7 12.1 12.6 0.7 2.1 2.9 3.5 4.0 4.4 4.8 5.2 5.5 5.8 2-141 Mitsubishi microcomputers D-A Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.8 D-A Converter Usage 2.8.1 Overview of the D-A converter usage The D-A converter used in the M16C/62A group is based on the 8-bit R-2R technique. (1) Output voltage The D-A converter outputs voltage within a range from 0 V to VREF. The output voltage is determined by VREF/(256) X the D-A register contents. The D-A converter is not effected by the Vref connection bit of the A-D converter. (2) Conversion time tsu = 3 µs (3) Output from the D-A converter and the direction register To use the D-A converter, do not set the direction register of the relevant port to output. (4) Pins related to the D-A converter • DA0 pin, DA1 pin Output pins of the D-A converter • AVcc pin The power source pin of the analog section • VREF pin Input pin of the reference voltage • AVss pin The GND pin of the analog section (5) Registers related to the D-A converter Figure 2.8.1 shows the memory map of D-A converter-related registers, and Figure 2.8.2 shows D-A converter-related registers. (6) Note D-A output pins shared with P93 and P94. The two pins are input ports and floating at the reset. 03D816 03D916 03DA16 03DB16 03DC16 D-A control register (DACON) D-A register 1 (DA1) D-A register 0 (DA0) Figure 2.8.1. Memory map of D-A converter-related registers D-A control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DACON Bit symbol DA0E DA1E Address 03DC16 Bit name D-A0 output enable bit D-A1 output enable bit When reset 0016 Function 0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0” D-A register b7 b0 Symbol DAi (i = 0,1) Address 03D816, 03DA16 When reset Indeterminate Function Output value of D-A conversion RW RW Figure 2.8.2. D-A converter-related registers 2-142 Mitsubishi microcomputers D-A Converter M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.8.2 D-A Converter Operation The following is the D-A converter operation. Figure 2.8.3 shows the set-up procedure. Operation (1) Writing a value to the D-A register starts D-A conversion. (2) Setting the D-Ai output enable bit to “1” outputs an analog signal on the DAi pin. (3) The D-A converter continues outputting an analog signal until the D-A output enable bit is set to “0”. Setting D-A register b7 b0 D-A register 0 [Address 03D816] DA0 D-A register 1 [Address 03DA16] DA1 Output value of D-A conversion Setting D-A control register b7 b0 D-A Control register [Address 03DC16] DACON D-A0 output enable bit 1 : Output enabled D-A1 output enable bit 1 : Output enabled Figure 2.8.3. Set-up procedure of D-A converter 2-143 Mitsubishi microcomputers DMAC M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.9 DMAC Usage 2.9.1 Overview of the DMAC usage DMAC transfers one data item held in the source address to the destination address every time a transfer request is generated. The following is an overview of the DMAC usage. (1) Source address and destination address Both the register which indicates a source and the register which indicates a destination comprise of 24 bits, so that each can cover a 1M bytes space. After transfer of one bit of data is completed, the address in either the source register or the destination register can be incremented. However, both registers cannot be incremented. The links between the source and destination are as follows: (a) A fixed address from an arbitrary 1M bytes space (b) An arbitrary 1M bytes space from a fixed address (c) A fixed address from another fixed address (2) The number of bits of data transferred The number of bit of data indicated by the transfer counter is transferred. If a 16-bit transfer is selected, up to 128K bytes can be transferred. If an 8-bit transfer is selected, up to 64K bytes can be transferred. The transfer counter is decremented each time one bit of data is transferred, and a DMA interrupt request occurs when the transfer counter underflows. (3) DMA transfer factor ________ The DMA transfer factor can be selected from the following 25 factors: falling edge/two edges of INT0/ ________ INT1 pin, timer A0 interrupt request through timer A4 interrupt request, timer B0 interrupt request through timer B5 interrupt request, UART0 transmission interrupt request, UART0 reception interrupt request, UART1 transmission/UART1 reception interrupt request, UART2 transmission interrupt request, UART2 reception interrupt request, SI/O 3, 4 interrupt request, A-D conversion interrupt request, and software trigger. When software trigger is selected, DMA transfer is generated by writing “1” to software DMA interrupt request bit. When other factor is selected, DMA transfer is generated by generating corresponding interrupt request. (4) Channel priority If DMA0 transfer request and DMA1 transfer request occur simultaneously, priority is given to DMA0. (5) Writing to a register When writing to the source register or the destination register with DMA enabled, the content of the register with a fixed address will change at the time of writing. Therefore, the user should not write to a register with a fixed address when the DMA enable bit is set to “1”. The contents of the register with ‘forward direction’ selected, and the transfer counter, are changed when reloaded. A reload occurs either when the transfer counter underflows, or when the DMA enable bit is re-enabled, after having been disabled. The reload register can be written to, as in normal conditions. (6) Reading to a register The reload register can be read to, as in normal conditions. 2-144 Mitsubishi microcomputers DMAC M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (7) Switching function (a) Switching between one-shot transfer and repeated transfer 'One-shot transfer' refers to a mode in which DMA is disabled after the transfer counter underflows. 'Repeated transfer' refers to a mode in which a reload is carried out after the transfer counter underflows. The reload is carried out for the transfer counter and on the address pointer subjected to forward direction. The following are examples of operation in which the options listed are selected. • A fixed address from an arbitrary 1M byte space, one-shot transfer ..................................... P2-148 • An arbitrary 1M byte space from a fixed address, repeated transfer ..................................... P2-150 (8) Registers related to DMAC Figure 2.9.1 shows the memory map of DMAC-related registers, and Figures 2.9.2 and 2.9.3 show DMAC-related registers. 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002C15 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003C16 004B16 004C16 03B816 03B916 03BA16 DMA1 cause select register (DM1SL) DMA1 transfer counter (TCR1) DMA1 destination pointer (DAR1) DMA1 source pointer (SAR1) DMA0 control register (DM0CON) DMA0 transfer counter (TCR0) DMA0 destination pointer (DAR0) DMA0 source pointer (SAR0) DMA1 control register (DM1CON) DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) DMA0 cause select register (DM0SL) Figure 2.9.1. Memory map of DMAC-related registers 2-145 Mitsubishi microcomputers DMAC M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMA0 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL Address 03B816 When reset 0016 Bit symbol Bit name DMA request cause select bit b3 b2 b1 b0 Function 0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0) /two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0) Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0) Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit R W DSEL0 DSEL1 DSEL2 DSEL3 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMS DSR DMA request cause expansion select bit Software DMA request bit 0 : Normal 1 : Expanded cause If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) DMA1 request cause select register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM1SL Address 03BA16 When reset 0016 Bit symbol Bit name Function b3 b2 b1 b0 R W DSEL0 DMA request cause select bit DSEL1 DSEL2 DSEL3 0 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3(DMS=0) /serial I/O3 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0) /serial I/O4 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 receive Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMS DMA request cause expansion select bit 0 : Normal 1 : Expanded cause DSR Software DMA request bit If software trigger is selected, a DMA request is generated by setting this bit to “1” (When read, the value of this bit is always “0”) Figure 2.9.2. DMAC-related registers (1) 2-146 Mitsubishi microcomputers DMAC M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER DMAi control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMiCON(i=0,1) Address 002C16, 003C16 When reset 00000X002 Bit symbol DMBIT DMASL DMAS DMAE DSD DAD Bit name Transfer unit bit select bit Repeat transfer mode select bit DMA request bit (Note 1) DMA enable bit Source address direction select bit (Note 3) 0 : 16 bits 1 : 8 bits Function R W 0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward (Note 2) Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to “0”. Note 3: Source address direction select bit and destination address direction select bit cannot be set to “1” simultaneously. DMAi source pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 002216 to 002016 003216 to 003016 When reset Indeterminate Indeterminate Function • Source pointer Stores the source address Transfer address specification 0000016 to FFFFF16 RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMAi destination pointer (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol DAR0 DAR1 Address 002616 to 002416 003616 to 003416 When reset Indeterminate Indeterminate RW Function • Destination pointer Stores the destination address Transfer address specification 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. DMAi transfer counter (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol TCR0 TCR1 Address 002916, 002816 003916, 003816 When reset Indeterminate Indeterminate RW Function • Transfer counter Set a value one less than the transfer count Transfer count specification 000016 to FFFF16 Figure 2.9.3. DMAC-related registers (2) 2-147 Mitsubishi microcomputers DMAC M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.9.2 Operation of DMAC (one-shot transfer mode) In one-shot transfer mode, choose functions from the items shown in Table 2.9.1. Operations of the circled items are described below. Figure 2.9.4 shows an example of operation and Figure 2.9.5 shows the set-up procedure. Table 2.9.1. Choosed functions Item Transfer space O Set-up Fixed address from an arbitrary 1 M bytes space Arbitrary 1 M bytes space from a fixed address Fixed address from fixed address Unit of transfer O 8 bits 16 bits Operation (1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA transfer request signal. (2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi forward-direction address pointer are transferred to the address indicated by the DMAi destination pointer. When data transfer starts directly after DMAC becomes active, the value of the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer. Each time a DMA transfer request signal is generated, 1 byte of data is transferred. The DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up counted. (3) If the DMA transfer counter underflows, the DMA enable bit changes to “0” and DMA transfer is completed. The DMA interrupt request bit changes to “1” simultaneously. (1) Request signal for a DMA transfer occurs (2) Data transfer begins BCLK Destination Address bus CPU use Source Dummy cycle CPU use Source (3) Underflow Destination Dummy cycle CPU use RD signal WR signal Destination Data bus Write signal to software DMAi request bit DMAi request bit CPU use Source Dummy cycle CPU use Source Destination Dummy cycle CPU use DMA transfer counter Indeterminate 0116 0016 FF16 DMAi interrupt request bit DMAi enable bit Cleared to “0” when interrupt request is accepted, or cleared by software • In the case in which the number of transfer times is set to 2. Figure 2.9.4. Example of operation of one-shot transfer mode 2-148 Mitsubishi microcomputers DMAC M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting DMAi request cause select register b7 b0 0 0 0 0 1 DMAi request cause select register (i = 0, 1) [Address 03B816, 03BA16] DMiSL(i = 0, 1) DMA request cause select bit b3 b2 b1 b0 0 0 0 1 : Software trigger Software DMA request bit Set to “0” Setting DMAi control register b7 b0 01 00 0 1 DMAi control register (i = 0, 1) [Address 002C16, 003C16] DMiCON(i = 0, 1) Transfer unit bit select bit 1 : 8 bits Repeat transfer mode select bit 0 : Single transfer DMA request bit 0 : DMA not requested DMA enable bit 0 : Disabled Source address direction select bit 1 : Forward (Bit 4 and bit 5 cannot be set to “1” simultaneously) Destination address direction select bit 0 : Fixed (Bit 4 and bit 5 cannot be set to “1” simultaneously) Setting DMAi source pointer (b23) b7 (b19) b3 (b16)(b15) b0 b7 DMA0 source pointer [Address 002216 to 002016] SAR0 DMA1 source pointer [Address 003216 to 003016] SAR1 (b8) b0 b7 b0 Source pointer Stores the source address Setting DMAi destination pointer (b23) b7 (b19) b3 (b16)(b15) b0 b7 DMA0 destination pointer [Address 002616 to 002416] DAR0 DMA1 destination pointer [Address 003616 to 003416] DAR1 (b8) b0 b7 b0 Destination pointer Stores the destination address Setting DMAi transfer counter (b15) b0 (b8) b0 b7 b0 DMA0 transfer counter [Address 002916, 002816] TCR0 DMA1 transfer counter [Address 003916, 003816] TCR1 Transfer counter Set a value one less than the transfer count Setting DMAi control register b7 b0 1 DMAi control register (i = 0, 1) [Address 002C16, 003C16] DMiCON(i = 0, 1) DMA enable bit 1 : Enabled Note: Clear DMA request bit simultaneously again. When software DMA request bit = “1” Start DMA transmission Figure 2.9.5. Set-up procedure of one-shot transfer mode 2-149 Mitsubishi microcomputers DMAC M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.9.3 Operation of DMAC (repeated transfer mode) In repeat transfer mode, choose functions from the items shown in Table 2.9.2. Operations of the circled items are described below. Figure 2.9.6 shows an example of operation and Figure 2.9.7 shows the setup procedure. Table 2.9.2. Choosed functions Item Transfer space O Set-up Fixed address from an arbitrary 1 M bytes space Arbitrary 1 M bytes space from a fixed address Fixed address from fixed address Unit of transfer O 8 bits 16 bits Operation (1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA transfer request signal. (2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi forward-direction address pointer are transferred to the address indicated by the DMAi destination pointer. When data transfer starts directly after DMAC becomes active, the value of the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer. Each time a DMA transfer request signal is generated, 2 byte of data is transferred. The DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up counted. (3) Though DMAi transfer counter is underflowed, DMA enable bit is still “1”. The DMA interrupt request bit changes to “1” simultaneously. (4) After DMAi transfer counter is underflowed, when the next DMA request is generated, DMA transfer is repeated from (1). (1) Request signal for a DMA transfer occurs (2) Data transfer begins BCLK (3) Underflow Destination Address bus Dummy cycle Destination CPU use Dummy cycle CPU use Destination Source Dummy cycle CPU use CPU use Source Source RD signal WR signal Destination Data bus Dummy cycle CPU use Destination Source Dummy cycle CPU use Destination Source Dummy cycle CPU use CPU use Source Write signal to software DMAi request bit DMAi request bit 0116 DMA transfer counter 0116 0016 Indeterminate FF16 0016 DMAi interrupt request bit Cleared to “0” when interrupt request is accepted, or cleared by software “1” DMAi enable bit • In the case in which the number of transfer times is set to 2. Figure 2.9.6. Example of operation of repeated transfer mode 2-150 Mitsubishi microcomputers DMAC M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting DMAi request cause select register b7 b0 0 0 0 0 1 DMAi request cause select register (i = 0, 1) [Address 03B816, 03BA16] DMiSL(i = 0, 1) DMA request cause select bit b3 b2 b1 b0 0 0 0 1 : Software trigger Software DMA request bit Set to “0” Setting DMAi control register b7 b0 10 0 0 10 DMAi control register (i = 0, 1) [Address 002C16, 003C16] DMiCON(i = 0, 1) Transfer unit bit select bit 0 : 16 bits Repeat transfer mode select bit 1 : Repeat transfer DMA request bit 0 : DMA not requested DMA enable bit 0 : Disabled Source address direction select bit 0 : Fixed (Bit 4 and bit 5 cannot be set to “1” simultaneously) Destination address direction select bit 1 : Forward (Bit 4 and bit 5 cannot be set to “1” simultaneously) Setting DMAi source pointer (b23) b7 (b19) b3 (b16) (b15) b0 b7 DMA0 source pointer [Address 002216 to 002016] SAR0 DMA1 source pointer [Address 003216 to 003016] SAR1 (b8) b0 b7 b0 Source pointer Stores the source address Setting DMAi destination pointer (b23) b7 (b19) b3 (b16) (b15) b0 b7 DMA0 destination pointer [Address 002616 to 002416] DAR0 DMA1 destination pointer [Address 003616 to 003416] DAR1 (b8) b0 b7 b0 Destination pointer Stores the destination address Setting DMAi transfer counter (b15) b0 (b8) b0 b7 b0 DMA0 transfer counter [Address 002916, 002816] TCR0 DMA1 transfer counter [Address 003916, 003816] TCR1 Transfer counter Set a value one less than the transfer count Setting DMAi control register b7 b0 1 DMAi control register (i = 0, 1) [Address 002C16, 003C16] DMiCON(i = 0, 1) DMA enable bit 1 : Enabled Note: Clear DMA request bit simultaneously again. When software DMA request bit = “1” Start DMA transmission Figure 2.9.7. Set-up procedure of repeated transfer mode 2-151 Mitsubishi microcomputers CRC Calculation Circuit M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.10 CRC Calculation Circuit Usage 2.10.1 Overview of the CRC calculation circuit usage Cyclic Redundancy Check (CRC) is a method that compares CRC code formed from transmission data by use of a polynomial generation with CRC check data so as to detect errors in transmission data. Using the CRC calculation circuit allows generation of CRC code. A polynomial counter is used for the polynomial generation of CRC_CCITT (X16 + X12 + X5 + 1). (1) Registers related to CRC calculation circuit Figure 2.10.1 shows the memory map of CRC-related registers, and Figure 2.10.2 shows CRC- related registers. 03BC16 03BD16 03BE16 CRC data register (CRCD) CRC input register (CRCIN) Figure 2.10.1. Memory map of CRC-related registers CRC data register (b15) b7 (b8) b0 b7 b0 Symbol CRCD Address 03BD16, 03BC16 When reset Indeterminate Values that can be set 000016 to FFFF16 Function CRC calculation result output register RW CRC input register b7 b0 Symbo CRCIN Function Data input register Address 03BE16 When reset Indeterminate Values that can be set 0016 to FF16 RW Figure 2.10.2. CRC-related registers 2-152 Mitsubishi microcomputers CRC Calculation Circuit M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.10.2 Operation of CRC Calculation Circuit The following describes the operation of the CRC calculation. Figure 2.10.3 shows an example of calculation data 012316 using the CRC calculation circuit. Operation (1) The CRC calculation circuit sets an initial value in the CRC data register. (2) Writing 1 byte data to the CRC input register generates CRC code based on the data register. CRC code generation for 1 byte data finishes in two machine cycles. (3) The CRC calculation circuit detects an error by means of comparing the CRC-checking data with the content of the CRC data register, after the next data is written to the CRC input register. (4) The content of CRC data register after all data is written becomes CRC code. b15 b0 (1) Setting 000016 CRC data register CRCD [03BD16, 03BC16] b7 b0 (2) Setting 0116 CRC input register CRCIN [03BE16] 2 cycles After CRC calculation is complete b15 b0 118916 CRC data register CRCD [03BD16, 03BC16] Stores CRC code The code resulting from sending 0116 in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial, (X16 + X12 + X5 + 1), becomes the remainder resulting from dividing (1000 0000) X16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. LSB 1000 1000 1 0001 0000 0010 0001 1000 0000 0000 1000 1000 0001 1000 0001 1000 1000 1001 LSB 8 1 0000 0000 0000 0001 0001 1 0000 1 1000 0000 1000 0000 0 1 1000 MSB MSB Modulo-2 operation is operation that complies with the law given below. 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1 9 Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000) corresponds to 118916 in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC operation. Also switch between the MSB and LSB of the result as stored in CRC data. b7 b0 (3) Setting 2316 CRC input register CRCIN [03BE16] After CRC calculation is complete b15 b0 0A4116 CRC data register CRCD [03BD16, 03BC16] Stores CRC code Figure 2.10.3. Calculation example using the CRC calculation circuit 2-153 Mitsubishi microcomputers Watchdog Timer M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.11 Watchdog Timer Usage 2.11.1 Overview of the watchdog timer usage The watchdog timer can detect a runaway program using its 15-bit timer prescaler. The following is an overview of the watchdog timer usage. (1) Watchdog timer start procedure When reset, the watchdog timer is in stopped state. Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start performing a down count. The watchdog timer, once started operating, cannot be stopped by any means other than stopping conditions. (2) Watchdog timer stop conditions The watchdog timer stops in any one of the following states: (a) Period in which the CPU is in stopped state (b) Period in which the CPU is in waiting state (c) Period in which the microcomputer is in hold state (3) Watchdog timer initialization The watchdog timer is initialized to 7FFF16 in the cases given below, and begins a down count. (a) When the watchdog timer writes to the watchdog timer start register while a count is in progress (b) When the watchdog timer underflows (4) Runaway detection When the watchdog timer underflows, a watchdog timer interrupt occurs. In writing a program, write to the watchdog timer start register before the watchdog timer underflows. The watchdog timer interrupt occurs regardless of the status of the interrupt enable flag (I flag). In processing a watchdog timer interrupt, set the software reset bit to “1” to reset software. (5) Watchdog timer cycle The watchdog timer cycle varies depending on the BCLK and the frequency division ratio of the prescaler selected. Table 2.11.1. The watchdog timer cycle CM07 0 0 CM06 0 0 CM17 0 0 CM16 0 1 BCLK 16MHz 8MHz WDC7 0 1 0 1 0 1 0 1 0 1 1 Invalid Invalid Invalid Invalid Invalid 2MHz 32kHz 0 1 Invalid Period Approx. 32.8ms (Note) Approx. 262.1ms (Note) Approx. 65.5ms (Note) Approx. 524.3ms (Note) Approx. 131.1ms (Note) Approx. 1.049s (Note) Approx. 524.3ms (Note) Approx. 4.194s (Note) Approx. 262.1ms (Note) Approx. 2.097s (Note) Approx. 2s (Note) 0 0 0 0 1 1 0 1 4MHz 1MHz Note: An error due to the prescaler occurs. 2-154 Mitsubishi microcomputers Watchdog Timer M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (6) Registers related to the watchdog timer Figure 2.11.1 shows the memory map of watchdog timer-related registers, and Figure 2.11.2 shows watchdog timer-related registers. 000E16 000F16 Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Figure 2.11.1. Memory map of watchdog timer-related registers Watchdog timer control register b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol WDC Bit symbol Address 000F16 Bit name When reset 000XXXXX2 Function RW High-order bit of watchdog timer Reserved bit Reserved bit WDC7 Must always be set to “0” Must always be set to “0” Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Watchdog timer start register b7 b0 Symbol WDTS Address 000E16 When reset Indeterminate RW Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of whatever value is written. Figure 2.11.2. Watchdog timer-related registers 2-155 Mitsubishi microcomputers Watchdog Timer M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.11.2 Operation of Watchdog Timer The following is an operation of the watchdog timer. Figure 2.11.3 shows the operation timing, and Figure 2.11.4 shows the set-up procedure. Operation (1) Writing to the watchdog timer start register initializes the watchdog timer to 7FFF16 and causes it to start a down count. (2) With a count in progress, writing to the watchdog timer start register again initializes the watchdog timer to 7FFF16 and causes it to resume counting. (3) Either executing the WAIT instruction or going to the stopped state causes the watchdog timer to hold the count in progress and to stop counting. The watchdog timer resumes counting after returning from the execution of the WAIT instruction or from the stopped state. (4) If the watchdog timer underflows, it is initialized to 7FFF16 and continues counting. At this time, a watchdog timer interrupt occurs. (1) Start count (3) In stopped state, or WAIT instruction is executing, etc (2) Write operation (4) Generate watchdog timer interrupt 7FFF16 000016 Write signal to the “H” watchdog timer start register “L” Figure 2.11.3. Operation timing of watchdog timer 2-156 Mitsubishi microcomputers Watchdog Timer M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting watchdog timer control register b7 b0 00 Watchdog timer control register [Address 000F16] WDC Reserved bit Must always be set to “0” Prescaler select bit 0 : Divided by 16 1 : Divided by 128 Setting watchdog timer start register b7 b0 Watchdog timer start register [Address 000E16] WDTS The watchdog timer is initialized and starts counting with a write instruction to this register. The watchdog timer value is always initialized to “7FFF16” regardless of the value written. Generating watchdog timer interrupt Clearing the protect b7 b0 1 Protect register [Address 000A16] PRCR Enables writing to processor mode registers 0 and 1 (addresses 000416 and 000516) 1 : Write-enabled Software reset b7 b0 1 Processor mode register 0 [Address 000416] PM0 Software reset bit The device is reset when this bit is set to “1”. The value of this bit is “0” when read. Figure 2.11.4. Set-up procedure of watchdog timer 2-157 Mitsubishi microcomputers Address Match Interrupt M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.12 Address Match Interrupt Usage 2.12.1 Overview of the address match interrupt usage The address match interrupt is used for correcting a ROM or for a simplified debugging-purpose monitor. The following is an overview of the address match interrupt usage. (1) Enabling/disabling the address match interrupt The address match interrupt enable bit can be used to enable and disable an address match interrupt. It is affected neither by the processor interrupt priority level (IPL) nor the interrupt enable flag (I flag). (2) Timing of the address match interrupt An interrupt occurs immediately before executing the instruction in the address indicated by the address match interrupt register. Set the first address of the instruction in the address match interrupt register. Setting a half address of an instruction or an address of tabulated data does not generate an address match interrupt. The first instruction of an interrupt routine does not generate an address match interrupt either. (3) Returning from an address match interrupt The address put in the stack when an address match interrupt occurs depends on the instruction not yet executed (the instruction the address match interrupt register indicates). The return address is not put in the stack. For this reason, to return from an address match interrupt, either rewrite the content of the stack and use the REIT instruction or use the POP instruction to restore the stack to the state as it was before the interrupt occurred and return by use of a jump instruction. Figure 2.12.1 shows unexecuted instructions and corresponding the stacked addresses. • 16-bit operation code instructions • 8-bit operation code instructions given below ADD.B:S OR.B:S STNZ.B:S CMP.B:S JMPS MOV.B:S #IMM8,dest #IMM8,dest #IMM8,dest #IMM8,dest #IMM8 SUB.B:S MOV.B:S STZX.B:S PUSHM JSRS #IMM8,dest #IMM8,dest src #IMM8 AND.B:S STZ.B:S POPM #IMM8,dest #IMM8,dest dest #IMM81,#IMM82,dest #IMM,dest (However, dest = A0/A1) • Instructions other than those listed above Figure 2.12.1. Unexecuted instructions and corresponding stacked addresses (4) How to determine an address match interrupt Address match interrupts can be set at two different locations. However, both location will have the same vector address. Therefore, it is necessary to determine which interrupt has occurred; address match interrupt 0 or address match interrupt 1. Using the content of the stack, etc., determine which interrupt has occurred according to the first part of the address match interrupt routine. 2-158 Mitsubishi microcomputers Address Match Interrupt M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (5) Registers related to the address match interrupt Figure 2.12.2 shows the memory map of address match interrupt-related registers, and Figure 2.12.3 shows address match interrupt-related registers. 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 Address match interrupt enable register (AIER) Address match interrupt register 0 (RMAD0) Address match interrupt register 1 (RMAD1) Figure 2.12.2. Memory map of address match interrupt-related registers Address match interrupt enable register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit symbol Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW AIER0 AIER1 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. Address match interrupt register i (i = 0, 1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol RMAD0 RMAD1 Address 001216 to 001016 001616 to 001416 When reset X0000016 X0000016 Function Address setting register for address match interrupt Values that can be set R W 0000016 to FFFFF16 Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminated. Figure 2.12.3. Address match interrupt-related registers 2-159 Mitsubishi microcomputers Address Match Interrupt M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.12.2 Operation of Address Match Interrupt The following is an operation of address match interrupt. Figure 2.12.4 shows the set-up procedure of address match interrupt, and Figure 2.12.5 shows the overview of the address match interrupt handling routine. Operation (1) The address match interrupt handling routine sets an address to be used to cause the address match interrupt register to generate an interrupt. (2) Setting the address match enable flag to “1” enables an interrupt to occur. (3) An address match interrupt occurs immediately before the instruction in the address indicated by the address match interrupt register as a program is executed. Setting address match interrupt register Address match interrupt register 0 [Address 001216 to 001016] RMAD0 Address match interrupt register 1 [Address 001616 to 001416] RMAD1 (b23) b7 (b20) (b19) b4 b3 (b16) (b15) b0 b7 (b8) b0 b7 b0 Can be set to “0000016” to “FFFFF16” Setting address match interrupt enable register b7 b0 Address match interrupt enable register [Address 000916] AIER Address match interrupt 0 enable bit 1: Interrupt enabled Address match interrupt 1 enable bit 1: Interrupt enabled Figure 2.12.4. Set-up procedure of address match interrupt 2-160 Mitsubishi microcomputers Address Match Interrupt M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address match interrupt routine [1] Storing registers [2] Determining the interrupt address No No Address match 0? Yes Address match 0 program Address match 1? Yes Address match 1 program [3] Rewriting the stack Restoring registers REIT Handling an error Explanation: [1] Storing the contents of the registers holding the main program status to be kept. [2] Determining the interrupt address Determining which factor generated the interrupt. [3] Rewriting the stack Rewriting the return address. Figure 2.12.5. Overview of the address match interrupt handling routine 2-161 Mitsubishi microcomputers Key-Input Interrupt M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.13 Key-Input Interrupt Usage 2.13.1 Overview of the key-input interrupt usage Key-input interrupt occurs when a falling edge is input to P104 through P107. The following is an overview of the key-input interrupt usage: (1) Enabling/disabling the key-input interrupt The key-input interrupt can be enabled and disabled using the key-input interrupt register. The keyinput interrupt is affected by the interrupt priority level (IPL) and the interrupt enable flag (I flag). (2) Occurrence timing of the key-input interrupt With key-input interrupt acceptance enabled, pins P104 through P107, which are set to input, become _____ _____ key-input interrupt pins (KI0 through KI3). A key-input interrupt occurs when a falling edge is input to a key-input interrupt pin. At this moment, the level of other key-input interrupt pins must be “H”. No interrupt occurs when the level of other key-input interrupt pins is “L”. (3) How to determine a key-input interrupt A key-input interrupt occurs when a falling edge is input to one of four pins, but each pin has the same vector address. Therefore, read the input level of pins P104 through P107 in the key-input interrupt routine to determine the interrupted pin. (4) Registers related to the key-input interrupt Figure 2.13.1 shows the memory map of key-input interrupt-related registers, and Figure 2.13.2 shows key-input interrupt-related registers. 004D16 Key input interrupt control register(KUPIC) 03F616 Port P10 direction register (PD10) 03FE16 Pull-up control register 2 (PUR2) Figure 2.13.1. Memory map of key-input interrupt-related registers 2-162 Mitsubishi microcomputers Key-Input Interrupt M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt control register (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol KUPIC Address 004D16 When reset XXXX00002 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 R W ILVL1 ILVL2 IR Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested (Note1) Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts. Port P10 direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD10 Address 03F616 When reset 0016 Bit symbol PD10_0 PD10_1 PD10_2 PD10_3 PD10_4 PD10_5 PD10_6 PD10_7 Bit symbol Bit symbol R W Port P100 direction register Port P101 direction register 0 : Imput mode (Functions as an input port) Port P102 direction register 1 : Output mode Port P103 direction register (Functions as an output port) Port P104 direction register Port P105 direction register Port P106 direction register Port P107 direction register Pull-up control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR2 Bit symbol PU20 PU21 PU22 PU23 PU24 PU25 Address 03FE16 Bit name P80 to P83 pull-up P84 to P87 pull-up (Except P85) P90 to P93 pull-up P94 to P97 pull-up P100 to P103 pull-up P104 to P107 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Figure 2.13.2. key-input interrupt-related registers 2-163 Mitsubishi microcomputers Key-Input Interrupt M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.13.2 Operation of Key-Input Interrupt The following is an operation of key-input interrupt. Figure 2.13.3 shows an example of a circuit that uses the key-input interrupt, Figure 2.13.4 shows an example of operation of key-input interrupt, and Figure 2.13.5 shows the setting procedure of key-input interrupt. Operation (1) Set the direction register of the ports to be changed to key-input interrupt pins to input, and set the pull-up function. (2) Setting the key-input interrupt control register and setting the interrupt enable flag makes the interrupt-enabled state ready. _____ _____ (3) If a falling edge is input to either KI0 through KI3, the key-input interrupt request bit goes to “1”. P100 P101 P102 P103 VREF I/O port P104 / KI0 P105 / KI1 P106 / KI2 P107 / KI3 Figure 2.13.3. Example of circuit using the key-input interrupt (1) Enter to stop mode (2) Cancel stop mode (3) Key scan (4) Enter to stop mode Key matrix scan P100 output P101 output P102 output P103 output P104 to P107 input Key input Key input interrupt processing Key OFF Key ON Key OFF Key ON Figure 2.13.4. Example of operation of key-input interrupt 2-164 Mitsubishi microcomputers Key-Input Interrupt M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting port P10 direction register b7 b0 Port P10 direction register [Address 03F616] PD10 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Setting pull-up control register 2 b7 b0 1 Pull-up control register 2 [Address 03FE16] PUR2 P104 to P107 1 : Pulled high Setting interrupt control register b7 b0 0 Key input interrupt control register [Address 004D16] KUPIC Interrupt priority level select bit b2 b1 b0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : Level 0 (interrupt disabled) 1 : Level 1 0 : Level 2 1 : Level 3 0 : Level 4 1 : Level 5 0 : Level 6 1 : Level 7 Interrupt request bit 0 : Interrupt not requested Figure 2.13.5. Set-up procedure of key-input interrupt 2-165 Mitsubishi microcomputers Multiple Interrupts M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.14 Multiple interrupts Usage 2.14.1 Overview of the Multiple interrupts usage The following is an overview of the multiple interrupts usage. (1) Interrupt control Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level select bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 2.14.1 shows the memory map of the interrupt control registers, and Figure 2.14.2 shows the interrupt control registers. 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 INT3 interrupt control register (INT3IC) Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) SI/O4 interrupt control register (S4IC) INT5 interrupt control register (INT5IC) SI/O3 interrupt control register (S4IC) INT4 interrupt control register (INT4IC) Bus collision detection interrupt control register (BCNIC) DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) Key input interrupt control register(KUPIC) A-D conversion interrupt control register (ADIC) UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control regster(S1TIC) UART1 receive interrupt control register(S1RIC) Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) Timer A4 interrupt control register (TA4IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) INT2 interrupt control register (INT2IC) Figure 2.14.1. Memory map of the interrupt control registers 2-166 Mitsubishi microcomputers Multiple Interrupts M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt control register (Note 2) Symbol TBiIC(i=3 to 5) BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 2) Address 004516 to 004716 004A16 004B16, 004C16 004D16 004E16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005916 005A16 to 005C16 When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 b7 b6 b5 b4 b3 b2 b1 b0 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 R W ILVL1 ILVL2 IR Interrupt request bit 0 : Interrupt not requested 1 : Interrupt requested (Note 1) Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address INTiIC(i=3) 004416 SiIC/INTjIC (i=4, 3) 004816, 004916 (j=5, 4) 004816, 004916 INTiIC(i=0 to 2) 005D16 to 005F16 When reset XX00X0002 XX00X0002 XX00X0002 XX00X0002 Bit symbol ILVL0 Bit name Interrupt priority level select bit b2 b1 b0 Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Must always be set to “0” R W ILVL1 ILVL2 IR Interrupt request bit (Note 1) POL Polarity select bit Reserved bit Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate. Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. For details, see the precautions for interrupts. Figure 2.14.2. Interrupt control registers 2-167 Mitsubishi microcomputers Multiple Interrupts M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) Interrupt Enable Flag (I flag) The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset. The content is changed when the I flag is changed causes the acceptance of the interrupt request in the following timing: • When changing the I flag using the REIT instruction, the acceptance of the interrupt takes effect as the REIT instruction is executed. • When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the acceptance of the interrupt is effective as the next instruction is executed. When changed by REIT instruction Interrupt request generated Determination whether or not to accept interrupt request Time Previous instruction REIT Interrupt sequence (If I flag is changed from 0 to 1 by REIT instruction) When changed by FCLR, FSET, POPC, or LDC instruction Interrupt request generated Determination whether or not to accept interrupt request Time Previous instruction FSET I Next instruction Interrupt sequence (If I flag is changed from 0 to 1 by FSET instruction) Figure 2.14.3. The timing of reflecting the change in the I flag to the interrupt (3) Interrupt Request Bit The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1"). (4) Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL) Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 2.14.1 shows the settings of interrupt priority levels and Table 2.14.2 shows the interrupt levels enabled, according to the contents of the IPL. The following are conditions under which an interrupt is accepted: · interrupt enable flag (I flag) = 1 · interrupt request bit = 1 · interrupt priority level > IPL 2-168 Mitsubishi microcomputers Multiple Interrupts M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another. Table 2.14.1. Settings of interrupt priority levels Table 2.14.2. Interrupt levels enabled according to the contents of the IPL IPL IPL2 IPL1 IPL0 Interrupt priority level select bit b2 b1 b0 Interrupt priority level Priority order Enabled interrupt priority levels 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Low 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt in the following timing: • When changing the IPL using the REIT instruction, the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction. • When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the instruction used. • When changing the interrupt priority level using the MOV or similar instruction, the reflection takes effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in the instruction used. (5) Interrupt Priority If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 2.14.4 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine. _______ ________ Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match Figure 2.14.4. Hardware interrupts priorities 2-169 Mitsubishi microcomputers Multiple Interrupts M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (6) Interrupt resolution circuit When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure 2.14.5 shows the circuit that judges the interrupt priority level. Priority level of each interrupt Level 0 (initial value) INT1 Timer B2 Timer B0 Timer A3 Timer A1 Timer B4 INT3 High INT2 INT0 Timer B1 Timer A4 Timer A2 Timer B3 Timer B5 UART1 reception UART0 reception UART2 reception/ACK A-D conversion DMA1 Bus collision detection Serial I/O4/INT5 Priority of peripheral I/O interrupts (if priority levels are same) Timer A0 UART1 transmission UART0 transmission UART2 transmission/NACK Key input interrupt DMA0 Serial I/O3/INT4 Processor interrupt priority level (IPL) Low Interrupt request level judgment output to clock generating circuit (Fig.1.10.3) Interrupt enable flag (I flag) Address match Interrupt request accepted Watchdog timer DBC NMI Reset Figure 2.14.5. Interrupts resolution circuit 2-170 Mitsubishi microcomputers Multiple Interrupts M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.14.2 Multiple Interrupts Operation The state when control branched to an interrupt routine is described below: · The interrupt enable flag (I flag) is set to “0” (the interrupt is disabled). · The interrupt request bit of the accepted interrupt is set to “0”. · The processor interrupt priority level (IPL) is assigned to the same interrupt priority level as as signed to the accepted interrupt. Setting the interrupt enable flag (I flag) to “1” within an interrupt routine allows an interrupt request assigned a priority higher than the IPL to be accepted. An interrupt request that is not accepted because of low priority will be held. If the condition following is met when the REIT instruction returns the IPL and the interrupt priority is determined, then the interrupt request being held is accepted. Interrupt priority level of the interrupt request being held > Returned the IPL Figure 2.14.6 shows the example of the multiple interrupts operation. 2-171 Mitsubishi microcomputers Multiple Interrupts M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Interrupt request generated Nesting Main routine I=0 IPL = 0 Time Reset Interrupt 1 I=1 Interrupt priority level = 3 Interrupt 1 I=0 IPL = 3 I=1 Interrupt 2 Interrupt priority level = 5 Multiple interrupts Interrupt 2 I=0 IPL = 5 Interrupt 3 REIT Interrupt priority level = 2 I=1 IPL = 3 Interrupt 3 REIT I=1 Not acknowledged because of low interrupt priority IPL = 0 Main routine instructions are not executed. Interrupt 3 I=0 IPL = 2 REIT I=1 IPL = 0 I : Interrupt enable flag IPL : Processor interrupt priority level : Automatically executed. : Be sure to set in software. Figure 2.14.6. Example of the multiple interrupts operation 2-172 Mitsubishi microcomputers Power Control M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.15 Power Control Usage 2.15.1 Overview of the power control usage ‘Power Control’ refers to the reduction of CPU power consumption by stopping the CPU and oscillators, or decreasing the operation clock. The following is a description of the three available power control modes: (1) Modes Power control is available in three modes. (a) Normal operation mode • High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK selected. Each peripheral function operates according to its assigned clock. • Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the BCLK selected. Each peripheral function operates according to its assigned clock. • Low-speed mode fC becomes the BCLK. The CPU operates according to the fc clock. The fC clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock. • Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 2.15.1 is the state transition diagram of the above modes. (2) Switching the driving capacity of the oscillation circuit Both the main clock and the secondary clock have the ability to switch the driving capacity. Reducing the driving capacity after the oscillation stabilizes allows for further reduction in power consumption. 2-173 Mitsubishi microcomputers Power Control M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Transition of stop mode, wait mode Reset All oscillators stopped WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction Interrupt CPU operation stopped Stop mode All oscillators stopped CM10 = “1” Interrupt Interrupt CM10 = “1” Medium-speed mode (divided-by-8 mode) Wait mode CPU operation stopped Stop mode All oscillators stopped High-speed/mediumspeed mode Wait mode CPU operation stopped Stop mode CM10 = “1” Interrupt Low-speed/low power dissipation mode Wait mode Normal mode (Refer to the following for the transition of normal mode.) Transition of normal mode Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode) CM06 = “1” BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” CM04 = “1” (Notes 1, 3) CM07 = “0” (Note 1) CM06 = “1” CM04 = “0” Main clock is oscillating CM04 = “0” Sub clock is oscillating High-speed mode BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1” Medium-speed mode (divided-by-8 mode) BCLK : f(XIN)/8 CM07 = “0” CM06 = “1” Main clock is oscillating Sub clock is oscillating Low-speed mode CM07 = “0” (Note 1, 3) BCLK : f(XCIN) CM07 = “1” CM07 = “1” (Note 2) Medium-speed mode (divided-by-4 mode) BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0” Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1” CM05 = “0” CM04 = “0” CM05 = “1” Main clock is oscillating Sub clock is stopped CM04 = “1” High-speed mode BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0” CM06 = “0” (Notes 1,3) Medium-speed mode (divided-by-2 mode) BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1” Main clock is stopped Sub clock is oscillating Low power dissipation mode CM07 = “1” (Note 2) CM05 = “1” BCLK : f(XCIN) CM07 = “1” CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1” Medium-speed mode (divided-by-4 mode) BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0” Medium-speed mode (divided-by-16 mode) BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1” Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow. Figure 2.15.1. State transition diagram of power control mode 2-174 Mitsubishi microcomputers Power Control M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (3) Clearing stop mode and wait mode The stop mode and wait mode can be cleared by generating an interrupt request, or by resetting hardware. Set the priority level of the interrupt to be used for clearing, higher than the processor interrupt priority level (IPL), set that of the interrupt to “0” not to be used for clearing, and enable the interrupt enable flag (I flag). When an interrupt clears a mode, that interrupt is processed. Table 2.15.1 shows the interrupts that can be used for clearing a stop mode and wait mode. (4) BCLK in returning from wait mode or stop mode (a) Returning from wait mode The processor immediately returns to the BCLK, which was in use before entering wait mode. (b) Returning from stop mode CM06 is set to “1” when the device enters stop mode after selecting the main clock for BCLK. CM17, CM16, and CM07 do not change state. In this case, when restored from stop mode, the device starts operating in divided-by-8 mode. When the device enters stop mode after selecting the subclock for BCLK, CM06, CM17, CM16, and CM07 all do not change state. In this case, when restored from stop mode, the device starts operating in low-speed mode. Table 2.15.1. Interrupts available for clearing stop mode and wait mode Wait mode Interrupt for clearing Bus collision detection interrupt DMA0 interrupt DMA1 interrupt Key input interrupt A-D interrupt UART0 transmit interrupt UART0 receive interrupt UART1 transmit interrupt UART1 receive interrupt UART2 transmit interrupt UART2 receive interrupt SI/O3 interrupt SI/O4 interrupt Timer A0 interrupt Timer A1 interrupt Timer A2 interrupt Timer Timer Timer Timer Timer Timer Timer Timer INT0 INT1 INT2 INT3 A3 A4 B0 B1 B2 B3 B4 B5 interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt CM02 = 0 Possible Impossible Impossible Possible Note 3 Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible Possible CM02 =1(Note 6), CM07 = 0, CM05 = 0 Note 1 Impossible Impossible Possible Impossible Note 1 Note 1 Note 1 Note Note Note Note 1 1 1 4 Stop mode Note 1 Impossible Impossible Possible Impossible Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 4 Note 4 Note 2 Note Note Note Note Note Note Note Note 2 2 2 2 2 2 2 2 Note 4 Note 2, Note 5 Note Note Note Note Note Note Note Note Note 2, 2, 2, 2, 2, 2, 2, 2, 2, Note Note Note Note Note Note Note Note Note 5 5 5 5 5 5 5 5 5 interrupt interrupt interrupt interrupt Note 2, Note 5 Possible Possible Possible Possible Possible Possible Possible Note 2 Note 2 Possible Possible Possible Possible Possible Possible Possible INT4 interrupt INT5 interrupt NMI interrupt Note 1: Can be used when an external clock is selected (UART0, UART1). Can be used when an external clock in clock synchronous serial I/O mode is selected (UART2). Note 2: Can be used when the external signal is being counted in event counter mode. Note 3: Can be used in one-shot mode and one-shot sweep mode. Note 4: Can be used when an external clock is selected. Note 5: Can be used when count source is fC32. Note 6: When the MCU running in low-speed or low power dissipation mode, do not enter wait mode with CM02 is set to “1”. 2-175 Mitsubishi microcomputers Power Control M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (5) Sequence of returning from stop mode Sequence of returning from stop mode is oscillation start-up time and interrupt sequence. When interrupt is generated in stop mode, CM10 becomes “0” and clearing stop mode. Starting oscillation and supplying BCLK execute the interrupt sequence as follow: In the interrupt sequence, the processor carries out the following in sequence given: (a) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. The interrupt request bit of the interrupt written in address 0000016 will then be set to “0”. (b) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer assignment flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (d) Saves the content of the temporary register (Note) within the CPU in the stack area. (e) Saves the content of the program counter (PC) in the stack area. (f) Sets the interrupt priority level of the accepted instruction in the IPL. Note: This register cannot be utilized by the user. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Figure 2.15.2 shows the sequence of returning from stop mode. Writing “1” to CM10 (all clock stop control bit) Operated by divided-by-8 mode BCLK Address bus Data bus RD WR INTi Stop mode Oscillation start-up Interrupt sequence approximately 20 cycle (13µ sec) (Single-chip mode, f(XIN) = 16MHz) Address 00000 Interrupt information Indeterminate Indeterminate Indeterminate SP-2 SP-4 vec vec+2 vec+2 contents PC SP-2 SP-4 vec contents contents contents Note: Shown above is the case where the main clock is selected for BCLK. If the sub-clock is selected for BCLK, the sub-clock functions as BCLK when restored from stop mode, with the main clock's divide ratio unchanged. Figure 2.15.2. Sequence of returning from stop mode (6) Registers related to power control Figure 2.15.3 shows the memory map of power control-related registers, and Figure 2.15.4 shows power control-related registers. 000616 000716 System clock control register 0 (CM0) System clock control register 1 (CM1) Figure 2.15.3. Memory map of power control-related registers 2-176 Mitsubishi microcomputers Power Control M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER System clock control register 0 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Bit symbol CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07 Address 000616 Bit name Clock output function select bit (Valid only in single-chip mode) WAIT peripheral function clock stop bit When reset 4816 Function b1 b0 RW 0 0 : I/O port P57 0 1 : fC output 1 0 : f8 output 1 1 : f32 output 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8) XCIN-XCOUT drive capacity 0 : LOW select bit (Note 2) 1 : HIGH Port XC select bit Main clock (XIN-XOUT) stop bit (Note 3, 4, 5) Main clock division select bit 0 (Note 7) System clock select bit (Note 6) 0 : I/O port 1 : XCIN-XCOUT generation (Note 9) 0 : On 1 : Off 0 : CM16 and CM17 valid 1 : Division by 8 mode 0 : XIN, XOUT 1 : XCIN, XCOUT Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: Changes to “1” when shiffing to stop mode and at a reset. Note 3: When entering low power dissipation mode, main clock stops by using this bit. To stop the main clock, when the sub clock oscillation is stable, set system clock select bit (CM07) to “1” before setting this bit to “1”. Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT (“H”) via the feedback resistor. Note 6: Set port XC select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting this bit from “0” to “1”. Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock oscillating before setting this bit from “1” to “0”. Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 8: fC32 is not included. Do not set to “1” when using low-speed or low power dissipation mode. Note 9: When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up. System clock control register 1 (Note 1) b7 b6 b5 b4 b3 b2 b1 b0 00 0 0 Symbol CM1 Bit symbol CM10 Address 000716 Bit name All clock stop control bit (Note4) When reset 2016 Function 0 : Clock on 1 : All clocks off (stop mode) Must always be set to “0” Must always be set to “0” Must always be set to “0” Must always be set to “0” 0 : LOW 1 : HIGH b7 b6 RW Reserved bit Reserved bit Reserved bit Reserved bit CM15 CM16 CM17 XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3) 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8. Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn highimpedance state. Figure 2.15.4. Power control-related registers 2-177 Mitsubishi microcomputers Power Control M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.15.2 Stop Mode Set-Up Settings and operation for entering stop mode are described here. Operation (1) Enables the interrupt used for returning from stop mode. (2) Sets the interrupt enable flag (I flag) to “1”. (3) Clearing the protection and setting all clock stop control bit to “1” stops oscillation and causes the processor to go into stop mode. (1) Setting interrupt to cancel stop mode Interrupt control register TBiIC(i=3 to 5) BCNIC KUPIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 2) b7 b0 [Address 004516 to 004716] [Address 004A16] [Address 004D16] [Address 005116, 005316, 004F16] [Address 005216, 005416, 005016] [Address 005516 to 005916] [Address 005A16 to 005C16] b7 INTiIC(i=3) SiIC/INTjIC(i=4, 3) (j=3, 4) INTiIC(i=0 to 2) b0 [Address 004416] [Address 004816, 004916] [Address 004816, 004916] [Address 005D16 to 005F16] 0 Interrupt priority level select bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority(IPL) of the routine where the WAIT instruction is executed. Interrupt priority level select bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority(IPL) of the routine where the WAIT instruction is executed. Reserved bit Must always be set to “0” (2) Interrupt enable flag (I flag) “1” (3) Canceling protect b7 b0 1 Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled (3) Setting operation clock after returning from stop mode (When operating with XIN after returning) b7 b0 (When operating with XCIN after returning) b7 b0 System clock control register [Address 000616] CM0 0 0 1 1 System clock control register 0 [Address 000616] CM0 Main clock (XIN-XOUT) stop bit On Port XC select bit XCIN-XCOUT generation System clock select bit XIN, XOUT As this register becomes setting mentioned above when operating with XIN (count source of BCLK is XIN), the user does not need to set it again. System clock select bit XCIN, XCOUT As this register becomes setting mentioned above when operating with XCIN (count source of BCLK is XCIN), the user does not need to set it again. When operating with XIN, set port Xc select bit to “1” before setting system clock select bit to “1”. The both bits cannot be set at the same time. (3) All clocks off (stop mode) b7 b0 0 0 0 0 1 System clock control register [Address 000716] CM1 All clock stop control bit 1 : All clocks off (stop mode) Reserved bit Must always be set to “0” Insert at least four NOPs after the instruction that sets the all clock stop control bit to “1”. All clocks off (stop mode) Figure 2.15.5. Example of stop mode set-up 2-178 Mitsubishi microcomputers Power Control M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.15.3 Wait Mode Set-Up Settings and operation for entering wait mode are described here. Operation (1) Enables the interrupt used for returning from wait mode. (2) Sets the interrupt enable flag (I flag) to “1”. (3) Clears the protection and changes the content of the system clock control register. (4) Executes the WAIT instruction. (1) Setting interrupt to cancel wait mode Interrupt control register TBiIC(i=3 to 5) BCNIC KUPIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 4) TBiIC(i=0 to 2) b7 b0 [Address 004516 to 004716] [Address 004A16] [Address 004D16] [Address 005116, 005316, 004F16] [Address 005216, 005416, 005016] [Address 005516 to 005916] [Address 005A16 to 005C16] b7 INTiIC(i=3) SiIC/INTjIC (i=4, 3) (j=3, 4) INTiIC(i=0 to 2) b0 [Address 004416] [Address 004816, 004916] [Address 004816, 004916] [Address 005D16 to 005F16] 0 Interrupt priority level select bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority (IPL) of the routine where the WAIT instruction is executed. Interrupt priority level select bit Make sure that the interrupt priority level of the interrupt which is used to cancel the wait mode is higher than the processor interrupt priority (IPL) of the routine where the WAIT instruction is executed. Reserved bit Must always be set to “0” (2) Interrupt enable flag (I flag) (3) Canceling protect b7 b0 “1” 1 Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled (3) Control of CPU clock b7 b0 0 0 0 0 System clock control register 1 [Address 000716] CM1 Reserved bit Must always be set to “0” Main clock division select bit b7 b6 b7 b0 System clock control register 0 [Address 000616] CM0 WAIT peripheral function clock stop bit (Note 2) 0 : Do not stop f1, f8, f32 in wait mode 1 : Stop f1, f8, f32 in wait mode Port XC select bit 0 : I/O port 1 : XCIN-XCOUT generation Main clock (XIN-XOUT) stop bit 0 : On 1 : Off Main clock division select bit 0 0 : CM16 and CM17 valid 1 : Division by 8 mode System clock select bit (Note 1) 0 : XIN, XOUT 1 : XCIN, XCOUT 0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode Note 1: When switching the system clock, it is necessary to wait for the oscillation to stabilize. Note 2: Set the WAIT peripheral function clock stop bit to “0” when the system clock select bit is “1”. (4) WAIT instruction Insert at least four NOPs after the WAIT instruction is executed. Wait Figure 2.15.6. Example of wait mode set-up 2-179 Mitsubishi microcomputers Power Control M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.15.4 Precautions in Power Control ______ (1) The processor does not switch to stop mode when the NMI pin is at “L” level. ____________ (2) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is stabilized. (3) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the all clock stop control bit to “1” within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the all clock stop control bit to “1”. (4) Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock. (5) Suggestions to reduce power consumption (a) Ports The processor retains the state of each programmable I/O port even when it goes to wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in input ports that float. When entering wait mode or stop mode, set non-used ports to input and stabilize the potential. (b) A-D converter A current always flows in the VREF pin. When entering wait mode or stop mode, set the Vref connection bit to “0” so that no current flows into the VREF pin. (c) D-A converter The processor retains the D-A state even when entering wait mode or stop mode. Disable the output from the D-A converter then work on the programmable I/O ports. Set D-A register to “0016”. (d) Stopping peripheral functions In wait mode, stop non-used peripheral functions using the WAIT peripheral function clock stop bit. However, peripheral function clock fC32 does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. (e) Switching the oscillation-driving capacity Set the driving capacity to “LOW” when oscillation is stable. (f ) External clock When using an external clock input for the CPU clock, set the main clock stop bit to “1”. Setting the main clock stop bit to “1” causes the XOUT pin not to operate and the power consumption goes down (when using an external clock input, the clock signal is input regardless of the content of the main clock stop bit). 2-180 Mitsubishi microcomputers Programmable I/O Ports M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 2.16 Programmable I/O Ports Usage 2.16.1 Overview of the programmable I/O ports usage Eighty-seven programmable I/O ports and one input-only port are available. I/O pins also serve as I/O pins for built-in peripheral functions. Each port has a direction register that defines the I/O direction and also has a port register for I/O data. In addition, each port has a pull-up control register that defines pull-up in terms of 4 bits. The input-only port has neither direction register nor pull-up control bit. The following is an overview of the programmable I/O ports usage: (1) Writing to a port register With the direction register set to output, the level of the written values from each relevant pin is output by writing to a port register. The output level conforms to CMOS output. Port P70 and P71 are N channel open drain. Writing to the port register, with the direction register set to input, inputs a value to the port register, but nothing is output to the relevant pins. The output level remains floating. In memory expansion and microprocessor mode, the contents of corresponding port and direction _______ _______ _____ ________ ______ ________ _______ _______ __________ registers of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, _________ HLDA and BCLK cannot be modified. (2) Reading a port register With the direction register set to output, reading a port register takes out the content of the port register, not the content of the pin. With the direction register set to input, reading the port register takes out the content of the pin. (3) Effect of the protection register Data written to the direction register of P9 is affected by the protection register. The direction register of P9 cannot be easily rewritten. (4) Input-only port _______ P85 is used as the input-only port, it also serves as NMI. P85 has no direction register. Pull-up cannot _______ _______ be set to this port. As NMI cannot be disabled, an NMI interrupt occurs if a falling edge is input to P85. Use P85 for reading the level input at this time only. (5) Setting pull-up The pull-up control bit allows setting of the pull-up, in terms of 4 bits, either in use or not in use. For the four bits chosen, pull-up is effective only in the ports whose direction register is set to input. Pull-up is not effective in ports whose direction register is set to output. Do not set pull-up of corresponding pin when XCIN/XCOUT is set or a port is used as A-D input. Pull-up can be set for P0 to P3, P40 to P43, P5 in only single-chip mode. Pull-up cannot be set for P0 to P3, P40 to P43, P5 in memory expansion and microprocessor modes. The contents of register can be changed, but the pull-up resistance is not connected. 2-181 Mitsubishi microcomputers Programmable I/O Ports M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (6) I/O functions of built-in peripheral devices Table 2.16.1 shows relation between ports and I/O functions of built-in peripheral devices. Table 2.16.1. Relation between ports and I/O functions of built-in peripheral devices Port P15 to P17 P6 P70 P71 P72 to P73 P74 to P75 P76 to P77 P80, P81 P82 to P84 P86, P87 P90 to P92 P93, P94 P95, P96 P97 P100 to P103 P104 to P107 Internal peripheral device I/O pins Input pins for external interrupt I/O pins for serial I/O communication I/O pins for serial I/O communication/Timer A I/O pin I/O pins for serial I/O communication/Timer A I/O pins/Timer B input pin I/O pins for serial I/O communication/Timer A I/O pins/Three-phase motor control output pins Timer A I/O pins/Three-phase motor control output pins Timer A I/O pins Timer A I/O pins Input pins for external interrupt Sub-clock oscillation circuit I/O pins Timer B input pins D-A converter output pins A-D converter extended input pins A-D trigger input pin A-D converter input pins A-D converter input pins / key-input interrupt function input pins (7) Examples of working on non-used pins Table 2.16.2 contains examples of working on non-used pins. There are shown here for mere examples. In practical use, make suitable changes and perform sufficient evaluation in compliance with you application. (a) Single-chip mode Table 2.16.2. Examples of working on unused pins in single-chip mode Pin name Connection Ports P0 to P10 (excluding P85) After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. (Note 1, Note 3) XOUT (Note 2) NMI AVCC AVSS, VREF, BYTE Open Connect to VCC via a resistor Connect to VCC Connect to VSS Note 1: If setting these pins in output mode and opening them, ports are in input mode until switched into output mode by use of software after reset. Thus the voltage levels of the pins become unstable, and there can be instances in which the power source current increases while the ports are in input mode. In view of an instance in which the contents of the direction registers change due to a runaway generated by noise or other causes, setting the contents of the direction registers periodically by use of software increases program reliability. Note 2: When an external clock is input to the XIN pin. Note 3: Output "L" if port P70 and P71 are set to output mode. Port P70 and P71 are N channel open drain output. 2-182 Mitsubishi microcomputers Programmable I/O Ports M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (b) Memory expansion mode, microprocessor mode Table 2.16.3. Examples of working on unused pins in memory expansion mode or microprocessor mode Pin name Connection Ports P6 to P10 (excluding P85) After setting for input mode, connect every pin to VSS or VCC via a resistor; or after setting for output mode, leave these pins open. (Note 1, Note 2, Note 5) BHE, ALE, HLDA XOUT (Note 4), BCLK (Note 6) HOLD, RDY, NMI AVCC AVSS, VREF Open (Note 3) Open Connect via resistor to VCC (pull-up) Connect to VCC Connect to VSS Note 1: If setting these pins in output mode and opening them, ports are in input mode until switched into output mode by use of software after reset. Thus the voltage levels of the pins become unstable, and there can be instances in which the power source current increases while the ports are in input mode. In view of an instance in which the contents of the direction registers change due to a runaway generated by noise or other causes, setting the contents of the direction registers periodically by use of software increases program reliability. Note 2: Make wiring as short as possible (not more than 2 cm from the microcomputer's pins) in working on non-used pins. Note 3: When a VSS level is connected to the CNVSS pin, these pins are input ports until the processor mode is switched by use of software after reset. Thus the voltage levels of the pins destabilize, and there can be an increase in the power source current while these pins are input ports. Note 4: When an external clock is input to the XIN pin. Note 5: Output "L" if port P70 and P71 are set to output mode. Port P70 and P71 are N channel open drain output. Note 6: When the BCLK output disable bit (bit 7 at address 000416) is set to “1”, connect to VCC via a resistor (pull-up). 2-183 Mitsubishi microcomputers Programmable I/O Ports M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (8) Registers related to the programmable I/O ports Figure 2.16.1 shows the memory map of programmable I/O ports-related registers, and Figures 2.16.2 to 2.16.4 show programmable I/O ports-related registers. 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03FC16 03FD16 03FE16 03FF16 Port P0 register (P0) Port P1 register (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 register (P2) Port P3 register (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 register (P4) Port P5 register (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 register (P6) Port P7 register (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 register (P8) Port P9 register (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 register (P10) Port P10 direction register (PD10) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR) Figure 2.16.1. Memory map of programmable I/O ports-related registers 2-184 Mitsubishi microcomputers Programmable I/O Ports M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi direction register (Note 1, 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PDi (i = 0 to 10, except 8) Address 03E216, 03E316, 03E616, 03E716, 03EA16 03EB16, 03EE16, 03EF16, 03F316, 03F616 When reset 0016 Bit symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7 Bit name Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 10 except 8) RW Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the port P9 direction register. Note 2: In memory expansion and microprocessor mode, the contents of corresponding port Pi direction register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Port P8 direction register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PD8 Address 03F216 When reset 00X000002 Bit symbol PD8_0 PD8_1 PD8_2 PD8_3 Bit name Port P80 direction register Port P81 direction register Port P82 direction register Port P83 direction register Function 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) RW PD8_4 Port P84 direction register Nothing is assigned. In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate. PD8_6 PD8_7 Port P86 direction register Port P87 direction register 0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) Figure 2.16.2. Programmable I/O ports-related registers (1) 2-185 Mitsubishi microcomputers Programmable I/O Ports M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Port Pi register (Note 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Pi (i = 0 to 10, except 8) Address 03E016, 03E116, 03E416, 03E516, 03E816 03E916, 03EC16, 03ED16, 03F116, 03F416 When reset Indeterminate Indeterminate Bit symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7 Bit name Port Pi0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : “L” level data 1 : “H” level data (Note 1) (i = 0 to 10 except 8) RW Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance. Note 2: In memory expansion and microprocessor mode, the contents of corresponding port Pi register of pins A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be modified. Port P8 register b7 b6 b5 b4 b3 b2 b1 b0 Symbol P8 Address 03F016 When reset Indeterminate Bit symbol P8_0 P8_1 P8_2 P8_3 P8_4 P8_5 P8_6 P8_7 Bit name Port P80 register Port P81 register Port P82 register Port P83 register Port P84 register Port P85 register Port P86 register Port P87 register Function Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P85) 0 : “L” level data 1 : “H” level data RW Figure 2.16.3. Programmable I/O ports-related registers (2) 2-186 Mitsubishi microcomputers Programmable I/O Ports M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up control register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR0 Bit symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07 Address 03FC16 Bit name P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up P20 to P23 pull-up P24 to P27 pull-up P30 to P33 pull-up P34 to P37 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW Note : In memory expansion and microprocessor mode, the content of this register can be changed, but the pull-up resistance is not connected. Pull-up control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR1 Bit symbol PU10 PU11 PU12 PU13 PU14 PU15 PU16 Address 03FD16 Bit name When reset 0016 (Note 2) Function RW P40 to P43 pull-up (Note 3) The corresponding port is pulled high with a pull-up resistor P44 to P47 pull-up 0 : Not pulled high P50 to P53 pull-up (Note 3) 1 : Pulled high P54 to P57 pull-up P60 to P63 pull-up P64 to P67 pull-up P72 to P73 pull-up (Note 1) PU17 P74 to P77 pull-up Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them. Note 2: When the VCC level is being impressed to the CNVSS terminal, this register becomes to 0216 when reset (PU11 becomes to “1”). Note 3: In memory expansion and microprocessor mode, the content of these bits can be changed, but the pull-up resistance is not connected. Pull-up control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Symbol PUR2 Bit symbol PU20 PU21 PU22 PU23 PU24 PU25 Address 03FE16 Bit name P80 to P83 pull-up P84 to P87 pull-up (Except P85) P90 to P93 pull-up P94 to P97 pull-up P100 to P103 pull-up P104 to P107 pull-up When reset 0016 Function The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW Nothing is assigned. In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”. Figure 2.16.4. Programmable I/O ports-related registers (3) 2-187 Mitsubishi microcomputers Programmable I/O Ports M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER [ MEMO ] 2-188 Chapter 3 Examples of Peripheral functions Applications Mitsubishi microcomputers Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER This chapter presents applications in which peripheral functions built in the M16C/62A are used. They are shown here as examples. In practical use, make suitable changes and perform sufficient evaluation. For basic use, see Chapter 2 Peripheral Functions Usage. Here follows the list of applications that appear in this chapter. • 3.1 Long-period timers ........................................................................................................... P2-192 • 3.2 Variable-period variable-duty PWM output ...................................................................... P2-196 • 3.3 Delayed one-shot output ................................................................................................. P2-200 • 3.4 Buzzer output .................................................................................................................. P2-204 • 3.5 Solution for external interrupt pins shortage .................................................................... P2-206 • 3.6 Memory to memory DMA transfer ................................................................................... P2-208 • 3.7 Controlling power using stop mode ................................................................................. P2-212 • 3.8 Controlling power using wait mode .................................................................................. P2-216 2-190 Mitsubishi microcomputers Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER [ MEMO ] 2-191 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 3.1 Long-Period Timers Overview In this process, Timer A0 and Timer A1 are connected to make a 16-bit timer with a 16-bit prescaler. Figure 3.1.1 shows the operation timing, Figure 3.1.2 shows the connection diagram, and Figures 3.1.3 and 3.1.4 show the set-up procedure. Use the following peripheral functions: • Timer mode of timer A • Event counter mode of timer A Specifications (1) Set timer A0 to timer mode, and set timer A1 to event counter mode. (2) Perform a count on count source f1 using timer A0 to count for 1 ms, and perform a count on timer A0 using timer A1 to count for 1 second. (3) Connect a 16-MHz oscillator to XIN. Operation (1) Setting the count start flag to “1” causes the counter to begin counting. The counter of timer A0 performs a down count on count source f1. (2) If the counter of timer A0 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer A0 interrupt request bit goes to “1”. The counter of timer A1 performs a down count on underflows in timer A0. (3) If the counter of timer A1 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer A1 interrupt request bit goes to “1”. l = reload register content Timer A0 counter content (hex) FFFF16 l (1) Start count (2) Timer A0 underflow (3) Timer A1 underflow 000016 Timer A1 counter content (hex) Time n = reload register content FFFF16 n 000016 Set to “1” by software Cleard “0” by software Time “1” “0” Set to “1” by software “1” “0” Start count. Timer A0 count start flag Timer A1 count start flag Timer A0 interrupt “1” “0” request bit Cleared to “0” when interrupt request is accepted, or cleared by software Timer A1 interrupt “1” request bit “0” Figure 3.1.1. Operation timing of long-period timers 2-192 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER f1 f8 f32 fC32 Used for timer mode Timer A0 Timer A1 Timer A0 interrupt request bit Timer A1 interrupt request bit Used for event counter mode Figure 3.1.2. Connection diagram of long-period timers 2-193 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting timer A0 Selecting timer mode and functions b7 b0 0 0 0 0 0 0 0 0 Timer A0 mode register [Address 039616] TA0MR Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Gate function select bit b4 b3 0 0 : Gate function not available (TA0IN pin is a normal port pin) 0 (Must always be “0” in timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Setting counter value (b15) b7 (b8) b0 b7 b0 3E16 7F16 Timer A0 register [Address 038716, 038616] TA0 Setting timer A1 Selecting event counter mode and each function b7 b0 0 0 0 0 0 0 1 Timer A1 mode register [Address 039716] TA1MR Selection of event counter mode Pulse output function select bit] 0 : Pulse is not output (TA1OUT pin is a normal port pin) Count polarity select bit Up/down switching cause select bit 0 : Up/down flag content 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type Continued to the next page Figure 3.1.3. Set-up procedure of long-period timers (1) 2-194 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Setting trigger select register b7 b0 10 Trigger select register [Address 038316] TRGSR Timer A1 event/trigger select bit b1 b0 1 0 : TA0 overflow is selected Setting counter value (b15) b7 (b8) b0 b7 b0 0316 E716 Timer A1 register [Address 038916, 038816] TA1 Setting count start flag b7 b0 1 1 Count start flag [Address 038016] TABSR Timer A0 count start flag 1 : Starts counting Timer A1 count start flag 1 : Starts counting Start counting Figure 3.1.4. Set-up procedure of long-period timers (2) 2-195 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 3.2 Variable-Period Variable-Duty PWM Output Overview In this process, Timer A0 and A1 are used to generate variable-period, variable-duty PWM output. Figure 3.2.1 shows the operation timing, Figure 3.2.2 shows the connection diagram, and Figures 3.2.3 and 3.2.4 show the set-up procedure. Use the following peripheral functions: • Timer mode of timer A • One-shot timer mode of timer A Specifications (1) Set timer A0 in timer mode, and set timer A1 in one-shot timer mode with pulse-output function. (2) Set 1 ms, the PWM period, to timer A0. Set 500 µs, the width of PWM “H” pulse, to timer A1. Both timer A0 and timer A1 use f1 for the count source. (3) Connect a 16-MHz oscillator to XIN. Operation (1) Setting the count start flag to “1” causes the counter of timer A0 to begin counting. The counter of timer A0 performs a down count on count source f1. (2) If the counter of timer A0 underflows, the counter reloads the content of the reload register and continues counting. At this time, the timer A0 interrupt request bit goes to “1”. (3) An underflow in timer A0 triggers the counter of timer A1 and causes it to begin counting. When the counter of timer A1 begins counting, the output level of the TA1OUT pin goes to “H”. (4) As soon as the count of the counter of timer A1 becomes “000016”, the output level of TA1OUT pin goes to “L”, and the counter reloads the content of the reload register and stops counting. At the same time, the timer A1 interrupt request bit goes to “1”. 2-196 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER l = reload register content (1) Timer A0 start count Timer A0 counter content (hex) FFFF16 l (2) Timer A0 underflow 000016 Timer A1 counter content (hex) n = reload register content FFFF16 n 000116 Time (3) Timer A1 start count (4) Timer A1 stop count Set to “1” by software Timer A0 count start flag Timer A1 count start flag “1” “0” “1” “0” Time Set to “1” by software 1ms 500µs PWM pulse output “H” from TA1OUT pin “L” Timer A0 interrupt “1” request bit “0” Cleared to “0” when interrupt request is accepted, or cleared by software Timer A1 interrupt “1” request bit “0” Cleared to “0” when interrupt request is accepted, or cleared by software Figure 3.2.1. Operation timing of variable-period variable-duty PWM output f1 Used for timer mode (Set to period) f8 Timer A0 f32 fC32 Timer A0 interrupt request bit Timer A1 Timer A1 interrupt request bit Used for one-shot timer mode (Set to “H” width) Figure 3.2.2. Connection diagram of variable-period variable-duty PWM output 2-197 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting timer A0 Selecting timer mode and functions b7 b0 0 0 0 0 0 0 0 0 Timer A0 mode register [Address 039616 ] TA0MR Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Gate function select bit b4 b3 0 0 : Gate function not available (TA0IN pin is a normal port pin) 0 (Must always be “0” in timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Setting counter value (b15) b7 (b8) b0 b7 b0 3E16 7F16 Timer A0 register [Address 038716, 038616] TA0 Setting timer A1 Selecting one-shot timer mode and functions b7 b0 0 0 0 1 0 1 1 0 Timer A1 mode register [Address 039716 ] TA1MR Selection of one-shot timer mode Pulse output function select bit 1 : Pulse is output External trigger select bit (Invalid when choosing timer's overflow as trigger) Trigger select bit 1 : Selected by event/trigger select register 0 (Must always be “0” in one-shot timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Continued to the next page Figure 3.2.3. Set-up procedure of variable-period variable-duty PWM output (1) 2-198 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Setting trigger select register b7 b0 10 Trigger select register [Address 038316] TRGSR Timer A1 event/trigger select bit b1 b0 1 0 : TA0 overflow is selected Setting one-shot timer's time (b15) b7 (b8) b0 b7 b0 1F16 4016 Timer A1 register [Address 038916, 038816] TA1 Setting count start flag b7 b0 1 1 Count start flag [Address 038016] TABSR Timer A0 count start flag 1 : Starts counting Timer A1 count start flag 1 : Starts counting Start counting Figure 3.2.4. Set-up procedure of variable-period variable-duty PWM output (2) 2-199 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 3.3 Delayed One-Shot Output Overview The following are steps of outputting a pulse only once after a specified elapse since an external trigger is input. Figure 3.3.1 shows the operation timing, Figure 3.3.2 shows the connection diagram, and Figures 3.3.3 and 3.3.4 show the set-up procedure. Use the following peripheral function: • One-shot timer mode of timer A Specifications (1) Set timer A0 in one-shot timer mode, and set timer A1 in one-shot timer mode with pulseoutput function. (2) Set 1 ms, an interval before a pulse is output, in timer A0; and set 50 µs, a pulse width, in timer A1. Both timer A0 and timer A1 use f1 for the count source. (3) Connect a 16-MHz oscillator to XIN. Operation (1) Setting the trigger select bit to “1” and setting the count start flag to “1” enables the counter of timer A0 to count. (2) If an effective edge, selected by use of the external trigger select bit, is input to the TA0IN pin, the counter begins a down count. The counter of timer A0 performs a down count on count source f1. (3) As soon as the counter of timer A0 becomes “000016”, the counter reloads the content of the reload register and stops counting. At this time, the timer A0 interrupt request bit goes to “1”. (4) An underflow in timer A0 triggers the counter of timer A1 and causes it to begin counting. When timer A1 begins counting, the output level of the TA1OUT pin goes to “H”. (5) As soon as the counter of timer A1 becomes “000016”, the output level of the TA1OUT pin goes to “L”, the counter reloads the content of the reload register, and stops counting. At this time, timer A1 interrupt request bit goes to “1”. 2-200 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER l = reload register content (1) Count enabled (2) Timer A0 start count Timer A0 counter content (hex) FFFF16 l (3) Timer A0 stop count 000116 Timer A1 counter content (hex) n = reload register content FFFF16 n 000116 Set to “1” by software (4) Timer A1 start count (5) Timer A1 stop count Time Time Timer A0 count start flag Timer A1 count start flag Input signal from TA0IN pin “1” “0” “1” “0” “H” “L” Set to “1” by software 1ms 50µs PWM pulse output “H” from TA1OUT pin “L” Timer A0 interrupt “1” “0” request bit Timer A1 interrupt request bit Cleared to “0” when interrupt request is accepted, or cleared by software “1” “0” Cleared to “0” when interrupt request is accepted, or cleared by software Figure 3.3.1. Operation timing of delayed one-shot output TA0IN pin input f1 f8 f32 fC32 Used for one-shot timer mode Timer A0 Timer A0 interrupt request bit Timer A1 Timer A1 interrupt request bit Used for one-shot timer mode Figure 3.3.2. Connection diagram of delayed one-shot output 2-201 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Setting timer A0 Selecting one-shot timer mode and functions b7 b0 0 0 0 1 0 0 1 0 Timer A0 mode register [Address 039616] TA0MR Selection of one-shot timer mode Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is normal port pin) External trigger select bit 0 : Falling edge of TA0IN pin's input signal Trigger select bit 1 : Selected by event/trigger select register 0 (Must always be “0” in one-shot timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Setting one-shot start flag (Select TA0IN pin to input TA0 trigger) b7 b0 One-shot start flag [Address 038216] ONSF Timer A0 event/trigger select bit b7 b6 0 0 : Input on TA0IN is selected (Note) Note: Set the corresponding port direction register to “0”. Setting delay time (b15) b7 (b8) b0 b7 b0 3E16 8016 Timer A0 register [Address 038716, 038616] TA0 Continued to the next page Figure 3.3.3. Set-up procedure of delayed one-shot output (1) 2-202 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Setting timer A1 Selecting one-shot timer mode and functions b7 b0 0 0 0 1 0 1 1 0 Timer A1 mode register [Address 039716] TA1MR Selection of one-shot timer mode Pulse output function select bit 1 : Pulse is output (TA1OUT pin is pulse output pin) External trigger select bit Invalid when choosing timer's overflow Trigger select bit 1 : Selected by event/trigger select register 0 (Must always be “0” in one-shot timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs Setting trigger select register (Set timer A0 to trigger timer A1) b7 b0 10 Trigger select register [Address 038316] TRGSR Timer A1 event/trigger select bit b1 b0 1 0 : TA0 overflow is selected Setting one-shot timer's time (b15) b7 (b8) b0 b7 b0 0316 2016 Timer A1 register [Address 038916, 038816] TA1 Setting count start flag b7 b0 1 1 Count start flag [Address 038016] TABSR Timer A0 count start flag 1 : Starts counting Timer A1 count start flag 1 : Starts counting Start counting Figure 3.3.4. Set-up procedure of delayed one-shot output (2) 2-203 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 3.4 Buzzer Output Overview The timer mode is used to make the buzzer ring. Figure 3.4.1 shows the operation timing, and Figure 3.4.2 shows the set-up procedure. Use the following peripheral function: • The pulse-outputting function in timer mode of timer A. Specifications (1) Sound a 2-kHz buzz beep by use of timer A0. (2) Effect pull-up in the relevant port by use of a pull-up resistor. When the buzzer is off, set the port high-impedance, and stabilize the potential resulting from pulling up. (3) Connect a 16-MHz oscillator to XIN. Operation (1) The microcomputer begins performing a count on timer A0. Timer A0 has disabled interrupts. (2) The microcomputer begins pulse output by setting the pulse output function select bit to “Pulse output effected”. P70 changes into TA0OUT pin and outputs 2-kHz pulses. (3) The microcomputer stops outputting pulses by setting the pulse output function select bit to “Pulse output not effected”. P70 goes to an input pin, and the output from the pin becomes high-impedance. (1) Start count (2) Buzzer output ON (3) Buzzer output OFF Timer A0 overflow timing “1” Count start flag “0” “1” “0” “1” Pulse output function select bit P70 output “0” High-impedance High-impedance Figure 3.4.1. Operation timing of buzzer output 2-204 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Initialization of timer A0 b7 b0 00 0 0 0 00 0 Timer A0 mode register TA0MR [Address 039616 ] Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA0out pin is a normal port pin) Gate function select bit b4 b3 0 0 : Gate function not available 0 (Must always be “0” in timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 0 0 : f1 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs b15 b8 b7 b0 0F16 b7 b0 9F16 Timer A0 register TA0 [Address 038716, 038616] b7 b0 1 Count start flag [Address 038016] TABSR Timer A0 count start flag 1 : Starts counting Initialization of port P7 direction register b7 b0 0 Port P7 direction register [Address 03EF16] PD7 Port P70 direction register 0 : Input mode Buzzer ON b7 b0 1 Timer A0 mode register [Address 039616 ] TA0MR Pulse output function select bit 1 : Pulse is output (Port P70 is TA0OUT output pin) Buzzer OFF b7 b0 0 Timer A0 mode register [Address 039616 ] TA0MR Pulse output function select bit 0 : Pulse is not output Figure 3.4.2. Set-up procedure of buzzer output 2-205 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 3.5 Solution for External Interrupt Pins Shortage Overview The following are solution for external interrupt pins shortage. Figure 3.5.1 shows the set-up procedure. Use the following peripheral function: • Event counter mode of timer A Specifications (1) Inputting a falling edge to the TA0IN pin generates a timer A0 interrupt. Operation (1) Set timer A0 to event counter mode, set timer to “0”, and set interrupt priority levels in timer A0. (2) Inputting a falling edge to the TA0IN pin generates a timer A0 interrupt. 2-206 Mitsubishi microcomputers Timer A Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Initialization of timer A0 b7 b0 0 00 0 00 0 1 Timer A0 mode register TA0MR [Address 039616 ] Selection of event counter mode Pulse output function select bit 0 : Pulse is not output (TA0out pin is a normal port pin) Count polarity select bit 0 : Counts external signal's falling edge Up/down switching cause select bit 0 : Up/down flag's content 0 (Must always be “0” in event counter mode) Count operation type select bit 0 : Reload type 0 (Must always be “0” in event counter mode) b15 b8 b7 b0 0016 b7 b7 b0 0016 Timer A0 register TA0 [Address 038716, 038616] b0 0 Up/down flag [Address 038416] UDF Timer A0 up/down flag 0 : Down count b7 b0 0 0 One shot start flag [Address 038216] ONSF Timer A0 event/trigger select flag b7 b6 0 0 : Input on TA0IN is selected b7 b0 1 Count start flag [Address 038016] TABSR Timer A0 count start flag 1 : Starts counting Setting interrupt priority levels in timer A0 b7 b0 Timer A0 interrupt control register [Address 005516] TA0IC Interrupt control level (set a value 1 to 7) Initialization of port P7 direction register b7 b0 0 Port P7 direction register [Address 03EF16] PD7 Port P71 direction register 0 : Input mode Setting interrupt enable flag (I flag) Figure 3.5.1. Set-up procedure of solution for a shortage of external interrupt pins 2-207 Mitsubishi microcomputers DMAC Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 3.6 Memory to Memory DMA Transfer Overview The following are steps for changing both source address and destination address to transfer data from memory to another. The DMA transfer utilizes the workings that assign a higher priority to the DMA0 transfer if transfer requests simultaneously occur in two DMA channels. Figure 3.6.1 shows the operation timing, Figure 3.6.2 shows the block diagram, and Figures 3.6.3 and 3.6.4 show the set-up procedure. Use the following peripheral functions: • Timer mode of timer A • Two DMAC channels • One-byte temporary RAM (address 080016) Specifications (1) Transfer the content of memory extending over 128 bytes from address A000016 to a 128byte area starting from address C000016. Transfer the content every time a timer A0 interrupt request occurs. (2) Use DMA0 for a transfer from the source to built-in memory, and DMA1 for a transfer from built-in memory to the destination. Operation (1) A timer A interrupt request occurs. Though both a DMA0 transfer request and a DMA1 transfer request occur simultaneously, the former is executed first. (2) DMA0 receives a transfer request and transfers data from the source to the built-in memory. At this time, the source address is incremented. (3) Next, DMA1 receives a transfer request and transfers data involved from built-in memory to the destination. At this time, the destination address is incremented. (1) Transfer request generation (2) Start DMA0 transferring “1” Timer A0 transfer request “0” Source address Address bus A000016 080016 (3) Start DMA1 transferring Source address 080016 C000016 Destination address Destination address “1” RD signal “0” “1” WR signal “0” Instruction cycle DMA0 operation DMA1 operation Note 1: The DMA0 operation and DMA1 operation are not necessarily executed in succession due to the a cycle steal operation. Note 2: The instruction cycle varies from instruction to instruction. Note 3: Since the parts of the RD and WR signals shown in short-dash lines vary in step with writing to the internal RAM, waveforms are not output to the RD and WR pins. Figure 3.6.1. Operation timing of memory to memory DMA transfer 2-208 Mitsubishi microcomputers DMAC Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Source area A000016 Destination area A00016 content A00116 content A00216 content C000016 A007F16 Temporary RAM A007F16 content C007F16 80016 Data transfer by DMA0 Data transfer by DMA1 Figure 3.6.2. Block diagram of memory to memory DMA transfer 2-209 Mitsubishi microcomputers DMAC Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Initialization of DMA0 b7 b0 0 0 0 1 0 DMA0 request cause select register DM0SL [Address 03B816] b7 b0 0 1 1 0 11 DMA0 control register DM0CON [Address 002C16] Transfer unit bit select bit 1 : 8 bits Repeat transfer mode select bit 1 : Repeat transfer DMA request bit 0 : DMA not requested DMA enable bit 1 : Enabled Source address direction select bit 1 : Forward Destination address direction select bit 0 : Fixed DMA request cause select bit b3 b2 b1 b0 0 0 1 0 : Timer A0 Software DMA request bit 0 : Software is not generated b23 b16 b15 b8 b7 b0 0A16 b7 b23 0016 b0 b7 b16 b15 0016 b0 b8 b7 b0 DMA0 source pointer SAR0 [Address 002216, 002116, 002016] 0016 b7 b0 b7 b15 0816 b0 b8 b7 0016 b0 DMA0 destination pointer DAR0 [Address 002616, 002516, 002416] 0016 b7 b0 7F16 DMA0 transfer counter TCR0 [Address 002916, 002816] Initialization of DMA1 b7 b0 b7 b0 0 0010 DMA0 request cause select register DM1SL [Address 03BA16] 101011 DMA1 control register DM1CON [Address 003C16] Transfer unit bit select bit 1 : 8 bits Repeat transfer mode select bit 1 : Repeat transfer DMA request bit 0 : DMA not requested DMA enable bit 1 : Enabled Source address direction select bit 0 : Fixed Destination address direction select bit 1 : Forward DMA request cause select bit b3 b2 b1 b0 0 0 1 0 : Timer A0 Software DMA request bit 0 : Software is not generated b23 b16 b15 b8 b7 b0 0016 b7 b23 b0 b7 b16 b15 0816 b0 b8 b7 0016 b0 DMA1 source pointer SAR1 [Address 003216, 003116, 003016] 0C16 b7 b0 b7 b15 0016 b0 b8 b7 0016 b0 DMA1 destination pointer DAR1 [Address 003616, 003516, 003416] 0016 b7 b0 7F16 DMA1 transfer counter TCR1 [Address 003916, 003816] Continued to the next page Figure 3.6.3. Set-up procedure of memory to memory DMA transfer (1) 2-210 Mitsubishi microcomputers DMAC Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Initialization of timer A0 b7 b0 0 0 0 0 0 0 0 0 Timer A0 mode register TA0MR [Address 039616 ] Selection of timer mode Pulse output function select bit 0 : Pulse is not output (TA0OUT pin is a normal port pin) Gate function select bit b4 b3 0 0 : Gate function not available (TA0IN pin is a normal port pin) 0 (Must always be “0” in timer mode) Count source select bit b7 b6 b7 b6 0 0 1 1 0 1 0 1 Count source period Count source f(XIN) : 16MHZ f(XcIN) : 32.768kHZ f1 f8 f32 fC32 62.5ns 500ns 2µs 976.56µs 0 0 : f1 b15 b8 b7 b0 3E16 b7 b0 0F16 Timer A0 register TA0 [Address 0387, 038616 ] b7 b0 1 Count start flag [Address 038016] TABSR Timer A0 count start flag 1 : Starts counting Figure 3.6.4. Set-up procedure of memory to memory DMA transfer (2) 2-211 Mitsubishi microcomputers Controlling Power Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 3.7 Controlling Power Using Stop Mode Overview The following are steps for controlling power using stop mode. Figure 3.7.1 shows the operation timing, Figure 3.7.2 shows an example of circuit, and Figures 3.7.3 and 3.7.4 show the set-up procedure. Use the following peripheral functions: • Key-input interrupts • Stop mode • Pull-up function Specifications _____ (1) Use P100 through P103 for the scan output pins of a key matrix. Use the input pins (KI0 _____ through KI3) of the key-input interrupt function for the key-input reading pins. The pull-up function is also used. (2) If a key-input interrupt request occurs, clear the stop mode and read a key. _____ _____ Operation (1) Enable a key-input interrupt and set the pull-up function to pins KI0 through KI3. Change the output of P100 through P103 to “L” and enter stop mode. _____ _____ (2) If a key is pressed, “L” is input to one of pins KI0 through KI3 to clear stop mode. A key-input interrupt occurs to execute the key-input interrupt handling routine. (3) Sequentially set P100 through P103 to “L” to determine which key was pressed. (4) When the process to determine the key pressed is completed, change the output from P100 through P103 to “L” again and enter stop mode. (1) Shift to stop mode (2) Cancel a stop mode (3) Key scan (4) Shift to stop mode Key matrix scan P100 output P101 output P102 output P103 output P104 to P107 input Key input Key input interrupt processing CPU clock Stop mode Stop mode Key OFF Key ON Key OFF Key ON Figure 3.7.1. Operation timing of controlling power using stop mode 2-212 Mitsubishi microcomputers Controlling Power Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER P100 P101 P102 P103 P104 / KI0 P105 / KI1 P106 / KI2 P107 / KI3 VREF I/O port Figure 3.7.2. Example of circuit of controling power using stop mode 2-213 Mitsubishi microcomputers Controlling Power Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Main Initial condition b7 b0 1 Pull-up control register 2 [Address 03FE16] PUR2 b7 b0 0 0 00 1 1 11 Port P10 direction register [Address 03F616] PD10 Key scan output port Key scan input port Key input interrupt control register [Address 004D16] KUPIC P104 to P107 pulled high b7 b0 0 00 0 Port P10 register [Address 03F416] P10 b7 b0 Key scan data 00 1 Interrupt priority level select bit Set higher value than the present IPL Processor interrupt priority level (IPL) = 0 Interrupt enable flag (I) =0 Setting interrupt except stop mode cancel Interrupt control register TBiIC(i=3 to 5) [Address 004516 to 004716] b7 0 BCNIC DMiIC(i=0, 1) ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) b0 TAiIC(i=0 to 4) 0 0 TBiIC(i=0 to 2) [Address 004A16] [Address 004B16, 004C16] [Address 004E16] [Address 005116, 005316, 004F16] [Address 005216, 005416, 005016] b7 [Address 005516 to 005916] [Address 005A16 to 005C16] b0 0 0 0 0 INTiIC(i=0 to 2) [Address 005D16 to 005F16] Interrupt priority level select bit 000 : Interrupt disabled Interrupt priority level select bit 000 : Interrupt disabled Reserved bit Must always be set to “0” Canceling protect b7 b0 1 Protect register [Address 000A16] PRCR Enables writing to system clock control registers 0 and 1 (addresses 000616 and 000716) 1 : Write-enabled Setting operation clock after returning from stop mode (When operating with XIN after returning) b7 b0 (When operating with XCIN after returning) b7 b0 System clock control register 0 [Address 000616] CM0 Main clock (XIN-XOUT) stop bit On System clock control register 0 [Address 000616] CM0 Port XC select bit XCIN-XCOUT generation 0 0 1 1 System clock select bit XIN, XOUT As this register becomes setting mentioned above when operating with XIN (count source of BCLK is XIN), the user does not need to set it again. System clock select bit XCIN, XCOUT As this register becomes setting mentioned above when operating with XCIN (count source of BCLK is XCIN), the user does not need to set it again. When operating with XIN, set port Xc select bit to “1” before setting system clock select bit to “1”. The both bits cannot be set at the same time. Interrupt enable flag (I flag) “1” All clocks off (stop mode) b7 b0 0 00 0 1 System clock control register 1 [Address 000716] CM1 All clock stop control bit 1 : All clocks off (stop mode) Reserved bit Must always be set to “0” NOP instruction X 4 Key input interrupt request generation Figure 3.7.3. Set-up procedure of controlling power using stop mode (1) 2-214 Mitsubishi microcomputers Controlling Power Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Key-input interrupt Store the registers Key matrix scan b7 b0 Port P10 register [Address 03F416] P10 Key scan data 1110, 1101, 1011, 0111 Decision of key-input data b7 b0 0000 Port P10 register [Address 03F416] P10 Key scan data Restore the registers REIT instruction Figure 3.7.4. Set-up procedure of controlling power using stop mode (2) 2-215 Mitsubishi microcomputers Controlling Power Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 3.8 Controlling Power Using Wait Mode Overview The following are steps for controling power using wait mode. Figure 3.8.1 shows the operation timing, and Figures 3.8.2 to 3.8.4 show the set-up procedure. Use the following peripheral functions: • Timer mode of timer B • Wait mode A flag named “F-WIT” is used in the set-up procedure. The purpose of this flag is to decide whether or not to clear wait mode. If F_WIT = “1” in the main program, the wait mode is entered; if F_WIT = “0”, the wait mode is cleared. Specifications (1) Connect a 32.768-kHz oscillator to XCIN to serve as the timer count source. As interrupts occur every one second, which is a count the timer reaches, the controller returns from wait mode and count the clock using a program. ________ (2) Clear wait mode if a INT0 interrupt request occurs. Operation (1) Switch the system clock from XIN to XCIN to get low-speed mode. _______ (2) Stop XIN and enter wait mode. In this instance, enable the timer B2 interrupt and the INT0 interrupt. (3) When a timer B2 interrupt request occurs (at 1-second intervals), start supplying the BCLK from XCIN. At this time, count the clock within the routine that handles the timer B2 interrupts and enter wait mode again. _______ (4) If a INT0 interrupt occurs, start supplying the BCLK from XCIN. Start the XIN oscillation within _______ the INT0 interrupt, and switch the system clock to XIN. (1) Shift to low-speed mode (2) Stop XIN (3) Timer B2 interrupt XOUT (4) INT0 interrupt XCIN Timer B2 overflow Timer B2 interrupt processing INT0 “H” “L” BCLK High-speed Low-speed Low-speed Low-speed High-speed Low-speed Figure 3.8.1. Operation timing of controling power using wait mode 2-216 Mitsubishi microcomputers Controlling Power Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Main Initial condition b7 b0 0 0 1 0 System clock control register 0 [Address 000616] CM0 WAIT peripheral function clock stop bit 0 : Do not stop peripheral function clock in wait mode XCIN-XCOUT drive capacity select bit Port XC select bit 1 : Functions as XCIN-XCOUT oscillator Main clock (XIN-XOUT) stop bit 0 : Oscillating Main clock divide ratio select bit 0 System clock select bit 0 : XIN-XOUT b7 b0 1 1 00 Timer B2 mode register [Address 039D16] TB2MR Operation mode select bit b1 b0 0 0 : Timer mode Count source select bit b7 b6 1 1 : fC32 (f(XCIN) divided by 32) b15 b8 b7 b0 0316 b7 b0 FF16 Timer B2 register [Address 039516, 039416] TB2 1 Clock prescaler reset flag [Address 038116] CPSRF Rrescaler is reset b7 b0 1 Count start flag [Address 038016] TABSR TB2 start counting b0 b7 0 0 1 Timer B2 interrupt control register [Address 005C16] TB2IC TB2 interrupt priority level INT0 interrupt control register [Address 005D16] INT0IC INT0 interrupt priority level b7 b0 0 0 01 Processor interrupt priority level (IPL) = 0 Interrupt enable flag (I) = 0 Setting interrupt except clearing wait mode TBiIC(i=3 to 5) BCNIC DMiIC (i = 0, 1) KUPIC ADIC SiTIC (i = 0 to 2) b0 SiRIC (i = 0 to 2) 00 TAiIC (i = 0 to 4) Interrupt priority level select bit TBiIC (i = 0, 1) INTiIC (i =3) b2 b1 b0 SiIC/INTjIC (i =4 to 3) 0 0 0 : Interrupt disabled (j=3, 4) INTiIC (i =1 to 2) Interrupt control register [Address 004516 to 004716] [Address 004A16] [Address 004B16, 004C16] [Address 004D16] [Address 004E16] [Address 005116, 005316, 004F16] [Address 005216, 005416, 005016] [Address 005516 to 005916] [Address 005A16, 005B16] [Address 004416] [Address 004816 to 004916] [Address 004816 to 004916] [Address 005E16 to 005F16] b7 0 Continued to the next page Figure 3.8.2. Set-up procedure of controlling power using wait mode (1) 2-217 Mitsubishi microcomputers Controlling Power Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Continued from the previous page Canceling protect b7 b0 1 Protect register [Address 000A 16] PRCR Enables writing to system clock control registers 0 and 1 (address 0006 1 : write-enabled 16 and 0007 16) Switching system clock b7 b0 1 System clock control register 0 [Address 0006 CM0 System clock select bit 1 : X CIN-XCOUT 16] Stopping main clock b7 b0 1 System clock control register 0 [Address 0006 CM0 Main clock (X IN-XOUT) stop bit 1 : Off 16] [F_WIT] = 1 Interrupt enable flag (I flag) “1” WAIT instruction NOP instruction X 4 INT0 interrupt request generated = [F_WIT] : 1 TB2 interrupt request generated ≠ Starting main clock oscillator b7 b0 0 System clock control register 0 [Address 0006 CM0 Main clock (X IN-XOUT) stop bit 0 : On 16] Wait until the main clock has stabilized Switching system clock b7 b0 0 System clock control register 0 [Address 0006 CM0 System clock select bit 0 : X IN-XOUT 16] Figure 3.8.3. Set-up procedure of controlling power using wait mode (2) 2-218 Mitsubishi microcomputers Controlling Power Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER INT0 interrupt Timer B2 interrupt Store the registers Store the registers [F_WIT] = 0 Counting clock Restore the registers REIT instruction Restore the registers REIT instruction Figure 3.8.4. Set-up procedure of controlling power using wait mode (3) 2-219 Mitsubishi microcomputers Controlling Power Applications M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER [ MEMO ] 2-220 Chapter 4 External Buses Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.1 Overview of External Buses Memory and I/O external expansion can be connected to microcomputer easily by using external buses. When memory expansion mode or microprocessor mode is selected for processor mode, some of the pins function as the address bus, the data bus, and as control signals and this makes the external buses be able to operate. When accessing an external area, 8-bit data bus width or 16-bit data bus width can be selected, based on the BYTE pin level. 16-bit width is used to access an internal area, regardless of the level of the BYTE pin. Fix the BYTE pin either to “H” or “L” level. 8-bit and 16-bit data bus widths cannot be used together in an external area. 2-222 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.2 Data Access 4.2.1 Data Bus Width If the voltage level input to the BYTE pin is “H”, the external data bus width becomes 8 bits, and P10 (/ D8) through P17 (/D15) can be used as I/O ports (Figure 4.2.1). If the voltage level input to the BYTE pin is “L”, the external data bus width becomes 16 bits, and P10 (/D8) through P17 (/D15) operate as a data bus (D8 through D15) (Figure 4.2.1). Bus width : 8-bit (BYTE = “H”) Microcomputer P00 to P07 Data bus D0 to D7 External device P10 to P17 I/O port P20 to P27 P30 to P37 Address bus A0 to A15 P40 to P43 Address bus A16 to A19 (Note 1) P44 to P47 Chip select CS0 to CS3 (Note 2) P50 to P52 RD, WRL, WRH / RD, BHE, WR (Note 3) P53 to P57 BCLK, HLDA, HOLD, ALE, RDY Bus width : 16-bit (BYTE = “L”) Microcomputer P00 to P07 Data bus D0 to D7 External device P10 to P17 Data bus D8 to D15 P20 to P27 P30 to P37 Address bus A0 to A15 P40 to P43 Address bus A16 to A19 (Note 1) P44 to P47 Chip select CS0 to CS3 (Note 2) P50 to P52 RD, WRL, WRH / RD, BHE, WR (Note 3) P53 to P57 BCLK, HLDA, HOLD, ALE, RDY Note 1: Can be switched to I/O port using the port P40 to P43 function select bits of processor mode register 0 (address 000416). Note 2: When reset, only CS0 outputs a chip select signal. CS1 through CS3 become input ports. I/O ports can be switched using the CSi output enable bit of the chip select control register (address 000816). Note 3: The feature can be switched using the R/W mode select bit of processor mode register 0 (address 000416). Figure 4.2.1. Level of BYTE pin and external data bus width 2-223 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.2.2 Chip Selects and Address Bus _______ _______ Chip selects (P44/CS0 through P47/CS3) are output in areas resulting from dividing a 1-M byte memory space into four. To use the chip select, the chip select output must be enabled by setting the chip select control register. Figure 4.2.2 shows addresses in which chip selects become active (“L”). Since the extent of the internal area and the external area in memory expansion mode is different from _______ those in microprocessor mode, there is a difference between areas for which CS0 is output. When an internal ROM/RAM area is being accessed, no chip select is output, and the address bus does not change (the address of the external area that was accessed previously is held). 0000016 003FF16 0040016 RAM size Address XXXXX16 00FFF16 013FF16 017FF16 02BFF16 053FF16 ROM size 32K bytes 64K bytes 96K bytes 128K bytes 256K bytes Address YYYYY16 F800016 F000016 E800016 E000016 C000016 SFR area 3K bytes 4K bytes Internal RAM area XXXXX16 5K bytes 10K bytes 20K bytes 03FFF16 0400016 07FFF16 0800016 27FFF16 2800016 Internal reserved area CS3 0400016 to 07FFF16 (16K) CS2 0800016 to 27FFF16 (128K) CS3 0400016 to 07FFF16 (16K) CS2 0800016 to 27FFF16 (128K) CS1 2800016 to 2FFFF16 (32K) 2FFFF16 3000016 CS1 2800016 to 2FFFF16 (32K) CFFFF16 D000016 CS0 3000016 to CFFFF16 (640K) 3000016 to F7FFF16 (800K) Internal reserved area CS0 3000016 to FFFFF16 (832K) YYYYY16 Internal ROM area FFFFF16 Memory expansion mode Microprocessor mode Note : These memory maps show an instance in which PM13 is set to 0; but in the case of products in which the internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which PM13 is set to 1. Figure 4.2.2. Addresses in which chip selects turn active (“L”) 2-224 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Chip select control register b7 b6 b5 b4 b3 b2 b1 b0 Symbol CSR Address 000816 When reset 0116 Bit symbol CS0 CS1 CS2 CS3 CS0W CS1W CS2W CS3W Bit name CS0 output enable bit CS1 output enable bit CS2 output enable bit CS3 output enable bit CS0 wait bit CS1 wait bit CS2 wait bit CS3 wait bit Function 0 : Chip select output disabled (Normal port pin) 1 : Chip select output enabled RW 0 : Wait state inserted 1 : No wait state Figure 4.2.3. Chip select control register 4.2.3 Bus Types The M16C/62A Group has two types of buses: a separate bus where separate pins are used for address output and data input/output and a multiplexed bus where pins are time- multiplexed and switched between address output and data input/output to save the number of pins used. A separate bus is used to access devices such as ROM and RAM which have separate buses. The areas accessed via separate buses can be allocated for programs and data. A multiplexed bus is used to access devices such as ASSPs which have multiplexed buses. The areas accessed via a multiplexed bus can only be allocated for data. Programs cannot be located in these areas. _______ ______ The area accessed via a multiplex bus can be selected from three types of area CS2 area, CS1 area, and entire space by setting the multiplexed bus select bits (bits 4 and 5) of the processor mode register 0 (address 000416). However, the entire space cannot be selected when operating in the microprocessor mode. Areas not accessed via multiplexed bus are accessed through separate buses. When accessing an area set for access via a multiplexed bus the BYTE pin is “H” level, the data bus D0 to D7 is multiplexed with address bus A0 to A7. If the BYTE pin is “L” level, the data bus D0 to D7 is multiplexed with address bus A1 to A8. In either case, the bus is switched between data and address separated only in time. In the latter case, however, the addresses of connected devices are mapped into even addresses (every other addresses) of the M16C/62A. Therefore, be sure to access the M16C/62A's even addresses in length of bytes when accessing a connected device. 4.2.4 R/W Modes _____ The read/write signal that is output when accessing an external area can be selected between the RD/ _______ ______ _____ _________ ________ BHE/WR and the RD/WRH/WRL modes by setting the R/W mode select bit (bit 2) of the processor mode _____ ________ ______ _____ _________ register 0 (address 000416). Use the RD/BHE/WR mode to access a 16-bit wide RAM and the RD/WRH/ ________ WRL mode to access an 8-bit wide RAM. _____ ________ ______ When the M16C/62A is reset, the RD/BHE/WR mode is selected by default. To switch over the R/W _____ ________ ______ _____ _________ ________ mode, change the RD/BHE/WR to the RD/WRH/WRL mode before accessing an external RAM. _____ ________ ______ _____ _________ ________ Refer to the connection examples of RD/BHE/WR and RD/WRH/WRL shown in Section 4.3, "Connection Examples." 2-225 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.3 Connection Examples 4.3.1 16-bit Memory to 16-bit Width Data Bus Connection Example Figure 4.3.1 shows an example of connecting M5M51016BTP (SRAM). In this diagram, when reset the microcomputer starts operating in single-chip mode. Change this mode to memory expansion mode in a program. Microcomputer CNVSS BYTE A0 to A16 WR BHE A16 to A1 CS1 CS1 RD RD A15 to A0 CS OE BC1 BC2 W A0 BHE WR D0 DQ1 to to D15 DQ16 M5M51016BTP D0 to D15 Figure 4.3.1. Example of connecting M5M51016BTP 2-226 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.3.2 8-bit Memory to 16-bit Width Data Bus Connection Example Figure 4.3.2 shows an example of connecting two M5M5278's (SRAM) to a 16-bit data bus.In this diagram, when reset the microcomputer starts operating in single-chip mode. Change this mode to memory expansion mode in a program. Microcomputer CNVSS BYTE D0 to D15 WRH WRL CS0 CS0 RD RD S OE W DQ1 to DQ8 WRL D0 to D7 CS0 RD S OE W WRH A15 A14 to to A1 A0 A15 A14 to to A1 A0 D8 DQ1 to to D15 DQ8 M5M5278D M5M5278D A1 to A15 Figure 4.3.2. Example of connecting two M5M5278's to a 16-bit data bus 2-227 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ________ ________ Figure 4.3.3 shows how to connect two Am29LV008B (flash memory). In 16-bit bus mode, the BHE/WRH ________ pin functions as BHE. When connecting 8-bit flash memory chips to the 16-bit bus, make sure the ________ ______ microcomputer’s WRL pin is connected to the WR pins on both flash memory chips, and that data is written to the flash memory in units of 16 bits beginning with an even address. Microcomputer CNVSS WRL BYTE D0 to D15 CS0 CS0 RD RD CE OE WE DQ0 to DQ7 D0 to D7 CS0 CE RD OE WE D8 DQ0 to to D15 DQ7 A19 A18 to to A1 A0 A19 A18 to to A1 A0 Am29LV008B Am29LV008B A1 to A19 Figure 4.3.3. Example of connecting two Am29LV008B's to a 16-bit data bus 2-228 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.3.3 8-bit Memory to 8-bit Width Data Bus Connection Example Figure 4.3.4 shows an example of connecting two M5M5278's (SRAM) to an 8-bit data bus. In this diagram, when reset the microcomputer starts operating in single-chip mode. Change this mode to memory expansion mode in a program. Microcomputer CNVSS WR D0 to D7 BYTE CS0 CS1 RD CS0 S W DQ1 to DQ8 WR D0 to D7 CS1 RD S OE A14 to A0 W WR RD OE A14 to A0 D0 DQ1 to to D7 DQ8 M5M5278D M5M5278D A0 to A14 Figure 4.3.4. Example of connecting two M5M5278's to an 8-bit data bus 2-229 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.3.4 Two 8-bit and 16-Bit Memory to 16-Bit Width Data Bus Connection Example Figure 4.3.5 shows an example of connecting M5M28F102 (16-bit flash memory) and two M5M5278's (8bit SRAM) to a 16-bit data bus. Microcomputer CNVSS BYTE WRH WRL A1 to A16 A15 A14 W to RD to A1 A0 OE CS1 S A15 to A14 W RD to A1 OE A0 CS1 S CS0 D0 D1 to to D8 D7 D8 D1 to to D8 D15 VPP A15 A16 to to CE A0 A1 D15 to D0 OE WE RD D0 to D15 CS1 CS0 RD M5M5278D M5M5278D M5M28F102 Figure 4.3.5. Example of connection of two 8-bit memories and one 16-bit memory to 16-bit width data bus 2-230 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.3.5 Chip Selects and Address Bus When there are insufficient chip select signals, it is necessary to generate chip selects externally. Figure ________ 4.3.6 shows an example of a connection in which the CS2 (128K bytes) area is divided into four 32K byte areas. Microcomputer CNVSS WR RD A0 to A17 BYTE IC0 IC3 A15 A16 A17 1 2 3 4 5 6 8 16 Y1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 A11 A12 A13 A14 Y1 D7 D6 D5 D4 D3 M5M5278 D0 to D7 A0 to A14 14 13 12 11 Y2 Y3 Y4 CS2 ..... Y4 74HC138 M5M5278 D0 to D7 Memory map 0000016 0800016 IC0 0FFFF16 1000016 17FFF16 1800016 IC2 1FFFF16 2000016 IC3 2FFFF16 3000016 FFFFF16 IC1 CS2 Figure 4.3.6. Chip selects and address bus 2-231 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.4 Connectable Memories 4.4.1 Operation Frequency and Access Time Connectable memories depend upon the BCLK frequency f(BCLK). The frequency of f(BCLK) is equal to that of the BCLK , and is contingent on the oscillator's frequency and on the settings in the system clock select bits (bit 6 of address 000616, and bits 6 and 7 of address 000716). The following are the conditional equations for the connections. Meet these conditions minimally. Figures 4.4.1 and 4.4.2 show the relation between the frequency of BCLK and memory. (1) Read cycle time (tCR)/write cycle time (tCW) Read cycle time (tCR) and write cycle time (tCW) must satisfy the following conditional expressions: • With the Wait option cleared tCR < 109/f(BCLK) and tCW < 109/f(BCLK) • With the Wait option selected tCR < 2 X 109/f(BCLK) and tCW < 2 X 109/f(BCLK) (2) Address access time [ta(A)] Address access time [ta(A)] must satisfy the following conditional expressions: (a) Vcc = 5V • With the Wait option cleared ta(A) < 109/f(BCLK) – 65(ns)* • With the Wait option selected ta(A) < 2 X 109/f(BCLK) – 65(ns)* * 65(ns) = td(BCLK – AD) + tsu(DB – RD) – th(BCLK – RD) = (address output delay time) + (data input setup time) – (RD signal output hold time) (b) Vcc = 3V • With the Wait option cleared ta(A) < 109/f(BCLK) – 140(ns)* • With the Wait option selected ta(A) < 2 X109/f(BCLK) – 140(ns)* * 140(ns) = td(BCLK-AD) + tsu(DB – RD) – th(BCLK – RD) = (address output delay time) + (data input setup time) – (RD signal output hold time) (3) Chip select access time [ta(S)] Chip select access time [ta(S)] must satisfy the following conditional expressions: (a) Vcc = 5V • With the Wait option cleared ta(S) < 109/f(BCLK) – 65(ns)* • With the Wait option selected ta(S) < 2 X109/f(BCLK) – 65(ns)* * 65(ns) = td(BCLK – CS) + tsu(DB – RD) – th(BCLK – RD) = (chip select output delay time) + (data input setup time) – (RD signal output hold time) 2-232 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (b) Vcc = 3V • With the Wait option cleared ta(S) < 109/f(BCLK) – 140(ns)* • With the Wait option selected ta(S) < 2 X109/f(BCLK) – 140(ns)* * 140(ns) = td(BCLK – CS) + tsu(DB – RD) – th(BCLK – RD) = (chip select output delay time) + (data input setup time) – (RD signal output hold time) (4) Output enable time [ta(OE)] Output enable time [ta(OE)] must satisfy the following conditional expressions: (a) Vcc = 5V • With the Wait option cleared ta(OE) < 109/(f(BCLK) X 2) – 45(ns) = tac1(RD-DB) • With the Wait option selected ta(OE) < 3 X 109/(f(BCLK) X 2) – 45(ns) = tac2(RD-DB) (b) Vcc = 3V • With the Wait option cleared ta(OE) < 109/(f(BCLK) X 2) – 90(ns) = tac1(RD-DB) • With the Wait option selected ta(OE) < 3X109/(f(BCLK) X 2) – 90(ns) = tac2(RD-DB) (5) Data setup time [tsu(D)] Data setup time [tsu(D)] must satisfy the following conditional expressions: (a) Vcc = 5V • With the Wait option cleared tsu(D) < 109/(f(BCLK) X 2) – 40(ns)* • With the Wait option selected tsu(D) < 109/f(BCLK) – 40(ns)* * 40(ns) = td(BCLK – DB) – th(BCLK – WR) = (data output delay time) – (WR signal output hold time) (b) Vcc = 3V • With the Wait option cleared tsu(D) < 109/(f(BCLK) X 2) – 80(ns)* • With the Wait option selected tsu(D) < 109/f(BCLK) – 80(ns)* * 80(ns) = td(BCLK – DB) – th(BCLK – WR) = (data output delay time) – (WR signal output hold time) 2-233 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Access time 2500 2000 1935 Without wait With wait 1500 1000 935 935 602 435 268 500 435 185 335 135 268 102 221 78 185 157 60 46 135 35 10 117 26 11 102 18 12 89 12 13 78 6 14 68 2 15 0 1 2 3 4 5 6 7 8 MHz 60 -3 16 9 OE access time 1600 1400 1200 1000 800 705 600 400 200 0 1 2 3 4 5 6 7 8 MHz 9 455 205 121 80 455 330 255 55 205 38 169 26 142 17 121 10 105 5 10 11 91 0 12 1455 Without wait With wait 80 -3 13 70 -7 14 62 -9 15 55 -12 48 -14 16 Data set up time 1200 1000 960 Without wait With wait 800 600 460 400 293 200 210 127 210 85 160 60 127 43 103 31 460 85 23 71 16 60 10 10 11 51 5 12 43 2 37 -2 13 14 31 -4 15 0 1 2 3 4 5 6 7 8 MHz 9 27 -7 16 23 -9 Figure 4.4.1. Relation between the frequency of BCLK and memory (Vcc = 5V) 2-234 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Access time 2,000 1860 1,500 Without wait With wait 1,000 860 860 500 360 527 360 193 110 260 60 5 MHz 6 193 27 7 146 3 110 -15 82 -29 9 10 60 -40 0 1 2 3 4 8 OE access time 1600 1400 1200 1000 800 660 600 400 200 0 1 2 3 4 5 MHz 410 160 76 35 410 285 210 10 6 -7 -18 7 8 -27 9 160 124 97 76 -34 60 -40 10 1410 Without wait With wait Data set up time 1,000 920 800 Without wait With wait 600 400 420 420 253 200 170 87 0 1 2 3 4 5 MHz 6 170 45 120 20 87 3 -9 7 8 -18 9 63 45 31 -24 10 20 -30 Figure 4.4.2. Relation between the frequency of BCLK and memory (Vcc = 3V) 2-235 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.4.2 Connecting Low-Speed Memory To connect memory with long access time [ta(A)], either decrease the frequency of BCLK or set a soft________ ware wait. Using the RDY feature allows you to connect memory having the timing that precludes connection though you set software wait. (1) Using software wait Set software wait by using either of bit 7 (PM17) of processor mode register 1 or bits 4 through 7 (CS0W through CS3W) of the chip select control register. With software wait set, if an address space is accessed in which a separate bus is selected, the bus cycle results in two cycles of BCLK; if an address space is accessed in which a multiplex bus is selected, the bus cycle results in three cycles of BCLK. If bit 7 (PM17) of processor mode register 1 is set to “Wait selected”, the microcomputer accesses every area with this option in effect. If bit 7 (PM17) of processor mode register 1 is set to “Wait cleared”, the Wait option can be either selected or cleared, chip select by chip select, by setting bits 4 through 7 (CS0W through CS3W) of the chip select control register. Figures 4.4.3 through 4.4.5 show relation of processor mode and the wait bit (PM17, CSiW). In case of M30620MAA Single-chip mode (When, PM17 = “0”) 0000016 0040016 SFR area Internal RAM area 0000016 BCLK X 2 BCLK X 1 Single-chip mode (When, PM17 = “1”) SFR area Internal RAM area BCLK X 2 BCLK X 2 0040016 02C0016 02C0016 E800016 Internal ROM area FFFFF16 BCLK X 1 E800016 Internal ROM area FFFFF16 BCLK X 2 Figure 4.4.3. Relation of processor mode and the wait bit (PM17, CSiW) (1) 2-236 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In case of M30620MAA Memory expansion mode When, PM17 = “0” PM04, PM05 = “00” CS0 = “1” CS3 = “1” CS0W = “0” CS3W = “1” 0000016 SFR area 0040016 02C0016 0400016 0800016 1000016 CS3 external area Separate bus BCLK X 1 BCLK X 2 BCLK X 1 Memory expansion mode When, PM17 = “1” PM04, PM05 = “00” CS0 = “1” CS3 = “1” CS0W = “0” CS3W = “1” 0000016 SFR area 0040016 02C0016 0400016 0800016 1000016 CS3 external area Separate bus BCLK X 2 BCLK X 2 BCLK X 2 Internal RAM area Internal RAM area 3000016 CS0 external area D000016 E800016 Internal ROM area FFFFF16 Separate bus BCLK X 2 3000016 CS0 external area D000016 E800016 Separate bus BCLK X 2 BCLK X 1 Internal ROM area FFFFF16 BCLK X 2 Memory expansion mode When, PM17 = “0” PM04, PM05 = “10” CS0 = “1” CS2 = “1” CS0W = “0” CS2W = “0” 0000016 SFR area 0040016 02C0016 0400016 0800016 CS2 external area 2800016 Multiplex bus BCLK X 3 BCLK X 2 BCLK X 1 Memory expansion mode When, PM17 = “1” PM04, PM05 = “10” CS0 = “1” CS2 = “1” CS0W = “0” CS2W = “0” 0000016 SFR area 0040016 02C0016 0400016 0800016 CS2 external area 2800016 Multiplex bus BCLK X 3 BCLK X 2 BCLK X 2 Internal RAM area Internal RAM area 3000016 CS0 external area D000016 E800016 Internal ROM area FFFFF16 Separate bus BCLK X 2 3000016 CS0 external area D000016 E800016 Separate bus BCLK X 2 BCLK X 1 Internal ROM area BCLK X 2 FFFFF16 Figure 4.4.4. Relation of processor mode and the wait bit (PM17, CSiW) (2) 2-237 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In case of M30620MAA Microprocessor mode When, PM17 = “0” PM04, PM05 = “00” CS0 = “1” CS3 = “1” CS0W = “0” CS3W = “1” 0000016 0040016 02C0016 0400016 0800016 1000016 CS3 external area SFR area Internal RAM area BCLK X 2 BCLK X 1 Microprocessor mode When, PM17 = “1” PM04, PM05 = “00” CS0 = “1” CS3 = “1” CS0W = “0” CS3W = “1” 0000016 0040016 02C0016 SFR area Internal RAM area BCLK X 2 BCLK X 2 Separate bus BCLK X 1 0400016 0800016 1000016 CS3 external area Separate bus BCLK X 2 3000016 3000016 CS0 external area Separate bus BCLK X 2 CS0 external area Separate bus BCLK X 2 FFFFF16 FFFFF16 Microprocessor mode When, PM17 = “0” PM04, PM05 = “10” CS0 = “1” CS2 = “1” CS0W = “0” CS2W = “0” 0000016 0040016 02C0016 0400016 0800016 CS2 external area 2800016 BCLK X 2 BCLK X 1 Microprocessor mode When, PM17= “1” PM04, PM05 = “10” CS0 = “1” CS2 = “1” CS0W = “0” CS2W = “0” 0000016 0040016 02C0016 0400016 SFR area Internal RAM area SFR area Internal RAM area BCLK X 2 BCLK X 2 Multiplex bus BCLK X 3 0800016 CS2 external area 2800016 Multiplex bus BCLK X 3 3000016 3000016 CS0 external area Separate bus BCLK X 2 CS0 external area Separate bus BCLK X 2 FFFFF16 FFFFF16 Figure 4.4.5. Relation of processor mode and the wait bit (PM17, CSiW) (3) 2-238 Mitsubishi microcomputers External Buses ________ M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (2) RDY function usage ________ To use the RDY function, set a software wait. ________ ________ The RDY function operates when the BCLK signal falls with the RDY pin at “L”; the bus does not vary for 1 BCLK, and the state at that moment is held. ________ ________ The RDY function holds the state of bus for the period in which the RDY pin is at “L”, and releases it ________ ________ when the BCLK signal falls with the RDY pin at “H”. Figure 4.4.6 shows an example of RDY circuit that holds the state of bus for 1 BCLK. BCLK S CK 1Q S CK 2Q RDY D R CS0 RD 1Q D R 2Q • Timings in separate bus BCLK CS0 RD 1Q 2Q RDY (1) • Timings in multiplex bus BCLK CS0 RD 1Q 2Q RDY (2) (1) (2) (1) (2) (1) (2) (1) RDY accepted (2) RDY cleared The state of data bus and that of address bus are held for the period between (1) and (2). ________ Figure 4.4.6. Example of RDY circuit holding state of bus for 1 BCLK 2-239 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.4.3 Connectable Memories Connectable memories and their maximum frequencies are given here; M16C/62A group maximum frequency is 16MHz (without the wait) for Vcc=5V, 10MHz (with the one wait) for Vcc=3V (1) Flash memories (Read only mode) (a) 3V without wait Maximum frequency (MHz) 3.57 Model No. M5M29GB/T160BVP-80 (b) 3V with wait Maximum frequency (MHz) 8.33 Model No. M5M29GB/T160BVP-80 (2) SRAM (a) 3V without wait Maximum frequency (MHz) 5.12 Model No. M5M54R08AJ-12 M5M54R16AJ,ATP-12 (b) 3V with wait Maximum frequency (MHz) 10.0 Model No. M5M54R08AJ-12 M5M54R16AJ,ATP-12 2-240 Mitsubishi microcomputers External Buses __________ _________ M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 4.5 Releasing an External Bus (HOLD input and HLDA output) The Hold feature is to relinquish the address bus, the data bus, and the control bus on M16C/62A side in line with the Hold request from the bus master other than M16C/62A when the two or more bus masters share the address bus, the data bus, and the control bus. The Hold feature is effective only in memory expansion mode and microprocessor mode. The sequence of using the Hold feature may be: __________ 1. The external bus master turns the input level of the HOLD terminal to “L”. 2. When M16C/62A becomes ready to relinquish buses, each bus becomes high-impedance state at the falling edge of BCLK. __________ 3. The HLDA terminal becomes “L” at the rising edge of the next BCLK. 4. The external bus master uses a bus. 5. When the external bus master finishes using a bus, the external bus master returns the input level of __________ the HOLD terminal to “H”. __________ 6. The output from HLDA terminal becomes “H” at the rising edge of the next BCLK. 7. Each bus returns from the high-impedance state to the former state at the falling edge of the next BCLK. __________ As given above, each bus invariably gets in the high-impedance state while the HLDA output is “L”. Also, M16C/62A does not relinquish buses during a bus cycle. That is, if a Hold request comes in during a bus __________ cycle, the HLDA output become “L” after that bus cycle finishes. In the Hold state, the state of each terminal becomes as follows. • Address bus A0 to A19 High-impedance state. The case in which A16 to A19 are used as ports P40 to P43 (64K byte address space) and the case in which A9 to A19 are used as ports P31 to P37 and P40 to P43 (multiplex for the whole area) in microprocessor mode and in memory expansion mode too fall under this category. • Data bus D0 to D15 High-impedance state. The case in which D8 to D15 are used as ports P10 to P17 (8-bit external bus width) and the case in which D0 to D15 are used as ports P00 to P07 and P10 to P17 (multiplex for the whole area) in microprocessor mode and in memory expansion mode too fall under this category. _____ ______ ________ _________ ________ • RD, WR, WRL, WRH, BHE High-impedance state. • ALE An internal clock signal having the same phase as BCLK is output. _______ _______ • CS0 to CS3 High-impedance state. The case in which ports are selected by the chip selection control register too falls under this category. Figure. 4.5.1 shows an example of relinquishing external buses. 2-241 Mitsubishi microcomputers External Buses M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER BCLK HOLD HLDA Indeterminate ALE CSn ADi DBi HiZ RD/WR Bus released HiZ HiZ HiZ (1) (2) (3) (4) (1) An “L” level is input to the HOLD pin. (2) HOLD is detected. (3) The CPU releases the bus. (4) An “L” is output to the HLDA pin. (5) An “H” is input to the HOLD pin. (6) An “H” is output to the HLDA pin. (7) The CPU not releases the bus. (8) The CPU resumes using the bus. Figure 4.5.1. Example of releasing the external bus (5)(6) (7) (8) 4.6 Precautions for External Bus (1) The external ROM version can operate only in the microprocessor mode, so be sure to perform the following: • Connect the CNVSS pin to Vcc. 2-242 Chapter 5 External ROM Version Mitsubishi microcomputers M16C / 62A Group External ROM SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The external ROM version can operate only in the microprocessor mode. Functions of the external ROM version differ from those of the mask ROM version in the following. therefore, only the differences are described in this chapter: For the other functions, refer to chapters 1 to 4. • Memory map • Operated in only microprocessor mode 2-244 Mitsubishi microcomputers M16C / 62A Group External ROM SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 5.1 Pin Configuration Figures 5.1.1 and 5.1.2 show the pin configrations (top view). PIN CONFIGURATION (top view) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P10/D8 P11/D9 P12/D10 P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 A0(/D0/-) A1(/D1/D0) A2(/D2/D1) A3(/D3/D2) A4(/D4/D3) A5(/D5/D4) A6(/D6/D5) A7(/D7/D6) Vss A8(/-/D7) Vcc A9 A10 A11 A12 A13 A14 A15 P40/A16 P41/A17 P42/A18 P43/A19 D7 D6 D5 D4 D3 D2 D1 D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 23 45 6 7 8 M16C/62A group (external ROM version) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P44/CS0 P45/CS1 P46/CS2 P47/CS3 WRL/WR WRH/BHE RD BCLK HLDA HOLD ALE RDY P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Note: P70 and P71 are N channel open-drain output pin. P96/ANEX1/SOUT4 P95/ANEX0/CLK4 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V P72/CLK2/TA1OUT/V P71/RxD2/SCL/TA0IN/TB5IN (Note) P70/TXD2/SDA/TA0OUT (Note) Package: 100P6S-A Figure 5.1.1. Pin configuration (top view) 2-245 Mitsubishi microcomputers M16C / 62A Group External ROM SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (top view) P13/D11 P14/D12 P15/D13/INT3 P16/D14/INT4 P17/D15/INT5 A0(/D0/-) A1(/D1/D0) A2(/D2/D1) A3(/D3/D2) A4(/D4/D3) A5(/D5/D4) A6(/D6/D5) A7(/D7/D6) Vss A8(/-/D7) Vcc A9 A10 A11 A12 A13 A14 A15 P40/A16 P41/A17 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P12/D10 P11/D9 P10/D8 D7 D6 D5 D4 D3 D2 D1 D0 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVSS P100/AN0 VREF AVcc P97/ADTRG/SIN4 P96/ANEX1/SOUT4 P95/ANEX0/CLK4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 M16C/62A group (external ROM version) P42/A18 P43/A19 P44/CS0 P45/CS1 P46/CS2 P47/CS3 WRL/WR WRH/BHE RD BCLK HLDA HOLD ALE RDY P60/CTS0/RTS0 P61/CLK0 P62/RxD0 P63/TXD0 P64/CTS1/RTS1/CLKS1 P65/CLK1 P66/RxD1 P67/TXD1 P70/TXD2/SDA/TA0OUT (Note) P71/RxD2/SCL/TA0IN/TB5IN (Note) P72/CLK2/TA1OUT/V 12 345 67 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P94/DA1/TB4IN P93/DA0/TB3IN P92/TB2IN/SOUT3 P91/TB1IN/SIN3 P90/TB0IN/CLK3 BYTE CNVss P87/XCIN P86/XCOUT RESET XOUT VSS XIN VCC P85/NMI P84/INT2 P83/INT1 P82/INT0 P81/TA4IN/U P80/TA4OUT/U P77/TA3IN P76/TA3OUT P75/TA2IN/W P74/TA2OUT/W P73/CTS2/RTS2/TA1IN/V Package: 100P6Q-A Note: P70 and P71 are N channel open-drain output pin. Figure 5.1.2. Pin configuration (top view) 2-246 Mitsubishi microcomputers M16C / 62A Group External ROM SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 5.2 Pin Description Tables 5.2.1 and 5.2.2 show the pin description. Table 5.2.1. Pin Description (1) Pin name VCC, VSS CNVSS RESET XIN XOUT Signal name Power supply input CNVSS Reset input Clock input Clock output Input Input Input Output I/O type Function Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin. Connect this pin to VCC. A “L” on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. This pin selects the width of an external data bus. A 16-bit width is selected when this input is “L”; an 8-bit width is selected when this input is “H”. This input must be fixed to either “H” or “L”. This pin is a power supply input for the A-D converter. Connect this pin to VCC. This pin is a power supply input for the A-D converter. Connect this pin to VSS. Input This pin is a reference voltage input for the A-D converter. When set as a separate bus, these pins input and output data (D0–D7). This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set as a separate bus, these pins input and output data (D8–D15). These pins output 8 low-order address bits (A0–A7). If the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (D0–D7) and output 8 low-order address bits (A0–A7) separated in time by multiplexing. If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D0–D6) and output address (A1–A7) separated in time by multiplexing. They also output address (A0). These pins output 8 middle-order address bits (A8–A15). If the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (D7) and output address (A8) separated in time by multiplexing. They also output address (A9–A15). This is an 8-bit I/O port equivalent to P1. These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip select signals used to specify an access space. A16–A19 are 4 highorder address bits. BYTE External data bus width select input Analog power supply input Analog power supply input Reference voltage input Data bus I/O port P1 Input AVCC AVSS VREF D0 to D7 P10 to P17 Input/output Input/output D8 to D15 A0 to A7 A0/D0 to A7/D7 Data bus Address bus Address bus/ data bus Input/output Output Input/output A0 , A1/D0 to A7/D6 A8 to A15 A8/D7, A9 to A15 P40 to P47 CS0 to CS3, A16 to A19 Address bus Address bus/ data bus I/O port P4 Output Input/output Output Input/output Output Input/output Output Output 2-247 Mitsubishi microcomputers M16C / 62A Group External ROM SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 5.2.2. Pin Description (2) Pin name WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY Signal name WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD, ALE, RDY I/O type Output Output Output Output Output Input Output Input Function Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control. WRL, WRH, and RD selecte With a 16-bit external data bus, data is written to even addresses when the WRL signal is “L” and to the odd addresses when the WRH signal is “L”. Data is read when RD is “L”. WR, BHE, and RD selected Data is written when WR is “L”. Data is read when RD is “L”. Odd addresses are accessed when BHE is “L”. Use this mode when using an 8-bit external data bus. While the input level at the HOLD pin is “L”, the microcomputer is placed in the hold state. While in the hold state, HLDA outputs a “L" level. ALE is used to latch the address. While the input level of the RDY pin is “L”, the microcomputer is in the ready state. This is an 8-bit I/O port equivalent to P1. The port can be set to have or not have a pull-up resistor in units of four bits by software. Pins in this port also function as UART0 and UART1 I/O pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as timer A0–A3, timer B5, or UART2 I/O pins as selected by software. P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P86 and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P86 (XCOUT pin) and P87 (XCIN pin). P85 is an input-only port that also functions for NMI. The NMI interrupt is generated when the input at this pin changes from “H” to “L”. The NMI function cannot be canceled using software. The pull-up cannot be set for this pin. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as SI/O3,4 I/O pin, timer B0–B2 input pins, D-A converter output pins, A-D converter’s extended input pins, or A-D trigger input pins as selected by software. This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A-D converter input pins. Furthermore, P104–P107 also function as input pins for the key input interrupt function. P60 to P67 I/O port P6 Input/output P70 to P77 P80 to P84, P86, P87, P85 I/O port P7 I/O port P8 Input/output Input/output Input/output Input/output I/O port P85 Input P90 to P97 I/O port P9 Input/output P100 to P107 I/O port P10 Input/output 2-248 Mitsubishi microcomputers M16C / 62A Group External ROM SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 5.3 Memory Map Figure 5.3.1 shows the memory map. Figures 5.3.2 and 5.3.3 show the SFR memory map. 0000016 SFR area For detail, see Figures 5.3.2 and 5.3.3 FFE0016 0040016 Internal Ram area XXXXX16 Special page vector table Internal reserved area 0400016 FFFDC16 External ROM area FFFFF16 FFFFF16 RAM size 10K byte 3K byte XXXXX16 02BFF16 013FF16 Underfined instruction Overfiow BRK instruction Address match Single step Watchdog timer DBC NMI Reset Figure 5.3.1. Memory map 2-249 Mitsubishi microcomputers M16C / 62A Group External ROM SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Chip select control register (CSR) Address match interrupt enable register (AIER) Protect register (PRCR) 004416 004516 004616 004716 004816 004916 004A16 004B16 INT3 interrupt control register (INT3IC) Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) SI/O4 interrupt control register (S4IC) INT5 interrupt control register (INT5IC) SI/O3 interrupt control register (S3IC) INT4 interrupt control register (INT4IC) Bus collision detection interrupt control register (BCNIC) Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Address match interrupt register 0 (RMAD0) 004C16 004D16 004E16 004F16 005016 005116 005216 DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC) UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC) Address match interrupt register 1 (RMAD1) 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 DMA0 source pointer (SAR0) 005F16 006016 006116 006216 Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) Timer A4 interrupt control register (TA4IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) INT2 interrupt control register (INT2IC) DMA0 destination pointer (DAR0) 006316 006416 006516 DMA0 transfer counter (TCR0) DMA0 control register (DM0CON) 032A16 032B16 032C16 032D16 032E16 DMA1 source pointer (SAR1) 032F16 033016 033116 033216 DMA1 destination pointer (DAR1) 033316 033416 033516 033616 033716 033816 033916 DMA1 transfer counter (TCR1) DMA1 control register (DM1CON) 033A16 033B16 033C16 033D16 033E16 033F16 Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 5.3.2. SFR memory map (1) 2-250 Mitsubishi microcomputers M16C / 62A Group External ROM SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 Timer B3, 4, 5 count start flag (TBSR) Timer A1-1 register (TA11) Timer A2-1 register (TA21) Timer A4-1 register (TA41) Three-phase PWM control register 0(INVC0) Three-phase PWM control register 1(INVC1) Three-phase output buffer register 0(IDB0) Three-phase output buffer register 1(IDB1) Dead time timer(DTT) Timer B2 interrupt occurrence frequency set counter(ICTB2) 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 Count start flag (TABSR) Clock prescaler reset flag (CPSRF) One-shot start flag (ONSF) Trigger select register (TRGSR) Up-down flag (UDF) Timer A0 register (TA0) Timer A1 register (TA1) Timer A2 register (TA2) Timer A3 register (TA3) Timer A4 register (TA4) Timer B0 register (TB0) Timer B1 register (TB1) Timer B2 register (TB2) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR) Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5) Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register (TB5MR) Interrupt cause select register (IFSR) SI/O3 transmit/receive register (S3TRR) SI/O3 control register (S3C) SI/O3 bit rate generator (S3BRG) SI/O4 transmit/receive register (S4TRR) SI/O4 control register (S4C) SI/O4 bit rate generator (S4BRG) 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 UART0 transmit/receive mode register (U0MR) UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB) UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1) UART0 receive buffer register (U0RB) UART1 transmit/receive mode register (U1MR) UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB) UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1) UART1 receive buffer register (U1RB) UART transmit/receive control register 2 (UCON) UART2 special mode register 2(U2SMR2) UART2 special mode register (U2SMR) UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG) UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB) 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 DMA0 request cause select register (DM0SL) DMA1 request cause select register (DM1SL) CRC data register (CRCD) CRC input register (CRCIN) Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 5.3.3. SFR memory map (2) 2-251 Mitsubishi microcomputers M16C / 62A Group External ROM SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7) A-D control register 2 (ADCON2) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) D-A register 1 (DA1) D-A control register (DACON) Port P1 register (P1) Port P1 direction register (PD1) Port P4 register (P4) Port P4 direction register (PD4) Port P6 register (P6) Port P7 register (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 register (P8) Port P9 register (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 register (P10) Port P10 direction register (PD10) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Port control register (PCR) Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write. Figure 5.3.4. SFR memory map (3) 2-252 Mitsubishi microcomputers M16C / 62A Group External ROM SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 5.4 Processor Mode The external ROM version is operated only in microprocessor mode, so be sure to perform the following: • Connect CNVSS pin to VCC. Figure 5.4.1 shows the processor mode register 0. Processor mode register 0 (Note) b7 b6 b5 b4 b3 b2 b1 b0 11 Symbol PM0 Address 000416 When rese 0316 Bit symbol PM00 PM01 PM02 PM03 Bit name Processor mode bit b1 b0 Function 0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Must not be set 1 1: Microprocessor mode 0 : RD,BHE,WR 1 : RD,WRH,WRL The device is reset when this bit is set to “1”. The value of this bit is “0” when read. b5 b4 RW R/W mode select bit Software reset bit PM04 PM05 PM06 Multiplexed bus space select bit 0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Must not be set 0 : Address output 1 : Port function (Address is not output) 0 : BCLK is output 1 : BCLK is not output (Pin is left floating) Port P40 to P43 function select bit BCLK output disable bit PM07 Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register. Figure 5.4.1. Processor mode register 0 2-253 Mitsubishi microcomputers M16C / 62A Group Appendix 1 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Appendix 1 Check Sheet The following check sheet was created based on items which had been the source of problems in the past. We recommend you refer to the check sheet when troubleshooting. Are you making use of Technical News? For the latest copy of Technical News, contact an authorized dealer. Checks regarding register initial settings Has the initial setting been made in the interrupt stack pointer (ISP) at the top of the program? Has the initial setting been made in the user stack pointer (USP)? (Only if using the USP) Does the USP overlap the ISP area? (Only if using the USP) Is interrupt enabled after setting the ISP and USP? Is the top address of the variable interrupt vector table set in the interrupt table register (INTB)? Is interrupt enabled after setting the INTB? Has the initial setting been made in the frame base register (FB)? (Only if using the FB) Has the initial setting been made in the stack base register (SB)? (Only if using the SB) Checks regarding the internal memory Does the RAM capacity used in the program exceed the RAM capacity of the microcomputer? Does the ROM capacity used in the program exceed the ROM capacity of the microcomputer? Checks regarding the protect register Is writing enabled in the protect register (address 000A16) before writing in the system clock control register (addresses 000616 and 000716)? Is writing enabled in the protect register before writing in the processor mode register (addresses 000416 and 000516)? Is writing enabled in the protect register before writing in the port P9 direction register (address 03F316)? Is writing effectuated in the port P9 direction register by the next instruction after writing is enabled in the protect register? Does not an interrupt generate between the instruction writing is enabled in the protect register and the instruction writing in the port P9 direction register? 2-254 Mitsubishi microcomputers M16C / 62A Group Appendix 1 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Does not instruction DMA transfer occur between the instruction writing is enabled in the protect register and the instruction writing in the port P9 direction register starts? Is writing enabled in the protect register before writing in the SI/Oi (i=3,4) control register (address 036216, 036616)? Is writing effectuated in the SI/Oi (i=3,4) control register by the next instruction after writing is enabled in the protect register? Does not an interrupt generate between the instruction writing is enabled in the protect register and the instruction writing in the SI/Oi (i=3,4) control register? Does not instruction DMA transfer occur between the instruction writing is enabled in the protect register and the instruction writing in the SI/Oi (i=3,4) control register starts? Checks regarding the timer Is the timer started after a value is set in the timer register? Checks regarding Interrupt When rewrite the interrupt register, do so at a point that does not generate the interruput request? Checks regarding low voltage and low power consumption When using at low voltage, have you checked recommended operating conditions and changed the wait bit (address 000516, bit 7) to “1”? Does the oscillator to which the count source is going to be switched be oscillating stably, before the count source for BCLK can be changed from XIN to XCIN or vice versa? In the low power consumption mode, does not current flow from Vref when the Vref connection bit (bit 5 in address 03D716) is set? Is not voltage level of port floating in the low power consumption mode? Checks regarding A-D converter Have you selected other than fAD (no dividing) for øAD when using the A-D converter at VCC = 2.7V to 4.0V? Have you selected no sample & hold function when using the A-D converter at VCC = 2.7V to 4.0V? Have you selected 8-bit mode when using the A-D converter at VCC = 2.7V to 4.0V? Does øAD use it by less than 10MHZ? 2-255 Mitsubishi microcomputers M16C / 62A Group Appendix 2 Hexadecimal instruction CODE table SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D7 to D4 D3 to D0 0000 0 0000 0 BRK 0001 1 AND.B:S R0H,R0L 0010 2 ADD.B:S R0H,R0L ADD.B:S dsp:8[SB],R0L ADD.B:S dsp:8[FB],R0L ADD.B:S abs16,R0L ADD.B:S R0L,R0H ADD.B:S dsp:8[SB],R0H ADD.B:S dsp:8[FB],R0H ADD.B:S abs16,R0H SUB.B:S R0H,R0L SUB.B:S 0011 3 MOV.B:S R0H,A0 MOV.B:S dsp:8[SB],A0 MOV.B:S dsp:8[FB],A0 MOV.B:S abs16,A0 MOV.B:S R0Çk,A1 MOV.B:S dsp:8[SB],A1 MOV.B:S dsp:8[FB],A1 MOV.B:S abs16,A1 CMP.B:S R0H,R0L CMP.B:S 0100 4 BCLR:S 0,11[SB] BCLR:S 1,11[SB] BCLR:S 2,11[SB] BCLR:S 3,11[SB] BCLR:S 4,11[SB] BCLR:S 5,11[SB] BCLR:S 6,11[SB] BCLR:S 7,11[SB] BSET:S 0,11[SB] BSET:S 1,11[SB] BSET:S 2,11[SB] BSET:S 3,11[SB] BSET:S 4,11[SB] BSET:S 5,11[SB] BSET:S 6,11[SB] BSET:S 7,11[SB] 0101 5 BNOT:S 0,11[SB] BNOT:S 1,11[SB] BNOT:S 2,11[SB] BNOT:S 3,11[SB] BNOT:S 4,11[SB] BNOT:S 5,11[SB] BNOT:S 6,11[SB] BNOT:S 7,11[SB] BTST:S 0,11[SB] BTST:S 1,11[SB] BTST:S 2,11[SB] BTST:S 3,11[SB] BTST:S 4,11[SB] BTST:S 5,11[SB] BTST:S 6,11[SB] BTST:S 7,11[SB] 0110 6 JMP.S label JMP.S label JMP.S label JMP.S label JMP.S label JMP.S label JMP.S label JMP.S label JGEU/C label JGTU label JEQ/Z label JN label JLTU/NC label JLEU label JNE/JNZ label JPZ label 0111 7 MULU.B src,dest MULU.W src,dest MOV.B:G src,dest MOV.W:G src,dest CODE_74 0001 1 MOV.B:S R0L,dsp:8[SB] AND.B:S dsp:8[SB],R0L AND.B:S dsp:8[FB],R0L AND.B:S abs16,R0L AND.B:S R0L,R0H 0010 2 MOV.B:S R0L,dsp:8[FB] 0011 3 MOV.B:S R0L,abs16 0100 4 NOP 0101 5 MOV.B:S R0H,dsp:8[SB] AND.B:S dsp:8[SB],R0H AND.B:S dsp:8[FB],R0H AND.B:S abs16,R0H OR.B:S R0H,R0L OR.B:S dsp:8[SB],R0L OR.B:S dsp:8[FB],R0L OR.B:S abs16,R0L OR.B:S R0L,R0H OR.B:S dsp:8[SB],R0H OR.B:S dsp:8[FB],R0H OR.B:S abs16,R0H CODE_75 0110 6 MOV.B:S R0H,dsp:8[FB] CODE_76 0111 7 MOV.B:S R0H,abs16 CODE_77 1000 8 MOV.B:S R0H,R0L MUL.B src,dest MUL.W src,dest CODE_7A 1001 9 MOV.B:S dsp:8[SB],R0L dsp:8[SB],R0L dsp:8[SB],R0L SUB.B:S dsp:8[FB],R0L SUB.B:S abs16,R0L SUB.B:S R0L,R0H SUB.B:S CMP.B:S dsp:8[FB],R0L CMP.B:S abs16,R0L CMP.B:S R0L,R0H CMP.B:S 1010 A MOV.B:S dsp:8[FB],R0L 1011 B MOV.B:S abs16,R0L CODE_7B 1100 C MOV.B:S R0L,R0H CODE_7C 1101 D MOV.B:S dsp:8[SB],R0H CODE_7D dsp:8[SB],R0H dsp:8[SB],R0H SUB.B:S CMP.B:S 1110 E MOV.B:S dsp:8[FB],R0H CODE_7E dsp:8[FB],R0H dsp:8[FB],R0H SUB.B:S abs16,R0H CMP.B:S abs16,R0H 1111 F MOV.B:S abs16,R0H The next instruction is arranged in each CODE. CODE_74 : STE, MOV, PUSH, NEG, ROT, NOT, LDE, POP, SHL, SHA CODE_75 : STE, MOV, PUSH, NEG, ROT, NOT, LDE, POP, SHL, SHA CODE_76 : TST, XOR, AND, OR, ADD, SUB, ADC, SBB, CMP, DIVX, ROLC, RORC, DIVU, DIV, ADCF, ABS CODE_77 : TST, XOR, AND, OR, ADD, SUB, ADC, SBB, CMP, DIVX, ROLC, RORC, DIVU, DIV, ADCF, ABS CODE_7A : XCHG, LDC CODE_7B : XCHG, STC CODE_7C : MOVDir, MULU, MUL, EXTS, STC, DIVU, DIV, PUSH, DIVX, DADD, DSUB, DADC, DSBB, SMOVF, SMOVB, SSTR, ADD, LDCTX, RMPA, ENTER CODE_7D : JMPI, JSRI, MULU, MUL, PUSHA, LDIPL, ADD, JCnd, BMCnd, DIVU, DIV, PUSH, DIVX, DADD, DSUB, DADC, DSBB, SMOVF, SMOVB, SSTR, STCTX, RMPA, EXITD, WAIT CODE_7E : BTSTC, BMCnd, BNTST, BAND, BNAND, BOR, BNOR, BCLR, BSET, BNOT, BTST, BXOR, BNXOR CODE_EB:SHL,FSET,FCLR,MOVA,LDC,SHA,PUSHC,POPC,INT 2-256 Mitsubishi microcomputers M16C / 62A Group Appendix 2 Hexadecimal instruction CODE table SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER D7 to D4 D3 to D0 0000 0 1000 8 TST.B src,dest 1001 9 AND.B:G src,dest AND.W:G src,dest POP.B:S R0L AND.B:S #IMM8,R0H AND.B:S #IMM8,R0L AND.B:S 1010 A ADD.B:G src,dest ADD.W:G src,dest MOV.W:S #IMM,A0 INC.B R0H INC.B R0L INC.B dsp:8[SB] INC.B dsp:8[FB] INC.B abs16 SUB.B:G src,dest SUB.W:G src,dest MOV.W:S #IMM,A1 DEC.B R0H DEC.B R0L DEC.B dsp:8[SB] DEC.B dsp:8[FB] DEC.B abs16 1011 B ADC.B src,dest ADC.w src,dest INC.W A0 MOV.B:Z #0,R0H MOV.B:Z #0,R0L MOV.B:Z #0,dsp:8[SB] MOV.B:Z #0,dsp:8[FB] MOV.B:Z #0,abs16 SBB.B src,dest SBB.W src,dest INC.W A1 NOT.B:S R0H NOT.B:S R0L NOT.B:S dsp:8[SB] NOT.B:S dsp:8[FB] NOT.B:S abs16 1100 C CMP.B:G src,dest CMP.W:G src,dest PUSH.W:S A0 MOV.B:S #IMM8,R0H MOV.B:S #IMM8,R0L MOV.B:S #IMM8,dsp:8[SB] MOV.B:S #IMM8,dsp:8[FB] MOV.B:S #IMM8,abs16 ADD.B:Q #IMM,dest ADD.W:Q #IMM,dest PUSH.W:S A1 STZ #IMM8,R0H STZ #IMM8,R0L STZ 1101 D CMP.B:Q #IMM,dest CMP.W:Q #IMM,dest POP.W:S A0 STNZ #IMM8,R0H STNZ #IMM8,R0L STNZ #IMM8,dsp:8[SB] STNZ #IMM8,dsp:8[FB] STNZ #IMM8,abs16 MOV.B:Q #IMM,dest MOV.W:Q #IMM,dest POP.W:S A1 STZX #IMM8,#IMM8,R0H STZX #IMM8,#IMM8,R0L STZX 1110 E ROT.B #IMM,dest ROT.W #IMM,dest MOV.B:S #IMM,A0 CMP.B:S #IMM8,R0H CMP.B:S #IMM8,R0L CMP.B:S #IMM8,dsp:8[SB] CMP.B:S #IMM8,dsp:8[FB] CMP.B:S #IMM8,abs16 SHL.B #IMM,dest SHL.W #IMM,dest MOV.B:S #IMM,A1 CODE_EB 1111 F SHA.B #IMM,dest SHA.W #IMM,dest DEC.W A0 RTS 0001 1 TST.W src,dest 0010 2 PUSH.B:S R0L 0011 3 ADD.B:S #IMM8,R0H 0100 4 ADD.B:S #IMM8,R0L JMP.W label JSR.W label INTO 0101 5 ADD.B:S #IMM8,dsp:8[SB] #IMM8,dsp:8[SB] 0110 6 ADD.B:S AND.B:S #IMM8,dsp:8[FB] #IMM8,dsp:8[FB] 0111 7 ADD.B:S #IMM8,abs16 1000 8 XOR.B src,dest 1001 9 XOR.W src,dest 1010 A PUSH.B:S R0H 1011 B SUB.B:S #IMM8,R0H 1100 C SUB.B:S #IMM8,R0L 1101 D SUB.B:S AND.B:S #IMM8,abs16 OR.B:G src,dest OR.W:G src,dest POP.B:S R0H OR.B:S #IMM8,R0H OR.B:S #IMM8,R0L OR.B:S ADJNZ.B #IMM,dest,label ADJNZ.W #IMM,dest,label DEC.W A1 REIT PUSHM src POPM dest JMPS #IMM8 JSRS #IMM8 JMP.A label JSR.A label JMP.B label UND #IMM8,dsp:8[SB] #IMM8,dsp:8[SB] 1110 E SUB.B:S OR.B:S #IMM8,dsp:8[SB] #IMM8,#IMM8,dsp:8[SB] STZ STZX #IMM8,dsp:8[FB] #IMM8,dsp:8[FB] 1111 F SUB.B:S #IMM8,abs16 OR.B:S #IMM8,abs16 #IMM8,dsp:8[FB] #IMM8,#IMM8,dsp:8[FB] STZ #IMM8,abs16 STZX #IMM8,#IMM8,abs16 2-257 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The following shows the register to select pin and the setting value. Refer to the table as follows. Pin function I/O direction of pin function See page for peripheral function Contents of pin function Pin name P96/ANEX1/SOUT4 Function selection Pin No. 1 (FP) 99 (GP) Setting register Remarks Page 1-149 1-145 1-163 1-163 1-163 1-168 1-170 1-151 1-151 1-146 1-146 6,3F3h ANEX1 SOUT4 P96 P96 P96 I AD extend input 0 0 0 0 1 6,3F3h 3,3FEh 7,3D7h 6,3D7h 3,366h 2,366h 3,3FEh 0 0 0 1 X 7,3D7h 1 0 0 0 0 6,3D7h 0 0 0 0 0 3,366h 0 1 0 0 0 2,366h X 0 X X X O Serial I/O data output I I Port input (No pulled high) Port input (Pulled high) O Port output Port P96 direction register P94 to P97 pull-up control register External op-amp connection mode bit of A-D contol register 1 External op-amp connection mode bit of A-D contol register 1 SI/O4 port select bit of SI/O4 control register SOUT4 output disable bit of SI/O4 control register Setting value of bit 0 : Set to “0” 1 : Set to “1” X : Can be “0” or “1” See page for register A symbol to show a bit to select pin function (bit No., address) 2-258 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P96/ANEX1/SOUT4 Function selection Pin No. 1 (FP) 99 (GP) Setting register Remarks Page 1-149 1-145 1-163 1-163 1-163 1-168 1-170 1-151 1-151 1-146 1-146 6,3F3h ANEX1 SOUT4 P96 P96 P96 I AD extend input 0 0 0 0 1 6,3F3h 3,3FEh 7,3D7h 6,3D7h 3,366h 2,366h 3,3FEh 0 0 0 1 X 7,3D7h 1 0 0 0 0 6,3D7h 0 0 0 0 0 3,366h 0 1 0 0 0 2,366h X 0 X X X O Serial I/O data output I I Port input (No pulled high) Port input (Pulled high) O Port output Port P96 direction register P94 to P97 pull-up control register External op-amp connection mode bit of A-D contol register 1 External op-amp connection mode bit of A-D contol register 1 SI/O4 port select bit of SI/O4 control register SOUT4 output disable bit of SI/O4 control register Pin name P95/ANEX0/CLK4 Function selection Pin No. 2 (FP) 100 (GP) Setting register Remarks Page 1-149 1-149 1-145 1-145 1-163 1-163 1-163 1-168 1-170 1-151 1-151 1-146 1-146 5,3F3h ANEX0 ANEX0 SCLK4 SCLK4 P95 P95 P95 I AD extend input 0 0 0 0 0 0 1 5,3F3h 3,3FEh 7,3D7h 6,3D7h 3,366h 6,366h 3,3FEh 0 0 0 0 0 1 X 7,3D7h 0 1 0 0 0 0 0 6,3D7h 1 1 0 0 0 0 0 3,366h 0 0 1 1 0 0 0 6,366h X X 1 0 X X X Output when op-amp connection O mode O Serial clock output I I I Serial clock input Port input (No pulled high) Port input (Pulled high) O Port output Port P95 direction register P94 to P97 pull-up control register External op-amp connection mode bit of A-D control register 1 External op-amp connection mode bit of A-D control register 1 SI/O4 port select bit of SI/O4 control register Synchronous clock select bit of SI/O4 control register Pin name P94/DA1/TB4IN Function selection Pin No. 3 (FP) 1 (GP) Setting register Remarks Page 1-159 1-90 1-163 1-163 1-163 1-168 1-170 1-160 1-90 4,3F3h DA1 TB4IN P94 P94 P94 O DA output I I I Count source input Port input (No pulled high) Port input (Pulled high) 0 0 0 0 1 4,3F3h 3,3FEh 3,3FEh 0 0 0 1 X 1,3DCh 1 0 0 0 0 7,35Ch 0 0 0 0 0 O Port output Port P94 direction register P94 to P97 pull-up control register 1,3DCh D-A1 output enable bit of D-A control register 7,35Ch Event clock select bit ot timer B4 mode register 2-259 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P93/DA0/TB3IN Function selection Pin No. 4 (FP) 2 (GP) Setting register Remarks Page 1-159 1-90 1-163 1-163 1-163 1-168 1-170 1-160 1-90 3,3F3h DA0 TB3IN P93 P93 P93 O DA output I I I Count source input Port input (No pulled high) Port input (Pulled high) 0 0 0 0 1 3,3F3h 2,3FEh 0,3DCh 7,35Bh 2,3FEh 0 0 0 1 X 0,3DCh 1 0 0 0 0 7,35Bh 0 0 0 0 0 O Port output Port P93 direction register P90 to P93 pull-up control register D-A0 output enable bit of D-A control register Event clock select bit ot timer B3 mode register Pin name P92/TB2IN/SOUT3 Function selection Pin No. 5 (FP) 3 (GP) Setting register Remarks Page 1-90 1-145 1-163 1-163 1-163 1-168 1-170 1-90 1-146 1-146 2,3F3h TB2IN SOUT3 P92 P92 P92 I Count source input 0 0 0 0 1 2,3F3h 2,3FEh 7,39Dh 3,362h 2,362h 2,3FEh 0 0 0 1 X 7,39Dh 0 0 X X X 3,362h 0 1 0 0 0 2,362h X 0 X X X O Serial I/O data output I I Port input (No pulled high) Port input (Pulled high) O Port output Port P92 direction register P90 to P93 pull-up control register Event clock select bit ot timer B2 mode register SI/O3 port select bit of SI/O3 control register SOUT3 output disable bit of SI/O3 control register Pin name P91/TB1IN/SIN3 Function selection Pin No. 6 (FP) 4 (GP) Setting register Remarks Page 1-90 1-145 1-163 1-163 1-163 1-168 1-170 1-90 1-146 1,3F3h TB1IN SIN3 P91 P91 P91 I I I I Count source input Serial I/O data input Port input (No pulled high) Port input (Pulled high) 0 0 0 0 1 1,3F3h 2,3FEh 7,39Ch 3,362h 2,3FEh 0 0 0 1 X 7,39Ch 0 0 X X X 3,362h 0 1 0 0 0 O Port output Port P91 direction register P90 to P93 pull-up control register Event clock select bit of timer B1 mode register SI/O3 port select bit of SI/O3 control register 2-260 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P90/TB0IN/CLK3 Function selection Pin No. 7 (FP) 5 (GP) Setting register Remarks Page 1-90 1-145 1-145 1-163 1-163 1-163 1-168 1-170 1-90 1-146 1-146 0,3F3h TB0IN CLK3 CLK3 P90 P90 P90 I Count source input 0 0 0 0 0 1 0,3F3h 2,3FEh 7,39Bh 3,362h 6,362h 2,3FEh 0 0 0 0 1 X 7,39Bh 0 X X X X X 3,362h 0 1 1 0 0 0 6,362h X 1 0 X X X O Serial clock output I I I Serial clock input Port input (No pulled high) Port input (Pulled high) O Port output Port P90 direction register P90 to P93 pull-up control register Event clock select bit of timer B0 mode register SI/O3 port select bit of SI/O3 control register Synchronous clock select bit of SI/O3 control register Pin name P87/XCIN Function selection Pin No. 10 (FP) 8 (GP) Setting register Remarks Page 1-36 1-163 1-163 1-163 1-168 1-170 1-39 7,3F2h XCIN P87 P87 P87 I I I Sub clock input Port input (No pulled high) Port input (Pulled high) 0 0 0 1 7,3F2h 1,3FEh 4,006h 1,3FEh 0 0 1 X 4,006h 1 0 0 0 O Port output Port P87 direction register P84 to P87 pull-up control register Port Xc select bit of system clock control register 0 Pin name P86/XCOUT Function selection Pin No. 11 (FP) 9 (GP) Setting register Remarks Page 1-36 1-163 1-163 1-163 1-168 1-170 1-39 6,3F2h XCOUT P86 P86 P86 O Sub clock output I I Port input (No pulled high) Port input (Pulled high) 0 0 0 1 6,3F2h 1,3FEh 4,006h 1,3FEh 0 0 1 X 4,006h 1 0 0 0 O Port output Port P86 direction register P84 to P87 pull-up control register Port Xc select bit of system clock control register 0 2-261 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P84/INT2 Function selection Pin No. 18 (FP) 16 (GP) Setting register Remarks Page 1-61 1-163 1-163 1-163 1-168 1-170 4,3F2h INT2 P84 P84 P84 I I I Interrupt input Port input (No pulled high) Port input (Pulled high) 0 0 0 1 4,3F2h 1,3FEh 1,3FEh X 0 1 X Port P84 direction register P84 to P87 pull-up control register 1 O Port output Remark 1: Interrupt request bit generates by state change of a port, not by setting value of register. Pin name P83/INT1 Function selection Pin No. 19 (FP) 17 (GP) Setting register Remarks Page 1-61 1-163 1-163 1-163 1-168 1-170 4,3F2h INT1 P83 P83 P83 I I I Interrupt input Port input (No pulled high) Port input (Pulled high) 0 0 0 1 3,3F2h 0,3FEh 1,3FEh X 0 1 X Port P83 direction register P80 to P83 pull-up control register 1 O Port output Remark 1: Interrupt request bit generates by state change of a port, not by setting value of register. Pin name P82/INT0 Function selection Pin No. 20 (FP) 18 (GP) Setting register Remarks Page 1-61 1-163 1-163 1-163 1-168 1-170 2,3F2h INT0 P82 P82 P82 I I I Interrupt input Port input (No pulled high) Port input (Pulled high) 0 0 0 1 2,3F2h 0,3FEh 0,3FEh X 0 1 X Port P82 direction register P80 to P83 pull-up control register 1 O Port output Remark 1: Interrupt request bit generates by state change of a port, not by setting value of register. Pin name P81/TA4IN/U Function selection Pin No. 21 (FP) 19 (GP) Setting register Remarks Page 1-78 1-78 1-78 1-96 1-163 1-163 1-163 1-168 1-170 1-82 1-82 1-80 1-96 1,3F2h TA4IN TA4IN TA4IN U P81 P81 P81 I I I Gate function level input Count source input External trigger input 0 0 0 X 0 0 1 1,3F2h 0,3FEh 7,383h 6,383h 4,39Ah 2,348h 0,3FEh X X X X 0 1 X 7,383h 0 0 0 X X X X 6,383h 0 0 0 X X X X 4,39Ah 1 X 1 X X X X 2,348h 0 0 0 1 0 0 0 O U phase output I I Port input (No pulled high) Port input (Pulled high) O Port output Port P81 direction register P80 to P83 pull-up control register Timer A4 event/trigger select bit of trigger select register Timer A4 event/trigger select bit of trigger select register Bit 4 of timer A4 mode register Three phase mode select bit 2-262 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P80/TA4OUT/U Function selection Pin No. 22 (FP) 20 (GP) Setting register Remarks Page 1-78 1-78 1-78 1-96 1-163 1-163 1-163 1-168 1-170 1-80 1-80 1-81 1-96 0,3F2h TA4OUT TA4OUT TA4OUT U P80 P80 P80 O Pulse output I I Up/down polarity select input Two-phase pulse signal input X 0 0 X 0 0 1 0,3F2h 0,3FEh 4,39Ah 2,39Ah 7,384h 2,348h 0,3FEh X X X X 0 1 X 4,39Ah X 1 1 X X X X 2,39Ah 1 0 0 X 0 0 0 7,384h 0 0 1 X 0 0 0 2,348h 0 0 0 1 0 0 0 1 O U phase output I I Port input (No pulled high) Port input (Pulled high) O Port output Port P80 direction register P80 to P83 pull-up control register Bit 4 of timer A4 mode register Bit 2 of timer A4 mode register Timer A4 two-phase pulse signal processing select bit of up/down flag Three phase mode select bit Remark 1: Can not be use when processing two-phase pulse signal. Pin name P77/TA3IN Function selection Pin No. 23 (FP) 21 (GP) Setting register Remarks Page 1-78 1-78 1-78 1-163 1-163 1-163 1-168 1-170 1-82 1-82 1-80 7,3EFh TA3IN TA3IN TA3IN P77 P77 P77 I I I I I Gate function level input Count source input External trigger input Port input (No pulled high) Port input (Pulled high) 0 0 0 0 0 1 7,3EFh 7,3FDh 5,383h 4,383h 4,399h 7,3FDh X X X 0 1 X 5,383h 0 0 0 X X X 4,383h 0 0 0 X X X 4,399h 1 X 1 X X X O Port output Port P77 direction register P74 to P77 pull-up control register Timer A3 event/trigger select bit of trigger select register Timer A3 event/trigger select bit of trigger select register Bit 4 of timer A3 mode register Pin name P76/TA3OUT Function selection Pin No. 24 (FP) 22 (GP) Setting register Remarks Page 1-78 1-78 1-78 1-163 1-163 1-163 1-168 1-170 1-80 1-80 1-81 6,3EFh TA3OUT TA3OUT TA3OUT P76 P76 P76 O Pulse output I I I I Up/down polarity select input Two-phase pulse signal input Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 6,3EFh 7,3FDh 4,399h 2,399h 6,384h 7,3FDh X X X 0 1 X 4,399h X 1 1 X X X 2,399h 1 0 0 0 0 0 6,384h 0 0 1 0 0 0 1 O Port output Port P76 direction register P74 to P77 pull-up control register Bit 4 of timer A3 mode register Bit 2 of timer A3 mode register Timer A3 two-phase pulse signal processing select bit of up/down flag Remark 1: Can not be use when processing two-phase pulse signal. 2-263 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P75/TA2IN/W Function selection Pin No. 25 (FP) 23 (GP) Setting register Remarks Page 1-78 1-78 1-78 1-96 1-163 1-163 1-163 1-168 1-170 1-82 1-82 1-80 1-96 5,3EFh TA2IN TA2IN TA2IN W P75 P75 P75 I I I Gate function level input Count source input External trigger input 0 0 0 0 0 0 1 5,3EFh 7,3FDh 3,383h 2,383h 4,398h 2,348h 7,3FDh X X X 0 0 1 X 3,383h 0 0 0 X X X X 2,383h 0 0 0 X X X X 4,398h 1 X 1 X X X X 2,348h 0 0 0 1 0 0 0 O W phase output I I Port input (No pulled high) Port input (Pulled high) O Port output Port P75 direction register P74 to P77 pull-up control register Timer A2 event/trigger select bit of trigger select register Timer A2 event/trigger select bit of trigger select register Bit 4 of timer A2 mode register Three phase mode select bit Pin name P74/TA2OUT/W Function selection Pin No. 26 (FP) 24 (GP) Setting register Remarks Page 1-78 1-78 1-78 1-96 1-163 1-163 1-163 1-168 1-170 1-80 1-80 1-81 1-96 4,3EFh TA2OUT TA2OUT TA2OUT W P74 P74 P74 O Pulse output I I Up/down polarity select input Two-phase pulse signal input X 0 0 X 0 0 1 4,3EFh 7,3FDh 4,398h 2,398h 5,384h 2,348h 7,3FDh X X X X 0 1 X 4,398h X 1 1 X X X X 2,398h 1 0 0 X 0 0 0 5,384h 0 0 1 X 0 0 0 2,348h 0 0 0 1 0 0 0 1 O W phase output I I Port input (No pulled high) Port input (Pulled high) O Port output Port P74 direction register P74 to P77 pull-up control register Bit 4 of timer A2 mode register Bit 2 of timer A2 mode register Timer A2 two-phase pulse signal processing select bit of up/down flag Three phase mode select bit Remark 1: Can not be use when processing two-phase pulse signal. 2-264 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P73/CTS2/RTS2/TA1IN/V Function selection Pin No. 27 (FP) 25 (GP) Setting register Remarks Page 1-7 8 1-78 1-78 1 1 1-10 8 1-108 1-96 1-163 1-163 1-163 1-168 1-170 1-82 1-82 1-80 1-114 1-114 1-96 3,3EFh TA1IN TA1IN TA1IN RTS2 CTS2 V P73 P73 P73 I I I Gate function level input Count source input External trigger input 0 0 0 X 0 X 0 0 1 3,3EFh 6,3FDh 1,383h 0,383h 4,397h 4,37Ch 2,37Ch 2,348h 6,3FDh X X X X X X 0 1 X 1,383h 0 0 0 X X X X X X 0,383h 0 0 0 X X X X X X 4,397h 1 X 1 X X X X X X 4,37Ch X X X 0 0 X X X X 2,37Ch X X X 1 0 X X X X 2,348h 0 0 0 0 0 1 0 0 0 O RTS output I CTS input O V phase output I I Port input (No pulled high) Port input (Pulled high) O Port output Port P73 direction register P70 to P73 pull-up control register Bit 1 of trigger select register Bit 0 of trigger select register Bit 4 of timer A1 mode register CTS/RTS disable bit of UART2 transmit/receive control register 0 CTS/RTS select bit of UART2 transmit/receive control register 0 Three phase mode select bit Remark 1 : Set serial I/O enabled by serial I/O mode select bit of UART2 transmit/receive mode register. Pin name P72/CLK2/TA1OUT/V Function selection Pin No. 28 (FP) 26 (GP) Setting register Remarks Page 1-78 1-78 1 1,2 1-108 1-108 1-96 1-163 1-163 1-163 1-168 1-170 1-80 1-80 1-113 1-96 2,3EFh TA1OUT TA1OUT CLK2 CLK2 V P72 P72 P72 O Pulse output I I Up/down polarity select input Serial I/O clock input X 0 0 X X 0 0 1 2,3EFh 6,3FDh 4,397h 2,397h 3,378h 2,348h 6,3FDh X X 0 0 X 0 1 X 4,397h X 1 X X X X X X 2,397h 1 0 X X X 0 0 0 3,378h X X 1 0 X X X X 2,348h 0 0 0 0 1 1 0 0 O Serial I/O clock output O V phase output I I Port input (No pulled high) Port input (Pulled high) O Port output Port P72 direction register P70 to P73 pull-up control register Bit 4 of timer A1 mode register Bit 2 of timer A1 mode register Internal/external clock select bit of UART2 transmit/receive mode register Three phase mode select bit Remark 1: Set serial I/O enabled by serial I/O mode select bit of UART2 transmit/receive mode register. Remark 2: It become I/O port when UART mode selected. 2-265 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P71/RXD2/TA0IN/TB5IN/SCL Function selection Pin No. 29 (FP) 27 (GP) Setting register Remarks Page 1-78 1-78 1-78 1-90 1 1 1 1-137 1-137 1-108 1-163 1-163 1-168 1-170 1-82 1-82 1-80 1-90 1-137 1-127 1,3EFh TA0IN TA0IN TA0IN TB5IN SCL SCL RXD2 P71 P71 I I I I Gate function level input Count source input External trigger input Count source input 0 0 0 0 0 0 0 0 1 1,3EFh 6,3FDh 7,382h 6,382h 4,396h 7,35Dh 0,377h 3,378h 6,3FDh X X X 0 0 0 0 0 X 7,382h 0 0 0 X X X X X X 6,382h 0 0 0 X X X X X X 4,396h 1 X 1 X X X X X X 7,35Dh 0 0 0 1 0 0 0 0 0 0,377h 0 0 0 X 1 1 0 0 0 3,378h X X X 0 0 1 X X X O IIC clock output I I I IIC clock input Serial I/O data input Port input O Port output Port P71 direction register P70 to P73 pull-up control register Bit 7 of one-shot start flag Bit 6 of one-shot start flag Bit 4 of timer A0 mode register Event clock select bit of timer B5 mode register IIC mode select bit Internal /external clock select bit Remark 1 : Set serial I/O enabled by serial I/O mode select bit of UART2 transmit/receive mode register. Pin name P70/TXD2/TA0OUT/SDA Function selection Pin No. 30 (FP) 28 (GP) Setting register Remarks Page 1-78 1-78 1, 2 1 1, 2 1-108 1-137 1-137 1-163 1-163 1-168 1-170 1-80 1-80 1-137 1-141 0,3EFh TA0OUT TA0OUT TXD2 SDA SDA P70 P70 O Pulse output I Up/down polarity select input X 0 X 0 0 0 1 0,3EFh 6,3FDh 4,396h 2,396h 0,377h 6,376h 6,3FDh X X X 0 0 0 X 4,396h X 1 X 0 0 0 0 2,396h 1 0 X 0 0 0 0 0,377h 0 0 0 1 1 0 0 6,376h X X X 1 0 X X O Serial I/O data output I IIC data input O IIC data output I Port input O Port output Port P70 direction register P70 to P73 pull-up control register Bit 4 of timer A0 mode register Bit 2 of timer A0 mode register IIC mode select bit SDA output stop bit Remark 1: Set serial I/O enabled by serial I/O mode select bit of UART2 transmit/receive mode register. Remark 2: N channel open-drain output. 2-266 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P67/TXD1 Function selection Pin No. 31 (FP) 29 (GP) Setting register Remarks Page 1-108 1-163 1-163 1-163 1-168 1-170 7,3EEh TXD1 P67 P67 P67 O Serial I/O data output I I Port input (No pulled high) Port input (Pulled high) X 0 0 1 7,3EEh 5,3FDh 5,3FDh X 0 1 X Port P67 direction register P64 to P67 pull-up control register 1, 2 O Port output Remark 1: Set serial I/O enabled by serial I/O mode select bit of UART1 transmit/receive mode register. Remark 2: Can be selected CMOS output or N channel open-drain output. Pin name P66/RXD1 Function selection Pin No. 32 (FP) 30 (GP) Setting register Remarks Page 1-108 1-163 1-163 1-163 1-168 1-170 6,3EEh RXD1 P66 P66 P66 I I I Serial I/O data input Port input (No pulled high) Port input (Pulled high) 0 0 0 1 6,3EEh 5,3FDh 5,3FDh X 0 1 X Port P66 direction register P64 to P67 pull-up control register 1 O Port output Remark 1: Set serial I/O enabled by serial I/O mode select bit of UART1 transmit/receive mode register. Pin name P65/CLK1 Function selection Pin No. 33 (FP) 31 (GP) Setting register Remarks Page 1-10 8 1-108 1-163 1-163 1-163 1-168 1-170 1-113 5,3EEh CLK1 CLK1 P65 P65 P65 I Serial I/O clock input 0 X 0 0 1 6,3EEh 5,3FDh 3,3A8h 5,3FDh X X 0 1 X 3,3A8h 1 0 X X X 1 1, 2 O Serial I/O clock output I I Port input (No pulled high) Port input (Pulled high) O Port output Port P65 direction register P64 to P67 pull-up control register Internal/external clock select bit of UART1 transmit/receive mode register Remark 1: Set serial I/O enabled by serial I/O mode select bit of UART1 transmit/receive mode register. Remark 2: It become I/O port when UART mode selected. 2-267 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P64/CTS1/RTS1/CLKS1 Function selection Pin No. 34 (FP) 32 (GP) Setting register Remarks Page 1-108 1-108 1-108 1-163 1-163 1-163 1-168 1-170 1-116 1-116 1-114 1-114 1-113 4,3EEh CLKS1 RTS1 CTS1 P64 P64 P64 O Serial I/O clock output O RTS output I I I CTS input Port input (No pulled high) Port input (Pulled high) X X 0 0 0 1 4,3EEh 5,3FDh 5,3B0h 4,3B0h 4,3ACh 2,3ACh 3,3A8h 5,3FDh X X X 0 1 X 5,3B0h 1 0 0 X X X 4,3B0h 1 0 0 X X X 4,3ACh 1 0 0 X X X 2,3ACh X 1 0 X X X 3,3A8h 0 X X X X X 1 1 1 O Port output Port P64 direction register P64 to P67 pull-up control register CLK/CLKS select bit 1 of UART transmit/receive control register 2 CLK/CLKS select bit 0 of UART transmit/receive control register 2 CTS/RTS disable bit of UART1 transmit/receive control register 0 CTS/RTS function select bit of UART1 transmit/receive control register 0 Internal/external clock select bit of UART1 transmit/receive mode register Remark 1: Set serial I/O enabled by serial I/O mode select bit of UART1 transmit/receive mode register. Pin name P63/TXD0 Function selection Pin No. 35 (FP) 33 (GP) Setting register Remarks Page 1-108 1-163 1-163 1-163 1-168 1-170 3,3EEh TXD0 P63 P63 P63 O Serial I/O data output I I Port input (No pulled high) Port input (Pulled high) X 0 0 1 3,3EEh 4,3FDh 4,3FDh X 0 1 X Port P63 direction register P60 to P63 pull-up control register 1, 2 O Port output Remark 1: Set serial I/O enabled by serial I/O mode select bit of UART0 transmit/receive mode register. Remark 2: Can be selected CMOS output or N channel open-drain output. Pin name P62/RXD0 Function selection Pin No. 36 (FP) 34 (GP) Setting register Remarks Page 1-108 1-163 1-163 1-163 1-168 1-170 2,3EEh RXD0 P62 P62 P62 I I I Serial I/O data input Port input (No pulled high) Port input (Pulled high) 0 0 0 1 2,3EEh 4,3FDh 4,3FDh X 0 1 X Port P62 direction register P60 to P63 pull-up control register 1 O Port output Remark 1: Set serial I/O enabled by serial I/O mode select bit of UART0 transmit/receive mode register. 2-268 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P61/CLK0 Function selection Pin No. 37 (FP) 35 (GP) Setting register Remarks Page 1-108 1-108 1-163 1-163 1-163 1-168 1-170 1-113 1,3EEh CLK0 CLK0 P61 P61 P61 I Serial I/O clock input 0 X 0 0 1 1,3EEh 4,3FDh 3,3A0h 4,3FDh X X 0 1 X 3,3A0h 1 0 X X X 1 1, 2 O Serial I/O clock output I I Port input (No pulled high) Port input (Pulled high) O Port output Port P61 direction register P60 to P63 pull-up control register Internal/external clock select bit of UART0 transmit/receive mode register Remark 1: Set serial I/O enabled by serial I/O mode select bit of UART0 transmit/receive mode register. Remark 2: It become I/O port when UART mode selected. Pin name P60/CTS0/RTS0 Function selection Pin No. 38 (FP) 36 (GP) Setting register Remarks Page 1-108 1-108 1-163 1-163 1-163 1-168 1-170 1-114 1-114 0,3EEh RTS0 CTS0 P60 P60 P60 O RTS output I I I CTS input Port input (No pulled high) Port input (Pulled high) X 0 0 0 1 0,3EEh 4,3FDh 4,3A4h 2,3A4h 4,3FDh X X 0 1 X 4,3A4h 0 0 X X X 2,3A4h 1 0 X X X 1 1 O Port output Port P60 direction register P60 to P63 pull-up control register CTS/RTS disable bit of UART0 transmit/receive control register 0 CTS/RTS function select bit of UART0 transmit/receive control register 0 Remark 1: Set serial I/O enabled by serial I/O mode select bit of UART0 transmit/receive mode register. Pin name P57/RDY/CLKOUT Function selection Pin No. 39 (FP) 37 (GP) Setting register Remarks Page 1-40 X 0 0 0 1 1-32 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-39 1-39 7,3EBh CLKOUT RDY P57 P57 P57 O CLKOUT output I I I RDY input Port input (No pulled high) Port input (Pulled high) X X 0 0 1 7,3EBh 3,3FDh 1,004h 0,004h 1,006h 0,006h 3,3FDh X X 0 1 X 1,004h 0 X 0 0 0 0,004h 0 1 0 0 0 1,006h 0,006h Except 00 X 0 0 0 O Port output Port P57 direction register P54 to P57 pull-up control register Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Clock output function select bit of system clock control register 0 Clock output function select bit of system clock control register 0 Remark 1: When the user is using the RDY, the wait bit of relevant chip selects must be set to "0". 2-269 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P56/ALE Function selection Pin No. 40(FP) 38 (GP) Setting register Remarks Page 1-31 1-163 1-163 1-163 1-168 1-170 1-23 1-23 6,3EBh ALE P56 P56 P56 O ALE output I I Port input (No pulled high) Port input (Pulled high) X 0 0 1 6,3EBh 3,3FDh 1,004h 0,004h 3,3FDh X 0 1 X 1,004h X 0 0 0 0,004h 1 0 0 0 O Port output Port P56 direction register P54 to P57 pull-up control register Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P55/HOLD Function selection Pin No. 41 (FP) 39 (GP) Setting register Remarks Page 1-33 1-163 1-163 1-163 1-168 1-170 1-23 1-23 5,3EBh HOLD P55 P55 P55 I I I HOLD input Port input (No pulled high) Port input (Pulled high) X 0 0 1 5,3EBh 3,3FDh 1,004h 0,004h 3,3FDh X 0 1 X 1,004h X 0 0 0 0,004h 1 0 0 0 O Port output Port P55 direction register P54 to P57 pull-up control register Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P54/HLDA Function selection Pin No. 42 (FP) 40 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 4,3EBh HLDA P54 P54 P54 O HLDA output I I Port input (No pulled high) Port input (Pulled high) X 0 0 1 4,3EBh 3,3FDh 1,004h 0,004h 3,3FDh X 0 1 X 1,004h X 0 0 0 0,004h 1 0 0 0 O Port output Port P54 direction register P54 to P57 pull-up control register Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 2-270 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P53/BCLK Function selection Pin No. 43 (FP) 41 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 3,3EBh BCLK P53 P53 P53 O BCLK output I I Port input (No pulled high) Port input (Pulled high) X 0 0 1 3,3EBh 2,3FDh 7,004h 1,004h 0,004h 2,3FDh X 0 1 X 7,004h 0 X X X 1,004h X 0 0 0 0,004h 1 0 0 0 O Port output Port P53 direction register P50 to P53 pull-up control register BCLK output disable bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P52/RD Function selection Pin No. 44 (FP) 42 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 2,3EBh RD P52 P52 P52 O RD output I I Port input (No pulled high) Port input (Pulled high) X 0 0 1 2,3EBh 2,3FDh 1,004h 0,004h 2,3FDh X 0 1 X 1,004h X 0 0 0 0,004h 1 0 0 0 O Port output Port P52 direction register P50 to P53 pull-up control register Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P51/WRH/BHE Function selection Pin No. 45 (FP) 43 (GP) Setting register Remarks Page 1-28 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1,3EBh BHE WRH P51 P51 P51 O BHE output O WRH output I I Port input (No pulled high) Port input (Pulled high) X X 0 0 1 1,3EBh 2,3FDh 2,004h 1,004h 0,004h 2,3FDh X X 0 1 X 2,004h 0 1 X X X 1,004h X X 0 0 0 0,004h 1 1 0 0 0 O Port output Port P51 direction register P50 to P53 pull-up control register R/W mode select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P50/WRL/WR Function selection Pin No. 46 (FP) 44 (GP) Setting register Remarks Page 1-28 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 0,3EBh WR WRL P50 P50 P50 O WR output O WRL output I I Port input (No pulled high) Port input (Pulled high) X X 0 0 1 0,3EBh 2,3FDh 2,004h 1,004h 0,004h 2,3FDh X X 0 1 X 2,004h 0 1 X X X 1,004h X X 0 0 0 0,004h 1 1 0 0 0 O Port output Port P50 direction register P50 to P53 pull-up control register R/W select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 2-271 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P47/CS3 Function selection Pin No. 47 (FP) 45 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-29 1-23 1-23 7,3EAh CS3 P47 P47 P47 O Chip select output I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 7,3EAh 1,3FDh 3,008h 1,004h 0,004h 1,3FDh X 0 0 1 1 X X 3,008h 1 X 0 X 0 X 0 1,004h X 0 X 0 X 0 X 0,004h 1 0 1 0 1 0 1 O Port output Port P47 direction register P44 to P47 pull-up control register CS3 output enable bit of chip select control register Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P46/CS2 Function selection Pin No. 48 (FP) 46 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-29 1-23 1-23 6,3EAh CS2 P46 P46 P46 O Chip select output I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 6,3EAh 1,3FDh 2,008h 1,004h 0,004h 1,3FDh X 0 0 1 1 X X 2,008h 1 X 0 X 0 X 0 1,004h X 0 X 0 X 0 X 0,004h 1 0 1 0 1 0 1 O Port output Port P46 direction register P44 to P47 pull-up control register CS2 output enable bit of chip select control register Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P45/CS1 Function selection Pin No. 49 (FP) 47 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-29 1-23 1-23 5,3EAh CS1 P45 P45 P45 O Chip select output I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 5,3EAh 1,3FDh 1,008h 1,004h 0,004h 1,3FDh X 0 0 1 0 X X 1,008h 1 X 0 X 0 X 0 1,004h X 0 X 0 X 0 X 0,004h 1 0 1 0 1 0 1 O Port output Port P45 direction register P44 to P47 pull-up control register CS1 output enable bit of chip select control register Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 2-272 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P44/CS0 Function selection Pin No. 50 (FP) 48 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-29 1-23 1-23 4,3EAh CS0 P44 P44 P44 O Chip select output I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 4,3EAh 1,3FDh 0,008h 1,004h 0,004h 1,3FDh X 0 0 1 0 X X 0,008h 1 X 0 X 0 X 0 1,004h X 0 X 0 X 0 X 0,004h 1 0 1 0 1 0 1 O Port output Port P44 direction register P44 to P47 pull-up control register CS0 output enable bit of chip select control register Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P43/A19 Function selection Pin No. 51 (FP) 49 (GP) Setting register Remarks Page 1-28 1-163 3,3EAh A19 P43 O Address output I Port input (No pulled high) X 0 0 0 0 0 0 1 1 1 3,3EAh 0,3FDh 6,004h 5,004h 4,004h 1,004h 0,004h 0,3FDh X 0 0 0 1 1 1 X X X 6,004h 0 X 0 1 X 0 1 X 0 1 5,004h 4,004h 1,004h X 0 0 X 0 0 X 0 0 X 0,004h 1 0 1 1 0 1 1 0 1 1 Except 11 X X 1 1 Except 11 X X 1 1 Except 11 X X 1 1 Except 11 P43 I Port input (Pulled high) 1-163 P43 O Port output 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-23 Port P43 direction register P40 to P43 pull-up control register Port P40 to P43 function select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P42/A18 Function selection Pin No. 52 (FP) 50 (GP) Setting register Remarks Page 1-28 1-163 2,3EAh A18 P42 O Address output I Port input (No pulled high) X 0 0 0 0 0 0 1 1 1 2,3EAh 0,3FDh 6,004h 5,004h 4,004h 1,004h 0,004h 0,3FDh X 0 0 0 1 1 1 X X X 6,004h 0 X 0 1 X 0 1 X 0 1 5,004h 4,004h 1,004h X 0 0 X 0 0 X 0 0 X 0,004h 1 0 1 1 0 1 1 0 1 1 Except 11 X X 1 1 Except 11 X X 1 1 Except 11 X X 1 1 Except 11 P42 I Port input (Pulled high) 1-163 P42 O Port output 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-23 Port P42 direction register P40 to P43 pull-up control register Port P40 to P43 function select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 2-273 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P41/A17 Function selection Pin No. 53 (FP) 51 (GP) Setting register Remarks Page 1-28 1-163 1,3EAh A17 P41 O Address output I Port input (No pulled high) X 0 0 0 0 0 0 1 1 1 1,3EAh 0,3FDh 6,004h 5,004h 4,004h 1,004h 0,004h 0,3FDh X 0 0 0 1 1 1 X X X 6,004h 0 X 0 1 X 0 1 X 0 1 5,004h 4,004h 1,004h X 0 0 X 0 0 X 0 0 X 0,004h 1 0 1 1 0 1 1 0 1 1 Except 11 X X 1 1 Except 11 X X 1 1 Except 11 X X 1 1 Except 11 P41 I Port input (Pulled high) 1-163 P41 O Port output 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-23 Port P41 direction register P40 to P43 pull-up control register Port P40 to P43 function select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P40/A16 Function selection Pin No. 54 (FP) 52 (GP) Setting register Remarks Page 1-28 1-163 0,3EAh A16 P40 O Address output I Port input (No pulled high) X 0 0 0 0 0 0 1 1 1 0,3EAh 0,3FDh 6,004h 5,004h 4,004h 1,004h 0,004h 0,3FDh X 0 0 0 1 1 1 X X X 6,004h 0 X 0 1 X 0 1 X 0 1 5,004h 4,004h 1,004h X 0 0 X 0 0 X 0 0 X 0,004h 1 0 1 1 0 1 1 0 1 1 Except 11 X X 1 1 Except 11 X X 1 1 Except 11 X X 1 1 Except 11 P40 I Port input (Pulled high) 1-163 P40 O Port output 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-23 Port P40 direction register P40 to P43 pull-up control register Port P40 to P43 function select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P37/A15 Function selection Pin No. 55 (FP) 53 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 7,3E7h A15 P37 P37 P37 O Address output I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 7,3E7h 7,3FCh 5,004h 4,004h 1,004h 0,004h 7,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 Except 11 X 1 0 1 0 0 X 1 0 1 0 0 O Port output 0 0 0 0 0 0 Port P37 direction register P34 to P37 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 2-274 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P36/A14 Function selection Pin No. 56 (FP) 54 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 6,3E7h A14 P36 P36 P36 O Address output I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 6,3E7h 7,3FCh 5,004h 4,004h 1,004h 0,004h 7,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 Except 11 X 1 0 1 0 0 X 1 0 1 0 0 O Port output 0 0 0 0 0 0 Port P36 direction register P34 to P37 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P35/A13 Function selection Pin No. 57 (FP) 55 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 5,3E7h A13 P35 P35 P35 O Address output I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 5,3E7h 7,3FCh 5,004h 4,004h 1,004h 0,004h 7,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 Except 11 X 1 0 1 0 0 X 1 0 1 0 0 O Port output 0 0 0 0 0 0 Port P35 direction register P34 to P37 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P34/A12 Function selection Pin No. 58 (FP) 56 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 4,3E7h A12 P34 P34 P34 O Address output I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 4,3E7h 7,3FCh 5,004h 4,004h 1,004h 0,004h 7,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 Except 11 X 1 0 1 0 0 X 1 0 1 0 0 O Port output 0 0 0 0 0 0 Port P34 direction register P34 to P37 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 2-275 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P33/A11 Function selection Pin No. 59 (FP) 57 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 3,3E7h A11 P33 P33 P33 O Address output I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 3,3E7h 6,3FCh 5,004h 4,004h 1,004h 0,004h 6,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 Except 11 X 1 0 1 0 0 X 1 0 1 0 0 O Port output 0 0 0 0 0 0 Port P33 direction register P30 to P33 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P32/A10 Function selection Pin No. 60 (FP) 58 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 2,3E7h A10 P32 P32 P32 O Address output I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 2,3E7h 6,3FCh 5,004h 4,004h 1,004h 0,004h 6,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 Except 11 X 1 0 1 0 0 X 1 0 1 0 0 O Port output 0 0 0 0 0 0 Port P32 direction register P30 to P33 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 Pin name P31/A9 Function selection Pin No. 61 (FP) 59 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1,3E7h A9 P31 P31 P31 O Address output I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 1,3E7h 6,3FCh 5,004h 4,004h 1,004h 0,004h 6,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 Except 11 X 1 X 1 X 1 X 1 X 1 X 1 O Port output 0 0 0 0 0 0 Port P31 direction register P30 to P33 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 2-276 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P30/A8(/-/D7) Function selection Pin No. 63 (FP) 61 (GP) Setting register Remarks Page 1-28 1-28 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 0,3E7h A8/D7 A8/A8 P30 P30 P30 I/O Multiplexed bus O Multiplexed bus O Address output I I Port input (No pulled high) Port input (Pulled high) X X X X X 0 0 1 0,3E7h 6,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 6,3FCh X X X X X 0 1 X 5,004h 0 1 X 1 0 X X X 4,004h 1 0 1 X 0 X X X 1,004h X X X X X 0 0 0 0,004h 1 1 1 1 1 0 0 0 BYTE L L H H X X X X O Port output Port P30 direction register P30 to P33 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P27/A7(/D7/D6) Function selection Pin No. 65 (FP) 63 (GP) Setting register Remarks Page 1-28 1-28 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 7,3E6h A7/D6 A7/D7 A7 P27 P27 P27 I/O Multiplexed bus I/O Multiplexed bus O Address output I I Port input (No pulled high) Port input (Pulled high) X X X X X 0 0 1 7,3E6h 5,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 5,3FCh X X X X X 0 1 X 5,004h 0 1 X 1 0 X X X 4,004h 1 0 1 X 0 X X X 1,004h X X X X X 0 0 0 0,004h 1 1 1 1 1 0 0 0 BYTE L L H H X X X X O Port output Port P27 direction register P24 to P27 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P26/A6(/D6/D5) Function selection Pin No. 66 (FP) 64 (GP) Setting register Remarks Page 1-28 1-28 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 6,3E6h A6/D5 A6/D6 A6 P26 P26 P26 I/O Multiplexed bus I/O Multiplexed bus O Address output I I Port input (No pulled high) Port input (Pulled high) X X X X X 0 0 1 6,3E6h 5,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 5,3FCh X X X X X 0 1 X 5,004h 0 1 X 1 0 X X X 4,004h 1 0 1 X 0 X X X 1,004h X X X X X 0 0 0 0,004h 1 1 1 1 1 0 0 0 BYTE L L H H X X X X O Port output Port P26 direction register P24 to P27 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin 2-277 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P25/A5(/D5/D4) Function selection Pin No. 67 (FP) 65 (GP) Setting register Remarks Page 1-28 1-28 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 5,3E6h A5/D4 A5/D5 A5 P25 P25 P25 I/O Multiplexed bus I/O Multiplexed bus O Address output I I Port input (No pulled high) Port input (Pulled high) X X X X X 0 0 1 5,3E6h 5,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 5,3FCh X X X X X 0 1 X 5,004h 0 1 X 1 0 X X X 4,004h 1 0 1 X 0 X X X 1,004h X X X X X 0 0 0 0,004h 1 1 1 1 1 0 0 0 BYTE L L H H X X X X O Port output Port P25 direction register P24 to P27 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P24/A4(/D4/D3) Function selection Pin No. 68 (FP) 66 (GP) Setting register Remarks Page 1-28 1-28 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 4,3E6h A4/D3 A4/D4 A4 P24 P24 P24 I/O Multiplexed bus I/O Multiplexed bus O Address output I I Port input (No pulled high) Port input (Pulled high) X X X X X 0 0 1 4,3E6h 5,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 5,3FCh X X X X X 0 1 X 5,004h 0 1 X 1 0 X X X 4,004h 1 0 1 X 0 X X X 1,004h X X X X X 0 0 0 0,004h 1 1 1 1 1 0 0 0 BYTE L L H H X X X X O Port output Port P24 direction register P24 to P27 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P23/A3(/D3/D2) Function selection Pin No. 69 (FP) 67 (GP) Setting register Remarks Page 1-28 1-28 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 3,3E6h A3/D2 A3/D3 A3 P23 P23 P23 I/O Multiplexed bus I/O Multiplexed bus O Address output I I Port input (No pulled high) Port input (Pulled high) X X X X X 0 0 1 3,3E6h 4,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 4,3FCh X X X X X 0 1 X 5,004h 0 1 X 1 0 X X X 4,004h 1 0 1 X 0 X X X 1,004h X X X X X 0 0 0 0,004h 1 1 1 1 1 0 0 0 BYTE L L H H X X X X O Port output Port P23 direction register P20 to P23 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin 2-278 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P22/A2(/D2/D1) Function selection Pin No. 70 (FP) 68 (GP) Setting register Remarks Page 1-28 1-28 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 2,3E6h A2/D1 A2/D2 A2 P22 P22 P22 I/O Multiplexed bus I/O Multiplexed bus O Address output I I Port input (No pulled high) Port input (Pulled high) X X X X X 0 0 1 2,3E6h 4,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 4,3FCh X X X X X 0 1 X 5,004h 0 1 X 1 0 X X X 4,004h 1 0 1 X 0 X X X 1,004h X X X X X 0 0 0 0,004h 1 1 1 1 1 0 0 0 BYTE L L H H X X X X O Port output Port P22 direction register P20 to P23 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P21/A1(/D1/D0) Function selection Pin No. 71 (FP) 69 (GP) Setting register Remarks Page 1-28 1-28 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 1,3E6h A1/D0 A1/D1 A1 P21 P21 P21 I/O Multiplexed bus I/O Multiplexed bus O Address output I I Port input (No pulled high) Port input (Pulled high) X X X X X 0 0 1 1,3E6h 4,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 4,3FCh X X X X X 0 1 X 5,004h 0 1 X 1 0 X X X 4,004h 1 0 1 X 0 X X X 1,004h X X X X X 0 0 0 0,004h 1 1 1 1 1 0 0 0 BYTE L L H H X X X X O Port output Port P21 direction register P20 to P23 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P20/A0(/D0/-) Function selection Pin No. 72 (FP) 70 (GP) Setting register Remarks Page 1-28 1-28 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 0,3E6h A0/A0/D0 A0 P20 P20 P20 I/O Multiplexed bus I/O Multiplexed bus O Address output I I Port input (No pulled high) Port input (Pulled high) X X X X X 0 0 1 0,3E6h 4,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 4,3FCh X X X X X 0 1 X 5,004h 0 1 X 1 0 X X X 4,004h 1 0 1 X 0 X X X 1,004h X X X X X 0 0 0 0,004h 1 1 1 1 1 0 0 0 BYTE L L H H X X X X O Port output Port P20 direction register P20 to P23 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin 2-279 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P17/D15/INT5 Function selection Pin No. 73 (FP) 71 (GP) Setting register Remarks Page 1-28 1-61 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 7,3E3h D15 INT5 P17 P17 P17 I/O Data bus I I I Interrupt input Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 0 0 1 1 7,3E3h 3,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 3,3FCh X X X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 0 1 BYTE L X H X H X H X H Except 11 X X X X X X X X X X X X X X X X O Port output 0 X 0 X 0 X 0 X Port P17 direction register P14 to P17 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P16/D14/INT4 Function selection Pin No. 74 (FP) 72 (GP) Setting register Remarks Page 1-28 1-61 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 6,3E3h D14 INT4 P16 P16 P16 I/O Data bus I I I Interrupt input Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 0 0 1 1 6,3E3h 3,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 3,3FCh X X X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 0 1 BYTE L X H X H X H X H Except 11 X X X X X X X X X X X X X X X X O Port output 0 X 0 X 0 X 0 X Port P16 direction register P14 to P17 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P15/D13/INT3 Function selection Pin No. 75 (FP) 73 (GP) Setting register Remarks Page 1-28 1-61 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 5,3E3h D13 INT3 P15 P15 P15 I/O Data bus I I I Interrupt input Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 0 0 1 1 5,3E3h 3,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 3,3FCh X X X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 0 1 BYTE L X H X H X H X H Except 11 X X X X X X X X X X X X X X X X O Port output 0 X 0 X 0 X 0 X Port P15 direction register P14 to P17 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin 2-280 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P14/D12 Function selection Pin No. 76 (FP) 74 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 4,3E3h D12 P14 P14 P14 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 4,3E3h 3,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 3,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE L X H X H X H Except 11 X X X X X X X X X X X X O Port output 0 X 0 X 0 X Port P14 direction register P14 to P17 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P13/D11 Function selection Pin No. 77 (FP) 75 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 3,3E3h D11 P13 P13 P13 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 3,3E3h 2,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 2,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE L X H X H X H Except 11 X X X X X X X X X X X X O Port output 0 X 0 X 0 X Port P13 direction register P10 to P13 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P12/D10 Function selection Pin No. 78 (FP) 76 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 2,3E3h D10 P12 P12 P12 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 2,3E3h 2,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 2,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE L X H X H X H Except 11 X X X X X X X X X X X X O Port output 0 X 0 X 0 X Port P12 direction register P10 to P13 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin 2-281 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P11/D9 Function selection Pin No. 79 (FP) 77 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 1,3E3h D9 P11 P11 P11 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 1,3E3h 2,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 2,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE L X H X H X H Except 11 X X X X X X X X X X X X O Port output 0 X 0 X 0 X Port P11 direction register P10 to P13 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P10/D8 Function selection Pin No. 80 (FP) 78 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 0,3E3h D8 P10 P10 P10 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 0,3E3h 2,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 2,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE L X H X H X H Except 11 X X X X X X X X X X X X O Port output 0 X 0 X 0 X Port P10 direction register P10 to P13 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P07/D7 Function selection Pin No. 81 (FP) 79 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 7,3E2h D7 P07 P07 P07 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 7,3E2h 1,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 1,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE X X H X H X H Except 11 X 1 X 1 X 1 X 1 X 1 X 1 O Port output X 0 0 0 0 0 Port P07 direction register P04 to P07 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin 2-282 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P06/D6 Function selection Pin No. 82 (FP) 80 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 6,3E2h D6 P06 P06 P06 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 6,3E2h 1,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 1,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE X X H X H X H Except 11 X 1 X 1 X 1 X 1 X 1 X 1 O Port output 0 0 0 0 0 0 Port P06 direction register P04 to P07 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P05/D5 Function selection Pin No. 83 (FP) 81 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 5,3E2h D5 P05 P05 P05 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 5,3E2h 1,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 1,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE X X H X H X H Except 11 X 1 X 1 X 1 X 1 X 1 X 1 O Port output 0 0 0 0 0 0 Port P05 direction register P04 to P07 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P04/D4 Function selection Pin No. 84 (FP) 82 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 4,3E2h D4 P04 P04 P04 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 4,3E2h 1,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 1,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE X X H X H X H Except 11 X 1 X 1 X 1 X 1 X 1 X 1 O Port output 0 0 0 0 0 0 Port P04 direction register P04 to P07 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin 2-283 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P03/D3 Function selection Pin No. 85 (FP) 83 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-167 1-168 1-170 1-23 1-23 1-23 1-23 1-26 3,3E2h D3 P03 P03 P03 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 3,3E2h 0,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 0,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE X X H X H X H Except 11 X 1 X 1 X 1 X 1 X 1 X 1 O Port output 0 0 0 0 0 0 Port P03 direction register P00 to P03 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P02/D2 Function selection Pin No. 86 (FP) 84 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 2,3E2h D2 P02 P02 P02 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 2,3E2h 0,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 0,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE X X H X H X H Except 11 X 1 X 1 X 1 X 1 X 1 X 1 O Port output 0 0 0 0 0 0 Port P02 direction register P00 to P03 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P01/D1 Function selection Pin No. 87 (FP) 85 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 1,3E2h D1 P01 P01 P01 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 1,3E2h 0,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 0,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE X X H X H X H Except 11 X 1 X 1 X 1 X 1 X 1 X 1 O Port output 0 0 0 0 0 0 Port P01 direction register P00 to P03 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin 2-284 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P00/D0 Function selection Pin No. 88 (FP) 86 (GP) Setting register Remarks Page 1-28 1-163 1-163 1-163 1-168 1-170 1-23 1-23 1-23 1-23 1-26 0,3E2h D0 P00 P00 P00 I/O Data bus I I Port input (No pulled high) Port input (Pulled high) X 0 0 0 0 1 1 0,3E2h 0,3FCh 5,004h 4,004h 1,004h 0,004h BYTE 0,3FCh X 0 0 1 1 X X 5,004h 4,004h 1,004h X 0,004h 1 0 1 0 1 0 1 BYTE X X H X H X H Except 11 X 1 X 1 X 1 X 1 X 1 X 1 O Port output 0 0 0 0 0 0 Port P00 direction register P00 to P03 pull-up control register Multiplexed bus space select bit of processor mode register 0 Multiplexed bus space select bit of processor mode register 0 Processor mode bit of processor mode register 0 Processor mode bit of processor mode register 0 BYTE pin Pin name P107/AN7/KI3 Function selection Pin No. 89 (FP) 87 (GP) Setting register Remarks Page 1-62 1-149 1-163 1-163 1-163 1-168 1-170 7,3F6h KI3 AN7 P107 P107 P107 I I I I Key input A-D input Port input (No pulled high) Port input (Pulled high) 0 0 0 0 1 7,3F6h 5,3FEh 5,3FEh X 0 0 1 X Port P107 direction register P104 to P107 pull-up control register O Port output Pin name P106/AN6/KI2 Function selection Pin No. 90 (FP) 88 (GP) Setting register Remarks Page 1-62 1-149 1-163 1-163 1-163 1-168 1-170 6,3F6h KI2 AN6 P106 P106 P106 I I I I Key input A-D input Port input (No pulled high) Port input (Pulled high) 0 0 0 0 1 6,3F6h 5,3FEh 5,3FEh X 0 0 1 X Port P106 direction register P104 to P107 pull-up control register O Port output Pin name P105/AN5/KI1 Function selection Pin No. 91 (FP) 89 (GP) Setting register Remarks Page 1-62 1-149 1-163 1-163 1-163 1-168 1-170 5,3F6h KI1 AN5 P105 P105 P105 I I I I Key input A-D input Port input (No pulled high) Port input (Pulled high) 0 0 0 0 1 5,3F6h 5,3FEh 5,3FEh X 0 0 1 X Port P105 direction register P104 to P107 pull-up control register O Port output 2-285 Mitsubishi microcomputers M16C / 62A Group Appendix 3 Setting register for pin function selected SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P104/AN4/KI0 Function selection Pin No. 92 (FP) 90 (GP) Setting register Remarks Page 1-62 1-149 1-163 1-163 1-163 1-168 1-170 4,3F6h KI0 AN4 P104 P104 P104 I I I I Key input A-D input Port input (No pulled high) Port input (Pulled high) 0 0 0 0 1 4,3F6h 5,3FEh 5,3FEh X 0 0 1 X Port P104 direction register P104 to P107 pull-up control register O Port output Pin name P103/AN3 Function selection Pin No. 93 (FP) 91 (GP) Setting register Remarks Page 1-149 1-163 1-163 1-163 1-168 1-170 3,3F6h AN3 P103 P103 P103 I I I A-D input Port input (No pulled high) Port input (Pulled high) 0 0 0 1 3,3F6h 4,3FEh 4,3FEh 0 0 1 X Port P103 direction register P100 to P103 pull-up control register O Port output Pin name P102/AN2 Function selection Pin No. 94 (FP) 92 (GP) Setting register Remarks Page 1-149 1-163 1-163 1-163 1-168 1-170 2,3F6h AN2 P102 P102 P102 I I I A-D input Port input (No pulled high) Port input (Pulled high) 0 0 0 1 2,3F6h 4,3FEh 4,3FEh 0 0 1 X Port P102 direction register P100 to P103 pull-up control register O Port output Pin name P101/AN1 Function selection Pin No. 95 (FP) 93 (GP) Setting register Remarks Page 1-149 1-163 1-163 1-163 1-168 1-170 1,3F6h AN1 P101 P101 P101 I I I A-D input Port input (No pulled high) Port input (Pulled high) 0 0 0 1 1,3F6h 4,3FEh 4,3FEh 0 0 1 X Port P101 direction register P100 to P103 pull-up control register O Port output 2-286 Mitsubishi microcomputers Appendix 3 Setting register for pin function selected M16C / 62A Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pin name P100/AN0 Function selection Pin No. 97 (FP) 95 (GP) Setting register Remarks Page 1-149 1-163 1-163 1-163 1-168 1-170 0,3F6h AN0 P100 P100 P100 I I I A-D input Port input (No pulled high) Port input (Pulled high) 0 0 0 1 0,3F6h 4,3FEh 4,3FEh 0 0 1 X Port P100 direction register P100 to P103 pull-up control register O Port output Pin name P97/ADTRG/SIN4 Function selection Pin No. 100 (FP) 98 (GP) Setting register Remarks Page 1-149 1-145 1-163 1-163 1-163 1-168 1-170 1-151 1-146 7,3F3h ADTRG SIN4 P97 P97 P97 I I I I A-D trigger input Serial I/O data input Port input (No pulled high) Port input (Pulled high) 0 0 0 0 1 7,3F3h 3,3FEh 5,3D6h 3,366h 3,3FEh 0 0 0 1 X 5,3D6h 1 X X X X 3,366h 0 1 0 0 0 O Port output Port P97 direction register P94 to P97 pull-up control register Trigger select bit of A-D control register 0 SI/O4 port select bit of SI/O4 control register 2-287 Mitsubishi microcomputers M16C / 62A Group Appendix 4 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Appendix 4 A practical example of connecting to the reset IC M62015 and M62016 are reset ICs compatible with the M16C's backup mode. Here follow these ICs' overview and characteristics together with an example of connecting to the M16C when Vcc = 3 V. • Overview of the reset ICs Either M62015 or M62016 detects the rising edge of the power, the falling edge, and abnormal voltage of the power of the 3-V family of microcomputer systems. It is an optimal semiconductor integrated circuit to reset or release the microcomputer system. Either M62015 or M61016 carries out 2-step power voltage detection, and is provided with two output terminals (the forced reset signal output RESET and the interrupt handling signal output INT). Either M62015 or M62016 embeds the BiCMOS process and the low power consumption circuit, and outputs optimal signals from respective output terminals with low power consumption especially in dealing with a system that requires its RAM backup. • Characteristics of the reset ICs * BiCMOS process low-consumption circuit configuration Circuit current Icc = 3 µA (standard value normal mode Vcc = 3.0 V) Icc = 3 µA (standard value backup mode Vcc = 2.5 V) * Two-step power voltage detection Normal power detection Vs = 2.7 V (standard value) Power detection for backup VBATT = 2.0 V (standard value) * Two outputs ____________ Forced reset signal output RESET ______ Interrupt handling signal output INT * Output form CMOS output : M62015 Open drain output : M62016 • A practical example of connection Power supply VCC(+3V) Smoothing capacity 100µF VCC Power terminal + VCC Note Power for backup VBATT(+3V) + - INT INT Interrupt handling signal RESET Forced reset signal INT Interrupt input Cd Delay capacity 0.33µF + - RESET RESET Reset input Reset IC Clock signal input/output M62015 / M62016 M16C/62A group Note: Pull-up resistors are necessary only for open drain output form. 2-288 Mitsubishi microcomputers M16C / 62A Group Appendix 5 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Appendix 5 Countermeasures against noise Countermeasures against noise are described below. The following countermeasures are generally effective as countermeasures against noise, however, it is necessary not only to take measures as follows but to evaluate before actual use. 1.1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. 1.1.1 Package Select the smallest possible package to make the total wiring length short. q Reason The wiring length depends on a microcomputer package. Use of a small package, for example QFP and not DIP, makes the total wiring length short to reduce influence of noise. DIP SDIP SOP QFP Figure 1.1.1. Selection of packages ____________ 1.1.2 Wiring for RESET pin ____________ Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect ____________ a capacitor across the RESET pin and the VSS pin or reset IC with the shortest possible wiring (within 20mm). q Reason ____________ The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise ____________ having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway. Noise Reset circuit VSS RESET VSS Reset circuit VSS RESET VSS N.G. __________ O.K. Figure 1.1.2. Wiring for RESET pin 2-289 Mitsubishi microcomputers M16C / 62A Group Appendix 5 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1.1.3 Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other VSS patterns. (See Figure 1.4.3.) Noise XIN VSS XOUT XIN VSS XOUT N.G. Figure 1.1.3. Wiring for clock I/O pins O.K. q Reason If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. 1.1.4 Wiring to CNVss pin Connect the CNVss pin to the Vss pin with the shortest possible wiring. q Reason The processor mode of a microcomputer is influenced by a potential at the CNVss pin. If a potential difference is caused by the noise between pins CNVss and Vss, the processor mode may become unstable. This may cause a microcomputer malfunction or a program runaway. Noise CNVSS VSS CNVSS VSS N.G. Figure 1.1.4. Wiring for CNVss pin O.K. 2-290 Mitsubishi microcomputers M16C / 62A Group Appendix 5 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1.2 Connection of bypass capacitor across Vss line and Vcc line Connect an approximately 0.1 µF bypass capacitor across the Vss line and the Vcc line as follows: • Connect a bypass capacitor across the Vss pin and the Vcc pin at equal length. • Connect a bypass capacitor across the Vss pin and the Vcc pin with the shortest possible wiring. • Use lines with a larger diameter than other signal lines for Vss line and Vcc line. • Connect the power source wiring via a bypass capacitor to the Vss pin and the Vcc pin. VCC VCC VSS VSS N.G. O.K. Figure 1.2.1. Bypass capacitor across the Vss line and the Vcc line 1.3 Wiring to analog input pins • Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. • Connect an approximately 1000 pF capacitor across the Vss pin and the analog input pin. Besides, connect the capacitor to the Vss pin as close as possible. Also, connect the capacitor across the analog input pin and the Vss pin at equal length. q Reason Signals which is input in an analog input pin (such as an A-D converter/comparator input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. Noise (Note) Microcomputer Thermistor Analog input pin N.G. O.K. VSS Note: The resistor is used for dividing resistance with a thermistor. Figure 1.3.1. Analog signal line and a resistor and a capacitor 2-291 Mitsubishi microcomputers M16C / 62A Group Appendix 5 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1.4 Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. 1.4.1 Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. q Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. Microcomputer Mutual inductance M Large current GND XIN VSS XOUT Figure 1.4.1. Wiring for a large current signal line 1.4.2 Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Or do not stretch long such signal lines parallelly to these said lines. q Reason Signal lines where potential levels change frequently (such as the TAOUT pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. Do not cross TAOUT XIN VSS XOUT N.G. Figure 1.4.2. Wiring of signal lines where potential levels change frequently 2-292 Mitsubishi microcomputers M16C / 62A Group Appendix 5 1.4.3 Oscillator protection using Vss pattern SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns. An example of Vss patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN VSS XOUT Oscillator mounting unit Top View (on the component side) Figure 1.4.3. VSS pattern on the underside of an oscillator 1.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: • Connect a resistor of 100 Ω or more to a signal line which is connected to an I/O port in series. Besides, connect the resistor to the microcomputer as close as possible. • As for an input port, read data several times by a program for checking whether input levels are equal or not. • As for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. • Rewrite data to direction registers and pull-up control registers at fixed periods. Noise O.K. Data bus Noise Direction register N.G. Data register I/O port pin Figure 1.5.1. Setup for I/O ports 2-293 Mitsubishi microcomputers M16C / 62A Group Appendix 5 SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. • Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 ≥≥ (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. • Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. • Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. • Decrements the SWDT contents by 1 at each interrupt processing. • Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). • Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. Main routine (SWDT)← N FSET I Main processing ≠N (SWDT) =N? =N Interrupt processing routine (SWDT)← (SWDT) – 1 Interrupt processing 0 REIT Return Main routine errors (SWDT) ≤0? ≤0 Interrupt processing routine errors Figure 1.6.1. Watchdog timer by software 2-294 Index A A practical example of connecting to the reset IC ........ ............................................................................ 2-288 A-D Converter ..................................................... 1-149 A-D Converter Usage .......................................... 2-110 Address Match Interrupt ........................................ 1-63 Address Match Interrupt Usage .......................... 2-158 Applications ............................................................. 1-2 F Features .................................................................. 1-2 Flash Memory ..................................................... 1-218 Functions To Inhibit Rewriting Flash Memory Version ............................................................................ 1-233 I ______ B Block Diagram ......................................................... 1-5 Bus Control ........................................................... 1-28 Bus Settings .......................................................... 1-26 Buzzer Output ..................................................... 2-204 C Central Processing Unit (CPU) ............................. 1-12 Check Sheet ........................................................ 2-254 Clock Control ......................................................... 1-37 Clock Generating Circuit ....................................... 1-36 Clock Output ......................................................... 1-40 Clock-Asynchronous Serial I/O (UART) Usage ..... 2-74 Clock-Synchronous Serial I/O Usage.................... 2-52 Connectable Memories ....................................... 2-232 Connection Examples ......................................... 2-226 Controlling Power Using Stop Mode ................... 2-212 Controlling Power Using Wait Mode ................... 2-216 Countermeasures against noise ......................... 2-289 CPU Rewrite Mode ............................................. 1-219 CRC Calculation Circuit ...................................... 1-161 CRC Calculation Circuit Usage ........................... 2-152 INT Interrupt .......................................................... 1-61 Internal Reserved Area Expansion Bit (PM13) ...... 1-24 Interrupt Control .................................................... 1-51 Interrupt Priority ..................................................... 1-59 Interrupt resolution circuit ...................................... 1-59 Interrupt Sequence ................................................ 1-55 Items to be submitted when ordering masked ROM version ................................................................. 1-173 K Key Input Interrupt ................................................. 1-62 Key-Input Interrupt Usage ................................... 2-162 L Long-Period Timers ............................................. 2-192 M Memory ................................................................. 1-11 Memory Map (External ROM version) ................. 2-249 Memory to Memory DMA Transfer ...................... 2-208 Multiple interrupts Usage .................................... 2-166 N ______ NMI Interrupt ......................................................... 1-62 D D-A Converter ..................................................... 1-159 D-A Converter Usage .......................................... 2-142 Data Access ........................................................ 2-223 Delayed One-Shot Output ................................... 2-200 Description .............................................................. 1-2 DMAC .................................................................... 1-68 DMAC Usage ...................................................... 2-144 O Operation of Functional Blocks ............................. 1-11 Outline Performance ........................................... 1-217 Outline Performance (CPU Rewrite Mode) ......... 1-220 Overview of External Buses ................................ 2-222 Overview of Interrupt ............................................. 1-46 Overview of standard serial I/O mode 1 (clock synchronized) ........................................................... 1-240 Overview of standard serial I/O mode 2 (clock asynchronized) .................................................... 1-256 E Example of oscillator circuit ................................... 1-36 P W Parallel I/O Mode ................................................ 1-235 Wait Mode ............................................................. 1-41 Performance Outline ............................................... 1-6 Watchdog Timer .................................................... 1-66 Pin Configuration ..................................................... 1-3 Watchdog Timer Usage ....................................... 2-154 Pin Configuration (External ROM version) .......... 2-245 Pin Description (External ROM version) ............. 2-247 Power control ........................................................ 1-43 Power Control Usage .......................................... 2-173 Precautions for External Bus ............................... 2-242 Precautions for Interrupts ...................................... 1-64 Processor Mode ........................................ 1-22, 2-253 Programmable I/O Ports ..................................... 1-163 Programmable I/O Ports Usage .......................... 2-181 Protect Usage ......................................................... 2-2 Protection .............................................................. 1-45 R __________ _________ Releasing an External Bus (HOLD input and HLDA output) ................................................................. 2-241 Reset ..................................................................... 1-15 Returning from an Interrupt Routine ...................... 1-59 S Serial I/O ............................................................. 1-108 SI/O3, 4 Usage .................................................... 2-106 Software Reset ...................................................... 1-22 Solution for External Interrupt Pins Shortage ...... 2-206 Standard serial I/O mode .................................... 1-239 Status Transition of BCLK ..................................... 1-42 Stop Mode ............................................................. 1-40 T Timer ..................................................................... 1-78 Timer A .................................................................. 1-80 Timer A Usage ......................................................... 2-6 Timer B .................................................................. 1-90 Timer B Usage ...................................................... 2-38 Timers functions for three-phase motor control .... 1-96 U UART0 to 2 ......................................................... 1-108 V Variable-Period Variable-Duty PWM Output ....... 2-196 MITSUBISHI Single-Chip Microcomputer User's Manual M16C/62 (M16C/62A, M16C/62M) Group Rev.1.0 June First Edition 2001 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Kitaitami Works This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©2001 MITSUBISHI ELECTRIC CORPORATION User’s Manual M16C/62 (M16C/62A, M16C/62M) Group