M30624FGPGP

M16C/62P Group (M16C/62P, M16C/62PT) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0001-0241 Rev.2.41 Jan 10, 2006 1. Overview The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires highspeed arithmetic/logic operations. 1.1 Applications Audio, cameras, television, home appliance, office/communications/portable/industrial equipment, automobile, etc. Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 1 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview 1.2 Performance Outline Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version). Table 1.1 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version) Item CPU Number of Basic Instructions Minimum Instruction Execution Time Operating Mode Address Space Memory Capacity Peripheral Function Port Multifunction Timer Performance M16C/62P 91 instructions 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Single-chip, memory expansion and microprocessor mode 1 Mbyte (Available to 4 Mbytes by memory space expansion function) See Table 1.4 to 1.5 Product List Input/Output : 113 pins, Input : 1 pin Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels, Three phase motor control circuit 3 channels Clock synchronous, UART, I2C bus(1), IEBus(2) 2 channels Clock synchronous 10-bit A/D converter: 1 circuit, 26 channels 8 bits x 2 channels 2 channels CCITT-CRC 15 bits x 1 channel (with prescaler) Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), On-chip oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Stop detection of main clock oscillation, re-oscillation detection function Available (option(4)) VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=24MHz) VCC1=2.7 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=10MHz) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode) 0.7µA (VCC1=VCC2=3V, stop mode) 3.3±0.3 V or 5.0±0.5 V 100 times (all area) or 1,000 times (user ROM area without block A and block 1) / 10,000 times (block A, block 1) (3) -20 to 85°C, -40 to 85°C (3) 128-pin plastic mold LQFP Serial Interface A/D Converter D/A Converter DMAC CRC Calculation Circuit Watchdog Timer Interrupt Clock Generation Circuit Electric Characteristics Oscillation Stop Detection Function Voltage Detection Circuit Supply Voltage Power Consumption Flash memory version Program/Erase Supply Voltage Program and Erase Endurance Operating Ambient Temperature Package NOTES: 1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release schedule. 4. All options are on request basis. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 2 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.2 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(100-pin version) Item Performance M16C/62P M16C/62PT(4) 91 instructions 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Single-chip, memory expansion Single-chip and microprocessor mode CPU Number of Basic Instructions Minimum Instruction Execution Time Operating Mode Address Space 1 Mbyte (Available to 4 Mbytes by 1 Mbyte memory space expansion function) Memory Capacity See Table 1.4 to 1.7 Product List Peripheral Port Input/Output : 87 pins, Input : 1 pin Function Multifunction Timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels, Three phase motor control circuit Serial Interface 3 channels Clock synchronous, UART, I2C bus(1), IEBus(2) 2 channels Clock synchronous A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits x 2 channels DMAC 2 channels CRC Calculation Circuit CCITT-CRC Watchdog Timer 15 bits x 1 channel (with prescaler) Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels Interrupt Clock Generation Circuit 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), On-chip oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Oscillation Stop Stop detection of main clock oscillation, re-oscillation detection function Detection Function Absent Voltage Detection Circuit Available (option (5)) Electric Supply Voltage VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1=VCC2=4.0 to 5.5V Characteristics VCC1 (f(BCLK=24MHz) (f(BCLK=24MHz) VCC1=2.7 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=10MHz) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) Power Consumption 8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 2.0µA (VCC1=VCC2=5V, f(XCIN)=32kHz, wait mode) 1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode) 0.8µA (VCC1=VCC2=5V, stop mode) 0.7µA (VCC1=VCC2=3V, stop mode) Flash memory Program/Erase Supply Voltage 3.3±0.3 V or 5.0±0.5 V 5.0±0.5 V version Program and Erase 100 times (all area) Endurance or 1,000 times (user ROM area without block A and block 1) / 10,000 times (block A, block 1) (3) Operating Ambient Temperature -20 to 85°C, T version : -40 to 85°C V version : -40 to 125°C -40 to 85°C (3) Package 100-pin plastic mold QFP, LQFP NOTES: 1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release schedule. 4. Use the M16C/62PT on VCC1=VCC2 5. All options are on request basis. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 3 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.3 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version) Item Performance M16C/62P M16C/62PT(4) 91 instructions 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V) 100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) Single-chip mode CPU 1 Mbyte See Table 1.4 to 1.7 Product List Peripheral Port Input/Output : 70 pins, Input : 1 pin Function Multifunction Timer Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer), Timer B : 16 bits x 6 channels (Timer B1 is internal timer) Serial Interface 2 channels Clock synchronous, UART, I2C bus(1), IEBus(2) 1 channel Clock synchronous, I2C bus(1), IEBus(2) 2 channels Clock synchronous (1 channel is only transmission) A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits x 2 channels DMAC 2 channels CRC Calculation Circuit CCITT-CRC Watchdog Timer 15 bits x 1 channel (with prescaler) Internal: 29 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels Interrupt Clock Generation Circuit 4 circuits Main clock generation circuit (*), Subclock generation circuit (*), On-chip oscillator, PLL synthesizer (*)Equipped with a built-in feedback resistor. Oscillation Stop Stop detection of main clock oscillation, re-oscillation detection function Detection Function Absent Voltage Detection Circuit Available (option (4)) Electric Supply Voltage VCC1=3.0 to 5.5 V, (f(BCLK=24MHz) VCC1=4.0 to 5.5V, (f(BCLK=24MHz) Characteristics VCC1=2.7 to 5.5 V, (f(BCLK=10MHz) Power Consumption 14 mA (VCC1=5V, f(BCLK)=24MHz) 14 mA (VCC1=5V, f(BCLK)=24MHz) 8 mA (VCC1=3V, f(BCLK)=10MHz) 2.0µA (VCC1=5V, f(XCIN)=32kHz, wait mode) 1.8µA (VCC1=3V, f(XCIN)=32kHz, 0.8µA (VCC1=5V, stop mode) wait mode) 0.7µA (VCC1=3V, stop mode) 5.0 ± 0.5V Flash memory Program/Erase Supply Voltage 3.3 ± 0.3V or 5.0 ± 0.5V version Program and Erase 100 times (all area) Endurance or 1,000 times (user ROM area without block A and block 1) / 10,000 times (block A, block 1) (3) Operating Ambient Temperature -20 to 85°C, T version : -40 to 85°C V version : -40 to 125°C -40 to 85°C (3) Memory Capacity Package 80-pin plastic mold QFP NOTES: 1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V. 2. IEBus is a registered trademark of NEC Electronics Corporation. 3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature. In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release schedule. 4. All options are on request basis. Number of Basic Instructions Minimum Instruction Execution Time Operating Mode Address Space Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 4 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview 1.3 Block Diagram Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram, Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram. 8 8 8 8 8 8 8 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 (4) Port P7 (4) Internal peripheral functions Timer (16-bit) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit 8 A/D converter (10 bits X 8 channels Expandable up to 26 channels) UART or clock synchronous serial I/O System clock generation circuit XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator Port P8 7 (8 bits X 3 channels) CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) (4) Port P8_5 Clock synchronous serial I/O (8 bits X 2 channels) M16C/60 series16-bit CPU core Watchdog timer (15 bits) R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM (1) Port P9 8 DMAC (2 channels) RAM (2) Port P10 D/A converter (8 bits X 2 channels) 8 Multiplier (4) Port P11 (3) (4) Port P12 (3) Port P14 (3) Port P13 (3) 8 2 8 8 NOTES : 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type. 3. Ports P11 to P14 exist only in 128-pin version. 4. Use M16C/62PT on VCC1= VCC2. Figure 1.1 M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 5 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview 8 8 8 4 8 8 Port P0 Port P2 Port P3 (4) Port P4 Port P5 Port P6 Port P7 4 Internal peripheral functions Timer (16-bit) Output (timer A): 5 Input (timer B): 6 A/D converter (10 bits X 8 channels Expandable up to 26 channels) UART or clock synchronous serial I/O (2 channels) UART (1 channel) (3) System clock generation circuit XIN-XOUT XCIN-XCOUT PLL frequency synthesizer On-chip oscillator Clock synchronous serial I/O Port P8 Port P8_5 7 CRC arithmetic circuit (CCITT ) (Polynomial : X16+X12+X5+1) (8 bits X 2 channels) (4) Watchdog timer (15 bits) M16C/60 series16-bit CPU core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory Port P9 ROM (1) RAM (2) DMAC (2 channels) 7 D/A converter (8 bits X 2 channels) Port P10 Multiplier NOTES : 1. ROM size depends on microcomputer type. 2. RAM size depends on microcomputer type. 3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled). 4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program. 8 Figure 1.2 M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 6 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview 1.4 Product List Table 1.4 to 1.7 list the product list, Figure 1.3 shows the Type No., Memory Size, and Package, Table 1.8 lists the Product Code of Flash Memory version and ROMless version for M16C/62P, and Table 1.9 lists the Product Code of Flash Memory version for M16C/62PT. Figure 1.4 shows the Marking Diagram of Flash Memory version and ROM-less version for M16C/62P (Top View), and Figure 1.5 shows the Marking Diagram of Flash Memory version for M16C/62PT (Top View) at the time of ROM order. Table 1.4 Product List (1) (M16C/62P) ROM Capacity RAM Capacity Package Type 48 Kbytes 4 Kbytes PRQP0100JB-A PLQP0100KB-A 64 Kbytes 4 Kbytes PRQP0100JB-A PLQP0100KB-A PRQP0080JA-A 96 Kbytes 5 Kbytes PRQP0100JB-A PLQP0100KB-A PRQP0080JA-A 128 Kbytes 10 Kbytes PRQP0100JB-A PLQP0100KB-A PRQP0080JA-A 192 Kbytes 12 Kbytes PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A 256 Kbytes 12 Kbytes PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A 20 Kbytes PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A 320 Kbytes 16 Kbytes PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A 24 Kbytes PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A 31 Kbytes PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A (1) As of Dec. 2005 Remarks Mask ROM version Type No. M30622M6P-XXXFP M30622M6P-XXXGP M30622M8P-XXXFP M30622M8P-XXXGP M30623M8P-XXXGP M30622MAP-XXXFP M30622MAP-XXXGP M30623MAP-XXXGP M30620MCP-XXXFP M30620MCP-XXXGP M30621MCP-XXXGP M30622MEP-XXXFP M30622MEP-XXXGP M30623MEP-XXXGP M30622MGP-XXXFP M30622MGP-XXXGP M30623MGP-XXXGP M30624MGP-XXXFP M30624MGP-XXXGP M30625MGP-XXXGP M30622MWP-XXXFP M30622MWP-XXXGP M30623MWP-XXXGP M30624MWP-XXXFP M30624MWP-XXXGP M30625MWP-XXXGP M30626MWP-XXXFP M30626MWP-XXXGP M30627MWP-XXXGP (D): Under development NOTES: 1. The old package type numbers of each package type are as follows. PLQP0128KB-A : 128P6Q-A, PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A, PRQP0080JA-A : 80P6S-A Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 7 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.5 Product List (2) (M16C/62P) Type No. ROM Capacity 384 Kbytes RAM Capacity 16 Kbytes Package Type (1) PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A PRQP0100JB-A PLQP0100KB-A PRQP0080JA-A PRQP0100JB-A PLQP0100KB-A PRQP0080JA-A PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A PRQP0100JB-A PLQP0100KB-A PLQP0128KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A PRQP0100JB-A PLQP0100KB-A As of Dec. 2005 Remarks Mask ROM version M30622MHP-XXXFP M30622MHP-XXXGP M30623MHP-XXXGP M30624MHP-XXXFP M30624MHP-XXXGP M30625MHP-XXXGP M30626MHP-XXXFP M30626MHP-XXXGP M30627MHP-XXXGP M30626MJP-XXXFP M30626MJP-XXXGP M30627MJP-XXXGP M30622F8PFP M30622F8PGP M30623F8PGP M30620FCPFP M30620FCPGP M30621FCPGP M3062LFGPFP(3) M3062LFGPGP(3) M30625FGPGP M30626FHPFP M30626FHPGP M30627FHPGP M30626FJPFP M30626FJPGP M30627FJPGP M30622SPFP M30622SPGP M30620SPFP M30620SPGP M30624SPFP M30624SPGP M30626SPFP M30626SPGP 24 Kbytes 31 Kbytes (D) 512 Kbytes (D) (D) 64K+4 Kbytes 31 Kbytes 4 Kbytes Flash memory version (2) 128K+4 Kbytes 10 Kbytes (D) 256K+4 Kbytes 20 Kbytes (D) 384K+4 Kbytes 31 Kbytes 512K+4 Kbytes 31 Kbytes − 4 Kbytes 10 Kbytes ROM-less version (D) − (D) (D) (D) 20 Kbytes 31 Kbytes (D): Under development NOTES: 1. The old package type numbers of each package type are as follows. PLQP0128KB-A : 128P6Q-A, PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A, PRQP0080JA-A : 80P6S-A 2. In the flash memory version, there is 4K bytes area (block A). 3. Please use M3062LFGPFP and M3062LFGPGP for your new system instead of M30624FGPFP and M30624FGPGP. The M16C/62P Group (M16C/62P, M16C/62PT) hardware manual is still good for M30624FGPFP and M30624FGPGP. M30624FGPFP M30624FGPGP 256K+4 Kbytes 20 Kbytes PRQP0100JB-A Flash memory version PLQP0100KB-A Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 8 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.6 Product List (3) (T version (M16C/62PT)) Type No. RAM Package Type (1) Capacity (D) 48 Kbytes 4 Kbytes PRQP0100JB-A (D) PLQP0100KB-A (P) PRQP0080JA-A (D) 64 Kbytes 4 Kbytes PRQP0100JB-A (D) PLQP0100KB-A (P) PRQP0080JA-A (D) 96 Kbytes 5 Kbytes PRQP0100JB-A (D) PLQP0100KB-A (P) PRQP0080JA-A (D) 128 Kbytes 10 Kbytes PRQP0100JB-A (D) PLQP0100KB-A (P) PRQP0080JA-A (D) 64 K+4 Kbytes 4 Kbytes PRQP0100JB-A PLQP0100KB-A (D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A (D) PLQP0100KB-A (P) PRQP0080JA-A (D) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A (D) PLQP0100KB-A ROM Capacity As of Dec. 2005 Remarks Mask ROM T Version version (High reliability 85°C version) M3062CM6T-XXXFP M3062CM6T-XXXGP M3062EM6T-XXXGP M3062CM8T-XXXFP M3062CM8T-XXXGP M3062EM8T-XXXGP M3062CMAT-XXXFP M3062CMAT-XXXGP M3062EMAT-XXXGP M3062AMCT-XXXFP M3062AMCT-XXXGP M3062BMCT-XXXGP M3062CF8TFP M3062CF8TGP M3062AFCTFP M3062AFCTGP M3062BFCTGP M3062JFHTFP M3062JFHTGP Flash memory version (2) (D): Under development (P): Under planning NOTES: 1. The old package type numbers of each package type are as follows. PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A, PRQP0080JA-A : 80P6S-A 2. In the flash memory version, there is 4K bytes area (block A). Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 9 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.7 Product List (4) (V version (M16C/62PT)) Type No. RAM Package Type(1) Capacity (P) 48 Kbytes 4 Kbytes PRQP0100JB-A (P) PLQP0100KB-A (P) PRQP0080JA-A (P) 64 Kbytes 4 Kbytes PRQP0100JB-A (P) PLQP0100KB-A (P) PRQP0080JA-A (P) 96 Kbytes 5 Kbytes PRQP0100JB-A (P) PLQP0100KB-A (P) PRQP0080JA-A (D) 128 Kbytes 10 Kbytes PRQP0100JB-A (D) PLQP0100KB-A (P) PRQP0080JA-A (D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A (D) PLQP0100KB-A (P) PRQP0080JA-A (P) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A (P) PLQP0100KB-A ROM Capacity As of Dec. 2005 Remarks Mask ROM V Version version (High reliability 125°C version) M3062CM6V-XXXFP M3062CM6V-XXXGP M3062EM6V-XXXGP M3062CM8V-XXXFP M3062CM8V-XXXGP M3062EM8V-XXXGP M3062CMAV-XXXFP M3062CMAV-XXXGP M3062EMAV-XXXGP M3062AMCV-XXXFP M3062AMCV-XXXGP M3062BMCV-XXXGP M3062AFCVFP M3062AFCVGP M3062BFCVGP M3062JFHVFP M3062JFHVGP Flash memory version (2) (D): Under development (P): Under planning NOTES: 1. The old package type numbers of each package type are as follows. PLQP0128KB-A : 128P6Q-A, PRQP0100JB-A : 100P6S-A, PLQP0100KB-A : 100P6Q-A, PRQP0080JA-A : 80P6S-A 2. In the flash memory version, there is 4K bytes area (block A). Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 10 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Type No. M3062 6 MH P - XXX FP Package type: FP : Package GP : Package PRQP0100JB-A (100P6S-A) PRQP0080JA-A (80P6S-A), PLQP0100KB-A (100P6Q-A), PLQP0128KB-A (128P6Q-A), ROM No. Omitted for flash memory version and ROMless version Classification P : M16C/62P T : T version (M16C/62PT) V : V version (M16C/62PT) ROM capacity: 6: 48 Kbytes 8: 64 Kbytes A: 96 Kbytes C: 128 Kbytes E: 192 Kbytes G: 256 Kbytes W: 320 Kbytes H: 384 Kbytes J: 512 Kbytes Memory type: M: Mask ROM version F: Flash memory version S: ROM-less version Shows RAM capacity, pin count, etc Numeric, Alphabet (L) : M16C/62P Alphabet (L is excluded.) : M16C/62PT M16C/62(P) Group M16C Family Figure 1.3 Type No., Memory Size, and Package Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 11 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P Internal ROM (User ROM Area Without Block A, Block 1) Program and Erase Endurance 100 Temperature Range 0°C to 60°C Internal ROM (Block A, Block 1) Program and Erase Endurance 100 Temperature Range 0°C to 60°C -40°C to 85°C -20°C to 85°C Lead-free 100 100 0°C to 60°C -40°C to 85°C -20°C to 85°C Leadincluded Lead-free − − − − − − − − Product Code Package Operating Ambient Temperature Flash memory Version D3 D5 D7 D9 U3 U5 U7 U9 Leadincluded -40°C to 85°C -20°C to 85°C -40°C to 85°C -20°C to 85°C -40°C to 85°C -20°C to 85°C -40°C to 85°C -20°C to 85°C -40°C to 85°C -20°C to 85°C -40°C to 85°C -20°C to 85°C 1,000 10,000 1,000 10,000 ROM-less version D3 D5 U3 U5 M1 6 C M3 0 6 2 6 F H P F P B D5 XXXXXXX Type No. (See Figure 1.3 Type No., Memory Size, and Package ) Chip version and product code B : Shows chip version. Henceforth, whenever it changes a version, it continues with B, C, and D. D5 : Shows Product code. (See table 1.8 Product Code) Date code seven digits The product without marking of chip version of the flash memory version and the ROMless version corresponds to the chip version “A”. Figure 1.4 Marking Diagram of Flash Memory version and ROM-less version for M16C/62P (Top View) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 12 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.9 Product Code of Flash Memory version for M16C/62PT Internal ROM (User ROM Area Without Block A, Block 1) Program and Erase Endurance 100 1,000 Lead-free 100 1,000 Temperature Range 0°C to 60°C Internal ROM (Block A, Block 1) Program and Erase Endurance 100 10,000 100 10,000 Temperature Range 0°C to 60°C -40°C to 85°C 0°C to 60°C -40°C to 85°C Operating Ambient Temperature -40°C to 85°C -40°C to 125°C -40°C to 85°C -40°C to 85°C -40°C to 125°C U7 -40°C to 85°C -40°C to 125°C -40°C to 125°C -40°C to 125°C -40°C to 125°C U Product Code Package Flash memory Version T Version V Version T Version V Version T Version V Version T Version V Version B B7 Leadincluded M1 6 C M3 0 6 2 J F H T F P Y YY X X X X X X X Type No. (See Figure 1.3 Type No., Memory Size, and Package ) Date code seven digits Product code. (See table 1.9 Product Code ) “ ” : Product code “B” “ P B F ” : Product code “U” “B7 ” : Product code “B” “U7 ” : Product code “U7” NOTES: 1. : Blank Figure 1.5 Marking Diagram of Flash Memory version for M16C/62PT (Top View) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 13 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview 1.5 Pin Configuration Figures 1.6 to 1.9 show the Pin Configuration (Top View). PIN CONFIGURATION (top view) P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P12_0 P12_1 P12_2 P12_3 P12_4 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P1_1/D9 P1_2/D10 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 (2) 63 62 61 60 59 58 57 56 55 54 53 M16C/62P Group (M16C/62P) 52 51 50 49 48 47 46 45 44 43 42 41 40 39 (2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P12_5 P12_6 P12_7 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P13_0 P13_1 P13_2 P13_3 P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P13_4 P13_5 P13_6 P13_7 P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 VSS NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/62PT on VCC1=VCC2. Package : PLQP0128KB-A (128P6Q-A) Figure 1.6 Pin Configuration (Top View) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 14 of 96 P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_0/TXD2/SDA2/TA0OUT (1) P6_7/TXD1/SDA1 VCC1 P6_6/RXD1/SCL1 VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 P14_1 P14_0 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT M16C/62P Group (M16C/62P, M16C/62PT) Table 1.10 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1. Overview Pin Characteristics for 128-Pin Package (1) Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin Control Pin VREF AVCC P9_7 P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 P14_1 P14_0 BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 VCC1 P6_6 VSS P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P13_7 P13_6 P13_5 P13_4 P5_7 NMI INT2 INT1 INT0 SIN4 SOUT4 CLK4 TB4IN TB3IN TB2IN TB1IN TB0IN ADTRG ANEX1 ANEX0 DA1 DA0 SOUT3 SIN3 CLK3 P8_7 P8_6 ZP TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN/TB5IN TA0OUT CTS2/RTS2 CLK2 RXD2/SCL2 TXD2/SDA2 TXD1/SDA1 RXD1/SCL1 CLK1 CTS1/RTS1/CTS0/CLKS1 TXD0/SDA0 RXD0/SCL0 CLK0 CTS0/RTS0 RDY/CLKOUT Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 15 of 96 M16C/62P Group (M16C/62P, M16C/62PT) Table 1.11 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1. Overview Pin Characteristics for 128-Pin Package (2) Port P5_6 P5_5 P5_4 P13_3 P13_2 P13_1 P13_0 P5_3 P5_2 P5_1 P5_0 P12_7 P12_6 P12_5 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P12_4 P12_3 P12_2 P12_1 P12_0 Control Pin Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin ALE HOLD HLDA BCLK RD WRH/BHE WRL/WR CS3 CS2 CS1 CS0 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 VCC2 P3_0 VSS P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 INT5 INT4 INT3 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 A7(/D7/D6) A6(/D6/D5) A5(/D5/D4) A4(/D4/D3) A3(/D3/D2) A2(/D2/D1) A1(/D1/D0) A0(/D0/-) D15 D14 D13 D12 D11 A8(/-/D7) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 16 of 96 M16C/62P Group (M16C/62P, M16C/62PT) Table 1.12 Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 1. Overview Pin Characteristics for 128-Pin Package (3) Port P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 KI3 KI2 KI1 KI0 Control Pin Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS P10_0 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 17 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview PIN CONFIGURATION (top view) P1_0/D8 P1_1/D9 P1_2/D10 P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 P4_2/A18 P4_3/A19 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG/SIN4 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 (2) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 M16C/62P Group (M16C/62P, M16C/62PT) (2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/62PT on VCC1=VCC2. Figure 1.7 Pin Configuration (Top View) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT P7_5/TA2IN/W P7_4/TA2OUT/W P7_3/CTS2/RTS2/TA1IN/V P7_2/CLK2/TA1OUT/V P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_0/TXD2/SDA2/TA0OUT (1) Package : PRQP0100JB-A (100P6S-A) Page 18 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview PIN CONFIGURATION (top view) P1_3/D11 P1_4/D12 P1_5/D13/INT3 P1_6/D14/INT4 P1_7/D15/INT5 P2_0/AN2_0/A0(/D0/-) P2_1/AN2_1/A1(/D1/D0) P2_2/AN2_2/A2(/D2/D1) P2_3/AN2_3/A3(/D3/D2) P2_4/AN2_4/A4(/D4/D3) P2_5/AN2_5/A5(/D5/D4) P2_6/AN2_6/A6(/D6/D5) P2_7/AN2_7/A7(/D7/D6) VSS P3_0/A8(/-/D7) VCC2 P3_1/A9 P3_2/A10 P3_3/A11 P3_4/A12 P3_5/A13 P3_6/A14 P3_7/A15 P4_0/A16 P4_1/A17 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P1_2/D10 P1_1/D9 P1_0/D8 P0_7/AN0_7/D7 P0_6/AN0_6/D6 P0_5/AN0_5/D5 P0_4/AN0_4/D4 P0_3/AN0_3/D3 P0_2/AN0_2/D2 P0_1/AN0_1/D1 P0_0/AN0_0/D0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/SOUT4 P9_5/ANEX0/CLK4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (2) 50 49 48 47 46 45 44 43 42 41 40 M16C/62P Group (M16C/62P, M16C/62PT) 39 38 37 36 35 34 33 32 31 30 29 (2) 28 27 26 P4_2/A18 P4_3/A19 P4_4/CS0 P4_5/CS1 P4_6/CS2 P4_7/CS3 P5_0/WRL/WR P5_1/WRH/BHE P5_2/RD P5_3/BCLK P5_4/HLDA P5_5/HOLD P5_6/ALE P5_7/RDY/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT (1) P7_1/RXD2/SCL2/TA0IN/TB5IN (1) P7_2/CLK2/TA1OUT/V P9_4/DA1/TB4IN P9_3/DA0/TB3IN P9_2/TB2IN/SOUT3 P9_1/TB1IN/SIN3 P9_0/TB0IN/CLK3 BYTE CNVSS P8_7/XCIN P8_6/XCOUT RESET XOUT VSS XIN VCC1 P8_5/NMI P8_4/INT2/ZP P8_3/INT1 P8_2/INT0 P8_1/TA4IN/U P8_0/TA4OUT/U P7_7/TA3IN P7_6/TA3OUT P7_5/TA2IN/W P7_4/TA2OUT/W NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. 2. Use the M16C/62PT on VCC1=VCC2. Package : PLQP0100KB-A (100P6Q-A) Figure 1.8 Pin Configuration (Top View) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 19 of 96 P7_3/CTS2/RTS2/TA1IN/V M16C/62P Group (M16C/62P, M16C/62PT) Table 1.13 Pin Characteristics for 100-Pin Package (1) Port P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 BYTE CNVSS XCIN XCOUT TB4IN TB3IN TB2IN TB1IN TB0IN SOUT3 SIN3 CLK3 1. Overview Pin No. Control Pin FP GP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 100 1 2 3 4 5 6 7 8 9 Interrupt Pin Timer Pin SOUT4 CLK4 UART Pin Analog Pin ANEX1 ANEX0 DA1 DA0 Bus Control Pin P8_7 P8_6 10 RESET 11 XOUT 12 VSS 13 XIN 14 VCC1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TA0IN/TB5IN TA0OUT CTS2/RTS2 CLK2 RXD2/SCL2 TXD2/SDA2 TXD1/SDA1 RXD1/SCL1 CLK1 CTS1/RTS1/CTS0/CLKS1 TXD0/SDA0 RXD0/SCL0 CLK0 CTS0/RTS0 RDY/CLKOUT ALE HOLD HLAD BCLK RD WRH/BHE WRL/WR CS3 CS2 CS1 CS0 ZP Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 20 of 96 M16C/62P Group (M16C/62P, M16C/62PT) Table 1.14 Pin Characteristics for 100-Pin Package (2) Port P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 P10_0 KI3 KI2 KI1 KI0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 INT5 INT4 INT3 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 1. Overview Pin No. Control Pin FP GP 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 VCC2 61 62 VSS 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 AVSS 95 96 VREF 97 AVCC 98 Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8(/-/D7) A7(/D7/D6) A6(/D6/D5) A5(/D5/D4) A4(/D4/D3) A3(/D3/D2) A2(/D2/D1) A1(/D1/D0) A0(/D0/-) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P9_7 SIN4 ADTRG Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 21 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview PIN CONFIGURATION (top view) P2_0/AN2_0 P2_1/AN2_1 P2_2/AN2_2 P2_4/AN2_4 P2_5/AN2_5 P2_7/AN2_7 P0_7/AN0_7 P2_3/AN2_3 P2_6/AN2_6 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P4_0 P4_1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P4_2 P0_6/AN0_6 P0_5/AN0_5 P0_4/AN0_4 P0_3/AN0_3 P0_2/AN0_2 P0_1/AN0_1 P0_0/AN0_0 P10_7/AN7/KI3 P10_6/AN6/KI2 P10_5/AN5/KI1 P10_4/AN4/KI0 P10_3/AN3 P10_2/AN2 P10_1/AN1 AVSS P10_0/AN0 VREF AVCC P9_7/ADTRG/SIN4 P9_6/ANEX1/SOUT4 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 P4_3 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7/CLKOUT P6_0/CTS0/RTS0 P6_1/CLK0 P6_2/RXD0/SCL0 P6_3/TXD0/SDA0 P6_4/CTS1/RTS1/CTS0/CLKS1 P6_5/CLK1 P6_6/RXD1/SCL1 P6_7/TXD1/SDA1 P7_0/TXD2/SDA2/TA0OUT (1) P7_1/RXD2/SCL2/TA0IN/TB5IN P7_6/TA3OUT M16C/62P Group (M16C/62P, M16C/62PT) 32 31 30 29 28 27 26 25 24 23 22 21 (1) P9_0/TB0IN/CLK3 CNVSS(BYTE) P8_5/NMI P8_3/INT1 P9_5/ANEX0/CLK4 P8_2/INT0 RESET XOUT VCC1 P9_4/DA1/TB4IN P8_0/TA4OUT P8_6/XCOUT P8_4/INT2/ZP P8_1/TA4IN VSS XIN P9_3/DA0/TB3IN NOTES: 1. P7_0 and P7_1 are N channel open-drain output pins. P9_2/TB2IN/SOUT3 Package : PRQP0080JA-A (80P6S-A) Figure 1.9 Pin Configuration (Top View) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 22 of 96 P7_7/TA3IN P8_7/XCIN M16C/62P Group (M16C/62P, M16C/62PT) Table 1.15 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CNVSS (BYTE) XCIN XCOUT RESET XOUT VSS XIN VCC1 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 P5_5 P5_4 P5_3 P5_2 P5_1 P5_0 P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 NMI INT2 INT1 INT0 TA4IN TA4OUT TA3IN TA3OUT TA0IN/TB5IN TA0OUT RXD2/SCL2 TXD2/SDA2 TXD1/SDA1 RXD1/SCL1 CLK1 CTS1/RTS1/CTS0/CLKS1 TXD0/SDA0 RXD0/SCL0 CLK0 CTS0/RTS0 ZP 1. Overview Pin Characteristics for 80-Pin Package (1) Port P9_5 P9_4 P9_3 P9_2 P9_0 Control Pin Interrupt Pin Timer Pin CLK4 TB4IN TB3IN TB2IN TB0IN SOUT3 CLK3 UART Pin Analog Pin ANEX0 DA1 DA0 Bus Control Pin P8_7 P8_6 CLKOUT Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 23 of 96 M16C/62P Group (M16C/62P, M16C/62PT) Table 1.16 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 VREF AVCC P9_7 P9_6 SIN4 SOUT4 ADTRG ANEX1 AVSS P10_0 AN0 1. Overview Pin Characteristics for 80-Pin Package (2) Port P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 KI3 KI2 KI1 KI0 Control Pin Interrupt Pin Timer Pin UART Pin Analog Pin AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN7 AN6 AN5 AN4 AN3 AN2 AN1 Bus Control Pin Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 24 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview 1.6 Pin Description Pin Description (100-pin and 128-pin Version) (1) Pin Name VCC1,VCC2 VSS AVCC AVSS RESET CNVSS I/O Power Description Type Supply(3) I − Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is that VCC1 ≥ VCC2. (1, 2) I VCC1 Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. I I VCC1 VCC1 The microcomputer is in a reset state when applying “L” to the this pin. Switches processor mode. Connect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. Switches the data bus in external memory space. The data bus is 16 bits long when the this pin is held "L" and 8 bits long when the this pin is held "H". Set it to either one. Connect this pin to VSS when an single-chip mode. Inputs and outputs data (D0 to D7) when these pins are set as the separate bus. Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the separate bus. Output address bits (A0 to A19). Input and output data (D0 to D7) and output address bits (A0 to A7) by timesharing when external 8-bit data bus are set as the multiplexed bus. Input and output data (D0 to D7) and output address bits (A1 to A8) by timesharing when external 16-bit data bus are set as the multiplexed bus. Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to specify an external space. Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or BHE and WR can be switched by program. • WRL, WRH and RD are selected The WRL signal becomes "L" by writing data to an even address in an external memory space. The WRH signal becomes "L" by writing data to an odd address in an external memory space. The RD pin signal becomes "L" by reading data in an external memory space. • WR, BHE and RD are selected The WR signal becomes "L" by writing data in an external memory space. The RD signal becomes "L" by reading data in an external memory space. The BHE signal becomes "L" by accessing an odd address. Select WR, BHE and RD for an external 8-bit data bus. ALE is a signal to latch the address. While the HOLD pin is held "L", the microcomputer is placed in a hold state. In a hold state, HLDA outputs a "L" signal. While applying a "L" signal to the RDY pin, the microcomputer is placed in a wait state. Table 1.17 Signal Name Power supply input Analog power supply input Reset input CNVSS External data bus width select input Bus control pins (4) BYTE I VCC1 D0 to D7 D8 to D15 A0 to A19 A0/D0 to A7/D7 A1/D0 to A8/D7 CS0 to CS3 WRL/WR WRH/BHE RD I/O I/O O I/O I/O VCC2 VCC2 VCC2 VCC2 VCC2 O O VCC2 VCC2 ALE HOLD HLDA RDY O I O I VCC2 VCC2 VCC2 VCC2 I : Input O : Output I/O : Input and output Power Supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be interfaced using the different voltage as VCC1. NOTES: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted. 2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 = VCC2. 3. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked. 4. Bus control pins in M16C/62PT cannot be used. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 25 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.18 Signal Name Main clock input Main clock output Sub clock input Sub clock output BCLK output (2) Clock output INT interrupt input NMI interrupt input Key input interrupt input Timer A Pin Description (100-pin and 128-pin Version) (2) Pin Name XIN XOUT XCIN XCOUT BCLK CLKOUT INT0 to INT2 NT3 to INT5 NMI KI0 to KI3 TA0OUT to TA4OUT TA0IN to TA4IN ZP TB0IN to TB5IN I/O Power Description Type Supply(1) I VCC1 I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (3). To use O VCC1 the external clock, input the clock from XIN and leave XOUT open. I O O O I I I I I/O I I I O VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. Input pins for the key input interrupt. These are timer A0 to timer A4 I/O pins. (however, output of TA0OUT for the N-channel open drain output.) These are timer A0 to timer A4 input pins. Input pin for the Z-phase. These are timer B0 to timer B5 input pins. These are Three-phase motor control output pins. I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT (3). To use the external clock, input the clock from XCIN and leave XCOUT open. Outputs the BCLK signal. The clock of the same cycle as fC, f8, or f32 is outputted. Input pins for the INT interrupt. Timer B Three-phase U, U, V, V, motor control W, W output Serial interface CTS0 to CTS2 RTS0 to RTS2 CLK0 to CLK4 RXD0 to RXD2 SIN3, SIN4 TXD0 to TXD2 SOUT3, SOUT4 CLKS1 I2C mode SDA0 to SDA2 SCL0 to SCL2 I O I/O I I O O O I/O I/O VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 These are send control input pins. These are receive control output pins. These are transfer clock I/O pins. These are serial data input pins. These are serial data input pins. These are serial data output pins. (however, output of TXD2 for the N-channel open drain output.) These are serial data output pins. This is output pin for transfer clock output from multiple pins function. These are serial data I/O pins. (however, output of SDA2 for the Nchannel open drain output.) These are transfer clock I/O pins. (however, output of SCL2 for the N-channel open drain output.) I : Input O : Output I/O : Input and output NOTES: 1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked. 2. This pin function in M16C/62PT cannot be used. 3. Ask the oscillator maker the oscillation characteristic. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 26 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.19 Signal Name Reference voltage input A/D converter Pin Description (100-pin and 128-pin Version) (3) Pin Name VREF AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7 ADTRG ANEX0 ANEX1 DA0, DA1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7 (2), P13_0 to P13_7 (2) P6_0 to P6_7, P7_0 to P7_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7 (2) P8_0 to P8_4, P8_6, P8_7, P14_0, P14_1(2) P8_5 I/O Power Description Type Supply(1) I VCC1 Applies the reference voltage for the A/D converter and D/A converter. I VCC1 Analog input pins for the A/D converter. I I/O I O I/O VCC1 VCC1 VCC1 VCC1 VCC2 This is an A/D trigger input pin. This is the extended analog input pin for the A/D converter, and is the output in external op-amp connection mode. This is the extended analog input pin for the A/D converter. This is the output pin for the D/A converter. 8-bit I/O ports in CMOS, having a direction register to select an input or output. Each pin is set as an input port or output port. An input port can be set for a pull-up or for no pull-up in 4-bit unit by program. D/A converter I/O port I/O VCC1 8-bit I/O ports having equivalent functions to P0. (however, output of P7_0 and P7_1 for the N-channel open drain output.) I/O VCC1 I/O ports having equivalent functions to P0. Input port I : Input I VCC1 Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. O : Output I/O : Input and output NOTES: 1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked. 2. Ports P11 to P14 in M16C/62P (100-pin version) and M16C/62PT (100-pin version) cannot be used. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 27 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.20 Signal Name Power supply input Analog power supply input Reset input CNVSS Pin Description (80-pin Version) (1) (1) Pin Name VCC1, VSS AVCC AVSS RESET CNVSS (BYTE) I/O Type I I I I Power Supply − VCC1 VCC1 VCC1 Description Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin. (1, 2) Applies the power supply for the A/D converter. Connect the AVCC pin to VCC1. Connect the AVSS pin to VSS. The microcomputer is in a reset state when applying “L” to the this pin. Switches processor mode. Connect this pin to VSS to when after a reset to start up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor mode. As for the BYTE pin of the 80-pin versions, pull-up processing is performed within the microcomputer. I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT (3). To use the external clock, input the clock from XIN and leave XOUT open. I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT (3). To use the external clock, input the clock from XCIN and leave XCOUT open. The clock of the same cycle as fC, f8, or f32 is outputted. Input pins for the INT interrupt. Input pin for the NMI interrupt. Input pins for the key input interrupt. These are Timer A0,Timer A3 and Timer A4 I/O pins. (however, output of TA0OUT for the N-channel open drain output.) These are Timer A0, Timer A3 and Timer A4 input pins. Input pin for the Z-phase. These are Timer B0, Timer B2 to Timer B5 input pins. These are send control input pins. These are receive control output pins. These are transfer clock I/O pins. These are serial data input pins. This is serial data input pin. These are serial data output pins. (however, output of TXD2 for the N-channel open drain output.) These are serial data output pins. This is output pin for transfer clock output from multiple pins function. These are serial data I/O pins. (however, output of SDA2 for the N-channel open drain output.) These are transfer clock I/O pins. (however, output of SCL2 for the N-channel open drain output.) Main clock input Main clock output Sub clock input Sub clock output Clock output INT interrupt input NMI interrupt input Key input interrupt input Timer A XIN XOUT XCIN XCOUT CLKOUT INT0 to INT2 NMI KI0 to KI3 TA0OUT, TA3OUT, TA4OUT TA0IN, TA3IN, TA4IN ZP TB0IN, TB2IN to TB5IN RTS0 to RTS1 CLK0, CLK1, CLK3, CLK4 RXD0 to RXD2 SIN4 TXD0 to TXD2 SOUT3, SOUT4 CLKS1 I O I O O I I I I/O VCC1 VCC1 VCC1 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 I I I I O I/O I I O O O I/O I/O VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 Timer B Serial interface CTS0 to CTS1 I2C mode SDA0 to SDA2 SCL0 to SCL2 I : Input O : Output I/O : Input and output NOTES: 1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted. 2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 pin. 3. Ask the oscillator maker the oscillation characteristic. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 28 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview Table 1.21 Signal Name Reference voltage input A/D converter Pin Description (80-pin Version) (2) Pin Name VREF AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7 ADTRG ANEX0 ANEX1 DA0, DA1 P0_0 to P0_7, P2_0 to P2_7, P3_0 to P3_7, P5_0 to P5_7, P6_0 to P6_7, P10_0 to P10_7 P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7 P4_0 to P4_3, P7_0, P7_1, P7_6, P7_7 P8_5 I/O Power Description Type Supply(1) I VCC1 Applies the reference voltage for the A/D converter and D/A converter. I VCC1 Analog input pins for the A/D converter. I I/O I O I/O VCC1 VCC1 VCC1 VCC1 VCC1 This is an A/D trigger input pin. This is the extended analog input pin for the A/D converter, and is the output in external op-amp connection mode. This is the extended analog input pin for the A/D converter. This is the output pin for the D/A converter. 8-bit I/O ports in CMOS, having a direction register to select an input or output. Each pin is set as an input port or output port. An input port can be set for a pull-up or for no pull-up in 4-bit unit by program. D/A converter I/O port (1) I/O VCC1 I/O ports having equivalent functions to P0. I/O VCC1 I/O ports having equivalent functions to P0. (however, output of P7_0 and P7_1 for the N-channel open drain output.) Input pin for the NMI interrupt. Pin states can be read by the P8_5 bit in the P8 register. Input port I : Input I VCC1 O : Output I/O : Input and output NOTES: 1. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 29 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b31 b15 b8 b7 b0 R2 R3 R0H R1H R2 R3 A0 A1 FB R0L R1L Data Registers (1) Address Registers (1) Frame Base Registers (1) b0 b19 b15 INTBH INTBL Interrupt Table Register b19 b0 PC b15 b0 Program Counter USP ISP SB b15 b0 User Stack Pointer Interrupt Stack Pointer Static Base Register FLG b15 b8 b7 b0 Flag Register IPL UI OB S Z DC Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Area Processor Interrupt Priority Level Reserved Area NOTES: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 Central Processing Unit Register 2.1 Data Registers (R0, R1, R2 and R3) The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data register (R2R0). R3R1 is the same as R2R0. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 30 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU) 2.2 Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG. 2.7 Static Base Register (SB) SB is configured with 16 bits, and is used for SB relative addressing. 2.8 Flag Register (FLG) FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”. 2.8.3 Zero Flag (Z Flag) This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”. 2.8.4 Sign Flag (S Flag) This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”. 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”. 2.8.6 Overflow Flag (O Flag) This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”. 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag is cleared to “0” when the interrupt request is accepted. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 31 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU) 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”. The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. 2.8.10 Reserved Area When write to this bit, write “0”. When read, its content is indeterminate. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 32 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 3. Memory 3. Memory Figure 3.1 is a Memory Map of the M16C/62P group. The address space extends the 1M bytes from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh. As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs. The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start address of each interrupt routine here. The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 10-Kbyte internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data, the internal RAM also stores the stack used when calling subroutines and when interrupts are generated. The SRF is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users. The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual. In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. Use M16C/62P (80-pin version) and M16C/62PT in single-chip mode. The memory expansion and microprocessor modes cannot be used . 00000h SFR 00400h Internal RAM XXXXXh Reserved area (1) 0F000h Internal ROM (data area) (3) 0FFFFh 10000h Internal RAM Size 4 Kbytes 5 Kbytes 10 Kbytes 12 Kbytes 16 Kbytes 20 Kbytes 24 Kbytes 31 Kbytes Address XXXXXh 013FFh 017FFh 02BFFh 033FFh 043FFh 053FFh 063FFh 07FFFh Size 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes 192 Kbytes 256 Kbytes 320 Kbytes 384 Kbytes 512 Kbytes Internal ROM (3) FFE00h Special page vector table External area Address YYYYYh F4000h F0000h E8000h E0000h D0000h C0000h B0000h A0000h 80000h 27000h Reserved area 28000h External area 80000h Reserved area (2) YYYYYh Internal ROM (program area) (5) FFFFFh FFFFFh FFFDCh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC NMI Reset NOTES: 1. During memory expansion and microprocessor modes, can be used. 2. In memory expansion mode, can be used. 3. As for the flash memory version, 4-Kbyte space (block A) exists. 4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1” and the PM13 bit in the PM1 register is “1”. 5. When using the masked ROM version, write nothing to internal ROM area. Figure 3.1 Memory Map Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 33 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.6 list the SFR information. Table 4.1 SFR Information (1) (1) Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh NOTES: 1. 2. 3. 4. 5. 6. Register Symbol After Reset Processor Mode Register 0 (2) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Chip Select Control Register (6) Address Match Interrupt Enable Register Protect Register Data Bank Register (6) Oscillation Stop Detection Register (3) Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 PM0 PM1 CM0 CM1 CSR AIER PRCR DBR CM2 WDTS WDC RMAD0 00000000b(CNVSS pin is “L”) 00000011b(CNVSS pin is “H”) 00001000b 01001000b 00100000b 00000001b XXXXXX00b XX000000b 00h 0X000000b XXh 00XXXXXXb (4) 00h 00h X0h 00h 00h X0h Address Match Interrupt Register 1 RMAD1 Voltage Detection Register 1 (5, 6) Voltage Detection Register 2 (5, 6) Chip Select Expansion Control Register (6) PLL Control Register 0 Processor Mode Register 2 Low Voltage Detection Interrupt Register (6) DMA0 Source Pointer VCR1 VCR2 CSE PLC0 PM2 D4INT SAR0 00001000b 00h 00h 0001X010b XXX00000b 00h XXh XXh XXh XXh XXh XXh XXh XXh DMA0 Destination Pointer DAR0 DMA0 Transfer Counter TCR0 DMA0 Control Register DM0CON 00000X00b DMA1 Source Pointer SAR1 XXh XXh XXh XXh XXh XXh XXh XXh DMA1 Destination Pointer DAR1 DMA1 Transfer Counter TCR1 DMA1 Control Register DM1CON 00000X00b The blank areas are reserved and cannot be accessed by users. The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset. The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset. The WDC5 bit is “0” (cold start) immediately after power-on. I t can only be set to “1” in a program. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset. This register in M16C/62PT cannot be used. X : Nothing is mapped to this bit Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 34 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.2 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh SFR Information (2) (1) Register Symbol After Reset INT3 Interrupt Control Register Timer B5 Interrupt Control Register Timer B4 Interrupt Control Register, UART1 BUS Collision Detection Interrupt Control Register Timer B3 Interrupt Control Register, UART0 BUS Collision Detection Interrupt Control Register SI/O4 Interrupt Control Register, INT5 Interrupt Control Register SI/O3 Interrupt Control Register, INT4 Interrupt Control Register UART2 Bus Collision Detection Interrupt Control Register DMA0 Interrupt Control Register DMA1 Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register Timer A0 Interrupt Control Register Timer A1 Interrupt Control Register Timer A2 Interrupt Control Register Timer A3 Interrupt Control Register Timer A4 Interrupt Control Register Timer B0 Interrupt Control Register Timer B1 Interrupt Control Register Timer B2 Interrupt Control Register INT0 Interrupt Control Register INT1 Interrupt Control Register INT2 Interrupt Control Register INT3IC TB5IC TB4IC, U1BCNIC TB3IC, U0BCNIC S4IC, INT5IC S3IC, INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC XX00X000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XX00X000b XX00X000b NOTES: 1. The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 35 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h to 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01C0h to 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h to 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh SFR Information (3) (1) Register Symbol After Reset Flash Identification Register (2) Flash Memory Control Register 1 (2) Flash Memory Control Register 0 (2) Address Match Interrupt Register 2 FIDR FMR1 FMR0 RMAD2 XXXXXX00b 0X00XX0Xb 00000001b 00h 00h XXh XXXXXX00b 00h 00h XXh Address Match Interrupt Enable Register 2 Address Match Interrupt Register 3 AIER2 RMAD3 Peripheral Clock Select Register PCLKR 00000011b NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. This register is included in the flash memory version. X : Nothing is mapped to this bit Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 36 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.4 Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh SFR Information (4) (1) Register Timer B3, 4, 5 Count Start Flag Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Occurrence Frequency Set Counter TBSR TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 Symbol After Reset 000XXXXXb XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h XXh XXh Timer B3 Register Timer B4 Register Timer B5 Register TB3 TB4 TB5 XXh XXh XXh XXh XXh XXh Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register Interrupt Factor Select Register 2 Interrupt Factor Select Register SI/O3 Transmit/Receive Register SI/O3 Control Register SI/O3 Bit Rate Generator SI/O4 Transmit/Receive Register SI/O4 Control Register SI/O4 Bit Rate Generator TB3MR TB4MR TB5MR IFSR2A IFSR S3TRR S3C S3BRG S4TRR S4C S4BRG 00XX0000b 00XX0000b 00XX0000b 00XXXXXXb 00h XXh 01000000b XXh XXh 01000000b XXh UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Generator UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register U0SMR4 U0SMR3 U0SMR2 U0SMR U1SMR4 U1SMR3 U1SMR2 U1SMR U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h 000X0X0Xb X0000000b X0000000b 00h XXh XXh XXh 00001000b 00000010b XXh XXh NOTES: 1. The blank areas are reserved and cannot be accessed by users. X : Nothing is mapped to this bit Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 37 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.5 Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh SFR Information (5) (1) Register Count Start Flag Clock Prescaler Reset Fag One-Shot Start Flag Trigger Select Register Up-Down Flag Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Bit Rate Generator UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Generator UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register UART Transmit/Receive Control Register 2 Symbol TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON After Reset 00h 0XXXXXXXb 00h 00h 00h (2) XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh 00h 00h 00h 00h 00h 00XX0000b 00XX0000b 00XX0000b XXXXXX00b 00h XXh XXh XXh 00001000b 00XX0010b XXh XXh 00h XXh XXh XXh 00001000b 00XX0010b XXh XXh X0000000b DMA0 Request Factor Select Register DMA1 Request Factor Select Register CRC Data Register CRC Input Register DM0SL DM1SL CRCD CRCIN 00h 00h XXh XXh XXh NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. Bit 5 in the Up-down flag is “0” by reset. However, The values in these bits when read are indeterminate. X : Nothing is mapped to this bit Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 38 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) Table 4.6 Address 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh SFR Information (6) (1) Register A/D Register 0 A/D Register 1 A/D Register 2 A/D Register 3 A/D Register 4 A/D Register 5 A/D Register 6 A/D Register 7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Symbol XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh After Reset A/D Control Register 2 A/D Control Register 0 A/D Control Register 1 D/A Register 0 D/A Register 1 D/A Control Register Port P14 Control Register (3) Pull-Up Control Register 3 (3) Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register (3) Port P10 Direction Register Port P11 Direction Register (3) Port P12 Register (3) Port P13 Register (3) Port P12 Direction Register (3) Port P13 Direction Register (3) Pull-Up Control Register 0 Pull-Up Control Register 1 Pull-Up Control Register 2 Port Control Register ADCON2 ADCON0 ADCON1 DA0 DA1 DACON PC14 PUR3 P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 PUR0 PUR1 PUR2 PCR 00h 00000XXXb 00h 00h 00h 00h XX00XXXXb 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00X00000b 00h XXh XXh 00h 00h XXh XXh 00h 00h 00h 00000000b (2) 00000010b (2) 00h 00h NOTES: 1. The blank areas are reserved and cannot be accessed by users. 2. At hardware reset 1 or hardware reset 2, the register is as follows: • “00000000b” where “L” is inputted to the CNVSS pin • “00000010b” where “H” is inputted to the CNVSS pin At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: • “00000000b” where the PM01 to PM00 bits in the PM0 register are “00b” (single-chip mode). • “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or “11b” (microprocessor mode). 3. These registers do not exist in M16C/62P (80-pin version), and M16C/62PT (80-pin version). X : Nothing is mapped to this bit Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 39 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics 5. 5.1 Electrical Characteristics Electrical Characteristics (M16C/62P) Absolute Maximum Ratings Parameter Supply Voltage Supply Voltage Analog Supply Voltage Input Voltage RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, VREF, XIN P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 P7_0, P7_1 Output Voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, XOUT P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 P7_0, P7_1 Power Dissipation Operating When the Microcomputer is Operating Ambient Temperature Flash Program Erase Storage Temperature Condition VCC1=AVCC VCC2 VCC1=AVCC Rated Value −0.3 to 6.5 −0.3 to VCC1+0.1 −0.3 to 6.5 −0.3 to VCC1+0.3 (1) Unit V V V V Table 5.1 Symbol VCC1, VCC2 VCC2 AVCC VI −0.3 to VCC2+0.3 (1) V −0.3 to 6.5 −0.3 to VCC1+0.3 (1) VO V V −0.3 to VCC2+0.3 (1) V −0.3 to 6.5 −40°C VCC2, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins. 3. φAD frequency must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V, and φAD frequency into 10 MHz or less. 4. When sample & hold is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 3. When sample & hold is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 3. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 43 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Table 5.5 Symbol − − D/A Conversion Characteristics (1) Parameter Resolution Absolute Accuracy Setup Time Output Resistance Reference Power Supply Input Current Measuring Condition Min. Standard Typ. Max. 8 1.0 3 20 1.5 Unit Bits % µs kΩ mA tSU RO IVREF 4 (NOTE 2) 10 NOTES: 1. Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified. 2. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to “00h”. The resistor ladder of the A/D converter is not included. Also, when D/A register contents are not “00h”, the IVREF will flow even if Vref id disconnected by the A/D control register. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 44 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Table 5.6 Flash Memory Version Electrical Characteristics (1) for 100 cycle products (D3, D5, U3, U5) Parameter Program and Erase Endurance (3) Word Program Time (VCC1=5.0V) Lock Bit Program Time Block Erase Time (VCC1=5.0V) Min. 100 Standard Typ. 25 25 0.3 0.3 0.5 0.8 Max. 200 200 4 4 4 4 4×n 15 Unit cycle µs µs s s s s s µs year Symbol − − − − − − − − 4-Kbyte block 8-Kbyte block 32-Kbyte block 64-Kbyte block tPS − Erase All Unlocked Blocks Time (2) Flash Memory Circuit Stabilization Wait Time Data Hold Time (5) 10 Table 5.7 Flash Memory Version Electrical Characteristics (6) for 10,000 cycle products (D7, D9, U7, U9) (Block A and Block 1 (7)) Parameter Program and Erase Endurance (3, 8, 9) Word Program Time (VCC1=5.0V) Lock Bit Program Time Block Erase Time (VCC1=5.0V) Flash Memory Circuit Stabilization Wait Time Data Hold Time (5) Min. 10,000 (4) Standard Typ. 25 25 0.3 15 10 Max. Unit cycle µs µs s µs year Symbol − − − − 4-Kbyte block tPS − NOTES: 1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C (D3, D5, U3, U5) unless otherwise specified. 2. n denotes the number of block erases. 3. Program and Erase Endurance refers to the number of times a block erase can be performed. If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times. For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as one program and erase endurance. Data cannot be written to the same address more than once without erasing the block. (Rewrite prohibited) 4. Maximum number of E/W cycles for which operation is guaranteed. 5. Topr = -40 to 85 °C (D3, D7, U3, U7) / -20 to 85 °C (D5, D9, U5, U9). 6. Referenced to VCC1 = 4.5 to 5.5V, 3.0 to 3.6V at Topr = -40 to 85 °C (D7, U7) / -20 to 85 °C (D9, U9) unless otherwise specified. 7. Table 5.7 applies for block A or block 1 program and erase endurance > 1,000. Otherwise, use Table 5.6. 8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are used. For example, an 8-word program can be written 256 times maximum before erase becomes necessary. Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to track the total number of times erasure is used. 9. Should erase error occur during block erase, attempt to execute clear status register command, then block erase command at least three times until erase error disappears. 10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (D7, D9, U7 and U9). 11. Customers desiring E/W failure rate information should contact their Renesas technical support representative. Table 5.8 Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics (at Topr = 0 to 60 °C(D3, D5, U3, U5), Topr = -40 to 85 °C(D7, U7) / Topr = -20 to 85 °C(D9, U9)) Flash Read Operation Voltage VCC1=2.7 to 5.5 V Flash Program, Erase Voltage VCC1 = 3.3 V ± 0.3 V or 5.0 V ± 0.5 V Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 45 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Table 5.9 Symbol Vdet4 Vdet3 Vdet4-Vdet3 Vdet3s Vdet3r Low Voltage Detection Circuit Electrical Characteristics Parameter Low Voltage Detection Voltage (1) Reset Level Detection Voltage (1, 2) Electric potential difference of Low Voltage Detection and Reset Level Detection Low Voltage Reset Retention Voltage Low Voltage Reset Release Voltage (3) Measuring Condition VCC1=0.8V to 5.5V Min. 3.3 2.2 0.3 Standard Typ. 3.8 2.8 Max. 4.4 3.6 Unit V V V V V 2.2 2.9 0.8 4.0 NOTES: 1. Vdet4 > Vdet3. 2. Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection voltage, the microcomputer operates with f(BCLK) ≤ 10MHz. 3. Vdet3r > Vdet3 is not guaranteed. 4. The voltage detection circuit is designed to use when VCC1 is set to 5V. Table 5.10 Symbol td(P-R) td(R-S) td(W-S) td(S-R) td(E-A) Power Supply Circuit Timing Characteristics Parameter Time for Internal Power Supply Stabilization During Powering-On STOP Release Time Low Power Dissipation Mode Wait Mode Release Time Brown-out Detection Reset (Hardware Reset 2) Release Wait Time Low Voltage Detection Circuit Operation Start Time Measuring Condition VCC1=2.7V to 5.5V Min. Standard Typ. Max. 2 150 150 VCC1=Vdet3r to 5.5V VCC1=2.7V to 5.5V 6 (1) 20 20 Unit ms µs µs ms µs NOTES: 1. When VCC1 = 5V. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 46 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics td(P-R) Time for Internal Power Supply Stabilization During Powering-On Recommended operation voltage VCC1 td(P-R) CPU clock td(R-S) STOP Release Time Interrupt for (a) Stop mode release or (b) Wait mode release td(W-S) Low Power Dissipation Mode Wait Mode Release Time CPU clock (a) (b) td(R-S) td(W-S) td(S-R) Low Voltage Detection Reset (Hardware Reset 2) Release Wait Time VCC1 Vdet3r td(S-R) CPU clock td(E-A) Low Voltage Detection Circuit Operation Start Time VC26, VC27 Low Voltage Detection Circuit Stop Operate td(E-A) Figure 5.1 Power Supply Circuit Timing Diagram Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 47 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Table 5.11 Symbol VOH HIGH Output Voltage (3) Electrical Characteristics (1) Parameter (1) Measuring Condition IOH=−5mA IOH=−5mA (2) OH=−200µA Min. Standard Typ. Max. VCC1 Unit P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 VCC1−2.0 VCC2−2.0 VCC1−0.3 VCC2−0.3 VCC1−2.0 VCC1−2.0 2.5 1.6 V VCC2 VCC1 V VCC2 VCC1 VCC1 V V 2.0 VOH HIGH Output Voltage (3) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOH=−200µA (2) IOH=−1mA IOH=−0.5mA With no load applied With no load applied IOL=5mA VOH HIGH Output Voltage XOUT HIGHPOWER LOWPOWER HIGH Output Voltage XCOUT HIGHPOWER LOWPOWER VOL LOW Output Voltage (3) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOL=5mA (2) V 2.0 VOL LOW Output Voltage (3) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOL=200µA 0.45 IOL=200µA (2) V 0.45 VOL LOW Output Voltage XOUT HIGHPOWER LOWPOWER IOL=1mA IOL=0.5mA With no load applied With no load applied 2.0 2.0 0 0 0.2 1.0 V V LOW Output Voltage XCOUT HIGHPOWER LOWPOWER VT+-VT- Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4 V VT+-VTIIH Hysteresis HIGH Input Current (3) RESET P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE VI=5V 0.2 2.5 V 5.0 µA IIL LOW Input Current (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE VI=0V −5.0 µA RPULLUP Pull-Up Resistance (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 VI=0V 30 50 170 kΩ RfXIN RfXCIN VRAM Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage At stop mode 1.5 15 2.0 MΩ MΩ V NOTES: 1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=24MHz unless otherwise specified. 2. Where the product is used at VCC1 = 5 V and VCC2 = 3 V, refer to the 3 V version value for the pin specified value on VCC2 port side. 3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 48 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Table 5.12 Symbol ICC Electrical Characteristics (2) (1) Parameter Measuring Condition Mask ROM f(BCLK)=24MHz No division, PLL operation No division, On-chip oscillation Min. Standard Typ. Max. 14 1 18 1.8 15 25 25 25 420 50 7.5 2.0 0.8 0.7 1.2 3.0 4 8 27 20 Unit mA mA mA mA mA mA µA µA µA µA µA µA µA µA µA Power Supply Current In single-chip (VCC1=VCC2=4.0V to 5.5V) mode, the output pins are open and other pins are VSS Flash Memory f(BCLK)=24MHz, No division, PLL operation No division, On-chip oscillation Flash Memory Program Flash Memory Erase Mask ROM Flash Memory f(BCLK)=10MHz, VCC1=5.0V f(BCLK)=10MHz, VCC1=5.0V f(XCIN)=32kHz Low power dissipation mode, ROM (3) f(BCLK)=32kHz Low power dissipation mode, RAM (3) f(BCLK)=32kHz Low power dissipation mode, Flash Memory (3) On-chip oscillation, Wait mode Mask ROM Flash Memory f(BCLK)=32kHz Wait mode (2), Oscillation capability High f(BCLK)=32kHz Wait mode (2), Oscillation capability Low Stop mode Topr =25°C Idet4 Idet3 Low Voltage Detection Dissipation Current Reset Area Detection Dissipation Current (4) (4) NOTES: 1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=24MHz unless otherwise specified. 2. With one timer operated using fC32. 3. This indicates the memory in which the program to be executed exists. 4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled). Idet4: VC27 bit in the VCR2 register Idet3: VC26 bit in the VCR2 register Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 49 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.13 Symbol tc tw(H) tw(L) tr tf External Clock Input (XIN input) (1) Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Standard Min. 62.5 25 25 Max. Unit ns ns ns ns ns 15 15 NOTES: 1. The condition is VCC1=VCC2=3.0 to 5.0V. Table 5.14 Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK) tsu(HOLD-BCLK) th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) Memory Expansion Mode and Microprocessor Mode Parameter Data Input Access Time (for setting with no wait) Data Input Access Time (for setting with wait) Data Input Access Time (when accessing multiplex bus area) Data Input Setup Time RDY Input Setup Time HOLD Input Setup Time Data Input Hold Time RDY Input Hold Time HOLD Input Hold Time Standard Min. Max. (NOTE 1) (NOTE 2) (NOTE 3) Unit ns ns ns ns ns ns ns ns ns 40 30 40 0 0 0 NOTES: 1. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 45 [ ns ] f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 ( n – 0.5 ) x 10 ------------------------------------ – 45 [ ns ] f ( BCLK ) 9 ( n – 0.5 ) x 10 ------------------------------------ – 45 [ ns ] f ( BCLK ) n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: n is “2” for 2-wait setting, “3” for 3-wait setting. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 50 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.15 Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Timer A Input (Counter Input in Event Counter Mode) Parameter Standard Min. 100 40 40 Max. Unit ns ns ns Table 5.16 Symbol tc(TA) tw(TAH) tw(TAL) Timer A Input (Gating Input in Timer Mode) Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 400 200 200 Max. Unit ns ns ns Table 5.17 Symbol tc(TA) tw(TAH) tw(TAL) Timer A Input (External Trigger Input in One-shot Timer Mode) Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 200 100 100 Max. Unit ns ns ns Table 5.18 Symbol tw(TAH) tw(TAL) Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Parameter TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 100 100 Max. Unit ns ns Table 5.19 Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Timer A Input (Counter Increment/Decrement Input in Event Counter Mode) Parameter TAiOUT Input Cycle Time TAiOUT Input HIGH Pulse Width TAiOUT Input LOW Pulse Width TAiOUT Input Setup Time TAiOUT Input Hold Time Standard Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns Table 5.20 Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) Timer A Input (Two-phase Pulse Input in Event Counter Mode) Parameter TAiIN Input Cycle Time TAiOUT Input Setup Time TAiIN Input Setup Time Standard Min. 800 200 200 Max. Unit ns ns ns Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 51 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.21 Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Timer B Input (Counter Input in Event Counter Mode) Parameter TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Input LOW Pulse Width (counted on one edge) TBiIN Input Cycle Time (counted on both edges) TBiIN Input HIGH Pulse Width (counted on both edges) TBiIN Input LOW Pulse Width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns Table 5.22 Symbol tc(TB) tw(TBH) tw(TBL) Timer B Input (Pulse Period Measurement Mode) Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 400 200 200 Max. Unit ns ns ns Table 5.23 Symbol tc(TB) tw(TBH) tw(TBL) Timer B Input (Pulse Width Measurement Mode) Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 400 200 200 Max. Unit ns ns ns Table 5.24 Symbol tc(AD) tw(ADL) A/D Trigger Input Parameter ADTRG Input Cycle Time ADTRG input LOW Pulse Width Standard Min. 1000 125 Max. Unit ns ns Table 5.25 Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial Interface Parameter CLKi Input Cycle Time CLKi Input HIGH Pulse Width CLKi Input LOW Pulse Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RXDi Input Hold Time Standard Min. 200 100 100 0 70 90 Max. Unit ns ns ns ns ns ns ns 80 Table 5.26 Symbol tw(INH) tw(INL) External Interrupt INTi Input Parameter INTi Input HIGH Pulse Width INTi Input LOW Pulse Width Standard Min. 250 250 Max. Unit ns ns Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 52 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.27 Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Memory Expansion and Microprocessor Modes (for setting with no wait) Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR) (3) HLDA Output Delay Time Standard Min. Max. 25 4 0 (NOTE 2) 25 4 15 −4 25 0 25 0 40 4 (NOTE 1) (NOTE 2) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns See Figure 5.2 NOTES: 1. Calculated according to the BCLK frequency as follows: 9 0.5x10 f(BCLK) is 12.5MHz or less. ----------------------- – 40 [ ns ] f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = −CR X ln (1−VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time of output ”L” level is t = −30pF X 1k Ω X In(1−0.2VCC2 / VCC2) = 6.7ns. R DBi C P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 30pF Figure 5.2 Ports P0 to P14 Measurement Circuit Page 53 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.28 Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR)(3) HLDA Output Delay Time Standard Min. Max. 25 4 0 (NOTE 2) 25 4 15 See Figure 5.2 -4 25 0 25 0 40 4 (NOTE 1) (NOTE 2) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) NOTES: 1. Calculated according to the BCLK frequency as follows: 9 ( n – 0.5 ) x10 ----------------------------------- – 40 [ ns ] f ( BCLK ) n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting. (BCLK) is 12.5MHz or less. 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = −CR X ln (1−VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time of output ”L” level is t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2) = 6.7ns. R DBi C Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 54 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.29 Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area access and multiplex bus selection) Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) Chip Select Output Hold Time (in relation to RD) Chip Select Output Hold Time (in relation to WR) RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR) HLDA Output Delay Time ALE Signal Output Delay Time (in relation to BCLK) ALE Signal Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time (in relation to Address) ALE Signal Output Hold Time (in relation to Address) RD Signal Output Delay From the End of Address WR Signal Output Delay From the End of Address Address Output Floating Start Time Standard Min. Max. 25 4 (NOTE 1) (NOTE 1) 25 4 (NOTE 1) (NOTE 1) 25 0 25 See Figure 5.2 0 40 4 (NOTE 2) (NOTE 1) 40 15 −4 (NOTE 3) (NOTE 4) 0 0 Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(AD-ALE) td(AD-RD) td(AD-WR) tdz(RD-AD) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 NOTES: 1. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 10 [ ns ] f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 ( n – 0.5 ) x10 ----------------------------------- – 40 [ ns ] f ( BCLK ) n is “2” for 2-wait setting, “3” for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 25 [ ns ] f ( BCLK ) 4. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 15 [ ns ] f ( BCLK ) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 55 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V XIN input tr tw(H) tf tc tw(L) tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode th(TIN-UP) tsu(UP-TIN) tc(TA) TAiIN input tsu(TAIN-TAOUT) TAiOUT input tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) Figure 5.3 Timing Diagram (1) Page 56 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi td(C-Q) RXDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D) Figure 5.4 Timing Diagram (2) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 57 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY−BCLK) th(BCLK−RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD−BCLK) th(BCLK−HOLD) HOLD input HLDA input P0, P1, P2, P3, P4, P5_0 to P5_2 td(BCLK−HLDA) Hi−Z td(BCLK−HLDA) (1) NOTES: 1. These pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register. · Measuring conditions : · VCC1=VCC2=5V · Input timing voltage : Determined with VIL=1.0V, VIH=4.0V · Output timing voltage : Determined with VOL=2.5V, VOH=2.5V Figure 5.5 Timing Diagram (3) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 58 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (For setting with no wait ) Read timing VCC1=VCC2=5V BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 × tcyc-45)ns.max Hi-Z DBi tsu(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 × tcyc-10)ns.min td(BCLK-WR) 25ns.max ALE th(BCLK-WR) 0ns.min WR, WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) (0.5 × tcyc-40)ns.min th(WR-DB) (0.5 × tcyc-10)ns.min tcyc= 1 f(BCLK) Measuring conditions · VCC1=VCC2=5V · Input timing voltage : VIL=0.8V, VIH=2.0V · Output timing voltage : VOL=0.4V, VOH=2.4V Figure 5.6 Timing Diagram (4) Page 59 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access ) Read timing BCLK td(BCLK-CS) 25ns.max VCC1=VCC2=5V th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (1.5 × tcyc-45)ns.max DBi Hi-Z th(RD-DB) tsu(DB-RD) 40ns.min 0ns.min Write timing BCLK td(BCLK-CS) 25ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 25ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 × tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) tcyc= 1 f(BCLK) (0.5 × tcyc-40)ns.min th(WR-DB) (0.5 × tcyc-10)ns.min Measuring conditions · VCC1=VCC2=5V · Input timing voltage : VIL=0.8V, VIH=2.0V · Output timing voltage : VOL=0.4V, VOH=2.4V Figure 5.7 Timing Diagram (5) Page 60 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (for 2-wait setting and external area access) Read timing tcyc VCC1=VCC2=5V BCLK td(BCLK-CS) 25ns.max CSi td(BCLK-AD) 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-CS) 4ns.min th(BCLK-AD) 4ns.min th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max RD tac2(RD-DB) (2.5×tcyc-45)ns.max DBi Hi-Z th(BCLK-RD) 0ns.min tsu(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max CSi td(BCLK-AD) 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-CS) 4ns.min th(BCLK-AD) 4ns.min th(BCLK-ALE) -4ns.min th(WR-AD) (0.5×tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max DBi Hi-Z th(BCLK-DB) 4ns.min td(DB-WR) (1.5×tcyc-40)ns.min Tcyc= 1 f(BCLK) th(WR-DB) (0.5×tcyc-10)ns.min Measuring conditions · VCC1=VCC2=5V · Input timing voltage : V IL=0.8V, VIH=2.0V · Output timing voltage : V OL=0.4V, VOH=2.4V Figure 5.8 Timing Diagram (6) Page 61 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access ) Read timing tcyc BCLK td(BCLK-CS) 25ns.max CSi td(BCLK-AD) 25ns.max VCC1=VCC2=5V th(BCLK-CS) 4ns.min th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max RD tac2(RD-DB) (3.5×tcyc-45)ns.max th(BCLK-RD) 0ns.min DBi Hi-Z tsu(DB-RD) 40ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 25ns.max CSi td(BCLK-AD) 25ns.max th(BCLK-CS) 4ns.min th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5×tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DBi Hi-Z td(DB-WR) tcyc= 1 f(BCLK) (2.5×tcyc-40)ns.min th(WR-DB) (0.5×tcyc-10)ns.min Measuring conditions · VCC1=VCC2=5V · Input timing voltage : V IL=0.8V, VIH=2.0V · Output timing voltage : V OL=0.4V, VOH=2.4V Figure 5.9 Timing Diagram (7) Page 62 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (For 1- or 2-wait setting, external area access and multiplex bus selection ) Read timing BCLK td(BCLK-CS) 25ns.max tcyc th(RD-CS) (0.5×tcyc-10)ns.min th(BCLK-CS) 4ns.min CSi td(AD-ALE) ADi /DBi (0.5×tcyc-25)ns.min th(ALE-AD) (0.5×tcyc-15)ns.min Address tdZ(RD-AD) 8ns.max Data input Address tac3(RD-DB) (1.5×tcyc-45)ns.max tsu(DB-RD) 40ns.min th(RD-DB) 0ns.min td(AD-RD) td(BCLK-AD) 25ns.max 0ns.min th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) −4ns.min th(RD-AD) (0.5×tcyc-10)ns.min td(BCLK-RD) 25ns.max ALE th(BCLK-RD) 0ns.min RD Write timing BCLK td(BCLK-CS) 25ns.max tcyc th(WR-CS) (0.5×tcyc-10)ns.min th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min ADi /DBi Address Data output Address td(AD-ALE) (0.5×tcyc-25)ns.min td(DB-WR) (1.5×tcyc-40)ns.min th(WR-DB) (0.5×tcyc-10)ns.min th(BCLK-AD) 4ns.min td(BCLK-AD) 25ns.max ADi BHE td(BCLK-ALE) 25ns.max th(BCLK-ALE) −4ns.min td(AD-WR) 0ns.min th(WR-AD) (0.5×tcyc-10)ns.min ALE td(BCLK-WR) 25ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH Measuring conditions · VCC1=VCC2=5V · Input timing voltage : V IL=0.8V, VIH=2.0V · Output timing voltage : V OL=0.4V, VOH=2.4V Figure 5.10 Timing Diagram (8) Page 63 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection ) Read timing tcyc BCLK td(BCLK-CS) 25ns.max th(RD-CS) (0.5×tcyc-10)ns.min th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5×tcyc-25)ns.min th(ALE-AD) (0.5×tcyc-15)ns.min Data input ADi /DBi ADi BHE (no multiplex) Address td(BCLK-AD) 25ns.max tdZ(RD-AD) td(AD-RD) 0ns.min 8ns.max (2.5×tcyc-45)ns.max th(RD-DB) tac3(RD-DB) tsu(DB-RD) 40ns.min 0ns.min th(BCLK-AD) 4ns.min td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5×tcyc-10)ns.min ALE th(BCLK-RD) td(BCLK-RD) 25ns.max 0ns.min RD Write timing tcyc BCLK th(WR-CS) (0.5×tcyc-10)ns.min th(BCLK-CS) 4ns.min td(BCLK-CS) 25ns.max CSi td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min ADi /DBi Address Data output td(AD-ALE) (0.5×tcyc-25)ns.min td(BCLK-AD) 25ns.max td(DB-WR) (2.5×tcyc-40)ns.min th(WR-DB) (0.5×tcyc-10)ns.min th(BCLK-AD) 4ns.min ADi BHE (no multiplex) td(BCLK-ALE) 25ns.max th(BCLK-ALE) -4ns.min th(WR-AD) td(AD-WR) 0ns.min (0.5×tcyc-10)ns.min ALE th(BCLK-WR) td(BCLK-WR) WR, WRL WRH tcyc= 1 f(BCLK) 25ns.max 0ns.min Measuring conditions · VCC1=VCC2=5V · Input timing voltage : V IL=0.8V, VIH=2.0V · Output timing voltage : V OL=0.4V, VOH=2.4V Figure 5.11 Timing Diagram (9) Page 64 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Table 5.30 Symbol VOH HIGH Output Voltage (3) Electrical Characteristics (1) Parameter (1) Measuring Condition IOH=−1mA IOH=−1mA (2) IOH=−0.1mA IOH=−50µA With no load applied With no load applied IOL=1mA Min. Standard Typ. Max. VCC1 Unit P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 VCC1−0.5 VCC2−0.5 VCC1−0.5 VCC1−0.5 2.5 1.6 V VCC2 VCC1 VCC1 V V 0.5 VOH HIGH Output Voltage HIGH Output Voltage XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER VOL LOW Output Voltage (3) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 IOL=1mA (2) V 0.5 VOL LOW Output Voltage LOW Output Voltage XOUT XCOUT HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER IOL=0.1mA IOL=50µA With no load applied With no load applied 0.5 0.5 0 0 0.2 0.8 V V VT+-VT- Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK4, TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2, SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4 RESET P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1, XIN, RESET, CNVSS, BYTE VI=3V V VT+-VTIIH Hysteresis HIGH Input Current (3) 0.2 (0.7) 1.8 V 4.0 µA IIL LOW Input Current (3) VI=0V −4.0 µA RPULLUP Pull-Up Resistance (3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 VI=0V to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1 50 100 500 kΩ RfXIN RfXCIN VRAM Feedback Resistance XIN Feedback Resistance XCIN RAM Retention Voltage At stop mode 3.0 25 2.0 MΩ MΩ V NOTES: 1. Referenced to VCC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz no wait unless otherwise specified. 2. VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13 3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 65 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Table 5.31 Symbol ICC Electrical Characteristics (2) (1) Parameter Measuring Condition Mask ROM f(BCLK)=10MHz No division No division, On-chip oscillation Min. Standard Typ. Max. 8 1 8 1.8 12 22 25 25 420 45 6.0 1.8 0.7 0.6 0.4 3.0 4 2 13 11 Unit mA mA mA mA mA mA µA µA µA µA µA µA µA µA µA Power Supply Current In single-chip (VCC1=VCC2=2.7V to 3.6V) mode, the output pins are open and other pins are VSS Flash Memory f(BCLK)=10MHz, No division No division, On-chip oscillation Flash Memory Program Flash Memory Erase Mask ROM Flash Memory f(BCLK)=10MHz, VCC1=3.0V f(BCLK)=10MHz, VCC1=3.0V f(XCIN)=32kHz Low power dissipation mode, ROM (3) f(BCLK)=32kHz Low power dissipation mode, RAM (3) f(BCLK)=32kHz Low power dissipation mode, Flash Memory (3) On-chip oscillation, Wait mode Mask ROM Flash Memory f(BCLK)=32kHz Wait mode (2), Oscillation capability High f(BCLK)=32kHz Wait mode (2), Oscillation capability Low Stop mode Topr =25°C Idet4 Idet3 Low Voltage Detection Dissipation Current Reset Area Detection Dissipation Current (4) (4) NOTES: 1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=10MHz unless otherwise specified. 2. With one timer operated using fC32. 3. This indicates the memory in which the program to be executed exists. 4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled). Idet4: VC27 bit in the VCR2 register Idet3: VC26 bit in the VCR2 register Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 66 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.32 Symbol tc tw(H) tw(L) tr tf External Clock Input (XIN input)(1) Parameter External Clock Input Cycle Time External Clock Input HIGH Pulse Width External Clock Input LOW Pulse Width External Clock Rise Time External Clock Fall Time Standard Min. Max. (NOTE 2) (NOTE 3) (NOTE 3) (NOTE 4) (NOTE 4) Unit ns ns ns ns ns NOTES: 1. The condition is VCC1=VCC2=2.7 to 3.0V. 2. Calculated according to the VCC1 voltage as follows: 10 –6 --------------------------------------- [ns] 20 × V C C2 – 44 3. Calculated according to the VCC1 voltage as follows: 10 --------------------------------------- × 0.4 [ns] 20 × V C C1 – 44 –6 4. Calculated according to the VCC1 voltage as follows: – 10 × V C C1 + 45 [ns] Table 5.33 Symbol tac1(RD-DB) tac2(RD-DB) tac3(RD-DB) tsu(DB-RD) tsu(RDY-BCLK) tsu(HOLD-BCLK) th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) Memory Expansion Mode and Microprocessor Mode Parameter Data Input Access Time (for setting with no wait) Data Input Access Time (for setting with wait) Data Input Access Time (when accessing multiplex bus area) Data Input Setup Time RDY Input Setup Time HOLD Input Setup Time Data Input Hold Time RDY Input Hold Time HOLD Input Hold Time Standard Min. Max. (NOTE 1) (NOTE 2) (NOTE 3) Unit ns ns ns ns ns ns ns ns ns 50 40 50 0 0 0 NOTES: 1. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 60 [ ns ] f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 ( n – 0.5 ) x10 ----------------------------------- – 60 [ ns ] f ( BCLK ) 9 ( n – 0.5 ) x10 ----------------------------------- – 60 [ ns ] f ( BCLK ) n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: n is “2” for 2-wait setting, “3” for 3-wait setting. Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 67 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.34 Symbol tc(TA) tw(TAH) tw(TAL) TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Timer A Input (Counter Input in Event Counter Mode) Parameter Standard Min. 150 60 60 Max. Unit ns ns ns Table 5.35 Symbol tc(TA) tw(TAH) tw(TAL) Timer A Input (Gating Input in Timer Mode) Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 600 300 300 Max. Unit ns ns ns Table 5.36 Symbol tc(TA) tw(TAH) tw(TAL) Timer A Input (External Trigger Input in One-shot Timer Mode) Parameter TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 300 150 150 Max. Unit ns ns ns Table 5.37 Symbol tw(TAH) tw(TAL) Timer A Input (External Trigger Input in Pulse Width Modulation Mode) Parameter TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Standard Min. 150 150 Max. Unit ns ns Table 5.38 Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) Timer A Input (Counter Increment/Decrement Input in Event Counter Mode) Parameter TAiOUT Input Cycle Time TAiOUT Input HIGH Pulse Width TAiOUT Input LOW Pulse Width TAiOUT Input Setup Time TAiOUT Input Hold Time Standard Min. 3000 1500 1500 600 600 Max. Unit ns ns ns ns ns Table 5.39 Symbol tc(TA) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) Timer A Input (Two-phase Pulse Input in Event Counter Mode) Parameter TAiIN Input Cycle Time TAiOUT Input Setup Time TAiIN Input Setup Time Standard Min. 2 500 500 Max. Unit µs ns ns Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 68 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.40 Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Timer B Input (Counter Input in Event Counter Mode) Parameter TBiIN Input Cycle Time (counted on one edge) TBiIN Input HIGH Pulse Width (counted on one edge) TBiIN Input LOW Pulse Width (counted on one edge) TBiIN Input Cycle Time (counted on both edges) TBiIN Input HIGH Pulse Width (counted on both edges) TBiIN Input LOW Pulse Width (counted on both edges) Standard Min. 150 60 60 300 120 120 Max. Unit ns ns ns ns ns ns Table 5.41 Symbol tc(TB) tw(TBH) tw(TBL) Timer B Input (Pulse Period Measurement Mode) Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 600 300 300 Max. Unit ns ns ns Table 5.42 Symbol tc(TB) tw(TBH) tw(TBL) Timer B Input (Pulse Width Measurement Mode) Parameter TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Standard Min. 600 300 300 Max. Unit ns ns ns Table 5.43 Symbol tc(AD) tw(ADL) A/D Trigger Input Parameter ADTRG Input Cycle Time ADTRG Input LOW Pulse Width Standard Min. 1500 200 Max. Unit ns ns Table 5.44 Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial Interface Parameter CLKi Input Cycle Time CLKi Input HIGH Pulse Width CLKi Input LOW Pulse Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RXDi Input Hold Time Standard Min. 300 150 150 0 100 90 Max. Unit ns ns ns ns ns ns ns 160 Table 5.45 Symbol tw(INH) tw(INL) External Interrupt INTi Input Parameter INTi Input HIGH Pulse Width INTi Input LOW Pulse Width Standard Min. 380 380 Max. Unit ns ns Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 69 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.46 Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) Memory Expansion and Microprocessor Modes (for setting with no wait) Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR) (3) HLDA Output Delay Time Standard Min. Max. 30 4 0 (NOTE 2) 30 4 25 −4 30 0 30 0 40 4 (NOTE 1) (NOTE 2) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns See Figure 5.12 NOTES: 1. Calculated according to the BCLK frequency as follows: 9 0.5x10 f(BCLK) is 12.5MHz or less. ----------------------- – 40 [ ns ] f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = −CR X ln (1−VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time of output ”L” level is t = −30pF X 1k Ω X In(1−0.2VCC2 / VCC2) = 6.7ns. R DBi C P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 30pF Figure 5.12 Ports P0 to P14 Measurement Circuit Page 70 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.47 Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external area access) Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time ALE Signal Output Hold Time RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) (3) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR)(3) HLDA Output Delay Time Standard Min. Max. 30 4 0 (NOTE 2) 30 4 25 See Figure 5.12 -4 30 0 30 0 40 4 (NOTE 1) (NOTE 2) 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) td(BCLK-ALE) th(BCLK-ALE) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) NOTES: 1. Calculated according to the BCLK frequency as follows: 9 ( n – 0.5 ) x10 ----------------------------------- – 40 [ ns ] f ( BCLK ) n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting. (BCLK) is 12.5MHz or less. 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 10 [ ns ] f ( BCLK ) 3. This standard value shows the timing when the output is off, and does not show hold time of data bus. Hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. Hold time of data bus is expressed in t = −CR X ln (1−VOL / VCC2) by a circuit of the right figure. For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time of output ”L” level is t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2) = 6.7ns. R DBi C Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 71 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.48 Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area access and multiplex bus selection) Parameter Address Output Delay Time Address Output Hold Time (in relation to BCLK) Address Output Hold Time (in relation to RD) Address Output Hold Time (in relation to WR) Chip Select Output Delay Time Chip Select Output Hold Time (in relation to BCLK) Chip Select Output Hold Time (in relation to RD) Chip Select Output Hold Time (in relation to WR) RD Signal Output Delay Time RD Signal Output Hold Time WR Signal Output Delay Time WR Signal Output Hold Time Data Output Delay Time (in relation to BCLK) Data Output Hold Time (in relation to BCLK) Data Output Delay Time (in relation to WR) Data Output Hold Time (in relation to WR) HLDA Output Delay Time ALE Signal Output Delay Time (in relation to BCLK) ALE Signal Output Hold Time (in relation to BCLK) ALE Signal Output Delay Time (in relation to Address) ALE Signal Output Hold Time (in relation to Address) RD Signal Output Delay From the End of Address WR Signal Output Delay From the End of Address Address Output Floating Start Time Standard Min. Max. 50 4 (NOTE 1) (NOTE 1) 50 4 (NOTE 1) (NOTE 1) 40 0 40 See Figure 5.12 0 50 4 (NOTE 2) (NOTE 1) 40 25 −4 (NOTE 3) (NOTE 4) 0 0 Symbol td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(BCLK-DB) th(BCLK-DB) td(DB-WR) th(WR-DB) td(BCLK-HLDA) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(AD-ALE) td(AD-RD) td(AD-WR) tdz(RD-AD) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 NOTES: 1. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 10 [ ns ] f ( BCLK ) 2. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 50 [ ns ] f ( BCLK ) n is “2” for 2-wait setting, “3” for 3-wait setting. 3. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 40 [ ns ] f ( BCLK ) 4. Calculated according to the BCLK frequency as follows: 9 0.5x10 ----------------------- – 15 [ ns ] f ( BCLK ) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 72 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V XIN input tr tw(H) tf tc tw(L) tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During Event Counter Mode TAiIN input (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-Phase Pulse Input in Event Counter Mode TAiIN input tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN) th(TIN-UP) tsu(UP-TIN) tc(TA) TAiOUT input tsu(TAOUT-TAIN) tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input Figure 5.13 Timing Diagram (1) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 73 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics VCC1=VCC2=3V tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi tw(INL) INTi input tw(INH) Figure 5.14 Timing Diagram (2) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 74 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) VCC1=VCC2=3V BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY−BCLK) th(BCLK−RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD−BCLK) th(BCLK−HOLD) HOLD input HLDA output td(BCLK−HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 (1) Hi−Z td(BCLK−HLDA) NOTES: 1. These pins are set to high-impedance regardless of the input level of the BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register. Measuring conditions : · VCC1=VCC2=3V · Input timing voltage : Determined with V IL=0.6V, VIH=2.4V · Output timing voltage : Determined with V OL=1.5V, VOH=1.5V Figure 5.15 Timing Diagram (3) Rev.2.41 Jan 10, 2006 REJ03B0001-0241 Page 75 of 96 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (for setting with no wait ) Read timing VCC1=VCC2=3V BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 × tcyc-60)ns.max DBi Hi-Z tsu(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi tcyc td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 × tcyc-10)ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR, WRL, WRH td(BCLK-DB) 40ns.max Hi-Z th(BCLK-DB) 4ns.min DBi td(DB-WR) (0.5 × tcyc-40)ns.min th(WR-DB) (0.5 × tcyc-10)ns.min tcyc= 1 f(BCLK) Measuring conditions · VCC1=VCC2=3V · Input timing voltage : V IL=0.6V, VIH=2.4V · Output timing voltage : V OL=1.5V, VOH=1.5V Figure 5.16 Timing Diagram (4) Page 76 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access ) Read timing BCLK td(BCLK−CS) 30ns.max VCC1=VCC2=3V th(BCLK−CS) 4ns.min CSi tcyc td(BCLK−AD) 30ns.max th(BCLK−AD) 4ns.min ADi BHE td(BCLK−ALE) 30ns.max th(BCLK−ALE) −4ns.min th(RD−AD) 0ns.min ALE td(BCLK−RD) 30ns.max th(BCLK−RD) 0ns.min RD tac2(RD−DB) (1.5 × tcyc−60)ns.max DBi Hi−Z th(RD−DB) tsu(DB−RD) 50ns.min 0ns.min Write timing BCLK td(BCLK−CS) 30ns.max th(BCLK−CS) 4ns.min CSi tcyc td(BCLK−AD) 30ns.max th(BCLK−AD) 4ns.min ADi BHE td(BCLK−ALE) 30ns.max th(BCLK−ALE) −4ns.min th(WR−AD) (0.5 × tcyc−10)ns.min td(BCLK−WR) 30ns.max ALE th(BCLK−WR) 0ns.min WR,WRL, WRH td(BCLK−DB) 40ns.max Hi−Z th(BCLK−DB) 4ns.min DBi td(DB−WR) tcyc= 1 f(BCLK) (0.5 × tcyc−40)ns.min th(WR−DB) (0.5 × tcyc−10)ns.min Measuring conditions · VCC1=VCC2=3V · Input timing voltage : V IL=0.6V, VIH=2.4V · Output timing voltage : V OL=1.5V, VOH=1.5V Figure 5.17 Timing Diagram (5) Page 77 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (for 2-wait setting and external area access ) Read timing tcyc BCLK td(BCLK-CS) 30ns.max CSi td(BCLK-AD) 30ns.max ADi BHE td(BCLK-ALE) 30ns.max ALE td(BCLK-RD) 30ns.max RD tac2(RD-DB) (2.5 × tcyc-60)ns.max VCC1=VCC2=3V th(BCLK-CS) 4ns.min th(BCLK-AD) 4ns.min th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min th(BCLK-RD) 0ns.min DBi Hi-Z tsu(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 30ns.max CSi td(BCLK-AD) 30ns.max ADi BHE td(BCLK-ALE) 30ns.max ALE td(BCLK-WR) 30ns.max WR, WRL WRH td(BCLK-DB) 40ns.max DBi Hi-Z th(BCLK-CS) 4ns.min th(BCLK-AD) 4ns.min th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 × tcyc-10)ns.min th(BCLK-WR) 0ns.min th(BCLK-DB) 4ns.min td(DB-WR) tcyc= 1 f(BCLK) (1.5 × tcyc-40)ns.min th(WR-DB) (0.5 × tcyc-10)ns.min Measuring conditions · VCC1=VCC2=3V · Input timing voltage : V IL=0.6V, VIH=2.4V · Output timing voltage : V OL=1.5V, VOH=1.5V Figure 5.18 Timing Diagram (6) Page 78 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (for 3-wait setting and external area access ) Read timing tcyc BCLK td(BCLK-CS) 30ns.max VCC1 = VCC2 = 3V th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac2(RD-DB) (3.5 × tcyc-60)ns.max DBi Hi-Z tsu(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing tcyc BCLK td(BCLK-CS) 30ns.max th(BCLK-CS) 4ns.min CSi td(BCLK-AD) 30ns.max th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 30ns.max th(BCLK-ALE) -4ns.min th(WR-AD) (0.5 × tcyc-10)ns.min ALE td(BCLK-WR) 30ns.max th(BCLK-WR) 0ns.min WR, WRL WRH td(BCLK-DB) 40ns.max th(BCLK-DB) 4ns.min DBi Hi-Z td(DB-WR) tcyc= 1 f(BCLK) (2.5 × tcyc-40)ns.min th(WR-DB) (0.5 × tcyc-10)ns.min Measuring conditions · VCC1=VCC2=3V · Input timing voltage : V IL=0.6V, VIH=2.4V · Output timing voltage : V OL=1.5V, VOH=1.5V Figure 5.19 Timing Diagram (7) Page 79 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (For 2-wait setting, external area access and multiplex bus selection ) Read timing BCLK td(BCLK-CS) 40ns.max VCC1=VCC2=3V tcyc th(RD-CS) (0.5×tcyc-10)ns.min th(BCLK-CS) 4ns.min CSi td(AD-ALE) (0.5×tcyc-40)ns.min ADi /DBi Address th(ALE-AD) (0.5×tcyc-15)ns.min tdZ(RD-AD) 8ns.max Data input Address tac3(RD-DB) (1.5×tcyc-60)ns.max tsu(DB-RD) 50ns.min th(RD-DB) 0ns.min td(AD-RD) td(BCLK-AD) 40ns.max 0ns.min th(BCLK-AD) 4ns.min ADi BHE td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5×tcyc-10)ns.min td(BCLK-RD) 40ns.max ALE th(BCLK-RD) 0ns.min RD Write timing BCLK td(BCLK-CS) 40ns.max tcyc th(WR-CS) (0.5×tcyc-10)ns.min th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 50ns.max th(BCLK-DB) 4ns.min ADi /DBi Address Data output Address td(AD-ALE) (0.5×tcyc-40)ns.min td(DB-WR) (1.5×tcyc-50)ns.min th(WR-DB) (0.5×tcyc-10)ns.min th(BCLK-AD) 4ns.min td(BCLK-AD) 40ns.max ADi BHE td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min td(AD-WR) 0ns.min th(WR-AD) (0.5×tcyc-10)ns.min ALE td(BCLK-WR) 40ns.max th(BCLK-WR) 0ns.min WR,WRL, WRH tcyc= 1 f(BCLK) Measuring conditions · VCC1=VCC2=3V · Input timing voltage : V IL=0.6V, VIH=2.4V · Output timing voltage : V OL=1.5V, VOH=1.5V Figure 5.20 Timing Diagram (8) Page 80 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode (For 3-wait setting, external area access and multiplex bus selection) Read timing tcyc BCLK td(BCLK-CS) 40ns.max VCC1=VCC2=3V th(RD-CS) (0.5×tcyc-10)ns.min th(BCLK-CS) 6ns.min CSi td(AD-ALE) (0.5×tcyc-40)ns.min th(ALE-AD) ADi /DBi 40ns.max (0.5×tcyc-15)ns.min Data input Address td(BCLK-AD) ADi BHE (No multiplex) tdZ(RD-AD) td(AD-RD) 0ns.min 8ns.max (2.5×tcyc-60)ns.max th(RD-DB) tac3(RD-DB) tsu(DB-RD) 50ns.min 0ns.min th(BCLK-AD) 4ns.min td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min th(RD-AD) (0.5×tcyc-10)ns.min ALE td(BCLK-RD) 40ns.max th(BCLK-RD) 0ns.min RD Write timing tcyc BCLK td(BCLK-CS) 40ns.max th(WR-CS) (0.5×tcyc-10)ns.min th(BCLK-CS) 4ns.min CSi td(BCLK-DB) 50ns.max th(BCLK-DB) 4ns.min ADi /DBi Address Data output td(AD-ALE) (0.5×tcyc-40)ns.min td(BCLK-AD) 40ns.max td(DB-WR) (2.5×tcyc-50)ns.min th(WR-DB) (0.5×tcyc-10)ns.min th(BCLK-AD) 4ns.min ADi BHE (No multiplex) td(BCLK-ALE) 40ns.max th(BCLK-ALE) -4ns.min th(WR-AD) td(AD-WR) 0ns.min (0.5×tcyc-10)ns.min ALE th(BCLK-WR) td(BCLK-WR) WR, WRL WRH tcyc= 1 f(BCLK) 40ns.max 0ns.min Measuring conditions · VCC1=VCC2=3V · Input timing voltage : V IL=0.6V, VIH=2.4V · Output timing voltage : V OL=1.5V, VOH=1.5V Figure 5.21 Timing Diagram (9) Page 81 of 96 Rev.2.41 Jan 10, 2006 REJ03B0001-0241 M16C/62P Group (M16C/62P, M16C/62PT) 5. Electrical Characteristics 5.2 Electrical Characteristics (M16C/62PT) Absolute Maximum Ratings Parameter Supply Voltage Analog Supply Voltage Input Voltage RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, VREF, XIN P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 P7_0, P7_1 Output Voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1, XOUT P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7 P7_0, P7_1 Power Dissipation Operating Ambient Temperature When the Microcomputer is Operating Condition VCC1=VCC2=AVCC VCC1=VCC2=AVCC Rated Value −0.3 to 6.5 −0.3 to 6.5 Unit V V Table 5.49 Symbol VCC1, VCC2 AVCC VI −0.3 to VCC1+0.3 (1) V −0.3 to VCC2+0.3 (1) −0.3 to 6.5 −0.3 to VCC1+0.3 (1) V V V VO −0.3 to VCC2+0.3 (1) −0.3 to 6.5 −40°C VCC2 17-18 Table 1.10 to 1.11 NOTE 1 VCC1 VCC2 → VCC1 > VCC2 31 12 18, 20 19,21 24 25 33 34 35 37 Table 5.2 Power Supply Ripple Allowable Frequency Unit MHz → kHz Table 1.9 and Figure 1.5 are added. Table 1.11 to 1.13 are revised. Table 1.12 to 1.14 are revised. Figure 3.1 is partly revised. Note 3 is added. Note 6 is added. Table 5.3 is revised. Note 2 in Table 5.4 is added. Table 5.5 to 5.6 is partly revised. Table 5.8 is revised. Table 5.9 is revised. Table 5.11 is revised. 2.30 Sep 01, 2004 C-2 REVISION HISTORY Rev. Date Page 40 57 70 72 73 74 76 79 2.41 Jan 01, 2006 2-4 7 8 9 10 11 12 13 14 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Summary Table 5.24 is partly revised. Table 5.43 is partly revised. Table 5.48 is partly revised. Table 5.50 is partly revised. Table 5.53 is partly revised. Table 5.55 is revised. Table 5.57 is partly revised. Table 5.69 is partly revised. voltage down detection reset -> brown-out detection Reset Tables 1.1 to 1.3 Performance outline of M16C/62P group are partly revised. Table 1.4 Product List (1) is partly revised. Note 1 is added. Table 1.5 Product List (2) is partly revised. Note 1, 2 and 3 are added. Table 1.6 Product List (3) is partly revised. Note 1 and 2 are added. Table 1.7 Product List (4) is partly revised. Note 1 and 2 are added. Figure 1.3 Type No., Memory Size, Shows RAM capacity, and Package is partly revised Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P is partly revised. Table 1.9 Product Code of Flash Memory version for M16C/62P is partly revised. Figure 1.6 Pin Configuration (Top View) is partly revised. 15-17 Tables 1.10 to 1.12 Pin Characteristics for 128-Pin Package are added. 18-19 Figure 1.7 and 1.8 Pin Configuration (Top View) are partly revised. 20-21 Tables 1.13 to 1.14 Pin Characteristics for 100-Pin Package are added. 22 Figure 1.9 Pin Configuration (Top View) is partly revised. 23-24 Tables 1.15 to 1.16 Pin Characteristics for 80-Pin Package are added. 25-29 Tables 1.17 to 1.21 are partly revised. 34 43 45 Note 4 of Table 4.1 SFR Information is partly revised. Table 5.4 A/D Conversion Characteristics is partly revised. Table 5.6 Flash Memory Version Electrical Characteristics for 100 cycle products is partly revised. Table 5.7 Flash Memory Version Electrical Characteristics for 10,000 cycle products is partly revised. Table 5.8 Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics is partly revised. 46 Table 5.9 Low Voltage Detection Circuit Electrical Characteristics is partly revised. C-3 REVISION HISTORY Rev. Date Page 47 48 49 50 67 85 M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual Description Summary Figure 5.1 Power Supply Circuit Timing Diagram is partly revised. Table 5.11 Electrical Characteristics (1) is partly deleted. Table 5.12 Electrical Characteristics (2) is partly revised. Note 1 of Table 5.13 External Clock Input (XIN input) is added. Notes 1 to 4 of Table 5.32 External Clock Input (XIN input) are added. Table 5.53 Flash Memory Version Electrical Characteristics for 100 cycle products is partly revised. Standard (Min.) is partly revised. Table 5.54 Flash Memory Version Electrical Characteristics for 10,000 cycle products is partly revised. Standard (Min.) is partly revised. Note 5 is revised. Table 23.55 Flash Memory Version Program / Erase Voltage and Read Operation Voltage Characteristics is partly revised. Table 5.57 Electrical Characteristics (1) is partly deleted. Table 5.58 Electrical Characteristics is partly revised. 87 88 C-4 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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