To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
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You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
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When exporting the products or technology described in this document, you should comply with the applicable export control
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“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”:
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
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M16C/1N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0002-0100Z
Rev.1.00
2004.10.20
1. Overview
The M16C/1N group consists of single-chip microcomputers that use high-performance silicon gate CMOS
processes and have a on-chip M16C/60 series CPU core. The microcomputers are housed in 48-pin plastic
mold QFP package. These single-chip microcomputers have both high function instructions and high instruction efficiency and feature a one-megabyte address space and the capability to execute instructions at
high speed.
1.1 Applications
Automotive and industrial control systems, other automobile, other
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 1 of 29
M16C/1N Group
1. Overview
1.2 Performance Overview
Table 1.1 gives an overview of the M16C/1N group performance specification.
Table 1.1 Performance overview
Item
Number of basic instructions
Shortest instruction execution time
Memory
ROM
size
RAM
I/O port
Multifunction T1
timer
TX, TY, TZ
TC
Serial I/O (UART or clock synchronous)
A/D converter
(maximum resolution: 10 bits)
D/A converter
CAN controller
Watchdog timer
Interrupts
Clock generating circuits
Power supply voltage
Power consumption
I/O
I/O withstand voltage
characteristics Output current
Device configuration
Package
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 2 of 29
Performance
91 instructions
62.5 ns (when f(XIN)=16MHz)
See Table 1.2 Performance overview
See Table 1.2 Performance overview
P0 to P5: 37 lines
8 bits x 1
8 bits x 3
16 bits x 1
x2
x 12 channels
(Expandable up to 14 channels)
8 bits x 1
1 channel, 2.0B active
15 bits x 1 (with prescaler)
15 internal causes, 8 external causes, 4 software causes
3 internal circuits
4.2 V to 5.5V (when f(XIN)=16MHz)
70mW(VCC=5.0V, f(XIN)=16MHz)
5V
5mA (10mA:LED drive port)
CMOS silicon gate
48-pin LQFP
M16C/1N Group
1. Overview
1.3 Block Diagram
Figure 1.1 shows block diagram of the M16C/1N group.
8
I/O ports
Port P0
2
8
8
Port P3
Port P2
Port P1
8
Port P4
Internal peripheral functions
Timer
Timer 1 (8 bits)
Timer X (8 bits)
Timer Y (8 bits)
Timer Z (8 bits)
Timer C (16 bits)
A/D converter
D/A converter
(10 bits X 12 channels,
(8 bits X 1 channel)
expandable to 14 channels)
System clock generator
XIN-XOUT
XCIN-XCOUT
On-chip oscillation
UART/clock synchronous SI/O
(8 bits X 2 channels)
CAN controller (1 channel)
M16C/60 series 16-bit CPU core
Registers
Watchdog timer
(15 bits)
R0H
R0H
R1H
R0L
R0L
R1L
R2
R3
A0
A1
FB
SB
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Figure 1.1 Block diagram
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 3 of 29
Program counter
PC
Stack pointers
ISP
USP
Memory
ROM
(Note 1)
RAM
(Note 2)
Vector table
INTB
Flag register
FLG
Multiplier
3
Port P5
M16C/1N Group
1. Overview
1.4 Performance Overview
Table 1.2 shows performance overview.
Table 1.2 Performance overview
Type No.
M301N2M4T-XXXFP(D)
M301N2M8T-XXXFP(D)
M301N2F8TFP(D)
M301N2F8FP(D)
(D): Under development
Type No.
ROM
32Kbytes
RAM
1Kbytes
64Kbytes
3Kbytes
Package
As of June 2004
Remarks
Mask ROM
48P6Q-A
Flash memory
M30 1N 2 M 4 T - XXX FP
Package type:
FP: Package 48P6Q-A
ROM No.
Omitted for flash memory version
Indicates differences in characteristics and usage etc:
Nothing: Common
T:
Automobiles
ROM size:
4: 32 Kbytes
8: 64 Kbytes
Memory type:
M: Mask ROM version
F: Flash memory version
Indicates pin count, etc
(The value itself has no specific meaning)
M16C/1N Group
M16C Family
Figure 1.2 Type No., memory size, and package
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 4 of 29
M16C/1N Group
1. Overview
1.5 Pin Configuration
36
35
34
33
32
31
30
29
28
27
26
25
P07/AN0
IVCC
P30/TXOUT
VSS
P31/TZOUT
VCC
P40/ANEX0
P41/ANEX1
P42/INT3
P43/INT1
P32/TYOUT
P33/TCIN
Figure 1.3 shows pin configurations (top view) of the M16C/1N group.
37
38
39
40
41
42
43
44
45
46
47
48
M16C/1N Group
24
23
22
21
20
19
18
17
16
15
14
13
P44/INT2
P45/INT0
P10/KI0/AN8
P11/KI1/AN9
P12/KI2/AN10
P20
NC
P21
P13/KI3/AN11
P14/TxD0
P15/RxD0
P16/CLK0
P36/CLK1
P35/RxD1
P34/CLKS1/DA
CNVSS
P47/XCIN
P46/XCOUT
RESET
XOUT
VSS
XIN
VCC
P17/CNTR0
1
2
3
4
5
6
7
8
9
10
11
12
P06/AN1
P05/AN2
P04/AN3
VREF
P52
P51(CRx)(Note 1)
P50(CTx)(Note 1)
P03/AN4/CRx(Note 1)
P02/AN5/CTx(Note 1)
P01/AN6
P00/AN7
P37/TxD1/RxD1
Package: 48P6Q-A
Note 1: Either P02, P03 or P50, P51 can be selected as CAN0 I/O ports by software.
Figure 1.3 Pin configuration diagram (top view)
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 5 of 29
M16C/1N Group
1. Overview
1.6 Pin Description
Table 1.3 shows the pin description.
Table 1.3 Pin Description
Pin name
I/O type
Signal name
Function
VCC, VSS
Power supply
input
Input
IVCC
IVCC
Input
Connect a capacitor (0.1 µF) between this pin and VSS.
CNVSS
CNVSS
Input
Connect it to the VSS pin via resistance (about 5 kΩ).
RESET
Reset input
Input
A "L" on this input resets the microcomputer.
XIN
Clock input
Input
XOUT
Clock output
Output
These pins are provided for the main clock oscillation circuit.
Connect a ceramic resonator or crystal between the XIN and
XOUT pins. To use an externally derived clock, input it to the XIN
pin and leave the XOUT pin open.
VREF
Reference
voltage input
Input
P00 to P07
I/O port P0
Input/output
This is an 8-bit CMOS I/O port. It has an input/output port
direction register that allows the user to set each pin for input or
output individually. When set for input, the user can specify in
units of four bits via software whether or not they are tied to a
pull-up resistor. These pins are shared with analog input pins.
P02 and P03 function as CAN0 I/O pins by using software.
P10 to P17
I/O port P1
Input/output
This is an 8-bit I/O port equivalent to P0. P10 to P13 are shared
with analog inputs and key input interrupts. P14 to P16 are
shared with serial I/O pins. P17 is shared with timer input. Can
be used as an LED drive port.
P20 to P21
I/O port P2
Input/output
This is a 2-bit I/O port equivalent to P0.
P30 to P37
I/O port P3
Input/output
This is a 8-bit I/O port equivalent to P0. P30 to P33 are shared
with timer input/output. P34 to P37 are shared with serial I/O.
P34 is shared with analog outputs.
P40 to P47
I/O port P4
Input/output
This is a 8-bit I/O port equivalent to P0. P40 to 41 are shared
with analog inputs. P42 to P45 are shared with interrupt inputs.
P46 to P47 are shared with the I/O pin of the clock oscillation
circuit for the clock.
P50 to P52
I/O port P5
Input/output
This is a 3-bit I/O port equivalent to P0. P50 and P51 function as
CAN0 I/O pins by using software.
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 6 of 29
Supply 4.2 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
This pin is a reference voltage input for the A/D converter.
M16C/1N Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2
R0H (R0's high bits) R0L (R0's low bits)
R3
R1H (R1's high bits) R1L (R1's low bits)
Data registers (Note 1)
R2
R3
A0
Address registers (Note 1)
A1
FB
Frame base registers (Note 1)
b19
b0
INTBH
Interrupt table register
INTBL
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
Flag register
b8 b7
IPL
U
b0
I
O B S
Z
D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note 1: These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
2.1 Data Registers (R0, R1, R2, and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The A0 register consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 7 of 29
M16C/1N Group
2. Central Processing Unit (CPU)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
This flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0”; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is set to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is set to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt request is enabled.
2.8.10 Reserved Area
When white to this bit, write “0”. When read, its content is indeterminate.
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
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M16C/1N Group
3. Memory
3. Memory
Figure 3.1 is a memory map. The address space extends the 1M bytes from address 0000016 to FFFFF16.
From FFFFF16 down is ROM. For example, in the M301N2M4T-XXXFP, there is 32K bytes of internal ROM
from F800016 to FFFFF16. The vector table for fixed interrupts such as the reset are mapped to FFFDC16 to
FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for
timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts
for details.
From 0040016 up is RAM. For example, in the M301N2M4T-XXXFP, there is 1K byte of internal RAM from
0040016 to 007FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A/D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area
(For details, refer to
4. SFR)
FFE0016
0040016
Internal RAM area
XXXXX16
Special page
vector table
FFFDC16
YYYYY16
Internal ROM area
FFFFF16
Type No.
M301N2M4T
FFFFF 16
Internal RAM
Size
Address XXXXX16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
UART0 reception
Reset
Internal ROM
Size
Address YYYYY16
1 Kbytes
007FF16
32 Kbytes
F800016
3 Kbytes
00FFF16
64 Kbytes
F000016
M301N2M8T
M301N2F8TFP
M301N2F8FP
Figure 3.1 Memory map
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
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M16C/1N Group
4. Special Function Registers (SFR)
4. Special Function Registers (SFR)
Address
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Register
Symbol
After reset
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
PM0
PM1
CM0
CM1
XXXX0X002
00XXX0X02
4816
2016
Address match interrupt enable register
Protect register
AIER
PRCR
XXXXXX002
XXXXX0002
Oscillation stop detection register
CM2
Watchdog timer start register
Watchdog timer control register
WDTS
WDC
Address match interrupt register 0
RMAD0
Address match interrupt register 1
RMAD1
000000002
000000002
XXXX00002
INT0 input filter select register
INT0F
XXXXX0002
0416
XX16
000XXXXX2
000000002
000000002
XXXX00002
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
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M16C/1N Group
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
4. Special Function Registers (SFR)
Register
Symbol
After reset
CAN0 wakeup interrupt control register
CAN0 state/error interrupt control register
C01WKIC
C01ERRIC
XXXXX0002
XXXXX0002
CAN0 reception successful interrupt control register
CAN0 transmission successful interrupt control register
C0RECIC
C0TRMIC
XXXXX0002
XXXXX0002
Key input interrupt control register
A/D conversion interrupt control register
KUPIC
ADIC
XXXXX0002
XXXXX0002
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer 1 interrupt control register
Timer X interrupt control register
Timer Y interrupt control register
Timer Z interrupt control register
CNTR0 interrupt control register
TCIN interrupt control register
Timer C interrupt control register
INT3 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
S0TIC
S0RIC
S1TIC
S1RIC
T1IC
TXIC
TYIC
TZIC
CNTR0IC
TCINIC
TCIC
INT3IC
INT0IC
INT1IC
INT2IC
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XX00X0002
XX00X0002
XX00X0002
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
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M16C/1N Group
Address
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
009016
009116
009216
009316
009416
009516
009616
009716
009816
009916
009A16
009B16
009C16
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
4. Special Function Registers (SFR)
Register
Timer Y, Z mode register
Prescaler Y
Timer Y secondary
Timer Y primary
Timer Y, Z waveform output control register
Prescaler Z
Timer Z secondary
Timer Z primary
Prescaler 1
Timer 1
Timer Y, Z output control register
Timer X mode register
Prescaler X
Timer X
Timer count source set register
Clock prescaler reset flag
Symbol
TYZMR
PREY
TYSC
TYPR
PUM
PREZ
TZSC
TZPR
PRE1
T1
TYZOC
TXMR
PREX
TX
TCSS
CPSRF
After reset
000000X02
FF16
FF16
FF16
0016
FF16
FF16
FF16
XX16
XX16
XXXXX0002
000000002
FF16
FF16
0016
0XXXXXXX2
XX16
XX16
Timer C counter
TC
External input enable register
INTEN
0016
Key input enable register
KIEN
0016
Timer C control register 0
Timer C control register 1
TCC0
TCC1
Time measurement register
TM
0XX000002
XXXXXX112
XX16
XX16
UART0 transmit/receive mode register
UART0 bit rate generator
U0MR
U0BRG
UART0 transmit buffer register
U0TB
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
U0C0
U0C1
UART0 receive buffer register
U0RB
UART1 transmit/receive mode register
UART1 bit rate generator
U1MR
U1BRG
UART1 transmit buffer register
U1TB
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
U1C0
U1C1
UART1 receive buffer register
U1RB
UART transmit/receive control register 2
UCON
0016
XX16
XX16
XX16
0816
XXXX00102
XX16
XX16
0016
XX16
XX16
XX16
0816
XXXX00102
XX16
XX16
X00000002
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 12 of 29
M16C/1N Group
Address
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
4. Special Function Registers (SFR)
Register
Symbol
After reset
XX16
XX16
A/D register
AD
A/D control register 2
ADCON2
XXXX00002
A/D control register 0
A/D control register 1
D/A register
ADCON0
ADCON1
DA
00000XXX2
0016
XX16
D/A control register
DACON
XXXXX0X02
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
XX16
XX16
0016
0016
XX16
XX16
XXXXXX002
0016
XX16
XX16
0016
XXXXX0002
CAN0 I/O port select register
CIOSR
XXXXXXX02
Pull-up control register 0
Pull-up control register 1
Port P1 drive capacity control register
PUR0
PUR1
DRR
00X000002
XXXXX0002
0016
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 13 of 29
M16C/1N Group
Address
010016
010116
010216
010316
010416
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
023016
023116
023216
023316
023416
023516
023616
023716
023816
023916
023A16
023B16
023C16
023D16
023E16
023F16
4. Special Function Registers (SFR)
Register
Symbol
After reset
Flash memory control register 4 (Note 2)
FMR4
010000002
Flash memory control register 1 (Note 2)
FMR1
0000XX0X2
Flash memory control register 0 (Note 2)
FMR0
XX0000012
CAN0 message control register 0
CAN0 message control register 1
CAN0 message control register 2
CAN0 message control register 3
CAN0 message control register 4
CAN0 message control register 5
CAN0 message control register 6
CAN0 message control register 7
CAN0 message control register 8
CAN0 message control register 9
CAN0 message control register 10
CAN0 message control register 11
CAN0 message control register 12
CAN0 message control register 13
CAN0 message control register 14
CAN0 message control register 15
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
CAN0 control register
C0CTLR
CAN0 status register
C0STR
CAN0 slot status register
C0SSTR
CAN0 interrupt control register
C0ICR
CAN0 extended ID register
C0IDR
CAN0 configuration register
C0CONR
CAN0 receive error count register
CAN0 transmit error count register
C0RECR
C0TECR
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
X00000012
XX0X00002
0016
X00000012
000016
000016
000016
000016
000016
000016
XX16
XX16
0016
0016
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Note 2: These registers are available on flash memory versions only.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 14 of 29
M16C/1N Group
Address
024016
024116
024216
024316
024416
024516
024616
024716
024816
024916
024A16
024B16
024C16
024D16
024E16
024F16
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
026016
026116
026216
026316
026416
026516
026616
026716
026816
026916
026A16
026B16
026C16
026D16
026E16
026F16
027016
027116
027216
027316
027416
027516
027616
027716
027816
027916
027A16
027B16
027C16
027D16
027E16
027F16
4. Special Function Registers (SFR)
Register
Symbol
CAN0 acceptance filter support register
C0AFS
CAN0 clock select register
CCLKR
CAN0 slot 0: Identifier / DLC
CAN0 slot 0: Data Field
CAN0 slot 0: Time Stamp
CAN0 slot 1: Identifier / DLC
CAN0 slot 1: Data Field
CAN0 slot 1: Time Stamp
After reset
XX16
XX16
X000XXXX2
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 15 of 29
M16C/1N Group
Address
028016
028116
028216
028316
028416
028516
028616
028716
028816
028916
028A16
028B16
028C16
028D16
028E16
028F16
029016
029116
029216
029316
029416
029516
029616
029716
029816
029916
029A16
029B16
029C16
029D16
029E16
029F16
02A016
02A116
02A216
02A316
02A416
02A516
02A616
02A716
02A816
02A916
02AA16
02AB16
02AC16
02AD16
02AE16
02AF16
02B016
02B116
02B216
02B316
02B416
02B516
02B616
02B716
02B816
02B916
02BA16
02BB16
02BC16
02BD16
02BE16
02BF16
4. Special Function Registers (SFR)
Register
CAN0 slot 2: Identifier / DLC
CAN0 slot 2: Data Field
CAN0 slot 2: Time Stamp
CAN0 slot 3: Identifier / DLC
CAN0 slot 3: Data Field
CAN0 slot 3: Time Stamp
CAN0 slot 4: Identifier / DLC
CAN0 slot 4: Data Field
CAN0 slot 4: Time Stamp
CAN0 slot 5: Identifier / DLC
CAN0 slot 5: Data Field
CAN0 slot 5: Time Stamp
Symbol
After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 16 of 29
M16C/1N Group
Address
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
02EB16
02EC16
02ED16
02EE16
02EF16
02F016
02F116
02F216
02F316
02F416
02F516
02F616
02F716
02F816
02F916
02FA16
02FB16
02FC16
02FD16
02FE16
02FF16
4. Special Function Registers (SFR)
Register
CAN0 slot 6: Identifier / DLC
CAN0 slot 6: Data Field
CAN0 slot 6: Time Stamp
CAN0 slot 7: Identifier / DLC
CAN0 slot 7: Data Field
CAN0 slot 7: Time Stamp
CAN0 slot 8: Identifier / DLC
CAN0 slot 8: Data Field
CAN0 slot 8: Time Stamp
CAN0 slot 9: Identifier / DLC
CAN0 slot 9: Data Field
CAN0 slot 9: Time Stamp
Symbol
After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 17 of 29
M16C/1N Group
Address
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
4. Special Function Registers (SFR)
Register
CAN0 slot 10: Identifier / DLC
CAN0 slot 10: Data Field
CAN0 slot 10: Time Stamp
CAN0 slot 11: Identifier / DLC
CAN0 slot 11: Data Field
CAN0 slot 11: Time Stamp
CAN0 slot 12: Identifier / DLC
CAN0 slot 12: Data Field
CAN0 slot 12: Time Stamp
CAN0 slot 13: Identifier / DLC
CAN0 slot 13: Data Field
CAN0 slot 13: Time Stamp
Symbol
After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 18 of 29
M16C/1N Group
Address
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
4. Special Function Registers (SFR)
Register
Symbol
CAN0 slot 14: Identifier / DLC
CAN0 slot 14: Data Field
CAN0 slot 14: Time Stamp
CAN0 slot 15: Identifier / DLC
CAN0 slot 15: Data Field
CAN0 slot 15: Time Stamp
CAN0 Global mask
CAN0 local mask A
CAN0 local mask B
C0GMR
C0LMAR
C0LMBR
After reset
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
03B416
03B516
03B616
03B716
03B816
03B916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Note 1: Location in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
X : Undefined
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 19 of 29
M16C/1N Group
5. Electrical Characteristics
5. Electrical Characteristics
Table 5.1 Absolute maximum ratings
Symbol
Parameter
Vcc
Supply voltage
VI
Input voltage
Rated value
Unit
- 0.3 to 6.5
V
RESET, VREF, XIN
P00 to P07, P10 to P17, P20, P21,
P30 to P37, P40 to P47, P50 to P52, CNVss (Note 1)
- 0.3 to Vcc + 0.3
V
P00 to P07, P10 to P17, P20, P21, P30 to P37,
P40 to P47, P50 to P52, XOUT
- 0.3 to Vcc + 0.3
V
VO
Output voltage
Pd
Power dissipation
Topr
Operating ambient temperature
Tstg
Storage temperature
Condition
IVCC
Topr = 25 ˚C
Note 1: CNVSS pin of flash memory version: -0.3 to 6.5 V
Note 2: When flash memory version is program/erase mode: 0 to 60 °C
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 20 of 29
- 0.3 to 2.8V
V
300
mW
- 40 to 85 (Note 2)
˚C
- 65 to 150
˚C
M16C/1N Group
5. Electrical Characteristics
Table 5.2 Recommended operating conditions
(Unless otherwise noted: VCC = 4.2V to 5.5V, Topr = -40 to 85oC)
Symbol
Standard
Parameter
Min
Typ.
Max.
4.2
5.0
5.5
Unit
Vcc
Supply voltage
Vss
Supply voltage
VIH
HIGH input
voltage
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
P50 to P52, XIN, RESET, CNVSS
0.8Vcc
Vcc
V
VIL
LOW input
voltage
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
P50 to P52, XIN, RESET, CNVSS
0
0.2Vcc
V
IOH (peak)
HIGH peak
output current
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
P50 to P52
- 10.0
mA
IOH
HIGH average
output current
P00 to P07, P10 to P17, P20, P21, P30 to P37, P40 to P47,
P50 to P52
- 5.0
mA
LOW peak
output current
P00 to P07, P20, P21, P30 to P37, P40 to P47, P50 to P52
10.0
mA
P10 to P17
HIGH POWER
20.0
LOW POWER
10.0
(avg)
IOL (peak)
IOL (avg)
LOW average
output current
0
P00 to P07, P20, P21, P30 to P37, P40 to P47, P50 to P52
P10 to P17
f (XIN)
Main clock input oscillation frequency (Note 3)
f (XcIN)
Subclock oscillation frequency
5.0
HIGH POWER
10.0
LOW POWER
5.0
Vcc=4.2V to 5.5V
0
32.768
V
V
mA
mA
mA
16
MHz
50
kHz
Highest operation frequency [MHz]
Note 1: The average output current is an average value measured over 100ms.
Note 2: Keep output current as follows:
The sum of port P00 to P03, P13 to P17, P21, P34 to P37, P46, P47, P50 to P52 IOL (peak) is under 60
mA. The sum of port P00 to P03, P13 to P17, P21, P34 to P37, P46, P47, P50 to P52 IOH (peak) is
under 60 mA. The sum of port P04 to P07, P10 to P12, P20, P30 to P33, P40 to P45 IOL (peak) is under
60 mA. The sum of port P04 to P07, P10 to P12, P20, P30 to P33, P40 to P45 IOH (peak) is under 60
mA.
Note 3: Relationship between main clock oscillation frequency and supply voltage is shown as below.
Main clock input oscillation frequency
16.0
0.0
4.2
Power supply voltage [V]
(Main clock: no division)
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 21 of 29
5.5
M16C/1N Group
5. Electrical Characteristics
Table 5.3 Electrical characteristics (1)
(Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = -40 to 85oC, f(XIN) = 16MHz)
Parameter
Symbol
VOH
VOH
VOH
VOL
VOL
VOL
VOL
VT+ -VT-
Measuring condition
HIGH output P00 to P07,P10 to P17,P20 to P21, IOH = - 5 mA
P30 to P37,P40 to P47,P50 to P52
voltage
IOH = - 200 µA
Min.
Standard
Typ. Max.
3.0
V
4.7
HIGH output XOUT
voltage
HIGH POWER
IOH = - 1 mA
3.0
LOW POWER
IOH = - 0.5 mA
3.0
HIGH output XCOUT
voltage
HIGH POWER
No load
2.5
LOW POWER
No load
1.6
LOW output P00 to P07,P20,P21,P30 to P37,
voltage
P40 to P47,P50 to P52
V
IOL = 5 mA
V
2.0
IOL = 200 µA
0.45
LOW output P10 to P17
voltage
HIGH POWER
IOL = 10 mA
2.0
LOW POWER
IOL = 5 mA
2.0
LOW output XOUT
voltage
HIGH POWER
IOH = 1 mA
2.0
LOW POWER
IOH = 0.5 mA
2.0
LOW output XCOUT
voltage
HIGH POWER
No load
0
LOW POWER
No load
0
Hysteresis
Unit
V
V
V
V
CNTR0,TCIN,
INT0 to INT3,CLK0,CLK1,P45
RxD0,RxD1,KI0 to KI3,CRX0
0.2
0.8
V
0.2
1.8
V
VT+ -VT-
Hysteresis
RESET
IIH
HIGH input
current
P00 to P07,P10 to P17,P20,P21,
VI = 5V
P30 to P37,P40 to P47,P50 to P52,
XIN,RESET,CNVss
5.0
µA
LOW input
current
P00 to P07,P10 to P17,P20,P21,
VI = 0V
P30 to P37,P40 to P47,P50 to P52,
XIN,RESET,CNVss
-5.0
µA
167.0
kΩ
IIL
RPULLUP Pull-up
resistor
P00 to P07,P10 to P17,P20,P21,
VI = 0V
P30 to P37,P40 to P47,P50 to P52
RfXIN
Feedback
resistor
XIN
RfXCIN
Feedback
resistor
XCIN
VRAM
RAM retention voltage
ROSC
Oscillation frequency of
On-chip oscillator
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
When clock is stopped
30.0
50.0
1.0
MΩ
15.0
MΩ
2.0
V
Mask ROM
Flash memory
page 22 of 29
300
600
1200
kHz
M16C/1N Group
5. Electrical Characteristics
Table 5.4 Electrical characteristics (2)
(Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = 25oC, f(XIN) = 16MHz)
Parameter
Symbol
Icc
Measuring condition
I/O pin Mask ROM
has no
load
Flash memory
Power supply current
Mask ROM
Min.
f(XIN) = 16 MHz
Square wave, no division
On-chip oscillator mode
No division
Flash memory
Mask ROM
On-chip oscillator mode
When a WAIT instruction
is executed
Flash memory
Mask ROM
f(XCIN) = 32 kHz
Square wave
Flash memory
Mask ROM
Flash memory
Mask ROM
f(XCIN) = 32 kHz
When a WAIT instruction
is executed
f(XCIN) = 32 kHz
When a WAIT instruction
is executed
Topr = 25 ˚C when clock
is stopped
Flash memory
Standard
Typ. Max.
Unit
12.0
22.0
mA
14.0
24.0
mA
300
µA
800
µA
60
µA
100
µA
20
µA
450
µA
2
µA
2
µA
0.8
3
µA
0.8
3
µA
Table 5.5 Power supply timing circuit characteristics
Symbol
td(P-R)
td(R-S)
td(W-S)
td(M-L)
Parameter
Timer for internal power supply stabilization during powering-on
Stop release time
Wait release time during low power dissipation mode
Timer for internal power supply stabilization when main clock oscillation starts
Measuring condition
VCC = 4.2 to 5.5 V
Interrupt for
stop or wait mode
release
CPU clock
td(R-S)
td(W-S)
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 23 of 29
Min.
Standard
Typ. Max.
Unit
2
ms
150
µs
150
µs
150
µs
M16C/1N Group
5. Electrical Characteristics
Table 5.6 Flash memory version electrical characteristics
(Unless otherwise noted: Vcc = 4.2 to 5.5 V, Topr= 0 to 60oC)
Symbol
Parameter
Erase/write cycle (Note 2)
Word programming time
Block erasing time
2Kbyte block
8Kbyte block
16Kbyte block
32Kbyte block
td(SR-ES) Transition time from erasure operation
to erase-suspend
Data retention
-
Min.
100 (Note 3)
Standard
Typ. (Note 1)
75
0.2
0.4
0.7
1.2
10
Max.
Unit
600
9
9
9
9
cycle
µs
s
s
s
s
20
ms
year
Note1: Vcc=5.0V, Topr=25˚C
Note2: Definition of Programming and erasure times
The Programming and erasure times are defined to be per-block erasure times. For example a case where a 2Kbyte block is programmed in 1,024 operations by writing one word at a time and erased thereafter. Performing
multiple programs to the same address before an erase operation is prohibited.
Note 3: Minimum number of programming/erasure for which operation is guaranteed.
Erasure-suspend
request
(Interrupt request)
FMR46
td(SR-ES)
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 24 of 29
M16C/1N Group
5. Electrical Characteristics
Table 5.7 A/D conversion characteristics
(Unless otherwise noted: VCC = VREF = 5V, VSS = 0V at Topr = 25oC, f(XIN) = 16MHz)
Symbol
Parameter
Measuring condition
Min.
Resolution
VREF =VCC
Absolute Sample & hold function not available
VREF =VCC = 5V
accuracy Sample & hold function available(10bit) VREF =VCC = 5V AN0 to AN11 input
ANEX0, ANEX1 input,
external op-amp
connected mode
Sample & hold function available(8bit) VREF =VCC = 5V
Standard
Typ. Max.
10
Unit
±3
±3
Bits
LSB
LSB
±7
LSB
±2
LSB
RLADDER
Ladder resistance
VREF =VCC
10
tCONV
Conversion time(10bit)
f(XIN)=10MHz, ØAD=fAD=10MHz
3.3
µs
tCONV
tSAMP
VREF
Conversion time(8bit)
Sampling time
Reference voltage
f(XIN)=10MHz, ØAD=fAD=10MHz
f(XIN)=10MHz, ØAD=fAD=10MHz
2.8
0.3
µs
µs
f(XIN)=10MHz, ØAD=fAD=10MHz
2
VCC
V
VIA
Analog input voltage
f(XIN)=10MHz, ØAD=fAD=10MHz
0
VREF
V
40
k
Note 1: Divide the fAD if f(XIN) exceeds 10MHz, and make AD operation clock frequency (ØAD) equal to or
lower than 10MHz.
Table 5.8 D/A conversion characteristics
(Unless otherwise noted: VCC = VREF = 5V, VSS = 0V at Topr = 25oC, f(XIN) = 16MHz)
Symbol
tsu
RO
IVREF
Parameter
Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current
Measuring condition
Min.
4
(Note 1)
Standard
Typ. Max.
8
1.0
3
10
20
1.5
Unit
Bits
%
µs
k
mA
Note 1: The A/D converter's ladder resistance is not included.
When D/A register contents are not "0016", the current IVREF always flows even though VREF may
have been set to be unconnected by the A/D control register.
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 25 of 29
M16C/1N Group
5. Electrical Characteristics
5.1 Timing requirements
(Unless otherwise noted: VCC = 5V, VSS = 0V at Topr = -40 to 85oC)
Table 5.9 XIN input
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(XIN)
XIN input cycle time
62.5
ns
twH(XIN)
twL(XIN)
XIN input HIGH pulse width
30
ns
XIN input LOW pulse width
30
ns
Table 5.10 CNTR0 input
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(CNTR0)
CNTR0 input cycle time
CNTR0 input HIGH pulse width
100
40
ns
twH(CNTR0)
twL(CNTR0)
CNTR0 input LOW pulse width
40
ns
ns
Table 5.11 TCIN input
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(TCIN)
TCIN input cycle time
TCIN input HIGH pulse width
400(Note 1)
200(Note 2)
ns
twH(TCIN)
twL(TCIN)
TCIN input LOW pulse width
200(Note 2)
ns
ns
Note 1: Use the greater value, either (1/digital filter clock frequency X 6) or min. value.
Note 2: Use the greater value, either (1/digital filter clock frequency X 3) or min. value.
Table 5.12 Serial I/O
Symbol
Standard
Min.
Max.
Parameter
Unit
tc(CK)
CLKi input cycle time
CLKi input HIGH pulse width
200
100
ns
tw(CKH)
tw(CKL)
CLKi input LOW pulse width
100
ns
td(C-Q)
th(C-Q)
TxDi output delay time
tsu(D-C)
th(C-D)
ns
80
ns
0
ns
RxDi input setup time
30
ns
RxDi input hold time
90
ns
TxDi hold time
_______
Table 5.13 External interrupt INTi input
Symbol
tw(INH)
tw(INL)
Standard
Min.
Max.
Parameter
250(Note 1)
250(Note 2)
INTi input HIGH pulse width
INTi input LOW pulse width
_______
Unit
ns
ns
_______
Note 1: When the INT0 input filter select bit selects the digital filter, use the INT0 input HIGH pulse width
to the greater value, either (1/digital filter clock frequency X 3) or min. value.
_______
_______
Note 2: When the INT0 input filter select bit selects the digital filter, use the INT0 input LOW pulse width to
the greater value, either (1/digital filter clock frequency X 3) or min. value.
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 26 of 29
M16C/1N Group
5. Electrical Characteristics
P0
30pF
P1
P2
P3
P4
P5
Figure 5.1 Port P0 to P5 measurement circuit
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 27 of 29
M16C/1N Group
5. Electrical Characteristics
tc(CNTR0)
tWH(CNTR0)
CNTR0 input
tWL(CNTR0)
tc(TCIN)
tWH(TCIN)
TCIN input
tWL(TCIN)
tc(XIN)
tWH(XIN)
XIN input
tWL(XIN)
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TxDi
tsu(D-C)
td(C-Q)
RxDi
tw(INL)
INTi input
tw(INH)
Figure 5.2 Vcc=5V timing diagram
Rev.1.00 Oct 20, 2004
REJ03B0002-0100Z
page 28 of 29
th(C-D)
M16C/1N Group
Package Dimension
Package Dimension
Recommended
48P6Q-A
EIAJ Package Code
LQFP48-P-77-0.50
Plastic 48pin 7✕7mm body LQFP
Weight(g)
–
Lead Material
Cu Alloy
MD
ME
e
JEDEC Code
–
b2
HD
D
48
37
1
I2
Recommended Mount Pad
36
E
HE
Symbol
25
12
13
24
A
F
L1
A3
A2
e
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
y
b
x
Detail F
M
Rev.1.00 Oct 20, 2004
REJ030002-0100Z
L
page 29 of 29
Lp
c
A1
A3
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
1.7
0.1
0.2
0
–
–
1.4
0.17
0.22
0.27
0.105
0.125
0.175
6.9
7.0
7.1
6.9
7.0
7.1
–
0.5
–
8.8
9.0
9.2
8.8
9.0
9.2
0.35
0.5
0.65
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.08
–
–
0.1
–
0°
8°
–
–
0.225
1.0
–
–
–
–
7.4
–
–
7.4
M16C/1N Group Data Sheet
REVISION HISTORY
Rev.
Description
Summary
Date
Page
1.00 Oct 20, 2004
–
First edition issued (Renesas Technology version)
A-1
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits,
(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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