To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
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8.
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11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
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M32C/8B Group
RENESAS MCU
1.
REJ03B0242-0100
Rev.1.00
Nov 01, 2009
Overview
1.1
Features
The M32C/8B Group is a single-chip control MCU, fabricated using high-performance silicon gate CMOS
technology, embedding the M32C/80 Series CPU core. The M32C/8B Group is housed in 144-pin and 100-pin
plastic molded LQFP packages.
With a 16-Mbyte address space, this MCU combines advanced instruction manipulation capabilities to process
complex instructions by less bytes and execute instructions at higher speed.
The M32C/8B Group has a multiplier and DMAC adequate for office automation, communication devices and
industrial equipment, and other high-speed processing applications.
1.1.1
Applications
• Audio-Visual equipment (e.g. televisions, audio components)
• Home Appliances (e.g. air conditioners, washing machines, sewing machines)
• Industrial equipment (e.g. programmable logic controllers)
• Computers and peripherals, cameras, etc.
1.1.2
Specifications
Tables 1.1 to 1.4 list the specifications of the M32C/8B Group.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 1 of 67
M32C/8B Group
Table 1.1
Item
CPU
1. Overview
Specifications (144-Pin Package) (1/2)
Function
Central processing unit
Specification
M32C/80 core (multiplier: 16 bits × 16 bits → 32 bits,
multiply-addition operation instructions: 16 × 16 + 48 → 48 bits)
• Basic instructions: 108
• Minimum instruction execution time:
31.3 ns (f(CPU) = 32 MHz / VCC1 = 3.0 to 5.5 V)
• Operating modes: Single-chip mode, memory expansion mode,
and microprocessor mode
Memory
ROM / RAM
Flash memory version: 256KB + 8KB/32 KB, 128KB + 8KB/32 KB
ROMless version
: − / 32KB
Power Supply Voltage Detection
Voltage monitor interrupt (optional)(1)
External
Bus / memory expansion • Address space: 16 Mbytes
Bus
function
• External bus interface: 1 to 7 wait states can be inserted,
Expansion
4 chip select outputs, 3 V and 5 V interfaces
• Bus format: Switchable between separate bus and multiplexed
bus formats, switchable data bus width (8-bit or 16-bit)
Clock
Clock generation circuits • 4 circuits:
Main clock, sub clock, on-chip oscillator,
PLL frequency synthesizer
• Oscillation stop detection:
Main clock oscillation stop detect function
• Frequency divider circuit:
Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16
• Low power consumption features: Wait mode, stop mode
Interrupts
• Interrupt vectors: 70
• External interrupt inputs:
11 (NMI, INT × 6, Key input × 4)
Single-chip mode
Memory expansion and microprocessor mode with 8-bit external bus
8 (NMI, INT × 3, Key input × 4)
Memory expansion and microprocessor mode with 16-bit external bus
• Interrupt priority levels: 7
Watchdog Timer
15-bit × 1 channel (with prescaler)
DMA
DMAC
• 4 channels, cycle steal method
• Trigger sources: 31
• Transfer modes: 2 (single transfer and repeat transfer)
DMACII
• Can be activated by all peripheral function interrupt sources
• Transfer modes: 2 (single transfer and burst transfer)
• Immediate transfer, calculation transfer, and chain transfer
functions
Timer
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode,
pulse width modulation (PWM) mode
Event counter 2-phase pulse signal processing (2-phase
encoder input) × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse period measurement
mode, pulse width measurement mode
Timer function for
3-phase inverter control × 1 (using timer A1, timer A2, timer A4,
3-phase motor control
and timer B2)
On-chip dead time timer
NOTE:
1. Please contact a Renesas sales office for optional features.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 2 of 67
M32C/8B Group
Table 1.2
Item
Serial
Interface
1. Overview
Specifications (144-Pin Package) (2/2)
Function
UART0 to UART4
A/D Converter
D/A Converter
CRC Calculation Circuit
Specification
Clock synchronous / asynchronous × 5
I2C bus, special mode 2, GCI mode, SIM mode
IEBus (optional)(1)(2)
10-bit resolution x 34 channels (in single-chip mode)
10-bit resolution x 18 channels (in memory expansion mode
and microprocessor mode)
including sample and hold function
8-bit resolution × 2 channels
CRC-CCITT (X16 + X12 + X5 + 1) compliant
X/Y Converter
16 bits x 16 bits
I/O Ports
Programmable I/O ports • Input only: 1
• CMOS I/O:
121 (in single-chip mode)
81 (in memory expansion and microprocessor mode with 8-bit external bus)
73 (in memory expansion and microprocessor mode with 16-bit external bus)
with selectable pull-up resistor
• N channel open drain ports: 2
Flash Memory
• Erase and program voltage: VCC1 = VCC2 = 3.0 V to 5.5 V
• Erase and program endurance: 100 times (all areas)
• Program security: ROM code protect and ID code check
• Debug functions: On-chip debug and on-board flash reprogram
Operating Frequency /
32 MHz / VCC1 = 3.0 V to 5.5 V, VCC2 = 3.0 V to VCC1
Supply Voltage
Current Consumption
26 mA (32 MHz, VCC1 = VCC2 = 5 V)
23 mA (32 MHz, VCC1 = VCC2 = 3.3 V)
110 μA (approx. 1 MHz, VCC1 = VCC2 = 3.3 V,
on-chip oscillator low-power consumption mode → wait mode)
8 μA (approx. 32 kHz / VCC1 = VCC2 = 3.3 V,
low-power consumption mode → wait mode)
4 μA (VCC1 = VCC2 = 3.3 V, stop mode)
Operating Ambient Temperature (°C) -20 to 85°C, -40 to 85°C (optional)(2)
Package
144-pin LQFP (PLQP0144KA-A)
NOTES:
1. IEBus is a registered trademark of NEC Electronics Corporation.
2. Please contact a Renesas sales office for optional features.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 3 of 67
M32C/8B Group
Table 1.3
Item
CPU
1. Overview
Specifications (100-Pin Package) (1/2)
Function
Central processing unit
Specification
M32C/80 core (multiplier: 16 bits × 16 bits → 32 bits,
multiply-addition operation instructions: 16 × 16 + 48 → 48 bits)
• Basic instructions: 108
• Minimum instruction execution time:
31.3 ns (f(CPU) = 32 MHz / VCC1 = 3.0 to 5.5 V)
• Operating modes: Single-chip mode, memory expansion mode,
and microprocessor mode
Memory
ROM / RAM
Flash memory version: 256KB + 8KB/32 KB, 128KB + 8KB/32 KB
ROMless version
: − / 32KB
Power Supply Voltage Detection
Voltage monitor interrupt (optional)(1)
External
Bus / memory expansion • Address space: 16 Mbytes
Bus
function
• External bus interface: 1 to 7 wait states can be inserted,
Expansion
4 chip select outputs, 3 V and 5 V interfaces
• Bus format: Switchable between separate bus and multiplexed
bus formats, switchable data bus width (8-bit or 16-bit)
Clock
Clock generation circuits • 4 circuits:
Main clock, sub clock, on-chip oscillator,
PLL frequency synthesizer
• Oscillation stop detection:
Main clock oscillation stop detect function
• Frequency divider circuit:
Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16
• Low power consumption features: Wait mode, stop mode
Interrupts
• Interrupt vectors: 70
• External interrupt inputs:
11 (NMI, INT × 6, Key input × 4)
Single-chip mode
Memory expansion and microprocessor mode with 8-bit external bus
8 (NMI, INT × 3, Key input × 4)
Memory expansion and microprocessor mode with 16-bit external bus
• Interrupt priority levels: 7
Watchdog Timer
15-bit × 1 channel (with prescaler)
DMA
DMAC
• 4 channels, cycle steal method
• Trigger sources: 31
• Transfer modes: 2 (single transfer and repeat transfer)
DMACII
• Can be activated by all peripheral function interrupt sources
• Transfer modes: 2 (single transfer and burst transfer)
• Immediate transfer, calculation transfer, and chain transfer
functions
Timer
Timer A
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode,
pulse width modulation (PWM) mode
Event counter 2-phase pulse signal processing (2-phase
encoder input) × 3
Timer B
16-bit timer × 6
Timer mode, event counter mode, pulse period measurement
mode, pulse width measurement mode
Timer function for
3-phase inverter control × 1 (using timer A1, timer A2, timer A4,
3-phase motor control
and timer B2)
On-chip dead time timer
NOTE:
1. Please contact a Renesas sales office for optional features.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 4 of 67
M32C/8B Group
Table 1.4
Item
Serial
Interface
1. Overview
Specifications (100-Pin Package) (2/2)
Function
UART0 to UART4
A/D Converter
D/A Converter
CRC Calculation Circuit
Specification
Clock synchronous / asynchronous × 5
I2C bus, special mode 2, GCI mode, SIM mode
IEBus (optional)(1)(2)
10-bit resolution x 26 channels (in single-chip mode)
10-bit resolution x 10 channels (in memory expansion mode and
microprocessor mode)
including sample and hold function
8-bit resolution × 2 channels
CRC-CCITT (X16 + X12 + X5 + 1) compliant
X/Y Converter
16 bits x 16 bits
I/O Ports
Programmable I/O ports • Input only: 1
• CMOS I/O:
85 (in single-chip mode)
45 (in memory expansion and microprocessor mode with 8-bit external bus)
37 (in memory expansion and microprocessor mode with 16-bit external bus)
with selectable pull-up resistor
• N channel open drain ports: 2
Flash Memory Version
• Erase and program voltage: VCC1 = VCC2 = 3.0 V to 5.5 V
• Erase and program endurance: 100 times (all areas)
• Program security: ROM code protect and ID code check
• Debug functions: On-chip debug and on-board flash reprogram
Operating Frequency /
32 MHz: VCC1 = 3.0 V to 5.5 V, VCC2 = 3.0 to VCC1
Supply Voltage
Current Consumption
26 mA (32 MHz, VCC1 = VCC2 = 5 V)
23 mA (32 MHz, VCC1 = VCC2 = 3.3 V)
110 μA (approx. 1 MHz, VCC1 = VCC2 = 3.3 V,
on-chip oscillator low-power consumption mode → wait mode)
8 μA (approx. 32 kHz / VCC1 = VCC2 = 3.3 V,
low-power consumption mode → wait mode)
4 μA (VCC1 = VCC2 = 3.3 V, stop mode)
Operating Ambient Temperature (°C) -20 to 85°C, -40 to 85°C (optional)(2)
Package
100-pin LQFP (PLQP0100KB-A)
NOTES:
1. IEBus is a registered trademark of NEC Electronics Corporation.
2. Please contact a Renesas sales office for optional features.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 5 of 67
M32C/8B Group
1.2
1. Overview
Product List
Table 1.5 lists product information. Figure 1.1 shows product numbering system.
Table 1.5
Product List
Part Number
M308B8FGGP
M308B6FGGP
M308B8FCGP
M308B6FCGP
M308B8SGP
M308B6SGP
Current as of Oct. 2009
Package Code
(P)
(P)
PLQP0144KA-A (144P6Q-A)
PLQP0100KB-A (100P6Q-A)
PLQP0144KA-A (144P6Q-A)
PLQP0100KB-A (100P6Q-A)
PLQP0144KA-A (144P6Q-A)
PLQP0100KB-A (100P6Q-A)
ROM
Capacity
256 KB
+ 8KB(1)
128 KB
+ 8KB(1)
RAM
Capacity
Remarks
Flash memory
32 KB
−
ROMless
(P): Under planning
NOTE:
1. Additional 8-Kbyte space is available for data flash memory.
Part No. M30 8B x F G GP
Package type option
GP: PLQP0144KA-A (144P6Q-A)
GP: PLQP0100KB-A (100P6Q-A)
ROM capacity
C: 128 Kbytes
G: 256 Kbytes
Memory Type
F: Flash memory version
S: ROMless version
RAM capacity, pin count, etc.
(The value itself has no specific meaning.)
M32C/8B Group
M16C Family
Figure 1.1
Product Numbering System
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 6 of 67
M32C/8B Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a block diagram of the M32C/8B Group.
8
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Internal peripheral functions
10-bit A/D converter:
1 circuit, 34 input (2)
Timers (16-bit)
Output (timer A): 5
Input (timer B): 6
Clock generation circuits:
XIN-XOUT
XCIN-XCOUT
On-chip oscillator
PLL frequency synthesizer
8-bit D/A converters:
2 circuits
Three-phase motor
control circuit
DMAC: 4 channels
DMACII
Watchdog timer (15 bits)
M32C/80 Series CPU core
Serial Interface: 5 channels
R0H
R0L
R1H
R1L
FLG
ISP
R3
USP
A0
SVF
FB
SVP
SB
VCT
(1)
Port P13
8
Multiplier
(1)
Port P12
ROM
PC
A1
X/Y converter:
16 bits × 16 bits
RAM
INTB
R2
CRC calculation circuit
X16 + X12 + X5 + 1 (CCITT)
Memory
(1)
Port P11
8
5
(1)
Port P15
8
(1)
Port P14
7
Port P10
8
Port P9
8
P8_5
Port P8
7
NOTES:
1. Ports P11 to P15 are provided in the 144-pin package only.
2. 34 channels are available in the 144-pin package. 26 channels are available in the 100-pin package.
Figure 1.2
Block Diagram
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 7 of 67
M32C/8B Group
1.4
1. Overview
Pin Assignments
Figures 1.3 and 1.4 show pin assignments (top view).
73
74
75
76
77
78
79
80
81
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
82
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
M32C/8B Group
PLQP0144KA-A
(144P6Q-A)
(top view)
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
P4_4 / CS3 / A20
P4_5 / CS2 / A21
P4_6 / CS1 / A22
P4_7 / CS0 / A23
P12_5
P12_6
P12_7
P5_0 / WRL / WR
P5_1 / WRH / BHE
P5_2 / RD
P5_3 / CLKOUT / BCLK / ALE
P13_0
P13_1
VCC2
P13_2
VSS
P13_3
P5_4 / HLDA / ALE
P5_5 / HOLD
P5_6 / ALE
P5_7 / RDY
P13_4
P13_5
P13_6
P13_7
P6_0 / CTS0 / RTS0 / SS0
P6_1 / CLK0
P6_2 / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
P6_4 / CTS1 / RTS1 / SS1
P6_5 / CLK1
VSS
P6_6 / RXD1 / SCL1 / STXD1
VCC1
P6_7 / TXD1 / SDA1 / SRXD1
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 (1)
ANEX1 / TXD4 / SDA4 / SRXD4
ANEX0 / CLK4
DA1 / SS4 / RTS4 / CTS4 / TB4IN
DA0 / SS3 / RTS3 / CTS3 / TB3IN
SRXD3 / SDA3 / TXD3 / TB2IN
STXD3 / SCL3 / RXD3 / TB1IN
CLK3 / TB0IN
/ P9_6
/ P9_5
/ P9_4
/ P9_3
/ P9_2
/ P9_1
/ P9_0
P14_6
P14_5
P14_4
P14_3
P14_2
P14_1
P14_0
BYTE
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
VSS
XIN
VCC1
NMI / P8_5
INT2 / P8_4
INT1 / P8_3
INT0 / P8_2
U / TA4IN / P8_1
U / TA4OUT / P8_0
TA3IN / P7_7
TA3OUT / P7_6
W / TA2IN / P7_5
W / TA2OUT / P7_4
SS2 / RTS2 / CTS2 / V / TA1IN / P7_3
CLK2 / V / TA1OUT / P7_2
(1) STXD2 / SCL2 / RXD2 / TB5IN / TA0IN / P7_1
( note 2 )
98
99
100
101
102
103
104
105
106
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
1
D8 / P1_0
AN0_7 / P0_7
AN0_6 / P0_6
AN0_5 / P0_5
AN0_4 / P0_4
P11_4
P11_3
P11_2
P11_1
P11_0
D3 / AN0_3 / P0_3
D2 / AN0_2 / P0_2
D1 / AN0_1 / P0_1
D0 / AN0_0 / P0_0
AN15_7 / P15_7
AN15_6 / P15_6
AN15_5 / P15_5
AN15_4 / P15_4
AN15_3 / P15_3
AN15_2 / P15_2
AN15_1 / P15_1
VSS
AN15_0 / P15_0
VCC1
AN_7 / KI3 / P10_7
AN_6 / KI2 / P10_6
AN_5 / KI1 / P10_5
AN_4 / KI0 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
AN_0 / P10_0
VREF
AVCC
ADTRG / STXD4 / SCL4 / RXD4 / P9_7
D7 /
D6 /
D5 /
D4 /
107
108
P1_1 / D9
P1_2 / D10
P1_3 / D11
P1_4 / D12
P1_5 / INT3 / D13
P1_6 / INT4 / D14
P1_7 / INT5 / D15
P2_0 / AN2_0 / A0 , [ A0
P2_1 / AN2_1 / A1 , [ A1
P2_2 / AN2_2 / A2 , [ A2
P2_3 / AN2_3 / A3 , [ A3
P2_4 / AN2_4 / A4 , [ A4
P2_5 / AN2_5 / A5 , [ A5
P2_6 / AN2_6 / A6 , [ A6
P2_7 / AN2_7 / A7 , [ A7
VSS
P3_0 / A8 , [ A8 / D8 ]
VCC2
P12_0
P12_1
P12_2
P12_3
P12_4
P3_1 / A9 , [ A9 / D9 ]
P3_2 / A10 , [ A10 / D10 ]
P3_3 / A11 , [ A11 / D11 ]
P3_4 / A12 , [ A12 / D12 ]
P3_5 / A13 , [ A13 / D13 ]
P3_6 / A14 , [ A14 / D14 ]
P3_7 / A15 , [ A15 / D15 ]
P4_0 / A16
P4_1 / A17
VSS
P4_2 / A18
VCC2
P4_3 / A19
/
/
/
/
/
/
/
/
D0
D1
D2
D3
D4
D5
D6
D7
]
]
]
]
]
]
]
]
( note 3 )
NOTES:
1. P7_0 and P7_1 are N-channel open drain output ports .
2. Refer to Package Dimensions for the pin1 position on the package.
3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
Figure 1.3
Pin Assignment for 144-pin Package
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 8 of 67
M32C/8B Group
Table 1.6
Pin
No.
1. Overview
144-Pin Package List of Pin Names (1/3)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
1
2
3
P9_6
P9_5
P9_4
TB4IN
CTS4/RTS4/SS4
4
P9_3
TB3IN
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
P9_2
P9_1
P9_0
P14_6
P14_5
P14_4
P14_3
P14_2
P14_1
P14_0
TB2IN
TB1IN
TB0IN
CTS3/RTS3/SS3
TXD3/SDA3/SRXD3
RXD3/SCL3/STXD3
CLK3
20
21
22
23
24
BYTE
CNVSS
XCIN
XCOUT
TXD4/SDA4/SRXD4
CLK4
P8_7
P8_6
RESET
XOUT
VSS
XIN
VCC1
P8_5
NMI
25
P8_4
INT2
26
P8_3
INT1
27
P8_2
INT0
28
P8_1
TA4IN/U
29
P8_0
TA4OUT/U
30
P7_7
TA3IN
31
P7_6
TA3OUT
32
P7_5
TA2IN/W
33
P7_4
TA2OUT/W
34
P7_3
TA1IN/V
35
P7_2
TA1OUT/V
CTS2/RTS2/SS2
CLK2
36
P7_1
TA0IN/TB5IN
RXD2/SCL2/STXD2
37
P7_0
TA0OUT
TXD2/SDA2/SRXD2
38
39
40
41
42
43
P6_7
TXD1/SDA1/SRXD1
P6_6
RXD1/SCL1/STXD1
P6_5
P6_4
CTS1/RTS1/SS1
44
P6_3
TXD0/SDA0/SRXD0
45
P6_2
RXD0/SCL0/STXD0
46
P6_1
CLK0
47
P6_0
CTS0/RTS0/SS0
48
49
50
P13_7
P13_6
P13_5
VCC1
VSS
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 9 of 67
CLK1
Analog Pin
ANEX1
ANEX0
DA1
DA0
Bus Control Pin
M32C/8B Group
Table 1.7
Pin
No.
1. Overview
144-Pin Package List of Pin Names (2/3)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
51
52
P13_4
P5_7
RDY
53
P5_6
ALE
54
P5_5
HOLD
55
P5_4
HLDA/ALE
56
57
58
59
60
61
62
63
P13_3
VSS
P13_2
VCC2
CLKOUT
P13_1
P13_0
P5_3
P5_2
BCLK/ALE
RD
64
P5_1
WRH/BHE
65
P5_0
WRL/WR
66
67
68
69
P12_7
P12_6
P12_5
P4_7
CS0/A23
70
P4_6
CS1/A22
71
P4_5
CS2/A21
72
P4_4
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P4_3
CS3/A20
A19
P4_2
A18
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P12_4
P12_3
P12_2
P12_1
P12_0
A17
A16
A15,[A15/D15]
A14,[A14/D14]
A13,[A13/D13]
A12,[A12/D12]
A11,[A11/D11]
A10,[A10/D10]
A9,[A9/D9]
P3_0
A8,[A8/D8]
VCC2
VSS
VCC2
VSS
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 10 of 67
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
A7,[A7/D7]
A6,[A6/D6]
A5,[A5/D5]
A4,[A4/D4]
A3,[A3/D3]
A2,[A2/D2]
A1,[A1/D1]
M32C/8B Group
Table 1.8
Pin
No.
1. Overview
144-Pin Package List of Pin Names (3/3)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
AN2_0
Bus Control Pin
101
102
P2_0
P1_7
INT5
A0,[A0/D0]
D15
103
P1_6
INT4
D14
104
P1_5
INT3
D13
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130 VSS
131
132 VCC1
133
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P11_4
P11_3
P11_2
P11_1
P11_0
P0_3
P0_2
P0_1
P0_0
P15_7
P15_6
P15_5
P15_4
P15_3
P15_2
P15_1
AN0_3
AN0_2
AN0_1
AN0_0
AN15_7
AN15_6
AN15_5
AN15_4
AN15_3
AN15_2
AN15_1
P15_0
AN15_0
P10_7
KI3
AN_7
134
P10_6
KI2
AN_6
135
P10_5
KI1
AN_5
136
P10_4
KI0
137
138
139
140 AVSS
141
142 VREF
143 AVCC
144
P10_3
P10_2
P10_1
AN_3
AN_2
AN_1
P10_0
AN_0
AN0_7
AN0_6
AN0_5
AN0_4
P9_7
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 11 of 67
AN_4
RXD4/SCL4/STXD4
ADTRG
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
M32C/8B Group
1. Overview
D10 / P1_2
D9 / P1_1
D8 / P1_0
D7 / AN0_7 / P0_7
D6 / AN0_6 / P0_6
D5 / AN0_5 / P0_5
D4 / AN0_4 / P0_4
D3 / AN0_3 / P0_3
D2 / AN0_2 / P0_2
D1 / AN0_1 / P0_1
D0 / AN0_0 / P0_0
AN_7 / KI3 / P10_7
AN_6 / KI2 / P10_6
AN_5 / KI1 / P10_5
AN_4 / KI0 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AVSS
AN_0 / P10_0
VREF
AVCC
ADTRG / STXD4 / SCL4 / RXD4 / P9_7
ANEX1 / TXD4 / SDA4 / SRXD4 / P9_6
ANEX0 / CLK4 / P9_5
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
P1_3 / D11
P1_4 / D12
P1_5 / INT3 / D13
P1_6 / INT4 / D14
P1_7 / INT5 / D15
P2_0 / AN2_0 / A0 , [ A0 / D0 ]
P2_1 / AN2_1 / A1 , [ A1 / D1 ]
P2_2 / AN2_2 / A2 , [ A2 / D2 ]
P2_3 / AN2_3 / A3 , [ A3 / D3 ]
P2_4 / AN2_4 / A4 , [ A4 / D4 ]
P2_5 / AN2_5 / A5 , [ A5 / D5 ]
P2_6 / AN2_6 / A6 , [ A6 / D6 ]
P2_7 / AN2_7 / A7 , [ A7 / D7 ]
VSS
P3_0 / A8 , [ A8 / D8 ]
VCC2
P3_1 / A9 , [ A9 / D9 ]
P3_2 / A10 , [ A10 / D10 ]
P3_3 / A11 , [ A11 / D11 ]
P3_4 / A12 , [ A12 / D12 ]
P3_5 / A13 , [ A13 / D13 ]
P3_6 / A14 , [ A14 / D14 ]
P3_7 / A15 , [ A15 / D15 ]
P4_0 / A16
P4_1 / A17
( note 3 )
76
50
77
49
78
48
79
47
80
46
81
45
82
44
83
43
M32C/8B Group
84
85
42
41
86
40
87
39
88
38
PLQP0100KB-A
(100P6Q-A)
(top view)
89
90
91
92
37
36
35
34
93
33
94
32
95
31
96
30
97
29
98
28
99
27
100
26
P4_2 / A18
P4_3 / A19
P4_4 / CS3 / A20
P4_5 / CS2 / A21
P4_6 / CS1 / A22
P4_7 / CS0 / A23
P5_0 / WRL / WR
P5_1 / WRH / BHE
P5_2 / RD
P5_3 / CLKOUT / BCLK / ALE
P5_4 / HLDA / ALE
P5_5 / HOLD
P5_6 / ALE
P5_7 / RDY
P6_0 / CTS0 / RTS0 / SS0
P6_1 / CLK0
P6_2 / RXD0 / SCL0 / STXD0
P6_3 / TXD0 / SDA0 / SRXD0
P6_4 / CTS1 / RTS1 / SS1
P6_5 / CLK1
P6_6 / RXD1 / SCL1 / STXD1
P6_7 / TXD1 / SDA1 / SRXD1
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 (1)
P7_1 / TA0IN / TB5IN / RXD2 / SCL2 / STXD2 (1)
P7_2 / TA1OUT / V / CLK2
25
24
23
22
21
20
19
18
17
16
15
14
13
NMI
INT2
INT1
INT0
U / TA4IN
U / TA4OUT
TA3IN
TA3OUT
W / TA2IN
W / TA2OUT
SS2 / RTS2 / CTS2 / V / TA1IN
11
12
VSS
XIN
VCC1
/ P8_5
/ P8_4
/ P8_3
/ P8_2
/ P8_1
/ P8_0
/ P7_7
/ P7_6
/ P7_5
/ P7_4
/ P7_3
10
9
8
7
6
5
4
3
2
DA1 / SS4 / RTS4 / CTS4
DA0 / SS3 / RTS3 / CTS3
SRXD3 / SDA3 / TXD3
STXD3 / SCL3 / RXD3
CLK3
/
/
/
/
/
TB4IN
TB3IN
TB2IN
TB1IN
TB0IN
/
/
/
/
/
P9_4
P9_3
P9_2
P9_1
P9_0
BYTE
CNVSS
XCIN / P8_7
XCOUT / P8_6
RESET
XOUT
1
( note 2 )
NOTES:
1. P7_0 and P7_1 are N-channel open drain output ports.
2. Refer to Package Dimensions for the pin1 position on the package.
3. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
Figure 1.4
Pin Assignment for 100-pin Package
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 12 of 67
M32C/8B Group
Table 1.9
Pin
No.
1. Overview
100-Pin Package List of Pin Names (1/2)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
1
P9_4
TB4IN
CTS4/RTS4/SS4
DA1
2
P9_3
TB3IN
DA0
3
4
5
6
7
8
9
10
P9_2
P9_1
P9_0
TB2IN
TB1IN
TB0IN
CTS3/RTS3/SS3
TXD3/SDA3/SRXD3
RXD3/SCL3/STXD3
CLK3
11
12
13
14
BYTE
CNVSS
XCIN
XCOUT
Bus Control Pin
P8_7
P8_6
RESET
XOUT
VSS
XIN
VCC1
15
P8_5
NMI
16
P8_4
INT2
17
P8_3
INT1
18
P8_2
INT0
19
P8_1
TA4IN/U
20
P8_0
TA4OUT/U
21
P7_7
TA3IN
22
P7_6
TA3OUT
23
P7_5
TA2IN/W
24
P7_4
TA2OUT/W
25
P7_3
TA1IN/V
CTS2/RTS2/SS2
26
P7_2
TA1OUT/V
CLK2
27
P7_1
TA0IN/TB5IN
RXD2/SCL2/STXD2
28
P7_0
TA0OUT
TXD2/SDA2/SRXD2
29
P6_7
TXD1/SDA1/SRXD1
30
P6_6
RXD1/SCL1/STXD1
31
P6_5
CLK1
32
P6_4
CTS1/RTS1/SS1
33
P6_3
TXD0/SDA0/SRXD0
34
P6_2
RXD0/SCL0/STXD0
35
P6_1
CLK0
36
P6_0
CTS0/RTS0/SS0
37
P5_7
RDY
38
P5_6
ALE
39
P5_5
HOLD
40
P5_4
HLDA/ALE
P5_3
BCLK/ALE
42
P5_2
RD
43
P5_1
WRH/BHE
44
P5_0
WRL/WR
45
P4_7
CS0/A23
46
P4_6
CS1/A22
47
P4_5
CS2/A21
48
P4_4
CS3/A20
49
P4_3
A19
50
P4_2
A18
41
CLKOUT
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 13 of 67
M32C/8B Group
Table 1.10
Pin
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
1. Overview
100-Pin Package List of Pin Names (2/2)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
A17
A16
A15,[A15/D15]
A14,[A14/D14]
A13,[A13/D13]
A12,[A12/D12]
A11,[A11/D11]
A10,[A10/D10]
A9,[A9/D9]
P3_0
A8,[A8/D8]
VCC2
VSS
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
INT5
A7,[A7/D7]
A6,[A6/D6]
A5,[A5/D5]
A4,[A4/D4]
A3,[A3/D3]
A2,[A2/D2]
A1,[A1/D1]
A0,[A0/D0]
D15
72
P1_6
INT4
D14
73
P1_5
INT3
D13
74
75
76
77
78
79
80
81
82
83
84
85
86
87
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P10_7
KI3
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AN_7
88
P10_6
KI2
AN_6
89
P10_5
KI1
AN_5
90
P10_4
KI0
91
92
93
94
95
96
97
98
P10_3
P10_2
P10_1
AN_3
AN_2
AN_1
P10_0
AN_0
99
100
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
AN_4
AVSS
VREF
AVCC
P9_7
RXD4/SCL4/STXD4
P9_6
P9_5
TXD4/SDA4/SRXD4
CLK4
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 14 of 67
ADTRG
ANEX1
ANEX0
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
M32C/8B Group
1.5
1. Overview
Pin Functions
Table 1.11
Item
Power supply
Analog power
supply input
Reset input
Pin Functions (100-Pin and 144-Pin Packages) (1/3)
Pin Name
VCC1,VCC2
VSS
AVCC
AVSS
RESET
CNVSS
CNVSS
External data
bus width
select input
BYTE
Bus control
Pins
D0 to D7
D8 to D15
A0 to A22
A23
A0/D0 to
A7/D7
I/O
Supply
Description
Type Voltage
−
−
Apply 3.0 to 5.5 V to pins VCC1 and VCC2, and 0 V to the VSS pin.
Meet the input condition of VCC1 ≥ VCC2.
−
VCC1 Power supply input pins to the A/D converter and D/A converter.
Connect the AVCC pin to VCC1, and the AVSS pin to VSS.
I
VCC1 The MCU is placed in the reset state while applying an “L” signal to
the RESET pin.
I
VCC1 This pin switches processor mode. Apply an “L” to the CNVSS pin
to start up in single-chip mode, or an “H” to start up in
microprocessor mode and boot mode.
I
VCC1 This pin switches data bus width in external memory space 3. A
data bus is 16 bits wide when the BYTE pin is held “L” and 8 bits
wide when it is held “H”. Fix to either “L” or “H”. Apply an “L” to the
BYTE pin in single-chip mode.
I/O
VCC2 Data (D0 to D7) input/output pins while accessing an external
memory space with separate bus.
I/O
VCC2 Data (D8 to D15) input/output pins while accessing an external
memory space with 16-bit separate bus.
O
VCC2 Address bits (A0 to A22) output pins.
O
VCC2 Inverted address bit (A23) output pin.
I/O
VCC2
A8/D8 to
A15/D15
I/O
VCC2
CS0 to CS3
O
VCC2
WRL/WR
WRH/BHE
RD
O
VCC2
ALE
O
VCC2
HOLD
I
VCC2
HLDA
O
VCC2
The HLDA pin outputs an “L” while the MCU is placed in the hold state.
RDY
I
VCC2
Bus is placed in the wait state while an “L” signal is applied to the
RDY pin.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 15 of 67
Data (D0 to D7) input/output and 8 low-order address bits (A0 to
A7) output are performed by time-sharing these pins while
accessing an external memory space with multiplexed bus.
Data (D8 to D15) input/output and 8 middle-order address bits (A8
to A15) output are performed by time-sharing these pins while
accessing an external memory space with 16-bit multiplexed bus.
Chip-select signal output pins used to specify external devices.
WRL, WRH, (WR, BHE) and RD signal output pins. WRL and WRH
can be switched with WR and BHE by a program.
• WRL, WRH and RD are selected:
If external data bus is 16 bits wide, data is written to an even
address in external memory space while an “L” is output from the
WRL pin. Data is written to an odd address while an “L” is output
from the WRH pin.
Data is read while an “L” is output from the RD pin.
• WR, BHE and RD are selected:
Data is written while an “L” is output from the WR pin.
Data is read while an “L” is output from the RD pin.
Data in odd address is accessed while an “L” is output from the
BHE pin. Select WR, BHE and RD when an external data bus is
8 bits wide.
ALE signal is used for the external devices to latch address signals
when the multiplexed bus is selected.
The MCU is placed in the hold state while an “L” signal is applied to
the HOLD pin.
M32C/8B Group
Table 1.12
Item
Main clock
input
Main clock
output
Sub clock
input
Sub clock
output
BCLK output
Clock output
1. Overview
Pin Functions (100-Pin and 144-Pin Packages) (2/3)
Pin Name
XIN
XOUT
I/O
Supply
Description
Type Voltage
I
VCC1 Input/output pins for the main clock oscillation circuit. Connect a
ceramic resonator or crystal oscillator between XIN and XOUT. To
O
VCC1 apply an external clock, apply it to XIN and leave XOUT open.
XCIN
I
VCC1
XCOUT
O
VCC1
BCLK
CLKOUT
O
O
VCC2
VCC2
Bus clock output pin
The CLKOUT pin outputs the clock having the same frequency as
fC, f8, or f32
INT interrupt
input
INT0 to INT2
I
VCC1
INT interrupt input pins
NT3 to INT5
I
VCC2
NMI interrupt
input
Timer A
NMI
I
VCC1
TA0OUT to
TA4OUT
TA0IN to
TA4IN
TB0IN to
TB5IN
I/O
VCC1
I
VCC1
NMI interrupt input pin. Connect the NMI pin to VCC1 via a resistor
when the NMI interrupt is not used.
Timer A0 to A4 input/output pins
(TA0OUT is N-channel open drain output)
Timer A0 to A4 input pins
I
VCC1
Timer B0 to B5 input pins
U, U, V, V,
W, W
O
VCC1
Three-phase motor control timer output pins
CTS0 to
CTS4
I
VCC1
Input pins to control data transmission
RTS0 to
RTS4
CLK0 to CLK4
RXD0 to
RXD4
TXD0 to
TXD4
SDA0 to
SDA4
SCL0 to SCL4
O
VCC1
Output pins to control data reception
I/O
I
VCC1
VCC1
Serial clock input/output pins
Serial data input pins
O
VCC1
I/O
VCC1
I/O
VCC1
O
VCC1
I
VCC1
Serial data output pins
(TXD2 is N-channel open drain output)
Serial data input/output pins
(SDA2 is N-channel open drain output)
Serial clock input/output pins
(SCL2 is N-channel open drain output)
Serial data output pins when slave mode is selected
(STXD2 is N-channel open drain output)
Serial data input pins when slave mode is selected
I
VCC1
Control input pins used in the serial interface special mode.
Timer B
Three-phase
motor control
timer output
Serial
interface
I2C mode
STXD0 to
Serial
STXD4
interface
special function SRXD0 to
SRXD4
SS0 to SS4
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 16 of 67
Input/output pins for the sub clock oscillation circuit. Connect a
crystal oscillator between XCIN and XCOUT. To apply an external
clock, apply it to XCIN and leave XCOUT open.
M32C/8B Group
Table 1.13
Item
Reference
voltage input
A/D converter
D/A converter
I/O port
Input port
Key input
interrupt input
Table 1.14
Item
A/D converter
I/O port
1. Overview
Pin Functions (100-Pin and 144-Pin Packages) (3/3)
Pin Name
VREF
I/O Supply
Type Voltage
I
−
Description
AN_0 to AN_7
AN0_0 to
AN0_7,
AN2_0 to
AN2_7
I
I
VCC1
VCC2
The VREF pin supplies the reference voltage to the A/D converter
and D/A converter.
Analog input pins for the A/D converter.
Analog input pins for the A/D converter.
ADTRG
ANEX0
I
VCC1
External trigger input pin for the A/D converter.
I/O
VCC1
I
O
I/O
VCC1
VCC1
VCC2
Extended analog input pin for the A/D converter or output pin in
external op-amp connection mode.
Extended analog input pin for the A/D converter.
Output pins for the D/A converter.
8-bit CMOS I/O ports. The Port Pi Direction Register (i = 0 to 15)
determines if each pin is used as an input port or an output port.
The Pull-up Control Registers determine if the input ports, divided
into groups of four, are pulled up or not.
I/O
VCC1
ANEX1
DA0, DA1
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7
P6_0 to P6_7,
P7_0 to P7_7,
P9_0 to P9_7,
P10_0 to
P10_7
P8_0 to P8_4
P8_6, P8_7
P8_5
KI0 to KI3
These 8-bit I/O ports are functionally equivalent to P0.
(P7_0 and P7_1 are N-channel open drain output.)
These I/O ports are functionally equivalent to P0.
I
VCC1
I
VCC1
Shares the pin with NMI. Input port to read NMI pin level.
Key input interrupt input pins
Pin Functions (144-Pin Package Only)
Pin Name
AN15_0 to
AN15_7
P11_0 to
P11_4,
P12_0 to
P12_7,
P13_0 to
P13_7
P14_0 to
P14_6,
P15_0 to
P15_7
I/O
Supply
Description
Type Voltage
I
VCC1 Analog input pins for the A/D converter
I/O
VCC2
I/O
VCC1
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 17 of 67
These I/O ports are functionally equivalent to P0.
M32C/8B Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers.
The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, SB, and FB) out of 28 CPU registers. There
are two sets of register banks.
b31
General registers
b15
R2
R2
R3
R3
b0
R0H
R0H
R1H
R1H
R0L
R0L
R1L
R1L
Data registers(1)
R2
R2
R3
R3
b23
A0
A0
A1
A1
SB
SB
FB
FB
Static base register(1)
Frame base register(1)
USP
ISP
INTB
PC
User stack pointer
Interrupt stack pointer
Interrupt table register
Program counter
Address registers(1)
FLG
b15
Flag register
b8 b7
IPL
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved
Processor interrupt priority level
Reserved
b15
High-speed interrupt registers
b0
SVF
b23
Flag save register
PC save register
Vector register
SVP
VCT
b7
b0
DMD0
DMD1
DMAC-associated registers
b15
DCT0
DCT1
DRC0
DRC1
b23
DMA0
DMA1
DRA0
DRA1
DSA0
DSA1
DMA mode registers
DMA transfer count registers
DMA transfer count reload registers
DMA memory address registers
DMA memory address reload registers
DMA SFR address registers
NOTE:
1. These registers comprise a register bank.
There are two sets of register banks (register bank 0 and register bank 1).
Figure 2.1
CPU Register
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 18 of 67
M32C/8B Group
2.1
2. Central Processing Unit (CPU)
General Registers
2.1.1
Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into
high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers.
R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1.
2.1.2
Address Registers (A0 and A1)
A0 and A1 are 24-bit registers used for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer,
arithmetic and logic operations.
2.1.3
Static Base Register (SB)
SB is a 24-bit register used for SB-relative addressing.
2.1.4
Frame Base Register (FB)
FB is a 24-bit register used for FB-relative addressing.
2.1.5
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP.
Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an
interrupt sequence efficiently.
2.1.6
Interrupt Table Register (INTB)
INTB is a 24-bit register indicating the starting address of a relocatable interrupt vector table.
2.1.7
Program Counter (PC)
PC is 24 bits wide and indicates the address of the next instruction to be executed.
2.1.8
Flag Register (FLG)
FLG is a 16-bit register indicating the CPU state.
2.1.8.1
Carry Flag (C)
The C flag indicates whether or not carry or borrow has been generated after executing an instruction.
2.1.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.1.8.3
Zero Flag (Z)
The Z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0.
2.1.8.4
Sign Flag (S)
The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0.
2.1.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set to 1.
2.1.8.6
Overflow Flag (O)
The O flag becomes 1 when an arithmetic operation results in an overflow; otherwise becomes 0.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 19 of 67
M32C/8B Group
2.1.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1. The I flag becomes 0 when
an interrupt request is acknowledged.
2.1.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0. USP is selected when the U flag is set to 1.
The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction specifying
software interrupt numbers 0 to 31 is executed.
2.1.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority level than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
Only write 0 to bits assigned to the reserved space. When read, the bits return undefined values.
2.2
High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows:
• Flag save register (SVF)
• PC save register (SVP)
• Vector register (VCT)
2.3
DMAC-Associated Registers
Registers associated with the DMAC are as follows:
• DMA mode register (DMD0, DMD1)
• DMA transfer count register (DCT0, DCT1)
• DMA transfer count reload register (DRC0, DRC1)
• DMA memory address register (DMA0, DMA1)
• DMA memory address reload register (DRA0, DRA1)
• DMA SFR address register (DSA0, DSA1)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 20 of 67
M32C/8B Group
3.
3. Memory
Memory
Figure 3.1 shows a memory map of the M32C/8B Group.
The M32C/8B Group has 16-Mbyte address space from addresses 000000h to FFFFFFh.
The internal ROM is allocated in lower addresses, beginning with address FFFFFFh. For example, a 256-Kbyte
internal ROM area is allocated in addresses FC0000h to FFFFFFh.
The fixed interrupt vectors are allocated in addresses FFFFDCh to FFFFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 000400h. For example, a 32-Kbyte internal
RAM area is allocated in addresses 000400h to 0083FFh. The internal RAM is used not only for storing data but for
the stacks when subroutines are called or when interrupt requests are acknowledged.
SFRs are allocated in addresses 000000h to 0003FFh. The peripheral function control registers such as for I/O ports,
A/D converters, serial interfaces, timers are allocated here. All blank spaces within SFRs are reserved and cannot be
accessed by users.
The special page vectors are allocated addresses FFFE00h to FFFFDBh. They are used for the JMPS instruction and
JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details.
000000h
SFR
000400h
Internal RAM
Internal RAM
Capacity
32 Kbytes
XXXXXXh
0083FFh
FFFE00h
XXXXXXh
Reserved
00E000h
00FFFFh
Internal ROM(3)
(Data space)
FFFFDCh
Special page
vector table
Undefined instruction
Overflow
BRK instruction
External space(1)
Address match
Internal ROM
Capacity
YYYYYYh
128 Kbytes
FE0000h
256 Kbytes
FC0000h
F00000h
Watchdog timer
Reserved(2)
(5)
YYYYYYh
NMI
Internal ROM(4)
FFFFFFh
FFFFFFh
Reset
NOTES:
1. The space is used as the external space in memory expansion mode and microprocessor mode. It is reserved in single-chip mode.
2. The space is reserved in single-chip mode and memory expansion mode. It is used as the external space in microprocessor mode.
3. Additional two blocks of 4-Kbyte space are provided in the flash memory version to store data. This space is used in single-chip mode
and memory expansion mode. It is reserved in microprocessor mode.
4. This space is used as the internal ROM in single-chip mode and memory expansion mode. It is used as the external space in
microprocessor mode.
5. The watchdog timer interrupt, oscillation stop detection interrupt, and voltage monitor interrupt share the same vector.
Figure 3.1
Memory Map
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 21 of 67
M32C/8B Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
Special Function Registers (SFRs) are the control registers of peripheral functions. Tables 4.1 to 4.11 list SFR address
maps.
Table 4.1
SFR Address Map (1/11)
Address
Register
Symbol
After Reset
0000h
0001h
0002h
0003h
0004h
Processor Mode Register 0(1)
PM0
1000 0000b(CNVSS=”L”)
0000 0011b(CNVSS=”H”)
0005h
Processor Mode Register 1
PM1
00h
0006h
System Clock Control Register 0
CM0
0000 1000b
0007h
System Clock Control Register 1
CM1
0010 0000b
0009h
Address Match Interrupt Enable Register
AIER
00h
000Ah
Protect Register
PRCR
XXXX 0000b
DS
XXXX 1000b(BYTE=”L”)
XXXX 0000b(BYTE=”H”)
0008h
000Bh
External Data Bus Width Control Register
000Ch
Main Clock Division Register
MCD
XXX0 1000b
000Dh
Oscillation Stop Detection Register
CM2
00h
000Eh
Watchdog Timer Start Register
WDTS
XXh
000Fh
Watchdog Timer Control Register
WDC
000X XXXXb
Address Match Interrupt Register 0
RMAD0
000000h
Processor Mode Register 2
PM2
00h
Address Match Interrupt Register 1
RMAD1
000000h
Reference Voltage Configuration Register
DVCR
1000 1111b
Address Match Interrupt Register 2
RMAD2
000000h
Voltage Monitor Register
LVDC
0000 1000h
Address Match Interrupt Register 3
RMAD3
000000h
Voltage Regulator Control Register
VRCR
00h
PLL Control Register 0
PLC0
0001 X010b
Address Match Interrupt Register 4
RMAD4
000000h
Address Match Interrupt Register 5
RMAD5
000000h
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
NOTE:
1. Bits PM01 and PM00 in the PM0 register maintain values set before reset, even after software reset or watchdog timer reset has been
performed.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 22 of 67
M32C/8B Group
Table 4.2
4. Special Function Registers (SFRs)
SFR Address Map (2/11)
Address
Register
Symbol
After Reset
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
Address Match Interrupt Register 6
RMAD6
000000h
Address Match Interrupt Register 7
RMAD7
000000h
0048h
External Space Wait Control Register 0
EWCR0
X0X0 0011b
0049h
External Space Wait Control Register 1
EWCR1
X0X0 0011b
004Ah
External Space Wait Control Register 2
EWCR2
X0X0 0011b
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
004Bh
External Space Wait Control Register 3
EWCR3
X0X0 0011b
004Ch
Page Mode Wait Control Register 0(1)
PWCR0
0001 0001b
004Dh
Page Mode Wait Control Register 1(1)
PWCR1
0001 0001b
Flash Memory Control Register 3(2)
FMR 3
XX0X XX00b
Flash Memory Control Register 2(2)
FMR 2
XXXX XXX0b
Flash Memory Control Register 1(2)
FMR1
0000 XX0Xb
Flash Memory Control Register 0(2)
FMR0
0000 0001b
Flash Memory Control Register 4(2)
FMR4
00h
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
NOTES:
1. These registers are available only in ROMless version.
2. These registers are not available in ROMless version.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 23 of 67
M32C/8B Group
Table 4.3
4. Special Function Registers (SFRs)
SFR Address Map (3/11)
Address
Register
Symbol
After Reset
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
DMA0 Interrupt Control Register
DM0IC
XXXX X000b
0069h
Timer B5 Interrupt Control Register
TB5IC
XXXX X000b
006Ah
DMA2 Interrupt Control Register
DM2IC
XXXX X000b
006Bh
UART2 Receive/ACK Interrupt Control Register
S2RIC
XXXX X000b
006Ch
Timer A0 Interrupt Control Register
TA0IC
XXXX X000b
006Dh
UART3 Receive/ACK Interrupt Control Register
S3RIC
XXXX X000b
006Eh
Timer A2 Interrupt Control Register
TA2IC
XXXX X000b
006Fh
UART4 Receive/ACK Interrupt Control Register
S4RIC
XXXX X000b
0070h
Timer A4 Interrupt Control Register
TA4IC
XXXX X000b
0071h
UART0/UART3 Bus Conflict Detection Interrupt Control Register
BCN0IC/BCN3IC
XXXX X000b
0072h
UART0 Receive/ACK Interrupt Control Register
S0RIC
XXXX X000b
0073h
A/D0 Conversion Interrupt Control Register
AD0IC
XXXX X000b
0074h
UART1 Receive/ACK Interrupt Control Register
S1RIC
XXXX X000b
Timer B1 Interrupt Control Register
TB1IC
XXXX X000b
Timer B3 Interrupt Control Register
TB3IC
XXXX X000b
INT5 Interrupt Control Register
INT5IC
XX00 X000b
INT3 Interrupt Control Register
INT3IC
XX00 X000b
INT1 Interrupt Control Register
INT1IC
XX00 X000b
0088h
DMA1 Interrupt Control Register
DM1IC
XXXX X000b
0089h
UART2 Transmit/NACK Interrupt Control Register
S2TIC
XXXX X000b
008Ah
DMA3 Interrupt Control Register
DM3IC
XXXX X000b
008Bh
UART3 Transmit/NACK Interrupt Control Register
S3TIC
XXXX X000b
008Ch
Timer A1 Interrupt Control Register
TA1IC
XXXX X000b
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
008Dh
UART4 Transmit/NACK Interrupt Control Register
S4TIC
XXXX X000b
008Eh
Timer A3 Interrupt Control Register
TA3IC
XXXX X000b
008Fh
UART2 Bus Conflict Detection Interrupt Control Register
BCN2IC
XXXX X000b
X: Undefined
Blank spaces are all reserved. No access is allowed.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 24 of 67
M32C/8B Group
Table 4.4
4. Special Function Registers (SFRs)
SFR Address Map (4/11)
Address
Register
Symbol
After Reset
0090h
UART0 Transmit/NACK Interrupt Control Register
S0TIC
XXXX X000b
0091h
UART1/UART4 Bus Conflict Detection Interrupt Control Register
BCN1IC/BCN4IC
XXXX X000b
0092h
UART1 Transmit/NACK Interrupt Control Register
S1TIC
XXXX X000b
0093h
Key Input Interrupt Control Register
KUPIC
XXXX X000b
0094h
Timer B0 Interrupt Control Register
TB0IC
XXXX X000b
Timer B2 Interrupt Control Register
TB2IC
XXXX X000b
Timer B4 Interrupt Control Register
TB4IC
XXXX X000b
INT4 Interrupt Control Register
INT4IC
XX00 X000b
INT2 Interrupt Control Register
INT2IC
XX00 X000b
009Eh
INT0 Interrupt Control Register
INT0IC
XX00 X000b
009Fh
Exit Priority Register
RLVL
XXXX 0000b
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
00A0h
to
02BFh
X: Undefined
Blank spaces are all reserved. No access is allowed.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 25 of 67
M32C/8B Group
Table 4.5
4. Special Function Registers (SFRs)
SFR Address Map (5/11)
Address
02C0h
Register
Symbol
After Reset
X0 Register, Y0 Register
X0R, Y0R
XXXXh
X1 Register, Y1 Register
X1R, Y1R
XXXXh
X2 Register, Y2 Register
X2R, Y2R
XXXXh
X3 Register, Y3 Register
X3R, Y3R
XXXXh
X4 Register, Y4 Register
X4R, Y4R
XXXXh
X5 Register, Y5 Register
X5R, Y5R
XXXXh
X6 Register, Y6 Register
X6R, Y6R
XXXXh
X7 Register, Y7 Register
X7R, Y7R
XXXXh
X8 Register, Y8 Register
X8R, Y8R
XXXXh
X9 Register, Y9 Register
X9R, Y9R
XXXXh
X10 Register, Y10 Register
X10R, Y10R
XXXXh
X11 Register, Y11 Register
X11R, Y11R
XXXXh
X12 Register, Y12 Register
X12R, Y12R
XXXXh
X13 Register, Y13 Register
X13R, Y13R
XXXXh
X14 Register, Y14 Register
X14R, Y14R
XXXXh
X15 Register, Y15 Register
X15R, Y15R
XXXXh
X/Y Control Register
XYC
XXXX XX00b
02E4h
UART1 Special Mode Register 4
U1SMR4
00h
02E5h
UART1 Special Mode Register 3
U1SMR3
00h
02E6h
UART1 Special Mode Register 2
U1SMR2
00h
02E7h
UART1 Special Mode Register
U1SMR
00h
02E8h
UART1 Transmit/Receive Mode Register
U1MR
00h
02E9h
UART1 Baud Rate Register
U1BRG
XXh
UART1 Transmit Buffer Register
U1TB
XXXXh
02ECh
UART1 Transmit/Receive Control Register 0
U1C0
0000 1000b
02EDh
UART1 Transmit/Receive Control Register 1
U1C1
0000 0010b
UART1 Receive Buffer Register
U1RB
XXXXh
02C1h
02C2h
02C3h
02C4h
02C5h
02C6h
02C7h
02C8h
02C9h
02CAh
02CBh
02CCh
02CDh
02CEh
02CFh
02D0h
02D1h
02D2h
02D3h
02D4h
02D5h
02D6h
02D7h
02D8h
02D9h
02DAh
02DBh
02DCh
02DDh
02DEh
02DFh
02E0h
02E1h
02E2h
02E3h
02EAh
02EBh
02EEh
02EFh
X: Undefined
Blank spaces are all reserved. No access is allowed.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 26 of 67
M32C/8B Group
Table 4.6
4. Special Function Registers (SFRs)
SFR Address Map (6/11)
Address
Register
Symbol
After Reset
02F0h
02F1h
02F2h
02F3h
02F4h
UART4 Special Mode Register 4
U4SMR4
00h
02F5h
UART4 Special Mode Register 3
U4SMR3
00h
02F6h
UART4 Special Mode Register 2
U4SMR2
00h
02F7h
UART4 Special Mode Register
U4SMR
00h
02F8h
UART4 Transmit/Receive Mode Register
U4MR
00h
02F9h
UART4 Baud Rate Register
U4BRG
XXh
UART4 Transmit Buffer Register
U4TB
XXXXh
02FCh
UART4 Transmit/Receive Control Register 0
U4C0
0000 1000b
02FDh
UART4 Transmit/Receive Control Register 1
U4C1
0000 0010b
UART4 Receive Buffer Register
U4RB
XXXXh
Timer B3, B4, B5 Count Start Register
TBSR
000X XXXXb
Timer A11 Register
TA11
XXXXh
Timer A21 Register
TA21
XXXXh
Timer A41 Register
TA41
XXXXh
0308h
Three-Phase PWM Control Register 0
INVC0
00h
0309h
Three-Phase PWM Control Register 1
INVC1
00h
030Ah
Three-Phase Output Buffer Register 0
IDB0
XX11 1111b
02FAh
02FBh
02FEh
02FFh
0300h
0301h
0302h
0303h
0304h
0305h
0306h
0307h
030Bh
Three-Phase Output Buffer Register 1
IDB1
XX11 1111b
030Ch
Dead Time Timer
DTT
XXh
030Dh
Timer B2 Interrupt Generation Frequency Set Counter
ICTB2
XXh
Timer B3 Register
TB3
XXXXh
Timer B4 Register
TB4
XXXXh
Timer B5 Register
TB5
XXXXh
030Eh
030Fh
0310h
0311h
0312h
0313h
0314h
0315h
0316h
0317h
0318h
0319h
031Ah
031Bh
Timer B3 Mode Register
TB3MR
00XX 0000b
031Ch
Timer B4 Mode Register
TB4MR
00XX 0000b
031Dh
Timer B5 Mode Register
TB5MR
00XX 0000b
External Interrupt Source Select Register
IFSR
00h
031Eh
031Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 27 of 67
M32C/8B Group
Table 4.7
4. Special Function Registers (SFRs)
SFR Address Map (7/11)
Address
Register
Symbol
After Reset
0320h
0321h
0322h
0323h
0324h
UART3 Special Mode Register 4
U3SMR4
00h
0325h
UART3 Special Mode Register 3
U3SMR3
00h
0326h
UART3 Special Mode Register 2
U3SMR2
00h
0327h
UART3 Special Mode Register
U3SMR
00h
0328h
UART3 Transmit/Receive Mode Register
U3MR
00h
0329h
UART3 Baud Rate Register
U3BRG
XXh
UART3 Transmit Buffer Register
U3TB
XXXXh
032Ch
UART3 Transmit/Receive Control Register 0
U3C0
0000 1000b
032Dh
UART3 Transmit/Receive Control Register 1
U3C1
0000 0010b
UART3 Receive Buffer Register
U3RB
XXXXh
0334h
UART2 Special Mode Register 4
U2SMR4
00h
0335h
UART2 Special Mode Register 3
U2SMR3
00h
0336h
UART2 Special Mode Register 2
U2SMR2
00h
0337h
UART2 Special Mode Register
U2SMR
00h
032Ah
032Bh
032Eh
032Fh
0330h
0331h
0332h
0333h
0338h
UART2 Transmit/Receive Mode Register
U2MR
00h
0339h
UART2 Baud Rate Register
U2BRG
XXh
UART2 Transmit Buffer Register
U2TB
XXXXh
033Ch
UART2 Transmit/Receive Control Register 0
U2C0
0000 1000b
033Dh
UART2 Transmit/Receive Control Register 1
U2C1
0000 0010b
UART2 Receive Buffer Register
U2RB
XXXXh
0340h
Count Start Register
TABSR
00h
0341h
Clock Prescaler Reset Register
CPSRF
0XXX XXXXb
0342h
One-Shot Start Register
ONSF
00h
033Ah
033Bh
033Eh
033Fh
0343h
Trigger Select Register
TRGSR
00h
0344h
Up/Down Select Register
UDF
00h
Timer A0 Register
TA0
XXXXh
Timer A1 Register
TA1
XXXXh
Timer A2 Register
TA2
XXXXh
Timer A3 Register
TA3
XXXXh
Timer A4 Register
TA4
XXXXh
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 28 of 67
M32C/8B Group
Table 4.8
4. Special Function Registers (SFRs)
SFR Address Map (8/11)
Address
0350h
Register
Symbol
After Reset
Timer B0 Register
TB0
XXXXh
Timer B1 Register
TB1
XXXXh
Timer B2 Register
TB2
XXXXh
0356h
Timer A0 Mode Register
TA0MR
00h
0357h
Timer A1 Mode Register
TA1MR
00h
0358h
Timer A2 Mode Register
TA2MR
00h
0359h
Timer A3 Mode Register
TA3MR
00h
035Ah
Timer A4 Mode Register
TA4MR
00h
035Bh
Timer B0 Mode Register
TB0MR
00XX 0000b
035Ch
Timer B1 Mode Register
TB1MR
00XX 0000b
0351h
0352h
0353h
0354h
0355h
035Dh
Timer B2 Mode Register
TB2MR
00XX 0000b
035Eh
Timer B2 Special Mode Register
TB2SC
XXXX XXX0b
035Fh
Count Source Prescaler Register(1)
TCSPR
0XXX 0000b
0364h
UART0 Special Mode Register 4
U0SMR4
00h
0365h
UART0 Special Mode Register 3
U0SMR3
00h
0366h
UART0 Special Mode Register 2
U0SMR2
00h
0367h
UART0 Special Mode Register
U0SMR
00h
0360h
0361h
0362h
0363h
0368h
UART0 Transmit/Receive Mode Register
U0MR
00h
0369h
UART0 Baud Rate Register
U0BRG
XXh
UART0 Transmit Buffer Register
U0TB
XXXXh
036Ch
UART0 Transmit/Receive Control Register 0
U0C0
0000 1000b
036Dh
UART0 Transmit/Receive Control Register 1
U0C1
0000 0010b
UART0 Receive Buffer Register
U0RB
XXXXh
0378h
DMA0 Request Source Select Register
DM0SL
0X00 0000b
0379h
DMA1 Request Source Select Register
DM1SL
0X00 0000b
037Ah
DMA2 Request Source Select Register
DM2SL
0X00 0000b
037Bh
DMA3 Request Source Select Register
DM3SL
0X00 0000b
CRC Data Register
CRCD
XXXXh
CRC Input Register
CRCIN
XXh
036Ah
036Bh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
037Ch
037Dh
037Eh
037Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
NOTE:
1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 29 of 67
M32C/8B Group
Table 4.9
4. Special Function Registers (SFRs)
SFR Address Map (9/11)
Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
Register
Symbol
After Reset
A/D0 Register 0
AD00
00XXh
A/D0 Register 1
AD01
00XXh
A/D0 Register 2
AD02
00XXh
A/D0 Register 3
AD03
00XXh
A/D0 Register 4
AD04
00XXh
A/D0 Register 5
AD05
00XXh
A/D0 Register 6
AD06
00XXh
A/D0 Register 7
AD07
00XXh
A/D0 Control Register 4
AD0CON4
XXXX 00XXb
0390h
0391h
0392h
0393h
0394h
A/D0 Control Register 2
AD0CON2
XX0X X000b
0395h
A/D0 Control Register 3
AD0CON3
XXXX X000b
0396h
A/D0 Control Register 0
AD0CON0
00h
0397h
A/D0 Control Register 1
AD0CON1
00h
0398h
D/A Register 0
DA0
XXh
D/A Register 1
DA1
XXh
D/A Control Register
DACON
XXXX XX00b
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
X: Undefined
Blank spaces are all reserved. No access is allowed.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 30 of 67
M32C/8B Group
Table 4.10
4. Special Function Registers (SFRs)
SFR Address Map (10/11)
Address
Register
Symbol
After Reset
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
Function Select Register C
PSC
00X0 0000b
03B0h
Function Select Register A0
PS0
00h
03B1h
Function Select Register A1
PS1
00h
03B2h
Function Select Register B0
PSL0
00h
03B3h
Function Select Register B1
PSL1
00h
03B4h
Function Select Register A2
PS2
00X0 0000b
03B5h
Function Select Register A3
PS3
00h
03B6h
Function Select Register B2
PSL2
00X0 0000b
03B7h
Function Select Register B3
PSL3
00h
03C0h
Port P6 Register
P6
XXh
03C1h
Port P7 Register
P7
XXh
03C2h
Port P6 Direction Register
PD6
00h
03C3h
Port P7 Direction Register
PD7
00h
03C4h
Port P8 Register
P8
XXh
03C5h
Port P9 Register
P9
XXh
03C6h
Port P8 Direction Register
PD8
00X0 0000b
03C7h
Port P9 Direction Register
PD9
00h
03C8h
Port P10 Register
P10
XXh
03C9h
Port P11 Register(1)
P11
XXh
03CAh
Port P10 Direction Register
PD10
00h
03CBh
Port P11 Direction Register(1)(2)
PD11
XXX0 0000b
03CCh
Port P12 Register(1)
P12
XXh
03CDh
Port P13 Register(1)
P13
XXh
03CEh
Port P12 Direction Register(1)(2)
PD12
00h
03CFh
Port P13 Direction Register(1)(2)
PD13
00h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
X: Undefined
Blank spaces are all reserved. No access is allowed.
NOTES:
1. These registers cannot be used in the 100-pin package.
2. Set to FFh in the 100-pin package.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 31 of 67
M32C/8B Group
Table 4.11
4. Special Function Registers (SFRs)
SFR Address Map (11/11)
Address
Register
Symbol
After Reset
03D0h
Port P14 Register(1)
P14
XXh
03D1h
Port P15 Register(1)
P15
XXh
03D2h
Port P14 Direction Register(1)(2)
PD14
X000 0000b
03D3h
Port P15 Direction Register(1)(2)
PD15
00h
03DAh
Pull-Up Control Register 2
PUR2
00h
03DBh
Pull-Up Control Register 3
PUR3
00h
03DCh
Pull-Up Control Register 4(1)(3)
PUR4
XXXX 0000b
03E0h
Port P0 Register
P0
XXh
03E1h
Port P1 Register
P1
XXh
03E2h
Port P0 Direction Register
PD0
00h
03E3h
Port P1 Direction Register
PD1
00h
03E4h
Port P2 Register
P2
XXh
03E5h
Port P3 Register
P3
XXh
03E6h
Port P2 Direction Register
PD2
00h
03E7h
Port P3 Direction Register
PD3
00h
03E8h
Port P4 Register
P4
XXh
03E9h
Port P5 Register
P5
XXh
03EAh
Port P4 Direction Register
PD4
00h
03EBh
Port P5 Direction Register
PD5
00h
03F0h
Pull-Up Control Register 0
PUR0
00h
03F1h
Pull-Up Control Register 1
PUR1
XXXX 0000b
Port Control Register
PCR
XXXX X000b
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DDh
03DEh
03DFh
03ECh
03EDh
03EEh
03EFh
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
X: Undefined
Blank spaces are all reserved. No access is allowed.
NOTES:
1. These registers cannot be used in the 100-pin package.
2. Set to FFh in the 100-pin package.
3. Set to 00h in the 100-pin package.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 32 of 67
M32C/8B Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Symbol
Parameter
Condition
Value
Unit
VCC1,
VCC2
Supply voltage
VCC1 = AVCC
-0.3 to 6.0
V
VCC2
Supply voltage
−
-0.3 to VCC1 + 0.1
V
AVCC
Analog supply voltage
VCC1 = AVCC
-0.3 to 6.0
V
VI
Input voltage
RESET, CNVSS, BYTE, P6_0 to P6_7,
P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P14_0 to P14_6, P15_0 to P15_7(1),
VREF, XIN
-0.3 to VCC1 + 0.3
V
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(1)
-0.3 to VCC2 + 0.3
P7_0, P7_1
VO
Output voltage
-0.3 to 6.0
P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P14_0 to 14_6, P15_0 to P15_7(1),
XOUT
-0.3 to VCC1 + 0.3
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(1)
-0.3 to VCC2 + 0.3
P7_0, P7_1
Pd
Power consumption
Topr
Operating
ambient
temperature
Tstg
-0.3 to 6.0
-40°C≤Topr≤85°C
during CPU operation
during programming or erasing Flash
memory
Storage temperature
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
2. Contact a Renesas sales office if temperature range of -40 to 85°C is required.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 33 of 67
V
500
mW
-20 to 85/
-40 to 85(2)
°C
0 to 60
°C
-65 to 150
°C
M32C/8B Group
Table 5.2
5. Electrical Characteristics
Recommended Operating Conditions (1/3)
(VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85°C unless otherwise specified)
Symbol
Parameter
VCC1,
VCC2
Supply voltage (VCC1 ≥ VCC2)
AVCC
Analog supply voltage
Standard
Min.
Typ.
Max.
3.0
5.0
5.5
VCC1
Unit
V
V
VSS
Supply voltage
0
V
AVSS
Analog supply voltage
0
V
VIH
0.8VCC2
Input high “H” P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7,
voltage
P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(2)
VCC2
0.8VCC1
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7(1),
P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6,
P15_0 to P15_7(2),
XIN, RESET, CNVSS, BYTE
VCC1
P7_0, P7_1
VIL
Input low “L”
voltage
0.8VCC1
V
6.0
P0_0 to P0_7, P1_0 to P1_7 (in single-chip mode) 0.8VCC2
VCC2
P0_0 to P0_7, P1_0 to P1_7
(in memory expansion mode and microprocessor
mode)
0.5VCC2
VCC2
P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7,
P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(2)
0
0.2VCC2
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7(1),
P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6,
P15_0 to P15_7(2),
XIN, RESET, CNVSS, BYTE
0
0.2VCC1
P0_0 to P0_7, P1_0 to P1_7 (in single-chip mode)
0
0.2VCC2
P0_0 to P0_7, P1_0 to P1_7
(in memory expansion mode and microprocessor
mode)
0
0.16VCC2
V
NOTES:
1. VIH and VIL reference for P8_7 apply when P8_7 is used as a programmable input port. It does not apply when
P8_7 is used as XCIN.
2. P11 to P15 are provided in the 144-pin package only.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 34 of 67
M32C/8B Group
Table 5.3
5. Electrical Characteristics
Recommended Operating Conditions (2/3)
(VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85°C unless otherwise specified)
Symbol
Parameter
Standard
Min.
Typ.
Max.
Unit
IOH(peak)
Peak output
high “H”
current(2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(3)
-10.0
mA
IOH(avg)
Average
output high
“H” current(1)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(3)
-5.0
mA
IOL(peak)
Peak output
low “L”
current(2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(3)
10.0
mA
IOL(avg)
Average
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
output low “L” P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
current(1)
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(3)
5.0
mA
NOTES:
1. Average output current is the average value within 100 ms.
2. A total IOL(peak) of P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14, and P15 must be 80 mA or less.
A total IOL(peak) of P3, P4, P5, P6, P7,P8_0 to P8_4, P12, and P13 must be 80 mA or less.
A total IOH(peak) of P0, P1, P2, and P11 must be -40 mA or less.
A total IOH(peak) of P8_6 to P8_7, P9, P10, P14, and P15 must be -40 mA or less.
A total IOH(peak) of P3, P4, P5, P12, and P13 must be -40 mA or less.
A total IOH(peak) of P6, P7, and P8_0 to P8_4 must be -40 mA or less.
3. P11 to P15 are provided in the 144-pin package only.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 35 of 67
M32C/8B Group
Table 5.4
5. Electrical Characteristics
Recommended Operating Conditions (3/3)
(VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85°C unless otherwise specified)
Symbol
Standard
Parameter
Min.
Typ.
Max.
Unit
f(CPU)
CPU clock frequency
(same frequency as f(BCLK))
VCC1 = 3.0 to 5.5V
0
32
MHz
f(XIN)
Main clock input frequency
VCC1 = 3.0 to 5.5V
0
16
MHz
f(XCIN)
Sub clock frequency
32.768
50
kHz
f(Ring)
On-chip oscillator frequency
1
2
MHz
f(PLL)
PLL clock frequency
VCC1 = 3.0 to 5.5V
32
MHz
tsu(PLL)
Wait time to stabilize PLL frequency
synthesizer
VCC1 = 5.0V
20
ms
VCC1 = 3.3V
50
ms
Table 5.5
Symbol
−
−
−
−
−
0.5
10
Flash Memory Electrical Characteristics (VCC1 = VCC2 = 3.0 V to 5.5 V,
Topr = 0 to 60°C unless otherwise specified)
Parameter
Measurement Condition
Min.
Standard
Typ. Max.
CPU clock frequency (in CPU rewrite mode)(2)
Erase and program
10
endurance(1)
Program time (4 bytes) (Topr = 25°C)
Lock bit program time
Block erase time (Topr = 25°C)
tps
Wait time to stabilize flash memory circuit
−
Data hold time (Topr = -40 to 85°C)
100
Unit
MHz
times
Other than Data flash
150
900
Data flash
300
1700
Other than Data flash
70
500
Data flash
140
1000
4-Kbyte block
0.2
3
s
8-Kbyte block
0.2
3
s
64-Kbyte block
0.2
3
s
50
μs
10
μs
μs
years
NOTES:
1. If erase and program endurance is n times (n = 100), each block can be erased n times. For example, if a 4Kbyte block A is erased after programming four-byte data 1,024 times, each to a different address, this counts
as one erase and program time. Data cannot be programmed to the same address more than once without
erasing the block (rewrite prohibited).
2. Prior to accessing registers FMR0 to FMR3 or to entering CPU rewrite mode (EW0, EW1 mode), set the CPU
clock frequency to 10 MHz or lower using bits MCD4 to MCD0 in the MCD register, and also set the PM12 bit in
the PM1 register to 1 (1 wait state).
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 36 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 5.6
Electrical Characteristics (1/3)
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 32 MHz unless
otherwise specified)
Symbol
VOH
Parameter
Output
high “H”
voltage
Max.
VCC2 - 2.0
VCC2
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P14_0 to P14_6, P15_0 to P15_7(1)
IOH = -5 mA
VCC1 - 2.0
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7 IOH = -200 μA VCC2 - 0.3
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(1)
VCC2
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, IOH = -200 μA VCC1 - 0.3
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P14_0 to P14_6, P15_0 to P15_7(1)
VCC1
XOUT
VCC1
IOH = -1 mA
V
V
V
No load
applied
2.5
V
Drive capability
= low
No load
applied
1.7
V
XOUT
XCOUT
3.0
Unit
Drive capability
= high
Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
“L” voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1)
Hysteresis
Typ.
IOH = -5 mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1)
VT+ - VT-
Standard
Min.
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(1)
XCOUT
VOL
Condition
IOL = 5 mA
2.0
V
IOL = 200 μA
0.45
V
IOL = 1 mA
2.0
V
Drive capability
= high
No load
applied
0
V
Drive capability
= low
No load
applied
0
V
HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT5, ADTRG,
CTS0 to CTS4, CLK0 to CLK4,
TA0OUT to TA4OUT, NMI, KI0 to KI3,
RXD0 to RXD4, SCL0 to SCL4,
SDA0 to SDA4
0.2
1.0
V
RESET
0.2
1.8
V
NOTE:
1. P11 to P15 are provided in the 144-pin package only.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 37 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 5.7
Electrical Characteristics (2/3)
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 32 MHz unless
otherwise specified)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
IIH
Input high
“H” current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1), XIN, RESET, CNVSS,
BYTE
VI = 5 V
5.0
μA
IIL
Input low “L” P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
current
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1), XIN, RESET, CNVSS,
BYTE
VI = 0V
-5.0
μA
170
kΩ
RPULLUP Pull-up
resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1)
RfXIN
Feedback
resistance
XIN
1.5
MΩ
RfXCIN
Feedback
resistance
XCIN
15
MΩ
VRAM
RAM data
retention
voltage
In stop mode
NOTE:
1. P11 to P15 are provided in the 144-pin package only.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 38 of 67
VI = 0V
30
2.0
50
V
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 5.8
Electrical Characteristics (3/3) (VCC1 = VCC2 = 5.5 V, VSS = 0 V, Topr = 25°C)
Condition(1)
Symbol Parameter
ICC
Power
supply
current
f(CPU) = 32 MHz
f(CPU) = 16 MHz
f(CPU) = 8 MHz
f(CPU) = f(Ring)(3)
In on-chip oscillator low-power consumption mode
In on-chip oscillator low-power consumption mode, flash memory is
stopped(2)
f(CPU) = 32 kHz(4)
In low-power consumption mode, flash memory is operating
f(CPU) = 32 kHz(5)
In low-power consumption mode, flash memory is stopped(2)
Wait mode: f(CPU) = f(Ring)
After entering wait mode from on-chip oscillator low-power
consumption mode
Wait mode: f(CPU) = 32kHz(6)
After entering wait mode from low-power consumption mode
Stop mode (clock is stopped)
Stop mode (clock is stopped) Topr = 85°C
Standard
Unit
Min. Typ. Max.
26
42 mA
16
mA
10
mA
1.5
mA
400
μA
430
μA
50
μA
110
μA
10
μA
4
μA
μA
200
NOTES:
1. In single-chip mode, leave the output pins open and connect the input pins to VSS.
2. When setting the FMSTP bit in the FMR0 register to 1 (flash memory stopped) and running the program on
RAM.
3. When the FMR40 bit in the FMR4 register is set to 1 (low-speed access).
4. When the FMR40 bit is set to 1 and the MRS bit in the VRCR register is set to 1 (main voltage regulator stops).
5. When the MRS bit is set to 1.
6. When the MRS bit is set to 1 and the CM0 bit in the CM03 register is set to 0 (XCIN-XCOUT drive capability
Low).
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 39 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 5.9
Symbol
A/D Conversion Characteristics
(VCC1 = VCC2 = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85°C,
f(CPU) = 32MHz unless otherwise specified)
Parameter
Measurement Condition
−
Resolution
VREF = VCC1
INL
Integral nonlinearity error
VREF = VCC1
= VCC2 = 5 V
Standard
Min.
Typ.
Max.
Unit
10
Bits
AN_0 to AN_7,
AN0_0 to AN0_7,
AN2_0 to AN2_7,
AN15_0 to AN15_7,
ANEX0, ANEX1
±3
LSB
External op-amp
connection mode
±7
LSB
DNL
Differential nonlinearity
error
±1
LSB
−
Offset error
±3
LSB
−
Gain error
±3
LSB
20
kΩ
RLADDER Resistor ladder
VREF = VCC1
4
tCONV
10-bit conversion time(1)(2)
2.06
μs
tCONV
8-bit conversion time(1)(2)
1.75
μs
tSAMP
Sampling
time(1)
0.188
μs
VREF
Reference voltage
3
VCC1
V
VIA
Analog input voltage
0
VREF
V
NOTES:
1. The value is obtained when φAD frequency is at 16 MHz. Keep φAD frequency at 16 MHz or lower.
2. With using the sample and hold function
Table 5.10
Symbol
D/A Conversion Characteristics
(VCC1 = VCC2 = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85°C,
f(CPU) = 32MHz unless otherwise specified)
Parameter
−
Resolution
−
Absolute accuracy
tsu
Setup time
RO
Output resistance
IVREF
Reference power supply
input current
Measurement Condition
Standard
Min.
4
(note 1)
Typ.
10
Max.
Unit
8
Bits
1.0
%
3
μs
20
kΩ
1.5
mA
NOTE:
1. Measured when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set to
00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if the VCUT
bit in the AD0CON1 register is set to 0 (VREF not connected).
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 40 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 5.11
Voltage Detection Circuit Electrical Characteristics
(VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, Topr = 25°C unless otherwise specified)
Symbol
ΔVdet
Table 5.12
Symbol
Standard
Parameter
Min.
Detection voltage level accuracy
Typ.
VCC1 = 3.0 V to 5.5 V
Max.
±0.30
Unit
V
Power Supply Timing Characteristics
Parameter
Measurement Condition
Standard
Min.
Typ.
Max.
Unit
td(P-R)
Wait time to stabilize internal supply voltage
when power-on
VCC1 = 3.0 to 5.5 V
2
ms
td(E-A)
Start-up time for Vdet detection circuit
VCC1 = 3.0 to 5.5 V
150
μs
td(P-R)
Wait time to stabilize internal
supply voltage when power-on
Recommended
operating voltage
VCC1
td(P-R)
CPU clock
td(E-A)
Start-up time for Vdet detection
circuit
VDEN
Vdet detection circuit
Stop
Operating
td(E-A)
Figure 5.1
Power Supply Timing Diagram
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 41 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.13
External Clock Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc
External clock input cycle time
62.5
ns
tw(H)
External clock input high (“H”) pulse width
27.5
ns
tw(L)
External clock input low (“L”) pulse width
27.5
ns
tr
External clock rise time
5
ns
tf
External clock fall time
5
ns
Table 5.14
Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
100
ns
tw(TAH)
TAiIN input high (“H”) pulse width
40
ns
tw(TAL)
TAiIN input low (“L”) pulse width
40
ns
i = 0 to 4
Table 5.15
Timer A Input (Gate Signal Input in Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
400
ns
tw(TAH)
TAiIN input high (“H”) pulse width
200
ns
tw(TAL)
TAiIN input low (“L”) pulse width
200
ns
i = 0 to 4
Table 5.16
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
TAiIN input high (“H”) pulse width
100
ns
tw(TAL)
TAiIN input low (“L”) pulse width
100
ns
i = 0 to 4
Table 5.17
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(TAH)
TAiIN input high (“H”) pulse width
100
ns
tw(TAL)
TAiIN input low (“L”) pulse width
100
ns
i = 0 to 4
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 42 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.18
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
tc(UP)
Parameter
TAiOUT input cycle time
Standard
Min.
Max.
2000
Unit
ns
tw(UPH)
TAiOUT input high (“H”) pulse width
1000
ns
tw(UPL)
TAiOUT input low (“L”) pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
i = 0 to 4
Table 5.19
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Symbol
tc(TA)
Parameter
TAiIN input cycle time
Standard
Min.
Max.
Unit
800
ns
tsu(TAIN-TAOUT) TAiOUT input setup time
200
ns
tsu(TAOUT-TAIN) TAiIN input setup time
200
ns
i = 0 to 4
Table 5.20
Timer B Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input high (“H”) pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input low (“L”) pulse width (counted on one edge)
40
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
200
ns
tw(TBH)
TBiIN input high (“H”) pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input low (“L”) pulse width (counted on both edges)
80
ns
i = 0 to 5
Table 5.21
Timer B Input (Pulse Period Measurement Mode)
Symbol
tc(TB)
Parameter
TBiIN input cycle time
Standard
Min.
Max.
Unit
400
ns
tw(TBH)
TBiIN input high (“H”) pulse width
200
ns
tw(TBL)
TBiIN input low (“L”) pulse width
200
ns
i = 0 to 5
Table 5.22
Timer B Input (Pulse Width Measurement Mode)
Symbol
tc(TB)
Parameter
TBiIN input cycle time
Standard
Min.
Max.
Unit
400
ns
tw(TBH)
TBiIN input high (“H”) pulse width
200
ns
tw(TBL)
TBiIN input low (“L”) pulse width
200
ns
i = 0 to 5
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 43 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.23
A/D Trigger Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(AD)
ADTRG input cycle time (required for trigger)
1000
ns
tw(ADL)
ADTRG input low (“L”) pulse width
125
ns
tw(ADH)
ADTRG input high (“H”) pulse width
3
φAD
Table 5.24
Serial Interface
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high (“H”) pulse width
100
ns
tw(CKL)
CLKi input low (“L”) pulse width
100
ns
td(C-Q)
TXDi output delay time
80
ns
th(C-Q)
TXDi output hold time
0
ns
tsu(D-C)
RXDi input setup time
80
ns
th(C-D)
RXDi input hold time
90
ns
i=0 to 4
Table 5.25
External Interrupt INTi Input (Edge Sensitive)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(INH)
INTi input high (“H”) pulse width
250
ns
tw(INL)
INTi input low (“L”) pulse width
250
ns
i=0 to 5
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 44 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.26
Memory Expansion mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data input access time (RD standard)
(note 1)
ns
tac1(AD-DB)
Data input access time (AD standard, CS standard)
(note 1)
ns
(note 1)
ns
(note 1)
ns
tac2(RD-DB)
tac2(AD-DB)
Data input access time (RD standard, when accessing a space with the
multiplexed bus)
Data input access time (AD standard, when accessing a space with the
multiplexed bus)
tsu(DB-BCLK)
Data input setup time
26
ns
tsu(RDY-BCLK)
RDY input setup time
26
ns
30
ns
tsu(HOLD-BCLK) HOLD input setup time
th(RD-DB)
Data input hold time
0
ns
th(BCLK-RDY)
RDY input hold time
0
ns
th(BCLK-HOLD)
HOLD input hold time
0
ns
td(BCLK-HLDA)
HLDA output delay time
25
ns
NOTE:
1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) =
109 × m
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) + 1)
tac1(AD-DB) =
109 × n
f(BCLK)
tac2(RD-DB) =
109 × m
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
tac2(AD-DB) =
109 × p
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, p = {(a + b - 1) × 2} + 1)
- 35 [ns] (if external bus cycle is aφ + bφ, n = a + b)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 45 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Switching Characteristics
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.27
Memory Expansion Mode and Microprocessor Mode (when accessing external
memory space)
Symbol
Measurement
Condition
Parameter
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
18
standard)(3)
th(RD-AD)
Address output hold time (RD
th(WR-AD)
Address output hold time (WR standard)(3)
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
Chip-select signal output hold time (RD
th(WR-CS)
Chip-select signal output hold time (WR standard)(3)
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(DB-WR)
Data output delay time (WR standard)
Data output hold time (WR
tw(WR)
WR output width
0
ns
ns
ns
0
ns
ns
18
-5
109
f(BCLK) × 2
18
109
f(BCLK) × 2
- 10 [ns]
th(WR-CS) =
109
f(BCLK) × 2
- 10 [ns]
ns
(note 2)
ns
(note 1)
ns
(note 2)
ns
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations.
td(DB-WR)
=
tw(WR)
=
109 × m
f(BCLK)
109 × n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is aφ + bφ, m = b)
- 15 [ns] (if external bus cycle is aφ + bφ, n = (b × 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 46 of 67
ns
-5
- 10 [ns]
th(WR-AD) =
ns
ns
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) =
ns
-3
See Figure 5.2 (note 1)
standard)(3)
ns
ns
(note 1)
standard)(3)
Unit
-3
18
th(RD-CS)
th(WR-DB)
Standard
Min.
Max.
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 5V
Switching Characteristics
(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.28
Memory Expansion Mode and Microprocessor Mode
(when accessing external memory space with multiplexed bus)
Symbol
Measurement
Condition
Parameter
Standard
Min.
Max.
18
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
-3
ns
th(RD-AD)
Address output hold time (RD standard)(5)
(note 1)
ns
th(WR-AD)
Address output hold time (WR
standard)(5)
(note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
-3
ns
th(RD-CS)
Chip-select signal output hold time (RD standard)(5)
(note 1)
ns
th(WR-CS)
Chip-select signal output hold time (WR
standard)(5)
(note 1)
ns
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
ALE signal output delay time (BCLK standard)
th(BCLK-ALE)
ALE signal output hold time (BCLK standard)
td(AD-ALE)
th(ALE-AD)
tdz(RD-AD)
Address output float start time
18
18
See Figure 5.2
-5
ns
ns
ns
ns
18
ns
-5
ns
Data output delay time (WR standard)
(note 2)
ns
Data output hold time (WR standard)(5)
(note 1)
ns
18
ns
-2
ns
ALE signal output delay time (address standard)
(note 3)
ns
ALE signal output hold time (address standard)
(note 4)
ns
8
ns
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD)
=
109
f(BCLK) × 2
- 10 [ns]
th(WR-AD) =
109
f(BCLK) × 2
- 10 [ns]
th(RD-CS)
=
109
f(BCLK) × 2
- 10 [ns]
th(WR-CS) =
109
f(BCLK) × 2
- 10 [ns]
th(WR-DB) =
109
f(BCLK) × 2
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) =
109 × m
f(BCLK) × 2
- 25 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) =
109 × n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is aφ + bφ, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) =
109 × n
f(BCLK) × 2
- 10 [ns] (if external bus cycle is aφ + bφ, n = a)
5. tc [ns] is added when recovery cycle is inserted.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 47 of 67
M32C/8B Group
5. Electrical Characteristics
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
30 pF
Note 1
NOTE:
1. P11 to P15 are provided in the 144-pin package only.
Figure 5.2
P0 to P15 Measurement Circuit
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 48 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1=VCC2=5V
tc
XIN input
tr
tf
tw(H)
tw(L)
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/
decrement select input)
In event counter mode
th(TIN-UP)
TAiIN input (count on falling edge)
tsu(UP-TIN)
TAiIN input (count on rising edge)
In event counter mode with two-phase pulse
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
TAiOUT input
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tw(ADH)
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
RXDi
tw(INL)
INTi input
tw(INH)
NMI input
2 CPU clock cycles
+ 300 ns or more
("L" width)
Figure 5.3
VCC1 = VCC2 = 5 V Timing Diagram (1)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 49 of 67
2 CPU clock cycles
+ 300 ns or more
th(C-D)
M32C/8B Group
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode and Microprocessor Mode
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK)
th(BCLK-RDY)
BCLK
th(BCLK-HOLD)
tsu(HOLD-BCLK)
HOLD Input
HLDA Output
td(BCLK-HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2
td(BCLK-HLDA)
Hi-Z
Measurement Conditions
- VCC1 = VCC2 = 4.2 to 5.5 V
- Input high and low voltage: VIH = 4.0 V, VIL = 1.0 V
- Output high and low voltage: VOH = 2.5 V, VOL = 2.5 V
Figure 5.4
VCC1 = VCC2 = 5 V Timing Diagram (2)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 50 of 67
M32C/8B Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
VCC1=VCC2=5V
Read Timing (1φ + 1φ Bus Cycle)
BCLK
th(BCLK-CS)
-3ns.min
td(BCLK-CS)
18ns.max(1)
CSi
tcyc
th(RD-CS)
0ns.min
td(BCLK-AD)
18ns.max(1)
th(BCLK-AD)
-3ns.min
ADi
BHE
th(RD-AD)
0ns.min
td(BCLK-RD)
18ns.max
RD
th(BCLK-RD)
-5ns.min
tac1(RD-DB)(2)
tac1(AD-DB)(2)
DBi
Hi-Z
tsu(DB-BCLK)
26ns.min(1)
th(RD-DB)
0ns.min
NOTES:
1. Values guaranteed only when the MCU is used stand-alone.
A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK).
2. Varies with operation frequency:
tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + bφ, m = (b x 2) + 1)
tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle aφ + bφ, n = a + b)
Write Timing (1φ + 1φ Bus Cycle)
BCLK
th(BCLK-CS)
-3ns.min
td(BCLK-CS)
18ns.max(1)
CSi
tcyc
th(WR-CS)(3)
td(BCLK-AD)
18ns.max(1)
th(BCLK-AD)
-3ns.min
ADi
BHE
td(BCLK-WR)
18ns.max
th(WR-AD)(3)
tw(WR)(3)
WR,WRL,WRH
th(BCLK-WR)
-5ns.min
td(DB-WR)(3)
th(WR-DB)(3)
DBi
NOTES:
3. Varies with operation frequency:
td(DB-WR) = (tcyc x m - 20) ns.min
( if external bus cycle aφ + bφ, m = b)
th(WR-DB) = (tcyc / 2 - 10) ns.min
th(WR-AD) = (tcyc / 2 - 10) ns.min
th(WR-CS) = (tcyc / 2 - 10) ns.min
tw(WR) = (tcyc / 2 x n - 15) ns.min
( if external bus cycle aφ + bφ, n = (b x 2) - 1)
Figure 5.5
Measurement Conditions:
- VCC1 = VCC2 = 4.2 to 5.5 V
- Input high and low voltage: VIH = 2.5 V, VIL = 0.8 V
- Output high and low voltage: VOH = 2.0 V, VOL = 0.8 V
VCC1 = VCC2 = 5 V Timing Diagram (3)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 51 of 67
tcyc=
109
f(BCLK)
M32C/8B Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
VCC1=VCC2=5V
Read Timing (2φ + 2φ Bus Cycle)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max
th(BCLK-CS)
-3ns.min
tcyc
th(RD-CS)(1)
CSi
ADi /DBi
tsu(DB-BCLK) 26ns.min
th(ALE-AD)(1)
td(AD-ALE)(1)
Address
Data input
Address
tdz(RD-AD)
8ns.max
td(BCLK-AD)
18ns.max
th(RD-DB) 0ns.min
th(BCLK-AD)
-3ns.min
tac2(RD-DB)(1)
ADi
BHE
th(RD-AD)(1)
tac2(AD-DB)(1)
td(BCLK-RD)
18ns.max
RD
th(BCLK-RD)
-5ns.min
NOTES:
1. Varies with operation frequency:
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a φ + bφ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a φ + bφ, n = a)
th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min
tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + bφ, m = (b x 2) - 1)
tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a φ + bφ, p = {(a + b - 1) x 2} + 1)
Write Timing (2φ + 2φ Bus Cycle)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max
th(BCLK-CS)
-3ns.min
tcyc
th(WR-CS)(2)
CSi
td(AD-ALE)(2)
th(ALE-AD)(2)
Address
ADi /DBi
Data output
td(DB-WR)(2)
td(BCLK-AD)
18ns.max
Address
th(WR-DB)(2)
th(BCLK-AD)
-3ns.min
ADi
BHE
td(BCLK-WR)
18ns.max
WR,WRL,WRH
th(BCLK-WR)
-5ns.min
th(WR-AD)(2)
NOTES:
1. Varies with operation frequency:
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a φ + bφ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a φ + bφ, n = a)
th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min
th(WR-DB) = (tcyc / 2 - 10) ns.min
td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a φ + bφ, m = (b x 2) - 1)
tcyc=
Figure 5.6
109
f(BCLK)
VCC1 = VCC2 = 5 V Timing Diagram (4)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 52 of 67
Measurement Conditions:
- VCC1 = VCC2 = 4.2 to 5.5 V
- Input high and low voltage VIH = 2.5 V, VIL = 0.8 V
- Output high and low voltage VOH = 2.0 V, VOL = 0.8 V
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.29
Electrical Characteristics (1/3)
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 24 MHz unless otherwise
specified)
Symbol
VOH
Parameter
Output
high “H”
voltage
Condition
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7(1)
IOH = -1 mA
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P14_0 to P14_6, P15_0 to P15_7(1)
XOUT
XCOUT
VOL
IOH = -0.1 mA
Hysteresis
Typ.
Max.
VCC2 - 0.6
VCC2
VCC1 - 0.6
VCC1
2.7
VCC1
Unit
V
V
No load
applied
2.5
V
Drive capability
= low
No load
applied
1.7
V
XOUT
VT+ - VT-
Min.
Drive capability
= high
Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
“L” voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1)
XCOUT
Standard
IOL = 1 mA
0.5
V
IOL = 0.1 mA
0.5
V
Drive capability
= high
No load
applied
0
V
Drive capability
= low
No load
applied
0
V
HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT5, ADTRG,
CTS0 to CTS4, CLK0 to CLK4,
TA0OUT to TA4OUT, NMI, KI0 to KI3,
RXD0 to RXD4, SCL0 to SCL4,
SDA0 to SDA4
0.2
1.0
V
RESET
0.2
1.8
V
NOTE:
1. P11 to P15 are provided in the 144-pin package only.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 53 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.30
Electrical Characteristics (2/3)
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C, f(CPU) = 24 MHz unless
otherwise specified)
Symbol
Standard
Parameter
Condition
IIH
Input high P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
“H” current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1), XIN, RESET, CNVSS,
BYTE
VI = 3 V
4.0
μA
IIL
Input low
“L” current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1), XIN, RESET, CNVSS,
BYTE
VI = 0V
-4.0
μA
RPULLUP Pull-up
resistance
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7,
P11_0 to P11_4, P12_0 to P12_7,
P13_0 to P13_7, P14_0 to P14_6,
P15_0 to P15_7(1)
VI=0V
500
kΩ
RfXIN
Feedback
resistance
XIN
3.0
MΩ
RfXCIN
Feedback
resistance
XCIN
25
MΩ
VRAM
RAM data
retention
voltage
In stop mode
NOTE:
1. P11 to P15 are provided in the 144-pin package only.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 54 of 67
Min.
50
2.0
Typ.
100
Max.
Unit
V
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.31
Electrical Characteristics (3/3) (VCC1 = VCC2 = 3.3 V, VSS = 0 V, Topr = 25°C)
Condition(1)
Symbol Parameter
ICC
Power
supply
current
f(CPU) = 32 MHz
f(CPU) = 16 MHz
f(CPU) = 8 MHz
f(CPU) = f(Ring)(3)
In on-chip oscillator low-power consumption mode
In on-chip oscillator low-power consumption mode, flash memory is
stopped(2)
f(CPU) = 32 kHz(4)
In low-power consumption mode, flash memory is operating
f(CPU) = 32 kHz(5)
In low-power consumption mode, flash memory is stopped(2)
Wait mode: f(CPU) = f(Ring)
After entering wait mode from on-chip oscillator low-power
consumption mode
Wait mode: f(CPU) = 32kHz(6)
After entering wait mode from low-power consumption mode
Stop mode (clock is stopped)
Stop mode (clock is stopped) Topr = 85°C
Standard
Unit
Min. Typ. Max.
23
37 mA
15
mA
9
mA
1.5
mA
400
μA
430
μA
50
μA
110
μA
8
μA
4
μA
μA
200
NOTES:
1. In single-chip mode, leave the output pins open and connect the input pins to VSS.
2. When setting the FMSTP bit in the FMR0 register to 1 (flash memory stopped) and running the program on
RAM.
3. When the FMR40 bit in the FMR4 register is set to 1 (low-speed access).
4. When the FMR40 bit is set to 1 and the MRS bit in the VRCR register is set to 1 (main voltage regulator stops).
5. When the MRS bit is set to 1.
6. When the MRS bit is set to 1 and the CM0 bit in the CM03 register is set to 0 (XCIN-XCOUT drive capability
Low).
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 55 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 5.32
A/D Conversion Characteristics
(VCC1 = VCC2 = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Topr = -20 to 85°C,
f(CPU) = 24MHz unless otherwise specified)
Symbol
Parameter
Measurement Condition
Standard
Min.
Typ.
Max.
Unit
−
Resolution
VREF = VCC1
10
Bits
INL
Integral nonlinearity error (8-bit)
VREF = VCC1 = VCC2 = 3.3 V
±2
LSB
DNL
Differential nonlinearity error (8-bit)
±1
LSB
−
Offset error (8-bit)
±2
LSB
−
Gain error (8-bit)
±2
LSB
20
kΩ
RLADDER Resistor ladder
VREF = VCC1
time(1)(2)
4
μs
4.9
tCONV
8-bit conversion
VREF
Reference voltage
3
VCC1
V
VIA
Analog input voltage
0
VREF
V
NOTES:
1. The value when φAD frequency is at 10 MHz. Keep φAD frequency at 10 MHz or lower.
If f(CPU) (=fAD) is 24 MHz, divide f(CPU) by 3 to make it 8 MHz. The conversion time in this case is 6.1 μs.
2. S&H not available.
Table 5.33
Symbol
D/A Conversion Characteristics
(VCC1 = VCC2 = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V at Topr = -20 to 85°C,
f(CPU) = 24MHz unless otherwise specified)
Parameter
−
Resolution
−
Absolute accuracy
tsu
Setup time
RO
Output resistance
IVREF
Reference power supply
input current
Measurement Condition
Standard
Min.
Typ.
Max.
8
4
(note 1)
10
Unit
Bits
1.0
%
3
μs
20
kΩ
1.0
mA
NOTE:
1. Measurement when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set
to 00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if VCUT
bit in the AD0CON1 register is set to 0 (VREF not connected).
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 56 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.34
External Clock Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc
External clock input cycle time
62.5
ns
tw(H)
External clock input high (“H”) pulse width
27.5
ns
tw(L)
External clock input low (“L”) pulse width
27.5
tr
External clock rise time
5
ns
tf
External clock fall time
5
ns
Table 5.35
ns
Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
100
ns
tw(TAH)
TAiIN input high (“H”) pulse width
40
ns
tw(TAL)
TAiIN input low (“L”) pulse width
40
ns
i = 0 to 4
Table 5.36
Timer A Input (Gate Signal Input in Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
400
ns
tw(TAH)
TAiIN input high (“H”) pulse width
200
ns
tw(TAL)
TAiIN input low (“L”) pulse width
200
ns
i = 0 to 4
Table 5.37
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
TAiIN input high (“H”) pulse width
100
ns
tw(TAL)
TAiIN input low (“L”) pulse width
100
ns
i = 0 to 4
Table 5.38
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tw(TAH)
TAiIN input high (“H”) pulse width
100
ns
tw(TAL)
TAiIN input low (“L”) pulse width
100
ns
i = 0 to 4
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 57 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.39
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(UP)
TAiOUT input cycle time
2000
ns
tw(UPH)
TAiOUT input high (“H”) pulse width
1000
ns
tw(UPL)
TAiOUT input low (“L”) pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
i = 0 to 4
Table 5.40
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
2
μs
tsu(TAIN-TAOUT) TAiOUT input setup time
500
ns
tsu(TAOUT-TAIN) TAiIN input setup time
500
ns
tc(TA)
TAiIN input cycle time
i = 0 to 4
Table 5.41
Timer B Input (Count Source Input in Event Counter Mode)
Symbol
tc(TB)
Parameter
Standard
Min.
Max.
Unit
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input high (“H”) pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input low (“L”) pulse width (counted on one edge)
40
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
200
ns
tw(TBH)
TBiIN input high (“H”) pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input low (“L”) pulse width (counted on both edges)
80
ns
i = 0 to 5
Table 5.42
Timer B Input (Pulse Period Measurement Mode)
Symbol
tc(TB)
Parameter
TBiIN input cycle time
Standard
Min.
Max.
Unit
400
ns
tw(TBH)
TBiIN input high (“H”) pulse width
200
ns
tw(TBL)
TBiIN input low (“L”) pulse width
200
ns
i = 0 to 5
Table 5.43
Timer B Input (Pulse Width Measurement Mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high (“H”) pulse width
200
ns
tw(TBL)
TBiIN input low (“L”) pulse width
200
ns
i = 0 to 5
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 58 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.44
A/D Trigger Input
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(AD)
ADTRG input cycle time (required for trigger)
1000
ns
tw(ADL)
ADTRG input low (“L”) pulse width
125
ns
tw(ADH)
ADTRG input high (“H”) pulse width
3
φAD
Table 5.45
Serial Interface
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high (“H”) pulse width
100
ns
tw(CKL)
CLKi input low (“L”) pulse width
100
ns
td(C-Q)
TXDi output delay time
80
ns
th(C-Q)
TXDi output hold time
0
ns
tsu(D-C)
RXDi input setup time
80
ns
th(C-D)
RXDi input hold time
90
ns
i=0 to 4
Table 5.46
External Interrupt INTi Input (Edge Sensitive)
Symbol
tw(INH)
tw(INL)
Parameter
Standard
Min.
Max.
Unit
INTi input high (“H”) pulse width
250
ns
INTi input low (“L”) pulse width
250
ns
i=0 to 5
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 59 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.47
Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min.
Max.
Unit
tac1(RD-DB)
Data input access time (RD standard)
(note 1)
ns
tac1(AD-DB)
Data input access time (AD standard, CS standard)
(note 1)
ns
(note 1)
ns
(note 1)
ns
tac2(RD-DB)
tac2(AD-DB)
Data input access time (RD standard, when accessing a space with the
multiplexed bus)
Data input access time (AD standard, when accessing a space with the
multiplexed bus)
tsu(DB-BCLK)
Data input setup time
tsu(RDY-BCLK)
RDY input setup time
tsu(HOLD-BCLK) HOLD input setup time
27
ns
30
ns
40
ns
th(RD-DB)
Data input hold time
0
ns
th(BCLK-RDY)
RDY input hold time
0
ns
th(BCLK-HOLD)
HOLD input hold time
0
td(BCLK-HLDA)
HLDA output delay time
ns
25
ns
NOTE:
1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) =
109 × m
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) + 1)
tac1(AD-DB) =
109 × n
f(BCLK)
tac2(RD-DB) =
109 × m
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
tac2(AD-DB) =
109 × p
f(BCLK) × 2
- 35 [ns] (if external bus cycle is aφ + bφ, p = {(a + b - 1) × 2} + 1)
- 35 [ns] (if external bus cycle is aφ + bφ, n = a + b)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 60 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.48
Memory Expansion Mode and Microprocessor Mode (when accessing external
memory space)
Symbol
Parameter
Measurement
Condition
Standard
Min.
Max.
18
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
0
ns
th(RD-AD)
Address output hold time (RD standard)(3)
0
ns
th(WR-AD)
Address output hold time (WR standard)(3)
(note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
0
ns
th(RD-CS)
Chip-select signal output hold time (RD standard)(3)
0
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)(3)
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(DB-WR)
th(WR-DB)
tw(WR)
18
See Figure 5.2 (note 1)
ns
ns
ns
18
-3
ns
ns
18
ns
0
ns
Data output delay time (WR standard)
(note 2)
ns
Data output hold time (WR standard)(3)
(note 1)
ns
WR output width
(note 2)
ns
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) =
109
f(BCLK) × 2
- 15 [ns]
th(WR-AD) =
109
f(BCLK) × 2
- 10 [ns]
th(WR-CS) =
109
f(BCLK) × 2
- 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following
equations.
td(DB-WR)
=
tw(WR)
=
109 × m
f(BCLK)
109 × n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is aφ + bφ, m = b)
- 15 [ns] (if external bus cycle is aφ + bφ, n = (b × 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 61 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.49
Memory Expansion Mode and Microprocessor Mode (when accessing external
memory space with multiplexed bus)
Symbol
Measurement
Condition
Parameter
Standard
Min.
Max.
18
Unit
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
0
ns
th(RD-AD)
Address output hold time (RD standard)(5)
(note 1)
ns
th(WR-AD)
Address output hold time (WR
standard)(5)
(note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
0
ns
th(RD-CS)
Chip-select signal output hold time (RD standard)(5)
(note 1)
ns
th(WR-CS)
Chip-select signal output hold time (WR
standard)(5)
(note 1)
ns
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
th(BCLK-WR)
WR signal output hold time
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
ALE signal output delay time (BCLK standard)
th(BCLK-ALE)
ALE signal output hold time (BCLK standard)
td(AD-ALE)
th(ALE-AD)
tdz(RD-AD)
Address output float start time
18
18
See Figure 5.2
-3
ns
ns
ns
ns
18
ns
0
ns
Data output delay time (WR standard)
(note 2)
ns
Data output hold time (WR standard)(5)
(note 1)
ns
18
ns
-2
ns
ALE signal output delay time (address standard)
(note 3)
ns
ALE signal output hold time (address standard)
(note 4)
ns
8
ns
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD)
=
109
f(BCLK) × 2
- 10 [ns]
th(WR-AD) =
109
f(BCLK) × 2
- 10 [ns]
th(RD-CS)
=
109
f(BCLK) × 2
- 10 [ns]
th(WR-CS) =
109
f(BCLK) × 2
- 10 [ns]
th(WR-DB) =
109
f(BCLK) × 2
- 15 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) =
109 × m
f(BCLK) × 2
- 25 [ns] (if external bus cycle is aφ + bφ, m = (b × 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) =
109 × n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is aφ + bφ, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) =
109 × n
f(BCLK) × 2
- 10 [ns] (if external bus cycle is aφ + bφ, n = a)
5. tc [ns] is added when recovery cycle is inserted.
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 62 of 67
M32C/8B Group
5. Electrical Characteristics
VCC1=VCC2=3.3V
tc
XIN input
tr
tf
tw(H)
tw(L)
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/
decrement select input)
In event counter mode
th(TIN-UP)
TAiIN input (count on falling edge)
tsu(UP-TIN)
TAiIN input (count on rising edge)
In event counter mode with two-phase pulse
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
TAiOUT input
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tw(ADH)
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
RXDi
tw(INL)
INTi input
tw(INH)
NMI input
2 CPU clock cycles
+ 300 ns or more
("L" width)
Figure 5.7
2 CPU clock cycles
+ 300 ns or more
VCC1 = VCC2 = 3.3 V Timing Diagram (1)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 63 of 67
th(C-D)
M32C/8B Group
5. Electrical Characteristics
VCC1=VCC2=3.3V
Memory Expansion Mode and Microprocessor Mode
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK)
th(BCLK-RDY)
BCLK
th(BCLK-HOLD)
tsu(HOLD-BCLK)
HOLD Input
HLDA Output
td(BCLK-HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2
td(BCLK-HLDA)
Hi-Z
Measurement Conditions
-VCC1 = VCC2 = 3.0 to 3.6 V
-Input high and low voltage: VIH = 2.4 V, VIL = 0.6 V
-Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V
Figure 5.8
VCC1 = VCC2 = 3.3 V Timing Diagram (2)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 64 of 67
M32C/8B Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space)
VCC1=VCC2=3.3V
Read Timing (1φ + 1φ Bus Cycle)
BCLK
th(BCLK-CS)
0ns.min
td(BCLK-CS)
18ns.max(1)
CSi
tcyc
th(RD-CS)
0ns.min
td(BCLK-AD)
18ns.max(1)
th(BCLK-AD)
0ns.min
ADi
BHE
th(RD-AD)
0ns.min
td(BCLK-RD)
18ns.max
RD
th(BCLK-RD)
-3ns.min
tac1(RD-DB)(2)
tac1(AD-DB)(2)
DBi
Hi-Z
tsu(DB-BCLK)
27ns.min(1)
th(RD-DB)
0ns.min
NOTES:
1. Values guaranteed only when the MCU is used stand-alone.
A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK).
2. Varies with operation frequency:
tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + bφ, m = (b x 2) + 1)
tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle aφ + bφ, n = a + b)
Write Timing (1φ + 1φ Bus Cycle)
BCLK
th(BCLK-CS)
0ns.min
td(BCLK-CS)
18ns.max(1)
CSi
tcyc
th(WR-CS)(3)
td(BCLK-AD)
18ns.max(1)
th(BCLK-AD)
0ns.min
ADi
BHE
td(BCLK-WR)
18ns.max
th(WR-AD)(3)
tw(WR)(3)
WR,WRL,WRH
th(BCLK-WR)
0ns.min
td(DB-WR)(3)
th(WR-DB)(3)
DBi
NOTES:
3. Varies with operation frequency:
td(DB-WR) = (tcyc x m - 20) ns.min
( if external bus cycle aφ + bφ, m = b)
th(WR-DB) = (tcyc / 2 - 15) ns.min
th(WR-AD) = (tcyc / 2 - 10) ns.min
th(WR-CS) = (tcyc / 2 - 10) ns.min
tw(WR) = (tcyc / 2 x n - 15) ns.min
( if external bus cycle aφ + bφ, n = (b x 2) - 1)
Figure 5.9
Measurement Conditions:
- VCC1 = VCC2 = 3.0 to 3.6 V
- Input high and low voltage: VIH = 1.5 V, VIL = 0.5 V
- Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V
tcyc=
VCC1 = VCC2 = 3.3 V Timing Diagram (3)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 65 of 67
109
f(BCLK)
M32C/8B Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(when accessing an external memory space with the multiplexed bus)
VCC1=VCC2=3.3V
Read Timing (2φ + 2φ Bus Cycle)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max
th(BCLK-CS)
0ns.min
tcyc
th(RD-CS)(1)
CSi
ADi /DBi
tsu(DB-BCLK) 27ns.min
th(ALE-AD)(1)
td(AD-ALE)(1)
Address
Data input
Address
tdz(RD-AD)
8ns.max
td(BCLK-AD)
18ns.max
th(RD-DB) 0ns.min
th(BCLK-AD)
0ns.min
tac2(RD-DB)(1)
ADi
BHE
th(RD-AD)(1)
tac2(AD-DB)(1)
td(BCLK-RD)
18ns.max
RD
th(BCLK-RD)
-3ns.min
NOTES:
1. Varies with operation frequency:
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a φ + bφ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a φ + bφ, n = a)
th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min
tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a φ + bφ, m = (b x 2) - 1)
tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a φ + bφ, p = {(a + b - 1) x 2} + 1)
Write Timing (2φ + 2φ Bus Cycle)
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
18ns.max
th(BCLK-CS)
0ns.min
tcyc
th(WR-CS)(2)
CSi
td(AD-ALE)(2)
th(ALE-AD)(2)
Address
ADi /DBi
Data output
td(DB-WR)(2)
td(BCLK-AD)
18ns.max
Address
th(WR-DB)(2)
th(BCLK-AD)
0ns.min
ADi
BHE
td(BCLK-WR)
18ns.max
WR,WRL,WRH
th(BCLK-WR)
0ns.min
th(WR-AD)(2)
NOTES:
1. Varies with operation frequency:
td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a φ + bφ, n = a)
th(ALE-AD) = (tcyc / 2 x n - 10) ns.min (if external bus cycle a φ + bφ, n = a)
th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min
th(WR-DB) = (tcyc / 2 - 15) ns.min
td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a φ + bφ, m = (b x 2) - 1)
tcyc=
Figure 5.10
109
f(BCLK)
Measurement Conditions:
- VCC1 = VCC2 = 3.0 to 3.6 V
- Input high and low voltage VIH = 1.5 V, VIL = 0.5 V
- Output high and low voltage VOH = 1.5 V, VOL = 1.5 V
VCC1 = VCC2 = 3.3 V Timing Diagram (4)
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 66 of 67
M32C/8B Group
Appendix 1. Package Dimensions
Appendix 1.
Package Dimensions
JEITA Package Code
P-LQFP144-20x20-0.50
RENESAS Code
PLQP0144KA-A
Previous Code
144P6Q-A / FP-144L / FP-144LV
MASS[Typ.]
1.2g
HD
*1
D
108
73
109
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
72
bp
E
c
HE
c1
b1
*2
Reference
Symbol
Terminal cross section
Index mark
c
36
A
1
ZD
ZE
37
A2
144
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
A1
F
L
L1
*3
e
y
JEITA Package Code
P-LQFP100-14x14-0.50
RENESAS Code
PLQP0100KB-A
bp
e
x
y
ZD
ZE
L
L1
Detail F
x
Previous Code
100P6Q-A / FP-100U / FP-100UV
Dimension in Millimeters
Min Nom Max
19.9 20.0 20.1
19.9 20.0 20.1
1.4
21.8 22.0 22.2
21.8 22.0 22.2
1.7
0.05 0.1 0.15
0.17 0.22 0.27
0.20
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.10
1.25
1.25
0.35 0.5 0.65
1.0
MASS[Typ.]
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
HE
Reference Dimension in Millimeters
Symbol
c
c1
*2
E
b1
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
100
26
1
ZE
Terminal cross section
25
Index mark
ZD
y
e
*3
bp
A1
c
A
A2
F
L
x
L1
Detail F
REJ03B0242-0100 Rev.1.00 Nov 01, 2009
Page 67 of 67
e
x
y
ZD
ZE
L
L1
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
8°
0°
0.5
0.08
0.08
1.0
1.0
0.35 0.5 0.65
1.0
REVISION HISTORY
Rev.
Date
0.50
Oct 31, 2008
0.60
Jan 31, 2009
Description
Page
−
36
41
44
59
60
61
62
65
66
1.00
M32C/8B Group Datasheet
Nov 01, 2009
Summary
First Edition issued
Electrical Characteristics
• Table 5.5 Condition in the table title revised
• Table 5.11 Max value of “Detection voltage level accuracy” revised
• Table 5.24 RXDi input setup time for 5 V changed “30” to “80”
• Table 5.45 RXDi input setup time for 3.3 V changed “30” to “80”
• Table 5.47 Data input setup time changed to “27”, RDY input setup time
to “30”, HOLD input setup time to “40”
• Table 5.48 Equation for th(WR-DB) revised
• Table 5.49 Equation for th(WR-DB) revised
• Figure 5.9 Equation for th(WR-DB) revised
• Figure 5.10 Equation for th(WR-DB) revised
-
Throughtout the manual
• “Preliminary” deleted
6
Overview
• Table 1.4 Product List “(D): Under development” deleted
39, 55
44, 59
49, 63
51, 65
Electrical Characteristics
• Table 5.8, 5.31 “Stop mode” and “Stop mode Topr=85°C” revised
• Table 5.23, 5.44 “tw(ADH) ADTRG input high pulse width” added
• Figure 5.3, 5.7 “tw(ADH)” added
• Figure 5.5, 5.9 RD and DBi in Read timing revised
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Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: (1628) 585-100, Fax: (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: (21) 5877-1818, Fax: (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: 2265-6688, Fax: 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: (2) 2715-2888, Fax: (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: 6213-0200, Fax: 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: (2) 796-3115, Fax: (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: 7955-9390, Fax: 7955-9510
© 2009. Renesas Technology Corp., All rights reserved. Printed in Japan.
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