M32C84T

REJ09B0036-0101 16/32 M32C/84 Group (M32C/84, M32C/84T) Hardware Manual RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES Before using this material, please visit our website to verify that this is the most current document available. Rev. 1.01 Revision Date: Jul. 07, 2005 www.renesas.com Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 2. 3. 4. 5. 6. 7. 8. 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Any diversion or reexport contrary to the export control laws and regulations of Japan and/ or the country of destination is prohibited. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M32C/84 group (M32C/84, M32C/84T) microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below. XXX Register b7 b6 b5 b4 b3 b2 b1 b0 *1 00 Symbol XXX Bit Symbol XXX0 XXX bit XXX1 Address XXX After Reset 0016 Bit Name b1 b0 Function 0 0: XXX 0 1: XXX 1 0: Do not set a value 1 1: XXX RW *2 RW RW (b2) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Reserved bit Set to "0" *3 WO (b4 - b3) XXX5 XXX bit XXX6 *4 Function varies depending on mode of operation RW RW XXX bit 0: XXX 1: XXX XXX7 RO *1 Blank:Set to "0" or "1" according to the application 0: Set to "0" 1: Set to "1" X: Nothing is assigned *2 RW: RO: WO: –: *3 • Reserved bit Reserved bit. Set to specified value. *4 • Nothing is assigned Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to "0" when writing to this bit. • Do not set a value The operation is not guaranteed when a value is set. • Function varies depending on mode of operation Bit function varies depending on peripheral function mode. Refer to respective register for each mode. Read and write Read only Write only Nothing is assigned Table of Contents Quick Reference by Address _____________________ B-1 1. Overview _____________________________________ 1 1.1 1.2 1.3 1.4 1.5 1.6 Applications ................................................................................................................ 1 Performance Overview .............................................................................................. 2 Block Diagram ............................................................................................................ 4 Product Information ................................................................................................... 5 Pin Assignments and Descriptions .......................................................................... 7 Pin Description ......................................................................................................... 15 2. Central Processing Unit (CPU) __________________ 19 2.1 General Registers .................................................................................................... 20 2.1.1 Data Registers (R0, R1, R2 and R3) ................................................................. 20 2.1.2 Address Registers (A0 and A1) ....................................................................... 20 2.1.3 Static Base Register (SB) ................................................................................. 20 2.1.4 Frame Base Register (FB) ................................................................................ 20 2.1.5 Program Counter (PC) ...................................................................................... 20 2.1.6 Interrupt Table Register (INTB) ........................................................................ 20 2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ............................... 20 2.1.8 Flag Register (FLG) ........................................................................................... 20 2.2 High-Speed Interrupt Registers .............................................................................. 21 2.3 DMAC-Associated Registers ................................................................................... 21 3. Memory _____________________________________ 22 4. Special Function Registers (SFR)________________ 23 5. Reset _______________________________________ 43 5.1 Hardware Reset 1 ..................................................................................................... 43 5.1.1 Reset on a Stable Supply Voltage .................................................................... 43 5.1.2 Power-on Reset .................................................................................................. 43 5.2 Low Voltage Detection Reset (Hardware Reset 2)................................................. 45 5.3 Software Reset ......................................................................................................... 46 5.4 Watchdog Timer Reset ............................................................................................ 46 5.5 Internal Space ........................................................................................................... 47 6. Voltage Detection Circuit _______________________ 48 6.1 Low Voltage Detection Interrupt ............................................................................. 52 6.1.1 Limitations on Exiting Stop/Wait Mode........................................................... 54 6.2 Cold Start-up / Warm Start-up Determine Function .............................................. 54 A-1 7. Processor Mode ______________________________ 55 7.1 Types of Processor Mode ........................................................................................ 55 7.2 Setting of Processor Mode ...................................................................................... 56 8. Bus_________________________________________ 60 8.1 Bus Settings ............................................................................................................. 60 8.1.1 Selecting External Address Bus ...................................................................... 61 8.1.2 Selecting External Data Bus ............................................................................ 61 8.1.3 Selecting Separate/Multiplexed Bus ............................................................... 61 8.2 Bus Control ............................................................................................................... 63 8.2.1 Address Bus and Data Bus .............................................................................. 63 8.2.2 Chip-Select Signal ............................................................................................ 63 8.2.3 Read and Write Signals .................................................................................... 65 8.2.4 Bus Timing ........................................................................................................ 66 8.2.5 ALE Signal ......................................................................................................... 74 _______ 8.2.6 RDY Signal ......................................................................................................... 74 _________ 8.2.7 HOLD Signal ...................................................................................................... 76 8.2.8 External Bus Status when Accessing Internal Space ................................... 76 8.2.9 BCLK Output ..................................................................................................... 76 8.3 Page Mode Control Function .................................................................................. 77 9. Clock Generation Circuit _______________________ 81 9.1 Types of the Clock Generation Circuit ................................................................... 81 9.1.1 Main Clock ......................................................................................................... 90 9.1.2 Sub Clock .......................................................................................................... 91 9.1.3 On-Chip Oscillator Clock ................................................................................. 92 9.1.4 PLL Clock .......................................................................................................... 94 9.2 CPU Clock and BCLK .............................................................................................. 95 9.3 Peripheral Function Clock ....................................................................................... 95 9.3.1 f1, f8, f32 and f2n ......................................................................................................................... 95 9.3.2 fAD .................................................................................................................................................... 95 9.3.3 fC32 .................................................................................................................................................. 96 9.3.4 fCAN .................................................................................................................................................. 96 9.4 Clock Output Function ............................................................................................ 96 9.5 Power Consumption Control .................................................................................. 97 9.5.1 Normal Operating Mode ................................................................................... 97 9.5.2 Wait Mode .......................................................................................................... 98 9.5.3 Stop Mode ........................................................................................................ 100 9.6 System Clock Protect Function ............................................................................ 105 A-2 10. Protection _________________________________ 106 11. Interrupts __________________________________ 107 11.1 Types of Interrupts ............................................................................................... 107 11.2 Software Interrupts .............................................................................................. 108 11.2.1 Undefined Instruction Interrupt ................................................................... 108 11.2.2 Overflow Interrupt ......................................................................................... 108 11.2.3 BRK Interrupt ................................................................................................. 108 11.2.4 BRK2 Interrupt ............................................................................................... 108 11.2.5 INT Instruction Interrupt ............................................................................... 108 11.3 Hardware Interrupts ............................................................................................. 109 11.3.1 Special Interrupts .......................................................................................... 109 11.3.2 Peripheral Function Interrupt ....................................................................... 109 11.4 High-Speed Interrupt ............................................................................................ 110 11.5 Interrupts and Interrupt Vectors ......................................................................... 110 11.5.1 Fixed Vector Tables ....................................................................................... 111 11.5.2 Relocatable Vector Tables ............................................................................ 111 11.6 Interrupt Request Acknowledgement ................................................................. 114 11.6.1 I Flag and IPL ................................................................................................. 114 11.6.2 Interrupt Control Register and RLVL Register ........................................... 114 11.6.3 Interrupt Sequence ....................................................................................... 118 11.6.4 Interrupt Response Time .............................................................................. 119 11.6.5 IPL Change when Interrupt Request is Acknowledged ............................. 120 11.6.6 Saving a Register .......................................................................................... 121 11.6.7 Restoration from Interrupt Routine ............................................................. 121 11.6.8 Interrupt Priority ............................................................................................ 122 11.6.9 Interrupt Priority Level Select Circuit .......................................................... 122 ______ 11.7 INT Interrupt .......................................................................................................... 124 ______ 11.8 NMI Interrupt(1) ..................................................................................................... 125 11.9 Key Input Interrupt ............................................................................................... 125 11.10 Address Match Interrupt .................................................................................... 126 11.11 Intelligent I/O Interrupt and CAN Interrupt ....................................................... 127 12. Watchdog Timer ____________________________ 131 12.1 Count Source Protection Mode .......................................................................... 134 A-3 13. DMAC_____________________________________ 135 13.1 Transfer Cycle ...................................................................................................... 142 13.1.1 Effect of Source and Destination Addresses ............................................. 142 13.1.2 Effect of the DS Register .............................................................................. 142 13.1.3 Effect of Software Wait State ....................................................................... 142 ________ 13.1.4 Effect of RDY Signal ..................................................................................... 142 13.2 DMAC Transfer Cycle ........................................................................................... 144 13.3 Channel Priority and DMA Transfer Timing ....................................................... 144 14. DMAC II ___________________________________ 146 14.1 DMAC II Settings .................................................................................................. 146 14.1.1 RLVL Register................................................................................................ 146 14.1.2 DMAC II Index ................................................................................................ 148 14.1.3 Interrupt Control Register for the Peripheral Function ............................. 150 14.1.4 Relocatable Vector Table for the Peripheral Function ............................... 150 14.1.5 IRLT Bit in the IIOiIE Register (i=0 to 4, 8 to 11) ......................................... 150 14.2 DMAC II Performance .......................................................................................... 150 14.3 Transfer Data ........................................................................................................ 150 14.3.1 Memory-to-memory Transfer ....................................................................... 150 14.3.2 Immediate Data Transfer .............................................................................. 151 14.3.3 Calculation Transfer ..................................................................................... 151 14.4 Transfer Modes ..................................................................................................... 151 14.4.1 Single Transfer .............................................................................................. 151 14.4.2 Burst Transfer ............................................................................................... 151 14.5 Multiple Transfer .................................................................................................. 151 14.6 Chained Transfer .................................................................................................. 152 14.7 End-of-Transfer Interrupt ..................................................................................... 152 14.8 Execution Time ..................................................................................................... 153 15. Timer _____________________________________ 154 15.1 Timer A .................................................................................................................. 156 15.1.1 Timer Mode .................................................................................................... 162 15.1.2 Event Counter Mode ..................................................................................... 164 15.1.3 One-Shot Timer Mode ................................................................................... 168 15.1.4 Pulse Width Modulation Mode ..................................................................... 170 15.2 Timer B .................................................................................................................. 173 15.2.1 Timer Mode .................................................................................................... 176 15.2.2 Event Counter Mode ..................................................................................... 177 15.2.3 Pulse Period/Pulse Width Measurement Mode .......................................... 179 A-4 16. Three-Phase Motor Control Timer Functions ____ 182 17. Serial I/O __________________________________ 193 17.1 Clock Synchronous Serial I/O Mode .................................................................. 203 17.1.1 Selecting CLK Polarity Selecting ................................................................ 207 17.1.2 Selecting LSB First or MSB First ................................................................. 207 17.1.3 Continuous Receive Mode ........................................................................... 208 17.1.4 Serial Data Logic Inverse ............................................................................. 208 17.2 Clock Asynchronous Serial I/O (UART) Mode ................................................... 209 17.2.1 Transfer Speed .............................................................................................. 213 17.2.2 Selecting LSB First or MSB First ................................................................. 214 17.2.3 Serial Data Logic Inverse ............................................................................. 214 17.2.4 TxD and RxD I/O Polarity Inverse ................................................................ 215 17.3 Special Mode 1 (I2C Mode) .................................................................................. 216 17.3.1 Detecting Start Condition and Stop Condition .......................................... 222 17.3.2 Start Condition or Stop Condition Output .................................................. 222 17.3.3 Arbitration ...................................................................................................... 224 17.3.4 Transfer Clock ............................................................................................... 224 17.3.5 SDA Output .................................................................................................... 224 17.3.6 SDA Input ....................................................................................................... 225 17.3.7 ACK, NACK .................................................................................................... 225 17.3.8 Transmit and Receive Reset ........................................................................ 225 17.4 Special Mode 2 ..................................................................................................... 226 ______ 17.4.1 SSi Input Pin Function (i=0 to 4) .................................................................. 229 17.4.2 Clock Phase Setting Function ..................................................................... 230 17.5 Special Mode 3 (GCI Mode) ................................................................................. 232 17.6 Special Mode 4 (IE Mode) .................................................................................... 236 17.7 Special Mode 5 (SIM Mode) ................................................................................. 240 17.7.1 Parity Error Signal ........................................................................................ 244 17.7.2 Format ............................................................................................................ 245 18. A/D Converter ______________________________ 246 18.1 Mode Description ................................................................................................. 254 18.1.1 One-shot Mode .............................................................................................. 254 18.1.2 Repeat Mode .................................................................................................. 255 18.1.3 Single Sweep Mode ...................................................................................... 256 18.1.4 Repeat Sweep Mode 0 .................................................................................. 257 18.1.5 Repeat Sweep Mode 1 .................................................................................. 258 18.1.6 Multi-Port Single Sweep Mode ..................................................................... 259 18.1.7 Multi-Port Repeat Sweep Mode 0 ................................................................ 260 A-5 18.2 Functions .............................................................................................................. 261 18.2.1 Resolution Select Function .......................................................................... 261 18.2.2 Sample and Hold Function ........................................................................... 261 18.2.3 Trigger Select Function ................................................................................ 261 18.2.4 DMAC Operating Mode ................................................................................. 261 18.2.5 Extended Analog Input Pins ........................................................................ 262 18.2.6 External Operating Amplifier (Op-Amp) Connection Mode....................... 262 18.2.7 Power Consumption Reducing Function ................................................... 263 18.2.8 Output Impedance of Sensor Equivalent Circuit under A/D Conversion ..... 263 19. 20. 21. 22. D/A Converter ______________________________ CRC Calculation ____________________________ X/Y Conversion _____________________________ Intelligent I/O_______________________________ 265 268 270 273 22.1 Base Timer ............................................................................................................ 282 22.2 Time Measurement Function............................................................................... 287 22.3 Waveform Generating Function .......................................................................... 292 22.3.1 Single-Phase Waveform Output Mode ........................................................ 293 22.3.2 Phase-Delayed Waveform Output Mode ..................................................... 295 22.3.3 Set/Reset Waveform Output (SR Waveform Output) Mode ....................... 297 22.4 Communication Unit 0 and 1 Communication Function .................................. 300 22.4.1 Clock Synchronous Serial I/O Mode (Communication Units 0 and 1) ..... 310 22.4.2 Clock Asynchronous Serial I/O (UART) Mode (Communication Unit 1) ....... 314 22.4.3 HDLC Data Processing Mode (Communication units 0 and 1) ................. 317 23. CAN Module _______________________________ 320 23.1 CAN-Associated Registers ................................................................................. 324 23.1.1 CAN0 Control Register 0 (C0CTLR0 Register) ........................................... 324 23.1.2 CAN0 Control Register 1 (C0CTLR1 Register) ........................................... 327 23.1.3 CAN0 Sleep Control Register (C0SLPR Register) ..................................... 328 23.1.4 CAN0 Status Register (C0STR Register) .................................................... 329 23.1.5 CAN0 Extended ID Register (C0IDR Register) ........................................... 332 23.1.6 CAN0 Configuration Register (C0CONR Register) .................................... 333 23.1.7 CAN0 Baud Rate Prescaler (C0BRP Register) ........................................... 335 23.1.8 CAN0 Time Stamp Register (C0TSR Register) ........................................... 336 23.1.9 CAN0 Transmit Error Count Register (C0TEC Register) ........................... 337 23.1.10 CAN0 Receive Error Count Register (C0REC Register) .......................... 337 23.1.11 CAN0 Slot Interrupt Status Register (C0SISTR Register) ....................... 338 23.1.12 CAN0 Slot Interrupt Mask Register (C0SIMKR Register) ........................ 340 A-6 23.1.13 CAN0 Error Interrupt Mask Register (C0EIMKR Register) ...................... 341 23.1.14 CAN0 Error Interrupt Status Register (C0EISTR Register) ..................... 342 23.1.15 CAN0 Error Factor Register (C0EFR Register) ........................................ 343 23.1.16 CAN0 Mode Register (C0MDR Register) ................................................... 344 23.1.17 CAN0 Single-Shot Control Register (C0SSCTLR Register) .................... 346 23.1.18 CAN0 Single-Shot Status Register (C0SSSTR Register) ........................ 347 23.1.19 CAN0 Global Mask Register, CAN0 Local Mask Register A and CAN0 Local Mask Register B (C0GMRk, C0LMARk and C0LMBRk Registers) (k=0 to 4) ....................... 348 23.1.20 CAN0 Message Slot j Control Register (C0MCTLj Register) (j=0 to 15) ..... 355 23.1.21 CAN0 Slot Buffer Select Register (C0SBS Register) ............................... 359 23.1.22 CAN0 Message Slot Buffer j (j=0,1) ........................................................... 360 23.1.23 CAN0 Acceptance Filter Support Register (C0AFS Register)................. 364 23.2 CAN Clock ............................................................................................................. 365 23.2.1 Main Clock Direct Mode ............................................................................... 365 23.3 Timing with CAN-Associated Registers ............................................................. 366 23.3.1 CAN Module Reset Timing ........................................................................... 366 23.3.2 CAN Transmit Timing ................................................................................... 366 23.3.3 CAN Receive Timing ..................................................................................... 367 23.3.4 CAN Bus Error Timing .................................................................................. 368 23.4 CAN Interrupts ...................................................................................................... 368 23.4.1 CAN0 Wake-Up Interrupt .............................................................................. 368 23.4.2 CAN0j Interrupts ........................................................................................... 368 24. Programmable I/O Ports _____________________ 372 24.1 Port Pi Direction Register (PDi Register, i=0 to 15)........................................... 372 24.2 Port Pi Register (Pi Register, i=0 to 15) .............................................................. 372 24.3 Function Select Register Aj (PSj Register) (j=0 to 3, 5, 8, 9) ............................ 372 24.4 Function Select Register B0 to B3 (PSL0 to PSL3 Registers) ......................... 372 24.5 Function Select Register C (PSC, PSC2, PSC3 Registers) .............................. 373 24.6 Function Select Register D (PSD1 Register) ..................................................... 373 24.7 Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers) .............................. 373 24.8 Port Control Register (PCR Register) ................................................................ 373 24.9 Input Function Select Register (IPS and IPSA Registers) ................................ 373 24.10 Analog Input and Other Peripheral Function Input ......................................... 373 25. Flash Memory Version _______________________ 396 25.1 Memory Map ......................................................................................................... 397 25.1.1 Boot Mode ..................................................................................................... 398 A-7 25.2 Functions to Prevent the Flash Memory from Rewriting ................................. 398 25.2.1 ROM Code Protect Function ........................................................................ 398 25.2.2 ID Code Verify Function ............................................................................... 398 25.3 CPU Rewrite Mode ............................................................................................... 400 25.3.1 EW Mode 0 ..................................................................................................... 400 25.3.2 EW Mode 1 ..................................................................................................... 400 25.3.3 Flash Memory Control Register (FMR0 Register and FMR1 Register) .... 401 25.3.4 Precautions in CPU Rewrite Mode .............................................................. 407 25.3.5 Software Commands .................................................................................... 409 25.3.6 Data Protect Function ................................................................................... 415 25.3.7 Status Register (SRD Register) ................................................................... 415 25.3.8 Full Status Check .......................................................................................... 417 25.4 Standard Serial I/O Mode ..................................................................................... 419 25.4.1 ID Code Verify Function ............................................................................... 419 25.4.2 Circuit Application in Standard Serial I/O Mode ........................................ 424 25.5 Parallel I/O Mode .................................................................................................. 426 25.5.1 Boot ROM Area.............................................................................................. 426 25.5.2 ROM Code Protect Function ........................................................................ 426 26. Electrical Characteristics ____________________ 427 26.1 Electrical Characteristics (M32C/84) ................................................................... 427 26.2 Electrical Characteristics (M32C/84T) ................................................................. 456 27. Precautions ________________________________ 468 27.1 Restrictions to Use M32C/84T (High-Reliability Version) ................................. 468 27.2 Reset ..................................................................................................................... 469 27.3 Bus ........................................................................................................................ 470 __________ 27.3.1 HOLD Signal .................................................................................................. 470 27.3.2 External Bus .................................................................................................. 470 27.4 SFR ........................................................................................................................ 471 27.4.1 100-Pin Package ............................................................................................ 471 27.4.2 Register Settings .......................................................................................... 471 27.5 Clock Generation Circuit ..................................................................................... 472 27.5.1 CPU Clock...................................................................................................... 472 27.5.2 Sub Clock ...................................................................................................... 472 27.5.3 PLL Frequency Synthesizer ......................................................................... 473 27.5.4 External Clock ............................................................................................... 473 27.5.5 Clock Divide Ratio ........................................................................................ 473 27.5.6 Power Consumption Control ....................................................................... 473 27.6 Protection ............................................................................................................. 476 A-8 27.7 Interrupts .............................................................................................................. 477 27.7.1 ISP Setting ..................................................................................................... 477 _______ 27.7.2 NMI Interrupt .................................................................................................. 477 ______ 27.7.3 INT Interrupt .................................................................................................. 477 27.7.4 Watchdog Timer Interrupt ............................................................................ 478 27.7.5 Changing Interrupt Control Register .......................................................... 478 27.7.6 Changing IIOiIR Register (i = 0 to 4, 8 to 11) .............................................. 478 27.7.7 Changing RLVL Register .............................................................................. 478 27.8 DMAC .................................................................................................................... 479 27.9 Timer...................................................................................................................... 480 27.9.1 Timers A and B .............................................................................................. 480 27.9.2 Timer A ........................................................................................................... 480 27.9.3 Timer B ........................................................................................................... 482 27.10 Serial I/O .............................................................................................................. 483 27.10.1 Clock Synchronous Serial I/O Mode ......................................................... 483 27.10.2 UART Mode .................................................................................................. 484 27.10.3 Special Mode 1 (I2C Mode) ......................................................................... 484 27.11 A/D Converter ..................................................................................................... 485 27.12 Intelligent I/O ...................................................................................................... 487 27.12.1 Register Setting .......................................................................................... 487 27.13 Programmable I/O Ports .................................................................................... 488 27.14 Flash Memory Version ....................................................................................... 489 27.14.1 Differences Between Flash Memory Version and Masked ROM Version ...... 489 27.14.2 Boot Mode .................................................................................................... 489 27.15 Noise ................................................................................................................... 490 Package Dimensions ___________________________ 491 Register Index _________________________________ 493 A-9 Quick Reference by Address Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 Register Page Address 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 Register Page Processor Mode Register 0 (PM0) Processor Mode Register 1 (PM1) System Clock Control Register 0 (CM0) System Clock Control Register 1 (CM1) Address Match Interrupt Enable Register (AIER) Protect Register (PRCR) External Data Bus Width Control Register (DS) Main Clock Division Register (MCD) Oscillation Stop Detection Register (CM2) Watchdog Timer Start Register (WDTS) Watchdog Timer Control Register (WDC) Address Match Interrupt Register 0 (RMAD0) Processor Mode Register 2 (PM2) Address Match Interrupt Register 1 (RMAD1) Voltage Detection Register 2 (VCR2) Address Match Interrupt Register 2 (RMAD2) Voltage Detection Register 1 (VCR1) Address Match Interrupt Register 3 (RMAD3) 57 58 83 84 126 106 60 85 86 132 Address Match Interrupt Register 6 (RMAD6) 126 Address Match Interrupt Register 7 (RMAD7) 126 126 89 126 50 126 50 126 External Space Wait Control Register 0 (EWCR0) External Space Wait Control Register 1 (EWCR1) External Space Wait Control Register 2 (EWCR2) External Space Wait Control Register 3 (EWCR3) Page Mode Wait Control Register 0 (PWCR0) Page Mode Wait Control Register 1 (PWCR1) 66 78 79 Flash Memory Control Register 1 (FMR1) Flash Memory Control Register 0 (FMR0) 402 401 PLL Control Register 0 (PLC0) PLL Control Register 1 (PLC1) Address Match Interrupt Register 4 (RMAD4) 88 88 126 Address Match Interrupt Register 5 (RMAD5) Low Voltage Detection Interrupt Register (D4INT) 126 51 Blank spaces are reserved. No access is allowed. B-1 Quick Reference by Address Address 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 Register Page Address Register Page 009016 UART0 Transmit /NACK Interrupt Control Register (S0TIC) UART1 Bus Conflict Detect Interrupt Control Register (BCN1IC)/ 009116 UART4 Bus Conflict Detect Interrupt Control Register (BCN4IC) 009216 UART1 Transmit/NACK Interrupt Control Register (S1TIC) 009316 Key Input Interrupt Control Register (KUPIC) 009416 Timer B0 Interrupt Control Register (TB0IC) 115 Intelligent I/O Interrupt Control Register 1 (IIO1IC)/ 009516 CAN Interrupt 4 Control Register (CAN4IC) 009616 Timer B2 Interrupt Control Register (TB2IC) 009716 Intelligent I/O Interrupt Control Register 3 (IIO3IC) 009816 Timer B4 Interrupt Control Register (TB4IC) 009916 CAN Interrupt 5 Control Register (CAN5IC) 009A16 INT4 Interrupt Control Register (INT4IC) 116 009B16 009C16 INT2 Interrupt Control Register (INT2IC) 116 Intelligent I/O Interrupt Control Register 9 (IIO9IC)/ 009D16 115 CAN Interrupt 0 Control Register (CAN0IC) 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16 INT0 Interrupt Control Register (INT0IC) Exit Priority Control Register (RLVL) Interrupt Request Register 0 (IIO0IR) Interrupt Request Register 1 (IIO1IR) Interrupt Request Register 2 (IIO2IR) Interrupt Request Register 3 (IIO3IR) Interrupt Request Register 4 (IIO4IR) Interrupt Request Register 5 (IIO5IR) 116 117 DMA0 Interrupt Control Register (DM0IC) Timer B5 Interrupt Control Register (TB5IC) DMA2 Interrupt Control Register (DM2IC) UART2 Receive /ACK Interrupt Control Register (S2RIC) Timer A0 Interrupt Control Register (TA0IC) UART3 Receive /ACK Interrupt Control Register (S3RIC) Timer A2 Interrupt Control Register (TA2IC) UART4 Receive /ACK Interrupt Control Register (S4RIC) Timer A4 Interrupt Control Register (TA4IC) UART0 Bus Conflict Detect Interrupt Control Register (BCN0IC)/ UART3 Bus Conflict Detect Interrupt Control Register (BCN3IC) UART0 Receive/ACK Interrupt Control Register (S0RIC) A/D0 Conversion Interrupt Control Register (AD0IC) UART1 Receive/ACK Interrupt Control Register (S1RIC) Intelligent I/O Interrupt Control Register 0 (IIO0IC)/ CAN Interrupt 3 Control Register (CAN3IC) Timer B1 Interrupt Control Register (TB1IC) Intelligent I/O Interrupt Control Register 2 (IIO2IC) Timer B3 Interrupt Control Register (TB3IC) Intelligent I/O Interrupt Control Register 4 (IIO4IC) INT5 Interrupt Control Register (INT5IC) 115 129 007616 007716 007816 007916 007A16 007B16 007C16 INT3 Interrupt Control Register (INT3IC) 007D16 Intelligent I/O Interrupt Control Register 8 (IIO8IC) 007E16 INT1 Interrupt Control Register (INT1IC) Intelligent I/O Interrupt Control Register 10 (IIO10IC)/ 007F16 CAN Interrupt 1 Control Register (CAN1IC) 008016 008116 CAN Interrupt 2 Control Register (CAN2IC) 008216 008316 008416 008516 008616 008716 008816 DMA1 Interrupt Control Register (DM1IC) 008916 UART2 Transmit /NACK Interrupt Control Register (S2TIC) 008A16 DMA3 Interrupt Control Register (DM3IC) 008B16 UART3 Transmit /NACK Interrupt Control Register (S3TIC) 008C16 Timer A1 Interrupt Control Register (TA1IC) 008D16 UART4 Transmit /NACK Interrupt Control Register (S4TIC) 008E16 Timer A3 Interrupt Control Register (TA3IC) 008F16 UART2 Bus Conflict Detect Interrupt Control Register (BCN2IC) 116 116 115 116 115 Interrupt Request Register 8 (IIO8IR) Interrupt Request Register 9 (IIO9IR) Interrupt Request Register 10 (IIO10IR) Interrupt Request Register 11 (IIO11IR) 129 115 Interrupt Enable Register 0 (IIO0IE) Interrupt Enable Register 1 (IIO1IE) Interrupt Enable Register 2 (IIO2IE) Interrupt Enable Register 3 (IIO3IE) Interrupt Enable Register 4 (IIO4IE) Interrupt Enable Register 5 (IIO5IE) 130 Interrupt Enable Register 8 (IIO8IE) Interrupt Enable Register 9 (IIO9IE) Interrupt Enable Register 10 (IIO10IE) Interrupt Enable Register 11 (IIO11IE) 130 115 Blank spaces are reserved. No access is allowed. B-2 Quick Reference by Address Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 Register Page Address 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A16 011B16 011C16 011D16 011E16 011F16 Register Data Compare Register 00 (G0CMP0) Data Compare Register 01 (G0CMP1) Data Compare Register 02 (G0CMP2) Data Compare Register 03 (G0CMP3) Data Mask Register 00 (G0MSK0) Data Mask Register 01 (G0MSK1) Communication Clock Select Register (CCS) Page 308 309 Receive CRC Code Register 0 (G0RCRC) 308 Tramsmit CRC Code Register 0 (G0TCRC) SI/O Extended Mode Register 0 (G0EMR) SI/O Extended Receive Control Register 0 (G0ERC) SI/O Special Communication Interrupt Detect Register 0 (G0IRF) SI/O Extended Transmit Control Register 0 (G0ETC) Time Measurement Register 10 (G1TM0)/ Waveform Generating Register 10 (G1PO0) Time Measurement Register 11 (G1TM1)/ Waveform Generating Register 11 (G1PO1) Time Measurement Register 12 (G1TM2)/ Waveform Generating Register 12 (G1PO2) Time Measurement Register 13 (G1TM3)/ Waveform Generating Register 13 (G1PO3) Time Measurement Register 14 (G1TM4)/ Waveform Generating Register 14 (G1PO4) Time Measurement Register 15 (G1TM5)/ Waveform Generating Register 16 (G1PO5) Time Measurement Register 16 (G1TM6)/ Waveform Generating Register 16 (G1PO6) Time Measurement Register 17 (G1TM7)/ Waveform Generating Register 17 (G1PO7) Waveform Generating Control Register 10 (G1POCR0) Waveform Generating Control Register 11 (G1POCR1) Waveform Generating Control Register 12 (G1POCR2) Waveform Generating Control Register 13 (G1POCR3) Waveform Generating Control Register 14 (G1POCR4) Waveform Generating Control Register 15 (G1POCR5) Waveform Generating Control Register 16 (G1POCR6) Waveform Generating Control Register 17 (G1POCR7) Time Measurement Control Register 10 (G1TMCR0) Time Measurement Control Register 11 (G1TMCR1) Time Measurement Control Register 12 (G1TMCR2) Time Measurement Control Register 13 (G1TMCR3) Time Measurement Control Register 14 (G1TMCR4) Time Measurement Control Register 15 (G1TMCR5) Time Measurement Control Register 16 (G1TMCR6) Time Measurement Control Register 17 (G1TMCR7) 303 305 306 304 279/ 280 279 SI/O Receive Buffer Register0 (G0RB) Transmit Buffer/Receive Data Register 0 (G0TB/G0DR) Receive Input Register 0 (G0RI) SI/O Communication Mode Register 0 (G0MR) Transmit Output Register 0 (G0TO) SI/O Communication Control Register 0 (G0CR) 301 307 300 302 300 301 278 Blank spaces are reserved. No access is allowed. B-3 Quick Reference by Address Address 012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 012A16 012B16 012C16 012D16 012E16 012F16 013016 013116 013216 013316 013416 013516 013616 013716 013816 013916 013A16 013B16 013C16 013D16 013E16 013F16 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A16 014B16 014C16 014D16 014E16 014F16 Register Base Timer Register1 (G1BT) Base Timer Control Register 10 (G1BCR0) Base Timer Control Register 11 (G1BCR1) Time Measurement Prescaler Register 16 (G1TPR6) Time Measurement Prescaler Register 17 (G1TPR7) Function Enable Register 1 (G1FE) Function Select Register 1 (G1FS) SI/O Receive Buffer Register 1 (G1RB) Transmit Buffer/Receive Data Register 1 (G1TB/G1DR) Receive Input Register 1 (G1RI) SI/O Communication Mode Register 1 (G1MR) Transmit Output Register 1 (G1TO) SI/O Communication Control Register 1 (G1CR) Data Compare Register 10 (G1CMP0) Data Compare Register 11 (G1CMP1) Data Compare Register 12 (G1CMP2) Data Compare Register 13 (G1CMP3) Data Mask Register 10 (G1MSK0) Data Mask Register 11 (G1MSK1) Page 276 276 277 278 281 280 301 307 300 302 300 301 Address Register 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A16 015B16 015C16 015D16 015E16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A16 016B16 016C16 016D16 016E16 016F16 017016 017116 017216 017316 017416 017516 017616 017716 017816 Input Function Select Register (IPS) 017916 Input Function Select Register A (IPSA) 017A16 017B16 017C16 017D16 to 01DF16 Page 308 Receive CRC Code Register1 (G1RCRC) 308 Transmit CRC Code Register1 (G1TCRC) SI/O Extended Mode Register 1 (G1EMR) SI/O Extended Receive Control Register 1 (G1ERC) SI/O Special Communication Interrupt Detect Register 1 (G1IRF) SI/O Extended Transmit Control Register 1 (G1ETC) 303 305 307 304 389 390 Blank spaces are reserved. No access is allowed. B-4 Quick Reference by Address Address 01E016 01E116 01E216 01E316 01E416 01E516 01E616 01E716 01E816 01E916 01EA16 01EB16 01EC16 01ED16 01EE16 01EF16 01F016 01F116 01F216 01F316 01F416 01F516 01F616 01F716 01F816 01F916 01FA16 01FB16 01FC16 01FD16 01FE16 01FF16 020016 020116 020216 020316 020416 020516 020616 020716 020816 020916 020A16 020B16 020C16 020D16 020E16 020F16 Register Page CAN0 Message Slot Buffer 0 Standard ID0 (C0SLOT0_0) 360 CAN0 Message Slot Buffer 0 Standard ID1 (C0SLOT0_1) CAN0 Message Slot Buffer 0 Extended ID0 (C0SLOT0_2) 361 CAN0 Message Slot Buffer 0 Extended ID1 (C0SLOT0_3) CAN0 Message Slot Buffer 0 Extended ID2 (C0SLOT0_4) 362 CAN0 Message Slot Buffer 0 Data Length Code (C0SLOT0_5) CAN0 Message Slot Buffer 0 Data 0 (C0SLOT0_6) CAN0 Message Slot Buffer 0 Data 1 (C0SLOT0_7) CAN0 Message Slot Buffer 0 Data 2 (C0SLOT0_8) CAN0 Message Slot Buffer 0 Data 3 (C0SLOT0_9) CAN0 Message Slot Buffer 0 Data 4 (C0SLOT0_10) 363 CAN0 Message Slot Buffer 0 Data 5 (C0SLOT0_11) CAN0 Message Slot Buffer 0 Data 6 (C0SLOT0_12) CAN0 Message Slot Buffer 0 Data 7 (C0SLOT0_13) CAN0 Message Slot Buffer 0 Time Stamp High-Order (C0SLOT0_14) CAN0 Message Slot Buffer 0 Time Stamp Low-Order (C0SLOT0_15) CAN0 Message Slot Buffer 1 Standard ID0 (C0SLOT1_0) 360 CAN0 Message Slot Buffer 1 Standard ID1 (C0SLOT1_1) CAN0 Message Slot Buffer 1 Extended ID0 (C0SLOT1_2) 361 CAN0 Message Slot Buffer 1 Extended ID1 (C0SLOT1_3) CAN0 Message Slot Buffer 1 Extended ID2 (C0SLOT1_4) 362 CAN0 Message Slot Buffer 1 Data Length Code (C0SLOT1_5) CAN0 Message Slot Buffer 1 Data 0 (C0SLOT1_6) CAN0 Message Slot Buffer 1 Data 1 (C0SLOT1_7) CAN0 Message Slot Buffer 1 Data 2 (C0SLOT1_8) CAN0 Message Slot Buffer 1 Data 3 (C0SLOT1_9) CAN0 Message Slot Buffer 1 Data 4 (C0SLOT1_10) 363 CAN0 Message Slot Buffer 1 Data 5 (C0SLOT1_11) CAN0 Message Slot Buffer 1 Data 6 (C0SLOT1_12) CAN0 Message Slot Buffer 1 Data 7 (C0SLOT1_13) CAN0 Message Slot Buffer 1 Time Stamp High-Order (C0SLOT1_14) CAN0 Message Slot Buffer 1 Time Stamp Low-Order (C0SLOT1_15) CAN0 Control Register0 (C0CTLR0) CAN0 Status Register (C0STR) CAN0 Extended ID Register (C0IDR) CAN0 Configuration Register (C0CONR) CAN0 Time Stamp Register (C0TSR) CAN0 Transmit Error Count Register (C0TEC) CAN0 Receive Error Count Register (C0REC) CAN0 Slot Interrupt Status Register (C0SISTR) 324 329 332 333 336 337 338 Address 021016 021116 021216 021316 021416 021516 021616 021716 021816 021916 021A16 021B16 021C16 021D16 021E16 021F16 022016 022116 022216 022316 022416 022516 022616 022716 022816 022916 022A16 022B16 022C16 022D16 022E16 022F16 023016 023116 023216 023316 023416 023516 023616 023716 023816 Register CAN0 Slot Interrupt Mask Register (C0SIMKR) Page 340 CAN0 Error Interrupt Mask Register (C0EIMKR) CAN0 Error Interrupt Status Register (C0EISTR) CAN0 Error Cause Register (C0EFR) CAN0 Baud Rate Prescaler (C0BPR) CAN0 Mode Register (C0MDR) 341 342 343 335 344 CAN0 Single Shot Control Register (C0SSCTLR) 346 CAN0 Single Shot Status Register (C0SSSTR) 347 CAN0 Global Mask Register Standard ID0 (C0GMR0) CAN0 Global Mask Register Standard ID1 (C0GMR1) CAN0 Global Mask Register Extended ID0 (C0GMR2) CAN0 Global Mask Register Extended ID1 (C0GMR3) CAN0 Global Mask Register Extended ID2 (C0GMR4) 348 349 350 351 352 CAN0 Message Slot 0 Control Register (C0MCTL0)/ CAN0 Local Mask Register A Standard ID0 (C0LMAR0) CAN0 Message Slot 1 Control Register (C0MCTL1)/ CAN0Local Mask Register A Standard ID1 (C0LMAR1) CAN0 Message Slot 2 Control Register (C0MCTL2)/ CAN0 Local Mask Register A Extended ID0 (C0LMAR2) CAN0 Message Slot 3 Control Register (C0MCTL3)/ CAN0 Local Mask Register A Extended ID1 (C0LMAR3) CAN0 Message Slot 4 Control Register (C0MCTL4)/ CAN0 Local Mask Register A Extended ID2 (C0LMAR4) CAN0 Message Slot 5 Control Register (C0MCTL5) CAN0 Message Sot 6 Control Register (C0MCTL6) CAN0 Message Slot 7 Control Register (C0MCTL7) CAN0 Message Slot 8 Control register (C0MCTL8)/ CAN0 Local Mask Register B Standard ID0 (C0LMBR0) 355/ 348 355/ 349 355/ 350 355/ 351 355/ 352 355 355/ 348 Blank spaces are reserved . No access is allowed. B-5 Quick Reference by Address Address 023916 023A16 023B16 023C16 Register Page CAN0 Message Slot 9 Control Register (C0MCTL9)/ 355/ CAN0 Local Mask Register B Standard ID1 (C0LMBR1) 349 CAN0 Message Slot 10 Control Register (C0MCTL10)/ 355/ CAN0 Local Mask Register B Extended ID0 (C0LMBR2) 350 CAN0 Message Slot 11 Control Register (C0MCTL11)/ 355/ CAN0 Local Mask Register B Extended ID1 (C0LMBR3) 351 CAN0 Message Slot 12 Control Register (C0MCTL12)/ 355/ CAN0 Local Mask Register B Extended ID2 (C0LMBR4) 352 CAN0 Message Slot 13 Control Register (C0MCTL13) CAN0 Message Slot 14 Control Register (C0MCTL14) 355 CAN0 Message Slot 15 Control Register(C0MCTL15) CAN0 Slot Buffer Select Register (C0SBS) 359 CAN0 Control Register 1 (C0CTLR1) 327 CAN0 Sleep Control Register (C0SLPR) 328 Address 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 02EB16 02EC16 02ED16 02EE16 02EF16 Register X0 Register Y0 Register (X0R,Y0R) X1 Register Y1 Register (X1R,Y1R) X2 Register Y2 Register (X2R,Y2R) X3 Register Y3 Register (X3R,Y3R) X4 Register Y4 Register (X4R,Y4R) X5 Register Y5 Register (X5R,Y5R) X6 Register Y6 Register (X6R,Y6R) X7 Register Y7 Register (X7R,Y7R) 270 X8 Register Y8 Register (X8R,Y8R) X9 Register Y9 Register (X9R,Y9R) X10 Register Y10 Register (X10R,Y10R) X11 Register Y11 Register (X11R,Y11R) X12 Register Y12 Register (X12R,Y12R) X13 Register Y13 Register (X13R,Y13R) X14 Register Y14 Register (X14R,Y14R) X15 Register Y15 Register (X15R,Y15R) X/Y Control Register (XYC) 270 Page 023D16 023E16 023F16 024016 024116 024216 024316 024416 CAN0 Acceptance Filter Support Register (C0AFS) 024516 024616 024716 024816 024916 024A16 024B16 024C16 024D16 024E16 024F16 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025C16 025D16 025E16 025F16 026016 to 02BF16 364 UART1 Special Mode Register 4 (U1SMR4) UART1 Special Mode Register 3 (U1SMR3) UART1 Special Mode Register 2 (U1SMR2) UART1 Special Mode Register (U1SMR) UART1 Transmit/Receive Mode Register (U1MR) UART1 Bit Rate Register (U1BRG) UART1 Transmit Buffer Register (U1TB) UART1 Transmit/Receive Control Register 0 (U1C0) UART1 Transmit/Receive Control Register 1 (U1C1) UART1 Receive Buffer Register (U1RB) 201 200 199 198 196 195 197 198 195 Blank spaces are reserved. No access is allowed. B-6 Quick Reference by Address Address 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 Register Page Address 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 Register Page UART4 Special Mode Register 4 (U4SMR4) UART4 Special Mode Register 3 (U4SMR3) UART4 Special Mode Register 2 (U4SMR2) UART4 Special Mode Register (U4SMR) UART4 Transmit/Receive Mode Register (U4MR) UART4 Bit Rate Register (U4BRG) UART4 Transmit Buffer Register (U4TB) UART4 Transmit/Receive Control Register 0 (U4C0) UART4 Transmit/Receive Control Register 1 (U4C1) UART4 Receive Buffer Register (U4RB) Timer B3,B4,B5 Count Start Flag (TBSR) 201 200 199 198 196 195 197 198 195 175 UART3 Special Mode Register 4 (U3SMR4) UART3 Special Mode Register 3 (U3SMR3) UART3 Special Mode Register 2 (U3SMR2) UART3 Special Mode Register (U3SMR) UART3 Transmit/Receive Mode Register (U3MR) UART3 Bit Rate Register (U3BRG) UART3 Transmit Buffer Register (U3TB) UART3 Transmit/Receive Control Register 0 (U3C0) UART3 Transmit/Receive Control Register 1 (U3C1) UART3 Receive Buffer Register (U3RB) 201 200 199 198 196 195 197 198 195 Timer A1-1 Register (TA11) Timer A2-1 Register (TA21) Timer A4-1 Register (TA41) Three-Phase PWM Control Register 0 (INVC0) Three-Phase PWM Control Register 1 (INVC1) Three-Phase Output Buffer Register 0 (IDB0) Three-Phase Output Buffer Register 1 (IDB1) Dead Time Timer (DTT) Timer B2 Interrupt Generating Frequency Set Counter (ICTB2) 185 186 187 187 188 188 UART2 Special Mode Register 4 (U2SMR4) UART2 Special Mode Register 3 (U2SMR3) UART2 Special Mode Register 2 (U2SMR2) UART2 Special Mode Register (U2SMR) UART2 Transmit/Receive Mode Register (U2MR) UART2 Bit Rate Register (U2BRG) UART2 Transmit Buffer Register (U2TB) UART2 Transmit/Receive Control Register 0 (U2C0) UART2 Transmit/Receive Control Register 1 (U2C1) UART2 Receive Buffer Register (U2RB) Count Start Flag (TABSR) Clock Prescaler Reset Flag (CPSRF) One-Shot Start Flag (ONSF) Trigger Select Register (TRGSR) Up-Down Flag (UDF) 201 200 199 198 196 195 197 198 195 158 87 159 160 159 Timer B3 Register (TB3) Timer B4 Register (TB4) Timer B5 Register (TB5) 173 Timer A0 Register (TA0) Timer A1 Register (TA1) Timer A2 Register (TA2) Timer A3 Register (TA3) Timer A4 Register (TA4) 157 Timer B3 Mode Register (TB3MR) Timer B4 Mode Register (TB4MR) Timer B5 Mode Register (TB5MR) External Interrupt Request Source Select Register (IFSR) 174 124 Blank spaces are reserved. No access is allowed. B-7 Quick Reference by Address Address 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16 Register Timer B0 Register (TB0) Timer B1 Register (TB1) Timer B2 Register (TB2) Timer A0 Mode Register (TA0MR) Timer A1 Mode Register (TA1MR) Timer A2 Mode Register (TA2MR) Timer A3 Mode Register (TA3MR) Timer A4 Mode Register (TA4MR) Timer B0 Mode Register (TB0MR) Timer B1 Mode Register (TB1MR) Timer B2 Mode Register (TB2MR) Timer B2 Special Mode Register (TB2SC) Count Source Prescaler Register (TCSPR) 173 Page Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 Register A/D0 Register0 (AD00) A/D0 Register1 (AD01) A/D0 Register2 (AD02) A/D0 Register3 (AD03) 253 A/D0 Register4 (AD04) A/D0 Register5 (AD05) A/D0 Register6 (AD06) A/D0 Register7 (AD07) Page 158 174 188 87 A/D0 Control Register 4 (AD0CON4) A/D0 Control Register 2 (AD0CON2) A/D0 Control Register 3 (AD0CON3) A/D0 Control Register 0 (AD0CON0) A/D0 Control Register 1 (AD0CON1) D/A Register 0 (DA0) D/A Register 1 (DA1) D/A Control Register (DACON) 253 251 252 249 250 267 267 267 UART0 Special Mode Register 4 (U0SMR4) UART0 Special Mode Register 3 (U0SMR3) UART0 Special Mode Register 2 (U0SMR2) UART0 Special Mode Register (U0SMR) UART0 Transmit/Receive Mode Register (U0MR) UART0 Bit Rate Register (U0BRG) UART0 Transmit Buffer Register (U0TB) UART0 Transmit/Receive Control Register 0 (U0C0) UART0 Transmit/Receive Control Register 1 (U0C1) UART0 Receive Buffer Register (U0RB) 201 200 199 198 196 195 197 198 195 Function Select Register A8 (PS8) Function Select Register A9 (PS9) 381 382 Function Select Register D1 (PSD1) 382 DMA0 Request Source Select Register (DM0SL) DMA1 Request Source Select Register (DM1SL) DMA2 Request Source Select Register (DM2SL) DMA3 Request Source Select Register (DM3SL) CRC Data Register (CRCD) CRC Input Register (CRCIN) 137 268 Function Select Register C2 (PSC2) Function Select Register C3 (PSC3) Function Select Register C (PSC) 385 386 385 Blank spaces are reserved. No access is allowed. B-8 Quick Reference by Address Address 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 Register Function Select Register A0 (PS0) Function Select Register A1 (PS1) Function Select Register B0 (PSL0) Function Select Register B1 (PSL1) Function Select Register A2 (PS2) Function Select Register A3 (PS3) Function Select Register B2 (PSL2) Function Select Register B3 (PSL3) Function Select Register A5 (PS5) Page 379 383 376 384 Address 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 Register Port P14 Register (P0) Port P14 Register (P1) Port P14 Direction Register (PD0) Port P14 Direction Register (PD1) Port P14 Register (P2) Port P14 Register (P3) Port P14 Direction Register (PD2) Port P14 Direction Register (PD3) Port P14 Register (P4) Port P14 Register (P5) Port P14 Direction Register (PD4) Port P14 Direction Register (PD5) Page 378 377 378 377 378 377 381 Port P6 Register (P6) Port P7 Register (P7) Port P6 Direction Register (PD6) Port P7 Direction Register (PD7) Port P8 Register (P8) Port P9 Register (P9) Port P8 Direction Register (PD8) Port P9 Direction Register (PD9) Port P10 Register (P10) Port P11 Register (P11) Port P10 Direction Register (PD10) Port P11 Direction Register(PD11) Port P12 Register (P12) Port P13 Register (P13) Port P12 Direction Register (PD12) Port P13 Direction Register (PD13) Port P14 Register (P14) Port P15 Register (P15) Port P14 Direction Register (PD14) Port P15 Direction Register (PD15) 378 377 378 377 378 377 378 377 378 377 Pull-up Control Register 0 (PUR0) 03F116 Pull-up Control Register 1 (PUR1) 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Port Control Register (PCR) 387 389 Pull-Up Control Register 2 (PUR2) Pull-Up Control Register 3 (PUR3) Pull-Up Control Register 4 (PUR4) 387 388 Blank spaces are reserved. No access is allowed. B-9 M32C/84 Group (M32C/84, M32C/84T) SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER 1. Overview The M32C/84 group (M32C/84, M32C/84T) microcomputer is a single-chip control unit that utilizes highperformance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/84 group (M32C/84, M32C/84T) is available in 144-pin and 100-pin plastic molded LQFP/QFP packages. With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed. It includes a multiplier and DMAC adequate for office automation, communication devices and industrial equipments, and other high-speed processing applications. 1.1 Applications Automobiles, audio, cameras, office equipment, communications equipment, portable equipment, etc. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 1 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview 1.2 Performance Overview Tables 1.1 and 1.2 list performance overview of the M32C/84 group (M32C/84, M32C/84T). Table 1.1 M32C/84 Group (M32C/84, M32C/84T) Performance (144-Pin Package) Performance M32C/84 M32C/84T CPU Basic Instructions 108 instructions Minimum Instruction Execution Time 31.3 ns 31.3 ns (f(BCLK)=32 MHz, VCC1=4.2 V to 5.5 V) (f(BCLK)=32 MHz, VCC1=4.2 V to 5.5 V) 41.7 ns (f(BCLK)=24 MHz, VCC1=3.0 V to 5.5 V) Operating Mode Single-chip mode, Memory expansion Single-chip mode mode and Microprocessor mode Address Space 16 Mbytes Memory Capacity See Table 1.3 Peripheral I/O Port 123 I/O pins and 1 input pin Function Multifunction Timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Intelligent I/O Time measurement function or Waveform generating function: 16 bits x 8 channels Communication function (Clock synchronous serial I/O, Clock asynchronous serial I/O, HDLC data processing) Serial I/O 5 Channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) CAN Module 1 channel Supporting CAN 2.0B specification A/D Converter 10-bit A/D converter: 1 circuit, 34 channels D/A Converter 8 bits x 2 channels DMAC 4 channels DMAC II Can be activated by all peripheral function interrupt sources Immediate transfer, Calculation transfer and Chain transfer functions CRC Calculation Circuit CRC-CCITT X/Y Converter 16 bits x 16 bits Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt 38 internal and 8 external sources, 5 software sources Interrupt priority level: 7 Clock Generation Circuit 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Oscillation Stop Detect Function Main clock oscillation stop detect function Voltage Detection Circuit Available (optional) Not available(4) Electrical Supply Voltage VCC1=4.2 V to 5.5 V, VCC2=3.0 V to VCC1 VCC1=VCC2=4.2 V to 5.5 V, Charact(f(BCLK)=32 MHz) (f(BCLK)=32 MHz)(3) eristics VCC1=3.0 V to 5.5 V, VCC2=3.0 V to VCC1 (f(BCLK)=24 MHz) Power Consumption 28 mA (VCC1=VCC2=5 V, 28 mA (VCC1=VCC2=5 V, f(BCLK)=32 MHz) f(BCLK)=32 MHz) 10µA (VCC1=VCC2=5 V, 22 mA (VCC1=VCC2=3.3 V, f(BCLK)=24 MHz) f(BCLK)=32 kHz, in wait mode) 10µA (VCC1=VCC2=5 V, f(BCLK)=32 kHz, in wait mode) Flash Program/Erase Supply Voltage 3.3 V ± 0.3 V or 5.0 V ± 0.5 V 5.0 V ± 0.5 V Memory Program and Erase Endurance 100 times (all space) –40 to 85oC (T version) Operating Ambient Temperature –20 to 85oC –40 to 85oC (optional) Package 144-pin plastic molded LQFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 3. The supply voltage of M32C/84T (High-reliability version) must be VCC1=VCC2. 4. The cold start-up/warm start-up determine function is available only at the user's option. All options are on a request basis. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 2 of 495 Characteristic M32C/84 Group (M32C/84, M32C/84T) 1. Overview Table 1.2 M32C/84 Group (M32C/84, M32C/84T) Performance (100-Pin Package) Performance M32C/84 M32C/84T CPU Basic Instructions 108 instructions Minimum Instruction Execution Time 31.3 ns 31.3 ns (f(BCLK)=32 MHz, VCC1=4.2 V to 5.5 V) (f(BCLK)=32 MHz, VCC1=4.2 V to 5.5 V) 41.7 ns (f(BCLK)=24 MHz, V CC1=3.0 V to 5.5 V) Operating Mode Single-chip mode, Memory expansion Single-chip mode mode and Microprocessor mode Address Space 16 Mbytes Memory Capacity See Table 1.3 Peripheral I/O Port 87 I/O pins and 1 input pin Function Multifunction Timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels Three-phase motor control circuit Intelligent I/O Time measurement function or Waveform generating function: 16 bits x 8 channels Communication function (Clock synchronous serial I/O, Clock asynchronous serial I/O, HDLC data processing) Serial I/O 5 Channels Clock synchronous serial I/O, Clock asynchronous serial I/O, IEBus(1), I2C bus(2) CAN Module 1 channel Supporting CAN 2.0B specification A/D Converter 10-bit A/D converter: 1 circuit, 26 channels D/A Converter 8 bits x 2 channels DMAC 4 channels DMAC II Can be activated by all peripheral function interrupt sources Immediate transfer, Calculation transfer and Chain transfer functions CRC Calculation Circuit CRC-CCITT X/Y Converter 16 bits x 16 bits Watchdog Timer 15 bits x 1 channel (with prescaler) Interrupt 38 internal and 8 external sources, 5 software sources Interrupt priority level: 7 Clock Generation Circuit 4 circuits Main clock oscillation circuit(*), Sub clock oscillation circuit(*), On-chip oscillator, PLL frequency synthesizer (*)Equipped with a built-in feedback resistor. Ceramic resonator or crystal oscillator must be connected externally Oscillation Stop Detect Function Main clock oscillation stop detect function Voltage Detection Circuit Available (optional) Not available(4) Electrical Supply Voltage VCC1=4.2 V to 5.5 V, VCC2=3.0 V to VCC1 VCC1=VCC2=4.2 V to 5.5 V, Charact(f(BCLK)=32 MHz) (f(BCLK)=32 MHz)(3) eristics VCC1=3.0 V to 5.5 V, VCC2=3.0 V to VCC1 (f(BCLK)=24 MHz) 28 mA (VCC1=VCC2=5 V, Power Consumption 28 mA (VCC1=VCC2=5 V, f(BCLK)=32 MHz) f(BCLK)=32 MHz) 22 mA (VCC1=VCC2=3.3 V, 10µA (VCC1=VCC2=5 V, f(BCLK)=24 MHz) f(BCLK)=32 kHz, in wait mode) 10µA (VCC1=VCC2=5 V, f(BCLK)=32 kHz, in wait mode) Flash Program/Erase Supply Voltage 3.3 V ± 0.3 V or 5.0 V ± 0.5 V 5.0 V ± 0.5 V Memory Program and Erase Endurance 100 times (all space) Operating Ambient Temperature –20 to 85oC –40 to 85oC (T version) oC (optional) –40 to 85 Package 100-pin plastic molded LQFP/QFP NOTES: 1. IEBus is a trademark of NEC Electronics Corporation. 2. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 3. The supply voltage of M32C/84T (High-reliability version) must be VCC1=VCC2. 4. The cold start-up/warm start-up determine function is available only at the user's option. All options are on a request basis. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 3 of 495 Characteristic M32C/84 Group (M32C/84, M32C/84T) 1. Overview 1.3 Block Diagram Figure 1.1 shows a block diagram of the M32C/84 group (M32C/84, M32C/84T) microcomputer. 8 8 8 8 8 8 8 Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Peripheral Functions Timer (16 bits) Timer A: 5 channels Timer B: 6 channels Three-Phase Motor Control Circuit Watchdog Timer (15 bits) D/A Converter: 8 bits x 2 channels A/D Converter: 1 circuit Standard: 10 inputs Maximum: 34 inputs(2) UART/Clock Synchronous Serial I/O: 5 channels X/Y Converter: 16 bits x 16 bits CAN Module: 1 channel Clock Generation Circuit XIN - XOUT XCIN - XCOUT On-chip Oscillator PLL Frequency Synthesizer Port P7 8 DMAC Port P8 DMACII CRC Calculation Circuit (CCITT): X16+X12+X5+1 7 P85 M32C/80 series CPU Core Intelligent I/O Time Measurement: 8 channels Waveform Generating: 8 channels Communication Functions: Clock Synchronous Serial I/O, UART, HDLC Data Processing R0H R1H R2 R3 A0 A1 FB SB R0L R1L FLG INTB ISP USP PC SVF SVP VCT Memory ROM Port P9 8 RAM Port P10 8 Multiplier Port P14 Port P15 Port P11 Port P12 Port P13 7 8 5 8 8 (Note 1) NOTES: 1. Ports P11 to P15 are provided in the 144-pin package only. 2. Included in the 144-pin package only. 3. The supply voltage of M32C/84T (High-reliability version) must be VCC1=VCC2. Figure 1.1 M32C/84 Group (M32C/84, M32C/84T) Block Diagram Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 4 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview 1.4 Product Information Table 1.3 lists product information. Figure 1.2 shows the product numbering system. Table 1.3 M32C/84 Group (1) (M32C/84) Type Number M30845FJGP M30843FJGP M30843FJFP M30845FHGP M30843FHGP M30843FHFP M30845FWGP M30843FWGP M30845MW-XXXGP M30843MW-XXXGP M30843MW-XXXFP M30842ME-XXXGP M30840ME-XXXGP M30840ME-XXXFP M30842MC-XXXGP M30840MC-XXXGP M30840MC-XXXFP M30842SGP M30840SGP M30840SFP (D): Under Development (D) (D) (D) Package PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0144KA-A (144P6Q-A) Flash Memory PLQP0100KB-A (100P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0144KA-A (144P6Q-A) 320K+4K PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PRQP0100JB-A (100P6S-A) 10K PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PRQP0100JB-A (100P6S-A) --ROMless 128K 192K 16K Mask ROM 320K 384K+4K 24K 512K+4K ROM Capacity RAM Capacity As of July, 2005 Remarks Table 1.3 M32C/84 Group (2) (T Version, M32C/84T) Type Number M30845FJTGP M30843FJTGP M30845FHTGP M30843FHTGP M30843FWTGP M30842MCT-XXXGP M30840MCT-XXXGP (D): Under Development (D) (D) Package PLQP0144KA-A (144P6Q-A) 512K+4K PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) 384K+4K PLQP0100KB-A (100P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) 128K PLQP0100KB-A (100P6Q-A) 10K 320K+4K 24K ROM Capacity RAM Capacity As of July, 2005 Remarks Flash Memory T Version (High-releability 85° C Version) Mask ROM Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 5 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview M30 84 5 M W -XXX GP Package Type: FP = Package PRQP0100JB-A (100P6S-A) GP = Package PLQP0100KB-A (100P6Q-A) Package PLQP0144KA-A (144P6Q-A) ROM Number: Omitted in the Flash Memory Version Classification: Blank = General Industrial Use T = T Version ROM Capacity: C = 128 Kbytes E = 192 Kbytes W = 320 Kbytes H = 384 Kbytes J = 512 Kbytes Memory Type: M = Mask ROM Version F = Flash Memory Version S = ROMless Version RAM Capacity, Pin Count, etc M32C/84 Group M16C Family Figure 1.2 Product Numbering System Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 6 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview 1.5 Pin Assignments and Descriptions Figures 1.3 to 1.5 show pin assignments (top view). 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 D8 / P10 AN07 / D7 / P07 AN06 / D6 / P06 AN05 / D5 / P05 AN04 / D4 / P04 P114 OUTC13 / INPC13 / P113 BE1IN / ISRxD1 / OUTC12 / INPC12 / P112 ISCLK1 / OUTC11 / INPC11 / P111 BE1OUT / ISTxD1 / OUTC10 / INPC10 / P110 AN03 / D3 / P03 AN02 / D2 / P02 AN01 / D1 / P01 AN00 / D0 / P00 AN157 / P157 AN156 / P156 AN155 / P155 AN154 / P154 AN153 / P153 ISRxD0 / AN152 / P152 ISCLK0 / AN151 / P151 Vss ISTxD0 / AN150 / P150 Vcc1 KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN3 / P103 AN2 / P102 AN1 / P101 AVss AN0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss P30 / A8 ( / D8 ) Vcc2 P120 P121 P122 P123 P124 P31 / A9 ( / D9 ) P32 / A10 ( / D10 ) P33 / A11 ( / D11 ) P34 / A12 ( / D12 ) P35 / A13 ( / D13 ) P36 / A14 ( / D14 ) P37 / A15 ( / D15 ) P40 / A16 P41 / A17 Vss P42 / A18 Vcc2 P43 / A19 M32C/84 GROUP (3) (M32C/84, M32C/84T) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 38 37 P44 / CS3 / A20 P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P125 P126 P127 P50 / WRL / WR P51 / WRH / BHE P52 / RD P53 / CLKOUT / BCLK / ALE P130 P131 Vcc2 P132 Vss P133 P54 / HLDA / ALE P55 / HOLD P56 / ALE P57 / RDY P134 P135 P136 P137 P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64 / CTS1 / RTS1 / SS1 P65 / CLK1 Vss P66 / RxD1 / SCL1 / STxD1 Vcc1 P67 / TxD1 / SDA1 / SRxD1 (1, 2) P70 NOTES: 1. P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / INPC16 / OUTC16 2. P70 and P71 are ports for the N-channel open drain output. 3. The supply voltage of M32C/84T must be VCC1=VCC2. SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 SRxD3 / SDA3 / TxD3 / TB2IN / P92 STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 P146 P145 P144 OUTC17 / INPC17 / P143 OUTC16 / INPC16 / P142 OUTC15 / INPC15 / P141 OUTC14 / INPC14 / P140 BYTE CNVss XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc1 NMI / P85 INT2 / P84 CAN0IN / INT1 / P83 CAN0OUT / INT0 / P82 INPC15 / OUTC15 / U / TA4IN / P81 ISRxD0 / U / TA4OUT / P80 ISCLK0 / INPC14 / OUTC14 / CAN0IN / TA3IN / P77 ISTxD0 / INPC13 / OUTC13 / CAN0OUT / TA3OUT / P76 BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 BE1OUT / ISTxD1 / OUTC10 / INPC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 CLK2 / V / TA1OUT / P72 (2)INPC17 / OUTC17 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 36 11 1 2 3 4 5 6 7 8 9 PLQP0144KA-A (144P6Q-A) Figure 1.3 Pin Assignment for 144-Pin Package Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 7 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview Table 1.4 Pin Characteristics for 144-Pin Package Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BYTE 16 CNVSS 17 XCIN 18 XCOUT 19 RESET 20 XOUT 21 VSS 22 XIN 23 VCC1 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 VCC1 40 41 VSS 42 43 44 45 46 47 48 P87 P86 Control Pin Port P96 P95 P94 P93 P92 P91 P90 P146 P145 P144 P143 P142 P141 P140 TB4IN TB3IN TB2IN TB1IN TB0IN Interrupt Pin Timer Pin UART/CAN Pin TxD4/SDA4/SRxD4 CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 Intelligent I/O Pin Analog Pin Bus Control Pin(1) ANEX1 ANEX0 DA1 DA0 INPC17/OUTC17 INPC16/OUTC16 INPC15/OUTC15 INPC14/OUTC14 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P137 NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TB5IN/TA0IN TA0OUT CAN0IN CAN0OUT INPC15/OUTC15 ISRxD0 INPC14/OUTC14/ISCLK0 INPC13/OUTC13/ISTxD0 INPC12/OUTC12/ISRxD1/BE1IN INPC11/OUTC11/ISCLK1 INPC10/OUTC10/ISTxD1/BE1OUT INPC17/OUTC17 INPC16/OUTC16 CAN0IN CAN0OUT CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 NOTES: 1. Bus control pins in M32C/84T cannot be used. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 8 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview Table 1.4 Pin Characteristics for 144-Pin Package (Continued) Pin No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 VSS P132 VCC2 P131 P130 P53 P52 P51 P50 P127 P126 P125 P47 P46 P45 P44 P43 VCC2 P42 VSS P41 P40 P37 P36 P35 P34 P33 P32 P31 P124 P123 P122 P121 P120 VCC2 P30 VSS P27 P26 P25 AN27 AN26 AN25 A7(/D7) A6(/D6) A5(/D5) A8(/D8) A17 A16 A15(/D15) A14(/D14) A13(/D13) A12(/D12) A11(/D11) A10(/D10) A9(/D9) A18 CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19 CLKOUT/BCLK/ALE RD WRH/BHE WRL/WR Control Pin Port P136 P135 P134 P57 P56 P55 P54 P133 RDY ALE HOLD HLDA/ALE Interrupt Pin Timer Pin UART/CAN Pin Intelligent I/O Pin Analog Pin Bus Control Pin NOTES: 1. Bus control pins in M32C/84T cannot be used. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 9 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview Table 1.4 Pin Characteristics for 144-Pin Package (Continued) Pin No. 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 VSS 131 132 VCC1 133 134 135 136 137 138 139 140 AVSS 141 142 VREF 143 AVCC 144 Control Pin Port P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P114 P113 P112 P111 P110 P03 P02 P01 P00 P157 P156 P155 P154 P153 P152 P151 P150 P107 P106 P105 P104 P103 P102 P101 P100 KI3 KI2 KI1 KI0 ISRxD0 ISCLK0 ISTxD0 INPC13/OUTC13 INPC12/OUTC12/ISRxD1/BE1IN INPC11/OUTC11/ISCLK1 INPC10/OUTC10/ISTxD1/BE1OUT AN03 AN02 AN01 AN00 AN157 AN156 AN155 AN154 AN153 AN152 AN151 AN150 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 D3 D2 D1 D0 AN07 AN06 AN05 AN04 INT5 INT4 INT3 Interrupt Pin Timer Pin UART/CAN Pin Intelligent I/O Pin Analog Pin AN24 AN23 AN22 AN21 AN20 Bus Control Pin(1) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 P97 RxD4/SCL4/STxD4 ADTRG NOTES: 1. Bus control pins in M32C/84T cannot be used. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 10 of 495 M32C/84 Group (M32C/84, M32C/84T) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 11 of 495 Figure 1.4 Pin Assignment for 100-Pin Package KI0 / AN4 / P104 KI1 / AN5 / P105 KI2 / AN6 / P106 KI3 / AN7 / P107 D0 / AN00 / P00 D1 / AN01 / P01 D2 / AN02 / P02 D3 / AN03 / P03 D4 / AN04 / P04 D5 / AN05 / P05 D6 / AN06 / P06 D7 / AN07 / P07 AN1 / P101 AN2 / P102 AN3 / P103 AN0 / P100 NOTES: SRxD4 / SDA4 / TxD4 / ANEX1 / P96 CLK4 / ANEX0 / P95 SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 SRxD3 / SDA3 / TxD3 / TB2IN / P92 STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 BYTE CNVss XCIN / P87 XCOUT / P86 RESET XOUT Vss XIN Vcc1 NMI / P85 INT2 / P84 CAN0IN / INT1 / P83 CAN0OUT / INT0 / P82 OUTC15 / INPC15 / U / TA4IN / P81 ISRxD0 / U / TA4OUT / P80 ISCLK0 / OUTC14 / INPC14 / CAN0IN / TA3IN / P77 ISTxD0 / OUTC13 / INPC13 / CAN0OUT / TA3OUT / P76 BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CLK2 / V / TA1OUT / P72 (2)OUTC17 / INPC17 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71 (2)OUTC16 / INPC16 / SRxD2 / SDA2 / TxD2 / TA0OUT / P70 1. P97 / ADTRG / RxD4 / SCL4 / STxD4 2. P70 and P71 are ports for the N-channel open drain output. (1) VREF 98 AVcc 99 AVss P97 100 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P10 / D8 P11 / D9 P12 / D10 P13 / D11 P14 / D12 P15 / D13 / INT3 P16 / D14 / INT4 P17 / D15 / INT5 P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 Vss P30 / A8 ( / D8 ) Vcc2 P31 / A9 ( / D9 ) P32 / A10 ( / D10 ) P33 / A11 ( / D11 ) P34 / A12 ( / D12 ) P35 / A13 ( / D13 ) P36 / A14 ( / D14 ) P37 / A15 ( / D15 ) P40 / A16 P41 / A17 P42 / A18 P43 / A19 M32C/84 GROUP (M32C/84) 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 BE1OUT / ISTxD1 / OUTC10 / INPC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PRQP0100JB-A (100P6S-A) P67 / TxD1 / SDA1 / SRxD1 P66 / RxD1 / SCL1 / STxD1 P65 / CLK1 P64 / CTS1 / RTS1 / SS1 P63 / TxD0 / SDA0 / SRxD0 P62 / RxD0 / SCL0 / STxD0 P61 / CLK0 P60 / CTS0 / RTS0 / SS0 P57 / RDY P56 / ALE P55 / HOLD P53 / CLKOUT / BCLK / ALE P52 / RD P51 / WRH / BHE P50 / WRL / WR P47 / CS0 / A23 P46 / CS1 / A22 P45 / CS2 / A21 P44 / CS3 / A20 P54 / HLDA / ALE 1. Overview M32C/84 Group (M32C/84, M32C/84T) 1. Overview P20 / A0 ( / D0 ) / AN20 P21 / A1 ( / D1 ) / AN21 P22 / A2 ( / D2 ) / AN22 P23 / A3 ( / D3 ) / AN23 P24 / A4 ( / D4 ) / AN24 P25 / A5 ( / D5 ) / AN25 P26 / A6 ( / D6 ) / AN26 P27 / A7 ( / D7 ) / AN27 P32 / A10 ( / D10 ) P34 / A12 ( / D12 ) P35 / A13 ( / D13 ) P36 / A14 ( / D14 ) P15 / D13 / INT3 P31 / A9 ( / D9 ) P14 / D12 P13 / D11 P37 / A15 ( / D15 ) 53 P33 / A11 ( / D11 ) P16 / D14 / INT4 P17 / D15 / INT5 P30 / A8 ( / D8 ) P40 / A16 52 75 74 73 72 71 70 69 68 67 65 64 63 62 61 60 59 58 57 56 54 51 50 49 48 47 46 45 44 43 42 41 66 D10 / P12 D9 / P11 D8 / P10 D7 / AN07 / P07 D6 / AN06 / P06 D5 / AN05 / P05 D4 / AN04 / P04 D3 / AN03 / P03 D2 / AN02 / P02 D1 / AN01 / P01 D0 / AN00 / P00 KI3 / AN7 / P107 KI2 / AN6 / P106 KI1 / AN5 / P105 KI0 / AN4 / P104 AN3 / P103 AN2 / P102 AN1 / P101 AVss AN0 / P100 VREF AVcc STxD4 / SCL4 / RxD4 / ADTRG / P97 (3) 55 P41 / A17 Vcc2 Vss 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 P42 / A18 P43 / A19 P44 / CS3 / A20 P45 / CS2 / A21 P46 / CS1 / A22 P47 / CS0 / A23 P50 / WRL / WR P51 / WRH / BHE P52 / RD P53 / CLKOUT / BCLK / ALE P54 / HLDA / ALE P55 / HOLD P56 / ALE P57 / RDY P60 / CTS0 / RTS0 / SS0 P61 / CLK0 P62 / RxD0 / SCL0 / STxD0 P63 / TxD0 / SDA0 / SRxD0 P64 / CTS1 / RTS1 / SS1 P65 / CLK1 P66 / RxD1 / SCL1 / STxD1 P67 / TxD1 / SDA1 / SRxD1 P70 P71 (1, 4) (2, 4) M32C/84 GROUP (M32C/84, M32C/84T)(5) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 P96 10 12 13 14 15 16 17 19 20 21 23 24 25 18 22 11 1 2 3 4 5 6 7 8 9 CLK4 / ANEX0 / P95 P72 / TA1OUT / V / CLK2 XOUT SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94 SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93 SRxD3 / SDA3 / TxD3 / TB2IN / P92 STxD3 / SCL3 / RxD3 / TB1IN / P91 CLK3 / TB0IN / P90 XCIN / P87 XCOUT / P86 RESET BYTE Vss XIN Vcc1 NMI / P85 INT2 / P84 CAN0IN / INT1 / P83 CAN0OUT / INT0 / P82 OUTC15 / INPC15 / U / TA4IN / P81 ISRxD0 / U / TA4OUT / P80 ISCLK0 / OUTC14 / INPC14 / CAN0IN / TA3IN / P77 ISTxD0 / OUTC13 / INPC13 / CAN0OUT / TA3OUT / P76 BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75 ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74 NOTES: 1. P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC16 / INPC16 2. P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 / OUTC17 / INPC17 3. P96 / ANEX1 / TxD4 / SDA4 / SRxD4 4. P70 and P71 are ports for the N-channel open drain output. 5. The supply voltage of M32C/84T must be VCC1=VCC2. BE1OUT / ISTxD1 / OUTC10 / SS2 / INPC10 / RTS2 / CTS2 / V / TA1IN / P73 CNVss PLQP0100KB-A (100P6Q-A) Figure 1.5 Pin Assignment for 100-Pin Package Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 12 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview Table 1.5 Pin Characteristics for 100-Pin Package Package Pin No. FP GP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Control Pin Port P96 P95 P94 P93 P92 P91 P90 Interrupt Pin Timer Pin UART/CAN Pin TxD4/SDA4/SRxD4 CLK4 CTS4/RTS4/SS4 CTS3/RTS3/SS3 TxD3/SDA3/SRxD3 RxD3/SCL3/STxD3 CLK3 Intelligent I/O Pin Analog Bus Control Pin(1) Pin ANEX1 ANEX0 DA1 DA0 TB4IN TB3IN TB2IN TB1IN TB0IN BYTE CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC1 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54 P53 P52 P51 P50 P47 P46 P45 P44 NMI INT2 INT1 INT0 TA4IN/U TA4OUT/U TA3IN TA3OUT TA2IN/W TA2OUT/W TA1IN/V TA1OUT/V TB5IN/TA0IN TA0OUT CAN0IN CAN0OUT INPC15/OUTC15 CAN0IN CAN0OUT ISRxD0 INPC14/OUTC14/ISCLK0 INPC13/OUTC13/ISTxD0 INPC12/OUTC12/ISRxD1/BE1IN INPC11/OUTC11/ISCLK1 INPC10/OUTC10/ISTxD1/BE1OUT INPC17/OUTC17 INPC16/OUTC16 CTS2/RTS2/SS2 CLK2 RxD2/SCL2/STxD2 TxD2/SDA2/SRxD2 TxD1/SDA1/SRxD1 RxD1/SCL1/STxD1 CLK1 CTS1/RTS1/SS1 TxD0/SDA0/SRxD0 RxD0/SCL0/STxD0 CLK0 CTS0/RTS0/SS0 RDY ALE HOLD HLDA/ALE CLKOUT/BCLK/ALE RD WRH/BHE WRL/WR CS0/A23 CS1/A22 CS2/A21 CS3/A20 NOTES: 1. Bus control pins in M32C/84T cannot be used. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 13 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview Table 1.5 Pin Characteristics for 100-Pin Package (Continued) Package Pin No. FP GP 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 VCC2 P30 VSS P27 P26 P25 P24 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 P02 P01 P00 P107 P106 P105 P104 P103 P102 P101 AVSS P100 VREF AVCC P97 RxD4/SCL4/STxD4 ADTRG AN0 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 INT5 INT4 INT3 A7(/D7) A6(/D6) A5(/D5) A4(/D4) A3(/D3) A2(/D2) A1(/D1) A0(/D0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A8(/D8) P43 P42 P41 P40 P37 P36 P35 P34 P33 P32 P31 A19 A18 A17 A16 A15(/D15) A14(/D14) A13(/D13) A12(/D12) A11(/D11) A10(/D10) A9(/D9) Control Pin Port Interrupt Pin Timer Pin UART/CAN Pin Intelligent I/O Pin Analog Pin Bus Control Pin KI3 KI2 KI1 KI0 AN07 AN06 AN05 AN04 AN03 AN02 AN01 AN00 AN7 AN6 AN5 AN4 AN3 AN2 AN1 NOTES: 1. Bus control pins in M32C/84T cannot be used. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 14 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview 1.6 Pin Description Table 1.6 Pin Description (100-Pin and 144-Pin Packages) Classsfication Power Supply Analog Power Supply Reset Input CNVSS Symbol VCC1, VCC2 VSS AVCC AVSS ____________ I/O Type I I I I I Supply Voltage VCC1 VCC1 VCC1 VCC1 Function Apply 3.0 to 5.5V to both VCC1 and VCC2 pins. Apply 0V to the VSS pin. VCC1 ≥ VCC2(1, 2) Supplies power to the A/D converter. Connect the AVCC pin to VCC1 and the AVSS pin to VSS ___________ RESET CNVSS The microcomputer is in a reset state when "L" is applied to the RESET pin Switches processor mode. Connect the CNVSS pin to VSS to start up in single-chip mode or to VCC1 to start up in microprocessor mode Switches data bus width in external memory space 3. The data bus is 16 bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H". Set to either. Connect the BYTE pin to VSS Input to Switch BYTE External Data Bus Width(3) Bus Control Pins(3) D8 to D15 A0 to A22 ______ D 0 to D 7 I/O I/O O O I/O VCC2 VCC2 VCC2 VCC2 VCC2 to use the microcomputer in single-chip mode Inputs and outputs data (D0 to D7) while accessing an external memory space with separate bus Inputs and outputs data (D8 to D15) while accessing an external memory space with 16-bit separate bus Outputs address bits A0 to A22 Outputs inversed address bit A23 Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0 to A7) by time-sharing while accessing an external memory space with multiplexed bus A23 A0/D0 to A7/D7 A8/D8 to A15/D15 ______ ________ ______ I/O VCC2 Inputs and outputs data (D8 to D15) and outputs 8 middle-order address bits (A8 to A15) by time-sharing while accessing an external memory space with 16-bit multiplexed bus _______ _______ Outputs CS0 to CS3 that are chip-select signals specifying an external space ________ _________ _________ ______ ________ _____ ________ CS0 to CS3 ______ O O VCC2 VCC2 WRL / WR _________ ________ WRH / BHE _____ Outputs WRL, WRH, (WR, BHE) and RD signals. WRL and ______ _______ WRH can be switched with WR and BHE by program ________ _________ _____ RD WRL, WRH and RD selected: If external data bus is 16 bits wide, data is written to an even ________ address in external memory space when WRL is held "L". _________ Data is written to an odd address when WRH is held "L". _____ Data is read when RD is held "L". ________ _____ WR, BHE and RD selected: ______ ______ Data is written to external memory space when WR is held "L". _____ Data in an external memory space is read when RD is held "L". ________ An odd address is accessed when BHE is held "L". ______ ________ _____ Select WR, BHE and RD for external 8-bit data bus. ALE __________ HOLD __________ O I VCC2 VCC2 ALE is a signal latching the address __________ The microcomputer is placed in a hold state while the HOLD pin is held "L" I : Input NOTES: 1. VCC1 is hereinafter referred to as VCC unless otherwise noted. 2. Apply 4.2 to 5.5V to the VCC1 and VCC2 pins when using M32C/84T. VCC1=VCC2. 3. Bus cotrol pins in M32C/84T cannot be used. HLDA RDY O : Output ________ O VCC2 Outputs an "L" signal while the microcomputer is placed in a hold state ________ I VCC2 Bus is placed in a wait state while the RDY pin is held "L" I/O : Input and output Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 15 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued) Classsfication Symbol I/O Type I O I O O O I I I I I/O I I O I O I/O I O I/O I/O O I Supply Voltage VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 Function I/O pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To apply external clock, apply it to XIN and leave XOUT open I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To apply external clock, apply it to XCIN and leave XCOUT open Outputs BCLK signal Outputs the clock having the same frequency as fC, f8 or f32 ______ Input pins for the INT interrupt _______ Main Clock Input XIN Main Clock Output XOUT Sub Clock Input XCIN Sub Clock Output XCOUT BCLK Output(1) BCLK Clock Output ______ INT Interrupt CLKOUT ________ ________ INT0 to INT2 ________ ________ Input INT3 to INT5 _______ _______ NMI Interrupt Input NMI _____ _____ Input pin for the NMI interrupt Input pins for the key input interrupt I/O pins for the timer A0 to A4 (TA0OUT is a pin for the N-channel open drain output.) Input pins for the timer A0 to A4 Input pins for the timer B0 to B5 Output pins for the three-phase motor control timer Iutput pins for data transmission control Output pins for data reception control Inputs and outputs the transfer clock Inputs serial data Outputs serial data (TxD2 is a pin for the N-channel open drain output.) Inputs and outputs serial data (SDA2 is a pin for the N-channel open drain output.) Inputs and outputs the transfer clock (SCL2 is a pin for the N-channel open drain output.) Outputs serial data when slave mode is selected (STxD2 is a pin for the N-channel open drain output.) Inputs serial data when slave mode is selected Key Input Interrupt KI0 to KI3 Timer A TA0OUT to TA4OUT TA0IN to Timer B TA4IN TB0IN to TB5IN ___ ___ Three-phase Motor U, U, V, V, ___ Control Timer Output W, W _________ ________ Serial I/O CTS0 to CTS4 _________ ________ RTS0 to RTS4 CLK0 to CLK4 RxD0 to RxD4 TxD0 to TxD4 I 2C Mode SDA0 to SDA4 SCL0 to Serial I/O SCL4 STxD0 to Special Function STxD4 SRxD0 to I : Input NOTES: 1. Bus control pins in M32C/84T cannot be used. SRxD4 _______ _______ SS0 to SS4 I VCC1 Input pins to control serial I/O special function O : Output I/O : Input and output Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 16 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued) Classsfication Reference Voltage Input A/D Converter Symbol VREF AN0 to AN7 AN00 to AN07 AN20 to AN27 ___________ I/O Type I I Supply Voltage VCC1 Function Applies reference voltage to the A/D converter and D/A converter Analog input pins for the A/D converter ADTRG ANEX0 ANEX1 D/A Converter Intelligent I/O DA0, DA1 INPC10 to INPC13 INPC14 to INPC17 OUTC10 to OUTC13 OUTC14 to OUTC17 ISCLK0 ISCLK1 ISRXD0 ISRXD1 ISTXD0 ISTXD1 BE1IN BE1OUT CAN I/O Ports CAN0IN CAN0OUT P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P90 to P97 P100 to P107 P80 to P84 P86, P87 Input Port P85 I I/O I O I I O O I/O I/O I I O O I O I O I/O VCC1 VCC1 VCC1 VCC1 Input pin for an external A/D trigger Extended analog input pin for the A/D converter and output pin in external op-amp connection mode Extended analog input pin for the A/D converter Output pin for the D/A converter VCC1/VCC2(1) Input pins for the time measurement function VCC1 VCC1/VCC2(1) Output pins for the waveform generating function VCC1 (OUTC16 and OUTC17 assgined to P70 and P71 are pins for the N-channel open drain output.) VCC1 Inputs and outputs the clock for the intellignet I/O communication (1) function VCC1/VCC2 VCC1 Inputs data for the intellignet I/O communication function VCC1/VCC2(1) VCC1 Outputs data for the intellignet I/O communication function VCC1/VCC2(1) VCC1/VCC2(1) Inputs data for the intellignet I/O communication function VCC1/VCC2(1) Outputs data for the intellignet I/O communication function VCC1 VCC1 VCC2 Input pin for the CAN communication function Output pin for the CAN communication function I/O ports for CMOS. Each port can be programmed for input or output under the control of the direction register. An input port can be set, by program, for a pull-up resistor available or for no pull-up resister available in 4-bit units I/O VCC1 I/O ports having equivalent functions to P0 (P70 and P71 are ports for the N-channel open drain output.) I/O I VCC1 VCC1 I/O ports having equivalent functions to P0 _______ _______ Shares a pin with NMI. NMI input state can be got by reading P8 5 I : Input O : Output I/O : Input and output NOTES: 1. VCC2 is not available in the 100-pin package. VCC1 only available. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 17 of 495 M32C/84 Group (M32C/84, M32C/84T) 1. Overview Table 1.6 Pin Description (144-Pin Package only) (Continued) Classsfication A/D Converter I/O Ports Symbol AN150 to AN157 P110 to P114 P120 to P127 P130 to P137 P140 to P146 P150 to P157 I : Input O : Output I/O VCC1 I/O ports having equivalent functions to P0 I/O Type I I/O Supply Function Voltage Analog input pins for the A/D converter VCC1 I/O ports having equivalent functions to P0 VCC2 I/O : Input and output Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 18 of 495 M32C/84 Group (M32C/84, M32C/84T) 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised of 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers. Two sets of register banks are provided. b31 b15 b0 General Register R2 R3 R0H R1H R2 R0L R1L Data Register(1) b23 R3 A0 A1 SB FB USP ISP INTB PC FLG Address Register(1) Static Base Register(1) Frame Base Register(1) User Stack Pointer Interrupt Stack Pointer Interrupt Table Register Program Counter Flag Register b0 b15 b8 b7 IPL U I OBSZDC Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Space Processor Interrupt Priority Level Reserved Space b15 b0 High-Speed Interrupt Register b23 SVF SVP VCT b7 b0 Flag Save Register PC Save Register Vector Register DMAC-Associated Register b15 DMD0 DMD1 DCT0 DCT1 DRC0 b23 DMA Mode Register DMA Transfer Count Register DRC1 DMA0 DMA1 DRA0 DRA1 DSA0 DSA1 DMA Transfer Count Reload Register DMA Memory Address Register DMA Memory Address Reload Register DMA SFR Address Register NOTES: 1. The register bank is comprised of these registers. Two sets of register banks are provided. Figure 2.1 CPU Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 19 of 495 M32C/84 Group (M32C/84, M32C/84T) 2. Central Processing Unit (CPU) 2.1 General Registers 2.1.1 Data Registers (R0, R1, R2 and R3) R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and R3. 2.1.2 Address Registers (A0 and A1) A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations. 2.1.3 Static Base Register (SB) SB is a 24-bit register for SB-relative addressing. 2.1.4 Frame Base Register (FB) FB is a 24-bit register for FB-relative addressing. 2.1.5 Program Counter (PC) PC, 24 bits wide, indicates the address of an instruction to be executed. 2.1.6 Interrupt Table Register (INTB) INTB is a 24-bit register indicating the starting address of an relocatable interrupt vector table. 2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently. 2.1.8 Flag Register (FLG) FLG is a 16-bit register indicating a CPU state. 2.1.8.1 Carry Flag (C) The C flag indicates whether carry or borrow has occurred after executing an instruction. 2.1.8.2 Debug Flag (D) The D flag is for debug only. Set to "0". 2.1.8.3 Zero Flag (Z) The Z flag is set to "1" when the value of zero is obtained from an arithmetic operation; otherwise "0". 2.1.8.4 Sign Flag (S) The S flag is set to "1" when a negative value is obtained from an arithmetic operation; otherwise "0". Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 20 of 495 M32C/84 Group (M32C/84, M32C/84T) 2. Central Processing Unit (CPU) 2.1.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this flag is set to "1". 2.1.8.6 Overflow Flag (O) The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0". 2.1.8.7 Interrupt Enable Flag (I) The I flag enables a maskable interrupt. Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt is acknowledged. 2.1.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1". The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.1.8.9 Processor Interrupt Priority Level (IPL) IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled. 2.1.8.10 Reserved Space When writing to a reserved space, set to "0". When reading, its content is indeterminate. 2.2 High-Speed Interrupt Registers Registers associated with the high-speed interrupt are as follows: - Flag save register (SVF) - PC save register (SVP) - Vector register (VCT) Refer to 11.4 High-Speed Interrupt for details. 2.3 DMAC-Associated Registers Registers associated with DMAC are as follows: - DMA mode register (DMD0, DMD1) - DMA transfer count register (DCT0, DCT1) - DMA transfer count reload register (DRC0, DRC1) - DMA memory address register (DMA0, DMA1) - DMA SFR address register (DSA0, DSA1) - DMA memory address reload register (DRA0, DRA1) Refer to 13. DMAC for details. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 21 of 495 M32C/84 Group (M32C/84, M32C/84T) 3. Memory 3. Memory Figure 3.1 shows a memory map of the M32C/84 group (M32C/84, M32C/84T). The M32C/84 group (M32C/84, M32C/84T) provides 16-Mbyte address space from addresses 00000016 to FFFFFF16. The internal ROM is allocated lower addresses beginning with address FFFFFF16. For example, a 64Kbyte internal ROM is allocated in addresses FF000016 to FFFFFF16. The fixed interrupt vectors are allocated addresses FFFFDC16 to FFFFFF16. It stores the starting address of each interrupt routine. Refer to 11. Interrupt for details. The internal RAM is allocated higher addresses beginning with address 00040016. For example, a 10Kbyte internal RAM is allocated addresses 00040016 to 002BFF16. Besides storing data, it becomes stacks when the subroutine is called or an interrupt is acknowleged. SFR, consisting of control registers for peripheral functions such as I/O port, A/D converter, serial I/O, and timers, is allocated addresses 00000016 to 0003FF16. All blank spaces within SFR are reserved and cannot be accessed by users. The special page vectors are allocated addresses FFFE0016 to FFFFDB16. It is used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details. In memory expansion mode and microprocessor mode, some spaces are reserved and cannot be accessed by users. 00000016 SFR 00040016 0063FF16 Internal RAM XXXXXX16 Capacity 24 Kbytes 0063FF16 0043FF16 16 Kbytes 10 Kbytes 002BFF16 Internal ROM Capacity YYYYYY16 512 Kbytes 384 Kbytes 320 Kbytes 192 Kbytes 128 Kbytes F8000016 FA000016 FB000016 FD000016 FE000016 F0000016 F8000016 Internal ROM(4) FFFFFF16 FFFFFF 16 Reserved Space(2) Watchdog Timer(5) NMI Reset 00F00016 Internal RAM Reserved Space Internal ROM (Data space) 00FFFF16 External Space(1) (3) FFFE00 16 Special Page Vector Table FFFFDC 16 Undefined Instruction Overflow BRK Instruction Address Match NOTES: 1. In memory expansion mode and microprocessor mode. 2. In memory expansion mode. This space becomes external space in microprocessor mode. 3. Additional 4-Kbyte space is provided in flash memory version for storing data. This space can be used in single-chip mode and memory expansion mode. This space becomes reserved space in microprocessor mode. 4. This space can be used in single-chip mode and memory expansion mode. This space becomes external space in microprocessor mode. 5. Watchdog timer interrupts, oscillation stop detect interrupts, and voltage down detect interrupts share vectors. Figure 3.1 Memory Map Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 22 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) 4. Special Function Registers (SFR) Address 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 Register Symbol Value after RESET Processor Mode Register 0(1) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Address Match Interrupt Enable Register Protect Register External Data Bus Width Control Register(2) Main Clock Division Register Oscillation Stop Detection Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 Processor Mode Register 2 Address Match Interrupt Register 1 Voltage Detection Register 2(2) Address Match Interrupt Register 2 Voltage Detection Register 1(2) Address Match Interrupt Register 3 PM0 PM1 CM0 CM1 AIER PRCR DS MCD CM2 WDTS WDC RMAD0 PM2 RMAD1 VCR2 RMAD2 VCR1 RMAD3 1000 00002(CNVss pin ="L") 0000 00112(CNVss pin ="H") 0016 0000 10002 0010 00002 0016 XXXX 00002 XXXX 10002(BYTE pin ="L") XXXX 00002(BYTE pin ="H") XXX0 10002 0016 XX16 000X XXXX2 00000016 0016 00000016 0016 00000016 0000 10002 00000016 PLL Control Register 0 PLL Control Register 1 Address Match Interrupt Register 4 PLC0 PLC1 RMAD4 0001 X0102 000X 00002 00000016 Address Match Interrupt Register 5 Voltage Down Detection Interrupt Register(2) RMAD5 D4INT 00000016 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The PM01 and PM00 bits in the PM1 register maintain values set before reset even if software reset or watchdog timer reset is performed. 2. These registers in M32C/84T cannot be used. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 23 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 Register Symbol Value after RESET Address Match Interrupt Register 6 RMAD6 00000016 Address Match Interrupt Register 7 RMAD7 00000016 External Space Wait Control Register 0(1) External Space Wait Control Register 1(1) External Space Wait Control Register 2(1) External Space Wait Control Register 3(1) Page Mode Wait Control Register 0(2) Page Mode Wait Control Register 1(2) EWCR0 EWCR1 EWCR2 EWCR3 PWCR0 PWCR1 X0X0 00112 X0X0 00112 X0X0 00112 X0X0 00112 0001 00012 0001 00012 Flash Memory Control Register 1 FMR1 0000 01012 0000 00012(Flash memory version) XXXX XXX02(Masked ROM version) Flash Memory Control Register 0 FMR0 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. These registers in M32C/84T cannot be used. 2. These registers can be used only in the ROMless version. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 24 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16 008016 008116 008216 008316 008416 008516 008616 008716 008816 008916 008A16 008B16 008C16 008D16 008E16 008F16 Register Symbol Value after RESET DMA0 Interrupt Control Register Timer B5 Interrupt Control Register DMA2 Interrupt Control Register UART2 Receive /ACK Interrupt Control Register Timer A0 Interrupt Control Register UART3 Receive /ACK Interrupt Control Register Timer A2 Interrupt Control Register UART4 Receive /ACK Interrupt Control Register Timer A4 Interrupt Control Register UART0/UART3 Bus Conflict Detect Interrupt Control Register UART0 Receive/ACK Interrupt Control Register A/D0 Conversion Interrupt Control Register UART1 Receive/ACK Interrupt Control Register Intelligent I/O Interrupt Control Register 0 Timer B1 Interrupt Control Register Intelligent I/O Interrupt Control Register 2 Timer B3 Interrupt Control Register Intelligent I/O Interrupt Control Register 4 INT5 Interrupt Control Register INT3 Interrupt Control Register Intelligent I/O Interrupt Control Register 8 INT1 Interrupt Control Register Intelligent I/O Interrupt Control Register 10/ CAN Interrupt 1 Control Register CAN Interrupt 2 Control Register DM0IC TB5IC DM2IC S2RIC TA0IC S3RIC TA2IC S4RIC TA4IC BCN0IC/BCN3IC S0RIC AD0IC S1RIC IIO0IC TB1IC IIO2IC TB3IC IIO4IC INT5IC INT3IC IIO8IC INT1IC IIO10IC CAN1IC CAN2IC XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XX00 X0002 XX00 X0002 XXXX X0002 XX00 X0002 XXXX X0002 XXXX X0002 DMA1 Interrupt Control Register UART2 Transmit /NACK Interrupt Control Register DMA3 Interrupt Control Register UART3 Transmit /NACK Interrupt Control Register Timer A1 Interrupt Control Register UART4 Transmit /NACK Interrupt Control Register Timer A3 Interrupt Control Register UART2 Bus Conflict Detect Interrupt Control Register DM1IC S2TIC DM3IC S3TIC TA1IC S4TIC TA3IC BCN2IC XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 25 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 009016 009116 009216 009316 009416 009516 009616 009716 009816 009916 009A16 009B16 009C16 009D16 009E16 009F16 00A016 00A116 00A216 00A316 00A416 00A516 00A616 00A716 00A816 00A916 00AA16 00AB16 00AC16 00AD16 00AE16 00AF16 00B016 00B116 00B216 00B316 00B416 00B516 00B616 00B716 00B816 00B916 00BA16 00BB16 00BC16 00BD16 00BE16 00BF16 Register UART0 Transmit /NACK Interrupt Control Register UART1/UART4 Bus Conflict Detect Interrupt Control Register UART1 Transmit/NACK Interrupt Control Register Key Input Interrupt Control Register Timer B0 Interrupt Control Register Intelligent I/O Interrupt Control Register 1 Timer B2 Interrupt Control Register Intelligent I/O Interrupt Control Register 3 Timer B4 Interrupt Control Register INT4 Interrupt Control Register INT2 Interrupt Control Register Intelligent I/O Interrupt Control Register 9/ CAN Interrupt 0 Control Register INT0 Interrupt Control Register Exit Priority Control Register Interrupt Request Register 0 Interrupt Request Register 1 Interrupt Request Register 2 Interrupt Request Register 3 Interrupt Request Register 4 Symbol S0TIC BCN1IC/BCN4IC S1TIC KUPIC TB0IC IIO1IC TB2IC IIO3IC TB4IC INT4IC INT2IC IIO9IC CAN0IC INT0IC RLVL IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR Value after RESET XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XX00 X0002 XX00 X0002 XXXX X0002 XX00 X0002 XXXX 00002 0000 000X2 0000 000X2 0000 000X2 0000 000X2 0000 000X2 Interrupt Request Register 8 Interrupt Request Register 9 Interrupt Request Register 10 Interrupt Request Register 11 IIO8IR IIO9IR IIO10IR IIO11IR 0000 000X2 0000 000X2 0000 000X2 0000 000X2 Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Enable Register 4 IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE 0016 0016 0016 0016 0016 Interrupt Enable Register 8 Interrupt Enable Register 9 Interrupt Enable Register 10 Interrupt Enable Register 11 IIO8IE IIO9IE IIO10IE IIO11IE 0016 0016 0016 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 26 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 Register Symbol Value after RESET SI/O Receive Buffer Register 0 Transmit Buffer/Receive Data Register 0 Receive Input Register 0 SI/O Communication Mode Register 0 Transmit Output Register 0 SI/O Communication Control Register 0 G0RB G0TB/G0DR G0RI G0MR G0TO G0CR XXXX XXXX2 X000 XXXX2 XX16 XX16 0016 XX16 0000 X0112 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 27 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716 011816 011916 011A16 011B16 011C16 011D16 011E16 011F16 Register Data Compare Register 00 Data Compare Register 01 Data Compare Register 02 Data Compare Register 03 Data Mask Register 00 Data Mask Register 01 Communication Clock Select Register Symbol G0CMP0 G0CMP1 G0CMP2 G0CMP3 G0MSK0 G0MSK1 CCS Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XXXX 00002 XX16 Receive CRC Code Register 0 Transmit CRC Code Register 0 SI/O Extended Mode Register 0 SI/O Extended Receive Control Register 0 SI/O Special Communication Interrupt Detect Register 0 SI/O Extended Transmit Control Register 0 Time Measurement/Waveform Generating Register 10 Time Measurement/Waveform Generating Register 11 Time Measurement/Waveform Generating Register 12 Time Measurement/Waveform Generating Register 13 Time Measurement/Waveform Generating Register 14 Time Measurement/Waveform Generating Register 15 Time Measurement/Waveform Generating Register 16 Time Measurement/Waveform Generating Register 17 Waveform Generating Control Register 10 Waveform Generating Control Register 11 Waveform Generating Control Register 12 Waveform Generating Control Register 13 Waveform Generating Control Register 14 Waveform Generating Control Register 15 Waveform Generating Control Register 16 Waveform Generating Control Register 17 Time Measurement Control Register 10 Time Measurement Control Register 11 Time Measurement Control Register 12 Time Measurement Control Register 13 Time Measurement Control Register 14 Time Measurement Control Register 15 Time Measurement Control Register 16 Time Measurement Control Register 17 G0RCRC G0TCRC G0EMR G0ERC G0IRF G0ETC G1TM0/G1PO0 G1TM1/G1PO1 G1TM2/G1PO2 G1TM3/G1PO3 G1TM4/G1PO4 G1TM5/G1PO5 G1TM6/G1PO6 G1TM7/G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 XX16 0016 0016 0016 0016 0016 0000 0XXX2 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 0000 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0X00 X0002 0016 0016 0016 0016 0016 0016 0016 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 28 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 012016 012116 012216 012316 012416 012516 012616 012716 012816 012916 012A16 012B16 012C16 012D16 012E16 012F16 013016 013116 013216 013316 013416 013516 013616 013716 013816 013916 013A16 013B16 013C16 013D16 013E16 013F16 014016 014116 014216 014316 014416 014516 014616 014716 014816 014916 014A16 014B16 014C16 014D16 014E16 014F16 Base Timer Register 1 Register Symbol G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1RB G1TB/G1DR G1RI G1MR G1TO G1CR G1CMP0 G1CMP1 G1CMP2 G1CMP3 G1MSK0 G1MSK1 Value after RESET XX16 XX16 0016 X000 000X2 0016 0016 0016 0016 XXXX XXXX2 X000 XXXX2 XX16 XX16 0016 XX16 0000 X0112 XX16 XX16 XX16 XX16 XX16 XX16 Base Timer Control Register 10 Base Timer Control Register 11 Time Measurement Prescaler Register 16 Time Measurement Prescaler Register 17 Function Enable Register 1 Function Select Register 1 SI/O Receive Buffer Register 1 Transmit Buffer/Receive Data Register 1 Receive Input Register 1 SI/O Communication Mode Register 1 Transmit Output Register 1 SI/O Communication Control Register 1 Data Compare Register 10 Data Compare Register 11 Data Compare Register 12 Data Compare Register 13 Data Mask Register 10 Data Mask Register 11 XX16 Receive CRC Code Register 1 Transmit CRC Code Register 1 SI/O Extended Mode Register 1 SI/O Extended Receive Control Register 1 SI/O Special Communication Interrupt Detect Register 1 SI/O Extended Transmit Control Register 1 G1RCRC G1TCRC G1EMR G1ERC G1IRF G1ETC XX16 0016 0016 0016 0016 0016 0000 0XXX2 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 29 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address Register 015016 015116 015216 015316 015416 015516 015616 015716 015816 015916 015A16 015B16 015C16 015D16 015E16 015F16 016016 016116 016216 016316 016416 016516 016616 016716 016816 016916 016A16 016B16 016C16 016D16 016E16 016F16 017016 017116 017216 017316 017416 017516 017616 017716 017816 Input Function Select Register 017916 Input Function Select Register A 017A16 017B16 017C16 017D16 to 01DF16 Symbol Value after RESET IPS IPSA 0016 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 30 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 01E016 01E116 01E216 01E316 01E416 01E516 01E616 01E716 01E816 01E916 01EA16 01EB16 01EC16 01ED16 01EE16 01EF16 01F016 01F116 01F216 01F316 01F416 01F516 01F616 01F716 01F816 01F916 01FA16 01FB16 01FC16 01FD16 01FE16 01FF16 020016 020116 020216 020316 020416 020516 020616 020716 020816 020916 020A16 020B16 020C16 020D16 020E16 020F16 Register CAN0 Message Slot Buffer 0 Standard ID0 CAN0 Message Slot Buffer 0 Standard ID1 CAN0 Message Slot Buffer 0 Extended ID0 CAN0 Message Slot Buffer 0 Extended ID1 CAN0 Message Slot Buffer 0 Extended ID2 CAN0 Message Slot Buffer 0 Data Length Code CAN0 Message Slot Buffer 0 Data 0 CAN0 Message Slot Buffer 0 Data 1 CAN0 Message Slot Buffer 0 Data 2 CAN0 Message Slot Buffer 0 Data 3 CAN0 Message Slot Buffer 0 Data 4 CAN0 Message Slot Buffer 0 Data 5 CAN0 Message Slot Buffer 0 Data 6 CAN0 Message Slot Buffer 0 Data 7 CAN0 Message Slot Buffer 0 Time Stamp High-Order CAN0 Message Slot Buffer 0 Time Stamp Low-Order CAN0 Message Slot Buffer 1 Standard ID0 CAN0 Message Slot Buffer 1 Standard ID1 CAN0 Message Slot Buffer 1 Extended ID0 CAN0 Message Slot Buffer 1 Extended ID1 CAN0 Message Slot Buffer 1 Extended ID2 CAN0 Message Slot Buffer 1 Data Length Code CAN0 Message Slot Buffer 1 Data 0 CAN0 Message Slot Buffer 1 Data 1 CAN0 Message Slot Buffer 1 Data 2 CAN0 Message Slot Buffer 1 Data 3 CAN0 Message Slot Buffer 1 Data 4 CAN0 Message Slot Buffer 1 Data 5 CAN0 Message Slot Buffer 1 Data 6 CAN0 Message Slot Buffer 1 Data 7 CAN0 Message Slot Buffer 1 Time Stamp High-Order CAN0 Message Slot Buffer 1 Time Stamp Low-Order CAN0 Control Register 0 CAN0 Status Register CAN0 Extended ID Register CAN0 Configuration Register CAN0 Time Stamp Register CAN0 Transmit Error Count Register CAN0 Receive Error Count Register CAN0 Slot Interrupt Status Register Symbol C0SLOT0_0 C0SLOT0_1 C0SLOT0_2 C0SLOT0_3 C0SLOT0_4 C0SLOT0_5 C0SLOT0_6 C0SLOT0_7 C0SLOT0_8 C0SLOT0_9 C0SLOT0_10 C0SLOT0_11 C0SLOT0_12 C0SLOT0_13 C0SLOT0_14 C0SLOT0_15 C0SLOT1_0 C0SLOT1_1 C0SLOT1_2 C0SLOT1_3 C0SLOT1_4 C0SLOT1_5 C0SLOT1_6 C0SLOT1_7 C0SLOT1_8 C0SLOT1_9 C0SLOT1_10 C0SLOT1_11 C0SLOT1_12 C0SLOT1_13 C0SLOT1_14 C0SLOT1_15 C0CTLR0 C0STR C0IDR C0CONR C0TSR C0TEC C0REC C0SISTR Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX01 0X012(1) XXXX 00002(1) 0000 00002(1) X000 0X012(1) 0016(1) 0016(1) 0000 XXXX2(1) 0000 00002(1) 0016(1) 0016(1) 0016(1) 0016(1) 0016(1) 0016(1) X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 31 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 021016 021116 021216 021316 021416 021516 021616 021716 021816 021916 021A16 021B16 021C16 021D16 021E16 021F16 022016 022116 022216 022316 022416 022516 022616 022716 022816 022916 022A16 022B16 022C16 022D16 022E16 022F16 023016 023116 023216 023316 023416 023516 023616 023716 023816 Register CAN0 Slot Interrupt Mask Register Symbol C0SIMKR Value after RESET 0016(2) 0016(2) CAN0 Error Interrupt Mask Register CAN0 Error Interrupt Status Register CAN0 Error Cause Register CAN0 Baud Rate Prescaler CAN0 Mode Register C0EIMKR C0EISTR C0EFR C0BRP C0MDR XXXX X0002(2) XXXX X0002(2) 0016(2) 0000 00012(2) XXXX XX002(2) CAN0 Single-Shot Control Register C0SSCTLR 0016(2) 0016(2) CAN0 Single-Shot Status Register C0SSSTR 0016(2) 0016(2) CAN0 Global Mask Register Standard ID0 CAN0 Global Mask Register Standard ID1 CAN0 Global Mask Register Extended ID0 CAN0 Global Mask Register Extended ID1 CAN0 Global Mask Register Extended ID2 C0GMR0 C0GMR1 C0GMR2 C0GMR3 C0GMR4 XXX0 00002(2) XX00 00002(2) XXXX 00002(2) 0016(2) XX00 00002(2) (Note 1) CAN0 Message Slot 0 Control Register / CAN0 Local Mask Register A Standard ID0 CAN0 Message Slot 1 Control Register / CAN0 Local Mask Register A Standard ID1 CAN0 Message Slot 2 Control Register / CAN0 Local Mask Register A Extended ID0 CAN0 Message Slot 3 Control Register / CAN0 local Mask Register A Extended ID1 CAN0 Message Slot 4 Control Register / CAN0 Local Mask Register A Extended ID2 CAN0 Message Slot 5 Control Register CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register CAN0 Message Slot 8 Control Register / CAN0 Local Mask Register B Standard ID0 C0MCTL0/ C0LMAR0 C0MCTL1/ C0LMAR1 C0MCTL2/ C0LMAR2 C0MCTL3/ C0LMAR3 C0MCTL4/ C0LMAR4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8/ C0LMBR0 0000 00002(2) XXX0 00002(2) 0000 0000 2(2) XX00 00002(2) 0000 00002(2) XXXX 00002(2) 0016(2) 0016(2) 0000 0000 2(2) XX00 00002(2) 0016(2) 0016(2) 0016(2) 0000 0000 2(2) XXX0 00002(2) X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 32 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 023916 023A16 023B16 023C16 023D16 023E16 023F16 024016 024116 024216 024316 024416 024516 024616 024716 024816 024916 024A16 024B16 024C16 024D16 024E16 024F16 025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025C16 025D16 to 02BF16 Register CAN0 Message Slot 9 Control Register / CAN0 Local Mask Register B Standard ID1 CAN0 Message Slot 10 Control Register / CAN0 Local Mask Register B Extended ID0 CAN0 Message Slot 11 Control Register / CAN0 Local Mask Register B Extended ID1 CAN0 Message Slot 12 Control Register / CAN0 Local Mask Register B Extended ID2 CAN0 Message Slot 13 Control Register CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register CAN0 Slot Buffer Select Register CAN0 Control Register 1 CAN0 Sleep Control Register Symbol C0MCTL9/ C0LMBR1 C0MCTL10/ C0LMBR2 C0MCTL11/ C0LMBR3 C0MCTL12/ C0LMBR4 C0MCTL13 C0MCTL14 C0MCTL15 C0SBS C0CTLR1 C0SLPR Value after RESET 0000 00002(2) XX00 00002(2) 0000 00002(2) XXXX 00002(2) 0016(2) 0016(2) 0000 00002(2) XX00 00002(2) 0016(2) 0016(2) 0016(2) 0016(2) X000 00XX2(2) XXXX XXX02 0016(2) 0116(2) (Note 1) CAN0 Acceptance Filter Support Register C0AFS X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and supplying the clock to the CAN module. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 33 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 02C016 02C116 02C216 02C316 02C416 02C516 02C616 02C716 02C816 02C916 02CA16 02CB16 02CC16 02CD16 02CE16 02CF16 02D016 02D116 02D216 02D316 02D416 02D516 02D616 02D716 02D816 02D916 02DA16 02DB16 02DC16 02DD16 02DE16 02DF16 02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16 02EB16 02EC16 02ED16 02EE16 02EF16 X0 Register Y0 Register X1 Register Y1 Register X2 Register Y2 Register X3 Register Y3 Register X4 Register Y4 Register X5 Register Y5 Register X6 Register Y6 Register X7 Register Y7 Register X8 Register Y8 Register X9 Register Y9 Register Register Symbol X0R,Y0R X1R,Y1R X2R,Y2R X3R,Y3R X4R,Y4R X5R,Y5R X6R,Y6R X7R,Y7R X8R,Y8R X9R,Y9R X10R,Y10R X11R,Y11R X12R,Y12R X13R,Y13R X14R,Y14R X15R,Y15R XYC Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XXXX XX002 X10 Register Y10 Register X11 Register Y11 Register X12 Register Y12 Register X13 Register Y13 Register X14 Register Y14 Register X15 Register Y15 Register X/Y Control Register UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB 0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 34 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 02F016 02F116 02F216 02F316 02F416 02F516 02F616 02F716 02F816 02F916 02FA16 02FB16 02FC16 02FD16 02FE16 02FF16 030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 Register Symbol Value after RESET UART4 Special Mode Register 4 UART4 Special Mode Register 3 UART4 Special Mode Register 2 UART4 Special Mode Register UART4 Transmit/Receive Mode Register UART4 Bit Rate Register UART4 Transmit Buffer Register UART4 Transmit/Receive Control Register 0 UART4 Transmit/Receive Control Register 1 UART4 Receive Buffer Register Timer B3, B4, B5 Count Start Flag U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR 0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 000X XXXX2 XX16 Timer A1-1 Register Timer A2-1 Register Timer A4-1 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 XX16 XX16 XX16 XX16 XX16 0016 0016 XX11 11112 XX11 11112 XX16 XX16 XX16 Timer B3 Register Timer B4 Register Timer B5 Register TB3 TB4 TB5 XX16 XX16 XX16 XX16 XX16 Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register External Interrupt Cause Select Register TB3MR TB4MR TB5MR IFSR 00XX 00002 00XX 00002 00XX 00002 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 35 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address Register 032016 032116 032216 032316 032416 UART3 Special Mode Register 4 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16 034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 UART3 Special Mode Register 3 UART3 Special Mode Register 2 UART3 Special Mode Register UART3 Transmit/Receive Mode Register UART3 Bit Rate Register UART3 Transmit Buffer Register UART3 Transmit/Receive Control Register 0 UART3 Transmit/Receive Control Register 1 UART3 Receive Buffer Register Symbol Value after RESET U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB 0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register Count Start Flag Clock Prescaler Reset Flag One-Shot Start Flag Trigger Select Register Up/Down Flag U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF 0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 0016 0XXX XXXX2 0016 0016 0016 XX16 Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register TA0 TA1 TA2 TA3 TA4 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 36 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address Register 035016 Timer B0 Register 035116 035216 Timer B1 Register 035316 035416 Timer B2 Register 035516 035616 Timer A0 Mode Register 035716 Timer A1 Mode Register 035816 Timer A2 Mode Register 035916 Timer A3 Mode Register 035A16 Timer A4 Mode Register 035B16 Timer B0 Mode Register 035C16 Timer B1 Mode Register 035D16 Timer B2 Mode Register 035E16 Timer B2 Special Mode Register 035F16 Count Source Prescaler Register(1) 036016 036116 036216 036316 036416 UART0 Special Mode Register 4 036516 UART0 Special Mode Register 3 036616 UART0 Special Mode Register 2 036716 UART0 Special Mode Register 036816 UART0 Transmit/Receive Mode Register 036916 UART0 Bit Rate Register 036A16 UART0 Transmit Buffer Register 036B16 036C16 UART0 Transmit/Receive Control Register 0 036D16 UART0 Transmit/Receive Control Register 1 036E16 UART0 Receive Buffer Register 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 DMA0 Request Source Select Register 037916 DMA1 Request Source Select Register 037A16 DMA2 Request Source Select Register 037B16 DMA3 Request Source Select Register 037C16 CRC Data Register 037D16 037E16 CRC Input Register 037F16 Symbol TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR Value after RESET XX16 XX16 XX16 XX16 XX16 XX16 0016 0016 0016 0016 0016 00XX 00002 00XX 00002 00XX 00002 XXXX XXX02 0XXX 00002 U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB 0016 0016 0016 0016 0016 XX16 XX16 XX16 0000 10002 0000 00102 XX16 XX16 DM0SL DM1SL DM2SL DM3SL CRCD CRCIN 0X00 00002 0X00 00002 0X00 00002 0X00 00002 XX16 XX16 XX16 X: Indeterminate Blank spaces are reserved. No access is allowed. NOTES: 1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 37 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 Register A/D0 Register 0 A/D0 Register 1 A/D0 Register 2 A/D0 Register 3 A/D0 Register 4 A/D0 Register 5 A/D0 Register 6 A/D0 Register 7 Symbol AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 Value after RESET XXXX XXXX2 0000 00002 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 XX16 A/D0 Control Register 4 A/D0 Control Register 2 A/D0 Control Register 3 A/D0 Control Register 0 A/D0 Control Register 1 D/A Register 0 D/A Register 1 D/A Control Register AD0CON4 AD0CON2 AD0CON3 AD0CON0 AD0CON1 DA0 DA1 DACON XXXX 00XX2 XX0X X0002 XXXX X0002 0016 0016 XX16 XX16 XXXX XX002 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 38 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 Register Function Select Register A8 Function Select Register A9 Symbol PS8 PS9 Value after RESET X000 00002 0016 Function Select Register D1 PSD1 X0XX XX002 Function Select Register C2 Function Select Register C3 Function Select Register C Function Select Register A0 Function Select Register A1 Function Select Register B0 Function Select Register B1 Function Select Register A2 Function Select Register A3 Function Select Register B2 Function Select Register B3 Function Select Register A5 PSC2 PSC3 PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3 PS5 XXXX X00X2 X0XX XXXX2 00X0 00002 0016 0016 0016 0016 00X0 00002 0016 00X0 00002 0016 XXX0 00002 Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register Port P10 Direction Register Port P11 Direction Register Port P12 Register Port P13 Register Port P12 Direction Register Port P13 Direction Register P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 XX16 XX16 0016 0016 XX16 XX16 00X0 00002 0016 XX16 XX16 0016 XXX0 00002 XX16 XX16 0016 0016 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 39 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Register Port P14 Register Port P15 Register Port P14 Direction Register Port P15 Direction Register Symbol P14 P15 PD14 PD15 Value after RESET XX16 XX16 X000 00002 0016 Pull-Up Control Register 2 Pull-Up Control Register 3 Pull-Up Control Register 4 PUR2 PUR3 PUR4 0016 0016 XXXX 00002 Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016 Pull-Up Control Register 0 Pull-Up Control Register 1 PUR0 PUR1 0016 XXXX 00002 Port Control Register PCR XXXX XXX02 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 40 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16 03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 Register Symbol Value after RESET Function Select Register D1 PSD1 X0XX XX002 Function Select Register C2 Function Select Register C3 Function Select Register C Function Select Register A0 Function Select Register A1 Function Select Register B0 Function Select Register B1 Function Select Register A2 Function Select Register A3 Function Select Register B2 Function Select Register B3 PSC2 PSC3 PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3 XXXX X00X2 X0XX XXXX2 00X0 00002 0016 0016 0016 0016 00X0 00002 0016 00X0 00002 0016 Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P10 Direction Register Set default value to "FF16" P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10 XX16 XX16 0016 0016 XX16 XX16 00X0 00002 0016 XX16 0016 Set default value to "FF16" Set default value to "FF16" X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 41 of 495 M32C/84 Group (M32C/84, M32C/84T) 4. Special Function Registers (SFR) Address 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16 Register Symbol Value after RESET Set default value to "FF16" Set default value to "FF16" Pull-Up Control Register 2 Pull-Up Control Register 3 Set default value to "0016" PUR2 PUR3 0016 0016 Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5 XX16 XX16 0016 0016 XX16 XX16 0016 0016 XX16 XX16 0016 0016 Pull-up Control Register 0 Pull-up Control Register 1 PUR0 PUR1 0016 XXXX 00002 Port Control Register PCR XXXX XXX02 X: Indeterminate Blank spaces are reserved. No access is allowed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 42 of 495 M32C/84 Group (M32C/84, M32C/84T) 5. Reset 5. Reset Hardware reset 1, brown-out detection reset (hardware reset 2), software reset and watchdog timer reset are available to reset the microcomputer. 5.1 Hardware Reset 1 ____________ Pins, the CPU and SFR are reset by setting the RESET pin. If the supply voltage meets the recommended ___________ operating conditions, all pins are reset when a low-level ("L") signal is applied to the RESET pin (see Table 5.1). The oscillation circuit is also reset and the main clock starts oscillating. The CPU and SFR are reset ____________ when the signal applied to the RESET pin changes "L" to high level ("H"). The microcomputer executes the program in an address indicated by the reset vector. The internal RAM is not reset. When an "L" signal is ____________ applied to the RESET pin while writing data to the internal RAM, the internal RAM is in an indeterminate state. Figure 5.1 shows an example of the reset circuit. Figure 5.2 shows a reset sequence. Table 5.1 lists pin ____________ states while the RESET pin is held "L". 5.1.1 Reset on a Stable Supply Voltage ____________ (1) Apply an "L" signal to the RESET pin (2) Provide 20 or more clock cycle inputs into the XIN pin ____________ (3) Apply an "H" signal to the RESET pin 5.1.2 Power-on Reset ____________ (1) Apply an "L" signal to the RESET pin (2) Raise the supply voltage to the recommended operating level (3) Insert td(P-R) ms as wait time for the internal voltage to stabilize (4) Provide 20 or more clock cycle inputs into the XIN pin ____________ (5) Apply an "H" signal to the RESET pin Recommended operating voltage VCC1 0V RESET VCC1 RESET 0V td(P-R) + 20 or more clock cycle inputs provided into the XIN pin NOTES: 1. If VCC1>VCC2, the VCC2 voltage must be lower than that of VCC1 when the power is being turned on or off. The supply voltage of M32C/84T must be VCC1=VCC2. 0.2VCC1 or below 0.2VCC1 or below Figure 5.1 Reset Circuit Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 43 of 495 M32C/84 Group (M32C/84, M32C/84T) 5. Reset VCC1, VCC2(2) XIN XIN td(P-R) ms or more is equired 20 or more cycles are required RESET 168 to 173 BCLK cycles (Flash Memory Version) 40 to 45 BCLK cycles (Mask ROM Version) BCLK Microprocessor Mode BYTE="H" (3) Content of reset vector Address A23 RD WR Microprocessor Mode (3) BYTE="L" FFFFFC16 FFFFFD16 FFFFFE16 FFFFFF16 Content of reset vector Address A23 RD WR FFFFFC16 FFFFFE16 Single-Chip Mode (1) FFFFFC16 Content of reset vector Address FFFFFE16 NOTES: 1. Address data is not output from pins in single-chip mode. 2. The supply voltage of M32C/84T must be VCC1=VCC2. 3. M32C/84T cannot be used in memory expansion mode and microprocessor mode. Figure 5.2 Reset Sequence Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 44 of 495 M32C/84 Group (M32C/84, M32C/84T) ____________ 5. Reset Table 5.1 Pin States while RESET Pin is Held "L" Pin States(2) Pin Name P0 P1 P2, P3, P4 P50 P51 P52 P53 P54 CNVSS=VSS Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) CNVSS=VCC BYTE=VSS BYTE=VCC Inputs data (high-impedance) Inputs data (high-impedance) Input port (high-impedance) Output addresses (indeterminate) ______ Outputs the WR signal ("H")(3) ________ Outputs the BHE signal (indeterminate) _____ Outputs the RD signal ("H")(3) Outputs the BCLK(3) _________ Outputs the HLDA signal (Output signal depends on an input __________ signal to the HOLD pin.)(3) __________ Inputs the HOLD signal (high-impedance) Outputs an "H" signal(3) ________ Inputs the RDY signal (high-impedance) Input port (high-impedance) P55 Input port (high-impedance) P56 Input port (high-impedance) P57 Input port (high-impedance) P6 to P15(1) Input port (high-impedance) NOTES: 1. Ports P11 to P15 are provided in the 144-pin package only. 2. The availability of pull-up resistors is indeterminate until internal supply voltage stabilizes. 3. Each port is in this state after power is on and internal supply voltage stabilizes, but in an indeterminate state until internal supply voltage stabilizes. 5.2 Brown-Out Detection Reset (Hardware Reset 2) Pins, the CPU and SFR are reset by using the built-in voltage detection circuit, which monitors the voltage applied to the VCC1 pin. When the VC26 bit in the VCR2 register is set to "1" (reset level detection circuit enabled), pins, the CPU and SFR are reset as soon as the voltage applied to the VCC1 pin drops to Vdet3 or below. Then, pins, the CPU and SFR are reset as soon as the voltage applied to the VCC1 pin reaches Vdet3r or above. The microcomputer executes the program in an address determined by the reset vector. The microcomputer executes the program after detecting Vdet3r and waiting td(S-R) ms . The same pins and registers are reset by the hardware reset 1 and brown-out detection reset, and are also placed in the same reset state. The microcomputer cannot exit stop mode by brown-out detection reset. Figure 5.3 shows an example of brown-out detection reset operation. NOTES: 1. Brown-out detection reset cannot be used in M32C/84T. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 45 of 495 M32C/84 Group (M32C/84, M32C/84T) 5. Reset When Stop Mode is not Used 5.0V VCC1 Vdet4 Vdet3r Vdet3 Vdet3s VSS RESET Internal Reset Signal 5.0V VC13 Bit Indeterminate Set to "1" by program (reset level detection circuit enabled) VC26 Bit Indeterminate Set to "1" by program (low voltage detection circuit enabled) VC27 Bit Indeterminate Figure 5.3 Brown-out Detection Reset (Hardware Reset 2) 5.3 Software Reset Pins, the CPU and SFR are reset when the PM03 bit in the PM0 register is set to "1" (microcomputer reset). Then the microcomputer executes the program in an address determined by the reset vector. Set the PM03 bit to "1" while the main clock is selected as the CPU clock and the main clock oscillation is stable. In the software reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR for details. Processor mode remains unchanged since the PM01 and PM00 bits in the PM0 register are not reset. 5.4 Watchdog Timer Reset Pins, the CPU and SFR are reset when the CM06 bit in the CM0 register is set to "1" (reset) and the watchdog timer underflows. Then the microcomputer executes the program in an address determined by the reset vector. In the watchdog timer reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR for details. Processor mode remains unchanged since the PM01 and PM00 bits in the PM0 register are not reset. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 46 of 495 M32C/84 Group (M32C/84, M32C/84T) 5. Reset 5.5 Internal Space Figure 5.4 shows CPU register states after reset. Refer to 4. SFR for SFR states after reset. 0 : "0" after reset X : Indeterminate after reset General Registers b15 b0 High-Speed Interrupt Registers b15 b0 Flag Register (FLG) b15 b8 b7 b0 b23 XXXX16 XXXXXX16 XXXXXX16 Flag Save Register (SVF) PC Save Register (SVP) Vector Register (VCT) X000XXXX00000000 IPL U I OBSZDC b0 DMAC-Associated Registers b7 b0 0016 0016 000016 b23 0016 0016 Data Register (R0H/R0L) Data Register (R1H/R1L) Data Register (R2) Data Register (R3) Address Register (A0) Address Register (A1) Static Base Register (SB) Frame Base Register (FB) User Stack Pointer (USP) Interrupt Stack Pointer (ISP) Interrupt Table Register (INTB) Program Counter (PC) b23 b15 0016 0016 XXXX16 XXXX16 XXXX16 XXXX16 XXXXXX16 XXXXXX16 XXXXXX16 XXXXXX16 XXXXXX16 XXXXXX16 DMA Mode Register (DMD0) DMA Mode Register (DMD1) DMA Transfer Count Register (DCT0) DMA Transfer Count Register (DCT1) DMA Transfer Count Reload Register (DRC0) DMA Transfer Count Reload Register (DRC1) DMA Memory Address Register (DMA0) DMA Memory Address Register (DMA1) DMA Memory Address Reload Register (DRA0) DMA Memory Address Reload Register (DRA1) DMA SFR Address Register (DSA0) DMA SFR Address Register (DSA1) 000016 00000016 00000016 00000016 00000016 00000016 00000016 00000016 Contents of addresses FFFFFE16 to FFFFFC16 Figure 5.4 CPU Register States after Reset Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 47 of 495 M32C/84 Group (M32C/84, M32C/84T) 6. Voltage Detection Circuit 6. Voltage Detection Circuit NOTE The voltage detection circuit in M32C/84T cannot be used. However, the cold start-up/warm start-up determine function is available. The voltage detection circuit consists of the reset level detection circuit and the low voltage detection circuit. The reset level detection circuit monitors the voltage applied to the VCC1 pin. The microcomputer is reset if the reset level detection circuit detects VCC1 is Vdet3 or below. This circuit is disabled when the microcomputer is in stop mode. The voltage detection circuit also monitors the voltage applied to the VCC1 pin. The low voltage detection signal is generated when the low voltage detection circuit detects VCC1 is above or below Vdet4. This signal generates the low voltage detection interrupt. The VC13 bit in the VCR1 register determines whether VCC1 is above or below Vdet4. The voltage detection circuit is available when VCC1=4.2V to 5.5V. Figure 6.1 shows a block diagram of the voltage detection circuit. VCR2 Register RESET b7 b6 1 shot Reset Level Detection Circuit + ≥Vdet3 CM10 Bit=1 (Stop Mode) E Internal Reset Signal ("L" active) >T Q Wait Time to Release Brown-out Detection Reset td(S-R) VCC1 + ≥Vdet4 E Low Voltage Detection Circuit Noise Rejection Low Voltage Detection Signal VCR1 Register b3 VC13 Bit Figure 6.1 Voltage Detection Circuit Block Diagram Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 48 of 495 M32C/84 Group (M32C/84, M32C/84T) 6. Voltage Detection Circuit Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol WDC Address 000F16 After Reset 000X XXXX2 Bit Symbol (b4 - b0) WDC5 Bit Name High-Order Bit of the Watchdog Timer Cold Start-up/ Warm Start-up Determine Flag(1,2, 3) Reserved Bit Function RW RO 0 : Cold start-up 1 : Warm start-up Set to "0" 0 : Divide-by-16 1 : Divide-by-128 RW (b6) WDC7 RW Prescaler Select Bit RW NOTES: 1. The WDC5 bit remains set to "1", regardless of setting to "1" or "0". 2. The WDC5 bit is set to "0" when power is turned on and can be set to "1" by program only. 3. The WDC5 bit maintains a value set before reset, even after reset has been performed. Figure 6.2 WDC Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 49 of 495 M32C/84 Group (M32C/84, M32C/84T) 6. Voltage Detection Circuit Voltage Detection Register 1(2) b7 b6 b5 b4 b3 b2 b1 b0 0000 000 Symbol VCR1 Address 001B16 After Reset 0000 10002 Bit Symbol Bit Name Reserved Bit Set to "0" Function RW RW (b2 - b0) VC13 Low Voltage Monitor Flag(1) Reserved Bit (b7 - b4) NOTES: 1. The VC13 bit setting is enabled when the VC27 bit in the VCR2 register is set to "1" (low voltage detection circuit enabled). The VC13 bit is set to "1" when the VC27 bit is set to "0" (low voltage detection circuit disabled). 2. The VCR1 register in M32C/84T cannot be used. 0 : VCC1 < Vdet4 1 : VCC1 ≥ Vdet4 Set to "0" RO RW Voltage Detection Register 2(1, 5) b7 b6 b5 b4 b3 b2 b1 b0 000000 Symbol VCR2 Address 001716 After Reset 0016(2) Bit Symbol (b5 - b0) VC26 Bit Name Reserved Bit Reset Level Monitor Bit(2, 4, 6) Low Voltage Monitor Bit(3, 4) Set to "0" Function RW RW 0 : Disables reset level detection circuit RW 1 : Enables reset level detection circuit 0 : Disables low voltage detection circuit 1 : Enables low voltage detection circuit VC27 RW NOTES: 1. Set the VCR2 register after the PRC3 bit in the PRCR register is set to "1" (write enable). 2. To use the brown-out detection reset (hardware reset 2), set the VC26 bit to "1". 3. Set the VC27 bit to "1" to set the VC13 bit in the VCR1 register and the D42 bit in the D4INT register, or to set the D40 bit to "1" (low voltage detect interrupt enabled). 4. The reset level detection circuit and low voltage detection circuit start operating td(E-A) ms after the VC26 or VC27 bit is set to "1". 5. The VCR2 register in M32C/85T cannot be used. 6. The VC26 bit setting is disabled when the microcomputer is in stop mode. Its setting is not reset even if the voltage applied to the VCC1 pin drops below Vdet3. Figure 6.3 VCR1 and VCR2 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 50 of 495 M32C/84 Group (M32C/84, M32C/84T) 6. Voltage Detection Circuit Low Voltage Detection Interrupt Register(1,6) b7 b6 b5 b4 b3 b2 b1 b0 Symbol D4INT Address 002F16 After Reset 0016 Bit Symbol D40 Bit Name Low Voltage Detection Interrupt Enable Bit(2) Function 0: Disables the interrupt 1: Enables the interrupt RW RW D41 Stop/Wait Mode Deactivation Control Bit(3) 0: Disabled (cannot use the low voltage detection interrupt to exit stop/wait mode) RW 1: Enabled (can use the low voltage detection interrupt to exit stop/wait mode) 0: Not detected 1: Detects above or below Vdet4 0: Not detected 1: Detected b5 b4 D42 Voltage Change Detect Flag(4, 5) WDT Overflow Detect Flag(5) RW D43 RW DF0 Sampling Clock Select Bit DF1 0 0 : CPU clock divided by 8 0 1 : CPU clock divided by 16 1 0 : CPU clock divided by 32 1 1 : CPU clock divided by 64 When read, its content is indeterminate RW RW (b7 - b6) Reserved Bit RO NOTES: 1. Set the D4INT registers after the PRC3 bit in the PRCR register is set to "1" (write enable). 2. The D40 bit setting is enabled when the VC27 bit in the VCR2 register is set to "1" (low voltage detection circuit enabled). Use the following procedure to set the D40 bit to "1": (1) Set the VC27 bit to "1" (2) Wait td(E-A) ms to start operating the voltage detection circuit (3) Wait required sampling time (see Table 6.2) (4) Set the D40 bit to "1" 3. When exiting stop mode using the low voltage detection circuit again after having already done so, set the D41 bit to "1" after setting it to "0". 4. The D42 bit setting is enabled when the VC27 bit in the VCR2 register is set to "1" (low voltage detection circuit enabled). The D42 bit is set to "0" when the VC27 bit is set to "0" (low voltage detection circuit disabled). 5. The bit is set to "0" by a program. (It remains unchanged even if it is set to "1".) 6. The D4INT register in M32C/84T cannot be used. Figure 6.4 D4INT Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 51 of 495 M32C/84 Group (M32C/84, M32C/84T) 6. Voltage Detection Circuit 6.1 Low Voltage Detection Interrupt If the D40 bit in the D4INT register is set to "1" (low voltage detection interrupt enabled), low voltage detection interrupt request is generated when the voltage applied to the VCC1 pin rises above or drops below Vdet4. The low voltage detection interrupt shares the same interrupt vector with the watchdog timer interrupt and oscillation stop detection interrupt. The D42 bit in the D4INT register determines whether the low voltage detection interrupt has been generated. Read the D42 bit using an interrupt routine when using the low voltage detection interrupt at the same time as the watchdog timer interrupt and oscillation stop detection interrupt. Set the D41 bit in the D4INT register to "1" (enabled) to use the low voltage detection interrupt to exit stop mode or wait mode. The D42 bit is set to "1" (more or less than Vdet4 detected) as soon as the voltage applied to the VCC1 pin reaches Vdet4 due to the voltage rise and voltage drop. When the D42 bit setting changes "0" to "1", low voltage detection interrupt request is generated. Set the D42 bit to "0" (not detected) by program. However, when the D41 bit is set to "1" and the microcomputer is in stop mode or wait mode, low voltage detection interrupt request is generated, regardless of the D42 bit setting, if the voltage applied to the VCC1 pin is detected to be higher than Vdet4. The microcomputer then exits stop mode or wait mode. Table 6.1 shows how a low voltage detection interrupt request is generated. The DF1 and DF0 bits in the D4INT register determine sampling period that detects the voltage applied to the VCC1 pin rises above or drops below Vdet4. Table 6.2 shows the sampling periods. Table 6.1 Conditions to Generate Low Voltage Detection Interrupt Request Operating Mode Normal Operating Mode(1) Wait Mode( 2 ) , Stop Mode( 2 ) VC27 Bit D40 Bit D41 Bit D42 Bit( 4 ) VC13 Bit( 3 ) "0" to"1" "0" or "1" 1 1 1 "0" to"1" "1" to"0" "0" to"1" - : "0" or "1" NOTES: 1. All states excluding wait mode and stop mode are handled as normal operating mode. (Refer to 9. Clock Generation Circuit.) 2. Refer to 6.1.1 Limitations for Exiting Stop/Wait Mode. 3. Sampling begins after the VC13 bit setting changes. An interrupt request is generated after sampling is completed. See Figure 6.6 for details. 4. Set to "0" by program before generating an interrupt. Table 6.2 Sampling Periods CPU Clock (MHz) 16 32 Sampling Clock (µs) Divide-by-8 3.0 1.5 Divide-by-16 6.0 3.0 Divide-by-32 12.0 6.0 Divide-by-64 24.0 12.0 Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 52 of 495 M32C/84 Group (M32C/84, M32C/84T) 6. Voltage Detection Circuit Low Voltage Detection Interrupt Generation Circuit DF1, DF0 Low Voltage Detection Circuit VC27 bit CPU 1/8 Clock VC13 VCC1 + VREF Noise Rejection Low Voltage Detection Signal(1) Noise Rejection Circuit D41 CM10 WAIT Instruction (Wait Mode) Digital Filter 1/2 1/2 002 012 102 1/2 112 D42(2) Watchdog Timer Interrupt Signal Low Voltage Detection Interrupt Signal Oscillation Stop Detection Interrupt Signal D40 D43(3) (Rejection Range:200 ns) NonMaskable Interrupt Signal Watchdog Timer Underflow Signal from the Watchdog Timer NOTES: 1. Low voltage detection signal becomes "H" when the VC27 bit in the VCR2 register is set to "0" (disabled). 2. The D42 bit in the D4INT register is set to "0" (not detected) by program. The D42 bit is set to "0" when the VC27 bit is set to "0" (low voltage detection circuit disabled). 3. The D43 bit is set to “0”(not detected) by program. Figure 6.5 Low Voltage Detection Interrupt Generation Circuit VCC1 VC13 Bit Sampling Sampling Sampling No low voltage detection interrupt signal is output when the D42 bit is set to "1". Digital Filter(2) Sampling D42 Bit Set to "0" (not detected) by program Low Voltage Detection Interrupt Signal NOTES: 1. This example applies to an operation of the low voltage detection interrupt generation circuit when the D40 bit in the D4INT register is set to "1" (low voltage detection interrupt enabled). 2. Output from the digital filter shown in Figure 6.5. Figure 6.6 Low Voltage Detection Interrupt Generation Circuit Operation Example Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 53 of 495 M32C/84 Group (M32C/84, M32C/84T) 6. Voltage Detection Circuit 6.1.1 Limitations on Exiting Stop/Wait Mode The low voltage detection interrupt is generated and the microcomputer exits stop mode as soon as the CM10 bit in the CM1 register is set to "1" (all clocks stopped) under the conditions below. Additionally, if WAIT instruction is executed under these same conditions, the low voltage detection interrupt is immediately generated and the microcomputer exits wait mode. - the VC27 bit in the VCR2 register is set to "1" (low voltage detection circuit enabled), - the D40 bit in the D4INT register is set to "1" (low voltage detection interrupt enabled), - the D41 bit in the D4INT register is set to "1" (low voltage detection interrupt is used to exit stop/wait mode), and - the voltage applied to the VCC1 pin is higher than Vdet4 (the VC13 bit in the VCR1 register is set to "1") Set the CM10 bit to "1" when the VC13 bit is "0" (VCC1 < Vdet4), if the microcomputer is set to enter stop/ wait mode when the voltage applied to the VCC1 pin drops below Vdet4 and to exit stop/wait mode when the voltage applied rises to Vdet4 or above. 6.2 Cold Start-up / Warm Start-up Determine Function The WDC5 bit in the WDC register determines either cold start-up, power-on reset, or warm start-up, reset during the microcomputer running. Default value of the WDC5 bit is "0" (cold start-up) when power-on. It is set to "1" (warm start-up) by writing desired values to the WDC register. The WDC5 bit is not reset, regardless of a software reset or reset signal input. Figure 6.7 shows a block diagram of the cold start-up/warm start-up determine function. Figure 6.8 shows its operation exmaple. WDC5 Bit Write to WDC register S Q COLD/WARM (Cold Start-up/Warm Start-up) Hardware Reset 1 when Power-on R Figure 6.7 Cold Start-up/Warm Start-up Determine Function Block Diagram 5V VCC1 0V 5V RESET 0V T1 Pch transistor ON (Approx. 4V) CPU reset release Set to "1" by program T > 100µs No change even if the voltage applied to RESET is 0V. "1" T2 WDC5 Bit "0" Program running started Reset Sequence (Approx. 20µs @16MHz) The WDC5 bit is set to "0" as soon as enough voltage is applied to VCC1. NOTES: 1. Time difference between T1 and T2 may affect the WDC5 bit setting period. Figure 6.8 Cold Start-up/Warm Start-up Determine Function Operation Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 54 of 495 M32C/84 Group (M32C/84, M32C/84T) 7. Processor Mode 7. Processor Mode NOTE Use M32C/84T in single-chip mode only. M32C/84T cannot be used in memory expansion mode and microprocessor mode. 7.1 Types of Processor Mode Single-chip mode, memory expansion mode or microprocessor mode can be selected as a processor mode. Table 7.1 lists a feature of the processor mode. Table 7.1 Processor Mode Feature Processor Mode Single-chip Mode Memory Expansion Mode Microprocessor Mode Accessable Space SFR, Internal RAM, Internal ROM SFR, Internal RAM, Internal ROM, External Space(1) SFR, Internal RAM, External Space(1) Pin Status as I/O Ports All pins assigned to I/O ports or to I/O pins for the peripheral functions Some pins assigned to bus control pins(1) Some pins assigned to bus control pins(1) NOTES: 1. Refer to 8. Bus for details. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 55 of 495 M32C/84 Group (M32C/84, M32C/84T) 7. Processor Mode 7.2 Setting of Processor Mode The CNVSS pin state and the PM01 and PM00 bit settings in the PM0 register determine which processor mode is selected. Table 7.2 lists processor mode after hardware reset. Table 7.3 lists processor mode selected by PM01 and PM00 bit settings. Table 7.2 Processor Mode after Hardware Reset Input Level into the CNVSS pin VSS VCC1(1, 2) Processor Mode Single-chip Mode Microprocessor Mode NOTES: 1. The internal ROM cannot be accessed, regardless of PM01 and PM00 bit settings, when applying VCC1 to the CNVSS pin and generating the hardware reset (hardware reset 1 or brown-out detection reset). 2. Multiplex bus cannot be assigned to all CS areas. Table 7.3 Processor Mode Selected by the PM01 and PM00 bit Settings PM01 and PM00 Bits 002 012 102 112 Processor Mode Single-chip Mode Memory Expansion Mode Do not set to this value Microprocessor Mode If the PM01 and PM00 bits are rewritten, the mode corresponding to the PM01 and PM00 bits is selected regardless of CNVSS pin level. Do not change the PM01 and PM00 bits to "012" (memory expansion mode) or "112" (microprocessor mode) when the PM07 to PM02 bits in the PM0 register are being rewritten. Do not enter microprocessor mode while the CPU is executing a program in the internal ROM. Do not enter single-chip mode or memory expansion mode from microprocessor mode while the CPU is executing a program in an external memory space, the same address assigned for the internal ROM. The internal ROM cannot be accessed, regardless of PM01 and PM00 bit settings, when applying VCC1 to the CNVSS pin and generating the hardware reset (hardware reset 1 or low voltage detection reset). Figures 7.1 and 7.2 show the PM0 register and PM1 register. Figure 7.3 shows a memory map in each processor mode. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 56 of 495 M32C/84 Group (M32C/84, M32C/84T) 7. Processor Mode Processor Mode Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol PM0 Address 000416 After Reset 1000 00002 (CNVss = "L") 0000 00112 (CNVss = "H") Bit Symbol PM00 Bit Name b1 b0 Function 0 0: Single-chip mode 0 1: Memory expansion mode(8) 1 0: Do not set to this value 1 1: Microprocessor mode(8) 0: RD / BHE / WR 1: RD / WRH / WRL The microcomputer is reset when this bit is set to "1". When read, its content is "0". b5 b4 RW RW Processor Mode PM01 Bit(2, 3) RW PM02 R/W Mode Select Bit RW PM03 Software Reset Bit RW PM04 Multiplexed Bus Space Select Bit(4) PM05 0 0 : Multiplexed bus is not used RW 0 1 : Access the CS2 area using the bus 0 1 : Access the CS1 area using the bus 1 1 : Access all CS areas using the bus(5) RW Set to "0" RW (b6) Reserved Bit PM07 BCLK Output Disable Bit(6) 0 : BCLK is output(7) 1 : BCLK is not output RW The CM01 and CM00 bits in the CM0 register determine pin functions NOTES: 1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1"(write enable). 2. The PM01 and PM00 bits maintain values set before reset, even after software reset or watchdog timer reset has performed. 3. Set the PM01 and PM00 bits to "012" or "112" separately. Rewrite other bits before rewriting the PM01 and PM00 bits. 4. The PM04 and PM05 bits are available in memory expansion mode or microprocessor mode. • Set the PM05 and PM04 bits to "002" in mode 0. • Do not set the PM05 and PM04 bits to "012" in mode 2. 5. The PM05 and PM04 bits cannot be set to "112" in microprocessor mode since the microcomputer starts up with the separate bus after reset. When the PM05 and PM04 bits are set to "112" in memory expansion mode, the microcomputer can access each 64-Kbyte chip-select-assigned address space. The multiplexed bus is not available in mode 0. The microcomputer accesses the CS0 to CS2 in mode 1, CS0 and CS1 in mode 2 and CS0 to CS3 in mode 3. 6. No BCLK is output in single-chip mode even if the PM07 bit is set to "0". When a clock output is terminated in microprocessor mode or memory expansion mode, set the PM07 bit to "1" and the CM01 and CM00 bits in the CM0 register to "002" (I/O port P53). P53 outputs "L". 7. When the PM07 bit is set to "0" (BCLK output), set the CM01 and CM00 bits to "002". 8. M32C/84T cannot be used in memory expansion mode and microprocessor mode. Figure 7.1 PM0 Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 57 of 495 M32C/84 Group (M32C/84, M32C/84T) 7. Processor Mode Processor Mode Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 0 0 Symbol PM1 Address 000516 After Reset 0016 Bit Symbol PM10 Bit Name b1 b0 Function RW PM11 0 0 : Mode 0 (A20 to A23 for P44 to P47) RW 0 1 : Mode 1 (A20 for P44, CS2 to CS0 for P45 to P47) External Memory Space 1 0 : Mode 2 (A20, A21 for P44, P45, Mode Bit(2, 4) CS1, CS0 for P46, P47) RW 1 1 : Mode 3 (CS3 to CS0 for P44 to P47) Internal Memory Wait Bit SFR Area Wait Bit 0 : No wait state 1 : Wait state 0 : 1 wait state 1 : 2 Wait states b5 b4 PM12 RW PM13 RW PM14 ALE Pin Select Bit(2, 4) PM15 Reserved Bit (b7-b6) 0 0 : No ALE 0 1 : P53/BCLK(3) 1 0 : P56 1 1 : P54/HLDA Set to "0" RW RW RW NOTES: 1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable). 2. The PM15 and PM14 bit setting, PM11 and PM10 bit setting are available in memory expansion mode or microprocessor mode. 3. Set the CM01 and CM00 bits in the CM0 register to "002" (I/O port P53) when the PM15 and PM14 bits are set to "012" (P53/BCLK select). 4. M32C/84T cannot be used in memory expansion mode and microprocessor mode. Figure 7.2 PM1 Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 58 of 495 Single-Chip Mode Mode 1 Mode 2 Mode 3 Mode 0 Mode 1 SFR Internal RAM SFR Internal RAM Reserved Space Reserved Space SFR Internal RAM Reserved Space SFR Internal RAM Reserved Space Block A(3) Not Used External Space 0 CS1 1 Mbyte External Space 0 CS2 1 Mbyte External Space 1 External Space 1 CS1 4 Mbytes(2) External Space 0 CS2 2 Mbytes External Space 1 Not Used CS1 4 Mbytes(2) External Space 0 CS1 1 Mbyte External Space 0 CS2 1 Mbyte External Space 1 SFR Internal RAM Reserved Space Block A(3) Memory Expansion Mode Microprocessor Mode Mode 2 Mode 3 SFR Internal RAM Reserved Space Mode 0 SFR Internal RAM Reserved Space Block A(3) 00000016 SFR M32C/84 Group (M32C/84, M32C/84T) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 CS1 2 Mbytes(1)External Space0 CS1 2 Mbytes(1) External Space 0 CS2 2 Mbytes External Space 1 Not Used Not Used External Space 2 External Space 2 External Space 2 External Space 2 External Space 2 CS0 2 Mbytes External Space 3 CS0 3 Mbytes External Space 3 CS3 1 Mbyte External Space 2 Not Used External Space 3 Not Used CS0 4 Mbytes External Space 3 CS0 1 Mbyte External Space 3 Reserved Space Internal ROM CS0 2 Mbytes External Space 3 CS3 1 Mbyte External Space 2 Not Used Not Used Reserved Space Internal ROM Reserved Space Internal ROM CS0 1 Mbyte External Space 3 00040016 Internal RAM SFR Internal RAM Reserved Space Reserved Space 00F00016 01000016 Block A(3) Block A(3) Figure 7.3 Memory Map in Each Processor Mode NOTES: 1. 20000016 - 01000016=1984 Kbytes. 64K bytes less than 2 Mbytes. 2. 40000016 - 01000016=4032 Kbytes. 64K bytes less than 4 Mbytes. 3. Additional 4-Kbyte space is provided in the flash memory version for storing data. Page 59 of 495 10000016 External Space 0 20000016 30000016 External Space 1 40000016 Not Used External Space 2 C0000016 D0000016 External Space 3 E0000016 F0000016 Reserved Space FFFFFF 16 Internal ROM Internal ROM 7. Processor Mode The EWCRi register (i=0 to 3) can determine how many wait states are inserted for each space CS0 to CS3. M32C/84 Group (M32C/84, M32C/84T) 8. Bus 8. Bus In memory expansion mode or microprocessor mode, some pins function as bus control pins to control the _____ ______ ______ ______ ___ ______ _________ _______ _____ address bus and data bus. A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/WR, WRH/BHE, RD, BCLK/ALE, _________ _________ _______ HLDA/ALE, HOLD, ALE, RDY are used as bus control pins. NOTE Bus control pins in M32C/84T cannot be used. 8.1 Bus Settings The BYTE pin, the DS register, the PM05 and PM04 bits in the PM0 register and the PM11 and PM10 bits in the PM1 register determine bus settings. Table 8.1 lists how to change bus settings. Figure 8.1 shows the DS register. Table 8.1 Bus Settings Bus Setting Selecting External Address Bus Width Setting Bus Width after Reset Selecting Between Separate Bus or Multiplexed Bus Number of Chip-Select Changed By DS register BYTE pin (external space 3 only) PM05 and PM04 bits in PM0 register PM11 and PM10 bits in PM1 register External Data Bus Width Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DS Address 000B16 After Reset XXXX 10002 (BYTE pin = "L") XXXX 00002 (BYTE pin = "H") Bit Symbol DS0 Bit Name External Space 0 Data Bus Width Select Bit External Space 1 Data Bus Width Select Bit External Space 2 Data Bus Width Select Bit External Space 3 Data Bus Width Select Bit(1) Function 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide 0 : 8 bits wide 1 : 16 bits wide RW RW DS1 RW DS2 RW DS3 RW (b7 - b4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. The DS register in M32C/84T cannot be used. Figure 8.1 DS Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 60 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus 8.1.1 Selecting External Address Bus The number of externally-output address buses, the number of chip-select signals and chip-select-as_____ signed address space (CS area) vary depending on each external space mode. The PM11 and PM10 bits in the PM1 register determine the external space mode. 8.1.2 Selecting External Data Bus The DS register selects either external 8-bit or 16-bit data bus per external space. The data bus in the external space 3, after reset, becomes 16 bits wide when a low-level ("L") signal is applied to the BYTE pin and 8 bits wide when a high-level ("H") signal is applied. Keep the BYTE pin input level while the microcomputer is operating. Internal bus is always 16 bits wide. 8.1.3 Selecting Separate/Multiplexed Bus The PM05 and PM04 bits in the PM0 register determine either separate or multiplexed bus as bus format. 8.1.3.1 Separate Bus The separate bus is a bus format which allows the microcomputer to input and output data and address separatelly. The DS register selects 8-bit or 16-bit data bus as the external data bus per external space. If all DSi bits in the DS register (i=0 to 3) are set to "0" (8-bit data bus), port P0 becomes the data bus and port P1, the programmable I/O port. If one of the DSi bits is set to "1" (16-bit data bus), ports P0 and P1 become the data bus. Port P1 is indeterminate when the microcomputer accesses a space where the DSi bit is set to "0". The EWCRi register (i=0 to 3) determines the number of software wait states inserted, when the microcomputer accesses space using the separate bus. 8.1.3.2 Multiplexed Bus The multiplexed bus is a bus format which allow the microcomputer to input and output data and address by timesharing. D0 to D7 are multiplexed with A0 to A7 in space accessed by the 8-bit data bus. D0 to D15 are multiplexed with A0 to A15 in space accessed by the 16-bit data bus. The DSi bit controls the data bus width. The EWCRi register (i=0 to 3) controls the number of software wait states inserted, when the microcomputer accesses a space using the multiplexed bus. Refer to 8.2.4 Bus Timing for details. _______ _______ _____ The multiplexed bus can be assigned to access the CS1 area, CS2 area or all CS areas. However, because the microcomputer starts operation using the separate bus after reset, the multiplexed bus _____ cannot be assigned to access all CS areas in microprocessor mode. When the PM05 and PM04 bits _____ in the PM0 register are set to "112" (access all CS areas with the bus), 16 low-order bits, from A0 to A15, of an address are output. See Table 8.2 for details. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 61 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus Table 8.2 Processor Mode and Port Function Processor Mode PM05 to PM04 Bits in PM0 Register SingleChip Mode Memory Expansion Mode/ Microprocessor Mode "012", "102" Access CS1 or CS2 using the Multiplexed Bus Access All Other CS Areas using the Separate Bus Memory Expansion Mode "112"(1) Access all CS Areas using the Multiplexed Bus "002" Access all CS Areas using the Separate Bus Data Bus Width Access all Access one or more Access all Access one or more Access all Access one or more external space with external space with external space with external space with external space with external space with 8-bit data bus 16-bit data bus 8-bit data bus 16-bit data bus 8-bit data bus 16-bit data bus P00 to P07 P10 to P17 I/O port I/O port Data bus D0 to D7 Data bus D0 to D7 Data bus D0 to D7 Data bus D0 to D7 I/O port I/O port Address bus Data bus A0/D0 to A7/D7 Address bus A8 to A15 I/O port I/O port Address bus Data bus A0/D0 to A7/D7 Address bus/ Data bus A8/D8 to A15/D15 I/O port Address bus Data bus(2) A0/D0 to A7/D7 Address bus A8 to A15 Address bus A16 to A19 Data bus D8 to D15 Address bus Data bus(2) A0/D0 to A7/D7 Address bus/ Data bus(2) A8/D8 to A15/D15 Address bus A16 to A19 I/O port Address bus A0 to A7 Address bus A8 to A15 Address bus A16 to A19 Data bus D8 to D15 Address bus A0 to A7 Address bus A8 to A15 Address bus A16 to A19 P20 to P27 I/O port P30 to P37 P40 to P43 P44 to P46 P47 P50 to P53 P54 P55 P56 P57 I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port CS (Chip-select signal) or Address bus (A20 to A22) (Refer to 8.2 Bus Control for details)(4) CS (Chip-select signal) or Address bus (A23) (Refer to 8.2 Bus Control for details)(4) Outputs RD, WRL, WRH and BCLK or outputs RD, BHE, WR and BCLK (Refer to 8.2 Bus Control for details)(3) HDLA (3) HOLD ALE (3) RDY HDLA (3) HOLD ALE (3) RDY HDLA (3) HOLD ALE (3) RDY HDLA (3) HOLD ALE (3) RDY HDLA (3) HOLD ALE (3) RDY HDLA (3) HOLD ALE (3) RDY NOTES: 1. The PM05 and PM04 bits cannot be set to "112" (access all CS areas using multiplexed bus) in microprocessor mode because the microcomputer starts operation using the separate bus after reset. When the PM05 and PM04 bits are set to "112" in memory expansion mode, the microcomputer accesses 64-Kbyte memory space per chip-select using the address bus . 2. These ports become address buses when accessing space using the separate bus. 3. The PM15 and PM14 bits in the PM1 register determines which pin outputs the ALE signal. The PM02 bit in the PM0 register selects either "WRL,WRH" or "BHE,WR" combination. P56 provides an indeterminate output when the PM15 and PM14 bits to "002" (no ALE). It cannot be used as an I/O port. 4. The PM11 and PM10 bits in the PM1 register determine the CS signal and address bus. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 62 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus 8.2 Bus Control Signals, required to access external devices, are provided and software wait states are inserted as follows. The signals are available in memory expansion mode and microprocessor mode only. 8.2.1 Address Bus and Data Bus ______ _____ Address bus is a signal accessing 16-Mbyte space and uses 24 control pins; A0 to A22 and A23. A23 is the inversed output signal of the highest-order address bit. Data bus is a signal for data input and output. The DS register selects an 8-bit data bus from D0 to D7 or a 16-bit data bus from D0 to D15 for each external space. When applying a high-level ("H") signal to the BYTE pin, the data bus accessing the external memory space 3 becomes an 8-bit data bus after reset. When applying a low-level ("L") signal to the BYTE pin, the data bus accessing the external memory space 3 becomes the 16-bit data bus. When changing single-chip mode to memory expansion mode, the address bus is in an indeterminate state until the microcomputer accesses an external memory space. 8.2.2 Chip-Select Signal _____ Chip-select signal shares pins with A20 to A22 and A23. The PM11 and PM10 bits in the PM1 register _____ determine which CS area is accessed and how many chip-select signals are output. A maximum of four chip-select signals can be output. ______ In microprocessor mode, no chip-select signal, aside from A23 which can perform as a chip-select signal, is output after reset. ______ The chip-select signal becomes "L" while the microcomputer is accessing the external CSi area (i=0 to 3). It becomes "H" while the microcomputer is accessing other external memory space. Figure 8.2 shows an example of the address bus and chip-select signal output. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 63 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus Example 1: When the microcomputer accesses the external space j specified by another chip-select signal in the next cycle after having accessed the external space i, both address bus and chip-select signal change. Example 2: When the microcomputer accesses the SFR or the internal ROM/RAM area in the next cycle after having accessed an external space, the chip-select signal changes but the address bus does not. Access External Space Access SFR, Internal ROM/RAM Area Access External Space i Access External Space j Data Bus Address Bus Chip-Select Signal CSk Chip-Select Signal CSp Data Data Data Bus Address Bus Chip-Select Signal CSk Data Address Address i = 0 to 3 k = 0 to 3 j = 0 to 3, excluding i p= 0 to 3, excluding k (See Figure 7.3 for i, j and p, k) k = 0 to 3 Example 3: When the microcomputer accesses the space i specified by the same chip-select signal in the next cycle after having accessed the external space i, the address bus changes but the chip-select signal does not. Access External Space i Access External Space i Example 4: When the microcomputer does not access any space in the next cycle after having accessed an external space (no pre-fetch of an instruction is generated), neither address bus nor chip-select signal changes. Access External No Access Space Data Bus Address Bus Chip-Select Signal CSk Data Data Data Bus Address Bus Chip-Select Signal CSk Data Address Address i = 0 to 3 (See Figure 7.3 for i and k) k = 0 to 3 k = 0 to 3 NOTES: 1. The above applies to the address bus and chip-select signal in two consecutive cycles. By combining these examples, a chip-select signal extended by two or more cycles may be output. Figure 8.2 Address Bus and Chip-Select Signal Outputs (Separate Bus) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 64 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus 8.2.3 Read and Write Signals _____ ______ When using a16-bit data bus, the PM02 bit in the PM0 register selects a combination of the "RD, WR and ________ _____ ________ _________ BHE" signals or the "RD, WRL and WRH" signals to determine the read or write signal. When the DS3 to _____ ______ ________ DS0 bits in the DS register are set to "0" (8-bit data bus), set the PM02 bit to "0" (RD/WR/BHE). When any of the DS3 to DS0 bits are set to "1" (16-bit data bus) to access an 8-bit space, the combination of _____ ______ ________ "RD, WR and BHE" is automatically selected regardless of the PM02 bit setting. Tables 8.3 and 8.4 list each signal operation. _____ ______ ________ The RD, WR and BHE signals are combined for the read or write signal after reset. _____ ________ _________ When changing the combination of "RD, WRL and WRH", set the PM02 bit first to write data to an external memory. _____ ________ _________ Table 8.3 RD, WRL and WRH Signals Data Bus 16 Bits RD L H H H H L WRL H L H L L(1) H(1) WRH H H L L Not used Not used Status of External Data Bus Read data Write 1-byte data to even address Write 1-byte data to odd address Write data to both even and odd addresses Write 1-byte data Read 1-byte data 8 Bits NOTES: ______ _______ 1. The WR signal is used instead of the WRL signal. _____ ______ ________ Table 8.4 RD, WR and BHE Signals Data Bus RD H L H L H L H L WR L H L H L H L H BHE L L H H L L Not used Not used A0 H H L L L L H/L H/L Status of External Data Bus Write 1-byte data to odd address Read 1-byte data from odd address Write 1-byte data to even address Read 1-byte data from even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1-byte data Read 1-byte data 16 Bits 8 Bits Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 65 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus 8.2.4 Bus Timing Bus cycle for the internal ROM and internal RAM is basically one BCLK cycle. When the PM12 bit in the PM1 register is set to "1" (wait state), the bus cycles are two BCLK cycles. Bus cycles for the SFR are basically two BCLK cycles. Basic bus cycle for an external space is 2ø (1ø+1ø) to read and to write. Bus cycle is selected by the EWCRi register (i=0 to 3) from 12 types of separate bus settings and 7 types of multiplexed bus settings. If the EWCRi04 to EWCRi00 bits are set to "000112" (1ø+3ø), bus cycles are four BCLK cycles. Figure 8.3 shows the EWCRi register. Figures 8.4 to 8.8 show bus timing in an external space. External Space Wait Control Register i (i=0 to 3)(3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol EWCR0 to EWCR3 Address 004816, 004916, 004A16, 004B16 After Reset X0X0 00112 Bit Symbol EWCRi00 Bit Name b4 b3 b2 b1 b0 (1) Function 0 0 0 0 1: 1φ + 1φ 0 0 0 1 0: 1φ + 2φ 0 0 0 1 1: 1φ + 3φ 0 0 1 0 0: 1φ + 4φ 0 0 1 0 1: 1φ + 5φ 0 0 1 1 0: 1φ + 6φ 0 1 0 1 0: 2φ + 2φ 0 1 0 1 1: 2φ + 3φ 0 1 1 0 0: 2φ + 4φ 0 1 1 0 1: 2φ + 5φ 1 0 0 1 1: 3φ + 3φ 1 0 1 0 0: 3φ + 4φ 1 0 1 0 1: 3φ + 5φ 1 0 1 1 0: 3φ + 6φ Do not set values other than the above (2) RW RW EWCRi01 RW EWCRi02 Bus Cycle Select Bit RW EWCRi03 RW EWCRi04 RW (b5) Nothing is assigned. When read, its content is indeterminate. RW 0 : Adds no recovery cycle when Recovery Cycle Addition accessing external space i EWCRi06 1 : Adds a recovery cycle when Select Bit accessing external space i Nothing is assigned. When read, its content is indeterminate. (b7) NOTES: 1. The number of bus cycles from "when bus access begins" to "when RD or WR signal becomes "L". 2. The number of bus cycles from "when RD or WR signal becomes "L" to "when it becomes "H". 3. The EWCR0 to EWCR3 registers in M32C/84T cannot be used. Figure 8.3 EWCR0 to EWCR3 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 66 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus Table 8.5 Software Wait State and Bus Cycle PM1 Register Space External Bus Status PM13 Bit 0 SFR Internal ROM/RAM --1 0 ----1 000012 000102 000112 001002 001012 001102 Separate Bus ----010102 010112 011002 External Memory 100112 101002 101102 010102 010112 011012 Multiplexed Bus ----100112 101002 101012 101102 4 BCLK cycles 5 BCLK cycles 6 BCLK cycles 6 BCLK cycles 7 BCLK cycles 9 BCLK cycles 4 BCLK cycles 5 BCLK cycles 7 BCLK cycles 6 BCLK cycles 7 BCLK cycles 8 BCLK cycles 9 BCLK cycles -2 BCLK cycles 2 BCLK cycles 3 BCLK cycles 4 BCLK cycles 5 BCLK cycles 6 BCLK cycles 7 BCLK cycles ----3 BCLK cycles 1 BCLK cycles PM12 Bit EWCRi Register (i=0 to 3) Bus Cycles EWCRi04 to EWCRi00 Bits 2 BCLK cycles Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 67 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus • Bus Cycle 1φ + 1φ BCLK Address CSi (1) 1 bus cycle = 2φ • Bus Cycle 1φ + 2φ BCLK Address CSi (1) Data (Read) RD Data (Write) WR, WRL, WRH 1 bus cycle = 3φ Data (Read) RD Data (Write) WR, WRL, WRH • Bus Cycle 1φ + 3φ BCLK Address CSi (1) 1 bus cycle = 4φ • Bus Cycle 1φ + 4φ BCLK Address CSi (1) Data (Read) RD Data (Write) WR, WRL, WRH 1 bus cycle = 5φ Data (Read) RD Data (Write) WR, WRL, WRH • Bus Cycle 1φ + 5φ BCLK Address CSi (1) Data (Read) RD Data (Write) WR, WRL, WRH 1 bus cycle = 6φ • Bus Cycle 1φ + 6φ BCLK Address CSi (1) Data (Read) RD Data (Write) WR, WRL, WRH 1 bus cycle = 7φ i=0 to 3 NOTES: 1. When the microcomputer continuously accesses the same CS area, the CSi pin provides an "L" signal continuously. Figure 8.4 Bus Cycle with Separate Bus (1) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 68 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus • Bus Cycle 2φ + 2φ BCLK Address CSi (1) Data (Read) RD Data (Write) WR, WRL, WRH 1 bus cycle = 4φ • Bus Cycle 2φ + 3φ BCLK Address CSi (1) Data (Read) RD Data (Write) WR, WRL, WRH 1 bus cycle = 5φ • Bus Cycle 2φ + 4φ BCLK Address CSi (1) Data (Read) RD Data (Write) WR, WRL, WRH 1 bus cycle = 6φ i=0 to 3 NOTES: 1. When the microcomputer continuously accesses the same CS area, the CSi pin provides an "L" signal continuously. Figure 8.5 Bus Cycle with Separate Bus (2) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 69 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus • Bus Cycle 3φ + 3φ BCLK Address CSi (1) 1 bus cycle = 6φ Data (Read) RD Data (Write) WR, WRL, WRH • Bus Cycle 3φ + 4φ BCLK Address CSi (1) 1 bus cycle = 7φ Data (Read) RD Data (Write) WR, WRL, WRH • Bus Cycle 3φ + 6φ BCLK Address CSi (1) 1 bus cycle = 9φ Data (Read) RD Data (Write) WR, WRL, WRH i=0 to 3 NOTES: 1. When the microcomputer continuously accesses the same CS area, the CSi pin provides an "L" signal continuously. Figure 8.6 Bus Cycle with Separate Bus (3) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 70 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus • Bus Cycle 2φ + 2φ BCLK CSi (1) Data (Read) RD Data (Write) WR (WRL) ALE 1 bus cycle = 4φ • Bus Cycle 2φ + 3φ BCLK CSi (1) 1 bus cycle = 5φ LA RD Data (Read) RD LA RD LA WD Data (Write) WR (WRL) ALE LA WD • Bus Cycle 2φ + 5φ BCLK CSi (1) Data (Read) RD Data (Write) WR (WRL) ALE LA LA 1 bus cycle = 7φ RD WD LA : Latch Address RD : ReadData WD : Write Data i=0 to 3 NOTES: 1. When the microcomputer continuously accesses the same CS area, the CSi pin provides an "L" signal continuously. Figure 8.7 Bus Cycle with Multiplexed Bus (1) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 71 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus • Bus Cycle 3φ + 3φ BCLK CSi (1) Data (Read) RD Data (Write) WR (WRL) ALE LA LA 1 bus cycle = 6φ RD WD • Bus Cycle 3φ + 4φ BCLK CSi (1) Data (Read) RD Data (Write) WR (WRL) ALE LA LA 1 bus cycle = 7φ RD WD • Bus Cycle 3φ + 5φ BCLK CSi (1) Data (Read) RD Data (Write) WR (WRL) ALE LA LA 1 bus cycle = 8φ RD WD • Bus Cycle 3φ + 6φ BCLK CSi (1) Data (Read) RD Data (Write) WR (WRL) ALE LA LA 1 bus cycle = 9φ RD WD LA : Latch Address RD : Read Data WD : Write Data i=0 to 3 NOTES: 1. When the microcomputer continuously accesses the same CS area, the CSi pin provides an "L" signal continuously. Figure 8.8 Bus Cycle with Multiplexed Bus (2) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 72 of 495 M32C/84 Group (M32C/84, M32C/84T) 8. Bus 8.2.4.1 Bus Cycle with Recovery Cycle Added The EWCRi06 bit in the EWCRi register (i=0 to 3) determines whether the recovery cycle is added or not. In the recovery cycle, addresses and wrie data outputs are provided continuously (using the separate bus only). Devices, which take longer address hold time and data hold time to write data, are connectable. • Recovery Cycle with Separate Bus (For 1φ + 2φ) Recovery Cycle BCLK Address CSi (1) A IPL = the exit priority level (5) Set the PRC0 bit in the PRCR register to "1" (6) If the CPU clock source is the PLL clock, set the CM17 bit in the CM1 register to "0" (main clock) and PLC07 bit in the PLC0 register to "0" (PLL off) (7) Set the I flag to "1" (8) Execute the WAIT instruction • After Exiting Wait Mode Set the exit priority level to "7" as soon as exiting wait mode. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 98 of 495 M32C/84 Group (M32C/84, M32C/84T) 9. Clock Generation Circuit 9.5.2.3 Pin Status in Wait Mode Table 9.7 lists pin states in wait mode. Table 9.7 Pin States in Wait Mode Pin _______ ________ _______ Memory Expansion Mode(1) Microprocessor Mode(1) Maintains state immediately before entering wait mode "H" "H" "L" Single-Chip Mode Address Bus, Data Bus, CS0 to CS3, BHE _____ ______ ________ _________ RD, WR, WRL, WRH __________ HLDA, BCLK ALE Ports CLKOUT When fC is selected When f8, f32 are selected Maintains state immediately before entering wait mode Outputs clock Outputs the clock when the CM02 bit in the CM0 register is set to "0" (peripheral function clock does not stop in wait mode). Maintains state immediately before entering wait mode when the CM02 bit is set to "1" (peripheral function clock stops in wait mode). NOTES: 1. M32C/84T cannot be used in memory expansion mode and microprocessor mode. 9.5.2.4 Exiting Wait Mode _______ Wait mode is exited by the hardware reset, NMI interrupt or peripheral function interrupts. _______ When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to "0002" (interrupt disabled) before executing the WAIT instruction. CM02 bit setting affects the peripheral function interrupts. When the CM02 bit in the CM0 register is set to "0" (peripheral function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode. When the CM02 bit is set to "1" (peripheral function clock stops in wait mode), peripheral functions using the peripheral function clock stop. Therefore, the peripheral function interrupts cannot be used to exit wait mode. However, the peripheral function interrupts caused by an external clock, fC32, or f2n whose count source is the XIN clock or on-chip oscillator clock, can be used to exit wait mode. _______ The CPU clock used when exiting wait mode by the peripheral function interrupts or NMI interrupt is the same CPU clock used when the WAIT instruction is executed. Table 9.8 shows interrupts to be used to exit wait mode and usage conditions. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 99 of 495 M32C/84 Group (M32C/84, M32C/84T) 9. Clock Generation Circuit Table 9.8 Interrupts to Exit Wait Mode Interrupt NMI Interrupt Serial I/O Interrupt Key Input Interrupt A/D Conversion Interrupt Timer A Interrupt Timer B Interrupt INT Interrupt Low Voltage Detection Interrupt CAN Interrupt Intelligent I/O Interrupt Available Available when the internal and external clocks are used Available Available in single or single-sweep mode Available in all modes Available Available Available Available When CM02=0 Available Available when the external clock or f2n (when XIN clock or on-chip oscillator is selected) is used Available Do not use Available in event counter mode or when count source is fC32 or f2n (when XIN clock or on-chip oscillator is selected) Available Available Do not use Do not use When CM02=1 9.5.3 Stop Mode In stop mode, all oscillators and resonators stop. The CPU clock and peripheral function clock, as well as the CPU and peripheral functions operated by these clocks, also stop. The least power required to operate the microcomputer is in stop mode. The internal RAM holds its data when the voltage applied to the VCC1 and VCC2 pins is VRAM or more. If the voltage applied to the VCC1 and VCC2 pins is 2.7V or less, the voltage must be Vcc1 ≥ Vcc2 ≥ VRAM(1). The following interrupts can be used to exit stop mode: _______ • NMI interrupt • Key Input Interrupt ______ • INT interrupt • Timer A and B interrupt (Available when the timer counts external pulse, having its 100Hz or less frequency, in event counter mode) • Low voltage detection interrupt (Refer to 6.1 Low Voltage Detection Interrupt for usage conditions) NOTES: 1. The supply voltage of M32C/84T must be VCC1=VCC2. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 100 of 495 M32C/84 Group (M32C/84, M32C/84T) 9. Clock Generation Circuit 9.5.3.1 Entering Stop Mode Stop mode is entered when setting the CM10 bit in the CM10 register to "1" (all clocks stops). The MCD4 to MCD0 bits in the MCD register become set to "010002" (divide-by-8 mode). Enter stop mode after setting the followings. • Initial Setting Set each interrupt priority level after setting the exit priority level, required to exit stop mode, controlled by the RLVL2 to RLVL0 bits in the RLVL register, to "7". • Before Entering stop mode (1) Set the I flag to "0" (2) Set the interrupt priority level of the interrupt being used to exit stop mode (3) Set the interrupt priority levels of the interrupts, not being used to exit stop mode, to "0" (4) Set IPL in the FLG register. Then set the exit priority level to the same level as IPL Interrupt priority level of the interrupt used to exit stop mode > IPL = the exit priority level (5) Set the PRC0 bit in the PRCR register to "1" (write enable) (6) Select the main clock as the CPU clock • When the CPU clock source is the sub clock, (a) set the CM05 bit in the CM0 register to "0" (main clock oscillates) (b) set the CM07 bit in the CM0 register to "0" (clock selected by the CM21 bit divided by MCD register setting) • When the CPU clock source is the PLL clock, (a) set the CM17 bit in the CM1 register to "0" (main clock) (b) set the PLC07 bit in the PLC0 register to "0" (PLL off) • When main clock direct mode is used, (a) set the PRC1 bit in the PRCR register to "1" (write enable) (b) set the PM24 bit in the PM2 register to "0" (clock selected by the CM07 bit) • When the CPU clock source is the on-chip oscillator clock, (a) set MCD4 to MCD0 bits to "010002" (divide-by-8 mode) (b) set the CM05 bit to "0" (main clock oscillates) (c) set the CM21 bit in the CM2 register to "0" (clock selected by the CM17 bit) (7) The oscillation stop detect function is used, set the CM20 bit in the CM2 register to "0" (oscillation stop detect fucntion disabled) (8) Set the I flag to "1" (9) Set the CM10 bit to "1" (all clocks stops) • After Exiting Stop Mode Set the exit priority level to "7" as soon as exiting stop mode. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 101 of 495 M32C/84 Group (M32C/84, M32C/84T) 9. Clock Generation Circuit 9.5.3.2 Exiting Stop Mode _______ Stop mode is exited by the hardware reset, NMI interrupt or peripheral function interrupts (key input ______ interrupt and INT interrupt). _______ When the hardware reset or NMI interrupt, but not the peripheral function interrupts, is used to exit wait mode, set all ILVL2 to ILVL0 bits in the interrupt control registers for the peripheral function interrupt to "0002" (interrupt disabled) before setting the CM10 bit to "1" (all clocks stops). 9.5.3.3 Pin Status in Stop Mode Table 9.9 lists pin status in stop mode. Table 9.9 Pin Status in Stop Mode Pin _______ _______ _______ Memory Expansion Mode(1) Microprocessor Mode(1) Maintains state immediately before entering stop mode Single-Chip Mode Address Bus, Data Bus, CS0 to CS3, BHE _____ ______ ________ _________ RD, WR, WRL, WRH __________ "H" "H" "H" Maintains state immediately before entering stop mode HLDA, BCLK ALE Ports CLKOUT When fC selected When f8, f32 selected XIN XOUT XCIN, XCOUT "H" Maintains state immediately before entering stop mode Placed in a high-impedance state "H" Placed in a high-impedance state NOTES: 1. M32C/84T cannot be used in memory expansion mode and microprocessor mode. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 102 of 495 M32C/84 Group (M32C/84, M32C/84T) 9. Clock Generation Circuit Reset All oscillation is stopped CM10=1 (Note 2) CPU operation is stopped Stop Mode Interrupt Middle-Speed Mode (divide-by-8 mode) (Note 1) (Note 2) WAIT Instruction Interrupt Wait Mode Inter rupt (Note 2) Stop Mode CM10=1 (Note 2) High-Speed / Middle-Speed Mode (Note 1) (Note 3) WAIT Instruction Wait Mode Interrupt Low-Speed/ Low-Power Consumption Mode WAIT Instruction Wait Mode Interrupt On-Chip Oscillator / OnChip Oscillator Low-Power Consumption Mode WAIT Instruction Interrupt Wait Mode Normal Operating Mode NOTES: 1. See Figure 9.14. 2. When the CM17 bit is set to "1" (PLL clock as CPU clock source), set the CM17 bit to "0"(main clock as CPU clock source) and the PLC07 bit is set to "0" (PLL off). Then enter wait mode or stop mode. 3. When the CM17 bit is set to "1" (PLL clock as CPU clock source), set the CM17 bit to "0"(main clock as CPU clock source) and the PLC07 bit is set to "0" (PLL off). Then enter low-speed or low-power consumption mode. Figure 9.13 Status Transition in Wait Mode and Stop Mode Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 103 of 495 M32C/84 Group (M32C/84, M32C/84T) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 After reset, Medium-Speed Mode (Divide-by-8) MCD=XX16 (Note 1) High-Speed Mode CM17=0 Main Clock Oscillation Sub Clock Oscillation On-Chip Oscillator Clock stop PLL Clock Oscillation Main Clock Oscillation Sub Clock Oscillation On-Chip Oscillator Clock Stop PLL Clock Oscillation High-Speed Mode Main Clock Oscillation Sub Clock Stop On-Chip Oscillator Clock Stop PLL Clock Stop CPU Clock: f(XIN)/8 CM07=0 MCD=0816 CM21=0 CM05=0 CM04=0 PLC07=0 CM17=0 CM04=1 (Note 1) CPU clock: f(XIN) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=1 PLC07=1 CM17=0 CM17=1 Main Clock Oscillation Sub Clock Stop On-Chip Oscillator Clock Stop PLL Clock Stop Main Clock Oscillation Sub Clock Oscillation On-Chip Oscillator Clock Stop PLL Clock Stop PLC07=0 High-Speed Mode CM04=0 CPU clock :f(XIN) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=1 PLC07=0 CM17=0 CM07=0 (Note 1) PLC07=1 High-Speed Mode PLC07=1 CPU clock: f(XIN) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=0 PLC07=0 CM17=0 CM04=1 CPU clock: f(XPLL) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=1 PLC07=1 CM17=1 Medium-Speed Mode CPU clock: f(XIN)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=1 PLC07=1 CM17=0 Medium-Speed Mode CPU clock: f(XPLL)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=1 PLC07=1 CM17=1 Low-Speed Mode PLC07=0 Medium-Speed Mode CPU clock: f(XIN)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=0 PLC07=0 CM17=0 Medium-Speed Mode CPU clock: f(XIN)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=1 PLC07=0 CM17=0 CM21=1 On-Chip Oscillator Mode (Note 1) CM21=0 CM21=1 (Note 1) CM21=0 On-Chip Oscillator Mode CM07=1 (Note 2) Main clock stop is detected when CM20=1 Low-Speed Mode Main Clock Oscillation Sub Clock Oscillation On-Chip Oscillator Clock Stop PLL Clock Stop CPU clock: f(XCIN) CM07=1 CM21=0 CM05=0 CM04=1 PLC07=0 CM17=0 CM21=0 CM21=1 (Note 1) Main clock stop is detected when CM20=1 CM07=0 Main Clock Oscillation Sub Clock Stop On-Chip Oscillator Clock Oscillation CM04=0 PLL Clock Stop CPU Clock: On-Chip Oscillator Clock /n (n=1,2,3,4,6,8,10,12,14,16) CM04=1 CM07=0 MCD=XX16 CM21=1 CM05=0 CM04=0 PLC07=0 CM17=0 CM05=0 CM05=1 Main Clock Oscillation Sub Clock Oscillation On-Chip Oscillator Clock Oscillation PLL Clock Stop CPU Clock: On-Chip Oscillator Clock /n (n=1,2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=1 CM05=0 CM04=1 PLC07=0 CM17=0 CM05=1 (Note 4) CM07=1 (Note 2) Main Clock Oscillation Sub Clock Oscillation On-Chip Oscillator Clock Oscillation PLL Clock Stop CPU Clock: f(XCIN) CM07=1 CM21=1 CM05=0 CM04=1 PLC07=0 CM17=0 CM05=0 Low-Power Consumption Mode CM05=1 Low-Power Consumption Mode CM05=0 CM05=1 CM05=0 On-Chip Oscillator Low-Power Consumption Mode (Note 5) On-Chip Oscillator Low-Power Consumption Mode Main Clock Stop Sub Clock Stop CM04=0 On-Chip Oscillator Clock Oscillation PLL Clock Stop CPU Clock: On-Chip Oscillator Clock /n (n=1,2,3,4,6,8,10,12,14,16) CM04=1 CM07=0 MCD=XX16 CM21=1 CM05=1 CM04=0 PLC07=0 CM17=0 Main Clock Stop Sub Clock Oscillation On-Chip Oscillator Clock Oscillation PLL Clock Stop CPU Clock: On-Chip Oscillator Clock /n (n=1,2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=1 CM05=1 CM04=1 PLC07=0 CM17=0 Main Clock Stop Sub Clock Oscillation On-Chip Oscillator Clock Oscillation PLL Clock Stop CPU Clock: f(XCIN) CM07=1 MCD=0816 CM21=1 CM05=1 CM04=1 PLC07=0 CM17=0 (Note 3) Main Clock Stop Sub Clock Oscillation On-Chip Oscillator Clock Stop PLL Clock Stop CPU Clock: f(XCIN) CM07=1 MCD=0816 CM21=0 CM05=1 CM04=1 PLC07=0 CM17=0 (Note 3) Figure 9.14 Status Transition Page 104 of 495 Main Clock Oscillation Sub Clock Stop On-Chip Oscillator Clock Stop PLL Clock Oscillation Main Clock Oscillation Sub Clock Stop On-Chip Oscillator Clock Stop PLL Clock Oscillation High-Speed Mode High-Speed Mode CPU clock: f(XPLL) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=0 PLC07=1 CM17=1 CM17=1 CPU clock: f(XIN) CM07=0 MCD=1216 CM21=0 CM05=0 CM04=0 PLC07=1 CM17=0 Medium-Speed Mode CPU clock: f(XPLL)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=0 PLC07=1 CM17=1 CM17=0 Medium-Speed Mode CPU clock: f(XIN)/n (n=2,3,4,6,8,10,12,14,16) CM07=0 MCD=XX16 CM21=0 CM05=0 CM04=0 PLC07=1 CM17=0 : An arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown. MCD=XX16: Set the MCD to MCD0 bits in the MCD register to the desired division. NOTES: 1. Switch the clock after main clock oscillation is fully stabilized. 2. Switch the clock after sub clock oscillation is fully stabilized. 3. The MCD4 to MCD0 bits in the MCD register are set to "010002" (devide-by-8 mode) automatically. 4. The CM05 bit is not set to "1" when the microcomputer detects a main clock oscillation stop through the oscillation stop detection circuit . 5. The on-chip oscillator clock runs when setting the PM22 bit to "1" (on-chip oscillator clock as watchdog timer count source) and setting the PM27 and PM26 bits to "102" (on-chip oscillator clock), even if the CM21 bit is set to "0". 9. Clock Generation Circuit M32C/84 Group (M32C/84, M32C/84T) 9. Clock Generation Circuit 9.6 System Clock Protect Function The system clock protect function prohibits the CPU clock from changing clock sources when the main clock is selected as the CPU clock source. This prevents the CPU clock from stopping the program crash. When the PM21 bit in the PM2 register is set to "1" (clock change disable), the following bits cannot be written to: • The CM02 bit, CM05 bit and CM07 bit in the CM0 register • The CM10 bit and CM17 bit in the CM1 register • The CM20 bit in the CM2 register • All bits in the PLC0 and PLC1 registers The CPU clock continues running when the WAIT instruction is executed. To use the system clock protect function, set the CM05 bit in the CM0 register to "0" (main clock oscillation) and CM07 bit to "0" (main clock as BCLK clock source) and follow the procedure below. (1) Set the PRC1 bit in the PRCR register to "1" (write enable). (2) Set the PM21 bit in the PM2 register to "1" (protects the clock). (3) Set the PRC1 bit in the PRCR register to "0" (write disable). When the PM21 bit is set to "1", do not execute the WAIT instruction. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 105 of 495 M32C/84 Group (M32C/84, M32C/84T) 10. Protection 10. Protection The protection function protects important registers from being easily overwritten when a program runs out of control. Figure 10.1 shows the PRCR register. Each bit in the PRCR register protects the following registers: • The PRC0 bit protects the CM0, CM1, CM2, MCD, PLC0 and PLC1 registers; • The PRC1 bit protects the PM0, PM1, PM2, INVC0 and INVC1 registers; • The PRC2 bit protects the PD9 and PS3 registers; • The PRC3 bit protects the VCR2 and D4INT registers. The PRC2 bit is set to "0" (write disable) when data is written to a desired address after setting the PRC2 bit to "1" (write enable). Set the PD9 and PS3 registers immediately after setting the PRC2 bit in the PRCR register to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the following instruction. The PRC0, PRC1 and PRC3 bits are not set to "0" even if data is written to desired addresses. Set the PRC0, PRC1 and PRC3 bits to "0" by program. Protect Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol PRCR Address 000A16 After Reset XXXX 00002 Bit Symbol Bit Name Function Enables writing to CM0, CM1, CM2, MCD, PLC0, PLC1 registers 0 : Write disable 1 : Write enable Enables writing to PM0, PM1, PM2, INVC0, INVC1 registers 0 : Write disable 1 : Write enable Enables writing to PD9, PS3 registers 0 : Write disable 1 : Write enable Enables writing to VCR2, D4INT registers 0 : Write disable 1 : Write enable RW PRC0 Protect Bit 0 RW PRC1 Protect Bit 1 RW PRC2 Protect Bit 2(1) RW PRC3 Protect Bit 3 RW Nothing is assigned. When write, set to "0". (b7 - b4) When read, its content is indeterminate. NOTES: 1. The PRC2 bit is set to "0" by writing into a desired address after the PRC2 bit is set to "1". The PRC0, PRC1 and PRC3 bits are not automatically set to "0". Set them to "0" by program. Figure 10.1 PRCR Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 106 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11. Interrupts 11.1 Types of Interrupts Figure 11.1 shows types of interrupts. Software (Non-Maskable Interrupt) Special (Non-Maskable Interrupt) Hardware Peripheral Function(1) (Maskable Interrupt) NOTES: 1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt. 2. Do not use this interrupt. For development support tools only. 3. Low voltage detection interrupt cannot be used in M32C/84T. Figure 11.1 Interrupts • Maskable Interrupt The I flag enables or disables an interrupt. The interrupt priority order based on interrupt priority level can be changed. • Non-Maskable Interrupt The I flag does not enable nor disable an interrupt . The interrupt priority order based on interrupt priority level cannot be changed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 107 of 495       Interrupt      Undefined Instruction (UND Instruction) Overflow (INTO Instruction) BRK Instruction BRK2 Instruction(2) INT Instruction _______               NMI Watchdog Timer Oscillation Stop Detection Low voltage Detection(3) Single-Step(2) Address Match DMACII M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11.2 Software Interrupts Software interrupt occurs when an instruction is executed. The software interrupts are non-maskable interrupts. 11.2.1 Undefined Instruction Interrupt The undefined instruction interrupt occurs when the UND instruction is executed. 11.2.2 Overflow Interrupt The overflow interrupt occurs when the O flag in the FLG register is set to "1" (overflow of arithmetic operation) and the INTO instruction is executed. Instructions to set the O flag are : ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX 11.2.3 BRK Interrupt The BRK interrupt occurs when the BRK instruction is executed. 11.2.4 BRK2 Interrupt The BRK2 interrupt occurs when the BRK2 instruction is executed. Do not use this interrupt. For development support tools only. 11.2.5 INT Instruction Interrupt The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can select software interrupt numbers 0 to 63. Software interrupt numbers 8 to 48, 52 to 54 and 57 are assigned to the vector table used for the peripheral function interrupt. Therefore, the microcomputer executes the same interrupt routine when the INT instruction is executed as when a peripheral function interrupt occurs. When the INT instruction is executed, the FLG register and PC are saved to the stack. PC also stores the relocatable vector of specified software interrupt numbers. Where the stack is saved varies depending on a software interrupt number. ISP is selected as the stack for software interrupt numbers 0 to 31 (setting the U flag to "0"). SP, which is set before the INT instruction is executed, is selected as the stack for software interrupt numbers 32 to 63 (the U flag is not changed). With the peripheral function interrupt, the FLG register is saved and the U flag is set to "0" (ISP select) when an interrupt request is acknowledged. With software interrupt numbers 32 to 48, 52 to 54 and 57, SP to be used varies depending on whether the interrupt is generated by the peripheral function interrupt request or by the INT instruction. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 108 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11.3 Hardware Interrupts Special interrupts and peripheral function interrupts are available as hardware interrupts. 11.3.1 Special Interrupts Special interrupts are non-maskable interrupts. ______ 11.3.1.1 NMI Interrupt ______ ______ The NMI interrupt occurs when a signal applied to the NMI pin changes from a high-level ("H") signal ______ to a low-level ("L") signal. Refer to 11.8 NMI Interrupt for details. 11.3.1.2 Watchdog Timer Interrupt The watchdog timer interrupt occurs when a count source of the watchdog timer underflows. Refer to 12. Watchdog Timer for details. 11.3.1.3 Oscillation Stop Detection Interrupt The oscillation stop detection interrupt occurs when the microcomputer detects a main clock oscillation stop. Refer to 9. Clock Generation Circuit for details. 11.3.1.4 Low Voltage Detection Interrupt The low voltage detection interrupt occurs when the voltage applied to VCC1 is above or below Vdet4. Refer to 6. Voltage Detection Circuit for details. NOTES: 1. Low voltage detection interrupt cannot be used in M32C/84T. 11.3.1.5 Single-Step Interrupt Do not use the single-step interrupt. For development support tool only. 11.3.1.6 Address Match Interrupt The address match interrupt occurs immediately before executing an instruction that is stored into an address indicated by the RMADi register (i=0 to 7) when the AIERi bit in the AIER register is set to "1" (address match interrupt enabled). Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur when a table data or addresses of the instruction other than the starting address, if the instruction has multiple addresses, is set. Refer to 11.10 Address Match Interrupt for details. 11.3.2 Peripheral Function Interrupt The peripheral function interrupt occurs when a request from the peripheral functions in the microcomputer is acknowledged. The peripheral function interrupts and software interrupt numbers 8 to 48, 52 to 54 and 57 for the INT instruction use the same interrupt vector table. The peripheral function interrupt is a maskable interrupt. See Table 11.2 about how the peripheral function interrupt occurs. Refer to the descriptions of each function for details. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 109 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11.4 High-Speed Interrupt The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt in three cycles. When the FSIT bit in the RLVL register is set to "1" (interrupt priority level 7 available for the high-speed interrupt), the ILVL2 to ILVL0 bits in the interrupt control registers can be set to "1112" (level 7) to use the high-speed interrupt. Only one interrupt can be set as the high-speed interrupt. When using the high-speed interrupt, do not set multiple interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to "0" (interrupt priority level 7 available for interrupts). Set the starting address of the high-speed interrupt routine in the VCT register. When the high-speed interrupt is acknowledged, the FLG register is saved into the SVF register and PC is saved into the SVP register. The program is executed from an address indicated by the VCT register. Execute the FREIT instruction to return from the high-speed interrupt routine. The values saved into the SVF and SVP registers are restored to the FLG register and PC by executing the FREIT instruction. The high-speed interrupt and the DMA2 and DMA3 use the same register. When using the high-speed interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can be used. 11.5 Interrupts and Interrupt Vectors There are four bytes in one vector. Set the starting address of interrupt routine in each vector table. When an interrupt request is acknowledged, the interrupt routine is executed from the address set in the interrupt vectors. Figure 11.2 shows the interrupt vector. MSB LSB Vector Address + 0 Vector Address + 1 Vector Address + 2 Vector Address + 3 Low-order bits of an address Middle-order bits of an address High-order bits of an address 0 0 16 Figure 11.2 Interrupt Vector Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 110 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11.5.1 Fixed Vector Tables The fixed vector tables are allocated addresses FFFFDC16 to FFFFFF16. Table 11.1 lists the fixed vector tables. Refer to 25.2 Functions to Prevent Flash Memory from Rewriting for fixed vectors of flash memory. Table 11.1 Fixed Vector Table Interrupt Generated by Undefined Instruction Overflow Vector Addresses Address (L) to Address (H) FFFFDC16 to FFFFDF16 FFFFE016 to FFFFE316 M32C/80 Series If the content of address FFFFE716 is Software Manual FF16, a program is executed from the address stored into software interrupt number 0 in the relocatable vector table Reserved space These addresses are used for the watchdog timer interrupt, oscillation stop detection interrupt, and low voltage detection interrupt(1) Reserved space Reset, Clock Generation Circuit, Watchdog Timer Remarks Reference BRK Instruction FFFFE416 to FFFFE716 Address Match - FFFFE816 to FFFFEB16 FFFFEC16 to FFFFEF16 Watchdog Timer FFFFF016 to FFFFF316 NMI Reset FFFFF416 to FFFFF716 FFFFF816 to FFFFFB16 FFFFFC16 to FFFFFF16 Reset NOTES: 1. Low voltage detection interrupt cannot be used in M32C/84T. 11.5.2 Relocatable Vector Tables The relocatable vector tables occupy 256 bytes from the starting address set in the INTB register. Table 11.2 lists the relocatable vector tables. Set an even address as the starting address of the vector table set in the INTB register to increase interrupt sequence execution rate. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 111 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts Table 11.2 Relocatable Vector Tables Interrupt Generated by BRK Instruction(2) Reserved Space DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 Transmission, NACK(3) Vector Table Address Address(L) to Address(H)(1) +0 to +3 (000016 to 000316) +4 to +31 (000416 to 001F16) +32 to +35 (002016 to 002316) +36 to +39 (002416 to 002716) +40 to +43 (002816 to 002B16) +44 to +47 (002C16 to 002F16) +48 to +51 (003016 to 003316) +52 to +55 (003416 to 003716) +56 to +59 (003816 to 003B16) +60 to +63 (003C16 to 003F16) +64 to +67 (004016 to 004316) +68 to +71 (004416 to 004716) +72 to +75 (004816 to 004B16) +76 to +79 (004C16 to 004F16) +80 to +83 (005016 to 005316) +84 to +87 (005416 to 005716) +88 to +91 (005816 to 005B16) +92 to +95 (005C16 to 005F16) +96 to +99 (006016 to 006316) +100 to +103 (006416 to 006716) 0 1 to 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Interrupt Timer B Serial I/O Timer A Software Interrupt Number M32C/80 Series Software Manual DMAC Reference UART0 Reception, ACK(3) UART1 Transmission, NACK(3) UART1 Reception, ACK (3) Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 ________ INT5 ________ +104 to +107 (006816 to 006B16) 26 +108 to +111 (006C16 to 006F16) 27 +112 to +115 (007016 to 007316) +116 to +119 (007416 to 007716) 28 29 INT4 ________ INT3 ________ INT2 ________ INT1 _______ +120 to +123 (007816 to 007B16) 30 +124 to +127 (007C16 to 007F16) 31 +128 to +131 (008016 to 008316) NACK(3) +132 to +135 (008416 to 008716) 32 33 Timer B Serial I/O INT0 Timer B5 UART2 Transmission, UART2 Reception, ACK(3) UART3 Transmission, NACK(3) +136 to +139 (008816 to 008B16) 34 +140 to +143 (008C16 to 008F16) 35 +144 to +147 (009016 to 009316) +148 to +151 (009416 to 009716) 36 37 UART3 Reception, ACK(3) UART4 Transmission, NACK(3) UART4 Reception, ACK(3) +152 to +155 (009816 to 009B16) 38 Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 112 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts Table 11.2 Relocatable Vector Tables (Continued) Interrupt Generated by Vector Table Address Address("L") to Address("H")(1) Software Interrupt Number Reference Serial I/O Bus Conflict Detect, Start Condition Detect, +156 to +159 (009C16 to 009F16) 39 Stop Condition Detect (UART2)(3) Bus Conflict Detect, Start Condition Detect, +160 to +163 (00A016 to 00A316) 40 Stop Condition Detect (UART3/UART0)(4) Bus Conflict Detect, Start Condition Select, +164 to +167 (00A416 to 00A716) 41 Stop Condition Detect(UART4/UART1)(4) A/D0 Key Input Intelligent I/O Interrupt 0 Intelligent I/O Interrupt 1 Intelligent I/O Interrupt 2 Intelligent I/O Interrupt 3 Intelligent I/O Interrupt 4 Reserved Space Intelligent I/O Interrupt 8 Intelligent I/O Interrupt 9, CAN 0 Intelligent I/O Interrupt 10, CAN 1 Reserved Space CAN 2 Reserved Space INT Instruction(2) +168 to +171 (00A816 to 00AB16) 42 +172 to +175 (00AC16 to 00AF16) 43 +176 to +179 (00B016 to 00B316) 44 +180 to +183 (00B416 to 00B716) 45 +184 to +187 (00B816 to 00BB16) 46 +188 to +191 (00BC16 to 00BF16) 47 +192 to +195 (00C016 to 00C316) 48 +196 to +207 (00C416 to 00CF16) 49 to 51 +208 to +211 (00D016 to 00D316) 52 +212 to +215 (00D416 to 00D716) 53 +216 to +219 (00D816 to 00DB16) 54 +220 to +227 (00DC16 to 00E316) 55, 56 +228 to +231 (00E416 to 00E716) 57 +232 to +255 (00E816 to 00FF16) 58 to 63 +0 to +3 (000016 to 000316) to +252 to +255 (00FC16 to 00FF16) NOTES: 1. These addresses are relative to those in the INTB register. 2. The I flag does not disable interrupts. 3. In I2C mode, NACK, ACK or start/stop condition detection causes interrupts to be generated. 0 to 63 A/D Converter Interrupts Intelligent I/O Intelligent I/O Intelligent I/O CAN CAN Interrupts 4. The IFSR6 bit in the IFSR register determines whether these addresses are used for an interrupt in UART0 or in UART3. The IFSR7 bit in the IFSR register determines whether these addresses are used for an interrupt in UART1 or in UART4. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 113 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11.6 Interrupt Request Acknowledgement Software interrupts and special interrupts occur when conditions to generate an interrupt are met. The peripheral function interrupts are acknowledged when all conditions below are met. • I flag = "1" • IR bit = "1" • ILVL2 to ILVL0 bits > IPL The I flag, IPL, IR bit and ILVL2 to ILVL0 bits are independent of each other. The I flag and IPL are in the FLG register. The IR bit and ILVL2 to ILVL0 bits are in the interrupt control register. 11.6.1 I Flag and IPL The I flag enables or disables maskable interrupts. When the I flag is set to "1" (enable), all maskable interrupts are enabled; when the I flag is set to "0" (disable), they are disabled. The I flag is automatically set to "0" after reset. IPL, consisting of three bits, indicates the interrupt priority level from level 0 to level 7. If a requested interrupt has higher priority level than indicated by IPL, the interrupt is acknowledged. Table 11.3 lists interrupt priority levels associated with IPL. Table 11.3 Interrupt Priority Levels IPL2 0 0 0 0 1 1 1 1 IPL1 0 0 1 1 0 0 1 1 IPL0 0 1 0 1 0 1 0 1 Interrupt Priority Levels Level 1 and above Level 2 and above Level 3 and above Level 4 and above Level 5 and above Level 6 and above Level 7 and above All maskable interrupts are disabled 11.6.2 Interrupt Control Register and RLVL Register The peripheral function interrupts use interrupt control registers to control each interrupt. Figures 11.3 and 11.4 show the interrupt control register. Figure 11.5 shows the RLVL register. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 114 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts Interrupt Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0IC to TA4IC TB0IC to TA5IC S0TIC to S4TIC S0RIC to S4RIC BCN0IC to BCN4IC DM0IC to DM3IC AD0IC KUPIC IIO0IC to IIO4IC Address 006C16, 008C16, 006E16, 008E16, 007016 009416, 007616, 009616, 007816, 009816, 006916 009016, 009216, 008916, 008B16, 008D16 007216, 007416, 006B16, 006D16, 006F16 007116, 009116, 008F16, 007116(1), 009116(2) 006816, 008816, 006A16, 008A16 007316 009316 After Reset XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 XXXX X0002 007516, 009516, 007716, 009716, 007916 IIO8IC to IIO10IC 007D16, 009D16, 007F16 CAN0IC0 to CAN2IC 009D16, 007F16, 008116(3) Bit Symbol ILVL0 Bit Name b2 b1 b0 Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 RW RW ILVL1 Interrupt Priority Level Select Bit RW ILVL2 RW IR Interrupt Request Bit 0 : No interrupt requested 1 : Interrupt requested(4) RW Nothing is assigned. When write, set to "0". (b7 - b4) When read, its content is indeterminate. NOTES: 1. The BCN0IC register shares an address with the BCN3IC register. 2. The BCN1IC register shares an address with the BCN4IC register. 3. The IIO9IC register shares an address with the CAN0IC register. The IIO10IC register shares an address with the CAN1IC register. 4. The IR bit can be set to "0" only (do not set to "1"). Figure 11.3 Interrupt Control Register (1) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 115 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts Interrupt Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol INT0IC to INT2IC INT3IC to INT5IC(1) Address 009E16, 007E16, 009C16 007C16, 009A16, 007A16 After Reset XX00 X0002 XX00 X0002 Bit Symbol ILVL0 Bit Name b2 b1 b0 Function 0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 RW RW ILVL1 Interrupt Priority Level Select Bit RW ILVL2 RW IR Interrupt Request Bit Polarity Switch Bit Level Sensitive/Edge Sensitive Switch Bit 0 : Requests no interrupt 1 : Requests an interrupt(2) 0 : Selects falling edge or "L"(3) 1 : Selects rising edge or "H" 0 : Edge sensitive 1 : Level sensitive(4) RW POL RW LVS RW (b7 - b6) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1. When a 16-bit data bus is used in microprocessor or memory expansion mode, each INT3 to INT5 pin is used as the data bus. Set the ILVL2 to ILVL0 bits in the INT3IC, INT4IC and INT5IC registers to "0002". 2. The IR bit can be set to "0" only (do not set to "1"). 3. Set the POL bit to "0" when a corresponding bit in the IFSR register is set to "1" (both edges). 4. When setting the LVS bit to "1" , set a corresponding bit in the IFSR register to "0" (one edge). Figure 11.4 Interrupt Control Register (2) 11.6.2.1 ILVL2 to ILVL0 Bits The ILVL2 to ILVL0 bits determines an interrupt priority level. The higher the interrupt priority level is, the higher the interrupt priority is. When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is acknowledged only when its interrupt priority level is higher than IPL. When the ILVL2 to ILVL0 bits are set to "0002" (level 0), its interrupt is ignored. 11.6.2.2 IR Bit The IR bit is automatically set to "1" (interrupt requested) when an interrupt request is generated. The IR bit is automatically set to "0" (no interrupt requested) after an interrupt request is acknowledged and an interrupt routine in the corresponding interrupt vector is executed. The IR bit can be set to "0" by program. Do not set to "1". Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 116 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts Exit Priority Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RLVL Address 009F16 After Reset XXXX 00002 Bit Symbol RLVL0 Bit Name b2 b1 b0 Function 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 RW RW RLVL1 Stop/Wait Mode Exit Minimum Interrupt Priority Level Control Bit(1) RW RLVL2 RW FSIT High-Speed Interrupt Set Bit(2) 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt RW (b4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMA II transfer(3) DMAII DMA II Select Bit(4) RW Nothing is assigned. When write, set to "0". (b7 - b6) When read, its content is indeterminate. NOTES: 1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in the FLG register. 2. When the FSIT bit is set to "1", an interrupt having the interrupt priority level 7 becomes the high-speed interrupt. In this case, set only one interrupt to the interrupt priority level 7 and the DMAII bit to "0". 3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1". Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0" when the DMAII bit to "1". 4. The DMAII bit becomes indeterminate after reset. To use the DMAII bit for an interrupt setting, set it to "0" before setting the interrupt control register. Figure 11.5 RLVL Register 11.6.2.3 RLVL2 to RLVL0 Bits When using an interrupt to exit stop or wait mode, refer to 9.5.2 Wait Mode and 9.5.3 Stop Mode for details. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 117 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11.6.3 Interrupt Sequence The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine execution. When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, in regards to the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT or RMPA instruction, if an interrupt request is generated while executing the instruction, the microcomputer suspends the instruction to start the interrupt sequence. The interrupt sequence is performed as follows: (1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address 00000016 (address 00000216 for the high-speed interrupt). Then, the IR bit applicable to the interrupt information is set to "0" (interrupt requested). (2) The FLG register, prior to an interrupt sequence, is saved to a temporary register(1) within the CPU. (3) Each bit in the FLG register is set as follows: • The I flag is set to "0" (interrupt disabled) • The D flag is set to "0" (single-step disabled) • The U flag is set to "0" (ISP selected) (4) A temporary register within the CPU is saved to the stack; or to the SVF register for the high-speed interrupt. (5) PC is saved to the stack; or to the SVP register for the high-speed interrupt. (6) The interrupt priority level of the acknowledged interrupt is set in IPL . (7) A relocatable vector corresponding to the acknowledged interrupt is stored into PC. After the interrupt sequence is completed, an instruction is executed from the starting address of the interrupt routine. NOTES: 1. Temporary register cannot be modified by users. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 118 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11.6.4 Interrupt Response Time Figure 11.6 shows an interrupt response time. Interrupt response time is the period between an interrupt generation and the execution of the first instruction in an interrupt routine. Interrupt response time includes the period between an interrupt request generation and the completed execution of an instruction ((a) on Figure 11.6) and the period required to perform an interrupt sequence ((b) on Figure 11.6). Interrupt request is generated Interrupt request is acknowledged Time Instruction (a) Interrupt sequence (b) Instruction in interrupt routine Interrupt response time (a) Period between an interrupt request generation and the completed execution of an instruction. (b) Period required to perform an interrupt sequence. Figure 11.6 Interrupt Response Time Time (a) varies depending on an instruction being executed. The DIVX instruction requires the longest time (a); 42 cycles when an immediate value or register is set as the divisor. When the divisor is a value in the memory, the following value is added. • Normal addressing :2+X • Index addressing :3+X • Indirect addressing : 5 + X + 2Y • Indirect index addressing : 6 + X + 2Y X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores indirect addresses. If X and Y are in an odd address or in 8-bit bus space, the X and Y value must be doubled. Table 11.4 lists time (b) shown Figure 11.6. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 119 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts Table 11.4 Interrupt Sequence Execution Time Interrupt Peripheral Function Interrupt Vector Address Even address Odd address(1) INT Instruction Even address Odd address(1) _______ 16-Bit Bus 14 cycles 16 cycles 12 cycles 14 cycles 13 cycles 8-Bit Bus 16 cycles 16 cycles 14 cycles 14 cycles 15 cycles NMI Watchdog Timer Undefined Instruction Address Match Overflow BRK Instruction (relocatable vector table) Even address(2) Even address(2) Even address Odd address(1) 14 cycles 17 cycles 19 cycles 19 cycles 5 cycles 16 cycles 19 cycles 19 cycles 21 cycles BRK Instruction (fixed vector table) High-Speed Interrupt Even address(2) Vector table is internal register NOTES: 1. Allocate interrupt vectors in even addresses. 2. Vectors are fixed to even addresses. 11.6.5 IPL Change when Interrupt Request is Acknowledged When a peripheral function interrupt request is acknowledged, IPL sets the priority level for the acknowledged interrupt. Software interrupts and special interrupts have no interrupt priority level. If an interrupt request that has no interrupt priority level is acknowledged, the value shown in Table 11.5 is set in IPL as the interrupt priority level. Table 11.5 Interrupts without Interrupt Priority Levels and IPL Interrupt Source _______ Level Set to IPL 7 0 Not changed Watchdog Timer, NMI, Oscillation Stop Detection, Low Voltage Detection Reset Software, Address Match NOTES: 1. Low voltage detection interrupt cannot be used in M32C/84T. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 120 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11.6.6 Saving a Register In the interrupt sequence, the FLG register and PC are saved to the stack. After the FLG register is saved to the stack, 16 high-order bits and 16 low-order bits of PC, extended to 32 bits, are saved to the stack. Figure 11.7 shows stack states before and after an interrupt request is acknowledged. Other important registers are saved by program at the beginning of an interrupt routine. The PUSHM instruction can save several registers(1) in the register bank used. Refer to 11.4 High-Speed Interrupt for the high-speed interrupt. NOTES: 1. Can be selected from the R0, R1, R2, R3, A0, A1, SB and FB registers. Address The Stack MSB LSB Address The Stack MSB LSB m-6 m-5 m–4 m–3 m–2 m–1 m m+1 Content of previous stack Content of previous stack [SP] SP value before an interrupt is generated m-6 m-5 m–4 m–3 m–2 m–1 m m+1 PCL PCM PCH 0016 FLGL FLGH Content of previous stack Content of previous stack [SP] New SP value Stack state before an interrupt request is acknowledged Stack state after an interrupt request is acknowledged Figure 11.7 Stack States 11.6.7 Restoration from Interrupt Routine When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC before the interrupt sequence is performed, which have been saved to the stack, are automatically restored. The program, executed before an interrupt request was acknowledged, starts running again. Refer to 11.4 HighSpeed Interrupt for the high-speed interrupt. Restore registers saved by program in an interrupt routine by the POPM instruction or others before the REIT and FREIT instructions. Register bank is switched back to the bank used prior to the interrupt sequence by the REIT or FREIT instruction. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 121 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11.6.8 Interrupt Priority If two or more interrupt requests are existed at the same sampling points (a timing to detect whether an interrupt request is generated or not), the interrupt with the highest priority is acknowledged. Set the ILVL2 to ILVL0 bits to select the desired priority level for maskable interrupts (peripheral function interrupt). Priority levels of special interrupts such as reset (reset has the highest priority) and watchdog timer are set by hardware. Figure 11.8 shows priority levels of hardware interrupts. The interrupt priority does not affect software interrupts. Executing instruction causes the microcomputer to execute an interrupt routine. Oscillation Stop Detection Reset > NMI > Watchdog > Peripheral Function > Address Match Low voltage Detection(1) _______ NOTES: 1. Low voltage detection interrupt cannot be used in M32C/84T. Figure 11.8 Interrupt Priority 11.6.9 Interrupt Priority Level Select Circuit The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt requests are existed at the same sampling point. Figure 11.9 shows the interrupt priority level select circuit. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 122 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts Hig h Each Interrupt Priority Level Level 0 (Initial Value) DMA0 DMA1 DMA2 DMA3 Timer A0 Each Interrupt Priority Level Timer A1 Timer A2 Timer A3 Timer A4 UART0 Transmission/NACK UART0 Reception/ACK UART1 Transmission/NACK UART1 Reception/ACK Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 INT5 INT4 INT3 INT2 IPL INT1 INT0 Timer B5 UART2 Transmission/ NACK UART2 Reception/ ACK UART3 Transmission/NACK UART3 Reception/ACK UART4 Transmission/ NACK UART4 Reception/ ACK Bus Conflict/Start, Stop Condition(UART2) Bus Conflict/Start, Stop Condition (UART0, UART3) Bus Conflict/Start, Stop Condition (UART1, UART4) I Flag Address Match Watchdog Timer, Oscillation Stop (1) Detection, Low Voltage Detection NMI DMAC II RLVL2 to RLVL0 Bits A/D0 Key Input Interrupt Intelligent I/O Interrupt 0 Intelligent I/O Interrupt 1 Intelligent I/O Interrupt 2 Intelligent I/O Interrupt 3 Intelligent I/O Interrupt 4 Intelligent I/O Interrupt 8 Intelligent I/O Interrupt 9 /CAN Interrupt 0 Intelligent I/O Interrupt 10 /CAN Interrupt 1 CAN Interrupt 2 Interrupt request priority detection results output (to the clock generation circuit) Interrupt request acknowledged (to CPU) NOTES: 1. Low voltage detection interrupt cannot be used in M32C/84T. Low Peripheral Function Interrupt Priority (if priority levels are the same) Figure 11.9 Interrupt Priority Level Select Circuit Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 123 of 495 M32C/84 Group (M32C/84, M32C/84T) ______ 11. Interrupts 11.7 INT Interrupt ______ External input generates the INTi interrupt (i = 0 to 5). The LVS bit in the INTiIC register selects either edge sensitive triggering to generate an interrupt on any edge or level sensitive triggering to generate an interrupt at an applied signal level. The POL bit in the INTiIC register determines the polarity. For edge sensitive, when the IFSRi bit in the IFSR register is set to "1", an interrupt occurs on both rising and falling edges of the external input. If the IFSRi bit is set to "1", set the POL bit in the corresponding register to "0" (falling edge). _______ For level sensitive, set the IFSRi bit to "0" (single edge). When the INTi pin input level reaches the level set _______ in the POL bit, the IR bit in the INTiIC register is set to "1". The IR bit remains unchanged even if the INTi _______ pin level is changed. The IR bit is set to "0" when the INTi interrupt is acknowledged or when the IR bit is written to "0" by program. Figure 11.10 shows the IFSR register. External Interrupt Request Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Bit Symbol Address 031F16 After Reset 0016 Bit Name INT0 Interrupt Polarity Select Bit(1) INT1 Interrupt Polarity Select Bit(1) INT2 Interrupt Polarity Select Bit(1) INT3 Interrupt Polarity Select Bit(1) INT4 Interrupt Polarity select bit(1) INT5 Interrupt Polarity Select Bit(1) UART0, UART3 Interrupt Source Select Bit UART1, UART4 Interrupt Source Select Bit Function 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges RW RW IFSR0 IFSR1 RW IFSR2 RW IFSR3 RW IFSR4 RW IFSR5 RW IFSR6 0 : UART3 bus conflict, start condition detect, stop condition detect RW 1 : UART0 bus conflict, start condition detect, stop condition detect 0 : UART4 bus conflict, start condition detect, stop condition detect RW 1 : UART1 bus conflict, start condition detect, stop condition detect IFSR7 NOTES: 1. Set this bit to "0" to select a level-sensitive triggering. When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge). Figure 11.10 IFSR Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 124 of 495 M32C/84 Group (M32C/84, M32C/84T) ______ 11. Interrupts 11.8 NMI Interrupt(1) ______ ______ The NMI interrupt occurs when a signal applied to the NMI pin changes from a high-level ("H") signal to a ______ ______ low-level ("L") signal. The NMI interrupt is a non-maskable interrupt. Although the P85/NMI pin is used as ______ the NMI interrupt input pin, the P8_5 bit in the P8 register indicates the input level for this pin. NOTES: ______ ______ ______ 1. When the NMI interrupt is not used, connect the NMI pin to VCC1 via a resistor. Because the NMI interrupt cannot be ignored, the pin must be connected. 11.9 Key Input Interrupt Key input interrupt request is generated when one of the signals applied to the P104 to P107 pins in input mode is on the falling edge. The key input interrupt can be also used as key-on wake-up function to exit wait or stop mode. To use the key input interrupt, do not use P104 to P107 as A/D input ports. Figure 11.11 shows a block diagram of the key input interrupt. When an "L" signal is applied to any pins in input mode, signals applied to other pins are not detected as an interrupt request signal. When the PSC_7 bit in the PSC register(2) is set to "1" (key input interrupt disabled), no key input interrupt occurs regardless of interrupt control register settings. When the PSC_7 bit is set to "1", no input from a port pin is available even when in input mode. NOTES: 2. Refer to 24. Programmable I/O Ports about the PSC register. PU31 Bit in PUR3 Register Pull-up Transistor PD10_7 Bit PSC_7 Bit P107/KI3 Pull-up Transistor P106/KI2 Pull-up Transistor P105/KI1 Pull-up Transistor P104/KI0 PD10_4 Bit PD10_6 Bit Interrupt Control Circuit Key Input Interrupt Request PD10_7 Bit KUPIC Register PD10_5 Bit Figure 11.11 Key Input Interrupt Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 125 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11.10 Address Match Interrupt The address match interrupt occurs immediately before executing an instruction that is stored into an address indicated by the RMADi register (i=0 to 7). The address match interrupt can be set in eight addresses. The AIERi bit in the AIER register determines whether the interrupt is enabled or disabled. The I flag and IPL do not affect the address match interrupt. Figure 11.12 shows registers associated with the address match interrupt. The starting address of an instruction must be set in the RMADi register. The address match interrupt does not occur when a table data or addresses other than the starting address of the instruction is set. Address Match Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol AIER Bit Symbol Address 000916 After Reset 0000 00002 Bit Name Address Match Interrupt 0 Enable Bit Address Match Interrupt 1 Enable Bit Address Match Interrupt 2 Enable Bit Address Match Interrupt 3 Enable Bit Address Match Interrupt 4 Enable Bit Address Match Interrupt 5 Enable Bit Address Match Interrupt 6 Enable Bit Address Match Interrupt 7 Enable Bit Function 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt 0 : Disables the interrupt 1 : Enables the interrupt RW RW AIER0 AIER1 RW AIER2 RW AIER3 RW AIER4 RW AIER5 RW AIER6 RW AIER7 RW Address Match Interrupt Register i (i=0 to 7) b23 b16 b15 b8 b7 b0 Symbol RMAD0 RMAD1 RMAD2 RMAD3 RMAD4 RMAD5 RMAD6 RMAD7 Address 001216 - 001016 001616 - 001416 001A16 - 001816 001E16 - 001C16 002A16 - 002816 002E16 - 002C16 003A16 - 003816 003E16 - 003C16 After Reset 00000016 00000016 00000016 00000016 00000016 00000016 00000016 00000016 Function Addressing Register for the Address Match Interrupt Setting Range 00000016 to FFFFFF16 RW RW Figure 11.12 AIER Register and RMAD0 to RMAD7 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 126 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts 11.11 Intelligent I/O Interrupt and CAN Interrupt The intelligent I/O interrupt and CAN interrupt are assigned to software interrupt numbers 44 to 48, 52 to 54, and 57. When using the intelligent I/O interrupt or CAN interrupt, set the IRLT bit in the IIOiIE register (i = 0 to 4, 8 to 11) to "1" (interrupt request for interrupt used). Various interrupt requests cause the intelligent I/O interrupt to occur. When an interrupt request is generated with each intelligent I/O or CAN functions, the corresponding bit in the IIOiIR register is set to "1" (interrupt requested). When the corresponding bit in the IIOiIE register is set to "1" (interrupt enabled), the IR bit in the corresponding IIOiIC register is set to "1" (interrupt requested). After the IR bit setting changes "0" to "1", the IR bit remains set to "1" when a bit in the IIOiIR register is set to "1" by another interrupt request and the corresponding bit in the IIOiIE register is set to "1". Bits in the IIOiIR register are not set to "0" automatically, even if an interrupt is acknowledged. Set each bit to "0" by program. If these bit settings are left "1", all generated interrupt requests are ignored. Figure 11.13 shows a block diagram of the intelligent I/O interrupt and CAN interrupt. Figure 11.14 shows the IIOiIR register. Figure 11.15 shows the IIOiIE register. IIOiIR Register(2) Bit 1 IRLT Bit in IIOiIE Register 0 1 0 Interrupt Request(1) Bit 2 Intelligent I/O Interrupt i Request Interrupt Request(1) 1 0 Bit 7 Interrupt Request(1) IIOiIE Register(3) Bit 1 1 Bit 2 Bit 7 NOTES: 1. See Figures 11.14 and 11.15 about bits 1 to 7 in the IIOiIR register and bits 1 to 7 in the IIOiIE register. 2. Bits 1 to 7 in the IIOiIR register are not set to "0" automatically even if an interrupt request is generated. Set to "0" by program. 3. Do not change the IRLT bit and the interrupt enable bit in the IIOiIE register simultaneously. i= 0 to 4, 8 to 11 Figure 11.13 Intelligent I/O Interrupt and CAN Interrupt Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 127 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts The CAN0j (j=0 to 2) interrupt is provided as the CAN interrupt. The following registers are required for the CAN interrupts: • Bits 7 in the IIO9IR to IIO11IR registers and Bits 7 in the IIO9IE to IIO11IE registers for the CAN00 to CAN02 interrupts. The CAN0IC and CAN1IC registers share addresses with the following registers: • The CAN0IC register shares an address with the IIO9IC register. • The CAN1IC register shares an address with the IIO10IC register. Refer to 23.4 CAN Interrupt for details. When using the intelligent I/O interrupt or CAN interrupt to activate DMAC II, set the IRLT bit in the IIOiIE register to "0" (interrupt request is used for DMAC, DMAC II) to enable the interrupt request that the IIOiIE register requires. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 128 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts Interrupt Request Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol Address See below After Reset 0000 000X2 IIO0IR to IIO4IR, IIO8IR to IIO11IR Bit Symbol Function Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 : Requests no interrupt 1 : Requests an interrupt(2) 0 : Requests no interrupt 1 : Requests an interrupt(2) Reserved bit. Set to "0". When read, its content is indeterminate. 0 : Requests no interrupt 1 : Requests an interrupt(2) 0 : Requests no interrupt 1 : Requests an interrupt(2) 0 : Requests no interrupt 1 : Requests an interrupt(2) 0 : Requests no interrupt 1 : Requests an interrupt(2) RW (b0) (Note 1) RW (Note 1) RW (b1) (Note 1) RW RW (Note 1) RW (Note 1) RW (Note 1) RW NOTES: 1. See table below for bit symbols. 2. Only "0" can be set (nothing is changed even if "1" is set). Bit Symbols for the Interrupt Request Register Symbol IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO8IR IIO9IR IIO10IR IIO11IR BT1R TM1jR PO1jR SIOiRR SIOiTR GiTOR GiRIR SRT1R CAN0kR Address 00A016 00A116 00A216 00A316 00A416 00A816 00A916 00AA16 00AB16 Bit 7 SRT0R CAN00R CAN01R CAN02R Bit 6 SRT1R Bit 5 SIO0RR SIO0TR SIO1RR SIO1TR Bit 4 G0RIR G0TOR G1RIR G1TOR BT1R Bit 3 Bit 2 TM13R/PO13R TM14R/PO14R TM12R/PO12R TM10R/PO10R TM17R/PO17R Bit 1 TM11R/PO11R TM15R/PO15R TM16R/PO16R Bit 0 - : Intelligent I/O Base Timer Interrupt Request : Intelligent I/O Time Measurement j Interrupt Request : Intelligent I/O Waveform Generating Function j Interrupt Request : Intelligent I/O Communication Unit i Receive Interrupt Request : Intelligent I/O Communication Unit i Transmit Interrupt Request : Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Request (TO: Output to Transmit) : Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Request (RI: Input to Receive) : Intelligent I/O Special Communication Function Interrupt Request : CAN0 Communication Function Interrupt Request (k = 0 to 2) : Reserved Bit. Set to "0". i = 0, 1 j = 0 to 7 Figure 11.14 IIO0IR to IIO4IR, IIO8IR to IIO11IR Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 129 of 495 M32C/84 Group (M32C/84, M32C/84T) 11. Interrupts Interrupt Enable Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address See below After Reset 0000 00002 0 IIO0IE to IIO4IE, IIO8IE to IIO11IE Bit Symbol Bit Name Interrupt Request Select Bit(2) Function 0 : Interrupt request is used for DMAC, DMAC II 1 : Interrupt request is used for interrupt RW RW IRLT (Note 1) 0 : Disables an interrupt by bit 1 in IIOiIR register RW 1 : Enables an interrupt by bit 1 in IIOiIR register 0 : Disables an interrupt by bit 2 in IIOiIR register RW 1 : Enables an interrupt by bit 2 in IIOiIR register Reserved Bit Set to "0" (Note 1) (b3) (Note 1) RW 0 : Disables an interrupt by bit 4 in IIOiIR register RW 1 : Enables an interrupt by bit 4 in IIOiIR register 0 : Disables an interrupt by bit 5 in IIOiIR register 1 : Enables an interrupt by bit 5 in IIOiIR register (Note 1) RW (Note 1) 0 : Disables an interrupt by bit 6 in IIOiIR register RW 1 : Enables an interrupt by bit 6 in IIOiIR register 0 : Disables an interrupt by bit 7 in IIOiIR register RW 1 : Enables an interrupt by bit 7 in IIOiIR register (Note 1) NOTES: 1. See table below for bit symbols. 2. If an interrupt request is used for interrupt, set bit 1, 2, 4 to 7 to "1" after the IRLT bit is set to "1". Bit Symbols for the Interrupt Enable Register Symbol IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO8IE IIO9IE IIO10IE IIO11IE BT1E TM1jE PO1jE SIOiRE SIOiTE GiRIE GiTOE SRTiE CAN0kE Address 00B016 00B116 00B216 00B316 00B416 00B816 00B916 00BA16 00BB16 Bit 7 SRT0E CAN00E CAN01E CAN02E Bit 6 SRT1E Bit 5 SIO0RE SIO0TE SIO1RE SIO1TE - Bit 4 G0RIE G0TOE G1RIE G1TOE BT1E - Bit 3 - Bit 2 TM13E/PO13E TM14E/PO14E TM12E/PO12E TM10E/PO10E TM17E/PO17E - Bit 1 TM11E/PO11E TM15E/PO15E TM16E/PO16E - Bit 0 IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT - : Intelligent I/O Base Timer Interrupt Enabled : Intelligent I/O Time Measurement j Interrupt Enabled : Intelligent I/O Waveform Generating Function j Interrupt Enabled : Intelligent I/O Communication Unit i Receive Interrupt Enabled : Intelligent I/O Communication Unit i Transmit Interrupt Enabled : Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Enabled (RI: Output to Receive) : Intelligent I/O Communication Unit i HDLC Data Processing Function Interrupt Enabled (TO: Input to Transmit) : Intelligent I/O Special Communication Function Interrupt Enabled i = 0, 1 : CAN0 Communication Function Interrupt Enabled (k = 0 to 2) j = 0 to 7 : Reserved Bit. Set to "0". Figure 11.15 IIO0IE to IIO4IE, IIO8IE to IIO11IE Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 130 of 495 M32C/84 Group (M32C/84, M32C/84T) 12. Watchdog Timer 12. Watchdog Timer The watchdog timer monitors the program executions and detects defective program. It allows the microcomputer to trigger a reset or to generate an interrupt if the program error occurs. The watchdog timer contains a 15-bit counter, which is decremented by the CPU clock that the prescaler divides. The CM06 bit in the CM0 register determines whether a watchdog timer interrupt request or reset is generated if the watchdog timer underflows. The CM06 bit can only be set to "1" (reset). Once the CM06 bit is set to "1", it cannot be changed to "0" ( watchdog timer interrupt) by program. The CM06 bit is set to "0" only after reset. When the main clock, on-chip oscillator clock, or PLL clock runs as the CPU clock, the WDC7 bit in the WDC register determine whether the prescaler divides the clock by 16 or by 128. When the sub clock runs as the CPU clock, the prescaler divides the clock by 2 regardless of the WDC7 bit setting. Watchdog timer cycle is calculated as follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle. When the main clock, on-chip oscillator clock, or PLL clock is selected as the CPU clock, Watchdog timer cycle = Divide-by-16 or -128 prescaler x counter value of watchdog timer (32768) CPU clock Divide-by-2 prescaler x counter value of watchdog timer (32768) CPU clock When the sub clock is selected as the CPU clock, Watchdog timer cycle = For example, if the CPU clock frequency is 30MHz and the prescaler divides it by 16, the watchdog timer cycle is approximately 17.5 ms. The watchdog timer is reset when the WDTS register is set and when a watchdog timer interrupt request is generated. The prescaler is reset only when the microcomputer is reset. Both watchdog timer and prescaler stop after reset. They begin counting when the WDTS register is set. The watchdog timer and prescaler stop in stop mode, wait mode and hold state. They resume counting from the value held when the mode or state is exited. Figure 12.1 shows a block diagram of the watchdog timer. Figure 12.2 shows registers associated with the watchdog timer. Prescaler CM07 = 0 WDC7 = 0 1/16 CPU Clock HOLD Signal 1/128 CM07 = 0 WDC7 = 1 PM22 = 0 CM06 = 0 CM07 = 1 Watchdog Timer Interrupt Request 1/2 Watchdog Timer Reset CM06 = 1 On-chip Oscillator Clock Write to WDTS Register PM22 = 1 Set to 7FFF16 Internal Reset Signal CM06, CM07 : Bits in the CM0 Register WDC7 : Bit in the WDC Register PM22 : Bit in the PM2 Register Figure 12.1 Watchdog Timer Block Diagram Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 131 of 495 M32C/84 Group (M32C/84, M32C/84T) 12. Watchdog Timer Watchdog Timer Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol WDC Address 000F16 After Reset 000X XXXX2 Bit Symbol (b4 - b0) WDC5 Bit Name High-Order Bit of the Watchdog Timer Cold Start-up/ Warm Start-up Determine Flag(1,2, 3) Reserved Bit Function RW RO 0 : Cold start-up 1 : Warm start-up Set to "0" 0 : Divide-by-16 1 : Divide-by-128 RW (b6) WDC7 RW Prescaler Select Bit RW NOTES: 1. The WDC5 bit remains set to "1", regardless of setting to "1" or "0". 2. The WDC5 bit is set to "0" when power is turned on and can be set to "1" by program only. 3. The WDC5 bit maintains a value set before reset, even after reset has been performed. Watchdog Timer Start Register(1) b7 b0 Symbol WDTS Address 000E16 After Reset Indeterminate Function The watchdog timer is reset to start counting by a write instruction to the WDTS register. Default value of the watchdog timer is always set to "7FFF16" regardless of the value written. NOTES: 1. Write the WDTS register after the watchdog timer interrupt is generated. RW WO Figure 12.2 WDC Register and WDTS Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 132 of 495 M32C/84 Group (M32C/84, M32C/84T) 12. Watchdog Timer System Clock Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol CM0 Address 000616 After Reset 0000 10002 Bit Symbol CM00 Bit Name b1 b0 Function 0 0 : I/O port P53 0 1 : Outputs fC 1 0 : Outputs f8 1 1 : Outputs f32 RW RW Clock Output Function Select Bit(2) CM01 RW CM02 0 : Peripheral clock does not stop in In Wait Mode, Peripheral wait mode RW Function Clock Stop Bit(9) 1 : Peripheral clock stops in wait (3) mode XCIN-XCOUT Drive Capacity Select Bit(11) Port XC Switch Bit Main Clock (XIN-XOUT) Stop Bit(5, 9) Watchdog Timer Function Select Bit CPU Clock Select Bit 0(8, 9, 10) 0 : Low 1 : High RW CM03 CM04 0 : I/O port function RW 1 : XCIN-XCOUT oscillation function(4) 0 : Main clock oscillates 1 : Main clock stops(6) 0 : Watchdog timer interrupt 1 : Reset(7) 0: Clock selected by the CM21 bit divided by MCD register setting 1: Sub clock RW CM05 CM06 RW CM07 RW NOTES: 1. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable). 2. When the PM07 bit in the PM0 register is set to "0" (BCLK output), set the CM01 and CM00 bits to "002". When the PM15 and PM14 bits in the PM1 register are set to "012" (ALE output to P53), set the CM01 and CM00 bits to "002". When the PM07 bit is set to "1" (function selected in the CM01 and CM00 bits) in microprocessor or memory expansion mode, and the CM01 and CM00 bits are set to "002", an "L" signal is output from port P53 (port P53 does not function as an I/O port). 3. fc32 does not stop running. When the CM02 bit is set to "1", the PLL clock cannot be used in wait mode. 4. When setting the CM04 bit is set to "1", set the PD8_7 and PD8_6 bits in the PD8 register to "002" (port P87 and P86 in input mode) and the PU25 bit in the PUR2 register to "0" (no pull-up). 5. When entering low-power consumption mode or on-chip oscillator low-power consumption mode, the CM05 bit stops running the main clock. The CM05 bit cannot detect whether the main clock stops or not. To stop running the main clock, set the CM05 bit to "1" after the CM07 bit is set to "1" with a stable sub clock oscillation or after the CM21 bit in the CM2 register is set to "1" (on-chip oscillator clock). When the CM05 bit is set to "1", the clock applied to XOUT becomes "H". The built-in feedback resistor remains ON. XIN is pulled up to XOUT ("H" level) via the feedback resistor. 6. When the CM05 bit is set to "1", the MCD4 to MCD0 bits in the MCD register are set to "010002" (divide-by-8 mode). In on-chip oscillation mode, the MCD4 to MCD0 bits are not set to "010002" even if the CM05 bit terminates XIN-XOUT. 7. Once the CM06 bit is set to "1", it cannot be set to "0" by program. 8. After the CM04 bit is set to "1" with a stable sub clock oscillation, set the CM07 bit to "1" from "0". After the CM05 bit is set to "0" with a stable main clock oscillation, set the CM07 bit to "0" from "1". Do not set the CM07 bit and CM04 or CM05 bit simultaneously. 9. When the PM21 bit in the PM2 register is set to "1" (clock change disable), the CM02, CM05 and CM07 bits do not change even when written. 10. After the CM07 bit is set to "0", set the PM21 bit to "1". 11. When stop mode is entered, the CM03 bit is set to "1". Figure 12.3 CM0 Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 133 of 495 M32C/84 Group (M32C/84, M32C/84T) 12. Watchdog Timer 12.1 Count Source Protection Mode In count source protection mode, the on-chip oscillator clock is used as a count source for the watchdog timer. The count source protection mode allows the on-chip oscillator clock to run continuously, maintaining watchdog timer operation even if the program error occurs and the CPU clock stops running. Follow the procedures below when using this mode. (1) Set the PRC0 bit in the PRCR register to "1" (write to CM0 register enabled) (2) Set the PRC1 bit in the PRCR register to "1" (write to PM2 register enabled) (3) Set the CM06 bit in the CM0 register to "1" (reset when the watchdog timer overflows) (4) Set the PM22 bit in the PM2 register to "1" (the on-chip oscillator clock as a count source of the watchdog timer) (5) Set the PRC0 bit to "0" (write to CM0 register disabled) (6) Set the PRC1 bit to "0" (write to PM2 register disabled) (7) Write to the WDTS register (the watchdog timer starts counting) The followings will occur when the PM22 bit is set to "1". • The on-chip oscillator starts oscillating and the on-chip oscillator clock becomes a count source for the watchdog timer. Watchdog timer cycle = Counter value of watchdog timer (32768) On-chip oscillator clock • Write to the CM10 bit in the CM1 register is disabled. (The bit setting remains unchanged even if set it to "1". The microcomputer does not enter stop mode.) • In wait mode or hold state, the watchdog timer continues running. However, the watchdog timer interrupt cannot be used to exit wait mode. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 134 of 495 M32C/84 Group (M32C/84, M32C/84T) 13. DMAC 13. DMAC This microcomputer contains four DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC transmits a 8- or 16-bit data from a source address to a destination address whenever a transmit request occurs. DMA0 and DMA1 must be prioritized if using DMAC. DMA2 and DMA3 share registers required for high-speed interrupts. High-speed interrupts cannot be used when using three or more DMAC channels. The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU. The cycle-steal method employed on DMAC enables high-speed operation between a transfer request and the complete transmission of 16-bit (word) or 8-bit (byte) data. Figure 13.1 shows a mapping of registers to be used for DMAC. Table 13.1 lists specifications of DMAC. Figures 13.2 to 13.5 show registers associated with DMAC. Because the registers shown in Figure 13.1 are allocated in the CPU, use the LDC instruction to write to the registers. To set the DCT2, DCT3, DRC2, DRC3, DMA2 and DMA3 registers, set the B flag to "1" (register bank 1) and set the R0 to R3, A0 and A1 registers with the MOV instruction. To set the DSA2 and DSA3 registers, set the B flag to "1" and set the SB and FB registers with the LDC instruction. To set the DRA2 and DRA3 registers, set the SVP and VCT registers with the LDC instruction. DMAC-Associated Registers DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DSA0 DSA1 DRA0 DRA1 DMA Mode Register 0 DMA Mode Register 1 DMA 0 Transfer Count Register DMA 1 Transfer Count Register DMA 0 Transfer Count Reload Register(1) DMA 1 Transfer Count Reload Register(1) DMA 0 Memory Address Register DMA 1 Memory Address Register DMA 0 SFR Address Register DMA 1 SFR Address Register DMA 0 Memory Address Reload Register(1) DMA 1 Memory Address Reload Register(1) When Three or More DMAC Channels are Used, the Register Bank 1 is Used as DMAC Registers DCT2 (R0) DCT3 (R1) DRC2 (R2) DRC3 (R3) DMA2 (A0) DMA3 (A1) DSA2 (SB) DSA3 (FB) DMA2 Transfer Count Register DMA3 Transfer Count Register DMA2 Transfer Count Reload Register(1) DMA3 Transfer Count Reload Register(1) DMA2 Memory Address Register DMA3 Memory Address Register DMA2 SFR Address Register DMA3 SFR Address Register When Three or More DMAC Channels are Used, the High-Speed Interrupt Register is Used as DMAC Registers SVF DRA2 (SVP) DRA1 (VCT) Flag Save Register DMA2 Memory Address Reload Register(1) DMA3 Memory Address Reload Register(1) When using DMA2 and DMA3, use the CPU registers shown in parentheses (). NOTES: 1. Registers are used for repeat transfer, not for single transfer. Figure 13.1 Register Mapping for DMAC Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 135 of 495 M32C/84 Group (M32C/84, M32C/84T) 13. DMAC DMAC starts a data transfer by setting the DSR bit in the DMiSL register (i=0 to 3) or by using an interrupt request, generated by the functions determined by the DSEL 4 to DSEL0 bits in the DMiSL register, as a DMA request. Unlike interrupt requests, the I flag and interrupt control register do not affect DMA. Therefore, a DMA request can be acknowledged even if an interrupt is disabled and cannot be acknowledged. In addition, the IR bit in the interrupt control register does not change when a DMA request is acknowledged. Table 13.1 DMAC Specifications Specification Channels 4 channels (cycle-steal method) Transfer Memory Space • From a desired address in a 16-Mbyte space to a fixed address in a 16-Mbyte space • From a fixed address in a 16-Mbyte space to a desired address in a 16-Mbyte space Maximum Bytes Transferred 128 Kbytes (when a 16-bit data is transferred) or 64 Kbytes (with an 8bit data is transferred) ________ ________ DMA Request Source(1) Falling edge or both edges of signals applied to the INT0 to INT3 pins Timers A0 to A4 interrupt requests Timers B0 to B5 interrupt requests UART0 to UART4 transmit and receive interrupt requests A/D0 conversion interrupt request Intelligent I/O interrupt request CAN interrupt request Software trigger Channel Priority DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has highest priority) Transfer Unit 8 bits, 16 bits Destination Address Forward/fixed (forward and fixed directions cannot be specified when specifying source and destination addresses simultaneously) Transfer Mode Single Transfer Transfer is completed when the DCTi register (i = 0 to 3) is set to "000016" Repeat Transfer When the DCTi register is set to "000016", the value of the DRCi register is reloaded into the DCTi register and the DMA transfer is continued DMA Interrupt Request Generation Timing When the DCTi register changes "000116" to "000016" DMA Startup Single Transfer DMA starts when a DMA request is generated after the DCTi register is set to "000116" or more and the MDi1 and MD0 bits in the DMDj register (j = 0, 1) are set to "012" (single transfer) Repeat Transfer DMA starts when a DMA request is generated after the DCTi register is set to "000116" or more and the MDi1 and MD0 bits are set to "11 2" (repeat transfer) DMA Stop Single Transfer DMA stops when the MDi1 and MDi0 bits are set to "002" (DMA disabled) and the DCTi register is set to "000016" (0 DMA transfer) by DMA transfer or write Repeat Transfer DMA stops when the MDi1 and MDi0 bits are set to "002" and the DCTi register is set to "000016" and the DRCi register set to "000016" Reload Timing to the DCTi When the DCTi register is set to "000016" from "000116" in repeat transor DMAi Register fer mode DMA Transfer Cycles Minimum 3 cycles between SFR and internal RAM NOTES: 1. The IR bit in the interrupt control register does not change when a DMA request is acknowledged. Item Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 136 of 495 M32C/84 Group (M32C/84, M32C/84T) 13. DMAC DMAi Request Source Select Register (i=0 to 3) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address DM0SL to DM3SL 037816, 037916, 037A16, 037B16 Bit Symbol After Reset 0X00 00002 Bit Name Function RW RW RW DSEL0 DSEL1 DSEL2 DSEL3 DSEL4 Software DMA Request Bit(2) DMA Request Source Select Bit(1) See Table 13.2 for the DMiSL register (i = 0 to 3) function RW RW RW DSR When a software trigger is selected, a DMA request is generated by RW setting this bit to "1" (When read, its content is always "0") When read, its content is indeterminate 0 : Not requested 1 : Requested RO Reserved Bit (b6) DRQ DMA Request Bit(2, 3) RW NOTES: 1. Change the DSEL4 to DSEL0 bit settings while the MDi1 and MDi0 bits in the DMD0 and DMD1 registers are set to "002" (DMA disabled). Also, set the DRQ bit to "1" simultaneously when the DSEL4 to DSEL0 bit settings are changed. e.g., MOV.B #083h, DMiSL ; Set timer A0 2. When the DSR bit is set to "1", set the DRQ bit to "1" simultaneously. e.g., OR.B #0A0h, DMiSL 3. Do not set the DRQ bit to "0". Figure 13.2 DM0SL to DM3SL Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 137 of 495 M32C/84 Group (M32C/84, M32C/84T) 13. DMAC Table 13.2 DMiSL Register (i = 0 to 3) Function Setting Value b4 b3 b2 b1 b0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Intelligent I/O Interrupt 0 Request Intelligent I/O Interrupt 1 Request Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request Intelligent I/O Interrupt 4 Request Intelligent I/O Interrupt 8 Request Intelligent I/O Interrupt 9 Request(4) Intelligent I/O Interrupt 10 Request CAN Interrupt 2 Request Intelligent I/O Interrupt 0 Request Intelligent I/O Interrupt 1 Request Intelligent I/O Interrupt 8 Request (5) DMA Request Source DMA0 DMA1 Software trigger Falling Edge of INT0 Both Edges of INT0 Falling Edge of INT1 Both Edges of INT1 Falling Edge of INT2 Both Edges of INT2 Falling Edge of INT3(1,2) Both Edges of INT3(1,2) DMA2 DMA3 Timer A0 Interrupt Request Timer A1 Interrupt Request Timer A2 Interrupt Request Timer A3 Interrupt Request Timer A4 Interrupt Request Timer B0 Interrupt Request Timer B1 Interrupt Request Timer B2 Interrupt Request Timer B3 Interrupt Request Timer B4 Interrupt Request Timer B5 Interrupt Request UART0 Transmit Interrupt Request UART0 Receive or ACK Interrupt Request(3) UART1 Transmit Interrupt Request UART1 Receive or ACK Interrupt Request(3) UART2 Transmit Interrupt Request UART2 Receive or ACK Interrupt Request(3) UART3 Transmit Interrupt Request UART3 Receive or ACK Interrupt Request(3) UART4 Transmit Interrupt Request UART4 Receive or ACK Interrupt Request(3) A/D0 Interrupt Request Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request Intelligent I/O Interrupt 4 Request Intelligent I/O Interrupt 9 Request(4) Intelligent I/O Interrupt 10 Request(5) CAN Interrupt 2 Request Intelligent I/O Interrupt 0 Request Intelligent I/O Interrupt 1 Request Intelligent I/O Interrupt 2 Request Intelligent I/O Interrupt 3 Request NOTES: 1. If the INT3 pin is used for data bus in memory expansion mode or microprocessor mode, a DMA3 interrupt request cannot be generated by a signal applied to the INT3 pin. 2. The falling edge and both edges of a signal applied to the INTj pin (j=0 to 3) cause a DMA request generation. The INT interrupt (the POL bit in the INTjlC register, the LVS bit, the IFSR register) is not affected and vice versa. 3. Use the UkSMR register and UkSMR2 register (k=0 to 4) to switch between the UARTk receive and the ACK interrupt as a DMA request source. To use the ACK interrupt for a DMA reqest, set the IICM bit in the UkSMR register to "1" and the IICM2 bit in the UkSMR2 register to "0". 4. The same setting is used to generate an intelligent I/O interrupt 9 request and a CAN interrupt 0 request. 5. The same setting is used to generate an intelligent I/O interrupt 10 request and a CAN interrupt 1 request. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 138 of 495 M32C/84 Group (M32C/84, M32C/84T) 13. DMAC DMA Mode Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMD0 Bit Symbol Address (CPU Internal Register) After Reset 0016 Bit Name b1 b0 Function 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer 0 : 8 bits 1 : 16 bits RW RW MD00 Channel 0 Transfer Mode Select Bit MD01 Channel 0 Transfer Unit Select Bit Channel 0 Transfer Direction Select Bit RW BW0 RW RW0 0 : Fixed address to memory (forward direction) RW 1 : Memory (forward direction) to fixed address b5 b4 MD10 Channel 1 Transfer Mode Select Bit MD11 Channel 1 Transfer Unit Select Bit Channel 1 Transfer Direction Select Bit 0 0 : DMA disabled 0 1 : Single transfer 1 0 : Do not set to this value 1 1 : Repeat transfer 0 : 8 bits 1 : 16 bits RW RW BW1 RW RW1 0 : Fixed address to memory (forward direction) RW 1 : Memory (forward direction) to fixed address NOTES: 1. Use the LDC instruction to set the DMD0 register. DMA Mode Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol DMD1 Bit Symbol Address (CPU internal register) After Reset 0016 Bit Name b1 b0 Function RW RW MD20 MD21 0 0 : DMA disabled Channel 2 Transfer 0 1 : Single transfer Mode Select Bit 1 0 : Do not set to this value 1 1 : Repeat transfer Channel 2 Transfer 0 : 8 bits 1 : 16 bits Unit Select Bit RW BW2 RW RW2 Channel 2 Transfer 0 : Fixed address to memory (forward direction) RW Direction Select Bit 1 : Memory (forward direction) to fixed address b5 b4 MD30 MD31 0 0 : DMA disabled Channel 3 Transfer 0 1 : Single transfer Mode Select Bit 1 0 : Do not set to this value 1 1 : Repeat transfer Channel 3 Transfer 0 : 8 bits 1 : 16 bits Unit Select Bit RW RW BW3 RW3 RW Channel 3 Transfer 0 : Fixed address to memory (forward direction) RW Direction Select Bit 1 : Memory (forward direction) to fixed address NOTES: 1. Use the LDC instruction to set the DMD1 register. Figure 13.3 DMD0 and DMD1 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 139 of 495 M32C/84 Group (M32C/84, M32C/84T) 13. DMAC DMAi Transfer Count Register (i=0 to 3) b15 b8 b7 b0 Symbol DCT0(2) DCT1(2) DCT2(bank1;R0)(3) DCT3(bank1;R1)(4) Address (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) After Reset XXXX16 XXXX16 000016 000016 Function Set the number of transfers Setting Range 000016 to FFFF16(1) RW RW NOTES: 1. When the DCTi register is set to "000016", no data transfer occurs regardless of a DMA request. 2. Use the LDC instruction to set the DCT0 and DCT1 registers. 3. To set the DCT2 register, set the B flag in the FLG register to "1" (register bank 1) and set the R0 register. Use the MOV instruction to set the R0 register. 4. To set the DCT3 register, set the B flag to "1" and set R1 register. Use the MOV instruction to set the R1 register. DMAi Transfer Count Reload Register (i=0 to 3) b15 b8 b7 b0 Symbol DRC0(1) DRC1(1) DRC2(bank1;R2)(2) DRC3(bank1;R3)(3) Address (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) After Reset XXXX16 XXXX16 000016 000016 Function Set the number of transfers Setting Range 000016 to FFFF16 RW RW NOTES: 1. Use the LDC instruction to set the DRC0 and DRC1 registers. 2. To set the DRC2 register, set the B flag in the FLG register to "1" (register bank 1) and set the R2 register. Use the MOV instruction to set the R2 register. 3. To set the DRC3 register, set the B flag to "1" and set R3 register. Use the MOV instruction to set the R3 register. Figure 13.4 DCT0 to DCT3 Registers and DRC0 to DRC3 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 140 of 495 M32C/84 Group (M32C/84, M32C/84T) 13. DMAC DMAi Memory Address Register (i=0 to 3) b23 b16 b15 b8 b7 b0 Symbol DMA0(2) DMA1(2) DMA2(bank1;A0)(3) DMA3(bank1;A1)(4) Address (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) After Reset XXXXXX16 XXXXXX16 00000016 00000016 Function Set a source memory address or destination memory address(1) Setting Range 00000016 to FFFFFF16 (16-Mbyte space) RW RW NOTES: 1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1)is set to "0" (fixed address to memory), a destination address is selected. When the RWk bit is set to "1" (memory to fixed address), a source address is selected. 2. Use the LDC instruction to set the DMA0 and DMA1 registers. 3. To set the DMA2 register, set the B flag in the FLG register to "1" (register bank 1) and set the A0 register. Use the MOV instruction to set the A0 register. 4. To set the DMA3 register, set the B flag to "1" and set the A1 register. Use the MOV instruction to set the A1 register. DMAi SFR Address Register (i=0 to 3) b23 b16 b15 b8 b7 b0 Symbol DSA0(2) DSA1(2) DSA2(bank1;SB)(3) DSA3(bank1;FB)(4) Address (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) After Reset XXXXXX16 XXXXXX16 00000016 00000016 Function Set a source fixed address or destination fixed address(1) Setting Range 00000016 to FFFFFF16 (16-Mbyte space) RW RW NOTES: 1. When the RWk bit (k=0 to 3) in the DMDj register (j=0, 1) is set to "0" (fixed address to memory), a source address is selected. When the RWk bit is set to "1" (memory to fixed address), a destination address is selected. 2. Use the LDC instruction to set the DSA0 and DSA1 registers. 3. To set the DSA2 register, set the B flag in the FLG register to "1" (register bank 1) and the set the SB register. Use the LDC instruction to set the DSA2 register. 4. To set the DSA3 register, set the B flag to "1" and set the FB register. Use the LDC instruction to set the DSA3 register. DMAi Memory Address Reload Register(1) (i=0 to 3) b23 b16 b15 b8 b7 b0 Symbol DRA0 DRA1 DRA2(SVP)(2) DRA3(VCT)(3) Address (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) (CPU Internal Register) After Reset XXXXXX16 XXXXXX16 XXXXXX16 XXXXXX16 Function Set a source memory address or destination memory address(1) NOTES: 1. Use the LDC instruction to set the DRA0 and DRA1 registers. 2. To set the DRA2 register, set the SVP register. 3. To set the DRA3 register, set the VCT register. Setting Range 00000016 to FFFFFF16 (16-Mbyte space) RW RW Figure 13.5 DMA0 to DMA3 Registers, DSA0 to DSA3 Registers and DRA0 to DRA3 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 141 of 495 M32C/84 Group (M32C/84, M32C/84T) 13. DMAC 13.1 Transfer Cycle Transfer cycle contains a bus cycle to read data from a memory or the SFR area (source read) and a bus cycle to write data to a memory space or the SFR area (destination write). The number of read and write bus cycles depends on source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on DS register setting. Software wait state ________ insertion and the RDY signal make a bus cycle longer. 13.1.1 Effect of Source and Destination Addresses When a 16-bit data is transferred with a 16-bit data bus and a source address starting with an odd address, source read cycle is incremented by one bus cycle, compared to a source address starting with an even address. When a 16-bit data is transferred with a 16-bit data bus and a destination address starting with an odd address, a destination write cycle is incremented by one bus cycle, compared to a destination address starting with an even address. 13.1.2 Effect of the DS Register In an external space in memory expansion or microprocessor mode, transfer cycle varies depending on the data bus used at the source and destination addresses. See Figure 8.1 for details about the DS register. • When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing both source address and destination address, is used to transfer a 16-bit data, 8-bit data is transferred twice. Therefore, two bus cycles are required to read the data and another two bus cycles to write the data. • When an 8-bit data bus (the DSi bit in the DS register is set to "0" (i=0 to 3)), accessing source address, and a 16-bit data bus, accessing destination address, are used to transfer a 16-bit data, 8bit data is read twice but is written once as 16-bit data. Therefore, two bus cycles are required for reading and one bus cycle is for writing. • When a 16-bit data bus, accessing source address, and an 8-bit data bus, accessing destination address, are used to transfer a 16-bit data, 16-bit data is read once and 8-bit data is written twice. Therefore, one bus cycle is required for reading and two bus cycles is for writing. 13.1.3 Effect of Software Wait State When the SFR area or memory space with software wait states is accessed, the number of CPU clock cycles is incremented by software wait states. Figure 13.6 shows an example of a transfer cycle for the source-read bus cycle. In Figure 13.6, the number of source-read bus cycles is illustrated under different conditions, provided that the destination address is an address of an external space with the destination-write cycle as two CPU clock cycles (=one bus cycle). In effect, the destination-write bus cycle is also affected by each condition and the transfer cycles change accordingly. To calculate a transfer cycle, apply respective conditions to both destination-write bus cycle and source-read bus cycle. As shown in example (2) of Figure 13.6, when an 8-bit data bus, accessing both source and destination addresses, is used to transfer a 16-bit data, two bus cycles each are required for the source-read bus cycle and destination-write bus cycle. ________ 13.1.4 Effect of RDY Signal ________ In memory expansion or microprocessor mode, the RDY signal affects a bus cycle if a source address or _______ destination address is allocated address in an external space. Refer to 8.2.6 RDY Signal for details. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 142 of 495 M32C/84 Group (M32C/84, M32C/84T) 13. DMAC (1) When 8-bit data is transferred or when 16-bit data is transferred with a 16-bit data bus from an even source address CPU Clock Address Bus RD Signal WR Signal Data bus CPU Use Source Destination CPU Use CPU Use Source Destination CPU Use (2) When 16-bit data is transferred from an odd source address or when 16-bit data is transferred and 8-bit bus is used to access a source address CPU Clock CPU Clock Address Bus RD Signal WR Signal Data Bus CPU Use Source Source + 1 Destination CPU Use CPU Use Source Source + 1 Destination CPU Use (3) When one wait state is inserted into the source-read bus cycle under the conditions in (1) CPU Clock Address Bus RD Signal WR Signal Data Bus CPU Use Source Destination CPU Use CPU Use Source Destination CPU Use (4) When one wait state is inserted into the source-read bus cycle under the conditions in (2) CPU Clock Address Bus RD Signal WR Signal Data Bus CPU Use Source Source + 1 Destination CPU Use CPU Use Source Source + 1 Destination CPU Use NOTES: 1. The above applies when the destination-write bus cycle is 2 CPU clock cycles (=1 bus cycle). However, if the destination-write bus cycle is pleaced under these conditions, it will change to the same timing as the source-read cycle illustrated above. Figure 13.6 Transfer Cycle Examples with the Source-Read Bus Cycle Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 143 of 495 M32C/84 Group (M32C/84, M32C/84T) 13. DMAC 13.2 DMAC Transfer Cycle The number of DMAC transfer cycle can be calculated as follows. Any combination of even or odd transfer read and write addresses are possible. Table 13.3 lists the number of DMAC transfer cycles. Table 13.4 lists coefficient j, k. Transfer cycles per transfer = Number of read cycle x j + Number of write cycle x k Table 13.3 DMAC Transfer Cycles Single-Chip Mode Transfer Unit Bus Width Access Address 16-bit 8-bit transfers (BWi bit in the DMDp register = 0) 16-bit transfers (BWi bit = 1) i= 0 to 3, p = 0 to 1 Table 13.4 Coefficient j, k Internal Space Internal ROM Internal ROM SFR or internal RAM or internal RAM area with no wait state with a wait state j=1 j=2 j=2 k=1 k=2 k=2 j, k=2 to 9 External Space j and k BCLK cycles shown in Table 8.5. Add one cycle to j or k cycles when inserting a recovery cycle. 8-bit 16-bit 8-bit Even Odd Even Odd Even Odd Even Odd Read Cycle 1 1 — — 1 2 — — Write Cycle 1 1 — — 1 2 — — Memory Expansion Mode Microprocessor Mode Read Write Cycle Cycle 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 13.3 Channel Priority and DMA Transfer Timing When multiple DMA requests are generated in the same sampling period, between the falling edge of the CPU clock and the next falling edge, the DRQ bit in the DMiSL register (i = 0 to 3) is set to "1" (requested) simultaneously. Channel priority in this case is : DMA0 > DMA1 > DMA2 > DMA3. Figure 13.7 shows an example of the DMA transfer by external source. In Figure 13.7, the DMA0 request having highest priority is received first to start a transfer when a DMA0 request and DMA1 request are generated simultaneously. After one DMA0 transfer is completed, the bus privilege is returned to the CPU. When the CPU has completed one bus access, the DMA1 transfer starts. After one DMA1 transfer is completed, the privilege is again returned to the CPU. In addition, DMA requests cannot be counted up since each channel has one DRQ bit. Therefore, when DMA requests, as DMA1 in Figure 13.7, occur more than once before receiving bus privilege, the DRQ bit is set to "0" as soon as privilege is acquired. The bus privilege is returned to the CPU when one transfer is completed. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 144 of 495 M32C/84 Group (M32C/84, M32C/84T) 13. DMAC When DMA transfer request signals by external source are applied to INT0 and INT1 simultaneously and a DMA transfer with minimum cycle occurs. CPU Clock DMA0 DMA1 CPU INT0 DRQ Bit in DMA0 Register INT1 DRQ Bit in DMA1 Register Bus privilege acquired Figure 13.7 DMA Transfer by External Source Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 145 of 495 M32C/84 Group (M32C/84, M32C/84T) 14. DMACII 14. DMAC II DMAC II performs memory-to-memory transfer, immediate data transfer and calculation transfer, which transfers the sum of two data added by an interrupt request from any peripheral functions. Table 14.1 lists specifications of DMAC II. Table 14.1 DMAC II Specifications Specification Interrupt requests generated by all peripheral functions when the ILVL2 to ILVL0 bits are set to "1112" Transfer Data • Data in memory is transferred to memory (memory-to-memory transfer) • Immediate data is transferred to memory (immediate data transfer) • Data in memory (or immediate data) + data in memory are transferred to memory (calculation transfer) Transfer Block 8 bits or 16 bits Transfer Space 64-Kbyte space in addresses 0000016 to 0FFFF16(1, 2) Transfer Direction Fixed or forward address Selected separately for each source address and destination address Transfer Mode Single transfer, burst transfer Chained Transfer Function Parameters (transfer count, transfer address and other information) are switched when transfer counter reaches zero End-of-Transfer Interrupt Interrupt occurs when a transfer counter reaches zero Multiple Transfer Function Multiple data can be transferred by a generated request for one DMAC II transfer NOTES: 1. When transferring a 16-bit data to destination address 0FFFF16, it is transferred to 0FFFF16 and 1000016. The same transfer occurs when the source address is 0FFFF16. 2. The actual space where transfer can occurs is limited due to internal RAM capacity. Item DMAC II Request Source 14.1 DMAC II Settings DMAC II can be made available by setting up the following registers and tables. • RLVL register • DMAC II Index • Interrupt control register of the peripheral function causing a DMAC II request • The relocatable vector table of the peripheral function causing a DMAC II request • IRLT bit in the IIOiIE register (i = 0 to 4, 8 to 11) if using the intelligent I/O or CAN interrupt Refer to 11. Interrupts for details on the IIOiIE register. 14.1.1 RLVL Register When the DMAII bit is set to "1" (DMAC II transfer) and the FSIT bit to "0" (normal interrupt), DMAC II is activated by an interrupt request from any peripheral function with the ILVL2 to ILVL0 bits in the interrupt control register set to "1112" (level 7). Figure 14.1 shows the RLVL register. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 146 of 495 M32C/84 Group (M32C/84, M32C/84T) 14. DMACII Exit Priority Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol RLVL Address 009F16 After Reset XXXX 00002 Bit Symbol RLVL0 Bit Name b2 b1 b0 Function 0 0 0 : Level 0 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 RW RW RLVL1 Stop/Wait Mode Exit Minimum Interrupt Priority Level Control Bit(1) RW RLVL2 RW FSIT High-Speed Interrupt Set Bit(2) 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt RW (b4) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMA II transfer(3) DMAII DMA II Select Bit(4) RW Nothing is assigned. When write, set to "0". (b7 - b6) When read, its content is indeterminate. NOTES: 1. The microcomputer exits stop or wait mode when the requested interrupt priority level is higher than the level set in the RLVL2 to RLVL0 bits. Set the RLVL2 to RLVL0 bits to the same value as IPL in the FLG register. 2. When the FSIT bit is set to "1", an interrupt having the interrupt priority level 7 becomes the high-speed interrupt. In this case, set only one interrupt to the interrupt priority level 7 and the DMAII bit to "0". 3. Set the ILVL2 to ILVL0 bits in the interrupt control register after setting the DMAII bit to "1". Do not change the DMAII bit setting to "0" after setting the DMAII bit to "1". Set the FSIT bit to "0" when the DMAII bit to "1". 4. The DMAII bit becomes indeterminate after reset. To use the DMAII bit for an interrupt setting, set it to "0" before setting the interrupt control register. Figure 14.1 RLVL Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 147 of 495 M32C/84 Group (M32C/84, M32C/84T) 14. DMACII 14.1.2 DMAC II Index The DMAC II index is a data table which comprises 8 to 18 bytes (maximum 32 bytes when the multiple transfer function is selected). The DMAC II index stores parameters for transfer mode, transfer counter, source address (or immediate data), operation address as an address to be calculated, destination address, chained transfer address, and end-of-transfer interrupt address. This DMAC II index must be located on the RAM area. Figure 14.2 shows a configuration of the DMAC II index. Table 14.2 lists a configuration of the DMAC II index in transfer mode. Memory-to-Memory Transfer, Immediate Transfer, Calculation Transfer DMAC II Index Starting Address (BASE) 16 bits Transfer Mode Transfer Counter Operation Address(1) Transfer Destination Address Chained Transfer Address(2) Chained Transfer Address(2) End-of-Transfer Interrupt Address(3) End-of-Transfer Interrupt Address(3) (MOD) (COUNT) BASE BASE + 2 BASE + 4 BASE + 6 BASE + 8 Multiple Transfer 16 bits Transfer Mode Transfer Counter Transfer Source Address Transfer Destination Address Transfer Source Address (MOD) (COUNT) (SADR1) (DADR1) (SADR2) (DADR2) BASE + 2 BASE + 4 BASE + 6 BASE + 8 BASE + 10 BASE + 12 BASE + 14 BASE + 16 Transfer Source Address (or immediate data) (SADR) (OADR) (DADR) (CADR0) (CADR1) (IADR0) (IADR1) BASE + 10 Transfer Destination Address BASE + 28 Transfer Source Address BASE + 30 Transfer Destination Address (SADR7) (DADR7) NOTES: 1. This data is not required when not using the calculation transfer function. 2. This data is not required when not using the chained transfer function. 3. This data is not required when not using the end-of-transfer interrupt. The DMAC II index must be located on the RAM. Necessary data is set front-aligned. For example, if not using a calculation transfer function, set destination address to BASE+6. (See Table 14.2) Starting address of the DMAC II index must be set in the interrupt vector for the peripheral function interrupt causing a DMAC II request. Figure 14.2 DMAC II Index The followings are details of the DMAC II index. Set these parameters in the specified order listed in Table 14.2, according to DMAC II transfer mode. • Transfer mode (MOD) Two-byte data is required to set transfer mode. Figure 14.3 shows a configuration for transfer mode. • Transfer counter (COUNT) Two-byte data is required to set the number of transfer. • Transfer source address (SADR) Two-byte data is required to set the source memory address or immediate data. • Operation address (OADR) Two-byte data is required to set a memory address to be calculated. Set this data only when using the calculation transfer function. • Transfer destination address (DADR) Two-byte data is required to set the destination memory address. • Chained transfer address (CADR) Four-byte data is required to set the starting address of the DMAC II index for the next transfer. Set this data only when using the chained transfer function. • End-of-transfer interrupt address (IADR) Four-byte data is required to set a jump address for end-of-transfer interrupt processing. Set this data only when using the end-of-transfer interrupt. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 148 of 495 M32C/84 Group (M32C/84, M32C/84T) 14. DMACII Table 14.2 DMAC II Index Configuration in Transfer Mode Transfer Data Memory-to-Memory Transfer /Immediate Data Transfer Used Not Used MOD COUNT SADR DADR CADR0 CADR1 12 bytes Not Used Used MOD COUNT SADR DADR IADR0 IADR1 12 bytes Used Used MOD COUNT SADR DADR CADR0 CADR1 IADR0 IADR1 16 bytes Not Used Not Used MOD COUNT SADR OADR DADR 10 bytes Calculation Transfer Used Not Used MOD COUNT SADR OADR DADR CADR0 CADR1 14 bytes Not Used Used MOD COUNT SADR OADR DADR IADR0 IADR1 14 bytes Used Used MOD COUNT SADR OADR DADR CADR0 CADR1 IADR0 IADR1 18 bytes SADRi DADRi i=1 to 7 max. 32 bytes (when i=7) Multiple Transfer Not Available Not Available MOD COUNT SADR1 DADR1 Chained Transfer Not Used End-of-Transfer Not Used Interrupt MOD COUNT SADR DADR DMAC II Index 8 bytes Transfer Mode (MOD)(1) b15 b8 b7 b0 Bit Symbol SIZE Bit Name Transfer Unit Select Bit Transfer Data Select Bit Function (MULT=0) 0: 8 bits 1: 16 bits 0: Immediate data 1: Memory Function (MULT=1) RW RW IMM Set to "1" RW UPDS Transfer Source 0: Fixed address Direction Select Bit 1: Forward address Transfer Destination 0: Fixed address Direction Select Bit 1: Forward address b6 b5 b4 RW UPDD RW OPER/ Calculation Transfer 0: Not used CNT0(2) Function Select Bit 1: Used BRST/ Burst Transfer CNT1(2) Select Bit INTE/ End-of-Transfer CNT2(2) Interrupt Select Bit CHAIN Chained Transfer Select Bit 0: Single transfer 1: Burst transfer 0: Interrupt not used 1: Use interrupt 0 0 0: Do not set to this value 0 0 1: Once 0 1 0: Twice : : 1 1 0: 6 times 1 1 1: 7 times RW RW RW 0: Chained transfer not used Set to "0" 1: Use chained transfer RW Nothing is assigned. When write, set to "0". (b14 - b8) When read, its content is indeterminate. MULT Multiple Transfer Select Bit 0: Multiple transfer not used 1: Use multiple transfer RW NOTES: 1. MOD must be located on the RAM. 2. When the MULT bit is set to "0" (no multiple transfer), bits 6 to 4 becomes the INTE, OPER and BRST bits. When the MULT bit is set to "1" (multiple transfer), bits 6 to 4 becomes the CNT2 to CNT0 bits. Figure 14.3 MOD Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 149 of 495 M32C/84 Group (M32C/84, M32C/84T) 14. DMACII 14.1.3 Interrupt Control Register for the Peripheral Function For the peripheral function interrupt activating DMAC II, set the ILVL2 to ILVL0 bits to "1112" (level 7). 14.1.4 Relocatable Vector Table for the Peripheral Function Set the starting address of the DMAC II index in the interrupt vector for the peripheral function interrupt activating DMAC II. When using the chained transfer, the relocatable vector table must be located in the RAM. 14.1.5 IRLT Bit in the IIOiIE Register (i=0 to 4, 8 to 11) When the intelligent I/O interrupt or CAN interrupt is used to activate DMAC II, set the IRLT bit in the IIOiIE register of the interrupt to "0". 14.2 DMAC II Performance Function to activate DMAC II is selected by setting the DMA II bit to "1" (DMAC II transfer). DMAC II is activated by all peripheral function interrupts with the ILVL2 to ILVL0 bits set to "1112" (level 7). These peripheral function interrupt request signals become DMAC II transfer request signals and the peripheral function interrupt cannot be used. When an interrupt request is generated by setting the ILVL2 to ILVL0 bits to "1112" (level 7), DMAC II is activated regardless of what state the I flag and IPL are in. 14.3 Transfer Data DMAC II transfers 8-bit or 16-bit data. • Memory-to-memory transfer : Data is transferred from a desired memory location in a 64-Kbyte space (Addresses 0000016 to 0FFFF16) to another desired memory location in the same space. • Immediate data transfer : Immediate data is transferred to a desired memory location in a 64-Kbyte space. • Calculation transfer : Two 8-bit or16-bit data are added together and the result is transferred to a desired memory location in a 64-Kbyte space. When a 16-bit data is transferred to the destination address 0FFFF16, it is transferred to 0FFFF16 and 1000016. The same transfer occurs when the source address is 0FFFF16. Actual transferable space varies depending on the internal RAM capacity. 14.3.1 Memory-to-memory Transfer Data transfer between any two memory locations can be: • a transfer from a fixed address to another fixed address • a transfer from a fixed address to a relocatable address • a transfer from a relocatable address to a fixed address • a transfer from a relocatable address to another relocatable address When a relocatable address is selected, the address is incremented, after a transfer, for the next transfer. In a 8-bit transfer, the transfer address is incremented by one. In a 16-bit transfer, the transfer address is incremented by two. When a source or destination address exceeds address 0FFFF16 as a result of address incrementation, the source or destination address returns to address 0000016 and continues incrementation. Maintain source and destination address at address 0FFFF16 or below. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 150 of 495 M32C/84 Group (M32C/84, M32C/84T) 14. DMACII 14.3.2 Immediate Data Transfer DMAC II transfers immediate data to any memory location. A fixed or relocatable address can be selected as the destination address. Store the immediate data into SADR. To transfer an 8-bit immediate data, write the data in the low-order byte of SADR (high-order byte is ignored). 14.3.3 Calculation Transfer After two memory data or an immediate data and memory data are added together, DMAC II transfers calculated result to any memory location. SADR must have one memory location address to be calculated or immediate data and OADR must have the other memory location address to be calculated. Fixed or relocatable address can be selected as source and destination addresses when using a memory + memory calculation transfer. If the transfer source address is relocatable, the operation address also becomes relocatable. Fixed or relocatable address can be selected as the transfer destination address when using an immediate data + memory calculation transfer. 14.4 Transfer Modes Single and burst transfers are available. The BRST bit in MOD selects transfer method, either single transfer or burst transfer. COUNT determines how many transfers occur. No transfer occurs when COUNT is set to "000016". 14.4.1 Single Transfer For every transfer request source, DMAC II transfers one transfer unit of 8-bit or 16-bit data once. When the source or destination address is relocatable, the address is incremented, after a transfer, for the next transfer. COUNT is decremented every time a transfer occurs. When using the end-of-transfer interrupt, the interrupt is acknowledged when COUNT reaches "0". 14.4.2 Burst Transfer For every transfer request source, DMAC II continuously transfers data the number of times determined by COUNT. COUNT is decremented every time a transfer occurs. The burst transfer ends when COUNT reaches "0". The end-of-transfer interrupt is acknowledged when the burst transfer ends if using the endof-transfer interrupt. All interrupts are ignored while the burst transfer is in progress. 14.5 Multiple Transfer The MULT bit in MOD selects the multiple transfer. When using the multiple transfer, select the memory-tomemory transfer. One transfer request source initiates multiple transfers. The CNT2 to CNT0 bits in MOD selects the number of transfers from "0012" (once) to "1112" (7 times). Do not set the CNT2 to CNT0 bits to "0002". The transfer source and destination addresses for each transfer must be allocated alternately in addresses following MOD and COUNT. When the multiple transfer is selected, the calculation transfer, burst transfer, end-of-transfer interrupt and chained transfer cannot be used. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 151 of 495 M32C/84 Group (M32C/84, M32C/84T) 14. DMACII 14.6 Chained Transfer The CHAIN bit in MOD selects the chained transfer. The following process initiates the chained transfer. (1) Transfer, caused by a transfer request source, occurs according to the content of the DMAC II index. The vectors of the request source indicates where the DMAC II index is allocated. For each request, the BRST bit selects either single or burst transfer. (2) When COUNT reaches "0", the contents of CADR1 and CADR0 are written to the vector of the request source. When the INTE bit in MOD is set to "1", the end-of-transfer interrupt is generated simultaneously. (3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the DMAC II index indicated by the peripheral function interrupt vector rewritten in (2). Figure 14.4 shows the relocatable vector and DMACII index when the chained transfer is in progress. For the chained transfer, the relocatable vector table must be located in the RAM. RAM INTB Relocatable Vector Peripheral I/O interrupt vector causing DMAC II request Default value of DMAC II is BASE(1). BASE(1) DMAC II Index(1) (CADR1 to CADR0) BASE(2) The above vector is rewritten to BASE(2) when a transfer is completed. Starts at BASE(2) when next request conditions are met. Transferred according to the DMAC II Index. BASE(2) DMAC II Index(2) (CADR1 to CADR0) BASE(3) The above vector is rewritten to BASE(3) when a transfer is completed. Figure 14.4 Relocatable Vector and DMAC II Index 14.7 End-of-Transfer Interrupt The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt is generated when COUNT reaches "0." Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 152 of 495 M32C/84 Group (M32C/84, M32C/84T) 14. DMACII 14.8 Execution Time DMAC II execution cycle is calculated by the following equations: Multiple transfers: t = 21+ (11 + b + c) x k cycles Other than multiple transfers: t = 6 + (26 + a + b + c + d) x m + (4 + e) x n cycles a: If IMM = 0 (source of transfer is immediate data), a = 0; if IMM = 1 (source of transfer is memory), a = –1 b: If UPDS = 1 (source transfer address is a relocatable address), b = 0; if UPDS = 0 (source transfer address is a fixed address), b = 1 c: If UPDD = 1 (destination transfer address is a relocatable address), c = 0; if UPDD = 0 (destination transfer address is a fixed address), c = 1 d: If OPER = 0 (calculation function is not selected), d = 0; if OPER = 1 (calculation function is selected) and UPDS = 0 (source of transfer is immediate data or fixed address memory), d = 7; if OPER = 1 (calculation function is selected) and UPDS = 1 (source of transfer is relocatable address memory), d = 8 e: If CHAIN = 0 (chained transfer is not selected), e = 0; if CHAIN = 1 (chained transfer is selected), e = 4 m: BRST = 0 (single transfer), m = 1; BRST = 1 (burst transfer), m = the value set in transfer counter n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1 k: Number of transfers set in the CNT2 to CNT0 bits The equations above are approximations. The number of cycles may vary depending on CPU state, bus wait state, and DMAC II index allocation. The first instruction from the end-of-transfer interrupt routine is executed in the eighth cycle after the DMAC II transfer is completed. If the end-of-transfer interrupt (transfer counter = 2) occurs with no chained transfer function after a memory-to-memory transfer occurs with a relocatable source address, fixed destination address, single transfer and double transfer: a=-1 b=0 c=1 d=0 e=0 m=1 First DMAC II transfer t=6+26x1+4x1=36 cycles Second DMAC II transfer t=6+26x1+4x0=32 cycles DMAC II transfer request DMAC II transfer request Program DMAC II transfer (First time) 36 cycles Program DMAC II transfer (Second time) 32 cycles 7 cycles Processing the end-of-transfer interrupt Transfer counter = 2 Transfer counter = 1 Decrement a transfer counter Transfer counter = 0 Decrement a transfer counter Transfer counter = 1 Figure 14.5 Transfer Cycle When an interrupt request as a DMAC II transfer request source and another interrupt request with higher _______ priority (e.g., NMI or watchdog timer) are generated simultaneously, the interrupt with higher priority takes precedence over the DMAC II transfer. The pending DMAC II transfer starts after the interrupt sequence has been completed. Page 153 of 495 Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 M32C/84 Group (M32C/84, M32C/84T) 15. Timer 15. Timer The microcomputer has eleven 16-bit timers. Five timers A and six timers B have different functions. Each timer functions independently. The count source for each timer becomes the clock for timer operations including counting and reloading, etc. Figures 15.1 and 15.2 show block diagrams of timer A and timer B configuration. Clock prescaler XCIN Set the CPSR bit in the CPSRF register to "1" 00: Timer mode 10: One-shot timer mode 11: PWM mode 10 Noise filter 01 00 TMOD1 and TMOD0 1/32 Reset fC32 f1 f8 f2n fC32 00 01 10 11 TCK1 and TCK0 Timer A0 interrupt Timer A0 01: Event counter mode TA0IN 11 TA0TGH and TA0TGL TCK1 and TCK0 00 01 10 11 00: Timer mode 10: One-shot tiemr mode 11: PWM mode 10 TMOD1 and TMOD0 Timer A1 interrupt TA1IN Noise filter 01 00 11 Timer A1 01: Event counter mode TA1TGH and TA1TGL TCK1 and TCK0 00 01 10 11 00: Timer mode 10: One-shot timer mode 11: PWM mode 10 01 00 TMOD1 and TMOD0 Timer A2 interrupt TA2IN Noise filter Timer A2 01: Event counter mode 11 TA2TGH and TA2TGL TCK1 and TCK0 00 01 10 11 00: Timer mode 10: One-shot timer mode 11: PWM mode 10 01 00 TMOD1 and TMOD0 Timer A3 interrupt TA3IN Noise filter Timer A3 01: Event counter mode 11 TA3TGH and TA3TGL TCK1 and TCK0 00 01 10 11 00: Timer mode 10: One-shot timer mode 11: PWM mode 10 TMOD1 and TMOD0 Timer A4 interrupt TA4IN Noise filter 01 00 Timer A4 01: Event counter mode 11 TA4TGH and TA4TGL Timer B2 overflow or underflow signal CST: Bit in the TCSPR Register TCK1 and TCK0, TMOD1 and TMOD0 : Bits in the TAiMR Register (i=0 to 4) TAiTGH and TAiTGL: Bits in the ONSF Register or TRGSR Register Figure 15.1 Timer A Configuration Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 154 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer Clock prescaler XCIN Set the CPSR bit in the CPSRF register to "1" 1/32 Reset fC32 f1 f8 f2n fC32 00 01 10 11 Timer B2 overflow or underflow signal (to a count source of Timer A) 00: Timer mode 10: Pulse width measurement mode TMOD1 and TMOD0 1 0 TCK1 TCK1 to TCK0 TB0IN Noise filter 00 01 10 11 TCK1 and TCK0 Timer B0 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode 1 TMOD1 and TMOD0 Timer B0 interrupt Timer B1 interrupt Timer B1 TB1IN Noise filter 00 01 10 11 TCK1 and TCK0 0 TCK1 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode 1 TMOD1 and TMOD0 Timer B2 interrupt Timer B2 TB2IN Noise filter 0 TCK1 01:Event counter mode 00 01 10 11 TCK1 and TCK0 00: Timer mode 10: Pulse width measurement mode TMOD1 and TMOD0 1 TB3IN 00 01 10 11 Noise filter TCK1 and TCK0 Timer B3 TCK1 Timer B3 interrupt 0 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode 1 TMOD1 and TMOD0 TB4IN 00 01 10 11 Noise filter TCK1 and TCK0 Timer B4 0 TCK1 Timer B4 interrupt 01:Event counter mode 00: Timer mode 10: Pulse width measurement mode 1 TMOD1 and TMOD0 TB5IN Noise filter Timer B5 0 TCK1 Timer B5 interrupt 01:Event counter mode CST : Bit in the TCSPR Register TCK1 and TCK0, TMOD1 and TMOD0 : Bits in the TBiMR Register (i=0 to 5) Figure 15.2 Timer B Configuration Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 155 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) 15.1 Timer A Figure 15.3 shows a block diagram of the timer A. Figures 15.4 to 15.7 show registers associated with the timer A. The timer A supports the following four modes. Except in event counter mode, all timers A0 to A4 have the same function. The TMOD1 and TMOD0 bits in the TAiMR register (i=0 to 4) determine which mode is used. • Timer mode: The timer counts an internal count source. • Event counter mode: The timer counts an external pulse or an overflow and underflow of other timers. • One-shot timer mode: The timer outputs one valid pulse until a counter value reaches "000016". • Pulse width modulation mode: The timer continuously outputs desired pulse widths. Table 15.1 lists TAiOUT pin settings when used as an output. Table 15.2 lists TAiIN and TAiOUT pin settings when used as an input. Select clock Select Count Source High-Order Bits of Data Bus Low-Order Bits of Data Bus 8 loworder bits Reload Register f1 f8 f2n(1) fC32 00 01 10 11 TCK1 and TCK0 • Timer Mode :TMOD1 and TMOD0=00, MR2=0 • One-Shot Timer Mode :TMOD1 and TMOD0=10 • Pulse Width Modulation Mode :TMOD1 and TMOD0=11 TMOD1 and TMOD0, MR2 • Timer Mode (gate function): TMOD1 and TMOD0=00, MR2=1 • Event Counter Mode:TMOD1 and TMOD0=01 8 highorder bits TAiIN Polarity Selector TAiS Counter Increment / decrement Always decrement except in event counter mode 00 01 11 01 0 1 TMOD1 and TMOD0 TB2 Overflow(2) 10 TAj Overflow(2) 11 (2) TAk Overflow TAiTGH and TAiTGL 00 01 Decrement TAiUD Pulse Output MR2 TAiOUT Toggle Flip Flop i=0 to 4 j=i-1, except j=4 if i=0 k=i+1, except k=0 if i=4 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. Overflow or underflow signal TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Addresses 034716 034616 034916 034816 034B16 034A16 034D16 034C16 034F16 034E16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 TCK1 and TCK0, TMOD1 and TMOD0, MR2 and MR1 : Bits in the TAiMR register TAiTGH and TAiTGL : Bits in the ONSF register if i=0 or bits in the TRGSR register if i=1 to 4 TAiS : Bits in the TABSR register TAiUD : Bits in the UDF register Figure 15.3 Timer A Block Diagram Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 156 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) Timer Ai Register (i=0 to 4)(1) b15 b8 b7 b0 Symbol TA0 to TA2 TA3, TA4 Address 034716-034616, 034916-034816, 034B16-034A16 034D16-034C16, 034F16-034E16 After Reset Indeterminate Indeterminate Mode Timer Mode Function If setting value is n, count source is divided by n+1. If setting value is n, count source is divided by FFFF16 - n+1 when the counter is incremented and by n+1 when the counter is decremented. If setting value is n, count source is divided by n, then stops. Setting Range RW 000016 to FFFF16 RW Event Counter Mode(2) One-Shot Timer Mode(4) 000016 to FFFF16 RW 000016 to FFFF16(3) WO If count source frequency is fj Pulse Width and setting value of the TAi Modulation Mode(5) register is n, PWM cycle: (216-1) / fj (16-Bit PWM) "H" width of PWM pulse: n / fj If count source frequency is fj, setting value of high-order bits in the TAi register is n and setting value of low-order bits in the TAi register is m, PWM cycle: (28-1)x(m+1) / fj "H" width of PWM pulse: (m+1)n / fj 000016 to FFFE16(3) WO Pulse Width Modulation Mode(5) (8-Bit PWM) 0016 to FE16(3) (High-order address bits) 0016 to FF16(3) (Low-order address bits) WO fj : f1, f8, f2n, fC32 NOTES: 1. Use 16-bit data for reading and writing. 2. The TAi register counts how many pulse inputs are provided externally or how many times another timer counter overflows and underflows. 3. Use the MOV instruction to set the TAi register. 4. When the TAi register is set to "000016", the timer counter does not start and the timer Ai interrupt request is not generated. 5. When the TAi register is set to "000016", the pulse width modulator does not operate and the TAiOUT pin is held "L". The TAi interrupt request is also not generated. The same situation occurs in 8-bit pulse width modulator mode if the 8 high-order bits in the TAi register are set to "0016". Figure 15.4 TA0 to TA4 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 157 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) Timer Ai Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol TA0MR to TA4MR Address 035616, 035716, 035816, 035916, 035A16 After Reset 0016 Bit Symbol TMOD0 Bit Name b1b0 Function 0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode Set to "0" RW RW RW Operating Mode Select Bit TMOD1 (b3) MR1 MR2 MR3 TCK0 Reserved Bit RW RW Function varies depending on operating mode RW RW RW RW Count Source Select Bit TCK1 Function varies depending on operating mode Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 034016 After Reset 0016 Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit Name Timer A0 Count Start Flag Timer A1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer A4 Count Start Flag Timer B0 Count Start Flag Timer B1 Count Start Flag Timer B2 Count Start Flag Function 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting RW RW RW RW RW RW RW RW RW Figure 15.5 TA0MR to TA4MR Registers and TABSR Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 158 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) Up/Down Flag(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol UDF Address 034416 After Reset 0016 Bit Symbol TA0UD Bit Name Timer A0 Up/Down Flag(2) Timer A1 Up/Down Flag(2) Timer A2 Up/Down Flag(2) Timer A3 Up/Down Flag(2) Timer A4 Up/Down Flag(2) Function 0 : Decrement 1 : Increment 0 : Decrement 1 : Increment 0 : Decrement 1 : Increment 0 : Decrement 1 : Increment 0 : Decrement 1 : Increment RW RW TA1UD RW TA2UD RW TA3UD RW TA4UD RW TA2P TA3P TA4P 0 : Disables two-phase pulse signal Timer A2 Two-Phase processing function Pulse Signal Processing 1 : Enables two-phase pulse signal Function Select Bit(3) processing function 0 : Disables two-phase pulse signal Timer A3 Two-Phase Pulse Signal Processing 1 : processing function pulse signal Enables two-phase Function Select Bit(3) processing function 0 : Disables two-phase pulse signal Timer A4 Two-Phase processing function Pulse Signal Processing 1 : Enables two-phase pulse signal Function Select Bit(3) processing function WO WO WO NOTES: 1. Use the MOV instruction to set the UDF register. 2. This bit is enabled when the MR2 bit in the TAiMR register (i=0 to 4) is set to "0" (the UDF register causes increment/decrement switching) in event counter mode. 3. Set this bit to "0" when not using the two-phase pulse signal processing function. One-Shot Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol ONSF Address 034216 After Reset 0016 Bit Symbol TA0OS TA1OS TA2OS TA3OS TA4OS TAZIE Bit Name Timer A0 One-Shot Start Flag(1) Timer A1 One-Shot Start Flag(1) Timer A2 One-Shot Start Flag(1) Timer A3 One-Shot Start Flag(1) Timer A4 One-Shot Start Flag(1) Z-Phase Input Enable Bit Function 0 : In an idle state 1 : Starts the timer 0 : In an idle state 1 : Starts the timer 0 : In an idle state 1 : Starts the timer 0 : In an idle state 1 : Starts the timer 0 : In an idle state 1 : Starts the timer 0 : Disables Z-phase input 1 : Enables Z-phase input b7b6 RW RW RW RW RW RW RW TA0TGL Timer A0 Event/Trigger Select Bit TA0TGH NOTES: 1. When read, this bit is set to "0". 2. Overflow or underflow. 0 0 : Selects an input to the TA0IN pin RW 0 1 : Selects the TB2 overflows(2) 1 0 : Selects the TA4 overflows(2) RW 1 1 : Selects the TA1 overflows(2) Figure 15.6 UDF Register and ONSF Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 159 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) Trigger Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TRGSR Address 034316 After Reset 0016 Bit Symbol TA1TGL Bit Name b1 b0 Function RW Timer A1 Event/Trigger Select Bit TA1TGH 0 0 : Selects an input to the TA1IN pin RW 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA0 overflows(1) RW 1 1 : Selects the TA2 overflows(1) b3 b2 TA2TGL Timer A2 Event/Trigger Select Bit TA2TGH TA3TGL Timer A3 Event/Trigger Select Bit TA3TGH 0 0 : Selects an input to the TA2IN pin RW 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA1 overflows(1) RW 1 1 : Selects the TA3 overflows(1) b5 b4 0 0 : Selects an input to the TA3IN pin RW 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA2 overflows(1) RW 1 1 : Selects the TA4 overflows(1) b7 b6 TA4TGL TA4TGH Timer A4 Event/Trigger Select Bit 0 0 : Selects an input to the TA4IN pin RW 0 1 : Selects the TB2 overflows(1) 1 0 : Selects the TA3 overflows(1) RW 1 1 : Selects the TA0 overflows(1) NOTES: 1. Overflow or underflow Count Source Prescaler Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol TCSPR Address 035F16 After Reset(2) 0016 Bit Symbol CNT0 Bit Name Function RW RW CNT1 Divide Ratio Select Bit(1) CNT2 If setting value is n, f2n is the main clock, on-chip oscillator or PLL clock divided by 2n. Not divided if n=0. RW RW RW CNT3 Reserved Bit Operation Enable Bit When read, its content is indeterminate 0 : Stops a divider 1 : Starts a divider (b6 - b4) CST RO RW NOTES: 1. Set the CST bit to "0" before the CNT3 to CNT0 bits are rewritten. 2. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has performed. Figure 15.7 TRGSR Register and TCSPR Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 160 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) Table 15.1 Pin Settings for Output from TAiOUT Pin (i=0 to 4) Pin PS1, PS2 Registers P70/TA0OUT(1) P72/TA1OUT P74/TA2OUT P76/TA3OUT P80/TA4OUT PS1_0= 1 PS1_2= 1 PS1_4= 1 PS1_6= 1 PS2_0= 1 Setting PSL1, PSL2 Registers PSL1_0=1 PSL1_2=1 PSL1_4=0 PSL1_6=1 PSL2_0=0 PSC Register PSC_0= 0 PSC_2= 0 PSC_4= 0 PSC_6= 0 – NOTES: 1. P70/TA0OUT is a port for the N-channel open drain output. Table 15.2 Pin Settings for Input to TAiIN and TAiOUT Pins (i=0 to 4) Pin Setting PS1, PS2 Registers PD7, PD8 Registers P70/TA0OUT P71/TA0IN P72/TA1OUT P73/TA1IN P74TA2OUT P75/TA2IN P76TA3OUT P77/TA3IN P80/TA4OUT P81/TA4IN PS1_0=0 PS1_1=0 PS1_2=0 PS1_3=0 PS1_4=0 PS1_5=0 PS1_6=0 PS1_7=0 PS2_0=0 PS2_1=0 PD7_0=0 PD7_1=0 PD7_2=0 PD7_3=0 PD7_4=0 PD7_5=0 PD7_6=0 PD7_7=0 PD8_0=0 PD8_1=0 Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 161 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) 15.1.1 Timer Mode In timer mode, the timer counts an internally generated count source (see Table 15.3). Figure 15.8 shows the TAiMR register (i=0 to 4) in timer mode. Table 15.3 Timer Mode Specifications Item Count Source Counting Operation f1, f8, f2n(1), fC32 • The timer decrements a counter value When the timer counter underflows, content of the reload register is reloaded into the count register and counting resumes. Divide Ratio Counter Start Condition Counter Stop Condition TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer 1/(n+1) n: setting value of the TAi register (i=0 to 4) 000016 to FFFF16 The TAiS bit in the TABSR register is set to "1" (starts counting) The TAiS bit is set to "0" (stops counting) Programmable I/O port or gate input Programmable I/O port or pulse output The TAi register indicates counter value • While the timer counter stops, the value written to the TAi register is also written to both reload register and counter • While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Selectable Function • Gate function Input signal to the TAiIN pin determines whether the timer counter starts or stops counting • Pulse output function The polarity of the TAiOUT pin is inversed whenever the timer counter underflows Specification Interrupt Request Generation Timing The timer counter underflows NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 162 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) Timer Ai Mode Register (i=0 to 4) (Timer Mode) b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol TA0MR to TA4MR Address 035616, 035716, 035816, 035916, 035A16 After Reset 0016 Bit Symbol TMOD0 Bit Name Function RW RW Operating Mode Select Bit TMOD1 Reserved Bit b1b0 0 0 : Timer mode RW Set to "0" b4b3 (b2) MR1 RW Gate Function Select Bit MR2 MR3 TCK0 Count Source Select Bit TCK1 Set to "0" in timer mode 0 X : Gate function disabled(1) RW (TAiIN pin is a programmable I/O pin) 1 0 : Timer counts only while the TAiIN pin is held "L" RW 1 1 : Timer counts only while the TAiIN pin is held "H" RW b7b6 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 RW RW NOTES: 1. X can be set to either "0" or "1". 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 15.8 TA0MR to TA4MR Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 163 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) 15.1.2 Event Counter Mode In event counter mode, the timer counts how many external signals are applied or how many times another timer counter overflows and underflows. The timers A2, A3 and A4 can count externally generated two-phase signals. Table 15.4 lists specifications in event counter mode (when not handling a twophase pulse signal). Table 15.5 lists specifications in event counter mode (when handling a two-phase pulse signal with the timers A2, A3 and A4). Figure 15.9 shows the TAiMR register (i=0 to 4) in event counter mode. Table 15.4 Event Counter Mode Specifications (When Not Processing Two-phase Pulse Signal) Item Count Source Specification • External signal applied to the TAiIN pin (i = 0 to 4) (valid edge can be selected by program) • Timer B2 overflow or underflow signal, timer Aj overflow or underflow signal (j=i-1, except j=4 if i=0) and timer Ak overflow or underflow signal (k=i+1, except k=0 if i=4) Counting Operation • External signal and program can determine whether the timer increments or decrements a counter value • When the timer counter underflows or overflows, content of the reload register is reloaded into the count register and counting resumes. When the free-running count function is selected, the timer counter continues running without reloading. Divide Ratio Counter Start Condition Counter Stop Condition TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer • 1/(FFFF16 - n + 1) for counter increment • 1/(n + 1) for counter decrement n : setting value of the TAi register 0000 16 to FFFF16 The TAiS bit in the TABSR register is set to "1" (starts counting) The TAiS bit is set to "0" (stops counting) Programmable I/O port or count source input Programmable I/O port, pulse output or input selecting a counter increment or decrement The TAi register indicates counter value • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter • While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Interrupt Request Generation Timing The timer counter overflows or underflows Selectable Function • Free-running count function Content of the reload register is not reloaded even if the timer counter overflows or underflows • Pulse output function The polarity of the TAiOUT pin is inversed whenever the timer counter overflows or underflows Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 164 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) Table 15.5 Event Counter Mode Specifications (When Processing Two-phase Pulse Signal on Timer A2, A3 and A4) Item Count Source Counting Operation Specification Two-phase pulse signal applied to the TAiIN and TAiOUT pins (i = 2 to 4) • Two-phase pulse signal determines whether the timer increments or decrements a counter value • When the timer counter overflows or underflows, content of the reload register is reloaded into the count register and counting resumes. With the free-running count function, the timer counter continues running without reloading. Divide Ratio Counter Start Condition Counter Stop Condition TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer • 1/ (FFFF16 - n + 1) for counter increment • 1/ (n + 1) for counter decrement n : setting value of the TAi register 000016 to FFFF16 The TAiS bit in the TABSR register is set to "1" (starts counting) The TAiS bit is set to "0" (stops counting) Two-phase pulse signal is applied Two-phase pulse signal is applied The TAi register indicates the counter value • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter • While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) Interrupt Request Generation Timing The timer counter overflows or underflows Selectable Function(1) • Normal processing operation (the timer A2 and timer A3) While a high-level ("H") signal is applied to the TAjOUT pin (j = 2 or 3), the timer increments a counter value on the rising edge of the TAjIN pin or decrements a counter on the falling edge. TAjOUT TAjIN Increment Increment Increment Decrement Decrement Decrement • Multiply-by-4 processing operation (the timer A3 and timer A4) While an "H" signal is applied to the TAkOUT pin (k = 3 or 4) on the rising edge of the TAkIN pin, the timer increments a counter value on the rising and falling edges of the TAkOUT and TAkIN pins. While an "H" signal is applied to the TAkOUT pin on the falling edge of the TAkIN pin, the timer decrements a counter value on the rising and falling edges of the TAkOUT and TAkIN pins. TAkOUT TAkIN Increment on all edges Decrement on all edges NOTES: 1. Only timer A3 operation can be selected. The timer A2 is for the normal processing operation. The timer A4 is for the multiply-by-4 operation. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 165 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) Timer Ai Mode Register (i=0 to 4) (Event Counter Mode) b7 b6 b5 b4 b3 b2 b1 b0 0 001 Symbol TA0MR to TA4MR Address 035616, 035716, 035816, 035916, 035A16 After Reset 0016 Bit Symbol TMOD0 Function Bit Name (When not processing two-phase pulse signal) b1b0 Function (When processing two-phase pulse signal) RW Operating Mode Select Bit TMOD1 RW 0 1 : Event counter mode(1) RW (b2) Reserved Bit Set to "0" 0 : Counts falling edges of an external signal Set to "0" 1 : Counts rising edges of an external signal RW MR1 Count Polarity Select Bit(2) RW MR2 Increment/Decrement 0 : UDF registser setting Switching Source 1 : Input signal to Select Bit TAiOUT pin(3) Set to "0" in event counter mode Count Operation Type Select Bit 0 : Reloading 1 : Free running Set to "1" RW MR3 RW TCK0 RW 0 : Normal processing operation RW 1 : Multiply-by-4 processing operation TCK1 Two-Phase Pulse Set to "0" Signal Processing Operation Select Bit(4,5) NOTES: 1. The TAiTGH and TAiTGL bits in the ONSF or TRGSR register determine the count source in the event counter mode. 2. MR1 bit setting is enabled only when counting how many times external signals are applied. 3. The timer decrements a counter value when an "L" signal is applied to the TAiOUT pin and the timer increments a counter value when an "H" signal is applied to the TAiOUT pin. 4. The TCK1 bit is enabled only in the TA3MR register. 5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j=2 to 4) to "1" (two-phase pulse signal processing function enabled). Also, set the TAiTGH and TAiTGL bits to "002" (input to the TAjIN pin). Figure 15.9 TA0MR to TA4MR Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 166 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) 15.1.2.1 Counter Reset by Two-Phase Pulse Signal Processing Z-phase input resets the timer counter when processing a two-phase pulse signal. This function can be used in timer A3 event counter mode, two-phase pulse signal processing, free_______ running count operation type or multiply-by-4 processing. The Z-phase signal is applied to the INT2 pin. When the TAZIE bit in the ONSF register is set to "1" (Z-phase input enabled), Z-phase input can reset the timer counter. To reset the counter by a Z-phase input, set the TA3 register to "000016" beforehand. _______ Z-phase input is enabled when the edge of the signal applied to the INT2 pin is detected. The POL bit in the INT2IC register can determine edge polarity. The Z-phase must have a pulse width of one timer A3 count source cycle or more . Figure 15.10 shows two-phase pulses (A-phase and B-phase) and the Z-phase. Z-phase input resets the timer counter in the next count source following Z-phase input. Figure 15.11 shows the counter reset timing. Timer A3 interrupt request is generated twice continuously when a timer A3 overflow or underflow, _______ and a counter reset by INT2 input occur at the same time. Do not use the timer A3 interrupt request when this function is used. TA3OUT (A-phase) TA3IN (B-phase) Count source INT2 (1) (Z-phase) Pulse width of one count source cycle or more is required NOTES: 1. When the rising edge of INT2 is selected. Figure 15.10 Two-Phase Pulse (A-phase and B-phase) and Z-phase TA3OUT (A-phase) TA3IN (B-phase) Count source INT2 (1) (Z-phase) Counter value m m+1 1 2 3 4 5 Timer counter is reset at this timing NOTES: 1. When the rising edge of INT2 is selected. Figure 15.11 Counter Reset Timing Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 167 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) 15.1.3 One-Shot Timer Mode In one-shot timer mode, the timer operates only once for each trigger (see Table 15.6). Once a trigger occurs, the timer starts and continues operating for a desired period. Figure 15.12 shows the TAiMR register (i=0 to 4) in one-shot timer mode. Table 15.6 One-Shot Timer Mode Specifications Item Count Source Counting Operation f1, f8, f2n(1), fC32 • The timer decrements a counter value When the timer counter reaches "000016", it stops counting after reloading. If a trigger occurs while counting, content of the reload register is reloaded into the count register and counting resumes. Divide Ratio Counter Start Condition Specification 1/n n : setting value of the TAi register (i=0 to 4) 000016 to FFFF16, but the timer counter does not run if n=000016 The TAiS bit in the TABSR register is set to "1" (starts counting) and following triggers occur: • External trigger input is provided • Timer counter overflows or underflows • The TAiOS bit in the ONSF register is set to "1" (timer started) Counter Stop Condition • After the timer counter has reached "000016" and is reloaded • When the TAiS bit is set to "0" (stops counting) Interrupt Request Generation Timing The timer counter reaches "000016" TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer Programmable I/O port or trigger input Programmable I/O port or pulse output The value in the TAi register is indeterminate when read • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter • While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 168 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) Timer Ai Mode Register (i=0 to 4) (One-Shot Timer Mode) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TA0MR to TA4MR 0 010 Address 035616, 035716, 035816, 035916, 035A16 After Reset 0016 Bit Symbol TMOD0 Bit Name Function RW RW Operating Mode Select Bit TMOD1 b1b0 1 0 : One-shot timer mode RW (b2) MR1 Reserved Bit Set to "0" External Trigger Select 0 : Falling edge of input signal to TAiIN pin RW Bit(1) 1 : Rising edge of input signal to TAiIN pin Trigger Select Bit 0 : The TAiOS bit is enabled 1 : Selected by the TAiTGH and TAiTGL bits RW MR2 MR3 TCK0 Set to "0" in the one-shot timer mode b7b6 RW RW Count Source Select Bit TCK1 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 RW NOTES: 1. The MR1 bit setting is enabled only when the TAiTGH and TAiTGL bits in the TRGSR register are set to "002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or "112" (TAi overflow and underflow). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 15.12 TA0MR to TA4MR Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 169 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) 15.1.4 Pulse Width Modulation Mode In pulse width modulation mode, the timer outputs pulse of desired width continuously (see Table 15.7). The timer counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 15.13 shows the TAiMR register (i=0 to 4) in pulse width modulation mode. Figures 15.14 and 15.15 show examples of how a 16-bit pulse width modulator operates and of how an 8-bit pulse width modulator operates. Table 15.7 Pulse Width Modulation Mode Specifications Item Count Source Counting Operation f1, f8, f2n(1), fC32 • The timer decrements a counter value (The counter functions as an 8-bit or a 16-bit pulse width modulator) Content of the reload register is reloaded on the rising edge of PWM pulse and counting continues. The timer is not affected by a trigger that is generated during counting. 16-Bit PWM • "H" width = n / fj • Cycle = (216-1) / fj fixed 8-Bit PWM • "H" width = n x (m+1) / fj • Cycles = (28-1) x (m+1) / fj Specification n : setting value of the TAi register fj : count source frequency 000016 to FFFE16 m : setting value of low-order bit address of the TAi register n : setting value of high-order bit address of the TAi register Counter Start Condition • External trigger input is provided • Timer counter overflows or underflows • The TAiS bit in the TABSR register is set to "1" (starts counting) Counter Stop Condition TAiIN Pin Function TAiOUT Pin Function Read from Timer Write to Timer The TAiS bit is set to "0" (stops counting) Programmable I/O port or trigger input Pulse output The value in the TAi register is indeterminate when read Interrupt Request Generation Timing On the falling edge of the PWM pulse 0016 to FF16 0016 to FE16 • When the timer counter stops, the value written to the TAi register is also written to both reload register and counter • While counting, the value written to the TAi register is written to the reload register (It is transferred to the counter at the next reload timing) NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 170 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) Timer Ai Mode Register (i=0 to 4) (Pulse Width Modulator Mode) b7 b6 b5 b4 b3 b2 b1 b0 011 Symbol TA0MR to TA4MR Address 035616, 035716, 035816, 035916, 035A16 After Reset 0016 Bit Symbol TMOD0 Bit Name Function RW RW Operating Mode Select Bit TMOD1 b1b0 1 1 : Pulse width modulation (PWM) mode RW Reserved Bit (b2) MR1 External Trigger Select Bit(1) Trigger Select Bit 16/8-Bit PWM Mode Select Bit Set to "0" RW 0 : Falling edge of input signal to TAiIN pin RW 1 : Rising edge of input signal to TAiIN pin 0 : The TAiS bit is enabled 1 : Selected by the TAiTGH and TAiTGL bits RW MR2 MR3 TCK0 0: Functions as a 16-bit pulse width modulator RW 1: Functions as an 8-bit pulse width modulator b7b6 Count Source Select Bit TCK1 0 0 : f1 0 1 : f8 1 0 : f2n(2) 1 1 : fC32 RW RW NOTES: 1. MR1 bit setting is enabled only when the TAiTGH and TAiTGL bits in the TRGSR register are set to "002" (input to the TAiIN pin). The MR1 bit can be set to either "0" or "1" when the TAiTGH and TAiTGL bits are set to "012" (TB2 overflow and underflow), "102" (TAi overflow and underflow) or "112" (TAi overflow and underflow). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 15.13 TA0MR to TA4MR Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 171 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer A) When the reload register is set to "000316" and an external trigger (on rising edge of a signal applied to the TAiIN pin) is selected 1 / fj X (216 – 1) Count source Signal applied to TAiIN pin “H” “L” No trigger occurs by this signal 1 / fi X n PWM pulse output from TAiOUT pin “H” “L” “1” IR bit in TAiIC register “0” fj : Count source frequency (f1, f8, f2n(1), fC32) Set to "0" by an interrupt request acknowledgement or by program n=000016 to FFFE16 i=0 to 4 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 15.14 16-bit Pulse Width Modulator Operation When 8 high-order bits of the reload register are set to "0216", 8 low-order bits of the reload register are set to "0216" and an external trigger (on falling edge of a signal applied to the TAiIN pin) is selected 1 / fj X (m + 1) X (28 – 1) Count source(1) Signal applied to TAiIN pin “H” “L” 1 / fj X (m + 1) Underflow signal of 8-bit prescaler(2) “H” “L” 1 / fj X (m + 1) X n PWM pulse output from TAiOUT pin “H ” “L” “1” IR bit in TAiIC register “0” fj : Count source frequency (f1, f8, f2n(3), fC32) m=0016 to FF16, n=0016 to FE16 i=0 to 4 Set to "0" by an interrupt request acknowledgement or by program NOTES: 1. 8-bit prescaler counts a count source. 2. 8-bit pulse width modulator counts underflow signals of the 8-bit prescaler. 3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 15.15 8-bit Pulse Width Modulator Operation Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 172 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer B) 15.2 Timer B Figure 15.16 shows a block diagram of the timer B. Figures 15.17 to 15.19 show registers associated with the timer B. The timer B supports the following three modes. The TMOD1 and TMOD0 bits in the TBiMR register (i=0 to 5) determine which mode is used. • Timer mode : The timer counts an internal count source. • Event counter mode : The timer counts pulses from an external source or overflow and underflow of another timer. • Pulse period/pulse width measurement mode : The timer measures pulse period or pulse width of an external signal. Table 15.8 lists TBiIN pin settings. High-order Bits of Data Bus Select Clock Source TCK1 and TCK0 00 00: Timer Mode f1 TMOD1 and 01: Pulse Period/Pulse Width TMOD0 01 f8 Measurement Mode f2n(1) 10 fc32 11 01: Event TCK1 Counter Mode TBj Overflow 1 Signal(2,3) TBiIN Polarity Switching and Edge Pulse 0 Low-order Bits of Data Bus 8 low-order bits 8 highorder bits Reload Register Counter TBiS Counter Reset Circuit TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5 Address 035116 035016 035316 035216 035516 035416 031116 031016 031316 031216 031516 031416 TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4 i=0 to 5 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. Overflow signal or underflow signal. 3. j=i-1, except j=2 when i=0 j=5 when i=3 TCK1 and TCK0, TMOD1 and TMOD0 : Bits in the TBiMR Register TBiS : Bits in the TABSR and the TBSR Register Figure 15.16 Timer B Block Diagram Timer Bi Register(1) (i=0 to 5) b15 b8 b7 b0 Symbol TB0 to TB2 TB3 to TB5 Address 035116 - 035016, 035316 - 035216, 035516 - 035416 031116 - 031016, 031316 - 031216, 031516 - 031416 After Reset Indeterminate Indeterminate Mode Timer Mode Event Counter Mode Function Setting Range RW If setting value is n, a count source 000016 to FFFF16 RW is divided by n+1 If setting value is n, a count source 000016 to FFFF16 RW is divided by n+1(2) RO Pulse Period/Pulse A count source is incremented Width Measurement between one valid edge and Mode another valid edge of TBiIN pulse NOTES: 1. Use 16-bit data for reading and writing. 2. The TBi register counts how many pulse inputs are provided externally or how many times another timer counter overflows and underflows. Figure 15.17 TB0 to TB5 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 173 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer B) Timer Bi Mode Register (i=0 to 5) b7 b6 b5 b4 b3 b2 b1 b0 Symbol TB0MR to TB5MR Address After Reset 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 Bit Symbol TMOD0 Bit Name b1b0 Function RW Operating Mode Select Bit TMOD1 MR0 MR1 MR2 MR3 TCK0 Count Source Select Bit TCK1 0 0 : Timer mode RW 0 1 : Event counter mode 1 0 : Pulse period measurement mode, pulse width measurement mode RW 1 1 : Do not set to this value RW Function varies depending on operating mode (1, 2) RW RW RW RW Function varies depending on operating mode RW NOTES: 1. Only MR2 bits in the TB0MR and TB3MR registers are enabled. 2. Nothing is assigned in the MR2 bit in the TB1MR, TB2MR, TB4MR and TB5MR registers. When write, set to "0". When read, its content is indeterminate. Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TABSR Address 034016 After Reset 0016 Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Bit Name Timer A0 Count Start Flag Timer A1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer A4 Count Start Flag Timer B0 Count Start Flag Timer B1 Count Start Flag Timer B2 Count Start Flag Function 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting RW RW RW RW RW RW RW RW RW Figure 15.18 TB0MR to TB5MR Registers, TABSR Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 174 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer B) Timer B3, B4,B5 Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol TBSR Address 030016 After Reset 000X XXXX2 Bit Symbol Bit Name Function RW Nothing is assigned. When write, set to "0". (b4 - b0) When read, its content is indeterminate. TB3S TB4S TB5S Timer B3 Count Start Flag Timer B4 Count Start Flag Timer B5 Count Start Flag 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting RW RW RW Figure 15.19 TBSR Register Table 15.8 Settings for the TBiIN Pins (i=0 to 5) Port Name Function PS1, PS3(1) Registers Setting PD7, PD9(1) Registers P90 P91 P92 P93 P94 P71 TB0IN TB1IN TB2IN TB3IN TB4IN TB5IN PS3_0=0 PS3_1=0 PS3_2=0 PS3_3=0 PS3_4=0 PS1_1=0 PD9_0=0 PD9_1=0 PD9_2=0 PD9_3=0 PD9_4=0 PD7_1=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" ( write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 175 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer B) 15.2.1 Timer Mode In timer mode, the timer counts an internally generated count source (see Table 15.9). Figure 15.20 shows the TBiMR register (i=0 to 5) in timer mode. Table 15.9 Timer Mode Specifications Item Count Source Counting Operation f1, f8, f2n(1), fC32 • The timer decrements a counter value When the timer counter underflows, content of the reload register is reloaded into the count register and counting resumes Divide Ratio Counter Start Condition Counter Stop Condition TBiIN Pin Function Read from Timer Write to Timer Specification 1/(n+1) n: setting value of the TBi register (i=0 to 5) 000016 to FFFF16 The TBiS bits in the TABSR and TBSR registers are set to "1" (starts counting) The TBiS bit is set to "0" (stops counting) Programmable I/O port The TBi register indicates counter value • When the timer counter stops, the value written to the TBi register is also written to both reload register and counter • While counting, the value written to the TBi register is written to the reload register (It is transferred to the counter at the next reload timing) Interrupt Request Generation Timing Timer counter underflows NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Timer Bi Mode Register (i=0 to 5) (Timer Mode) b7 b6 b5 b4 b3 b2 b1 b0 0 00 Symbol Address After reset TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 Bit Symbol TMOD0 Bit Name Function RW RW RW Operating Mode Select Bit TMOD1 MR0 MR1 Disabled in timer mode. Can be set to "0" or "1". b1b0 0 0 : Timer mode RW RW RW TB0MR, TB3MR registers: Set to "0" in timer mode MR2 TB1MR, TB2MR TB4MR, TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Set to "0" in timer mode b7 b6 MR3 TCK0 RW 0 0 : f1 0 1 : f8 1 0 : f2n(1) 1 1 : fC32 RW RW Count Source Select Bit TCK1 NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 15.20 TB0MR to TB5MR Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 176 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer B) 15.2.2 Event Counter Mode In event counter mode, the timer counts how many external signals are applied or how many times another timer overflows and underflows. (See Table 15.10) Figure 15.21 shows the TBiMR register (i=0 to 5) in event counter mode. Table 15.10 Event Counter Mode Specifications Item Count Source program) • TBj overflow or underflow signal (j=i-1, except j=2 when i=0, j=5 when i=3) Counting Operation • The timer decrements a counter value When the timer counter underflows, content of the reload register is reloaded into the count register to continue counting Divide Ratio Counter Start Condition Counter Stop Condition TBiIN Pin Function Read from Timer Write to Timer Specification • External signal applied to the TBiIN pin (i = 0 to 5) (valid edge can be selected by 1/(n+1) n : setting value of the TBi register 000016 to FFFF16 The TBiS bits in the TABSR and TBSR register are set to "1" (starts counting) The TBiS bit is set to "0" (stops counting) Programmable I/O port or count source input The TBi register indicates counter value • When the timer counter stops, the value written to the TBi register is also written to both reload register and counter • While counting, the value written to the TBi register is written to the reload register (It is transferred to the counter at the next reload timing) Interrupt Request Generation Timing The timer counter underflows Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 177 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer B) Timer Bi Mode Register (i=0 to 5) (Event Counter Mode) b7 b6 b5 b4 b3 b2 b1 b0 0 01 Symbol Address After reset TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 Bit Symbol TMOD0 TMOD1 MR0 Bit Name Operating Mode Select Bit b1b0 Function RW RW RW 0 1 : Event counter mode b3b2 Count Polarity Select Bit(1) MR1 0 0 : Counts falling edges of external signal RW 0 1 : Counts rising edges of external signal 1 0 : Counts falling and rising edges of external signal RW 1 1 : Do not set to this value RW TB0MR and TB3MR registers: Set to "0" in event counter mode MR2 TB1MR, TB2MR, TB4MR and TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Disabled in event counter mode. When write, set to "0". When read, its content is indeterminate. Disabled in event counter mode. Can be set to "0" or "1". Event Clock Select Bit 0 : Input signal from the TBiIN pin 1 : TBj overflows(2) MR3 TCK0 TCK1 RW RW NOTES: 1. MR0 and MR1 bit settings are enabled when the TCK1 bit is set to "0". The MR1 bit can be set to either "0" or "1", when the TCK1 bit is set to "1". 2. j=i – 1, except j=2 when i=0 and j=5 when i=3. Figure 15.21 TB0MR to TB5MR Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 178 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer B) 15.2.3 Pulse Period/Pulse Width Measurement Mode In pulse period/pulse width measurement mode, the timer measures pulse period or pulse width of an external signal. (See Table 15.11) Figure 15.22 shows the TBiMR register (i=0 to 5) in pulse period/pulse width measurement mode. Figure 15.23 shows an operation example in pulse period measurement mode. Figure 15.24 shows an operation example in the pulse width measurement mode. Table 15.11 Pulse Period/Pulse Width Measurement Mode Specifications Item Count Source Counting Operation f1, f8, f2n(3), fC32 • The timer increments a counter value Counter value is transferred to the reload register on the valid edge of a pulse to be measured. It is set to "000016" and the timer continues counting Counter Start Condition Counter Stop Condition The TBiS bits (i=0 to 5) in the TABSR and TBSR register are set to "1" (starts counting) The TBiS bit is set to "0" (stops counting) • The timer counter overflows The MR3 bit in the TBiMR register is set to "1" (overflow) simultaneously. When the TBiS bit is set to "1" (start counting) and the next count source is counted after setting the MR3 bit to "1" (overflow), the MR3 bit can be set to "0" (no overflow) by writing to the TBiMR register. TBiIN Pin Function Read from Timer Write to Timer Input for a pulse to be measured The TBi register indicates reload register values (measurement results)(2) Value written to the TBi register can be written to neither reload register nor counter Specification Interrupt Request Generation Timing • On the valid edge of a pulse to be measured(1) NOTES: 1. No interrupt request is generated when the pulse to be measured is on the first valid edge after the timer has started counting. 2. The TBi register is in an indeterminate state until the pulse to be measured is on the second valid edge after the timer has started counting. 3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 179 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer B) Timer Bi Mode Register (i=0 to 5) (Pulse Period / Pulse Width Measurement Mode) b7 b6 b5 b4 b3 b2 b1 b0 10 Symbol Address After reset TB0MR to TB5MR 035B16, 035C16, 035D16, 031B16, 031C16, 031D16 00XX 00002 Bit Symbol TMOD0 TMOD1 MR0 Bit Name Operating Mode Select Bit b1b0 Function RW RW 1 0 : Pulse period measurement mode, Pulse width measurement mode RW RW RW RW b3b2 Measurement Mode Select Bit(1) MR1 0 0 : Pulse period measurement 1 0 1 : Pulse period measurement 2 1 0 : Pulse width measurement 1 1 : Do not set to this value TB0MR, TB3MR registers: Set to "0" in pulse period/pulse width measurement mode MR2 TB1MR, TB2MR TB4MR, TB5MR registers: Nothing is assigned. When write, set to "0". When read, its content is indeterminate. 0 : No overflow Timer Bi Overflow Flag(2) 1 : Overflow b7b6 MR3 RO TCK0 Count Source Select Bit TCK1 0 0 : f1 0 1 : f8 1 0 : f2n(3) 1 1 : fC32 RW RW NOTES: 1. The MR1 and MR0 bits selects the following measurements. Pulse period measurement 1 (the MR1 and MR0 bits are set to "002") : Measures between the falling edge and the next falling edge of a pulse to be measured Pulse period measurement 2 (the MR1 and MR0 bits are set to "012") : Measures between the rising edge and the next rising edge of a pulse to be measured Pulse width measurement (the MR1 and MR0 bits are set to "102") : Measures between a falling edge and the next rising edge of a pulse to be measured and between the rising edge and the next falling edge of a pulse to be measured 2. The MR3 bit is indeterminate when reset. To set the MR3 bit to "0", se the TBiMR register after the MR3 bit is set to "1" and one or more cycles of the count source are counted, while the TBiS bits in the TABSR and TBSR registers are set to "1" (starts counting). The MR3 bit cannot be set to "1" by program. 3. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 15.22 TB0MR to TB5MR Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 180 of 495 M32C/84 Group (M32C/84, M32C/84T) 15. Timer (Timer B) Count source Pulse to be measured "H" "L" Transferred (indeterminate value) Transferred (measured value) Timing to transfer value from counter to reload register Timing that the counter reaches "000016" "1" (Note 1) (Note 1) (Note 2) TBiS bits in TABSR and TBSR registers "0" IR bit in TBilC register "1" "0" Set to "0" by an interrupt request acknowledgement or by program MR3 bit in TBiMR register "1" "0" i=0 to 5 NOTES: 1. The counter is reset when a measurement is completed. 2. The timer counter overflows. Figure 15.23 Operation Example in Pulse Period Measurement Mode Count source "H" Pulse to be measured "L" Timing to transfer value from counter to reload register Timing that the counter reaches "000016" "1" "0" "1" "0" Transferred (indeterminate value) Transferred (measured value) Transferred (measured value) Transferred (measured value) (Note 1) (Note 1) (Note 1) (Note 1) (Note 2) TBiS bits in TABSR and TBSR registers IR bit in TBilC register Set to "0" by an interrupt request acknowledgement or by program. MR3 bit in TBiMR register “1” “0” i=0 to 5 NOTES: 1. The counter is reset when a measurement is completed. 2. The timer counter overflows. Figure 15.24 Operation Example in Pulse Width Measurement Mode Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 181 of 495 M32C/84 Group (M32C/84, M32C/84T) 16. Three-Phase Motor Control Timer Functions 16. Three-Phase Motor Control Timer Functions Three-phase motor driving waveform can be output by using the timers A1, A2, A4 and B2. Table 16.1 lists specifications of the three-phase motor control timer functions. Table 16.2 lists pin settings. Figure 16.1 shows a block diagram. Figures 16.2 to 16.7 show registers associated with the three-phase motor control timer functions. Table 16.1 Three-Phase Motor Control Timer Functions Specification Item ___ ___ ___ _______ Specification Apply a low-level ("L") signal to the NMI pin Timer A4, A1, A2 (used in one-shot timer mode): ___ Three-Phase Waveform Output Pin Six pins (U, U, V, V, W, W) Forced Cutoff(1) Timers to be Used Timer A4: U- and U-phase waveform control ___ Timer A1: V- and V-phase waveform control ___ Timer A2: W- and W-phase waveform control Timer B2 (used in timer mode): Carrier wave cycle control Dead time timer (three 8-bit timers share reload register): Dead time control Output Waveform Triangular wave modulation, Sawtooth wave modulation Can output a high-level waveform or a low-level waveform for one cycle; Can set positive-phase level and negative-phase level separately Carrier Wave Cycle Triangular wave modulation: count source x (m+1) x 2 Sawtooth wave modulation: count source x (m+1) m: setting value of the TB2 register, 000016 to FFFF16 Count source: f1, f8, f2n(2), fc32 Three-Phase PWM Output Width Triangular wave modulation: count source x n x 2 Sawtooth wave modulation: count source x n n : setting value of the TA4, TA1 and TA2 register (of the TA4, TA41, TA1, TA11, TA2 and TA21 registers when setting the INV11 bit to "1"), 000116 to FFFF16 Count source: f1, f8, f2n(2), fc32 Dead Time Count source x p, or no dead time p: setting value of the DTT register, 0116 to FF16 Count source: f1, or f1 divided by 2 Active Level current Active Disable Function Interrupt Frequency Selected from a high level ("H") or low level ("L") Positive and negative-phases concurrent active detect function For the timer B2 interrupt, one carrier wave cycle-to-cycle basis through 15 time- carrier wave cycle-to-cycle basis can be selected Positive- and Negative-Phase Con- Positive and negative-phases concurrent active disable function NOTES: _______ 1. Forced cutoff by the signal applied to the NMI pin is available when the INV02 bit is set to "1" (threephase motor control timer functions) and the INV03 bit is set to "1" (three-phase motor control timer output enabled). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 182 of 495 M32C/84 Group (M32C/84, M32C/84T) 16. Three-Phase Motor Control Timer Functions Table 16.2 Pin Settings Pin PS1, PS2 Registers(1) Setting PSL1, PSL2 Registers PSC Register P72/V P73/V P74/W P75/W P80/U P81/U PS1_2 =1 PS1_3 =1 PS1_4 =1 PS1_5 =1 PS2_0 =1 PS2_1 =1 PSL1_2 =0 PSL1_3 =1 PSL1_4 =1 PSL1_5 =0 PSL2_0 =1 PSL2_1 =0 PSC_2 =1 PSC_3 =0 PSC_4 =0 NOTES: 1. Set the PS1_5 to PS1_2 bits and PS2_1 and PS2_0 bits in the PS1 and PS2 registers to "1" after the INV02 bit is set to "1". Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 183 of 495 INV13 ICTB2 Register n=1 to 15 INV03 DQ T R INV07 to INV00: Bits in INVC0 Register INV15 to INV10: Bits in INVC1 Register DUi, DUBi: Bits in IDBi Register (i=0,1) TA4S to TA1S: Bits in TABSR Register INV00 1 0 PWCON INV07 f1 1/2 1 INV12 Trigger Trigger Dead Time Timer n = 1 to 255 DQ T Inverse Control Reload Register n = 1 to 255 0 ICTB2 Counter n=1 to 15 Timer B2 Interrupt Request Bit RESET NMI INV01 INV11 Circuit to set Interrupt Generating Frequency Value to be written to INV03 bit Write signal to INV03 bit Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 INV05 INV14 INV04 U INV02 INV06 U-Phase Output Control Circuit Transfer Trigger(1) D Q D Q T T Timer B2 Underflow Write Signal to Timer B2 INV10 Timer B2 (Timer Mode) M32C/84 Group (M32C/84, M32C/84T) Figure 16.1 Three-Phase Motor Control Timer Functions Block Diagram Page 184 of 495 DU1 bit DU0 bit U-Phase Output Signal TA41 Register Timer A4 One-Shot Pulse DUB1 bit DUB0 bit U-Phase Output Signal Three-Phase Output Shift Register (U Phase) INV11 D Q D Q T T Start Trigger Signal for Timers A1, A2, A4 Reload Control Signal for Timer A4 TA4 Register Reload Trigger Timer A4 Counter (One-Shot Timer Mode) TQ DQ T Inverse Control U When setting the TA4S bit to "0", signal is set to "0" Trigger Trigger TA11 Register INV06 V-Phase Output Signal V-Phase Output Control Circuit INV11 V-Phase Output Signal Dead Time Timer n = 1 to 255 DQ T Inverse Control V TA1 Register Reload Trigger Timer A1 Counter Inverse Control DQ T V (One-Shot Timer Mode) TQ Trigger Trigger INV06 Inverse Control Dead Time Timer n = 1 to 255 DQ T When setting the TA1S bit to "0", signal is set to "0" W TA2 Register TA21 Register Reload Trigger W-Phase Output Signal W-Phase Output Signal DQ T Inverse Control Timer A2 Counter W-Phase Output Control Circuit W (One-Shot Timer Mode) INV11 TQ 16. Three-Phase Motor Control Timer Functions When setting the TA2S bit to "0", signal is set to "0" Switching to P80, P81 and P72 to P75 is not shown in this diagram. NOTES: 1. Transfer trigger is generated only when the IDB0 and IDB1 registers are set and the first timer B2 counter underflows, if the INV06 bit is set to "0" (triangular wave modulation mode). M32C/84 Group (M32C/84, M32C/84T) 16. Three-Phase Motor Control Timer Functions Three-Phase PWM Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol INVC0 Bit Symbol Address 030816 After Reset 0016 Bit Name Interrupt Enable Output Polarity Select Bit(3) Interrupt Enable Output Specification Bit(2, 3) Function 0: The ICTB2 counter is incremented by one on the rising edge of the timer A1 reload control signal 1: The ICTB2 counter is incremented by one on the falling edge of the timer A1 reload control signal 0: ICTB2 counter is incremented by one when timer B2 counter underflows 1: Selected by the INV00 bit 0: No three-phase control timer function 1: Three-phase control timer function 0: Disables three-phase control timer output 1: Enables three-phase control timer output 0: Enables concurrent active output 1: Disables concurrent active output 0: Not detected 1: Detected 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode Transfer trigger is generated when the INV07 bit is set to "1". Trigger to the dead time timer is also generated when setting the INV06 bit to "1". Its value is "0" when read. RW INV00 RW INV01 RW INV02 Mode Select Bit(4, 5, 6) (6, 7) INV03 Output Control Bit RW RW Positive and NegativeINV04 Phases Concurrent Active Disable Function Enable Bit Positive and NegativeINV05 Phases Concurrent Active Output Detect Flag(8) INV06 Modulation Mode Select(9, 10) RW RW RW INV07 Software Trigger Select RW NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1" (write enable). Rewrite the INV02 to INV00 and INV06 bits when the timers A1,A2, A4 and B2 stop. 2. Set the INV01 bit to "1" after setting the ICTB2 register. 3. The INV01 and INV00 bit settings are enabled only when the INV11 bit in the INVC1 register is set to "1" (three-phase mode 1). The ICTB2 counter is incremented by one every time the timer B2 counter underflows, regardless of INV01 and INV00bit settings, when the INV11 bit is set to "0" (three-phase mode). When setting the INV01 bit to "1", set the timer A1 count start flag before the first timer B2 counter underflows. When the INV00 bit is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1 times, if n is the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 counter underflows. 4. Set the INV02 bit to "1" to operate the dead time timer, U-, V-and W-phase output control circuits and ICTB2 counter. 5. Set pins after the INV02 bit is set to "1". See Table 16.2 for pin settings. 6. When the INV02 bit is set to "1" and the INV03 bit to "0", the U, U, V, V, W and W pins, including pins shared with other output functions, are all placed in high-impedance states. 7. The INV03 bit is set to "0" when the followings occurs : - Reset - A concurrent active state occurs while the INV04 bit is set to "1" - The INV03 bit is set to "0" by program - An "H" signal applied to the NMI pin changes to an "L" signal 8. The INV05 bit can not be set to "1" by program. Set the INV04 bit to "0", as well, when setting the INV05 bit to "0". 9. The following table describes how the INV06 bit setting works. Item Mode Timing to Transfer from the IDB0 and IDB1 Registers to ThreePhase Output Shift Register INV06 = 0 Triangular wave modulation mode Transferred once by generating a transfer trigger after setting the IDB0 and IDB1 registers INV06 = 1 Sawtooth wave modulation mode Transferred every time a transfer trigger is generated Timing to Trigger the Dead Time On the falling edge of a one-shot pulse By a transfer trigger, or the falling edge of Timer when the INV16 Bit=0 a one-shot pulse of the timer A1, A2 or A4 of the timer A1, A2 or A4 INV13 Bit Enabled when the INV11 bit=1 and the Disabled INV06 bit=0 Transfer trigger : Timer B2 counter underflows and write to the INV07 bit, or write to the TB2 register when INV10 = 1 10. When the INV06 bit is set to "1", set the INV11 bit to "0" (three-phase mode 0) and the PWCON bit in the TB2SC register to "0" (timer B2 counter underflows). Figure 16.2 INVC0 Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 185 of 495 M32C/84 Group (M32C/84, M32C/84T) 16. Three-Phase Motor Control Timer Functions Three-Phase PWM Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 0 Symbol INVC1 Bit Symbol Address 030916 After Reset 0016 Bit Name Timer A1, A2 and A4 Start Trigger Select Bit Timer A1-1, A2-1 and A4-1 Control Bit(2, 3) Function 0: Timer B2 counter underflows 1: Timer B2 counter underflows and write to the TB2 register 0: Three-phase mode 0 1: Three-phase mode 1 RW RW INV10 INV11 RW INV12 Dead Time Timer 0 : f1 Count Source Select Bit 1 : f1 divided-by-2 Carrier Wave Detect Flag(4) RW INV13 0: Timer A1 reload control signal is "0" RO 1: Timer A1 reload control signal is "1" 0 : Active "L" of an output waveform 1 : Active "H" of an output waveform 0: Enables dead time 1: Disables dead time RW INV14 Output Polarity Control Bit INV15 Dead Time Disable Bit RW INV16 0: Falling edge of a one-shot pulse of Dead Time Timer Trigger the timer A1, A2 and A4(5) RW 1: Rising edge of the three-phase output Select Bit shift register (U-, V-, W-phase) Reserved Bit Set to "0" RW (b7) NOTES: 1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to "1" (write enable). The timers A1, A2, A4, and B2 must be stopped during rewrite. 2. The following table lists how the INV11 bit setting works. Item Mode INV11 = 0 Three-phase mode 0 INV11 = 1 Three-phase mode 1 Used Enabled Enabled when INV11=1 and INV06=0 TA11, TA21 and TA41 Registers Not used INV01 and INV00 Bit in the INVC0 Register INV13 Bit Disabled. The ICTB2 counter is incremented whenever the timer B2 counter underflows Disabled 3. When the INV06 bit in the INVC0 registser is set to "1" (sawtooth wave modulation mode), set the INV11 bit to "0". Also, when the INV11 bit is set to "0", set the PWCON bit in the TB2SC register to "0" (Timer B2 counter underflows). 4. The INV13 bit setting is enabled only when the INV06 bit is set to "0" (Triangular wave modulation mode) and the INV11 bit to "1". 5. If the following conditions are all met, set the INV16 bit to "1". • The INV15 bit is set to "0" • The Dij bit (i=U, V or W, j=0, 1) and DiBj bit always have different values when the INV03 bit in the INVC0 register is set to "1". (The positive-phase and negative-phase outputs always provide opposite level signals.) If the above conditions are not met, set the INV16 bit to "0". Figure 16.3 INVC1 Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 186 of 495 M32C/84 Group (M32C/84, M32C/84T) 16. Three-Phase Motor Control Timer Functions Three-Phase Output Buffer Register i(1) (i=0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset IDB0, IDB1 Bit Symbol DUi DUBi DVi DVBi DWi DWBi 030A16, 030B16 XX11 11112 Bit Name Function RW RW RW RW RW RW RW U-Phase Output Buffer i Write output level U-Phase Output Buffer i 0: Active level 1: Inactive level V-Phase Output Buffer i V-Phase Output Buffer i When read, the value of the threeW-Phase Output Buffer i phase shift register is read. W-Phase Output Buffer i Reserved Bit When read, its content is indeterminate (b7 - b6) RO NOTES: 1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a transfer trigger. After the transfer trigger occurs, the values written in the IDB0 register determine each phase output signal level first. Then the value written in the IDB1 register on the falling edge of the timers A1, A2 and A4 one-shot pulse determines each phase output signal level. Dead Time Timer(1, 2) b7 b0 Symbol DTT Address 030C16 After Reset Indeterminate Function If setting value is n, the timer stops when counting n times a count source selected by the INV12 bit after start trigger occurs. Positive or negative phase, which changes from inactive level to active level, shifts when the dead time timer stops. Setting Range RW 1 to 255 WO NOTES: 1. Use the MOV instruction to set the DTT register. 2. The DTT register setting is enabled when the INV15 bit in the INVC1 register is set to "0" (dead time enabled). No dead time can be set when the INV15 bit is set to "1" (dead time disabled). The INV06 bit in the INVC0 register determines start trigger of the DTT register. Figure 16.4 IDB0 and IDB1 registers, DTT Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 187 of 495 M32C/84 Group (M32C/84, M32C/84T) 16. Three-Phase Motor Control Timer Functions Timer B2 Interrupt Generation Frequency Set Counter(1, 2, 3) b7 b0 Symbol Address After Reset ICTB2 030D16 Function Indeterminate Setting Range RW When the INV01 bit is set to "0" (the ICTB2 counter increments whenever the timer B2 counter underflows) and the setting value is n, the timer B2 interrupt is generated every nth time timer B2 counter underflow occurs. When the INV01 bit is set to "1" (the INV00 bit selects count timing of the ICTB2 counter) and setting value is n, the timer B2 interrupt is generated every nth time timer B2 counter underflow meeting the condition selected in the INV00 bit occurs. Nothing is assigned. When write, set to "0". 1 to 15 WO NOTES: 1. Use the MOV instruction to set the ICTB2 register. 2. If the INV01 bit in the INVC0 register is set to "1", set the ICTB2 register in the TABSR register when the TB2S bit is set to "0" (timer B2 counter stopped). If the INV01 bit is set to "0" and the TB2S bit to "1" (timer B2 counter start), do not set the ICTB2 register when the timer B2 counter underflows. 3. If the INV00 bit in the INVC0 register is set to "1", the first interrupt is generated when the timer B2 counter underflows n-1 times, n being the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 counter underflows. Timer Ai, Ai-1 Register (i=1, 2, 4)(1, 2, 3, 4, 5, 6) b15 b8 b7 b0 Symbol TA1, TA2, TA4 TA11, TA21, TA41 Address After Reset 034916 - 034816, 034B16 - 034A16, 034F16 - 034E16 Indeterminate 030316 - 030216, 030516 - 030416, 030716 - 030616 Indeterminate Function If setting value is n, the timer stops when the n th count source is counted after a start trigger is generated. Positive phase changes to negative phase, and vice versa, when the timers A1, A2 and A4 stop. Setting Range RW 000016 to FFFF16 WO NOTES: 1. Use a 16-bit data for read and write. 2. If the TAi or TAi1 register is set to "000016", no counter starts and no timer Ai interrupt is generated. 3. Use the MOV instruction to set the TAi and TAi1 registers. 4. When the INV15 bit in the INVC1 register is set to "0" (dead timer enabled), phase switches from an inactive level to an active level when the dead time timer stops. 5. When the INV11 bit in the INVC1 register is set to "0" (three-phase mode 0), the value of the TAi register is transferred to the reload register by a timer Ai start trigger. When the INV11 bit is set to "1" (three-phase mode 1), the value of the TAi1 register is first transferred to the reload register by a timer Ai start trigger. Then, the value of the TAi register is transferred by the next trigger. The values of the TAi1 and TAi registers are transferred alternately to the reload register with every timer Ai start trigger. 6. Do not write to these registers when the timer B2 counter underflows. Timer B2 Special Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset TB2SC Bit Symbol PWCON 035E16 XXXX XXX02 Bit Name Timer B2 Reload Timing Switching Bit(1) Function 0 : Timer B2 counter underflows 1 : Timer A output in odd-number times RW RW Nothing is assigned. When write, set to "0". When read, its content is "0." NOTES: 1. Set the PWCON bit to "0" when setting the INV11 bit to "0" (three-phase mode 0) or the INV06 bit to "1" (sawtooth wave modulation mode). Figure 16.5 ICTB2 Register, TA1, TA2, TA4, TA11, TA21 and TA41 Registers, TB2SC Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 188 of 495 M32C/84 Group (M32C/84, M32C/84T) 16. Three-Phase Motor Control Timer Functions Timer B2 Register(1) b15 b8 b7 b0 Symbol TB2 Address 035516 - 035416 After Reset Indeterminate Function If setting value is n, count source is divided by n+1. The timers A1, A2 and A4 start every time an underflow occurs. NOTES: 1. Use a 16-bit data for read and write. Setting Range 000016 to FFFF16 RW RW Trigger Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset TRGSR Bit Symbol TA1TGL TA1TGH TA2TGL TA2TGH TA3TGL 034316 0016 Bit Name Timer A1 Event/Trigger Select Bit Timer A2 Event/Trigger Select Bit Function Set to "012" (TB2 underflow) before using a V-phase output control circuit Set to "012" (TB2 underflow) before using a W-phase output control circuit b5 b4 RW RW RW RW RW RW RW RW RW Timer A3 Event/Trigger Select Bit TA3TGH TA4TGL TA4TGH Timer A4 Event/Trigger Select Bit 0 0 1 1 0 : Selects an input to the TA3IN pin 1 : Selects TB2 overflow(1) 0 : Selects TA2 overflow(1) 1 : Selects TA4 overflow(1) Set to "012" (TB2 underflow) before using a U-phase output control circuit NOTES: 1. Overflow or underflow Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset TABSR Bit Symbol TA0S 034016 0016 Bit Name Timer A0 Count Start Flag Timer A1 Count Start Flag Timer A2 Count Start Flag Timer A3 Count Start Flag Timer A4 Count Start Flag Timer B0 Count Start Flag Timer B1 Count Start Flag Timer B2 Count Start Flag Function 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting 0 : Stops counting 1 : Starts counting RW RW TA1S RW TA2S RW TA3S RW TA4S RW TB0S TB1S RW RW TB2S RW Figure 16.6 TB2, TRGSR and TABSR Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 189 of 495 M32C/84 Group (M32C/84, M32C/84T) 16. Three-Phase Motor Control Timer Functions Timer Ai Mode Register (i=1, 2, 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 0 100 1 0 TA1MR, TA2MR, TA4MR Bit Symbol 035716, 035816, 035A16 0016 Bit Name Function Set to "102" (one-shot timer mode) when using the three-phase motor control timer function Set to "0" RW RW TMOD0 Operating Mode TMOD1 Select Bit MR0 Reserved Bit RW MR1 External Trigger Select Bit Set to "0" when using the three-phase RW motor control timer function Trigger Select Bit Set to "1" (selected by the TRGSR register) when using the threephase motor control timer function RW MR2 MR3 Set to "0" with the three-phase motor control timer function b7 b6 RW TCK0 Count Source Select Bit TCK1 0 0 1 1 0 : f1 1 : f8 0 : f2n(1) 1 : fC32 RW RW NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Timer B2 Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset 00000 TB2MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 035D16 00XX 00002 Bit Name Function RW Set to "002" (timer mode) when using Operating Mode RW the three-phase motor control timer Select Bit function Disabled when using the three-phase motor control timer function. When write, set to "0". When read, its content is indeterminate. Set to "0" when using three-phase motor control timer function Nothing is assigned. When write, set to "0". When read, its content is indeterminate. b7 b6 RW RW TCK0 Count Source Select Bit TCK1 0 0 1 1 0 : f1 1 : f8 0 : f2n(1) 1 : fC32 RW RW NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 16.7 TA1MR, TA2MR and TA4MR Registers, TB2MR Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 190 of 495 M32C/84 Group (M32C/84, M32C/84T) 16. Three-Phase Motor Control Timer Functions The three-phase motor control timer function is available by setting the INV02 bit in the INVC0 register to "1". The timer B2 is used for carrier wave control and the timers A1, A2, A4 for three-phase PWM output __ __ ___ (U, U, V, V, W, W) control. An exclusive dead time timer controls dead time. Figure 16.8 shows an example of the triangular modulation waveform. Figure 16.9 shows an example of the sawtooth modulation waveform. Triangular waveform as a Carrier Wave Triangular Wave Signal Wave TB2S Bit in TABSR Register Timer B2 Timer A1 Reload Control Signal(1) Timer A4 Start Trigger Signal(1) TA4 Register(2) TA4-1 Register(2) Reload Register(2) m m m m m m n n n n n n n p p p p p p q q q q q q r r r Timer A4 One-Shot Pulse(1) U-Phase Output Signal(1) U-Phase Output Signal(1) U-Phase INV14 = 0 ("L" active) U-Phase Rewrite the IDB0 and IDB1 registers Transfer the values to the three-phase shift register Dead time INV14 = 1 ("H" active) U-Phase Dead time U-Phase INV00, INV01: Bits in INVC0 register INV11, INV14: Bits in INVC1 register NOTES: 1. Internal signals. See Figure 16.1. 2. Applies only when the INV11 bit is set to "1" (three-phase mode). The above applies to INVC0 = 00XX11XX2 and INVC1 = 010XXXX02 (X varies depending on each system.) Examples of PWM output change are (b) When INV11=0 (three-phase mode 0) (a) When INV11=1 (three-phase mode 1) - INV01=0, ICTB2=116 (The timer B2 interrupt is generated - INV01=0 and ICTB2=216 (The timer B2 interrupt is whenever the timer B2 underflows) generated with every second timer B2 underflow) or - Default value of the timer: TA4=m INV01=1, INV00=1and ICTB2=116 (The timer B2 interrupt is The TA4 register is changed whenever the timer B2 generated on the falling edge of the timer A reload control interrupt is generated. signal) First time: TA4=m. Second time: TA4=n. - Default value of the timer: TA41=m, TA4=m Third time: TA4=n. Fourth time: TA=p. The TA4 and TA41 registers are changed whenever the Fifth time: TA4=p. timer B2 interrupt is generated. - Default value of the IDB0 and IDB1 registers: First time: TA41=n, TA4:=n. DU0=1, DUB0=0, DU1=0, DUB1=1 Second time: TA41=p, TA4=p. They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by - Default value of the IDB0 and IDB1 registers the sixth timer B2 interrupt. DU0=1, DUB0=0, DU1=0, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by the third timer B2 interrupt. Figure 16.8 Triangular Wave Modulation Operation Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 191 of 495 M32C/84 Group (M32C/84, M32C/84T) 16. Three-Phase Motor Control Timer Functions Sawtooth Waveform as a Carrier Wave Sawtooth Wave Signal Wave Timer B2 Timer A4 Start Trigger Signal(1) Timer A4 One-Shot Pulse(1) Rewrite the IDB0 and IDB1 registers Transfer the register values to the three-phase shift register U-Phase (1) Output Signal U-Phase (1) Output Signal U-Phase INV14 = 0 ("L" active) Dead time U-Phase U-Phase INV14 = 1 ("H" active) U-Phase INV14: Bits in INVC1 register NOTES: 1. Internal signals. See Figure 16.1. The above applies to INVC0 = 01XX110X2 and INVC1 = 000XXX002 (X varies depending on each system.) The examples of PWM output change are - Default value of the IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1 They are changed to DU0=1, DUB0=0, DU1=1, DUB1=1 by the timer B2 interrupt. Dead time Figure 16.9 Sawtooth Wave Modulation Operation Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 192 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O 17. Serial I/O Serial I/O consists of five channels (UART0 to UART4). Each UARTi (i=0 to 4) has an exclusive timer to generate the transfer clock and operates independently. Figure 17.1 shows a UARTi block diagram. UARTi supports the following modes : - Clock synchronous serial I/O mode - Clock asynchronous serial I/O mode (UART mode) - Special mode 1 (I2C mode) - Special mode 2 - Special mode 3 (Clock-divided synchronous function, GCI mode) - Special mode 4 (Bus conflict detect function, IE mode) - Special mode 5 (SIM mode) Figures 17.2 to 17.9 show registers associated with UARTi. Refer to the tables listing each mode for register and pin settings. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 193 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O RxDi RxD Polarity Switching Circuit Selecting Clock Source 00 CKDIR f1 Internal 01 0 f8 10 f2n(2) CLK1 and 1 CLK0 External UiBRG Register 1 / (m+1) Clock Asynchronous Receive SMD2 to SMD0 010, 100, 101, 110 1/16 Receive 001 Control Circuit Clock Synchronous Clock Asynchronous Transmit 1/16 010, 100, 101, 110 Clock Synchronous 001 Clock Synchronous (when internal clock is selected) Transmit Control Circuit Receive Clock TxD Polarity Switching Circuit Transmit/ Receive Unit (Note 1) TxDi Transmit Clock CKPOL CLK Polarity Switching Circuit 0 1 Clock Synchronous CKDIR Clock Synchronous (when internal clock is selected) (when external clock is selected) 1/2 CLKi CTSi / RTSi CTS/RTS selected 1 CRS 0 0 1 VSS CTS/RTS disabled CRD RTSi CRD CTS/RTS disabled CTSi m : setting value of UiBRG register NOTES: 1. P70 and P71 are ports for the N-channel open drain output, but not for the CMOS output. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 0 RxDi RxD Data Inverse Circuit 1 IOPOL No inverse Inverse Clock Synchronous 7-bit Clock Asynchronous 8-bit Clock Asynchronous STPS 1SP 0 PRYE PAR Clock disabled Synchronous 0 7-bit Clock Asynchronous UARTi Receive Register 0 0 SP 1 2SP SP PAR Clock 1 Asynchronous PAR enabled SMD2 to SMD0 1 9-bit Clock Asynchronous Type Clock 1 Synchronous 8-bit Clock Asynchronous 9-bit Clock Asynchronous 0 0 0 0 0 0 0 D8 D7 D6 D5 D4 D3 D2 D1 D0 UiRB Register Logic Inverse Circuit + MSB/LSB Conversion Circuit High-order bits of data bus Low-order bits of data bus Logic Inverse Circuit + MSB/LSB Conversion Circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UiTB Register PRYE STPS SMD2 to SMD0 2SP 1 PAR enabled 1 Clock Asynchronous 1 9-bit Clock Asynchronous 1 8-bit Clock Asynchronous 9-bit Clock Asynchronous Clock Synchronous 1 SP SP 0 1SP PAR 0 Clock PAR Synchronous disabled 0 0 7-bit Clock Asynchronous 8-bit Clock Asynchronous Clock Synchronous 0 7-bit Clock Asynchronous UARTi Transmit Register Error Signal Output disable 0 IOPOL 0 No inverse TxD Data Inverse Circuit TxDi SP: Stop bit PAR: Parity bit i=0 to 4 SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in the UiMR register CLK1 and CLK0, CKPOL, CRD, CRS: Bits in the UiC0 register UiERE: Bit in the UiC1 register UiERE Error Signal Output Circuit 1 Error Signal Output enable 1 Inverse Figure 17.1 UARTi Block Diagram Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 194 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O UARTi Transmit Buffer Register (i=0 to 4)(1) b15 b8 b7 b0 Symbol Address U0TB to U2TB 036B16-036A16, 02EB16-02EA16, 033B16-033A16 U3TB, U4TB 032B16-032A16, 02FB16-02FA16 Bit Symbol After Reset Indeterminate Indeterminate Function RW WO WO (b7 - b0) Transmit data (D7 to D0) Transmit data (D8) (b8) Nothing is assigned. When write, set to "0". (b15 - b9) When read, its content is indeterminate. NOTES: 1. Use the MOV instruction to set the UiTB register. UARTi Receive Buffer Register (i=0 to 4) b15 b8 b7 b0 Symbol Address U0RB to U2RB 036F16 - 036E16, 02EF16 - 02EE16, 033F16 - 033E16 U3RB, U4RB 032F16 - 032E16, 02FF16 - 02FE16 Bit Symbol After Reset Indeterminate Indeterminate Bit Name Function Received data (D7 to D0) RW RO RO (b7 - b0) (b8) Received data (D8) Nothing is assigned. When write, set to "0". (b10 - b9) When read, its content is indeterminate. ABT Arbitration Lost Detect Flag(1) 0: Not detected (win) 1: Detected (lose) RW RO RO RO RO OER FER 0: No overrun error occurs Overrun Error Flag(2) 1: Overrun error occurs Framing Error Flag(2, 3) Parity Error Flag(2, 3) Error Sum Flag(2, 3) 0: No framing error occurs 1: Framing error occurs 0: No parity error occurs 1: Parity error occurs 0: No error occurs 1: Error occurs PER SUM NOTES: 1. The ABT bit can be set to "0" only. 2. When the SMD2 to SMD0 bits in the UiMR register are set to "0002" (serial I/O disable) or the RE bit in the UiC1 register is set to "0" (receive disable), the OER, FER, PER and SUM bits are set to "0". When all OER, FER and PER bits are set to "0", the SUM bit is set to "0". Also, the FER and PER bits are set to "0" by reading low-order bits in the UiRB register. 3. These error flags are disabled when the SMD2 to SMD0 bits are set to "0012" (clock synchronous serial I/O mode) or to "0102" (I2C mode). When read, the contents are indeterminate. Figure 17.2 U0TB to U4TB Registers and U0RB to U4RB Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 195 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O UARTi Bit Rate Register (i=0 to 4)(1, 2) b7 b0 Symbol Address U0BRG to U4BRG 036916, 02E916, 033916, 032916, 02F916 Function If the setting value is m, the UiBRG register divides a count source by m+1 After Reset Indeterminate Setting Range 0016 to FF16 RW WO NOTES: 1. Use the MOV instruction to set the UiBRG register. 2. Set the UiBRG register while no data transfer occurs. UARTi Transmit/Receive Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0MR to U4MR Bit Symbol Address 036816, 02E816, 033816, 032816, 02F816 After Reset 0016 Bit Name b2 b1 b0 Function RW SMD0 SMD1 SMD2 0 0 0: Serial I/O disabled RW 0 0 1: Clock synchronous serial I/O mode 2 Serial I/O Mode Select 0 1 0: I C mode RW 1 0 0: UART mode, 7-bit transfer data Bit 1 0 1: UART mode, 8-bit transfer data 1 1 0: UART mode, 9-bit transfer data RW Do not set value other than the above Internal/External Clock 0 : Internal clock Select Bit 1 : External clock Stop Bit Length Select 0 : 1 stop bit Bit 1 : 2 stop bits Odd/Even Parity Select Enables when PRYE = 1 0 : Odd parity Bit 1 : Even parity Parity Enable Bit 0 : Disables a parity 1 : Enables a parity RW RW CKDIR STPS PRY RW PRYE RW IOPOL TxD,RxD Input/Output 0: Not inversed Polarity Switch Bit 1: Inverse RW Figure 17.3 U0BRG to U4BRG Registers and U0MR to U4MR Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 196 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O UARTi Transmit/Receive Control Register 0 (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0C0 to U4C0 Bit Symbol Address 036C16, 02EC16, 033C16, 032C16, 02FC16 After Reset 0000 10002 Bit Name b1 b0 Function RW RW CLK0 UiBRG Count Source Select Bit CLK1 0 0: Selects f1 0 1: Selects f8 1 0: Selects f2n(2) 1 1: Do not set to this value RW CRS CST/RTS Function Enabled when CRD=0 0 : Selects CTS function Select Bit 1 : Selects RTS function Transmit Register Empty Flag CTS/RTS Disable Bit 0 : Data in the transmit register (during transmission) 1 : No data in the transmit register (transmission is completed) 0 : Enables CTS/RTS function 1 : Disables CTS/RTS function RW TXEPT RO CRD RW 0 : TxDi/SDAi and SCLi are ports for the Data Output Select CMOS output NCH RW Bit(1) 1 : TxDi/SDAi and SCLi are ports for the N-channel open drain output 0 : Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge CLK Polarity CKPOL RW 1 : Data is transmitted on the rising edge of Select Bit the transfer clock and data is received on the falling edge UFORM Transfer Format Select Bit(3) 0 : LSB first 1 : MSB first RW NOTES: 1. P70/TxD2 and P71/SCL2 are ports for the N-channel open drain output, but not for the CMOS output. 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 3. The UFORM bit setting is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "0012" (clock syncronous serial I/O mode) or "1012" (UART mode, 8-bit transfer data). Set the UFORM bit to "1" when setting the SMD2 to SMD0 bits to"0102" (I2C mode), or to "0" when setting them to "1002" (UART mode, 7-bit transfer data) or "1102" (UART mode, 9-bit transfer data). Figure 17.4 U0C0 to U4C0 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 197 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O UARTi Transmit/Receive Control Register 1 (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0C1 to U4C1 Bit Symbol Address 036D16, 02ED16, 033D16, 032D16, 02FD16 After Reset 0000 00102 Bit Name Transmit Enable Bit Function 0: Transmit disable 1: Transmit enable RW RW RO RW TE TI RE Transmit Buffer 0: Data in the UiTB register 1: No data in the UiTB register Empty Flag Receive Enable Bit Receive Complete Flag 0: Receive disable 1: Receive enable 0: No data in the UiRB register 1: Data in the UiRB register RI RO UiIRS UARTi Transmit 0: No data in the UiTB register (TI = 1) Interrupt Cause 1: Transmission is completed (TXEPT = 1) Select Bit UARTi Continuous Receive Mode Enable Bit Data Logic Select Bit(2) RW UiRRM 0: Disables continuous receive mode to be entered RW 1: Enables continuous receive mode to be entered 0: Not inversed 1: Inverse RW UiLCH Clock-Divided Synchronous Stop SCLKSTPB Bit / /UiERE Error Signal Output Enable Bit(1) Clock-divided synchronous stop bit (special mode 3) 0: Stops synchronizing 1: Starts synchronizing RW Error signal output enable bit (special mode 5) 0: Not output 1: Output NOTES: 1. Set the SCLKSTPB/UiERE bit after setting the SMD2 to SMD0 bits in the UiMR register. 2. The UiLCH bit setting is enabled when setting the SMD2 to SMD0 bits to "0012" (clock syncronous serial I/O mode), "1002" (UART mode, 7-bit transfer data) or "1012" (UART mode, 8-bit transfer data). Set the UiLCH bit to "0" when setting the SMD2 to SMD0 bits to"0102" (I2C mode) or "1102" (UART mode, 9-bit transfer data). UARTi Special Mode Register (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR to U4SMR Bit Symbol Address 036716, 02E716, 033716, 032716, 02F716 After Reset 0016 Bit Name I2C Mode Select Bit Function 0: Except I2C mode 1: I2C mode RW RW RW RW(1) RW RW IICM ABC BBS LSYN ABSCS Arbitration Lost Detect 0: Update per bit Flag Control Bit 1: Update per byte Bus Busy Flag SCLL Sync Output Enable Bit 0: Stop condition detected 1: Start condition detected (Busy) 0: Disabled 1: Enabled Bus Conflict Detect 0: Rising edge of transfer clock Sampling Clock Select Bit 1: Timer Aj underflow(j=0 to 4)(2) Auto Clear Function Select 0: No auto clear function Bit for Transmit Enable Bit 1: Auto clear at bus conflict Transmit Start Condition Select Bit Clock Divide Synchronous Bit 0: Not related to RxDi 1: Synchronized with RxDi (Note 3) ACSE SSS SCLKDIV RW RW RW NOTES: 1. The BBS bit is set to "0" by program. It is unchanged if set to "1". 2. UART0: timer A3 underflow signal, UART1: timer A4 underflow signal, UART2: timer A0 underflow signal, UART3: timer A3 underflow signal, UART4: timer A4 underflow signal. 3. Refer to notes for the SU1HIM bit in the UiSMR2 register. Figure 17.5 U0C1 to U4C1 Registers and U0SMR to U4SMR Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 198 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O UARTi Special Mode Register 2 (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR2 to U4SMR2 Bit Symbol Address 036616, 02E616, 033616, 032616, 02F616 After Reset 0016 Bit Name I2C Mode Select Bit 2 (Note 1) Function RW RW RW IICM2 CSC Clock Synchronous Bit 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Output 1: No output 0: Disabled 1: Enabled 0: Transfer clock 1: "L" output 0: Output 1: No output (high-impedance) (Note 2) SWC SCL Wait Output Bit RW ALS SDA Output Stop Bit RW STC UARTi Initialize Bit RW SWC2 SCL Wait Output Bit 2 RW SDHI SDA Output Inhibit Bit External Clock Synchronous Enable Bit RW SU1HIM RW NOTES: 1. Refer to Table 17.14. 2. The external clock synchronous function can be selected by combining the SU1HIM bit and the SCLKDIV bit in the UiSMR register. SCLKDIV bit in the UiSMR Register 0 0 1 SU1HIM bit in the UiSMR2 Register 0 1 0 or 1 External Clock Synchronous Function Selection No synchronization Same division as the external clock External clock divided by 2 Figure 17.6 U0SMR2 to U4SMR2 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 199 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O UARTi Special Mode Register 3 (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR3 to U4SMR3 Bit Symbol Address 036516, 02E516, 033516, 032516, 02F516 After Reset 0016 Bit Name Function RW RW RW SSE CKPH SS Pin Function Enable Bit(1) Clock Phase Set Bit Serial Input Port Set Bit Clock Output Select Bit Fault Error Flag(2) 0: Disables SS pin function 1: Enables SS pin function 0: No clock delay 1: Clock delay 0: Selects the TxDi and RxDi pins (master mode) 1: Selects the STxDi and SRxDi pins (slave mode) 0: CMOS output 1: N-channel open drain output 0: No error 1: Error b7 b6 b5 DINC RW NODC ERR RW RW DL0 SDAi Digital Delay Time Set Bit(3, 4) DL1 DL2 000 : No delay 001 : 1-to-2 cycles of BRG count source 010 : 2-to-3 cycles of BRG count source 011 : 3-to-4 cycles of BRG count source 100 : 4-to-5 cycles of BRG count source 101 : 5-to-6 cycles of BRG count source 110 : 6-to-7 cycles of BRG count source 111 : 7-to-8 cycles of BRG count source RW RW RW NOTES: 1. Set the SS pin after the CRD bit in the UiC0 register is set to "1" (CTS/RTS function disabled). 2. The ERR bit is set to "0" by program. It is unchanged if set to "1". 3. Digital delay is generated from a SDAi output by the DL2 to DL0 bits in I2C mode. Set these bits to "0002" (no delay) except in the I2C mode. 4. When the external clock is selected, approximately 100ns delay is added. Figure 17.7 U0SMR3 to U4SMR3 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 200 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O UARTi Special Mode Register 4 (i=0 to 4) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR4 to U4SMR4 Bit Symbol Address 036416, 02E416, 033416, 032416, 02F416 After Reset 0016 Bit Name Start Condition Generate Bit(1) Restart Condition Generate Bit(1) Stop Condition Generate Bit(1) SCL, SDA Output Select Bit ACK Data Bit ACK Data Output Enable Bit SCL Output Stop Enable Bit SCL Wait Output Bit 3 0: Clear 1: Start 0: Clear 1: Start 0: Clear 1: Start Function RW RW STAREQ RSTAREQ RW STPREQ RW STSPSEL 0: Selects the serial I/O circuit 1: Selects the start/stop condition generating circuit 0: ACK 1: NACK 0: Serial I/O data output 1: ACK data output 0: Disabled 1: Enabled 0: SCL "L" hold disabled 1: SCL "L" hold enabled RW ACKD RW ACKC RW SCLHI RW SWC9 RW NOTES: 1. When each condition is generated, the STAREQ, RSTAREQ or STPREQ bit is set to "0". When a condition generation is incomplete, the bit remains unchanged as "1". Figure 17.8 U0SMR4 to U4SMR4 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 201 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O External Interrupt Request Source Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol IFSR Bit Symbol Address 031F16 After Reset 0016 Bit Name INT0 Interrupt Polarity Select Bit(1) INT1 Interrupt Polarity Select Bit(1) INT2 Interrupt Polarity Select Bit(1) INT3 Interrupt Polarity Select Bit(1) INT4 Interrupt Polarity select bit(1) INT5 Interrupt Polarity Select Bit(1) UART0, UART3 Interrupt Source Select Bit UART1, UART4 Interrupt Source Select Bit Function 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges 0 : One edge 1 : Both edges RW RW IFSR0 IFSR1 RW IFSR2 RW IFSR3 RW IFSR4 RW IFSR5 RW IFSR6 0 : UART3 bus conflict, start condition detect, stop condition detect RW 1 : UART0 bus conflict, start condition detect, stop condition detect 0 : UART4 bus conflict, start condition detect, stop condition detect RW 1 : UART1 bus conflict, start condition detect, stop condition detect IFSR7 NOTES: 1. Set this bit to "0" to select a level-sensitive triggering. When setting this bit to "1", set the POL bit in the INTilC register (i = 0 to 5) to "0" (falling edge). Figure 17.9 IFSR Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 202 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Clock Synchronous Serial I/O) 17.1 Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. Table 17.1 lists specifications of clock synchronous serial I/O mode. Table 17.2 lists register settings. Tables 17.3 to 17.5 list pin settings. When UARTi (i=0 to 4) operating mode is selected, the TxDi pin outputs a high-level ("H") signal before transfer starts (the TxDi pin is in a high-impedance state when the N-channel open drain output is selected). Figure 17.10 shows transmit and receive timings in clock synchronous serial I/O mode. Table 17.1 Clock Synchronous Serial I/O Mode Specifications Item Transfer Data Format Transfer Clock Specification Transfer data : 8 bits long • The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected): fj 2(m+1) fj=f1, f8, f2n(1) m :setting value of the UiBRG register, 0016 to FF16 • The CKDIR bit is set to "1" (external clock selected) : an input from the CLKi pin _______ _______ _______ _______ Selected from the CTS function, RTS function or CTS/RTS function disabled To start transmitting, the following requirements must be met(2): - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) ________ _______ - Apply a low-level ("L") signal to the CTSi pin when the CTS function is selected Receive Start Condition To start receiving, the following requirements must be met(2): - Set the RE bit in the UiC1 register to "1" (receive enable) - Set the TE bit to "1" (transmit enable) - Set the TI bit to "0" (data in the UiTB register) Interrupt Request Generation Timing • While transmitting, the following conditions can be selected: - The UiIRS bit in the UiC1 register is set to "0" (no data in the transmit buffer): when data is transferred from the UiTB register to the UARTi transmit register (transfer started) - The UiIRS bit is set to "1" (transmission completed): when a data transfer from the UARTi transmit register is completed • While receiving Error Detect When data is transferred from the UARTi receive register to the UiRB register (reception completed) Overrun error(3) This error occurs when the seventh bit of the next received data is read before reading the UiRB register Selectable Function • CLK polarity Transferred data output and input are provided on either the rising edge or falling edge of the transfer clock • LSB first or MSB first Data is transmitted or received in either bit 0 or in bit 7 • Continuous receive mode Data can be received simultaneously by reading the UiRB register • Serial data logic inverse This function inverses transmitted/received data logically NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) and the CLKi pin is held "H", or when the CKPOL bit is set to "1" (data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held "L". 3. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested). Transmit/Receive Control Transmit Start Condition Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 203 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Clock Synchronous Serial I/O) Table 17.2 Register Settings in Clock Synchronous Serial I/O Mode Register UiTB UiRB UiBRG UiMR Bit 7 to 0 7 to 0 OER 7 to 0 SMD2 to SMD0 CKDIR IOPOL UiC0 CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM UiLCH SCLKSTPB UiSMR UiSMR2 UiSMR3 7 to 0 7 to 0 2 to 0 NODC 7 to 4 UiSMR4 i=0 to 4 7 to 0 Set transmit data Received data can be read Overrun error flag Set bit rate Set to "0012" Select the internal clock or external clock Set to "0" Select count source for the UiBRG register _______ _______ Function Select CTS or RTS when using either Transmit register empty flag _______ _______ Enables or disables the CTS or RTS function Select output format of the TxDi pin Select transmit clock polarity Select either LSB first or MSB first Set to "1" to enable data transmission and reception Transmit buffer empty flag Set to "1" to enable data reception Reception complete flag Select what causes the UARTi transmit interrupt to be generated Set to "1" when using continuous receive mode Set to "1" when using data logic inverse Set to "0" Set to "0016" Set to "0016" Set to "0002" Select clock output format Set to "00002" Set to "0016" Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 204 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Clock Synchronous Serial I/O) Table 17.3 Pin Settings in Clock Synchronous Serial I/O Mode (1) Port P60 P61 P62 P63 P64 P65 P66 P67 Function PS0 Register __________ Setting PSL0 Register PSL0_4=0 PD6 Register PD6_0=0 PD6_1=0 PD6_2=0 PD6_4=0 PD6_5=0 PD6_6=0 PS0_0=0 PS0_0=1 PS0_1=0 PS0_1=1 PS0_2=0 PS0_3=1 PS0_4=0 PS0_4=1 PS0_5=0 PS0_5=1 PS0_6=0 PS0_7=1 CTS0 input __________ RTS0 output CLK0 input CLK0 output RxD0 input TxD0 output __________ CTS1 input _________ RTS1 output CLK1 input CLK1 output RxD1 input TxD1 output Table 17.4 Pin Settings (2) Port P70(1) P71(1) P72 P73 Function PS1 Register TxD2 output RxD2 input CLK2 input CLK2 output __________ Setting PSL1 Register PSL1_0=0 PSL1_2=0 PSL1_3=0 PSC Register PSC_0=0 PSC_2=0 PSC_3=0 PD7 Register PD7_1=0 PD7_2=0 PD7_3=0 PS1_0=1 PS1_1=0 PS1_2=0 PS1_2=1 PS1_3=0 PS1_3=1 CTS2 input __________ RTS2 output NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 17.5 Pin Settings (3) Port P90 P91 P92 P93 P94 P95 P96 P97 Function PS3 Register(1) CLK3 input CLK3 output RxD3 input TxD3 output __________ Setting PSL3 Register PSL3_2=0 PSL3_3=0 PSL3_4=0 PSL3_5=0 PD9 Register(1) PD9_0=0 PD9_1=0 PD9_3=0 PD9_4=0 PD9_5=0 PD9_7=0 PS3_0=0 PS3_0=1 PS3_1=0 PS3_2=1 PS3_3=0 PS3_3=1 PS3_4=0 PS3_4=1 PS3_5=0 PS3_5=1 PS3_6=1 PS3_7=0 CTS3 input __________ RTS3 output __________ CTS4 input __________ RTS4 output CLK4 input CLK4 output TxD4 output RxD4 input NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 205 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Clock Synchronous Serial I/O) (1) Transmit Timing (Internal clock selected) Tc Transfer Clock "1" "0" "1" "0" Data is transferred from the UiTB register to the UARTi transmit register "H" Data is set in the UiTB register TE bit in UiC1 register TI bit in UiC1 register CTSi "L" TCLK Pulse stops because an "H" signal is applied to CTSi Pulse stops because the TE bit is set to "0" CLKi TxDi TXEPT bit in UiC0 register IR bit in SiTIC register "1" "0" "1" "0" D0 D 1 D2 D3 D4 D5 D6 D7 D0 D 1 D2 D3 D4 D5 D 6 D7 D 0 D1 D2 D 3 D 4 D 5 D6 D7 Set to "0" by an interrupt request acknowledgement or by program The above applies to the following settings: TC=TCLK=2(m+1)/fj • The CKDIR bit in the UiMR register is set to "0" (internal clock selected) fj : Count source frequency set in the UiBRG register (f1, f8, f2n(1)) • The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled) m : Setting value of the UiBRG register The CRS bit is set to "0" (CTS function selected) i = 0 to 4 • The CKPOL bit the in UiC0 register is set to "0" (data transmitted on the NOTES: falling edge of the transfer clock) 1. The CNT3 to CNT0 bits in the TCSPR register select no division ( • The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register) n=0) or divide-by-2n (n=1 to 15). (2) Receive Timing (External clock selected) RE bit in UiC1 register TE bit in UiC1 register TI bit in UiC1 register RTSi "1" "0" "1" "0" "1" "0" Data is transferred from the UiTB register to the UARTi transmit register "H" "L" An "L" signal is applied when the UiRB register is read Dummy data is set in the UiTB register 1 / fEXT Received data is taken in CLKi RxDi RI bit in UiC1 register IR bit in SiRIC register "1" "0" "1" "0" D0 D 1 D2 D3 D4 D 5 D6 D7 Date is transferred from the UARTi receive register to the UiRB register D 0 D1 D2 D3 D 4 D 5 D6 D7 D0 D1 D2 D 3 D4 D 5 D6 Read by the UiRB register OER bit in UiRB register Set to "0" by an interrupt request acknowledgement or by program "1" "0" The above applies to the following settings: • The CKDIR bit in the UiMR register is set to "1" (external clock selected) • The CRD bit in the UiC0 register is set to "0" (RTS/CTS function enabled) The CRS bit is set to "1" (RTS function selected) • The CKPOL bit in the UiC0 register is set to "0" (Data is received on the rising edge of the transfer clock) fEXT: External clock frequency i=0 to 4 Meet the following conditions while an "H" signal is applied to the CLKi pin before receiving data: • Set the TE bit in the UiC1 register to "1" (transmit enable) • Set the RE bit in the UiC1 register to "1" (receive enable) • Write dummy data to the UiTB register Figure 17.10 Transmit and Receive Operation Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 206 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Clock Synchronous Serial I/O) 17.1.1 Selecting CLK Polarity Selecting As shown in Figure 17.11, the CKPOL bit in the UiC0 register (i=0 to 4) determines the polarity of the transfer clock. (1) When the CKPOL bit in the UiC0 register (i=0 to 4) is set to "0" (Data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 NOTES: 1. The CLKi pin is held high ("H") when no data is transferred. 2. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). (2) When the CKPOL bit in the UiC0 register is set to "1" (Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 NOTES: 3. The CLKi pin is held low ("L") when no data is transferred. 4. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). Figure 17.11 Transfer Clock Polarity 17.1.2 Selecting LSB First or MSB First As shown in Figure 17.12, the UFORM bit in the UiC0 register (i=0 to 4) determines a data transfer format. (1) When the UFORM bit in the UiC0 register (i=0 to 4) is set to "0" (LSB first) CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). (2) When the UFORM bit in the UiC0 register is set to "1" (MSB first) CLKi TXDi R XD i D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 NOTES: 2. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (not inversed). Figure 17.12 Transfer Format Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 207 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Clock Synchronous Serial I/O) 17.1.3 Continuous Receive Mode When the UiRRM bit in the UiC1 register (i=0 to 4) is set to "1" (continuous receive mode), the TI bit is set to "0" (data in the UiTB register) by reading the UiRB register. When the UiRRM bit is set to "1", do not set dummy data in the UiTB register by program. 17.1.4 Serial Data Logic Inverse When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB register. Figure 17.13 shows a switching example of the serial data logic. (1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (not inversed) Transfer clock TxDi "H" "L" "H" (no inverse) "L" D0 D1 D2 D3 D4 D5 D6 D7 (2) When the UiLCH bit in the UiC1 register is set to "1" (inverse) Transfer clock TxDi "H" "L" "H" (inverse) "L" D0 D1 D2 D3 D4 D5 D6 D7 NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge) and the UFORM bit in the UiC register is set to "0" (LSB first). Figure 17.13 Serial Data Logic Inverse Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 208 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (UART) 17.2 Clock Asynchronous Serial I/O (UART) Mode In UART mode, data is transmitted and received after setting a desired bit rate and data transfer format. Table 17.6 lists specifications of UART mode. Table 17.6 UART Mode Specifications Item Transfer Data Format Specification • Character bit (transfer data) : selected from 7 bits, 8 bits, or 9 bits long • Start bit: 1 bit long • Parity bit: selected from odd, even, or none Transfer Clock • Stop bit: selected from 1 bit or 2 bits long • The CKDIR bit in the UiMR register is set to "0" (internal clock selected): fj/16(m+1) fj = f1, f8, f2n(1) m: setting value of the UiBRG register , 0016 to FF16 • The CKDIR bit is set to "1" (external clock selected): Transmit/Receive Control Transmit Start Condition fEXT/16(m+1) fEXT: clock applied to the CLKi pin _______ _______ _______ _______ Select from CTS function, RTS function or CTS/RTS function disabled To start transmitting, the following requirements must be met: - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) _______ _______ - Apply a low-velel ("L") signal to the CTSi pin when the CTS function is selected Receive Start Condition To start receiving, the following requirements must be met: - Set the RE bit in the UiC1 register to "1" (receive enable) - The start bit is detected While transmitting, the following condition can be selected: - The UiIRS bit in the UiC1 register is set to "0" (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit register (transfer started) - The UiIRS bit is set to "1" (transmission completed): when data transmission from the UARTi transfer register is completed While receiving Interrupt Request Generation Timing Error Detect when data is transferred from the UARTi receive register to the UiRB register (reception completed) • Overrun error(2) This error occurs when the bit before the last stop bit of the next received data is read prior to reading the UiRB register (the first stop bit when selecting 2 stop bits) • Framing error This error occurs when the number of stop bits set is not detected • Parity error When parity is enabled, this error occurs when the number of "1" in parity and character bits does not match the number of "1" set • Error sum flag Selectable Function This flag is set to "1" when any of an overrun, framing or parity errors occur • LSB first or MSB first Data is transmitted or received in either bit 0 or in bit 7 •Serial data logic inverse Logic values of data to be transmitted and received data are inversed. The start bit and stop bit are not inversed •TxD and RxD I/O polarity Inverse TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register remains unchanged as "1" (interrupt requested). Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 209 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (UART) Table 17.7 lists register settings. Tables 17.8 to 17.10 list pin settings. When UARTi (i=0 to 4) operating mode is selected, the TxDi pin outputs a high-level ("H") signal before transfer is started (the TxDi pin is in a high-impedance state when the N-channel open drain output is selected). Figure 17.14 shows an example of a transmit operation in UART mode. Figure 17.15 shows an example of a receive operation in UART mode. Table 17.7 Register Settings in UART Mode Register UiTB UiRB 8 to 0 8 to 0 OER, FER, PER, SUM UiBRG UiMR 7 to 0 SMD2 to SMD0 Set bit rate Set to "1002" when transfer data is 7 bits long Set to "1012" when transfer data is 8 bits long Set to "1102" when transfer data is 9 bits long CKDIR STPS PRY, PRYE IOPOL UiC0 CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM UiLCH UiERE UiSMR UiSMR2 UiSMR3 UiSMR4 NOTES: 1. Use bits 0 to 6 when transfer data is 7 bits long, bits 0 to 7 when 8 bits long, bits 0 to 8 when 9 bits long. 7 to 0 7 to 0 7 to 0 7 to 0 Select the internal clock or external clock Select stop bit length Select parity enable or disable, odd or even Select TxD and RxD I/O polarity Select count source for the UiBRG register _______ _______ Bit Set transmit data(1) Received data can be read(1) Error flags Function Select either CTS or RTS when using either Transfer register empty flag ________ _______ Enables or disables the CTS or RTS function Select output format of the TxDi pin Set to "0" Select the LSB first or MSB first when a transfer data is 8 bits long Set to "0" when transfer data is 7 bits or 9 bits long Set to "1" to enable data transmission Transfer buffer empty flag Set to "1" to enable data reception Reception complete flag Select what causes the UARTi transmit interrupt to be generated Set to "0" Select whether data logic is inversed or not inversed when a transfer data is 7 bits or 8 bits long. Set to "0" when transfer data is 9 bits long Set to either "0" or "1" Set to "0016" Set to "0016" Set to "0016" Set to "0016" Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 210 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (UART) Table 17.8 Pin Settings in UART Mode (1) Port P60 P61 P62 P63 P64 P65 P66 P67 Function PS0 Register __________ Setting PSL0 Register – – – – – – PSL0_4=0 – – – PD6 Register PD6_0=0 – PD6_1=0 PD6_2=0 – PD6_4=0 – PD6_5=0 PD6_6=0 – PS0_0=0 PS0_0=1 PS0_1=0 PS0_2=0 PS0_3=1 PS0_4=0 PS0_4=1 PS0_5=0 PS0_6=0 PS0_7=1 CTS0 input __________ RTS0 output CLK0 input RxD0 input TxD0 output __________ CTS1 input __________ RTS1 output CLK1 input RxD1 input TxD1 output Table 17.9 Pin Settings (2) Port P70(1) P71(1) P72 P73 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Function PS1 Register TxD2 output RxD2 input CLK2 input __________ Setting PSL1 Register PSL1_0=0 – – – PSL1_3=0 PSC Register PSC_0=0 – – – PSC_3=0 PD7 Register – PD7_1=0 PD7_2=0 PD7_3=0 – PS1_0=1 PS1_1=0 PS1_2=0 PS1_3=0 PS1_3=1 CTS2 input __________ RTS2 output Table 17.10 Pin Settings (3) Port P90 P91 P92 P93 P94 P95 P96 P97 NOTES: 1. Set the PD9 and PS3 registers set immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Function PS3 CLK3 input RxD3 input TxD3 output __________ Setting Register(1) PSL3 Register – – PSL3_2=0 PSL3_3=0 – PSL3_4=0 – PSL3_5=0 – – PD9 Register(1) PD9_0=0 PD9_1=0 – PD9_3=0 – PD9_4=0 – PD9_5=0 – PD9_7=0 PS3_0=0 PS3_1=0 PS3_2=1 PS3_3=0 PS3_3=1 PS3_4=0 PS3_4=1 PS3_5=0 PS3_6=1 PS3_7=0 CTS3 input __________ RTS3 output __________ CTS4 input __________ RTS4 output CLK4 input TxD4 output RxD4 input Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 211 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (UART) (1) 8-bit Data Transmission Timing (with a parity and 1 stop bit) The transfer clock stops momentarily, because an "H" signal is applied to the CTS pin, when the stop bit is verified. The transfer clock resumes running as soon as an "L" signal is applied to the CTS pin. Tc Transfer Clock TE bit in UiC1 register TI bit in UiC1 register "1" "0" "1" "0" Data is set in the UiTB register Data is transferred from the UiTB register to the UARTi transmit register "H" CTSi "L" Start bit TxDi TXEPT bit in UiC0 "1" register "0" "1" "0" Parity bit P SP Stop bit Pulse stops because the TE bit is set to "0" P SP ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 ST D0 D1 D2 D3 D4 D5 D6 D7 IR bit in SiTIC register Set to "0" by an interrupt request acknowledgement or by program i=0 to 4 The above timing applies to the following settings : • The PRYE bit in the UiMR register is set to "1" (parity enabled) • The STPS bit in the UiMR register is set to "0" (1 stop bit) • The CRD bit in the UiC0 register is set to "0" and the CRS bit is set to "0" (CTS function selected) • The UilRS bit in the UiC1 register is set to "1" (transmission completed) Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT fj : count source frequency set in the UiBRG register (f1, f8, f2n(1)) fEXT : count source frequency set in the UiBRG register (external clock) m : setting value of the UiBRG register NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). (2) 9-bit Data Transmit Timing (with no parity and 2 stop bits) Tc Transfer Clock TE bit in UiC1 register TI bit in UiC1 register "1" "0" "1" "0" Data is set in the UiTB register Start bit TxDi TXEPT bit in UiC0 register "0" IR bit in SiTIC register "1" "0" "1" Data is transferred from the UiTB register to the UARTi transmit register Stop Stop bit bit ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP Set to "0" by an interrupt request acknowledgement or by program i=0 to 4 The above timing applies to the following settings : • The PRYE bit in the UiMR register is set to "0" (parity disabled) • The STPS bit in the UiMR register is set to "1" (2 stop bits) • The CRD bit in the UiC0 register is set to "1" (CTS function disabled) • The UilRS bit in the UiC1 register is set to "0" (no data in the transmit buffer) Tc = 16 (m + 1) / fj or 16 (m + 1) / fEXT fj : count source frequency set in the UiBRG register (f1, f8, f2n(1)) fEXT : count source frequency set in the UiBRG register (external clock) m : setting value of the UiBRG register NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Figure 17.14 Transmit Operation Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 212 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (UART) 8-bit Data Reception Timing (with no parity and 1 stop bit) Output from UiBRG RE bit in UiC1 register RxDi "1" "0" Start bit Verify if an "L" signal is applied Transfer Clock RI bit in UiC1 register RTSi IR bit in SiRIC register Data is transferred from the UARTi receive Start receiving when the transfer clock is "1" generated on the falling edge of the start bit register to the UiRB register "0" "H" "L" "1" "0" Set to "0" by an interrupt request acknowledgement or by program i=0 to 4 NOTES: 1. The above applies when the PRYE bit in the UiMR register is set to "0" (parity disabled), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the CRS bit in the UiC0 register is set to "1" (RTS function selected). Stop bit D0 D1 D7 Capture a received data Change to "L" by reading the UiRB register Figure 17.15 Receive Operation 17.2.1 Transfer Speed In UART mode, transfer speed is clock frequency which is divided by a setting value of the UiBRG (i=0 to 4) register and again divided by 16. Table 17.11 lists an example of transfer speed setting. Table 17.11 Transfer Speed Bit Rate (bps) Count Source of UiBRG f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 Peripheral Function Clock: 16MHz Setting Value of UiBRG: n 103 (67h) 51 (33h) 25 (19h) 103 (67h) 68 (44h) 51 (33h) 34 (22h) 31 (1Fh) 25 (19h) 19 (13h) Actual Bit Rate (bps) 1202 2404 4808 9615 14493 19231 28571 31250 38462 50000 Peripheral Function Clock: 24MHz Setting Value of UiBRG: n 155 (96h) 77 (46h) 38 (26h) 155 (96h) 103 (67h) 77 (46h) 51 (33h) 47 (2Fh) 38 (26h) 28 (1Ch) Actual Bit Rate (bps) 1202 2404 4808 9615 14423 19231 28846 31250 38462 51724 Peripheral Function Clock: 32MHz Setting Value of UiBRG: n 207 (CFh) 103 (67h) 51 (33h) 207 (CFh) 138 (8Ah) 103 (67h) 68 (44h) 63 (3Fh) 51 (33h) 38 (26h) Actual Bit Rate (bps) 1202 2404 4808 9615 14388 19231 28986 31250 38462 51282 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200 Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 213 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (UART) 17.2.2 Selecting LSB First or MSB First As shown in Figure 17.16, the UFORM bit in the UiC0 register (i=0 to 4) determines data transfer format. This function is available for 8-bit transfer data. (1) When the UFORM Bit in the UiC0 Register (i=0 to 4) is set to "0" (LSB first) CLKi TxDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP RxDi ST D0 D1 D2 D3 D4 D5 D6 D7 P SP (2) When the UFORM Bit in the UiC0 Register is set to "1" (MSB first) CLKi TxDi ST D7 D6 D5 D4 D3 D2 D1 D0 P SP RxDi ST D7 D6 D5 D4 D3 D2 D1 D0 P SP ST : Start bit P : Parity bit SP : Stop bit NOTES: 1. The above applies when the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and received on the rising edge) and the UiLCH bit in the UiC1 register is set to "0" (no inverse). Figure 17.16 Transfer Format 17.2.3 Serial Data Logic Inverse When the UiLCH bit (i=0 to 4) in the UiC1 register is set to "1" (inverse), data logic written in the UiTB register is inversed when transmitted. The inversed receive data logic can be read by reading the UiRB register. Figure 17.17 shows a switching example of the serial data logic. (1) When the UiLCH bit in the UiC1 register (i=0 to 4) is set to "0" (no inverse) Transfer Clock TxDi (no inverse) "H" "L" "H" "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP (2) When the UiLCH bit in the UiC1 register is set to "1" (inverse) Transfer Clock TxDi "H" "L" "H" (inverse) "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP NOTES: 1. The above applies to when the UFORM bit in the UiC0 register is set to "0" (LSB first), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled). Figure 17.17 Serial Data Logic Inverse Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 214 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (UART) 17.2.4 TxD and RxD I/O Polarity Inverse TxD pin output and RxD pin input are inversed. All I/O data level, including the start bit, stop bit and parity bit, are inversed. Figure 17.18 shows TxD and RxD I/O polarity inverse. (1) When the IOPOL bit in the UiMR register (i=0 to 4) is set to "0" (no inverse) Transfer Clock TxDi (no inverse) "H" "L" "H" "L" "H" "L" ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP RxDi (no inverse) (2) When the IOPOL bit in the UiMR register is set to "1" ( inverse) Transfer Clock "H" "L" TxDi "H" (inverse) "L" RxDi (inverse) "H" "L" ST ST D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 P P SP SP ST : Start bit P : Even parity SP : Stop bit NOTES: 1. The above applies when the UFORM bit in the UiC0 register is set to "0" (LSB first), the STPS bit in the UiMR bit is set to "0" (1 stop bit) and the PRYE bit is set to "1" (parity enabled). Figure 17.18 TxD and RxD I/O Polarity Inverse Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 215 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) 17.3 Special Mode 1 (I2C Mode) I2C mode is a mode to communicate with external devices with a simplified I2C. Table 17.12 lists specifications of I2C mode. Table 17.13 lists register settings, Table 17.14 lists each function. Figure 17.19 shows a block diagram of I2C mode. Figure 17.20 shows timings for transfer to the UiRB register and interrupts. Tables 17.15 to 17.17 list pin settings. As shown in Table 17.12, I2C mode is entered when the SMD2 to SMD0 bits in the UiMR register is set to "0102" and the IICM bit in the UiSMR register is set to "1". Output signal from the SDAi pin changes after the SCLi pin level becomes low ("L") and stabilizes due to a SDAi transmit output via the delay circuit. Table 17.12 I2C Mode Specifications Item Interrupt Specifications Start condition detect, stop condition detect, no acknowledgment detect, acknowledgment detect Selectable Function • Arbitration lost The update timing of the ABT bit in the UiRB register can be selected. Refer to 17.3.3 Arbitration • SDAi digital delay Selected from no digital delay or 2 to 8 cycle delay of the count source of the UiBRG register. Refer to 17.3.5 SDA Output • Clock phase setting Selected from clock delay or no clock delay. Refer to 17.3.4 Transfer clock Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 216 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) SDAi (Note1) Timer I/O UARTi IICM 1 Delay Circuit 0 SDHI D Q T To DMA IICM=0 or IICM2=1 Transmit Register UARTi IICM=1 and IICM2=0 UARTi Transmission NACK Interrupt Request ALS Arbitration 1 0 IICM Receive Register UARTi IICM=0 or IICM2=1 To DMA Noise Filter Detects Start Condition S R Q IICM=1 and IICM2=0 UARTi Reception ACK Interrupt Request DMA Request Bus busy NACK DQ T DQ T Detects Stop Condition Falling edge detect LSYN bit SCLi (Note 1) ACK I/O UARTi IICM=1 1 IICM 0 R Data Register Internal Clock 9th Pulse 1 0 IICM Bus Conflict Start Condition Detect Stop Condition Detect Interrupt Request Noise Filter Noise Filter Bus Conflict SWC2 CLK Detect Control UARTi External Clock QR S Falling Edge of 9th Pulse SWC Port reading (Note 1) UARTi IICM=0 I/O Timer * When the IICM bit is set to "1", port pin can be read regardless of the direction register being set to "1". CLKi i=0 to 4 NOTES: 1. Set the PSj (j=0,1,3), PSLj or PSC register to determine. IICM : Bit in the UiSMR register IICM2 : Bit in the UiSMR2 register Figure 17.19 I2C Mode Block Diagram Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 217 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) Table 17.13 Register Settings in I2C Mode Register UiTB UiRB Bit Master 7 to 0 7 to 0 8 ABT OER 7 to 0 SMD2 to SMD0 CKDIR IOPOL CLK1, CLK0 CRS TXEPT CRD, NCH CKPOL UFORM TE TI RE RI UiRRM, UiLCH, UiERE IICM ABC BBS 7 to 3 IICM2 CSC SWC Set transmit data Received data can be read ACK or NACK bit can be read Arbitration lost detect flag Overrun error flag Set bit rate Set to "0102" Set to "0" Set to "0" Select count source of the UiBRG register Disabled because the CRD bit is set to "1" Transfer register empty flag Set to "1" Set to "0" Set to "1" Set to "1" to enable data transmission Transfer buffer empty flag Set to "1" to enable data reception Reception complete flag Set to "0" Function Slave Disabled Disabled Set to "1" Disabled UiBRG UiMR UiC0 UiC1 UiSMR UiSMR2 UiSMR3 UiSMR4 Set to "1" Select an arbitration lost detect timing Disabled Bus busy flag Set to "000002" See Table 17.14 Set to "1" to enable clock synchronization Set to "0" Set to "1" to fix an "L" signal output from SCLi on the falling edge of the ninth bit of the transfer clock ALS Set to "1" to terminate SDAi output when Not used. Set to "0" detecting the arbitration lost STC Not used. Set to "0" Set to "1" to reset UARTi by detecting the start condition SWC2 Set to "1" for an "L" signal output from SCL forcibly SDHI Set to "1" to disable SDA output SU1HIM Set to "0" SSE Set to "0" CKPH See Table 17.14 DINC, NODC, ERR Set to "0" DL2 to DL0 Set digital delay value STAREQ Set to "1" when generating a start condition Not used. Set to "0" RSTAREQ Set to "1" when generating a restart condition STPREQ Set to "1" when generating a stop condition STSPSEL ACKD ACKC SCLHI SWC9 Set to "1" when using a condition generating function Select ACK or NACK Set to "1" for ACK data output Set to "1" to enable SCL output stop when Not used. Set to "0" detecting stop condition Not used. Set to "0" Set to "1" to fix an "L" signal output from SCLi on the falling edge of the ninth bit of the transfer clock IFSR i=0 to 4 IFSR6, IFSR7 Set to "1" Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 218 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) Table 17.14 I2C Mode Functions I2 C Mode (SMD2 to SMD0=0102, IICM=1) Function Clock Synchronous Serial I/O Mode (SMD2 to SMD0=0012, IICM=0) IICM2=0 (NACK/ACK interrupt) CKPH=0 (No clock delay) CKPH=1 (Clock delay) IICM2=1 (UART transmit / UART receive interrupt) CKPH=0 (No clock delay) CKPH=1 (Clock delay) Interrupt Numbers 39 to 41 Generated( 1 ) (See Figure 17.20) Interrupt Number 17, 19, 33, 35 and 37 Generated( 1 ) (See Figure 17.20) Interrupt Numbers 18, 20, 34, 36 and 38 Generated( 1 ) (See Figure 17.20) Data Transfer Timing from the UART Receive Shift Register to the UiRB Register UARTi Transmit Output Delay P63, P67, P70, P92, P96 Pin Functions P62, P66, P71, P91, P97 Pin Functions P61, P65, P72, P90, P95 Pin Functions Noise Filter Width Reading RxDi and SCLi Pin Levels Default Value of TxDi, SDAi Output SCLi Default and End Value DMA Generated (See Figure 17.20) UARTi Transmission Transmission started or completed (selected by the UiIRS register) UARTi Reception Receiving at 8th bit CKPOL=0(rising edge) CKPOL=1(falling edge) CKPOL=0(rising edge) CKPOL=1(falling edge) No delay TxDi output RxDi input Select CLKi input or output 15ns Can be read if port direction bit is set to "0" CKPOL=0 (H) CKPOL=1 (L) – UARTi reception Start condition or stop condition detect (See Table 17.18) UARTi Transmission Rising edge of 9th bit of SCLi No Acknowledgement Detection (NACK) Rising edge of 9th bit of SCLi Acknowledgement Detection (ACK) Rising edge of 9th bit of SCLi UARTi Transmission Next falling edge after the 9th bit of SCLi UARTi Reception Falling edge of 9th bit of SCLi Rising edge of 9th bit of SCLi Falling edge of 9th bit of SCLi Falling edge and rising edge of 9th bit of SCLi Delay SDAi input and output SCLi input and output – (Not used in I2 C mode) 200ns Can be read regardless of the port direction bit Values set in the port register before entering I2 C mode( 2 ) H L H L Acknowledgement detection (ACK) UARTi Reception Falling edge of 9th bit of SCLi 1st to 7th bits of the received data are stored into bits 6 to 0 in the UiRB register. 8th bit is stored into bit 8 in the UiRB register. 1st to 8th bits are stored into bits 7 to 0 in the UiRB register(3 ) Bits 6 to 0 in the UiRB registerts( 4 ) are read as bit 7 to 1. Bit 8 in the UiRB register is read as bit 0 Store Received Data 1st to 8th bits of the received data are stored into bits 7 to 0 in the UiRB register 1st to 8th bits of the received data are stored into bits 7 to 0 in the UiRB register Reading Received Data The UiRB register status is read i=0 to 4 NOTES: 1. Follow the procedures below to change what causes an interrupt to be generated. (a) Disable interrupt of corresponding interrupt number. (b) Change what causes an interrupt to be generated. (c) Set the IR bit of a corresponding interrupt number to "0" (no interrupt requested). (d) Set the ILVL2 to ILVL0 bits of a corresponding interrupt number. 2. Set default value of the SDAi output when the SMD2 to SMD0 bits in the UiMR register are set to "0002" (serial I/O disabled). 3. Second data transfer to the UiRB register (on the rising edge of the ninth bit of SCLi). 4. First data transfer to the UiRB register (on the falling edge of the ninth bit of SCLi). Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 219 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) (1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) ACK interrupt (DMA request) or NACK interrupt b15 b9 ••• b8 b7 b0 Data is transferred to the UiRB register D8 D7 D 6 D 5 D4 D3 D2 D1 D 0 Contents of the UiRB register (2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay) 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) ACK interrupt (DMA request) or NACK interrupt b15 b9 ••• b8 b7 b0 Data is transferred to the UiRB register D8 D7 D6 D 5 D 4 D3 D2 D1 D0 Contents of the UiRB register (3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0" 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) Transmit interrupt b15 b9 ••• b8 b7 b0 Receive interrupt (DMA request) Data is transferred to the UiRB register D0 D7 D6 D5 D4 D 3 D 2 D 1 Contents of the UiRB register (4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1" 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit SCLi SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK or NACK) Transmit interrupt Receive interrupt (DMA request) Data is transferred to the UiRB register b15 ••• b9 b8 b7 b0 Data is transferred to the UiRB register b15 ••• b9 b8 b7 b0 D0 D7 D6 D 5 D 4 D3 D2 D1 D 8 D7 D6 D5 D 4 D 3 D2 D 1 D0 i=0 to 4 IICM2 : Bit in the UiSMR2 register CKPH : Bit in the UiSMR3 regiser Contents of the UiRB register Contents of the UiRB register The above timing applies to the following setting : • The CKDIR bit in the UiMR register is set to "1" (slave) Figure 17.20 SCLi Timing Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 220 of 495 M32C/84 Group (M32C/84, M32C/84T) Table 17.15 Pin Settings in I2C Mode (1) Port P62 P63 P66 P67 Function PS0 Register SCL0 output SCL0 input SDA0 output SDA0 input SCL1 output SCL1 input SDA1 output SDA1 input PS0_2=1 PS0_2=0 PS0_3=1 PS0_3=0 PS0_6=1 PS0_6=0 PS0_7=1 PS0_7=0 Setting PSL0 Register PSL0_2=0 PSL0_6=0 - 17. Serial I/O (Special Function) PD6 Register PD6_2=0 PD6_3=0 PD6_6=0 PD6_7=0 Table 17.16 Pin Settings (2) Setting Port Function PS1 Register SDA2 output P70( 1 ) SDA2 input SCL2 output P71( 1 ) SCL2 input PS1_1=0 – – PD7_1=0 PS1_0=0 PS1_1=1 – PSL1_1=1 – PSC_1=0 PD7_0=0 – PS1_0=1 PSL1 Register PSC Register PD7 Register PSL1_0=0 PSC_0=0 – NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 17.17 Pin Settings (3) Port P91 P92 P96 P97 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Function PS3 SCL3 output SCL3 input SDA3 output SDA3 input SDA4 output SDA4 input SCL4 output SCL4 input Register(1) PS3_1=1 PS3_1=0 PS3_2=1 PS3_2=0 PS3_6=1 PS3_6=0 PS3_7=1 PS3_7=0 PSL3_1=0 PSL3_2=0 PSL3_7=0 Setting PSL3 Register PSC3 Register PSC3_6=0 PD9 Register(1) PD9_1=0 PD9_2=0 PD9_6=0 PD9_7=0 Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 221 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) 17.3.1 Detecting Start Condition and Stop Condition The microcomputer detects either a start condition or stop condition. The start condition detect interrupt is generated when the SCLi (i=0 to 4) pin level is held high ("H") and the SDAi pin level changes "H" to low ("L"). The stop condition detect interrupt is generated when the SCLi pin level is held "H" and the SDAi pin level changes "L" to "H". The start condition detect interrupt shares interrupt control registers and vectors with the stop condition detect interrupt. The BBS bit in the UiSMR register determines which interrupt is requested. 3 to 6 cycles < setup time(1) 3 to 6 cycles < hold time(1) Setup time SCLi SDAi (Start condition) Hold time SDAi (Stop condition) i=0 to 4 NOTES: 1. These cycles are main clock generation frequency cycles (XIN). Figure 17.21 Start Condition or Stop Condition Detecting 17.3.2 Start Condition or Stop Condition Output The start condition is generated when the STAREQ bit in the UiSMR4 register (i=0 to 4) is set to "1" (start). The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to "1" (start). The stop condition is generated the STPREQ bit in the UiSMR4 is set to "1" (start). The start condition is output when the STAREQ bit is set to "1" and the STSPSEL bit in the UiSMR4 register is set to "1" (start or stop condition generating circuit selected). The restart condition output is provided when the RSTAREQ bit and STSPSEL bit are set to "1". The stop condition output is provided when the STPREQ bit and the STSPSEL bit are set to "1". When the start condition, stop condition or restart condition is output, do not generate an interrupt between the instruction to set the STAREQ bit, STPREQ bit or RSTAREQ bit to "1" and the instruction to set the STSPSEL bit to "1". When the start condition is output, set the STAREQ bit to "1" before the STSPSEL bit is set to "1". Table 17.18 lists function of the STSPSEL bit. Figure 17.22 shows functions of the STSPSEL bit. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 222 of 495 M32C/84 Group (M32C/84, M32C/84T) Table 17.18 STSPSEL Bit Function Function Start condition and stop condition output STSPSEL = 0 Program with ports determines how the start condition or stop condition output is provided The start condition and stop condition are detected 17. Serial I/O (Special Function) STSPSEL = 1 The STAREQ bit, RSTAREQ bit and STPREQ bit determine how the start condition or stop condition output is provided Start condition and stop condition generation are completed Timing to generate start condition and stop condition interrupt requests (1) In slave mode, The CKDIR bit is set to "1" (external clock) The STSPSEL bit is set to "0" (no start condition and stop condition output) SCLi SDAi Start condition detect interrupt Stop condition detect interrupt (1) In master mode, The CKDIR bit is set to "0" (internal clock) The STSPSEL bit is set to "1" (start condition and stop condition output) Setting value of the STSPEL bit SCLi SDAi STPREQ bit is set to "1" (start) 0 1 0 1 0 Start condition detect interrupt STPREQ bit is set to "1" (start) Stop condition detect interrupt i=0 to 4 Figure 17.22 STSPSEL Bit Function Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 223 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) 17.3.3 Arbitration The ABC bit in the UiSMR register (i=0 to 4) determines an update timing for the ABT bit in the UiRB register. On the rising edge of the SCLi pin, the microcomputer determines whether a transmit data matches data input to the SDAi pin. When the ABC bit is set to "0" (update per bit), the ABT bit is set to "1" (detected-arbitration is lost) as soon as a data discrepancy is detected. The ABT bit is set to "0" (not detected-arbitration is won) if not detected. When the ABC bit is set to "1" (update per byte), the ABT bit is set to "1" on the falling edge of the ninth bit of the transfer clock if any discrepancy is detected. When the ABT bit is updated per byte, set the ABT bit to "0" between an ACK detection in the first byte data and the next byte data to be transferred. When the ALS bit in the UiSMR2 register is set to "1" (SDA output stop enabled), the arbitration lost occurs. As soon as the ABT bit is set to "1", the SDAi pin is placed in a high-impedance state. 17.3.4 Transfer Clock The transfer clock transmits and receives data as is shown in Figure 17.20. The CSC bit in the UiSMR2 register (i=0 to 4) synchronizes an internally generated clock (internal SCLi) with the external clock applied to the SCLi pin. When the CSC bit is set to "1" (clock synchronous enabled) and the internal SCLi is held high ("H"), the internal SCLi become low ("L") if signal applied to the SCLi pin is on the falling edge. Value of the UiBRG register is reloaded to start counting for low level. A counter stops when the SCLi pin is held "L" and then the internal SCLi changes "L" to "H". Counting is resumed when the SCLi pin become "H". The transfer clock of UARTi is equivalent to the AND for signals from the internal SCLi and the SCLi pin. The transfer clock is synchronized between a half cycle before the falling edge of first bit of the internal SCLi and the rising edge of the ninth bit. Select the internal clock as the transfer clock while the CSC bit is set to "1". The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed to be an "L" signal output on the falling edge of the ninth cycle of the transfer clock or not. When the SCLHI bit in the UiSMR4 register is set to "1" (enabled), a SCLi output stops when a stop condition is detected (high-impedance). When the SWC2 bit in the UiSMR2 register is set to "1" (0 output), the SCLi pin focibly outputs an "L" signal while transmitting and receiving. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC2 bit to "0" (transfer clock) and the transfer clock input to and output from the SCLi pin are provided. When the CKPH bit in the UiSMR3 register is set to "1" and the SWC9 bit in the UiSMR4 register is set to "1" (SCL "L" hold enabled), the SCLi pin is fixed to be an "L" signal output on the next falling edge after the ninth bit of the clock. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC9 bit to "0" (SCL "L" hold disabled). 17.3.5 SDA Output Values output set in bits 7 to 0 (D7 to D0) in the UiTB register (i=0 to 4) are provided in descending order from D7. The ninth bit (D8) is ACK or NACK. Set the default value of SDAi transmit output when the IICM bit is set to "1" (I2C mode) and the SMD2 to SMD0 bits in the UiMR register are set to "0002" (serial I/O disabled). The DL2 to DL0 bits in the UiSMR3 register determine no delay in the SDAi output or a delay of 2 to 8 UiBRG register count source cycles. When the SDHI bit in the UiSMR2 register is set to "1" (SDA output disabled), the SDAi pin is forcibly placed in a high-impedance state. Do not set the SDHI bit on the rising edge of the UARTi transfer clock. The ABT bit in the UiRB register may be set to "1" (detected). Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 224 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) 17.3.6 SDA Input When the IICM2 bit in the UiSMR2 register (i=0 to 4) is set to "0", the first eight bits of received data are stored into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK. When the IICM2 bit is set to "1", the first seven bits (D7 to D1) of received data are stored into bits 6 to 0 in the UiRB register. Store the eighth bit (D0) into bit 8 in the UiRB register. If the IICM2 bit is set to "1" and the CKPH bit in the UiSMR3 register is set to "1", the same data as that of when setting the IICM2 bit to "0" can be read. To read the data, read the UiRB register after the rising edge of the ninth bit of the transfer clock. 17.3.7 ACK, NACK When the STSPSEL bit in the UiSMR4 register (i=0 to 4) is set to "0" (serial I/O circuit selected) and the ACKC bit in the UiSMR4 register is set to "1" (ACK data output), the SDAi pin provides the value output set in the ACKD bit in the UiSMR4 register. If the IICM2 bit is set to "0", the NACK interrupt request is generated when the SDAi pin is held high ("H") on the rising edge of the ninth bit of the transfer clock. The ACK interrupt request is generated when the SDAi pin is held low ("L") on the rising edge of the ninth bit of the transfer clock. When ACK is selected to generate a DMA request, the DMA transfer is activated by an ACK detection. 17.3.8 Transmit and Receive Reset When the STC bit in the UiSMR2 register (i=0 to 4) is set to "1" (UARTi initialization enabled) and a start condition is detected, - the transmit shift register is reset and the content of the UiTB register is transferred to the transmit shift register. The first bit starts transmitting when the next clock is input. UARTi output value remains unchanged between when the clock is applied and when the first bit data output is provided. The value remains the same as when start condition was detected. - the receive shift register is reset and the first bit start receiving when the next clock is applied. - the SWC bit is set to "1" (SCL wait output enabled). The SCLi pin becomes "L" on the falling edge of the ninth bit of the transfer clock. If UARTi transmission and reception are started with this function, the TI bit in the UiC1 register remains unchanged. Select the external clock as the transfer clock when using this function. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 225 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) 17.4 Special Mode 2 In special mode 2, serial communication between one or multiple masters and multiple slaves is available. _____ The SSi input pin (i=0 to 4) controls the serial bus communication. Table 17.19 lists specifications of special mode 2. Table 17.20 lists register settings. Tables 17.21 to 17.23 list pin settings. Table 17.19 Special Mode 2 Specifications Item Transfer Data Format Transfer Clock Specification Transfer data : 8 bits long • The CKDIR bit in the UiMR register (i=0 to 4) is set to "0" (internal clock selected): fj/2(m+1) fj = f1, f8, f2n(1) m : setting value of the UiBRG register, 0016 to FF16 • The CKDIR bit to "1" (external clock selected) : input from the CLKi pin ______ Transmit/Receive Control SSi input pin function Transmit Start Condition To start transmitting, the following requirements must be met(2): - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) Receive Start Condition To start receiving, the following requirement must be met(2): - Set the RE bit in the UiC1 register to "1" (receive enable) - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) Interrupt Request • While transmitting, the following conditions can be selected: Generation Timing - The UiIRS bit in the UiC1 register is set to "0" (no data in a transmit buffer) : when data is transferred from the UiTB register to the UARTi transmit register (transmission started) - The UiIRS register is set to "1" (transmission completed): when data transmission from UARTi transfer register is completed • While receiving When data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detection • Overrun error(3) This error occurs when the seventh bit of the next received data is read before reading the UiRB register • Fault error ______ In master mode, the fault error occurs an "L" signal is applied to the SSi pin Selectable Function • CLK polarity Select from the rising edge or falling edge of the transfer clock when transferred data is output and input are provided • LSB first or MSB first Data is transmitted or received in either bit 0 or in bit 7 • Continuous receive mode Reception is enabled simultaneously by reading the UiRB register • Serial data logic inverse This function inverses transmitted or received data logically • TxD and RxD I/O polarity inverse TxD pin output and RxD pin input are inversed. All I/O data levels are also inversed • Clock phase Select from one of 4 combinations of transfer data polarity and phases _____ • SSi input pin function Output pin is placed in a high-impedance state to avoid data conflict between master and other masters or slaves NOTES: 1. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 2. To start transmission/reception when selecting the external clock, these conditions must be met after the CKPOL bit in the UiC0 register is set to "0" (data is transmitted on the falling edge of the transfer clock and data is received on the rising edge) and the CLKi pin is held high ("H"), or when the CKPOL bit is set to "1" (Data is transmitted on the rising edge of the transfer clock and data is received on the falling edge) and the CLKi pin is held low ("L"). 3. If an overrun error occurs, the UiRB register is in an indeterminate state. The IR bit in the SiRIC register does not change to "1" (interrupt requested). Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 226 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) Table 17.20 Register Settings in Special Mode 2 Register UiTB UiRB UiBRG UiMR 7 to 0 7 to 0 OER 7 to 0 SMD2 to SMD0 CKDIR IOPOL UiC0 CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM UiSMR UiSMR2 UiSMR3 7 to 0 7 to 0 SSE CKPH DINC NODC ERR 7 to 5 UiSMR4 i=0 to 4 7 to 0 Bit Set transmit data Received data can be read Overrun error flag Set bit rate Set to "0012" Set to "0" in master mode or "1" in slave mode Set to "0" Select count source for the UiBRG register Disabled because the CRD bit is set to "1" Transfer register empty flag Set to "1" Select the output format of the TxDi pin Clock phase can be set by the combination of the CKPOL bit and the CKPH bit in the UiSMR3 register Select either LSB first or MSB first Set to "1" to enable data transmission and reception Transfer buffer empty flag Set to "1" to enable data reception Reception complete flag Select what causes the UARTi transmit interrupt to be generated Set to "1" to enable continuous receive mode Set to "0016" Set to "0016" Set to "1" Clock phase can be set by the combination of the CKPH bit and the CKPOL bit in the UiC0 register Set to "0" in master mode or "1" in slave mode Set to "0" Fault error flag Set to "0002" Set to "0016" Function UiLCH, SCLKSTPB Set to "0" Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 227 of 495 M32C/84 Group (M32C/84, M32C/84T) Table 17.21 Pin Settings in Special Mode 2 (1) Port ______ 17. Serial I/O (Special Function) Function SS0 input CLK0 input (slave) CLK0 output (master) RxD0 input (master) STxD0 output (slave) TxD0 output (master) SRxD0 input (slave) ______ SS1 input CLK1 input (slave) CLK1 output (master) RxD1 input (master) STxD1 output (slave) TxD1 output (master) SRxD1 input (slave) PS0 Register PS0_0=0 PS0_1=0 PS0_1=1 PS0_2=0 PS0_2=1 PS0_3=1 PS0_3=0 PS0_4=0 PS0_5=0 PS0_5=1 PS0_6=0 PS0_6=1 PS0_7=1 PS0_7=0 P60 P61 P62 P63 P64 P65 P66 P67 Setting PSL0 Register – – – – PSL0_2=1 – – – – – – PSL0_6=1 – – PD6 Register PD6_0=0 PD6_1=0 – PD6_2=0 – – PD6_3=0 PD6_4=0 PD6_5=0 – PD6_6=0 – – PD6_7=0 Table 17.22 Pin Settings (2) Port P70(1) P71(1) P72 Function TxD2 output (master) SRxD2 input (slave) RxD2 input (master) STxD2 output (slave) CLK2 input (slave) CLK2 output (master) ______ SS2 input PS1 Register PS1_0=1 PS1_0=0 PS1_1=0 PS1_1=1 PS1_2=0 PS1_2=1 PS1_3=0 Setting PSL1 Register PSC Register PSL1_0=0 PSC_0=0 – – – – PSL1_1=1 PSC_1=0 – – PSL1_2=0 PSC_2=0 – – PD7 Register – PD7_0=0 PD7_1=0 – PD7_2=0 – PD7_3=0 P73 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Table 17.23 Pin Settings (3) Port P90 P91 P92 P93 P94 P95 P96 P97 Function CLK3 input (slave) CLK3 output (master) RxD3 input (master) STxD3 output (slave) TxD3 output (master) SRxD3 input (slave) ______ SS3 input _______ SS4 input CLK4 input (slave) CLK4 output (master) TxD4 output (master) SRxD4 input (slave) RxD4 input (master) STxD4 output (slave) PS3 Register(1) PS3_0=0 PS3_0=1 PS3_1=0 PS3_1=1 PS3_2=1 PS3_2=0 PS3_3=0 PS3_4=0 PS3_5=0 PS3_5=1 PS3_6=1 PS3_6=0 PS3_7=0 PS3_7=1 Setting PSL3 Register – – – PSL3_1=1 PSL3_2=0 – PSL3_3=0 PSL3_4=0 PSL3_5=0 – – PSL3_6=0 – PSL3_7=1 PD9 Register(1) PD9_0=0 – PD9_1=0 – – PD9_2=0 PD9_3=0 PD9_4=0 PD9_5=0 – – PD9_6=0 PD9_7=0 – NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 228 of 495 M32C/84 Group (M32C/84, M32C/84T) ______ 17. Serial I/O (Special Function) 17.4.1 SSi Input Pin Function (i=0 to 4) ____ When the SSE bit in the UiSMR3 register is set to "1" (SS function enabled), the special mode 2 is selected, activating the pin function. The DINC bit in the UiSMR3 register determines which microcomputer performs as master or slave. ______ When multiple microcomputers perform as the masters (multi-master system), the SSi pin setting determines which master microcomputer is active and when. 17.4.1.1 When Setting the DINC Bit to "1" (Slave Mode) _____ When a high-level ("H") signal is applied to the SSi pin, the STxDi and SRxDi pins are placed in a highimpedance state and the transfer clock applied to the CLKi pin is ignored. When a low-level ("L") signal _____ is applied to the SSi input pin, the transfer clock input is valid and serial communication is enabled. 17.4.1.2 When Setting the DINC Bit to "0" (Master Mode) ______ When using the SSi pin functin in master mode, set the UiIRS bit in the UiC1 register to "1" (transmission completed). _____ When an "H" signal is applied to the SSi pin, serial communication is available due to transmission _____ privilege. The master provides the transfer clock output. When an "L" signal is applied to the SSi pin, it indicates that another master is active. The TxDi and CLKi pins are placed in high-impedance states and the ERR bit in the UiSMR3 register is set to "1" (fault error) Use the transmit complete interrupt routine to verify the ERR bit state. To resume the serial communication after the fault error occurs, set the ERR bit to "0" while applying ______ the "H" signal to the SSi pin. The TxDi and CLKi pins become ready for signal outputs. Microcomputer P13 P12 P93(SS3) P90(CLK3) P91(RxD3) P92(TxD3) Master Microcomputer P93(SS3) P90(CLK3) P91(STxD3) P92(SRxD3) Slave Microcomputer P93(SS3) P90(CLK3) P91(STxD3) P92(SRxD3) Slave ____ Figure 17.23 Serial Bus Communication Control with SS Pin Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 229 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) 17.4.2 Clock Phase Setting Function The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four combinations of transfer clock polarity and phases. The transfer clock phase and polarity must be the same between the master and the slave involved in the transfer. 17.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock)) Figure 17.24 shows transmit and receive timing. 17.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock)) _____ When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin _____ is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the transfer clock. Figure 17.25 shows the transmit and receive timing. _____ When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high, the STxDi pin is placed _____ in a high-impedance state. When the SSi pin becomes low, the first data is output. The serial transmission is synchronized with the transfer clock. Figure 17.26 shows the transmit and receive timing. Signal Applied to the SS Pin "H" "L" Clock Output "H" (CKPOL=0, CKPH=0) "L" Clock Output "H" (CKPOL=1, CKPH=0) "L" Clock Output "H" (CKPOL=0, CKPH=1) "L" Clock Output "H" (CKPOL=1, CKPH=1) "L" "H" "L" Data Output Timing D0 D1 D2 D3 D4 D5 D6 D7 Data Input Timing Figure 17.24 Transmit and Receive Timing in Master Mode (Internal Clock) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 230 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) Signal Applied to the SS Pin "H" "L" "H" Clock Input (CKPOL=0, CKPH=0) "L" "H" Clock Input (CKPOL=1, CKPH=0) "L" Data Output Timing(1) "H" "L" Highimpedance D0 D1 D2 D3 D4 D5 D6 D7 Highimpedance Data Input Timing Indeterminate NOTES: 1. P70 and P71 is ports for the N-channel open drain output and must be pulled up externally for data output. Figure 17.25 Transmit and Receive Timing in Slave Mode (External Clock) (CKPH=0) "H" Signal Applied to the SS Pin "L" "H" Clock Input (CKPOL=0, CKPH=0) "L" "H" Clock Input (CKPOL=1, CKPH=1) "L" Data Output Timing(1) "H" "L" Highimpedance D0 D1 D2 D3 D4 D5 D6 D7 Highimpedance Data Input Timing NOTES: 1. P70 and P71 are ports for the N-channel open drain output and must be pulled up externally for data output. Figure 17.26 Transmit and Receive Timing in Slave Mode (External Clock) (CKPH=1) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 231 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) 17.5 Special Mode 3 (GCI Mode) In GCI mode, the external clock is synchronized with the transfer clock used in the clock synchronous serial I/O mode. Table 17.24 lists specifications of GCI mode. Table 17.25 lists registers settings. Tables 17.26 to 17.28 list pin settings. Table17.24 GCI Mode Specifications Item Transfer Data Format Transfer Clock Transfer data : 8 bits long The CKDIR bit in the UiMR register (i=0 to 4) is set to "1" (external clock selected): input from the CLKi pin ________ Specification Clock Synchronization Function Trigger signal input from the CTSi pin Transmit/Receive Start Condition To start data transmission and reception, meet the following conditions and then apply a ________ trigger signal to the CTSi pin: - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the RE bit in the UiC1 register to "1" (receive enable) - Set the TI bit in the UiC1 register to "0" (Data in the UiTB register) Interrupt Request Generation Timing • While transmitting, the following condition can be selected: - The UiIRS bit in the UiC1 register is set to "0" (UiTB register empty): when data is transferred from the UiTB register to the UARTi transmit register (transmission started) - The UiIRS bit is set to "1" (Transmit completed): when a data transmission from the UARTi transfer register is completed • While receiving, when data is transferred from the UARTi receive register to the UiRB register (reception completed) Overrun error(1) This error occurs when the seventh bit of the next received data is read before reading the Error Detection UiRB register. NOTES: 1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested). Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 232 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) Table 17.25 Register Settings in GCI Mode Register UiTB UiRB UiBRG UiMR 7 to 0 7 to 0 OER 7 to 0 SMD2 to SMD0 CKDIR IOPOL UiC0 CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM, UiLCH SCLKSTPB UiSMR UiSMR2 UiSMR3 6 to 0 SCLKDIV 6 to 0 SU1HIM 2 to 0 NODC 7 to 4 UiSMR4 i=0 to 4 7 to 0 Bit Set transmit data Received data Overrun error flag Set to "0016" Set to "0012" Set to "1" Set to "0" Set to "002" Disabled because the CRD bit is set to "1" Transfer register empty flag Set to "1" Select the output format of the TxDi pin Set to "0" Set to "0" Set to "1" to enable data transmission and reception Transfer buffer empty flag Set to "1" to enable data reception Reception complete flag Select what causes the UARTi transmit interrupt to be generated Set to "0" Set to "0" Set to "00000002" See Table 17.29 Set to "00000002" See Table 17.29 Set to "0002" Set to "0" Set to "00002" Set to "0016" Function Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 233 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) Table 17.26 Pin Settings in GCI Mode (1) Port P60 P61 P62 P63 P64 P65 P66 P67 NOTES: _______ Function PS0 Register __________ Setting PSL0 Register – – – – – – – – PD6 Register PD6_0=0 PD6_1=0 PD6_2=0 – PD6_4=0 PD6_5=0 PD6_6=0 – PS0_0=0 PS0_1=0 PS0_2=0 PS0_3=1 PS0_4=0 PS0_5=0 PS0_6=0 PS0_7=1 CTS0 input(1) CLK0 input RxD0 input TxD0 output __________ CTS1 input(1) CLK1 input RxD1 input TxD1 output 1. CTS input is used as a trigger siganl input. Table 17.27 Pin Settings (2) Port P70(1) P71(1) P72 P73 Function PS1 Register TxD2 output RxD2 input CLK2 input __________ Setting PSL1 Register PSL1_0=0 – – – PSC Register PSC_0=0 – – – PD7 Register – PD7_1=0 PD7_2=0 PD7_3=0 PS1_0=1 PS1_1=0 PS1_2=0 PS1_3=0 CTS2 input(2) NOTES: 1. P70 and P71 are ports for the N-channel open drain output. _______ 2. CTS input is used as a trigger siganl input. Table 17.28 Pin Settings (3) Port P90 P91 P92 P93 P94 P95 P96 P97 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. _______ 2. CTS input is used for a trigger siganl input. Function PS3 Register(1) CLK3 input RxD3 input TxD3 output __________ __________ Setting PSL3 Register – – PSL3_2=0 PSL3_3=0 PSL3_4=0 PSL3_5=0 – – PD9 Register(1) PD9_0=0 PD9_1=0 – PD9_3=0 PD9_4=0 PD9_5=0 – PD9_7=0 PS3_0=0 PS3_1=0 PS3_2=1 PS3_3=0 PS3_4=0 PS3_5=0 PS3_6=1 PS3_7=0 CTS3 input(2) CTS4 input(2) CLK4 input TxD4 output RxD4 input Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 234 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) To generate the internal clock synchronized with the external clock, set the SU1HIM bit in the UiSMR2 register (i=0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 17.29. Then apply ________ a trigger signal to the CTSi pin. Either the same clock cycle as the external clock or external clock divided by two can be selected as the transfer clock. The SCLKSTPB bit in the UiC1 register controls the transfer clock. Set the SCLKSTPB bit accordingly, to start or stop the transfer clock during an external clock operation. Figure 17.27 shows an example of the clock-divided synchronous function. Table 17.29 Clock-Divided Synchronous Function Select SCLKDIV Bit in UiSMR Register 0 0 1 SU1HIM Bit in UiSMR2 Register 0 1 0 or 1 Not synchronized Same division as the external clock Same division as the external clock divided by 2 i=0 to 4 A in Figure 17.27 B in Figure 17.27 Clock-Divided Synchronous Function Example of Waveform External Clock from the CLKi Pin Trigger Signal from the CTSi Pin 1 2 3 4 5 6 7 8 Transfer Clock A TxDi Transfer Clock 1 2 3 4 5 6 7 8 The SCLKSTPB bit in the UiC1 register stops the clock B TxDi i=0 to 4 A, B : See Table 17.29. 1 2 3 4 5 6 7 8 Figure 17.27 Clock-Divided Synchronous Function Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 235 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) 17.6 Special Mode 4 (IE Mode) In IE mode, devices connected with the IEBus can communicate in UART mode. Table 17.30 lists register settings. Tables 17.31 to 17.33 list pin settings. Table 17.30 Register Settings in IE Mode Register UiTB UiRB 8 to 0 8 to 0 OER, FER, PER, SUM UiBRG UiMR 7 to 0 SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL UiC0 CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM, UiLCH, SCLKSTPB UiSMR 3 to 0 ABSCS ACSE SSS SCLKDIV UiSMR2 UiSMR3 UiSMR4 IFSR i=0 to 4 7 to 0 7 to 0 7 to 0 IFSR6, IFSR7 Set to "00002" Select bus conflict detect sampling timing Set to "1" to automatically clear the transmit enable bit Select transmit start condition Set to "0" Set to "0016" Set to "0016" Set to "0016" Select how the bus conflict interrupt occurs Set bit rate Set to "1102" Select the internal clock or external clock Set to "0" Disabled because the PRYE bit is set to "0" Set to "0" Select TxD and RxD I/O polarity Select count source for the UiBRG register Disabled because the CRD bit is set to "1" Transfer register empty flag Set to "1" Select output format of the TxDi pin Set to "0" Set to "0" Set to "1" to enable data transmission Transfer buffer empty flag Set to "1" te enable data reception Reception complete flag Select what causes the UARTi transmit interrupt to be generated Set to "0" Bit Set transmit data Received data can be read Error flags Function Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 236 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) Table 17.31 Pin Settings in IE Mode (1) Port P61 P62 P63 P65 P66 P67 Function PS0 Register CLK0 input CLK0 output RxD0 input TxD0 output CLK1 input CLK1 output RxD1 input TxD1 output PS0_1=0 PS0_1=1 PS0_2=0 PS0_3=1 PS0_5=0 PS0_5=1 PS0_6=0 PS0_7=1 – – – – – – – – Setting PSL0 Register – PD6_2=0 – PD6_5=0 – PD6_6=0 – PD6 Register PD6_1=0 Table 17.32 Pin Settings (2) Port P70(1) P71(1) P72 NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Function PS1 Register TxD2 output RxD2 input CLK2 input CLK2 output PS1_0=1 PS1_1=0 PS1_2=0 PS1_2=1 – – PSL1_2=0 PSL1_0=0 Setting PSL1 Register – – PSC_2=0 PSC Register PSC_0=0 – PD7_1=0 PD7_2=0 – PD7 Register Table 17.33 Pin Settings (3) Port P90 P91 P92 P95 P96 P97 Function PS3 CLK3 input CLK3 output RxD3 input TxD3 output CLK4 input CLK4 output TxD4 output RxD4 input Register(1) – – – PSL3_2=0 PSL3_5=0 – – – PS3_0=0 PS3_0=1 PS3_1=0 PS3_2=1 PS3_5=0 PS3_5=1 PS3_6=1 PS3_7=0 Setting PSL3 Register – PD9_1=0 – PD9_5=0 – – PD9_7=0 PD9 Register(1) PD9_0=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 237 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) If the output signal level of the TxDi pin (i=0 to 4) differs from the input signal level of the RxDi pin, an interrupt request is generated. UART0 and UART3 are assigned software interrupt number 40. UART1 and UART4 are assigned number 41. When using the bus conflict detect function of UART0 or UART3, of UART1 or UART4, set the IFSR6 bit and the IFSR7 bit in the IFSR register accordingly. When the ABSCS bit in the UiSMR register is set to "0" (rising edge of the transfer clock), it is determined, on the rising edge of the transfer clock, if the output level of the TxD pin and the input level of the RxD pin match. When the ABSCS bit is set to "1" (timer Aj underflow), it is determined when the timer Aj (timer A3 in UART0, timer A4 in UART1, timer A0 in UART2, timer A3 in UART3, the timer A4 in UART4) counter overflows. Use the timer Aj in one-shot timer mode. When the ACSE bit in the UiSMR register is set to "1" (automatic clear at bus conflict) and the IR bit in the BCNiIC register to "1" (discrepancy detected), the TE bit in the UiC1 register is set to "0" (transmit disable). When the SSS bit in the UiSMR register is set to "1" (synchronized with RxDi), data is transmitted from the TxDi pin on the falling edge of the RxDi pin. Figure 17.28 shows bits associated with the bus conflict detect function. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 238 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) (1) The ABSCS Bit in the UiSMR Register (Bus conflict and sampling clock selected) (i=0 to 4) Bus conflict is detected on the rising edge of the transfer clock when the ABSCS bit is set to "0" Transfer Clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxDi RxDi Trigger signal is applied to the TAjIN pin Timer Aj When ABSCS is set to "1", bus conflict is detected when the timer Aj underflows (in the one-shot timer mode). An interrupt request is generated. Timer Aj: timer A3 in UART0 or UART3, timer A4 in UART1 or UART4, timer A0 in UART2 (2) The ACSE Bit in the UiSMR Register (Transmit enable bit is automatically cleared) Transfer Clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxDi RxDi IR bit in BCNilC register TE bit in UiC1 register (3) The SSS bit in the UiSMR Register (Transmit start condition selected) When the SSS bit is set to "0", data is transmitted after one transfer clock cycle if data transmission is enabled. Transfer Clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxDi transmit enable conditons are met When the SSS bit is set to "1", data is transmitted on the falling edge of the RxDi pin(1) CLKi ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TxDi RxDi (Note 2) NOTES: 1. Data is transmitted on the falling edge of a signal applied to the RxDi pin when the IOPOL bit is set to "0". Data is transmitted on the rising edge of a signal applied to the RxDi pin when the IOPOL bit is set to "1". 2. Data transmission condition must be met before the falling edge of the RxDi pin. Figure 17.28 Bit Function Related Bus Conflict Detection Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 239 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) 17.7 Special Mode 5 (SIM Mode) In SIM mode, SIM interface devices can communicate in UART mode. Both direct and inverse formats are available and a low-level ("L") signal output can be provided from the TxDi pin (i=0 to 4) when a parity error is detected. Table 17.34 lists specifications of SIM mode. Table 17.35 lists register settings. Tables 17.36 to 17.38 list pin settings. Table 17.34 SIM Mode Specifications Item Transfer Data Format • Transfer data: 8-bit UART mode • In direct format Parity: Data logic: Transfer format: Transfer Clock Even Direct LSB first Specification • One stop bit • In inverse format Parity: Data logic: Transfer format: Odd Inverse MSB first • The CKDIR bit in the UiMR register (i=0 to 4) is "0" (internal clock selected): fj/16(m+1)(1) fj = f1, f8, f2n(2) m : setting value of the UiBRG register, 0016 to FF16 Do not set the CKDIR bit to "1" (external clock selected) _______ _______ Transmit/Receive Control The CRD bit in the UiC0 register is set to "1" (CTS, RTS function disabled) Other Setting Items The UiIRS bit in the UiC1 register is set to "1" (transmission completed) Transmit Start Condition To start transmitting, the following requirements must be met: - Set the TE bit in the UiC1 register to "1" (transmit enable) - Set the TI bit in the UiC1 register to "0" (data in the UiTB register) Receive Start Condition To start receiving, the following requirements must be met: - Set the RE bit in the UiC1 register to "1" (receive enable) - Detect the start bit Interrupt Request Generation Timing • While transmitting, -The UiIRS bit is set to "1" (transmission completed): when data transmission from the UARTi transfer register is completed • While receiving, when data is transferred from the UARTi receive register to the UiRB register (reception completed) Error Detection • Overrun error(1) This error occurs when the eighth bit of the next data is received before reading the UiRB register • Flaming error This error occurs when the number of the stop bit set is not detected • Parity error This error occurs when the number of "1" in parity bit and character bits differs from the number set • Error sum flag The SUM bit is set to "1" when an overrun error, framing error or parity error occurs NOTES: 1. If an overrun error occurs, the UiRB register is indeterminate. The IR bit in the SiRIC register does not change to "1" (interrupt requested). 2. The CNT3 to CNT0 bits in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 240 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) Table 17.35 Register Settings in SIM Mode Register UiTB UiRB 7 to 0 7 to 0 OER, FER, PER, SUM UiBRG UiMR 7 to 0 SMD2 to SMD0 CKDIR STPS PRY PRYE IOPOL UiC0 CLK1, CLK0 CRS TXEPT CRD NCH CKPOL UFORM UiC1 TE TI RE RI UiIRS UiRRM UiLCH UiERE UiSMR UiSMR2 UiSMR3 UiSMR4 i=0 to 4 7 to 0 7 to 0 7 to 0 7 to 0 Set bit rate Set to "1012" Set to "0" Set to "0" Set to "1" for direct format or "0" for inverse format Set to "1" Set to "0" Select count source for the UiBRG register Disabled because the CRD bit is set to "1" Transfer register empty flag Set to "1" Set to "1" Set to "0" Set to "0" for direct format or "1" for inverse format Set to "1" to enable data transmission Transfer buffer empty flag Set to "1" to enable data reception Reception complete flag Set to "1" Set to "0" Set to "0" for direct format or "1" for inverse format Set to "1" Set to "0016" Set to "0016" Set to "0016" Set to "0016" Bit Set transmit data Received data can be read Error flags Function Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 241 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) Table 17.36 Pin Settings in SIM Mode (1) Port P62 P63 P66 P67 Function PS0 Register RxD0 input TxD0 output RxD1 input TxD1 output PS0_2=0 PS0_3=1 PS0_6=0 PS0_7=1 – – – – Setting PSL0 Register – PD6_6=0 – PD6 Register PD6_2=0 Table 17.37 Pin Settings (2) Port P70(1) P71(1) NOTES: 1. P70 and P71 are ports for the N-channel open drain output. Function PS1 Register TxD2 output RxD2 input PS1_0=1 PS1_1=0 PSL1_0=0 – Setting PSL1 Register – PSC Register PSC_0=0 PD7 Register – PD7_1=0 Table 17.38 Pin Settings (3) Port P91 P92 P96 P97 Function PS3 RxD3 input TxD3 output TxD4 output RxD4 input Register(1) – PSL3_2=0 – – PS3_1=0 PS3_2=1 PS3_6=1 PS3_7=0 Setting PSL3 Register – – PD9_7=0 PD9 Register(1) PD9_1=0 NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Figure 17.29 shows an example of a SIM interface operation. Figure 17.30 shows an example of a SIM interface connection. Connect the TxDi pin to the RxDi pin for a pull-up. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 242 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) (1) Transmit Timing Tc Transfer Clock TE bit in UiC1 register TI bit in UiC1 register "1" "0" "1" "0" Data is written to the UARTi register (Note 1) Data is transferred from the UiTB register to the UARi transmit register Start bit Parity Stop bit bit D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 An "L" signal is applied from the SIM card due to a parity error ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 An interrupt routine detects "H" or "L" P SP P SP TxDi Parity Error Signal returned from Receiving End Signal Line Level(2) TXEPT bit in UiC0 register IR bit in SiTIC register ST D0 D1 "1" "0" "1" "0" An interrupt routine detects "H" or "L" Set to "0" by an interrupt request acknowledgement or by program i=0 to 4 The above applies to the following settings : • The PRYE bit in the UiMR register is set to "1" (parity enabled) • The STPS bit in the UiMR register is set to "0" (1 stop bit) • The UiIRS bit in the UiC1 register is set to "1" (interrupt request generated when transmission completed) Tc = 16(m+1) / fj fj : count source frequency of the UiBRG register (f1, f8, f2n(4)) m : setting value of the UiBRG register (2) Receive Timing Transfer Clock RE bit in UiC1 register Transmit Waveform from the Transmitting End TxDi "1" "0" Start bit ST D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxDi outputs "L" due to a parity error ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP Signal Line Level(3) RI bit in UiC1 register IR bit in SiRIC register "1" "0" "1" "0" Read the UiRB register Set to "0" by an interrupt request acknowledgement or by program i=0 to 4 The above applies to the following settings : • The PRYE bit in the UiMR register is set to "1" (parity enabled) • The STPS bit in the UiMR register is set to "0" (1 stop bit) Tc = 16(m+1) / fj fj : count source frequency of the UiBRG register (f1, f8, f2n(4)) m : setting value of the UiBRG register NOTES: 1. Data transmission starts when BRG overflows after a value is set to the UiTB register on the rising edge of the TI bit. 2. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the TxDi pin and parity error signal from the receiving end, is generated. 3. Because the TxDi and RxDi pins are connected, a composite waveform, consisting of transmit waveform from the transmitting end and parity error signal from the TxDi pin, is generated. 4. The CNT3 to CNT0 bits in the TCSPR register selects no division (n=0) or divide-by-2n (n=1 to 15). Figure 17.29 SIM Interface Operation Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 243 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) Microcomputer SIM card TxDi RxDi i=0 to 4 Figure 17.30 SIM Interface Connection 17.7.1 Parity Error Signal 17.7.1.1 Parity Error Signal Output Function When the UiERE bit in the UiC1 register (i=0 to 4) is set to "1", the parity error signal output can be provided. The parity error signal output is provided when a parity error is detected upon receiving data. A low-level ("L") signal output is provided from the TxDi pin in the timing shown in Figure 17.31. When reading the UiRB register during a parity error output, the PER bit in the UiRB register is set to "0" and a high-level ("H") signal output is again provided simultaneously. 17.7.1.2 Parity Error Signal To determine whether the parity error signal is output, the port that shares a pin with the RxDi pin is read by using an end-of-transmit interrupt routine. Transfer Clock "H" "L" RxDi "H" "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP TxDi Recieve Complete Flag "H" "L" "1" "0" Hi-Z NOTES: 1. The above applies to direct format conditions. (The PRY bit is set to "1", the UFORM bit is set to "0", and the UiLCH bit is set to "0"). ST : Start bit P : Even parity SP : Stop bit i=0 to 4 Figure 17.31 Parity Error Signal Output Timing (LSB First) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 244 of 495 M32C/84 Group (M32C/84, M32C/84T) 17. Serial I/O (Special Function) 17.7.2 Format 17.7.2.1 Direct Format Set the PRYE bit in the UiMR register (i=0 to 4) to "1" (parity enabled), the PRY bit to "1" (even parity), the UFORM bit in the UiC0 register to "0" (LSB first) and the UiLCH bit in the UiC1 register to "0" (not inversed). When data are transmitted, data set in the UiTB register are transmitted with the even-numbered parity, starting from D0. When data are received, received data are stored in the UiRB register, starting from D0. The even-numbered parity determines whether a parity error occurs. 17.7.2.2 Inverse Format Set the PRYE bit to "1", the PRY bit to "0" (odd parity), the UFORM bit to "1" (MSB first) and the UiLCH bit to "1" (inversed). When data are transmitted, values set in the UiTB register are logically inversed and are transmitted with the odd-numbered parity, starting from D7. When data are received, received data are logically inversed to be stored in the UiRB register, starting from D7. The odd-numbered parity determines whether a parity error occurs. (1) Direct Format Transfer Clock "H" "L" TxDi "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 P P : Even parity (2) Inverse Format Transfer Clock TxDi "H" "L" "H" "L" D7 D6 D5 D4 D3 D2 D1 D0 P P : Odd parity i=0 to 4 Figure 17.32 SIM Interface Format Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 245 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 18. A/D Converter The A/D converter consists of one 10-bit successive approximation A/D converter with a capacitive coupling amplifier. The result of an A/D conversion is stored into the A/D registers corresponding to selected pins. It is stored into the AD00 register only when DMAC operating mode is entered. Table 18.1 lists specifications of the A/D converter. Figure 18.1 shows a block diagram of the A/D converter. Figures 18.2 to 18.6 show registers associated with the A/D converter. NOTE This section is described in the 144-pin package only as an example. The AN150 to AN157 pins are not included in the 100-pin package. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 246 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter Table 18.1 A/D Converter Specifications Item A/D Conversion Method Analog Input Resolution Operating Mode Voltage(1) Operating Clock, ØAD(2) 0V to AVCC (VCC1) fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8 Select from 8 bits or 10 bits One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat sweep mode 1, multi-port single sweep mode, multi-port repeat sweep mode 0 Analog Input Pins(3) 34 pins 8 pins each for AN (AN0 to AN7), AN0 (AN00 to AN07), AN2 (AN20 to AN27), AN15 (AN150 to AN157) 2 extended input pins (ANEX0 and ANEX1) A/D Conversion Start Condition • Software trigger The ADST bit in the AD0CON0 register is set to "1" (A/D conversion started) by program • External trigger (re-trigger is enabled) __________ Specification Successive approximation (with a capacitive coupling amplifier) When a falling edge is applied to the AD TRG pin after the ADST bit is set to "1" by program • Hardware trigger (re-trigger is enabled) The timer B2 interrupt request of the three-phase motor control timer functions (after the ICTB2 counter completes counting) is generated after the ADST bit is set to "1" by program Conversion Rate Per Pin • Without the sample and hold function 8-bit resolution : 49 ØAD cycles 10-bit resolution : 59 ØAD cycles • With the sample and hold function 8-bit resolution : 28 ØAD cycles 10-bit resolution : 33 ØAD cycles NOTES: 1. Analog input voltage is not affected by the sample and hold function status. 2. ØAD frequency must be under 16 MHz when VCC1=5V. ØAD frequency must be under 10 MHz when VCC1=3.3V. Without the sample and hold function, the ØAD frequency is 250 kHz or more. With the sample and hold function, the ØAD frequency is 1 MHz or more. 3. AVCC = VREF = VCC1 ≥ VCC2, A/D input voltage (for AN0 to AN7, AN150 to AN157, ANEX0 and ANEX1) ≤ VCC1, A/D input voltage (for AN00 to AN07 and AN20 to AN27) ≤ VCC2. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 247 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 000 001 010 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 P2(1) ADTRG Timer B2 interrupt request of the three-phase motor control timer functions 0 011 1 1 EX TRG0 TRG bit in AD0CON0 register 100 101 110 111 TRG0 bit in AD0CON2 register 000 001 AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN150 AN151 AN152 AN153 AN154 AN155 AN156 AN157 P15(2) P0(1) OPA1 and OPA0 bits in AD0CON1 register 010 011 100 P96 ANEX1 P95 ANEX0 1X X1 01 101 110 11 111 AN0 AN1 AN2 P10 AN3 AN4 AN5 AN6 AN7 000 001 010 011 100 101 110 111 CH2 to CH0 bits in AD0CON0 register APS1 and APS0 bits in AD0CON2 register 00 00 11 10 01 000 001 010 011 100 101 110 111 CH2 to CH0 bits in AD0CON0 register AD00 register AD01 register AD02 register Decoder AD03 register AD04 register AD05 register AD06 register AD07 register Successive conversion register Comparator 0 AD0CON0 register Resistor ladder AD0CON1 register AD0CON2 register 1 AD0CON3 register 1/2 AD0CON4 register fAD 0 1 1/3 0 1 0 ØAD 1 1/2 1/2 0 NOTES: 1. These pins are available in single-chip mode. 2. These pins are provided in the 144-pin package. CSK2 bit in AD0CON3 register CSK0 bit in AD0CON0 register CSK1 bit in AD0CON1 register Figure 18.1 A/D Converter Block Diagram Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 248 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter A/D0 Control Register 0(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol AD0CON0 Address 039616 After Reset 0016 Bit Symbol CH0 Bit Name b2 b1b0 Function 0 0 0 : ANi0 0 0 1 : ANi1 0 1 0 : ANi2 0 1 1 : ANi3 1 0 0 : ANi4 1 0 1 : ANi5 1 1 0 : ANi6 1 1 1 : ANi7 b4 b3 RW RW CH1 Analog Input Pin Select Bit(2, 3, 8, 9) RW CH2 (i=none, 0, 2, 15) RW MD0 MD1 0 0 : One-shot mode A/D Operating Mode 0 1 : Repeat mode Select Bit 0(2, 6, 7) 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 or 1 Trigger Select Bit A/D Conversion Start Flag Frequency Select Bit 0 : Software trigger 1 : External trigger, hardware trigger(4) 0 : A/D conversion stops 1 : A/D conversion starts(4) (Note 5) RW RW TRG RW ADST RW CKS0 RW NOTES: 1. When the AD0CON0 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. Analog input pins must be set again after changing an A/D operating mode. 3. The CH2 to CH0 bit settings are enabled in one-shot mode and repeat mode. 4. To set the TRG bit to "1", select the cause of trigger by setting the TRG0 bit in the AD0CON2 register. Then set the ADST bit to "1" after the TRG bit is set to "1". 5. AD frequency must be under 16 MHz when VCC1=5V. AD frequency must be under 10 MHz when VCC1=3.3V. Combination of the CKS0, CKS1 and CKS2 bits selects AD. The CKS2 Bit in the AD0CON3 Register The CKS0 Bit in the AD0CON0 Register 0 0 1 1 0 The CKS1 Bit in the AD0CON1 Register 0 1 0 1 0 1 AD fAD divided by 4 fAD divided by 3 fAD divided by 2 fAD fAD divided by 8 fAD divided by 6 6. When the MSS bit in the AD0CON3 register is set to "1" (multi-port sweep mode enabled), set the MD1 and MD0 bits to "102" to enter multi-port single sweep mode and to "112" to enter multi-port repeat sweep mode 0. 7. When the MSS bit is set to "1", the MD1 and MD0 bits cannot be set to "002" or "012". 8. AVCC=VREF=VCC1≥VCC2, AD input voltage (for AN0 to AN7, AN150 to AN157, ANEX0, ANEX1) ≤ VCC1, AD input voltage (for AN00 to AN07, AN20 to AM27) ≤ VCC2. 9. Set the PSC_7 bit in the PSC register to "1" to use the P10 pin as an analog input pin. Figure 18.2 AD0CON0 Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 249 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter A/D0 Control Register 1(1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol AD0CON1 Address 039716 After Reset 0016 Bit Symbol Bit Name b1 b0 Function Single sweep mode and repeat sweep mode 0 RW SCAN0 0 0 : ANi0, ANi1 0 1 : ANi0 to ANi3 1 0 : ANi0 to ANi5 1 1 : ANi0 to ANi7 Repeat sweep mode 1(3) A/D Sweep Pin Select Bit(2, 10) b1 b0 RW SCAN1 0 0 : ANi0 0 1 : ANi0, ANi1 1 0 : ANi0 to ANi2 1 1 : ANi0 to ANi3 (i=none, 0, 2, 15) RW Multi-port single sweep mode and multi-port repeat sweep mode 0(4) b1 b0 1 1 : ANi0 to ANi7 MD2 BITS A/D Operating Mode Select Bit 1 8/10-Bit Mode Select Bit Frequency Select Bit VREF Connection Bit External Op-Amp Connection Mode Bit(7, 9) 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1(5) 0 : 8-bit mode 1 : 10-bit mode (Note 6) 0 : No VREF connection(11) 1 : VREF connection b7 b6 RW RW CKS1 RW VCUT RW OPA0 OPA1 0 0 : ANEX0 and ANEX1 are not used(8) 0 1 : Signal into ANEX0 is A/D converted 1 0 : Signal into ANEX1 is A/D converted 1 1 : External op-amp connection mode RW RW NOTES: 1. When the AD0CON1 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. The SCAN1 and SCAN0 bit settings are disabled in single sweep mode, repeat sweep mode 0, repeat sweep mode 1, mutli-port single sweep mode and multi-port repeat sweep mode 0. 3. This pin is commonly used in the A/D conversion when the MD2 bit is set to "1". 4. In multi-port single sweep mode or multi-port repeat sweep mode 0, do not set the SCAN1 and SCAN0 bits to any setting other than "112". 5. When the MSS bit in the AD0CON3 register is set to "1" (multi-port sweep mode enabled), set the MD2 bit to "0". 6. Refer to the note for the CKS0 bit in the AD0CON0 register. 7. In one-shot mode and repeat mode, the OPA1 and OPA0 bits can be set to "012" or "102" only. Do not set the OPA0 and OPA1 bits to "012" or "102" in other modes. 8. To set the OPA1 and OPA0 bits to "002", set the PSL3_5 bit in PSL3 register to "0" (other than ANEX0) and the PSL3_6 bit to "0" (other than ANEX1). 9. When the MSS bit is set to "1", set the OPA1 and OPA0 bits to "002". 10. AVCC=VREF=VCC1≥VCC2, AD input voltage (for AN0 to AN7, AN150 to AN157, ANEX0, ANEX1) ≤ VCC1, AD input voltage (for AN00 to AN07, AN20 to AM27) ≤ VCC2. 11. Do not set the VCUT bit to "0" during the A/D conversion. VREF is a reference voltage for AD0 only. The VCUT bit setting does not affect the VREF performance Figure 18.3 AD0CON1 Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 250 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter A/D0 Control Register 2(1) b7 b6 b5 b4 b3 b2 b1 b0 00 Symbol AD0CON2 Bit Symbol Address 039416 After Reset XX0X X0002 Bit Name A/D Conversion Method Select Bit Function 0 : Without the sample and hold funtion 1 : With the sample and hold function b2b1 RW RW RW SMP APS0 Analog Input Port Select Bit(2, 3, 4) APS1 0 0 : AN0 to AN7, ANEX0, ANEX1 0 1 : AN150 to AN157 1 0 : AN00 to AN07 1 1 : AN20 to AN27 RW (b4 - b3) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. External Trigger Request Cause Select Bit 0 : Selects ADTRG 1 : Selects a timer B2 interrupt request RW of the three-phase motor control timer functions (after the ICTB2 counter completes counting) Set to "0". RW When read, its content is indeterminate. TRG0 (b7 - b6) Reserved Bit NOTES: 1. When the AD0CON2 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. When the MSS bit in the AD0CON3 register is set to "1" (multi-port sweep mode enabled), set the APS1 and APS0 bits to "012". 3. The APS1 and APS0 bits can be set to "012" in the 100-pin package only when the MSS bit in the AD0CON3 register is set to "1" (multi-port sweep mode enabled). 4. The APS1 and APS0 bits can be set to "102" or "112" in single-chip mode only. Figure 18.4 AD0CON2 Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 251 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter A/D0 Control Register 3(1, 2) b7 b6 b5 b4 b3 b2 b1 b0 000 Symbol AD0CON3 Address 039516 After Reset XXXX X0002 Bit Symbol DUS Bit Name DMAC Operation Select Bit(3) Multi-Port Sweep Mode Select Bit Function 0 : Disables DMAC operating mode 1 : Enables DMAC operating mode(4, 5) 0 : Disables multi-port sweep mode 1 : Enables multi-port sweep mode(3, 6) RW RW MSS RW CKS2 Frequency Select Bit (Note 7) b4 b3 RW MSF0 Multi-Port Sweep Status Flag(8) MSF1 0 0 : AN0 to AN7 0 1 : AN150 to AN157 1 0 : AN00 to AN07 1 1 : AN20 to AN27 Set to "0". When read, its content is indeterminate. RO RO (b7 - b5) Reserved Bit RW NOTES: 1. When the AD0CON3 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. The AD0CON3 may be read uncorrectly during the A/D conversion. It must be read or written after the A/D converter stops operating. 3. When the MSS bit is set to "1", set the DUS bit to "1". 4. When the DUS bit is set to "1", the AD00 register stores all A/D conversion results. 5. When the DUS bit is set to "1", set the DMAC. 6. When the MSS bit is set to "1", set the MD2 bit in the AD0CON1 register to "0" (other than repeat sweep mode 1), the APS1 and APS0 bits in the AD0CON2 register to "012" (AN150 to AN157) and the OPA1 and OPA0 bits in the AD0CON1 register to "002" (ANEX0 and ANEX1 not used). 7. Refer to the note for the CKS0 bit in the AD0CON0 register. 8. The MSF1 and MSF0 bit settings are enabled when the MSS bit is set to "1". Value in the bit is indeterminate when the MSS bit is set to "0". Figure 18.5 AD0CON3 Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 252 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter A/D0 Control Register 4(1) b7 b6 b5 b4 b3 b2 b1 b0 0000 00 Symbol AD0CON4 Address 039216 After Reset XXXX 00XX2 Bit Symbol Bit Name Reserved Bit Function RW (b1 - b0) MPS10 Set to "0". RW When read, its content is indeterminate. b3 b2 Multi-Port Sweep Port Select Bit(2, 3) MPS11 0 0 : (Note 4) 0 1 : AN0 to AN7, AN150 to AN157 1 0 : AN0 to AN7, AN00 to AN07 1 1 : AN0 to AN7, AN20 to AN27 RW RW Reserved Bit (b7 - b4) Set to "0". RW When read, its content is indeterminate. NOTES: 1. When the AD0CON4 register is rewritten during the A/D conversion, the conversion result is indeterminate. 2. The MPS11 and MPS10 bits cannot be set to "012" in the 100-pin package. 3. The MPS11 and MPS10 bits can be set to "102" or "112" in single-chip mode only. 4. When the MSS bit in the AD0CON3 regsiter is set to "0" (multi-port sweep mode disabled), set the MPS11 and MPS10 bits to "002". When the MSS bit is set to "1" (multi-port sweep mode enabled), set the MPS11 and MPS10 bits to "012", "102" or "112". A/D0 Register i (i =0 to 7)(1, 2, 3, 4, 5) b15 b8 b7 b0 Symbol AD00 AD01 to AD03 AD04 to AD06 AD07 Address 038116 - 038016 038316 - 038216, 038516 - 038416, 038716 - 038616 038916 - 038816, 038B16 - 038A16, 038D16 - 038C16 038F16 - 038E16 After Reset 00000000 XXXXXXXX2 Indeterminate Indeterminate Indeterminate Function 8 low-order bits in an A/D conversion result In 10-bit mode In 8-bit mode : 2 high-order bits in an A/D conversion result : When read, its content is indeterminate. RW RO RO RO When read, its content is indeterminate. NOTES: 1. In DMAC operating mode, register value read by program is indeterminate. 2. Register value is indeterminate when written while the A/D conversion is stopped. 3. Register value is indeterminate if the next A/D conversion result is stored before reading the register. 4. The AD00 register is available in DMAC operating mode. Other registers are indeterminate. 5. In DMAC operating mode and 10-bit mode, set DMAC for a 16-bit transfer. Figure 18.6 AD0CON4 Register and AD00 to AD07 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 253 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 18.1 Mode Description 18.1.1 One-shot Mode In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 18.2 lists specifications of one-shot mode. Table 18.2 One-shot Mode Specifications Item Function Specification The CH2 to CH0 bits in the AD0CON0 register, the OPA1 and OPA0 bits in the AD0CON1 register and the APS1 and APS0 bits in the AD0CON2 register select a pin. Analog voltage applied to the pin is converted to a digital code once Start Condition • When the TRG bit in the AD0CON0 register is set to "0" (software trigger), the ADST bit in the AD0CON0 register is set to "1" (A/D conversion starts) by program • When the TRG bit is set to "1" (external trigger, hardware trigger): __________ - a falling edge is applied to the AD TRG pin after the ADST bit is set to "1" by program - The timer B2 interrupt request of three-phase motor control timer functions (after the ICTB2 register counter completes counting) is generated after the ADST bit is set to "1" by program Stop Condition • A/D conversion is completed (the ADST bit is set to "0" when the software trigger is selected) • The ADST bit is set to "0" (A/D conversion stopped) by program Interrupt Request Generation Timing A/D conversion is completed Analog Voltage Input Pins Select one pin from ANi0 to ANi7 (i=none, 0, 2, 15), ANEX0 or ANEX1 mode disabled), the microcomputer reads the AD0j register (j=0 to 7) corresponding to selected pin • When the DUS bit is set to "1" (DMAC operating mode enabled), do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings Reading of A/D Conversion Result • When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 254 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 18.1.2 Repeat Mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 18.3 lists specifications of repeat mode. Table 18.3 Repeat Mode Specifications Item Function Specification The CH2 to CH0 bits in the AD0CON0 register, the OPA1 and OPA0 bits in the AD0CON1 register and the APS1 and APS0 bits in the AD0CON2 register select a pin. Analog voltage applied to the pin is repeatedly converted to a digital code Start Condition Stop Condition Same as one-shot mode The ADST bit in the AD0CON0 register is set to "0" (A/D conversion stopped) by program Interrupt Request Generation Timing • When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating mode disabled), no interrupt request is generated. • When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt request is generated every time an A/D conversion is completed. Analog Voltage Input Pins Select one pin from ANi0 to ANi7 (i=none, 0, 2, 15), ANEX0 or ANEX1 7) corresponding to the selected pin. • When DUS bit is set to "1", do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings Reading of A/D Conversion Result • When the DUS bit is set to "0", the microcomputer reads the AD0j register (j=0 to Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 255 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 18.1.3 Single Sweep Mode In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 18.4 lists specifications of single sweep mode. Table 18.4 Single Sweep Mode Specifications Item Function Specification The SCAN1 and SCAN0 bits in the AD0CON1 register and the APS1 and APS0 bits in the AD0CON2 register select pins. Analog voltage applied to the pin is converted one-by-one to a digital code Start Condition Stop Condition Same as one-shot mode Same as one-shot mode mode disabled), an interrupt request is generated after a sweep is completed. • When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt request is generated every time an A/D conversion is completed Analog Voltage Input Pins Select from ANi0 and ANi1 (2 pins) (i=none, 0, 2, 15), ANi0 to ANi3 (4 pins), ANi0 to ANi5 (6 pins) or ANi0 to ANi7 (8 pins) Reading of A/D Conversion Result • When the DUS bit is set to "0", the microcomputer reads the AD0j register corresponding to selected pins • When DUS bit is set to "1", do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings Interrupt Request Generation Timing • When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 256 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 18.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code. Table 18.5 lists specifications of repeat sweep mode 0. Table 18.5 Repeat Sweep Mode 0 Specifications Item Function Specification The SCAN1 and SCAN0 bits in the AD0CON1 register and the APS1 and APS0 bits in the AD0CON2 register select pins. Analog voltage applied to the pins is repeatedly converted to a digital code Start Condition Stop Condition Same as one-shot mode The ADST bit in the AD0CON0 register is set to "0" (A/D conversion stopped) by program Interrupt Request Generation Timing • When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating mode disabled), no interrupt request is generated • When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt request is generated every time an A/D conversion is completed Analog Voltage Input Pins Select from ANi0 and ANi1 (2 pins) (i=none, 0, 2, 15), ANi0 to ANi3 (4 pins), ANi0 to ANi5 (6 pins) or ANi0 to ANi7 (8 pins) Reading of A/D Conversion Result • When the DUS bit is set to "0", the microcomputer reads the AD0j register (j=0 to 7) corresponding to selected pins • When the DUS bit is set to "1", do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 257 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 18.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage selectively applied to eight pins is repeatedly converted to a digital code. Table 18.6 lists specifications of repeat sweep mode 1. Table 18.6 Repeat Sweep Mode 1 Specifications Item Function Specification The SCAN1 and SCAN0 bits in the AD0CON1 register and the APS1 and APS0 bits in the AD0CON2 register select 8 pins. Analog voltage selectively applied to 8 pins is repeatedly converted to a digital code e.g., When ANi0 is selected (i =none, 0, 2, 15), analog voltage is converted to a digital code in the following order: ANi0 Start Condition Stop Condition ANi1 ANi0 ANi2 ANi0 ANi3 ....... etc. Same as one-shot mode (Any trigger generated during an A/D conversion is invalid) The ADST bit is set to "0" (A/D conversion stopped) by program mode disabled), no interrupt request is generated • When DUS bit is set to "1" (DMAC operating mode enabled), an interrupt request is generated every time an A/D conversion is completed Analog Voltage Input Pins Prioritized Pins ANi0 to ANi7 (8 pins) ANi0 (1 pin), ANi0 and ANi1 (2 pins), ANi0 to ANi2 (3 pins) or ANi0 to ANi3 (4 pins) 7) corresponding to selected pins • When the DUS bit is set to "1", do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings Interrupt Request Generation Timing • When the DUS bit in the AD0CON3 register is set to "0" (DMAC operating Reading of A/D Conversion Result • When the DUS bit is set to "0", the microcomputer reads the AD0j register (j=0 to Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 258 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 18.1.6 Multi-Port Single Sweep Mode In multi-port single sweep mode, analog voltage applied to 16 selected pins is converted one-by-one to a digital code. Set the DUS bit in the AD0CON3 register to "1" (DMAC operating mode enabled). Table 18.7 lists specifications of multi-port single sweep mode. Table 18.7 Multi-Port Single Sweep Mode Specifications Item Function Specification The MPS11 and MPS10 bits in the AD0CON4 register select 16 pins. Analog voltage applied to 16 pins is converted one-by-one to a digital code in the following order: AN0 to AN7 ANi0 to ANi7 (i=0, 2, 15) e.g., When the MPS11 and MPS10 bits are set to "102" (AN0 to AN7, AN00 to AN07), analog voltage is converted to a digital code in the following order: AN0 AN00 Start Condition Stop Condition AN1 AN01 AN2 ....... AN3 AN06 AN4 AN07 AN5 AN6 AN7 Same as one-shot mode The ADST bit in the AD0CON0 register is set to "0" (A/D conversion stopped) by program Interrupt Request Generation Timing An interrupt request is generated every time A/D conversion is completed (Set the DUS bit to "1") Analog Voltage Input Pins Select from AN0 to AN7 AN7 AN20 to AN27 AN150 to AN157, AN0 to AN7 AN00 to AN07 or AN0 to Reading of A/D Conversion Result Do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings (Set the DUS bit to "1") Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 259 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 18.1.7 Multi-Port Repeat Sweep Mode 0 In multi-port repeat sweep mode 0, analog voltage that is applied to 16 selected pins is repeatedly converted to a digital code. Set the DUS bit in the AD0CON3 register to "1" (DMAC operating mode enabled). Table 18.8 lists specifications of multi-port repeat sweep mode 0. Table 18.8 Multi-Port Repeat Sweep Mode 0 Specifications Item Function Specification The MPS11 and MPS10 bits in the AD0CON4 register select 16 pins. Analog voltage applied to the 16 pins is repeatedly converted to a digital code in the following order: AN0 to AN7 ANi0 to ANi7 (i=0, 2, 15) e.g., When the MPS11 and MPS10 bits are set to "10 2" (AN0 to AN7, AN00 to AN07), analog voltage is repeatedly converted to a digital code in the following order: A N0 AN00 Start Condition Stop Condition AN1 AN01 AN2 ....... AN3 AN06 AN4 AN07 AN5 AN6 AN7 Same as one-shot mode The ADST bit is set to "0" (A/D conversion stopped) by program (Set the DUS bit to "1") Interrupt Request Generation Timing An interrupt request is generated after each A/D conversion is completed Analog Voltage Input Pins Selectable from AN0 to AN7 AN0 to AN7 AN20 to AN27 AN150 to AN157, AN0 to AN7 AN00 to AN07 or Reading of A/D Conversion Result Do not read the AD00 register. A/D conversion result is stored in the AD00 register after the A/D conversion is completed. DMAC transfers the conversion result to any memory space. Refer to 13. DMAC for DMAC settings (Set the DUS bit to "1") Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 260 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 18.2 Functions 18.2.1 Resolution Select Function The BITS bit in the AD0CON1 register determines the resolution. When the BITS bit is set to "1" (10-bit precision), the A/D conversion result is stored into bits 9 to 0 in the AD0j register (j = 0 to 7). When the BITS bit is set to "0" (8-bit precision), the A/D conversion result is stored into bits 7 to 0 in the AD0j register. 18.2.2 Sample and Hold Function When the SMP bit in the AD0CON2 register is set to "1" (with the sample and hold function), A/D conversion rate per pin increases to 28 ØAD cycles for 8-bit resolution and 33 ØAD cycles for 10-bit resolution. The sample and hold function is available in all operating modes. Start the A/D conversion after selecting whether the sample and hold function is to be used or not. 18.2.3 Trigger Select Function The TRG bit in the AD0CON0 register and the TRG0 bit in the AD0CON2 register select the trigger to start the A/D conversion. Table 18.9 lists settings of the trigger select function. Table 18.9 Trigger Select Function Settings Bit and Setting AD0CON0 Register TRG = 0 AD0CON2 Register Software trigger The A/D0 starts the A/D conversion when the ADST bit in the AD0CON0 register is set to "1" TRG = 1(1) TRG0 = 0 External trigger(2) __________ Trigger Falling edge of a signal applied to ADTRG TRG0 = 1 Hardware trigger(2) The timer B2 interrupt request of three-phase motor control timer functions (after the ICTB2 counter completes counting) NOTES: 1. A/D0 starts the A/D conversion when the ADST bit is set to "1" (A/D conversion started) and a trigger is generated. 2. The A/D conversion is restarted if an external trigger or a hardware trigger is inserted during the A/D conversion. (The A/D conversion in process is aborted.) 18.2.4 DMAC Operating Mode DMAC operating mode is available with all operating modes. When the A/D converter is in multi-port single sweep mode or multi-port repeat sweep mode 0, the DMAC operating mode must be used. When the DUS bit in the AD0CON3 register is set to "1" (DMAC operating mode enabled), all A/D conversion results are stored into the AD00 register. DMAC transfers data from the AD00 register to any memory space every time an A/D conversion is completed in each pin. 8-bit DMA transfer must be selected for 8bit resolution and 16-bit DMA transfer for 10-bit resolution. Refer to 13. DMAC for instructions. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 261 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 18.2.5 Extended Analog Input Pins In one-shot mode and repeat mode, the ANEX0 and ANEX1 pins can be used as analog input pins. The OPA1 and OPA0 bits in the AD0CON1 register select which pins to use as analog input pins. An A/D conversion result for the ANEX0 pin is stored into the AD00 register. The result for the ANEX1 pin is stored into the AD01 register, but is stored into the AD00 register when the DUS bit in the AD0CON3 register is set to "1" (DMAC operating mode enabled). Set the APS1 and APS0 bits in the AD0CON2 register to "002" (AN0 to AN7, ANEX0, ANEX1) and the MSS bit in the AD0CON3 register to "0" (multi-port sweep mode disabled). 18.2.6 External Operating Amplifier (Op-Amp) Connection Mode In external op-amp connection mode, multiple analog voltage can be amplified by one external op-amp using extended analog input pins ANEX0 and ANEX1. When the OPA1 and OPA0 bits in the AD0CON1 register are set to "112" (external op-amp connection), voltage applied to the AN0 to AN7 pins are output from ANEX0. Amplify this output signal by an external op-amp and apply it to ANEX1. Analog voltage applied to ANEX1 is converted to a digital code and the A/D conversion result is stored into the corresponding AD0j register (j=0 to 7). A/D conversion rate varies depending on the response of the external op-amp. The ANEX0 pin cannot be connected to the ANEX1 pin directly. Set the APS1 and APS0 bits in the AD0CON2 register to "002" (AN0 to AN7, ANEX0, ANEX1). Figure 18.7 shows an example of an external op-amp connection. Table 18.10 Extended Analog Input Pin Settings AD0CON1 Register OPA1 Bit 0 0 1 1 OPA0 Bit 0 1 0 1 Not used P95 as an analog input Not used Output to an external op-amp Not used Not used P96 as an analog input Input from an external op-amp ANEX0 Function ANEX1 Function Analog input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ANEX0 Resistor ladder Successive conversion register 002 ANEX1 APS1 and APS0 bits in AD0CON2 register External op-amp Comparator 0 Figure 18.7 External Op-Amp Connection Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 262 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter 18.2.7 Power Consumption Reducing Function When the A/D converter is not used, the VCUT bit in the AD0CON1 register isolates the resistor ladder of the A/D converter from the reference voltage input pin (VREF). Power consumption is reduced by shutting off any current flow into the resistor ladder from the VREF pin. When using the A/D converter, set the VCUT bit to "1" (VREF connection) before setting the ADST bit in the AD0CON0 register to "1" (A/D conversion started). Do not set the ADST bit and VCUT bit to "1" simultaneously, nor set the VCUT bit to "0" (no VREF connection) during the A/D conversion. The VCUT bit does not affect the VREF performance of the D/A converter. 18.2.8 Output Impedance of Sensor Equivalent Circuit under A/D Conversion For perfect A/D converter performance, complete internal capacitor (C) charging, shown in Figure 18.8, for the specified period (T) as sampling time. Output Impedance of the sensor equivalent circuit (R0) is determined by the following equations: VC = VIN {1 – e When t = T, VC = VIN – 1 C (R0 + R) T – 1 C (R0 + R) t } X ) Y X Y VIN = VIN (1 – e – – = X Y X 1 T= ln C (R0 +R) Y T R0 = – X C • ln Y –R where: VC = Voltage between pins R = Internal resistance of the microcomputer X = Precision (error) of the A/D converter Y = Resolution of the A/D converter (1024 in 10-bit mode, and 256 in 8-bit mode) Figure 18.8 shows analog input pin and external sensor equivalent circuit. The impedance (R0) can be obtained if the voltage between pins (VC) changes from 0 to VIN-(0.1/1024) VIN in the time (T), when the difference between VIN and VC becomes 0.1LSB. (0.1/1024) means that A/D precision drop, due to insufficient capacitor charge, is held to 0.1LSB at time of A/ D conversion in the 10-bit mode. Actual error, however, is the value of absolute precision added to 0.1LSB. When ØAD = 10 MHz, T = 0.3 µs in the A/D conversion mode with the sample and hold function. Output impedance (R0) for sufficiently charging capacitor (C) in the time (T) is determined by the following equation: Using T = 0.3 µs, R = 7.8 kΩ, C = 1.5 pF, X = 0.1, Y = 1024, R0 = – 0.3 X 10-6 1.5 X 10 –12 • ln 0.1 1024 –7.8 X103 = 13.9 X 103 Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less, is approximately 13.9 kΩ maximum. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 263 of 495 M32C/84 Group (M32C/84, M32C/84T) 18. A/D Converter Microcopmuter Sensor equivalent circuit R0 VIN C (1.5pF) VC R (7.8Ω) Sampling time 3 Sample and hold function is enabled : φAD 2 Sample and hold function is disabled : φAD Figure 18.8 Analog Input Pin and External Sensor Equivalent Circuit Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 264 of 495 M32C/84 Group (M32C/84, M32C/84T) 19. D/A Converter 19. D/A Converter The D/A converter consists of two separate 8-bit R-2R ladder D/A converters. Digital code is converted to an analog voltage when a value is written to the corresponding DAi registers (i=0,1). The DAiE bit in the DACON register determines whether the D/A conversion result output is provided or not. Set the DAiE bit to "1" (output enabled) to disable a pull-up of a corresponding port. Output analog voltage (V) is calculated from value n (n=decimal) set in the DAi register. V = VREF x n (n = 0 to 255) 256 VREF : reference voltage (not related to VCUT bit setting in the AD0CON1 register) Table 19.1 lists specifications of the D/A converter. Table 19.2 lists pin setting of the DA0 and DA1 pins. Figure 19.1 shows a block diagram of the D/A converter. Figure 19.2 shows the D/A control register. Figure 19.3 shows a D/A converter equivalent circuit. When the D/A converter is not used, set the DAi register to "0016" and the DAiE bit to "0" (output disabled). Table 19.1 D/A Converter Specifications Item D/A Conversion Method Resolution Analog Output Pin Table 19.2 Pin Settings Port P93 P94 Function PD9 DA0 output DA1 output Register(1) PD9_3=0 PD9_4=0 Bit and Setting PS3 Register(1) PS3_3=0 PS3_4=0 PSL3 Register PSL3_3=1 PSL3_4=1 Specification R-2R 8 bits 2 channels NOTES: 1. Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 265 of 495 M32C/84 Group (M32C/84, M32C/84T) 19. D/A Converter Low-Order Bits of Data Bus DA0 Register DA0E 0 R-2R Resistor Ladder 1 DA0 DA1 Register DA1E 0 R-2R Resistor Ladder 1 DA0E, DA1E: Bits in the DACON register DA1 Figure 19.1 D/A Converter Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 266 of 495 M32C/84 Group (M32C/84, M32C/84T) 19. D/A Converter D/A Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DACON Bit Symbol Address 039C16 After Reset XXXX XX002 Bit Name D/A0 Output Enable Bit Function 0 : Disables an output 1 : Enables an output 0 : Disables an output 1 : Enables an output RW RW DA0E DA1E D/A1 Output Enable Bit RW (b7 - b2) Nothing is assigned. When write, set to "0". When read, its content is indeterminate. D/A Register i (i=0, 1) b7 b0 Symbol DA0, DA1 Address 039816, 039A16 After Reset Indeterminate Function Output value of D/A conversion Setting Range 0016 to FF16 RW RW Figure 19.2 DACON Register, DA0 and DA1 Registers r DA0 DA0E "0" "1" 2R MSB R R R R R R R 2R 2R 2R 2R 2R 2R 2R 2R LSB D/A register 0 AVSS VREF(4) 0 1 NOTES: 1. The above applies when the DA0 register is set to "2A16". 2. This circuitry is the same for D/A1. 3. To reduce power consumption when the D/A converter is not used, set the DAiE bit (i=0, 1) to "0" (output disabled) and the DAi register to "0016" to stop current from flowing into the R-2R resistor. 4. VREF is not related to VCUT bit setting in the AD0CON1 register. Figure 19.3 D/A Converter Equivalent Circuit Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 267 of 495 M32C/84 Group (M32C/84, M32C/84T) 20. CRC Calculation 20. CRC Calculation The CRC (Cyclic Redundancy Check) calculation detects an error in data blocks. A generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) generates CRC code. The CRC code is a 16-bit code generated for a block of data of desired length. This block of data is in 8-bit units.The CRC code is set in the CRCD register every time one-byte data is transferred to the CRCIN register after a default value is written to the CRCD register. CRC code generation for one-byte data is completed in two cycles. Figure 20.1 shows a block diagram of a CRC circuit. Figure 20.2 shows associated registers. Figure 20.3 shows an example of the CRC calculation. High-order bits of data bus Low-order bits of data bus 8 low-order bits 8 highorder bits CRCD register CRC code generation circuit x16 + x12 + x5 + 1 CRCIN register Figure 20.1 CRC Calculation Block Diagram CRC Data Register b15 b8 b7 b0 Symbol CRCD Address 037D16- 037C16 After Reset Indeterminate Function After default value is written to the CRCD register, the CRC code can be read from the CRCD register by writing data to the CRCIN register. Bit position of the default value is inversed. The inversed value is read as the CRC code. Setting Range RW 000016 to FFFF16 RW CRC Input Register b7 b0 Symbol CRCIN Address 037E16 After Reset Indeterminate Function Data input. Inverse bit position of data. Setting Range 0016 to FF16 RW RW Figure 20.2 CRCD Register and CRCIN Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 268 of 495 M32C/84 Group (M32C/84, M32C/84T) 20. CRC Calculation CRC Calculation and Setup Procedure to Generate CRC Code for "80C416" CRC Calculation for M32C CRC Code : a remainder of a division, Generator Polynomial : X 16 value of the CRCIN register with inversed bit position generator polynomial +X 12 + X + 1 (1 0001 0000 0010 00012) 5 Setting Steps (1) Inverse a bit position of "80C416" per byte by program "8016" "0116", "C416" "2316" b15 b0 (2) Set "000016" (default value) b7 b0 CRCD register CRCIN register Bit position of the CRC code for "8016" (918816) is inversed to "118916", which is stored into the CRCD register in 3rd cycle. b15 b0 (3) Set "0116" 118916 b7 b0 CRCD register (4) Set "2316" CRCIN register Bit position of the CRC code for "80C416" (825016) is inversed to "0A4116", which is stored into the CRCD register in 3rd cycle. b15 b0 0A4116 CRCD register Details of CRC Calculation As shown in (3) above, bit position of "0116" (000000012) written to the CRCIN register is inversed and becomes "100000002". Add "1000 0000 0000 0000 0000 00002", as "100000002" plus 16 digits, to "000016" as the default value of the CRCD register to perform the modulo-2 division. 1000 1000 Modulo-2 Arithmetic is data 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 calculated on the law below. 1000 1000 0001 0000 1 0+0=0 1000 0001 0000 1000 0 0+1=1 Generator Polynomial 1000 1000 0001 0000 1 1+0=1 1001 0001 1000 1000 1+1=0 -1=1 CRC Code "0001 0001 1000 10012 (118916)", the remainder "1001 0001 1000 10002 (918816)" with inversed bit position, can be read from the CRCD register. When going on to (4) above, "2316 (001000112)" written in the CRCIN register is inversed and becomes "110001002". Add "1100 0100 0000 0000 0000 00002", as "110001002" plus 16 digits, to "1001 0001 1000 10002" as a remainder of (3) left in the CRCD register to perform the modulo-2 division. "0000 1010 0100 00012 (0A4116)", the remainder with inversed bit position, can be read from CRCD register. Figure 20.3 CRC Calculation Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 269 of 495 M32C/84 Group (M32C/84, M32C/84T) 21. X/Y Conversion 21. X/Y Conversion The X/Y conversion rotates a 16 x 16 matrix data by 90 degrees and inverses high-order bits and low-order bits of a 16-bit data. Figure 21.1 shows the XYC register. The 16-bit XiR register (i=0 to 15) and 16-bit YjR register (j=0 to 15) are allocated to the same address. The XiR register is a write-only register, while the YjR register is a read-only register. Access the XiR and YjR registers from an even address in 16-bit units. Performance cannot be guaranteed if the XiR and YiR registers are accessed in 8-bit units. X/Y Control Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol XYC Bit Symbol XYC0 Address 02E016 After Reset XXXX XX002 Bit Name Read Mode Set Bit Function 0 : Data conversion 1 : No data conversion 0 : No bit alignment conversion 1 : Bit alignment conversion RW RW XYC1 Write Mode Set Bit RW (b7 - b2) Noting is assigned. When write, set to "0". When read, its content is indeterminate. Figure 21.1 XYC Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 270 of 495 M32C/84 Group (M32C/84, M32C/84T) 21. X/Y Conversion The XYC0 bit in the XYC register determines how to read the YjR register. By reading the YjR register when the XYC0 bit is set to "0" (data conversion), bit j in the X0R to X15R registers can be read simultaneously. For example, bit 0 in the X0R register can be read if reading bit 0 in the Y0R register, bit 0 in the X1R register if reading bit 1 in the Y0R register..., bit 0 in the X14R register if reading bit 14 in the Y0R register and bit 0 in the X15R register if reading bit 15 in the Y0R register. Figure 21.2 shows the conversion table when the XYC0 bit is set to "0". Figure 21.3 shows an example of the X/Y conversion. Address to be read Y15R register Y14R register Y13R register Y12R register Y11R register Y10R register Y9R register Y8R register Y7R register Y6R register Y5R register Y4R register Y3R register Y2R register Y1R register Y0R register Address to be written b15 Bits in the XiR register b0 Figure 21.2 Conversion Table when Setting the XYC0 Bit to "0" b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 X0R register X1R register X2R register X3R register X4R register X5R register X6R register X7R register X8R register X9R register X10R register X11R register X12R register X13R register X14R register X15R register Y0R register Y1R register Y2R register Y3R register Y4R register Y5R register Y6R register Y7R register Y8R register Y9R register Y10R register Y11R register Y12R register Y13R register Y14R register Y15R register Figure 21.3 X/Y Conversion Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 271 of 495 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 X0R register X1R register X2R register X3R register X4R register X5R register X6R register X7R register X8R register X9R register X10R register X11R register X12R register X13R register X14R register X15R register b0 Bits in the YjR register M32C/84 Group (M32C/84, M32C/84T) 21. X/Y Conversion By reading the YjR register when the XYC0 bit in the XYC register is set to "1" (no data conversion), the value written to the XiR register can be read directly. Figure 21.4 shows the conversion table when the XYC0 bit is set to "1." Address to be written Address to be read X0R register, Y0R register X1R register, Y1R register X2R register, Y2R register X3R register, Y3R register X4R register, Y4R register X5R register, Y5R register X6R register, Y6R register X7R register, Y7R register X8R register, Y8R register X9R register, Y9R register X10R register, Y10R register X11R register, Y11R register X12R register, Y12R register X13R register, Y13R register X14R register, Y14R register X15R register, Y15R register b15 Bits in the XiR register Bits in the YjR register b0 i=0 to 15 j=0 to 15 Figure 21.4 Conversion Table when Setting the XYC0 Bit to "1" The XYC1 bit in the XYC register selects bit alignment of the value in the XiR register. By writing to the XiR register while the XYC1 bit is set to "0" (no bit alignment conversion), bit alignment is written as is. By writing to the XiR register while the XYC1 bit is set to "1" (bit sequence replaced), bit alignment is written inversed. Figure 21.5 shows the conversion table when the XYC1 bit is set to "1". b15 b0 Data to be written b15 b0 Bits in XiR register (i=0 to 15) Figure 21.5 Conversion Table when Setting the XYC1 Bit to "1" Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 272 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O 22. Intelligent I/O The intelligent I/O is a multifunctional I/O port for time measurement, waveform generating, clock synchronous serial I/O, clock asynchronous serial I/O (UART), HDLC data processing and more. The intelligent I/O has one 16-bit base timer for free-running operation, eight 16-bit registers for time measurement and waveform generating and two sets of two 8-bit shift registers for communications. Table 22.1 lists functions and channels of the intelligent I/O. Table 22.1 Intelligent I/O Functions and Channels Function Time Measurement(1) 8 channels 8 channels 2 channels (channel 6 and channel 7) 2 channels (channel 6 and channel 7) 8 channels 8 channels Description Digital Filter Trigger Input Prescaler Trigger Input Gate Waveform Generating(1) Single-Phase Waveform Output Mode Phase-Delayed Waveform Output Mode 8 channels SR Waveform Output Mode Communication Clock Synchronous Serial I/O Mode UART Mode HDLC Data Processing Mode NOTES: 1. The time measurement function and the waveform generating function share a pin. 8 channels Communication unit 0 Available Not Available Available Available Communication unit 1 The time measurement function and waveform generating function can be selected for each channel. The communication function is available by a combining multiple channels. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 273 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O Figures 22.1 shows a block diagram of the intelligent I/O. Figure 22.2 shows a block diagram of the intelligent I/O communication. Overflow of bit 15 in the base timer Overflow of bit 9 in the base timer 0 1 BTRE Request by matching the base timer with the G1PO0 register Base timer reset in the communication unit 1 Request from the INT pin BTS f1 Two-phase pulse signal is applied 11 10 BCK1 and BCK0 00 10 : fBT1 Digital 11 : f1 Filter DF1 and DF0 10 : fBT1 00 Digital 11 : f1 Filter DF1 and DF0 00 10 : fBT1 Digital 11 : f1 Filter DF1 and DF0 00 10 : fBT1 Digital 11 : f1 Filter DF1 and DF0 00 10 : fBT1 Digital 11 : f1 Filter DF1 and DF0 00 10 : fBT1 Digital 11 : f1 Filter DF1 and DF0 Divider 2(n+1) DIV4 to DIV0 Edge Select CTS1 and CTS0 Edge Select CTS1 and CTS0 Edge Select CTS1 and CTS0 Edge Select CTS1 and CTS0 Edge Select CTS1 and CTS0 Edge Select CTS1 and CTS0 fBT1 Base Timer INPC10 G1TM0, G1PO0 Register(1) PWM Output G1TM1, G1PO1 Register(1) G1TM2, G1PO2 Register(1) PWM Output G1TM3, G1PO3 Register(1) G1TM4, G1PO4 Register(1) PWM Output G1TM5, G1PO5 Register(1) 0 000 to 010 MOD2 to MOD0 OUTC10/ISTxD1 /BE1OUT 111 INPC11 / ISCLK1 INPC12 / ISRxD1 000 to 010 111 MOD2 to MOD0 OUTC11/ISCLK1 OUTC12 INPC13 OUTC13 INPC14 OUTC14 INPC15 OUTC15 INPC16 INPC17 00 0 10 : fBT1 Edge Gate Digital 11 : f1 Select Function 1 Filter DF1 and DF0 GT CTS1 and CTS0 00 0 10 : fBT1 Gate Digital 11 : f1 Edge Function 1 Filter Select DF1 and DF0 GT CTS1 and CTS0 Prescaler Function 1 PR 0 G1TM6, G1PO6 Register(1) PWM Output OUTC16 Prescaler Function 1 PR G1TM7, G1PO7 Register(1) OUTC17 Ch0 to Ch7 interrupt request signal ISCLK0 ISRxD0 Communication Unit 0 ISTxD0 Communication Unit 1 f1 f8 f2n NOTES: 1. Each register is placed in a reset state after the G1BCR0 register supplies the clock. DIV4 to DIV0 bits, BCK1 and BCK0 bits : Bits in the G1BCR0 Register BTS : Bit in the G1BCR1 Register CTS1 and CTS0, DF1 and DF0, GT, PR : Bits in the G1TMCRj Register (j = 0 to 7) MOD2 to MOD0 : Bits in the G1POCRj Register BTRE : Bit in the G1POCR0 Register Figure 22.1 Intelligent I/O Block Diagram Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 274 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O Communication Unit 0 ISRxD0 ISCLK0 CCS1 and CCS0 f1 f2n f8 01 10 11 Transmit Interrupt Request SIO0TR(2) G0TB Register (Transmit Buffer Register) Transmit Buffer Transmit Register SOF Generation Circuit Transmit Data Generation Circuit Transmission Bit Insert Circuit G0TCRC Register Transmit Latch Data Selector 1 TXSL 0 ISTxD0 G0TO Register Clock Wait Control Circuit Transmit CKDIR Operation 0 Clock 1 Transmit Register Transmit Buffer HDLC Data Transmit Interrupt Request G0TOR(2) Receive Operation Clock Reception Arbitration G0RI Register Receive Buffer Receive Register 1 G0RCRC Register Receive Data Generation Circuit 0 Bit Insert Check Data Selector G0RB Register Receive Buffer Receive Interrupt Request SIO0RR(2) RXSL G0DR Register (Receive Data Register) Shift Register Buffer Register Receive Register Special Interrupt Check Comparator Comparator Comparator Comparator Special Communication Interrupt Request SRT0R(2) G0CMP0 register G0CMP0 register G0CMP0 register G0CMP3 Register HDLC Data Receive Interrupt Request G0RIR(2) Communication Unit 1 SOF Generation Circuit Transmit Data Generation Circuit Transmission Transmit Interrupt Request SIO1TR(2) G1TB Register (Transmit Buffer Register) Transmit Buffer Transmit Register Bit Insert Circuit G1TCRC Register Transmit Latch Data Selector 1 TXSL 0 Generated Clock in the Channel i (i=1 to 3) CCS3 and CCS2 00 01 10 11 0 Polarity Inverse ISTxD1 f1 f2n f8 ISCLK1 ISRxD1 Clock Wait Control Circuit Start Bit Generation Circuit Stop Bit Generation Circuit G1TO Register Transmit Register Transmit Buffer Transmit Operation Clock CKDIR Receive Operation Clock HDLC Data Transmit Interrupt Request G1TOR(2) 1 Arbitration G1RI Register Receive Buffer Receive Register 1 Reception G1RCRC Register Receive Data Generation Circuit Data Selector G1RB Register Receive Buffer 0 Bit Insert Check Polarity Inverse RXSL G1DR Register (Receive Data Register) Shift Register Buffer Register Start Bit Check Receive Interrupt Request SIO1RR(2) Receive Register Stop Bit Check Special Interrupt Check Special Communication Interrupt Request SRT1R(2) G1CMP0 Register G1CMP0 Register (8bit) G1CMP0 Register (8bit) (8bit) G1CMP3 Register Comparator Comparator (8bit) Comparator (8bit) (8bit) Comparator HDLC Data Receive Interrupt Request G1RIR(2) NOTES: 1. Each register enters after the G1BCR0 register supplies the clock. 2. See Figure 11.14. CKDIR : Bit in the GiMR Register (i=0,1) TXSL, RXSL : Bits in the GiEMR Register CCS1 and CCS0 : Bits in the CCS Register Figure 22.2 Intelligent I/O Communication Block Diagram Page 275 of 495 Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O Figures 22.3 to 22.8 show registers associated with the intelligent I/O base timer, the time measurement function and waveform generating function. (For registers associated with the communication function, see Figures 22.19 to 22.28.) Base Timer Register 1(2) b15 b8 b7 b0 Symbol G1BT Address 012116 - 012016 After Reset Indeterminate Function When the base timer is counting: When read, the value of the base timer can be read. When write, the counter starts counting from the value written. When the base timer is reset, the G1BT register is set to "000016"(1). When the base timer is reset: The G1BT register is set to "000016" but value is indeterminate. No value is written(1). Setting Range RW 000016 to FFFF16 RW NOTES: 1. The base timer stops only when the BCK1 and BCK0 bits in the G1BCR0 register are set to "002" (clock stopped). The base timer counts when the BCK1 and BCK0 bits are set to a value other than "002". When the BTS bit in the G1BCR1 register is set to "0", the base timer is reset continually, remaining set to "000016". This, in effect, places the base timer in a "no counting" state. When the BTS bit is set to "1", this state is cleared and counting starts. 2. The G1BT register reflects the value of the base timer, with a delay of one half fBT1 cycle. Base Timer Control Register 10 b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1BCR0 Address 012216 After Reset 0016 Bit Symbol BCK0 Bit Name b1 b0 Function 0 0 1 1 RW Count Source Select Bit BCK1 RW 0 : Clock stops 1 : Do not set to this value 0 : Two-phase pulse signal is applied(1) RW 1 : f1 RW DIV0 If setting value is n (n = 0 to 31), count source is divided by 2(n + 1). No division if n=31. b6 b5 b4 b3 b2 DIV1 Count Source Divide Ratio Select Bit (n=0) 0 0 0 0 0 : Divide-by-2 (n=1) 0 0 0 0 1 : Divide-by-4 (n=2) 0 0 0 1 0 : Divide-by-6 (n=30) 1 1 1 1 0 : Divide-by-62 (n=31) 1 1 1 1 1 : No division RW DIV2 RW DIV3 RW DIV4 Base Timer Interrupt Select Bit 0 : Bit 15 overflows 1 : Bit 14 overflows RW IT RW NOTES: 1. This setting can be used only when the UD1 and UD0 bits in the G1BCR1 register are set to "102" (two-phase signal processing mode). Do not set the BCK1 and BCK0 bits to "102" in other modes. Figure 22.3 G1BT Register and G1BCR0 Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 276 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O Base Timer Control Register 11 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address 012316 After Reset X000 000X2 0 G1BCR1 Bit Symbol (b0) Bit Name Function RW Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Base Timer Reset Cause Select Bit 1 0: The base timer is not reset by matching with the G1PO0 register 1: The base timer is reset by matching with the G1PO0 register(1) 0: The base timer is not reset by applying "L" to the INT0 or INT1 pin 1: The base timer is reset by applying "L" to the INT0 or INT1 pin(2) Set to "0" 0: Base timer is reset 1: Base timer starts counting b6 b5 RST1 RW RST2 Base Timer Reset Cause Select Bit 2 RW Reserved Bit (b3) BTS Base Timer Start Bit RW RW UD0 UD1 RW 0 0 : Counter increment mode 0 1 : Counter increment/decrement mode Counter Increment/ Decrement Control Bit 1 0 : Two-phase pulse signal processing mode(3) RW 1 1 : Do not set to this value Nothing is assigned. When write, set to "0". When read, its content is indeterminate. (b7) NOTES: 1. The base timer is reset two fBT1 clock cycles after the base timer matches the value set in the G1PO0 register. (See Figure 22.7 for details on the G1PO0 register.) When the RST1 bit is set to "1", the value of the G1POj register (j=1 to 7) for the waveform generating function and communication function must be set to a value smaller than that of the G1PO0 register. 2. The IPSA_0 bit in the IPSA register can select the INT0 or INT1 pin. 3. In two-phase pulse signal processing mode, the base timer is not reset, even when the RST1 bit is set to "1", if the counter is decremented two clock cycles after the base timer matches the value set in the G1PO0 register. Figure 22.4 G1BCR1 Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 277 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O Time Measurement Control Register 1j (j=0 to 7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1TMCR0 to G1TMCR3 G1TMCR4 to G1TMCR7 Address 011816, 011916, 011A16, 011B16 011C16, 011D16, 011E16, 011F16 After Reset 0016 0016 Bit Symbol CTS0 Bit Name b1 b0 Function 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 : No time measurement : Rising edge : Falling edge : Both edges : No digital filter : Do not set to this value : fBT1 : f1 RW RW Time Measurement Trigger Select Bit CTS1 RW b3 b2 DF0 Digital Filter Function Select Bit DF1 Gate Function Select Bit(1) Gate Function Clear Select Bit(1, 2, 3) Gate Function Clear Bit(1, 2) Prescaler Function Select Bit(1) RW RW GT 0 : Gate function is not used 1 : Gate function is used RW GOC 0 : Not cleared 1 : The gate is cleared when the base RW timer matches the GiPOk register The gate is cleared by setting the GSC bit to "1" 0 : Not used 1 : Used RW GSC PR RW NOTES: 1. These bits are in the G1TMCR6 and G1TMCR7 registers. Set all bits 7 to 4 in the G1TMCR0 to G1TMCR5 registers to "0". 2. These bits are enabled only when the GT bit is set to "1". 3. The GOC bit is set to "0" after the gate function is cleared. See Figure 22.7 about the G1POk register (k=4 when j=6 and k=5 when j=7). Time Measurement Prescaler Register 1j (j=6,7) b7 b0 Symbol G1TPR6, G1TPR7 Address 012416, 012516 After Reset 0016 Function If the setting value is n, the base timer value is stored into G1TMj register whenever a trigger input is counted by n+1(1) Setting Range 0016 to FF16 RW RW NOTES: 1. The first prescaler, after the PR bit in the G1TMCRj register is changed from "0" (prescaler function used) to "1" (prescaler function not used), may be divided by n rather than n+1. The subsequent prescaler is divided by n+1. Figure 22.5 G1TMCR0 to G1TMCR7 Registers, G1TPR6 and G1TPR7 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 278 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O Time Measurement Register 1j (j=0 to 7) b15 b8 b7 b0 Symbol G1TM0 to G1TM2 G1TM3 to G1TM5 G1TM6, G1TM7 Address 010116 - 010016, 010316 - 010216, 010516 - 010416 010716 - 010616, 010916 - 010816, 010B16 - 010A16 010D16 - 010C16, 010F16 - 010E16 After Reset Indeterminate Indeterminate Indeterminate Function The base timer value is stored every measurement timing Setting Range RW RO Waveform Generating Control Register 1j (j=0 to 7) b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1POCR0 G1POCR1 to G1POCR3 G1POCR4 to G1POCR7 Address 011016 011116, 011216, 011316 011416, 011516, 011616, 011716 After Reset 0000 X0002 0X00 X0002 0X00 X0002 Bit Symbol MOD0 Bit Name b2 b1b0 Function RW MOD1 Operating Mode Select Bit MOD2 0 0 0 : Single waveform output mode RW 0 0 1 : SR waveform output mode(1) 0 1 0 : Phase-delayed waveform output mode 0 1 1 : Do not set to this value RW 1 0 0 : Do not set to this value 1 0 1 : Do not set to this value 1 1 0 : Do not set to this value(2) 1 1 1 : Use communication function RW output(3) (b3) IVL Nothing is assigned. When write, set to "0". When read, its content is indeterminate. Output Initial Value Select Bit(6) 0: "L" output as default value 1: "H" output as default value RW RLD BTRE 0: Reloads the G1POj register when G1POj Register Value value is written RW Reload Timing Select Bit 1: Reloads the G1POj register when the base timer is reset 0: Disables base timer reset when Base Timer Reset Enable bit 15 in the base timer overflows RW 1: Enables base timer reset when Bit(4) bit 9 in the base timer overflows(7) Inverse Output Function Select Bit(5) 0: Output is not inversed 1: Output is inversed RW INV NOTES: 1. This setting is enabled only for even channels. In SR waveform output mode, values written to the corresponding odd channel (next channel after an even channel) are ignored. Even channels provides waveform output. Odd channels provides no waveform output. 2. To receive data in UART mode, set the G1POCR2 register to "0000 01102". 3. This setting is enabled only for channels 0 and 1. To use the ISTxD1 pin, set the MOD2 to MOD0 bits in the G1POCR0 register to "1112". To use the ISCLK1 pin for an output, set the MOD2 to MOD0 bits in the G1POCR1 register to"1112". Do not set the MOD2 to MOD0 bits to "1112" except in channels 0 and 1 and for the communication function. 4. The BTRE bit is provided in the G1POCR0 register only. Set each bit 6 in the G1POCR1 to G1POCR7 registers to "0". 5. The inverse output function is the final step in waveform generating process. When the INV bit is set to "1", an "H" signal is provided a default output by setting the IVL bit to "0"; and an "L" signal is provided by setting it to "1". 6. To provide either "H" or "L" signal output set in the IVL bit, set the FSCj bit in the G1FS register to "0" (the time measurement function selected) and IFEj bit in the G1FE register to "1" (functions for channel j enabled). Then set the IVL bit to "0" or "1". 7. When the BTRE bit is set to "1", set the BCK1 and BCK0 bits in the G1BCR0 register to "112" (f1) and the UD1 and UD0 bits in the G1BCR1 register to "002" (counter increment mode). Figure 22.6 G1TM0 to G1TM7 Registers and G1POCR0 to G1POCR7 Registers Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 279 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O Waveform Generating Register 1j (j=0 to 7) b15 b8 b7 b0 Symbol G1PO0 to G1PO2 G1PO3 to G1PO5 G1PO6 to G1PO7 Address After Reset 010116-010016, 010316-010216, 010516-010416 Indeterminate 010716-010616, 010916-010816, 010B16-010A16 Indeterminate 010D16-010C16, 010F16-010E16 Indeterminate Function • When the RLD bit in the G1POCRj register is set to "0", value written is immediately reloaded into the G1POj register for output, for example, a waveform output, reflecting the value. • When the RLD bit is set to "1", the value is reloaded when the base timer is reset. The value written can be read until reloading. Setting Range RW 000016 to FFFF16 RW Function Select Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address 012716 After Reset 0016 G1FS Bit Symbol FSC0 Bit Name Function RW FSC1 Channel 0 Time Measure- 0 : Selects the waveform generating ment/Waveform Generating RW function Function Select Bit 1 : Selects the time measurement function Channel 1 Time Measurement/Waveform Generating RW Function Select Bit Channel 2 Time Measurement/Waveform Generating Function Select Bit Channel 3 Time Measurement/Waveform Generating Function Select Bit Channel 4 Time Measurement/Waveform Generating Function Select Bit Channel 5 Time Measurement/Waveform Generating Function Select Bit Channel 6 Time Measurement/Waveform Generating Function Select Bit Channel 7 Time Measurement/Waveform Generating Function Select Bit RW FSC2 FSC3 RW FSC4 RW FSC5 RW FSC6 RW FSC7 RW Figure 22.7 G1PO0 to G1PO7 Registers and G1FS Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 280 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O Function Enable Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol G1FE Bit Symbol IFE0 IFE1 IFE2 IFE3 IFE4 IFE5 IFE6 IFE7 Address 012616 After Reset 0016 Bit Name Function RW Channel 0 Function Enable Bit 0 : Disables functions for channel j RW Channel 1 Function Enable Bit 1 : Enables functions for channel j RW (j=0 to 7) Channel 2 Function Enable Bit RW Channel 3 Function Enable Bit Channel 4 Function Enable Bit Channel 5 Function Enable Bit Channel 6 Function Enable Bit Channel 7 Function Enable Bit RW RW RW RW RW Figure 22.8 G1FE Register Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 281 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Base Timer) 22.1 Base Timer The base timer is a free-running counter that counts an internally generated count source. Table 22.2 lists specifications of the base timer. Figures 22.3 and 22.4 show registers associated with the base timer. Figure 22.9 shows a block diagram of the base timer. Figure 22.10 shows an example of the base timer in counter increment mode. Figure 22.11 shows an example of the base timer in counter increment/decrement mode. Figure 22.12 shows an example of two-phase pulse signal processing mode. Table 22.2 Base Timer Specifications Item Count Source (fBT1) Specification f1 divided by 2(n+1) , two-phase pulse input divided by 2(n+1) n: determined by the DIV4 to DIV0 bits in the G1BCR0 register n=0 to 31; however no division when n=31 Counting Operation The base timer increments the counter value The base timer increments and decrements the counter value Two-phase pulse signal processing Counter Start Condition Counter Stop Condition Base Timer Reset Condition The BTS bit in the G1BCR1 register is set to "1" (base timer starts counting) The BTS bit in the G1BCR1 register is set to "0" (base timer reset) • The value of the base timer matches the value of the G1PO0 register ________ _______ • An low-level ("L") signal is applied to the INT0 or INT1 pin • Bit 15 or bit 9 in the base timer overflows Value when the Base Timer is Reset Interrupt Request Read from Base Timer Write to Base Timer "000016" The BT1R bit in the IIO4IR register is set to "1" (interrupt requested) when bit 9, bit 14 or bit 15 in the base timer overflows (See Figure 11.14.) • The G1BT register indicates the counter value while the base timer is running • The G1BT register is indeterminate when the base timer is reset When a value is written while the base timer is running, the timer counter immediately starts counting from this value. No value can be written while the base timer is reset • Counter increment/decrement mode The base timer starts counting when the BTS bit is set to "1". After incrementing to "FFFF16", the timer counter is then decremented back to "000016". If the RST1 bit in the G1BCR1 register is set to "1" (the base timer is reset by matching with the G1PO0 register), the timer counter decrements two counts after the base timer matches the G1PO0 register. The base timer increments the counter value again when the timer counter reaches "000016." (See Figure 22.11.) • Two-phase pulse processing mode Two-phase pulse signals from P76 and P77 pins or P80 and P81 pins are counted as well. (See Figure 22.12.) The IPSA_0 bit in the IPSA register controls input pin selection. (Refer to 24. Programmable I/O Ports) Selectable Function P80 (P76) P81 (P77) The timer increments counter on all edge The timer decrements counter on all edges Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 282 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Base Timer) BCK1 to BCK0 fBT1 2(n+1) Divider f1 Apply the Two-Phase Pulse Signal Base Timer b9 b14 b15 1 11 10 Overflow Signal BTRE Base Timer Interrupt Request (See the BT1R bit on Figure 11.14) 0 0 1 IT BTS Bit RST1 Matching with the G1PO0 Register RST2 Apply "L" to the INTi Pin Base Timer Reset (i=0,1) BCK1 and BCK0, IT : Bits in the G1BCR0 register RST2 to RST0, BTS : Bits in the G1BCR1 register BTRE : Bit in the G1POCR0 register Figure 22.9 Base Timer Block Diagram Table 22.3 Base Timer Associated Register Settings (Also applies when using time measurement function, waveform generating function and communication function) Register G1BCR0 Bit BCK1, BCK0 DIV4 to DIV0 IT RST2, RST1 BTS UD1, UD0 BTRE Function Select count source Select divide ratio of count source Select the base timer interrupt Select source for a base timer reset Used to start the base timer independently Select how to count Select source for a base timer reset Read or write base timer value G1BCR1 G1POCR0 G1BT Set the following registers to set the RST1 bit to "1" (base timer reset by matching the base timer with the G1PO0 register). G1POCR0 MOD2 to MOD0 Set to "0002" (single-phase waveform output mode) G1PO0 G1FS G1FE FSC0 IFE0 Set reset cycle Set to "0" (waveform generating function) Set to "1" (channel operation start) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 283 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Base Timer) (1) When the IT bit in the G1BCR0 register is set to "0" (bit 15 in the base timer overflows) FFFF16 Base Timer 800016 000016 Bit 15 Overflow Signal BT1R bit in IIO4IR register "1" "0" "1" "0" Write "0" by program if setting to "0" The above applies to the following conditions: • The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register) • The UD1 and UD0 bits in the G1BCR1 register are set to "002" (counter increment mode) (2) When the IT bit is set to "1" (bit 14 in the base timer overflows) FFFF16 C00016 Base Timer 800016 400016 000016 Bit 14 Overflow Signal BT1R bit in IIO4IR register "1" "0" "1" "0" Write "0" by program if setting to "0" The above applies to the following conditions: • The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register) • The UD1 and UD0 bits in the G1BCR1 register are set to "002" (counter increment mode) Figure 22.10 Counter Increment Mode Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 284 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Base Timer) (1) When the IT bit in the G1BCR0 register is set to "0" (bit 15 in the base timer overflows) FFFF16 Base Timer 800016 Bit 15 Overflow Signal BT1R bit in IIO4IR register "1" "0" "1" "0" Write "0" by program if setting to "0" The above applies to the following conditions: • The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register) • The UD1 and UD0 bits in the G1BCR1 register are set to "012" (counter increment/decrement mode) (2) When the IT bit is set to "1" (bit 14 in the base timer overflows) FFFF16 C00016 Base Timer 800016 400016 000016 Bit 14 Overflow Signal BT1R bit in IIO4IR register "1" "0" "1" "0" Write "0" by program if setting to "0" The above applies to the following conditions: • The RST1 in the G1BCR1 register is set to "0" (the base timer is not reset by matching the G1PO0 register) • The UD1 and UD0 bits in the G1BCR1 register are set to "012" (counter increment/decrement mode) (3) When the RST1 bit in the G1BCR1 register is set to "1" (the base timer is reset by matching with the G1PO0 register) 800216 800016 Base Timer 000016 The above applies to the following conditions: • Value of G1PO0 register: "800016" • The UD1 and UD0 bits in the G1BCR1 register are set to "012" (counter increment/decrement mode) Figure 22.11 Counter Increment/Decrement Mode Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 285 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Base Timer) (1) When the base timer is reset while the base timer increments the counter value P80 (P76)(2) "H" (A-phase) "L" P81 (P77)(2) "H" (B-phase) "L" fBT1 "H" min 1 µs min 1 µs Input Waveform ( When selects no division "L" with the divider by 2(n+1) ) INT1 "H" (Z-phase) "L" (Note 1) The base timer starts counting Base TImer m m+1 0 1 2 Set to "0" in this timing Set to "1" in this timing (2) When the base timer is reset while the base timer decrements the counter value P80 (P76)(2) (A-phase) "H" Input Waveform "L" P81 (P77)(2) (B-phase) "H" "L" fBT1 min 1 µs min 1 µs ( When selects no division "H" with the divider by 2(n+1) ) "L" "L" INT1 (Z-phase) "H" (Note 1) The base timer starts counting Base TImer m m-1 0 FFFF16 FFFE16 Set to "FFFF16" in this timing Set to "0" in this timing NOTES: 1. 1.5 fBT1 clock cycles or more are required. 2. Select either port by setting the IPSA_0 bit in the IPSA register. Figure 22.12 Base Timer Operation in Two-phase Pulse Signal Processing Mode Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 286 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Time Measurement Function) 22.2 Time Measurement Function When external trigger is applied, the value of the base timer is stored into the G1TMj register (j=0 to 7). Table 22.4 shows specifications of the time measurement function. Tables 22.5 and 22.6 list pin settings of the time measurement function. Figures 22.13 and 22.14 show operation examples of the time measurement function. Figure 22.15 shows an operation example of the prescaler function and gate function. Table 22.4 Time Measurement Function Specifications Item Measurement Channel Trigger Input Polarity Measurement Start Condition Channels 0 to 7 Rising edge, falling edge and both edges of the INPC1j pin The IFEj bit in the G1FE register is set to "1" (channel j function enabled) when the FSCj bit (j=0 to 7) in the G1FS register is set to "1" (time measurement function selected) Measurement Stop Condition Time Measurement Timing The IFEj bit is set to "0" (channel j function disabled) • No prescaler: every time a trigger signal is applied • Prescaler (for channel 6 and channel 7): every G1TPRk register (k=6,7) value +1 times a trigger signal is applied Interrupt Request Generating Timing INPC1j Pin Function Selectable Function The TM1jR bit in the interrupt request register (See Figure 11.14) is set to "1" (interrupt requested) at time measurement timing Trigger input pin • Digital filter function The digital filter samples a trigger input signal level every f1 or fBT1 cycles and passes pulse signals, matching trigger input signal level, three times • Prescaler function (for channel 6 and channel 7) Time measurement is executed every G1TPRk register value +1 times a trigger signal is applied • Gate function (for channel 6 and channel 7) After time measurement by the first trigger input, trigger input cannot be accepted. However, while the GOC bit in the G1TMCRk register is set to "1" (gate cleared by matching the base timer with the G1POp register (p=4 when k=6, p=5 when k=7), trigger input can be accepted again by matching the base timer value with the G1POp register setting or by setting the GSC bit in the G1TMCRk register is set to "1" Specification Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 287 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Time Measurement Function) Table 22.5 Pin Settings for Time Measurement Function Pin Bit and Setting PS1, PS2, PS5, PS8 Registers PD7, PD8, PD11, PD14 Registers P70/INPC16 P71/INPC17 P73/INPC10 P74/INPC11 P75/INPC12 P76/INPC13 P77/INPC14 P81/INPC15 P110/INPC10(1) P111/INPC11(1) P112/INPC12(1) P113/INPC13(1) P140/INPC14(1) P141/INPC15(1) P142/INPC16(1) P143/INPC17(1) NOTES: 1. This port is provided in the 144-pin package only. PS1_0 = 0 PS1_1 = 0 PS1_3 = 0 PS1_4 = 0 PS1_5 = 0 PS1_6 = 0 PS1_7 = 0 PS2_1 = 0 PS5_0 = 0 PS5_1 = 0 PS5_2 = 0 PS5_3 = 0 PS8_0 = 0 PS8_1 = 0 PS8_2 = 0 PS8_3 = 0 PD7_0 = 0 PD7_1 = 0 PD7_3 = 0 PD7_4 = 0 PD7_5 = 0 PD7_6 = 0 PD7_7 = 0 PD8_1 = 0 PD11_0 = 0 PD11_1 = 0 PD11_2 = 0 PD11_3 = 0 PD14_0 = 0 PD14_1 = 0 PD14_2 = 0 PD14_3 = 0 IPS1 = 1 IPS Register IPS1 = 0 Table 22.6 Time Measurement Function Associated Register Settings Register G1TMCRj Bit CTS1, CTS0 DF1, DF0 GT, GOC, GSC PR G1TPRk G1FS G1FE j = 0 to 7 FSCj IFEj k = 6, 7 Function Select a time measurement trigger Select the digital filter function Select the gate function Select the prescaler function Setting value of the prescaler Set to "1" (time measurement function) Set to "1" (channel j function enabled) Bit configurations and functions vary with channels used. Registers associated with the time measurement function must be set after setting registers associated with the base timer. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 288 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Time Measurement Function) Signal Applied to the INPC1j Pin "H" "L" FFFF16 n Base Timer p m 000016 G1TMj Register TM1jR Bit in the IIOiIR Register "1" "0" i= 0 to 4, 8 to 10 j= 0 to 7 m n p Write "0" by program if setting to "0" The above applies to the following conditions: The CTS1 and CTS0 bits in the G1TMCRj registers are set to "012" (rising edge). The PR bit is set to "0" (no prescaler used) and the GT bit is set to "0" (no gate function used). The RST2 and RST1 bits in the G1BCR1 register are set to "002" (no base timer reset). The UD1 and UD0 bits are set to "002" (counter increment mode). To set the base timer to "000016" (setting the RST1 bit to "1" and the RST2 bit to "0") when the base timer value matches the G1PO0 register setting, the base timer is set to "000016" after it reaches the G1PO0 register value +2. Figure 22.13 Time Measurement Function (1) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 289 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Time Measurement Function) (1) When selecting the rising edge as a time measurement trigger (The CTS1 and CTS0 bits in the G1TMCRj register (j=0 to 7) are set to "012") fBT1 Base timer n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 (Note 2) INPC1j pin "H" "L" "1" TM1jR bit(1) "0" Delayed by max. 1 clock Write "0" by program if setting to "0" n+5 n+8 G1TMj register n NOTES: 1. Bits in the IIO0IR to IIO8IR, IIO10IR to IIO11R registers. See Figure 11.14 about the TM1jR bit. 2. Input pulse applied to the INPC1j pin requires 1.5 fBT1 clock cycles or more. (2) When selecting both edges as a time measurement trigger (The CTS1 and CTS0 bits are set to "112") fBT1 Base timer "H" n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 INPC1j pin "L" (Note 2) "1" TM1jR bit(1) "0" Write "0" by program if setting to "0" G1TMj register n n+2 n+5 n+6 n+8 n+12 NOTES: 1. Bits in the IIO0IR to IIO4IR, IIO08IR to IIO10R registers. See Figure 11.14 about the TM1jR bit. 2. No interrupt is generated if the microcomputer receives a trigger signal when the TM1jR bit is set to "1". However, the value of the G1TMj register changes. (3) Trigger signal when using the digital filter (The DF1 and DF0 bits in the G1TMCRj register are set to "102" or "112") f1 or fBT1(1) "H" INPC1j pin Trigger signal after passing the digital filter "L" "H" "L" Signal, which does not match three times, is stripped off Maximum 3.5 f1 or fBT1(1) clock cycles The trigger signal is delayed by the digital filter NOTES: 1. fBT1 when the DF1 and DF0 bits are set to "102", and f1 when to "112". Figure 22.14 Time Measurement Function (2) Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 290 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Time Measurement Function) (a) With the prescaler function (When the G1TPRj register (j=6, 7) is set to "0216", the PR bit in the G1TMCRj register is set to "1") fBT1 Base Timer n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14 INPC1j pin input "H" "L" "H" Internal time measurement trigger "L" Prescaler(1) "1" "0" n n+12 0 2 Write "0" by program if setting to "0" 1 0 2 TM1jR bit(2) G1TMj register NOTES: 1. This applies to cycles following the first cycle the G1TPRj register decrements after the PR bit in the G1TMCRj register is set to "1" (prescaler used). 2. Bits in the IIO0IR to IIO4IR, IIO8IR to IIO10IR registers. See Figure 11.14 for the TM1jR bit. (b) With the gate function (The gate function is cleared by matching the base timer with the G1POk register (k=4, 5). the GT bit in the G1TMCRj register is set to "1", the GOC bit is set to "1") fBT1 FFFF16 Base Timer 000016 Value of the G1POk register IFEj bit in G1FE register "1" "0" "H" "L" This trigger input is disabled due to the gate function INPC1j pin input Internal time "H" measurement trigger "L" Signal to match G1POk register Gate control signal "H" "L" "H" "L" "1" "0" G1TMj register Gate Gate cleared Gate TM1jR bit(1) Write "0" by program if setting to "0" NOTES: 1. Bits in the IIO0IR to IIO4IR, IIO8IR to IIO10IR registers. See Figure 11.14 for the TM1jR bit. Figure 22.15 Prescaler Function and Gate Function Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 291 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Waveform Generating Function) 22.3 Waveform Generating Function Waveforms are generated when the value of the base timer matches that of the G1POj register (j=0 to 7). The waveform generating function has the following three modes : • Single-phase waveform output mode • Phase-delayed waveform output mode • Set/Reset waveform output (SR waveform output) mode Table 22.7 lists pin settings of the waveform generating function. Table 22.8 lists registers associated with the waveform generating function. Table 22.7 Pin Settings for Waveform Generating Function Pin PS1, PS2, PS5 to PS8 Registers P70/OUTC16 P71/OUTC17 P73/OUTC10 P74/OUTC11 P75/OUTC12 P76/OUTC13 P77/OUTC14 P81/OUTC15 P110/OUTC10(1) PS1_0 = 1 PS1_1 = 1 PS1_3 = 1 PS1_4 = 1 PS1_5 = 1 PS1_6 = 1 PS1_7 = 1 PS2_1 = 1 PS5_0 = 1 Bit and Setting PSL1, PSL2 Registers PSC, PSC2 Registers PSD1 Register PSL1_0 = 0 PSL1_1 = 0 PSL1_3 = 0 PSL1_4 = 0 PSL1_5 = 1 PSL1_6 = 0 PSL1_7 = 1 PSL2_1 = 1 - PSC_0 = 1 PSC_1 = 1 PSC_3 = 1 PSC_4 = 1 PSC_6 = 0 PSC2_1=1 - PSD1_0=1 PSD1_1=1 PSD1_6=1 - P111/OUTC11(1) PS5_1 = 1 P112/OUTC12(1) PS5_2 = 1 P113/OUTC13(1) PS5_3 = 1 P140/OUTC14(1) PS8_0 = 1 P141/OUTC15(1) PS8_1 = 1 P142/OUTC16(1) PS8_2 = 1 P143/OUTC17(1) PS8_3 = 1 NOTES: 1. This port is provided in the 144-pin package only. Table 22.8 Waveform Generating Function Associated Register Settings Register G1POCRj Bit MOD2 to MOD0 IVL RLD INV FSCj IFEj Function Select waveform output mode Select default output value Select a timing to reload the value of the G1POj register Select if output level is inversed Select when output waveform is inversed Set to "0" (waveform generating function) Set to "1" (enables a function on channel j) G1POj G1FS G1FE j = 0 to 7 Bit configurations and functions vary with channels used. Registers associated with the waveform generating measurement function must be set after setting registers associated with the base timer. Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 292 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Waveform Generating Function) 22.3.1 Single-Phase Waveform Output Mode Output signal level of the OUTC1j pin becomes high ("H") when the value of the base timer matches that of the G1POj register (j=0 to 7). The "H" signal swithches to a low-level ("L") signal when the base timer reaches "000016". If the IVL bit in the G1POCRj register is set to "1" ("H" output as default value), an "H" signal output is provided when waveform output starts. If the INV bit is set to "1" (output inversed), the level of the waveform output is inversed. See Figure 22.16 for details on single-phase waveform output mode operation. Table 22.9 lists specifications of single-phase waveform output mode. Table 22.9 Single-Phase Waveform Output Mode Specifications Item Output Waveform(2) • Free-running operation (the RST2 and RST1 bits in the G1BCR1 register are set to "002") Cycle "L" width "H" width : : : 65536 fBT1 m fBT1 65536-m fBT1 Specification m : setting value of the G1POj register (j=0 to 7), 000016 to FFFF16 • The base timer is cleared to "000016" by matching the base timer with the G1PO0 register (the RST1 bit is set to "1" and the RST2 bit is set to "0") n+2 Cycle : fBT1 m "L" width : fBT1 n+2-m "H" width : fBT1 m : setting value of the G1POj register (j=1 to 7), 000016 to FFFF16 n : setting value of the G1PO0 register, 000116 to FFFD16 If m ≥ n+2, the output level is fixed to "L" Waveform Output Start Condition(1) The IFEj bit in the G1FE register is set to "1" (channel j function enabled) The IFEj bit is set to "0" (channel j function disabled) The PO1jR bit in the interrupt request register is set to "1" (interrupt requested) when the value of the base timer matches that of the G1POj register. (See Figure 11.14) OUTC1j Pin Selectable Function Pulse signal output pin • Default value set function: Set starting waveform output level • Inversed output function: Waveform output signal is inversed and provided from the OUTC1j pin NOTES: 1. Set the FSCj bit in the G1FS register to "0" (waveform generating function selected). 2. When the INV bit in the G1POCRj register is set to "1" (output inversed), the "L" width and "H" width are inversed. Waveform Output Stop Condition Interrupt Request Rev. 1.01 Jul. 07, 2005 REJ09B0036-0101 Page 293 of 495 M32C/84 Group (M32C/84, M32C/84T) 22. Intelligent I/O (Waveform Generating Function) (1) Free-Running Operation (The RST2 to RST1 bits in the G1BCR1 register are set to "002") FFFF16 Base Timer m 000016 m fBT1 65536-m fBT1 OUTC1j pin(1) "H" "L" "H" "L" "1" "0" Write "0" by program if setting to "0" 65536 fBT1 OUTC1j pin(2) PO1jR bit in the IIOiIR register i=0 to 4, 8 to 10; j=0 to 7 m : Setting value of the G1POj register, 000016 to FFFF16 NOTES: 1. Waveform output when the INV bit in the G1POCRj register is set to "0" (not inversed) and the IVL bit is set to "0" (output "L" as default value). 2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1" ("H" output as default value). The above applies applies under the following condition: • The RST2 and RST1 bits in the G1BCR1 register are set to "002" (no base timer reset) and the UD1 and UD0 bits to "002" (counter increment mode) (2) The Base Timer is Reset when the Base Timer Matches the G1PO0 Register (The RST1 bit is set to "1" and the RST2 bit is set to "0") n+2 Base Timer m 000016 m fBT1 "H" n+2-m fBT1 OUTC1j pin "L" n+2 fBT1 Write "0" by program if setting to "0" PO1jR bit in the IIOiIR register "1" "0" i=0 to 4, 8 to 10; j=1 to 7 m : Setting value of the G1POj register, 000016 to FFFF16 n: Setting value of the G1PO0 register, 000116 to FFFD16 The above diagram applies under the following conditions: • The IVL bit in the G1POCRj register is set to "0" ("L" output as default value). The INV bit is set to "0" (not inversed). • The UD1 and UD0 bits in the G1BCR1 register are set to "002" (counter increment mode) • m