M37207EFFP

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER DESCRIPTION The M37207MF-XXXSP/FP and M37207M8-XXXSP are single-chip microcomputers designed with CMOS silicon gate technology. It is housed in a 64-pin shrink plastic molded DIP or a 80-pin plastic molded QFP. In addition to their simple instruction sets, the ROM, RAM and I/O addresses are placed on the same memory map to enable easy programming. The M37207MF-XXXSP/FP has a PWM function and an OSD function, so it is useful for a channel selection system for TV. The features of the M37207EFSP/FP are similar to those of the M37207MFXXXSP/FP except that these chips have a built-in PROM which can be written electrically. The difference between M37207MF-XXXSP/ FP and M37207M8-XXXSP are the ROM size, RAM size, ROM size for display and kinds of character. Accordingly, the following descriptions will be for the M37207MF-XXXSP/FP unless otherwise noted. • • • • • • • FEATURES • Number of basic instructions .................................................... 71 • Memory size ................................................................................. ROM ...................... 32K bytes (M37207M8-XXXSP) 62K bytes (M37207MF-XXXSP/FP, M37207EFSP/FP) RAM ...................... 512 bytes (M37207M8-XXXSP) 960 bytes (M37207MF-XXXSP/FP, M37207EFSP/FP) ROM correction memory ............................ 64 bytes ROM for display ....... 8K bytes (M37207M8-XXXSP) 12K bytes (M37207MF-XXXSP/FP, M37207EFSP/FP) RAM for display ........................................ 144 bytes Minimum instruction execution time ........................................ 0.5 µs (at 8 MHz oscillation frequency) Power source voltage .................................................. 5 V ± 10 % Subroutine nesting ............................................ 128 levels (Max.) Interrupts ...................................................... 15 types, 14 vectors 8-bit timers ................................................................................. 6 Programmable I/O ports (Ports P0, P1, P2, P30–P36, P4, P6) ....................................... 47 Input ports (Ports P70, P71) ....................................................... 2 Output ports (Ports P52–P56) ..................................................... 5 12 V withstand ports ................................................................. 10 LED drive ports .......................................................................... 4 Serial I/O ....................................... 8-bit ! 1 channel (2 systems) Multi-master I2C-BUS interface ............................... 1 (3 systems) Power dissipation In high-speed mode ........................................................ 165 mW (at VCC = 5.5 V, 8 MHz oscillation frequency, CRT on) In low-speed mode ......................................................... 0.33 mW (at VCC = 5.5 V, 32 kHz oscillation frequency) A-D comparator (6-bit resolution) ................................ 8 channels PWM output circuit ...................................... 14-bit ! 1, 8-bit ! 10 Interrupt interval determination circuit ........................................ 1 ROM correction function .......................................... 32 bytes ! 2 CRT display function Number of display characters ............... 24 characters ! 3 lines (16 lines maximum) Kinds of characters .................. 256 kinds (M37207M8-XXXSP) 384 kinds (M37207MF-XXXSP/FP, M37207EFSP/FP) Character display area .......................................... 12 ! 16 dots Kinds of character sizes ................................................. 4 kinds Kinds of character colors (It can be specified by the character) maximum 15 kinds (R, G, B, I) Kinds of character background colors (It can be specified by the character) maximum 7 kinds (R, G, B) 1/2-character unit color specification is possible. Kinds of raster colors (maximum 15 kinds) Display position Horizontal .................................................................. 64 levels Vertical .................................................................... 128 levels Bordering (horizontal and vertical) Wipe function Scanning line double count mode display is possible. • • • • • • • • • • • APPLICATION TV MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER PIN CONFIGURATION (TOP VIEW) OSC1/P7 0/AD4 OSC2/P7 1/AD5 P36/INT2/AD2 P35/AD1 P34/INT1 D-A/AD3 P60/PWM0 P61/PWM1 P62/PWM2 P63/PWM3 P64/PWM4 P65/PWM5 P66/PWM6 P67/PWM7 P33/TIM3 P32/TIM2/AD6 P31 P30 P47/SRDY1 /PWM8 P46/SIN1/PWM9 P45/SCLK1/SCL1 P44/SOUT1/SDA1 P43/SRDY2 /SCL2/AD7 P42/SIN2/SDA2/AD8 P41/SCLK2/SCL3/XCOUT P40/SOUT2/SDA3/X CIN CNV SS φ RESET 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 VCC HSYNC VSYNC R/P52 G/P53 B/P5 4 I/P5 5/TIM1 OVERFLOW OUT/P5 6 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 M37207MF-XXXSP, M37207M8-XXXSP M37207EFSP 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 XIN XOUT VSS Outline 64P4B 2 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER PIN CONFIGURATION (TOP VIEW) NC I/P5 5/TIM1 OVERFLOW OUT/P5 6 P00 P01 P02 P03 P04 P05 P06 P07 NC NC 55 59 57 50 48 47 56 53 46 54 44 62 63 60 52 49 64 61 51 58 45 43 42 41 NC P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 NC B/P54 G/P53 R/P52 VSYNC HSYNC NC VCC NC OSC1/P70/AD4 OSC2/P71/AD5 NC P36/INT2/AD2 P35/AD1 P34/INT1 D-A/AD3 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 13 14 4 16 22 23 2 3 5 7 15 17 10 12 40 39 38 37 36 35 34 33 NC NC P22 P23 P24 P25 P26 P27 VSS XOUT XIN RESET φ CNVSS NC NC M37207MF-XXXFP, M37207EFFP 32 31 30 29 28 27 26 25 20 18 11 19 21 Outline 80P6N-A P42/SIN2/SDA2/AD8 P41/SCLK2/SCL3/XCOUT P4φ/SOUT2/SDA3/X CIN P66/PWM6 P67/PWM7 NC NC P33/TIM3 P32/TIM2/AD6 P31 P30 P47/SRDY1 /PWM8 P46/SIN1/PWM9 NC NC P60/PWM0 P61/PWM1 P62/PWM2 P63/PWM3 P64/PWM4 P65/PWM5 P45/SCLK1/SCL1 P44/SOUT1/SDA1 P43/SRDY2 /SCL2/AD7 24 1 6 8 9 NC: Unconnected 3 INT1 INT2 P0(8) P3 (7) 14-bit PWM circuit P1 (8) P2 (8) SDA3 SCL3 SDA2 SCL2 SDA1 SCL1 P4 (8) P6 (8) OUT I B G R 6 26 25 24 23 22 21 20 19 14 13 12 11 10 9 8 7 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 A-D comparator SOUT2 S CLK2 SIN2 SRDY2 SOUT1 S CLK1 SIN1 SRDY1 49 50 51 52 53 54 55 56 41 42 43 44 45 46 47 48 33 34 35 36 37 38 39 40 3 4 5 15 16 17 18 57 58 59 60 61 62 63 I/O ports P00–P07 I/O ports P10–P17 I/O ports P30–P36 I/O ports P20–P27 D-A I/O ports P4 0–P47 I/O ports P6 0–P67 Output ports P52–P56 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Note 1: M37207M8-XXXSP has a 512 bytes RAM. Note 2: M37207M8-XXXSP has a 32 K bytes ROM. VSYNC Sync input HSYNC 4 VCC VSS CNV SS 32 27 2 1 64 FUNCTIONAL BLOCK DIAGRAM of M37207M8-XXXSP Input ports P7 0, P7 1 Clock input for CRT/ Clock output for CRT/ Sub-clock input Sub-clock output OSC1 OSC2 Clock Clock input output Timing output XIN XOUT φ Reset input RESET 30 31 28 29 Clock generating circuit TIM2 TIM3 (Note 2) Program counter A-D comparator Data bus Timer count source selection circuit Timer 1 T1 (8) Timer 2 T2 (8) Timer 3 T3 (8) XCIN ROM 64 K bytes (Note 1) XCOUT PCL (8) RAM 960 bytes Program counter PCH (8) Address bus Timer 4 T4 (8) Control signal Index register Accumulator A (8) Y (8) instruction register (8) Stack pointer S (8) Timer 5 T5 (8) Timer 6 T6 (8) Instruction decoder Index register 8-bit arithmetic and logical unit processor status register PS (8) X (8) CRT circuit SI/O (8) Multi-master I2C-BUS Interface 8-bit PWM circuit P5 (5) MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER FUNCTIONS Parameter Number of basic instructions Instruction execution time Clock frequency Memory size ROM M37207M8-XXXSP M37207MF-XXXSP/FP, M37207EFSP/FP RAM M37207M8-XXXSP M37207MF-XXXSP/FP, M37207EFSP/FP ROM correction memory CRT ROM M37207M8-XXXSP M37207MF-XXXSP/FP, M37207EFSP/FP Input/Output ports CRT RAM P00–P07 P10–P17 P20–P27 P30, P31 P32–P36 P40–P47 P52–P56 P60–P67 P70, P70 Serial I/O Multi-master I2C-BUS interface A-D comparator PWM output circuit Timers ROM correction function Subroutine nesting Interrupt interval determination circuit Interrupt I/O I/O I/O I/O I/O I/O Output I/O Input 71 0.5 m s (the minimum instruction execution time, at 8 MHz oscillation frequency) 8 MHz (maximum) 32 K bytes 64 K bytes 512 bytes 960 bytes 64 bytes 8K bytes 12K bytes 144 bytes 8-bit ! 1 (CMOS input/output structure) 8-bit ! 1 (CMOS input/output structure) 8-bit ! 1 (CMOS input/output structure) 2-bit ! 1 (CMOS input/output structure) 5-bit ! 1 (N-channel open-drain output structure, can be used as external clock input pins, A-D input pins, INT input pins) 8-bit ! 1 (N-channel open-drain output structure, can be used as serial I/O pins, A-D input pins, PWM output pins, multi-master I2C-BUS interface, sub-clock I/O pins) 5-bit ! 1 (CMOS output structure, can be used as CRT output pins, an external clock output pin) 8-bit ! 1 (N-channel open-drain output structure, can be used as PWM output) 2-bit ! 1 (can be used as CRT display clock I/O pins, analog input pins) 8-bit ! 1 (2 systems) 1 (3 systems) 8 channels (6-bit resolution) 14-bit ! 1, 8-bit ! 10 8-bit timer ! 6 32 bytes ! 2 128 levels (maximum) 1 External interrupt ! 2, Internal timer interrupt ! 6, Serial I/O interrupt ! 1, CRT interrupt ! 1 , Multi-master I 2 C-BUS interface interrupt ! 1 , f(XIN)/4096 interrupt ! 1, VSYNC interrupt ! 1, BRK interrupt ! 1 2 built-in circuits (externally connected to a ceramic resonator or a quartzcrystal oscillator) Functions Clock generating circuit 5 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER FUNCTIONS (continued) Parameter Power source voltage Power dissipation In high-speed CRT ON mode CRT OFF In low-speed mode In stop mode Operating temperature range Device structure Package M37207MF-XXXSP, M37207M8-XXXSP M37207EFSP M37207MF-XXXFP, M37207EFFP Number of display characters CRT display function Character display area Kinds of characters M37207M8-XXXSP M37207MF-XXXSP/FP, M37207EFSP/FP CRT OFF 5 V ± 10 % 165 mW typ. (at oscillation frequency f(XIN) = 8 MHz, fOSC = 8 MHz) 82.5 mW typ. (at oscillation frequency f(XIN) = 8 MHz) 0.33 mW typ. (at oscillation frequency fCLK = 32 kHz, f(XIN) = stopped) 1.1 mW (maximum) –10 °C to 70 °C CMOS silicon gate process 64-pin shrink plastic molded DIP 80-pin plastic molded QFP 24 characters ! 3 lines (maximum 16 lines by software) 12 ! 16 dots 256 Kinds 384 Kinds 4 kinds Maximum 15 kinds (R, G, B, I); can be specified by the character 64 levels (horizontal) ! 128 levels (vertical) Functions Kinds of character sizes Kinds of character colors Display position (horizontal, vertical) 6 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER PIN DESCRIPTION Pin VCC, VSS Name Power source Input/ Output Functions Apply voltage of 5 V ± 10 % (typical) to VCC and AVCC, and 0 V to VSS. CNVSS ______ CNVSS Reset input Input Connected to VSS. To enter the reset state, the reset input pin must be kept at a “L” for 2 m s or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT. If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is CMOS output. See notes at end of table for full details of port P0 functions. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Ports P30, P31 are 2-bit I/O ports and have basically the same functions as port P0. The output structure is CMOS output. Ports P32–P36 are 5-bit I/O ports and have basically the same functions as port P0. The output structure is N-channel open-drain output. Pins P32, P35, P36 are also used as analog input pins AD6, AD1 and AD2 respectively. Pins P32, P33 are also used as external clock input pins TIM2, TIM3 respectively. Pins P34, P36 are also used as external interrupt input pins INT1, INT2. Port P4 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is N-channel open-drain output. Pins P40, P42, P44, P46 are also used as serial I/O data input/output pins SOUT2, SIN2, SOUT1, SIN1 respectively. The output structure is N-channel open-drain output. Pins P41, P45 are also used as serial I/O synchronous clock input/output pins SCLK2, SCLK1 respectively. _____ _____ RESET XIN XOUT P00–P07 Clock input Clock output I/O port P0 Input Output I/O P10–P17 P20–P27 P30, P31 P32/TIM2/ AD6, P33/TIM3, P34/INT1, P35/AD1, P36/INT2/ AD2 P40/SOUT2/ SDA3/XCIN, P41/SCLK2/ SCL3/ XCOUT, P42/ SIN2/SDA2/ AD8, _____ I/O port P1 I/O port P2 I/O port P3 I/O port P3 Analog input External clock input External interrupt input I/O port P4 Serial I/O data input/output Serial I/O synchronous clock input/ output Serial I/O receive enable signal output Multi-master I2CBUS interface Sub-clock input Sub-clock output Analog input PWM output I/O I/O I/O I/O Input Input Input I/O I/O I/O P43/SRDY2/ SCL2/AD7, P44/SOUT1/ SDA1, P45/SCLK1/ SCL1, P46/SIN1/ PWM9, _____ Output I/O Pins P43, P47 are also used as serial I/O receive enable signal output pins SRDY2, SRDY1 respectively. The output structure is N-channel open-drain output. Pins P40–P45 are also used as SDA3, SCL3, SDA2, SCL2, SDA1, SCL1 respectively when multi-master I2C-BUS interface is used. The output structure is N-channel opendrain output. Pin P40 is also used as sub-clock input pin XCIN. Pin P41 is also used as sub-clock output pin XCOUT. The output structure is N-channel open-drain output. Pins P42, P43 are also used as analog input pins AD8, AD7 respectively. Pins P46, P47 are also used as PWM output pins PWM9, PWM8 respectively. The output structure is N-channel open-drain output. Input Output Input Output P47/SRDY1/ PWM8 7 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER PIN DESCRIPTION (continued) Pin R/P52, G/P53, B/P54, I/P55/TIM1 OVERFLOW, OUT/P56 P60/PWM– P67/PWM7 Name Output port P5 CRT output Timer 1 overflow signal output I/O port P6 PWM output OSC1/P70/ AD4, OSC2/P71/ AD5 Input port P7 Clock input for CRT display Clock output for CRT display Analog input HSYNC VSYNC f D-A/AD3 HSYNC input VSYNC input Timing output DA output Analog input Input/ Output Output Output Output I/O Output Input Input Functions Ports P52–P56 are 5-bit output ports. The output structure is CMOS output. Pins P52–P56 are also used as CRT output pins R, G, B, I, OUT respectively. The output structure is CMOS output. Pin P55 is also used as timer 1 overflow signal output pin TIM1 OVERFLOW. The output structure is CMOS output. Port P6 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is N-channel open-drain output. Pins P60–P67 are also used as PWM output pins PWM0–PWM7. The output structure is CMOS output. Ports P70, P71 are 2-bit input port. Pin P70 is also used as CRT display clock input pin OSC1. Output Pin P71 is also used as CRT display clock output pin OSC2. The output structure is CMOS output. Input Input Input Output Output Input Pins P70, P71 are also used as analog input pins AD4, AD5 respectively. This is a horizontal synchronous signal input for CRT display. This is a vertical synchronous signal input for CRT display. This is a timing output pin. This pin has reset-out output function. The output structure is CMOS output. This is an output pin for 14-bit PWM. The D-A pin is also used as analog input pin AD3. Note : As shown in the memory map (Figure 5), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0 direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins float, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. 8 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Ports P00–P07, P10–P17, P20–P27, P30, P31, D-A Direction register CMOS output Data bus Ports P00–P07, P10–P17, P20–P27, P30, P31, D-A Note : D-A pin is also used as AD3. Port latch Ports P46, P47, P60–P67 N-channel open-drain output Ports P46, P47, P60–P67 Data bus Port latch Note : Each port is also used as follows: P46 : _____ SIN1/PWM9 P47 : SRDY1/PWM8 P60–P67 : PWM0–PWM7 Direction register Ports P32–P36, P42–P45 Direction register N-channel open-drain output Ports P32–P36, P42–P45 Data bus Port latch Note : Each port is also used as follows: P32 : TIM2/AD6 P33 : TIM3 P34 : INT1 P35 : AD1 P36 : INT2/AD2 SIN2/SDA2/AD8 P42 : _____ P43 : SRDY2/SCL2/AD7 P44 : SOUT1/SDA1 P45 : SCLK1/SCL1 Fig. 1. I/O Pin Block Diagram (1) 9 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER HSYNC, VSYNC Schmidt input Internal circuit HSYNC, VSYNC R, G, B, I, OUT, P52–P55, φ CMOS output Internal circuit P52–P55, φ Note : Each port is also used as follows: P52 : R P53 : G P54 : B P55 : I/TIM1 P56 : OUT Fig. 2. I/O Pin Block Diagram (2) 10 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 User’s Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instructions can be used. CPU Mode Register The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated at address 00FB16. CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 00 1 CPU mode register (CPUM) (CM) [Address 00FB B Name 0, 1 Processor mode bits (CM0, CM1) Functions b1 b0 16] After reset R W 0 RW 0 0 1 1 0: Single-chip mode 1: 0: Not available 1: 1 1 RW RW RW 2 3 4 0: 0 page Stack page selection bit (CM2) (See note 1) 1: 1 page Fix these bits to “1.” Internal system clock output selection bit (CM4) (See note 2) 0: Output is stopped 1: Internal system clock φ output 0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped 0: X IN–XOUT selected (high-speed mode) 1: X CIN–XCOUT selected (high-speed mode) 1 5 XCOUT drivability selection bit (CM5) 6 Main Clock (X IN–XOUT) stop bit (CM6) 7 Internal system clock selection bit (CM7) 1 0 RW RW 0 RW Notes 1: This bit is set to “1” after the reset release. 2: The internal system clock φ stops at HIGH. Fig. 3. CPU Mode Register 11 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER MEMORY Special Function Register (SFR) Area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM ROM is used for storing user programs as well as the interrupt vector area. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. RAM for Display RAM for display is used for specifying the character codes and colors to display. ROM for Display ROM for display is used for storing character data. ROM Correction Memory (RAM) This is used as the program area for ROM correction. 000016 ROM for display (8 K bytes) for M37207M8 1000016 RAM (960 bytes) for M37207MF RAM 00C016 (512 bytes) for M37207M8 00FF16 01FF16 Zero page SFR area ROM for display (12 K bytes) for M37207MF 11FFF16 12FFF16 Not used 020416 021B16 02C016 02FF16 030016 ROM correction memory (64 bytes) Block 1: addresses 02C0 16 to 02DF16 Block 2: addresses 02E0 16 to 02FF 16 2 page register Not used 033F16 04FF16 RAM for display (144 bytes) (See note) Not used 060016 06D716 Not used 080016 ROM (62 K bytes) for M37207MF ROM (32 K bytes) for M37207M8 800016 Not used FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF 16 Note: Refer to Table 9. Contents of CRT display RAM. Fig. 4. Memory Map 12 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER sSFR Area (addresses C016 to DF16) < Bit allocation > 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Undefined immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register b7 Bit allocation b0 b7 State immediately after reset ? 0016 ? 0016 ? 0016 ?? 0016 ? ? ?? 0016 ? 0016 ? ?? ? ? ? ? ? 0016 0016 ? 0016 ? 0016 10 0016 0016 0016 ? b0 Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) Port P4 (P4) Port P4 direction register (D4) Port P5 (P5) Port P5 control register (D5) Port P6 (P6) Port P6 direction register (D6) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) Interrupt interval determination register (??) Interrupt interval determination control register (RE) RE5 RE4 RE3 RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 PN4 PN3 PN2 PN1 PN0 0 ? ? ? ? ? 0 ? ? ? ? ? 0 0 ? ? ? ? I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2 C control register (S1D) I2C clock control register (S2) Serial I/O mode register (SM) Serial I/O regsiter (SIO) SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB PIN AL AAS AD0 LRB 0 0 0 0 0 ? 10BIT BSEL1 BSEL0 ALS ESO BC2 BC1 BC0 SAD ACK FAST ACK BIT MODE CCR4 CCR3 CCR2 CCR1 CCR0 SM6 SM5 0 SM3 SM2 SM1 SM0 Fig. 5. Memory Map of Special Function Register (SFR) 13 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER s SFR Area (addresses E016 to FF16) < Bit allocation > < State immediately after reset > 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Undefined immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register b7 Bit allocation b0 b7 State immediately after reset 0016 ?? ?? ?? ?? ?? 0016 0016 0016 0016 0016 0016 0016 0016 0016 ?0 FF16 0716 FF16 0716 0016 0016 ? ? ? ? ? CK0 1 1 0016 0016 0016 0016 b0 Horizontal register (HR) Vertical register 1 (CV1) Vertical register 2 (CV2) Vertical register 3 (CV3) Character size register (CS) Border selection register (MD) Color register 0 (CO0) Color register 1 (CO1) Color register 2 (CO2) Color register 3 (CO3) CRT control register 1 (CC) Display block counter (CBC) CRT port control register (CRTP) Wipe mode register (SL) Wipe start register (??) A-D control register 1 (ADM) Timer 1 (TM1) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer mode register 1 (TMR1) Timer mode register 2 (TMR2) PWM5 register (PWM5) PWM6 register (PWM6) PWM7 register (PWM7) PWM8 register (PWM8) PWM9 register (PWM9) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0 HR5 HR4 HR3 HR2 HR1 HR0 CV16 CV15 CV14 CV13 CV12 CV11 CV10 CV26 CV25 CV24 CV23 CV22 CV21 CV20 CV36 CV35 CV34 CV33 CV32 CV31 CV30 CS7 CS31 CS30 CS21 CS20 CS11 CS10 MD31 MD30 MD21 MD20 MD11 MD10 0 0 0 0 0 ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CO07 CO06 CO05 CO04 CO03 CO02 CO01 CO00 CO17 CO16 CO15 CO14 CO13 CO12 CO11 CO11 CO27 CO26 CO25 CO24 CO23 CO22 CO21 CO22 CO37 CO36 CO35 CO34 CO33 CO32 CO31 CO33 0 B CC6 CC5 CC4 CC3 CC2 CC1 CC0 G R I R/G/B VSYC HSYC SL6 SL5 SL4 SL3 SL2 SL1 SL0 ADM4 ADM2 ADM1 ADM0 0 0 0 0 0 0 TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10 TMR27 TMR26 TMR25 TMR24 TMR23 TMR22 TMR21 TMR20 CM7 CM6 CM5 1 1 CM2 0 0 0 0 1 1 0 0 IICR VSCR CRTR TM4R TM3R TM2R TM1R 0 TM56C TM56R MSR CK0 S1R IT2R IT1R IICE VSCE CRTE TM4E TM3E TM2E TM1E 0 TM56E MSE 0 SIE IT2E IT1E Fig. 6. Memory Map of Special Function Register (SFR) 14 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER sSFR Area (addresses 20416 to 21B16) < Bit allocation > 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Undefined immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 Register b7 Bit allocation b0 b7 State immediately after reset 0016 0016 00 0016 0016 0016 ?? 0016 ? ? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 ?0 b0 Timer 5 (T5) Timer 6 (T6) Port control register (P7D) Serial I/O control register (SIC) CRT control register 2 (CBR) CRT clock selection register (OP) A-D control register (ADC) Timer mode register (TMR3) P7D4 P7D2 P7D1 P7D0 0 0 0 0 ? ? SIC7 SIC8 SIC5 SIC4 SIC3 SIC2 SIC1 SIC0 CBR1 CBR0 0 OP1OP0 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 TMR30 0 0 ? ? ? ? ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) 0 0 RC1 RC0 ? ? ? 0 0 0 Fig. 7. Memory Map of 2 Page Register 15 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER < Bit allocation > 0 : “0” immediately after reset : Name : Function bit 1 : “1” immediately after reset ? : Undefined immediately after reset : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Register b7 Processor status register (PS) Program counter (PCH) Program counter (PCL) Bit allocation b0 b7 State immediately after reset b0 N V T B D I Z C ? ????1?? Contents of address FFFF 16 Contents of address FFFE 16 Fig. 8. Internal State of Processor Status Register and Program Counter at Reset 16 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER INTERRUPTS Interrupts can be caused by 15 different sources consisting of 3 external, 10 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in Table 1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, (1) The contents of the program counter and processor status register are automatically stored into the stack. (2) The interrupt disable flag I is set to “1” and the corresponding interrupt request bit is set to “0.” (3) The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to “1.” All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figures 10 to 13 show the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,” and the interrupt disable flag is “0.” The interrupt request bit can be set to “0” by a program, but not set to “1.” The interrupt enable bit can be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 9 shows interrupt control. Interrupt Causes (1) VSYNC and CRT interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The CRT interrupt occurs after character block display to the CRT is completed. (2) INT1, INT2 interrupts With an external interrupt input, the system detects that the level of a pin changes from “L” to “H” or from “H” to “L,” and generates an interrupt request. The input active edge can be selected by bits 3 and 4 of the interrupt interval determination control register (address 00D816) : when this bit is “0,” a change from “L” to “H” is detected; when it is “1,” a change from “H” to “L” is detected. Note that all bits are cleared to “0” at reset. (3) Timer 1, 2, 3 and 4 interrupts An interrupt is generated by an overflow of timer 1, 2, 3 or 4. (4) Serial I/O interrupt This is an interrupt request from the clock synchronous serial I/O function. Table 1. Interrupt Vector Addresses and Priority Interrupt Source Reset CRT interrupt INT1 interrupt INT2 interrupt Timer 4 interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt Serial I/O interrupt Multi-master I2C-BUS interface interrupt Timer 5 · 6 interrupt BRK instruction interrupt Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF716, FFF616 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE716, FFE616 FFE316, FFE216 FFDF16, FFDE16 Source switch by software (See note) Non-maskable (software interrupt) Active edge selectable Active edge selectable Active edge selectable Non-maskable Remarks Note : Switching a source during a program causes an unnecessary interrupt. Therefore, set a source at initializing of program. 17 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (5) f(XIN)/4096 interrupt This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM output control register 1 to “0.” (6) Multi-master I2C-BUS interface interrupt This is an interrupt request related to the multi-master I2C-BUS interface. (7) Timer 5 · 6 interrupt An interrupt is generated by an overflow of timer 5 or 6. Their priorities are same, and can be switched by software. (8) BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable). Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Fig. 9. Interrupt Control 18 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Interrupt Request Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC 16] B 0 1 2 3 4 5 6 Name Timer 1 interrupt request bit (TM1R) Timer 2 interrupt request bit (TM2R) Timer 3 interrupt request bit (TM3R) Timer 4 interrupt request bit (TM4R) CRT interrupt request bit (CRTR) V SYNC interrupt request bit (VSCR) Multi-master I 2C-BUS interface interrupt request bit (IICR) Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued After reset R W 0 0 0 0 0 0 0 RV RV RV RV RV RV RV 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” 0 R— Fig. 10. Interrupt Request Register 1 Interrupt Request Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD 16] B 0 Name Functions After reset R W 0 0 0 0 0 0 0 RV RV RV R— RV RV RW INT1 interrupt 0 : No interrupt request issued request bit (ITIR) 1 : Interrupt request issued 1 INT2 interrupt 0 : No interrupt request issued request bit (IT2R) 1 : Interrupt request issued Serial I/O interrupt 0 : No interrupt request issued 2 request bit (SIR) 1 : Interrupt request issued 3,6 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 4 f(XIN)/4096 interrupt 0 : No interrupt request issued request bit (MSR) 1 : Interrupt request issued Timer 5 • 6 interrupt 5 0 : No interrupt request issued request bit (TM56R) 1 : Interrupt request issued 7 Fix this bit to “0.” V: “0” can be set by software, but “1” cannot be set. Fig. 11. Interrupt Request Register 2 19 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Interrupt Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B 0 1 2 3 4 5 6 Name Timer 1 interrupt enable bit (TM1E) Timer 2 interrupt enable bit (TM2E) Timer 3 interrupt enable bit (TM3E) Timer 4 interrupt enable bit (TM4E) CRT interrupt enable bit (CRTE) VSYNC interrupt enable bit (VSCE) Multi-master I 2C-BUS interface interrupt enable bit (IICE) Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 RW RW RW RW RW RW RW 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” 0 R— Fig. 12. Interrupt Control Register 1 Interrupt Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 0 Interrupt control register 2 (ICON2) [Address 00FF16] B 0 Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Timer 5 1 : Timer 6 0 0 0 RW RW RW RW RW RW RW INT1 interrupt enable bit (IT1E) 1 INT2 interrupt enable bit (IT2E) 2 Serial I/O interrupt enable bit (SIE) 3, 6 Fix these bits to “0.” 4 5 f(XIN)/4096 interrupt enable bit (MSE) Timer 5 • 6 interrupt enable bit (TM56E) 7 Timer 5 • 6 interrupt switch bit (TM56C) Fig. 13. Interrupt Control Register 2 20 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER TIMERS The M37267M6-XXXSP has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5 and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 17 . 0. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4, addresses 020C16 and 020D16 : timers 5 and 6), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse after the count value reaches “0016.” (5) Timer 5 Timer 5 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 f(XCIN) Timer 4 overflow signal The count source of timer 3 is selected by setting bit 6 of timer mode register 1 (address 00F416) and bit 7 of timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 5 interrupt request occurs at timer 5 overflow. • • • (6) Timer 6 Timer 6 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 Timer 5 overflow signal The count source of timer 6 is selected by setting bit 7 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 5 overflow signal is a count source for timer 6, timer 5 functions as an 8-bit prescaler. Timer 6 interrupt request occurs at timer 6 overflow. (1) Timer 1 Timer 1 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 f(XIN)/4096 or f(XCIN)/4096 f(XCIN) External clock from the TIM2 pin The count source of timer 1 is selected by setting bits 5 and 0 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 1 interrupt request occurs at timer 1 overflow. • • • • • • (2) Timer 2 Timer 2 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 Timer 1 overflow signal External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00F416). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 1 overflow signal is a count source for timer 2, timer 1 functions as an 8-bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow. • • • At reset, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. The f(XIN) V /16 is selected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN)V /16 is not selected as the timer 3 count source. So set bit 0 of timer mode register 2 (address 00F516) to “0” before execution of the STP instruction (f(X IN ) V / 16 is selected as timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected. As a result of the above procedure, the program can start under a stable clock. V : When bit 7 of the CPU mode register (CM7) is “1,” f(XIN) becomes f(XCIN). The timer-related registers is shown in Figures 14 to 16. (3) Timer 3 Timer 3 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 External clock from the TIM3 pin The count source of timer 3 is selected by setting bit 0 of timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. Timer 3 interrupt request occurs at timer 3 overflow. • • (4) Timer 4 Timer 4 can select one of the following count sources: f(XIN)/16 or f(XCIN)/16 f(XIN)/2 or f(XCIN)/2 Timer 3 overflow signal The count source of timer 3 is selected by setting bits 1 and 4 of timer mode register 2 (address 00F516). Either f(XIN) or f(XCIN) is selected by bit 7 of the CPU mode register. When timer 3 overflow signal is a count source for timer 4, the timer 3 functions as an 8-bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. • • • 21 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Timer Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TMR1) [Address 00F416] B Name 0 Timer 1 count source selection bit 1 (TMR10, TMR15) Functions b5 b0 After reset R W 0 RW 0 0 1 1 0: f(X IN)/16 or f(XCIN)/16 (See note) 1: f(X IN)/4096 or f(X CIN)/4096 (See note) 0: f(Xc IN) 1: External clock from TIM2 pin 0 RW 1 Timer 2 count source selection bit 1 (TMR11) Timer 1 count stop bit (TMR12) Timer 2 count stop bit (TMR13) Timer 2 count source selection bit 2 (TMR14) Timer 5 count source selection bit 2 (TMR16) Timer 6 internal count source selection bit (TMR17) 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(X CIN)/16 (See note) 1: Timer 1 overflow 0: Timer 2 overflow 1: Timer 4 overflow 0: f(XIN)/16 or f(X CIN)/16 (See note) 1: Timer 5 overflow 2 3 4 0 0 0 RW RW RW 6 7 0 0 RW RW Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. Fig. 14. Timer Mode Register 1 Timer Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TMR2) [Address 00F516] B Name 0 Timer 3 count source selection bit (TMR20) 1 Timer 4 count source selection bit 2 (TMR21) Timer 3 count stop bit (TMR22) Timer 4 count stop bit (TMR23) Timer 4 count source selection bit 1 (TMR24) Timer 5 count stop bit (TMR25) Timer 6 count stop bit (TMR26) Timer 5 count source selection bit 1 (TMR27) Functions 0 : f(XIN)/16 or f(X CIN)/16 (See note) 1 : External clock from TIM3 pin 0 : Timer 3 overflow signal 1 : f(XIN)/16 or f(X CIN)/16 (See note) 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count source selected by bit 1 of TMR2 1 : f(X IN)/2 or f(XCIN)/2 (See note) 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count source selected by bit 0 of TMR3 1: Count source selected by bit 6 of TMR1 After reset R W 0 RW 0 RW 2 3 4 0 0 0 RW RW RW 5 6 7 0 0 0 RW RW RW Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. Fig. 15. Timer Mode Register 2 22 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Timer Mode Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 3 (TMR3) [Address 020B 16] B Name 0 Timer 5 count source selection bit 3 (TMR30) Functions 0 : f(XIN)/16 or f(X CIN)/16 (See note) 1 : f(XCIN) After reset R W 0 RW 1 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are “0.” 7 0 R— Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. Fig. 16. Timer Mode Register 3 23 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Data bus 8 XCIN CM7 TMR1 5 1/4096 TMR1 5 Timer 1 latch (8) 8 XIN 1/2 1/8 TMR1 0 TMR12 TMR1 4 Timer 1 (8) 8 8 Timer 1 interrupt request Timer 2 latch (8) 8 TIM2 TMR1 1 TMR13 Timer 2 (8) 8 8 Timer 2 interrupt request TIM3 FF16 Timer 3 latch(8) 8 Reset STP instruction Timer 3 (8) TMR2 0 TMR22 8 8 Timer 3 interrupt request TMR2 1 0716 Timer 4 latch (8) 8 Timer 4 (8) TMR2 4 TMR23 TMR1 6 Selection gate : Connected to black side at reset. TMR1 : Timer mode register 1 TMR2 : Timer mode register 2 TMR3 : Timer mode register 3 CM : CPU mode register TMR2 7 TMR3 0 TMR2 5 8 8 Timer 4 interrupt request Timer 5 latch (8) 8 Timer 5 (8) 8 8 Timer 5 interrupt request Timer 6 latch (8) 8 Timer 6 (8) TMR1 7 TMR26 8 Timer 6 interrupt request Notes 1: HIGH pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used. Fig. 17. Timer Block Diagram 24 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER SERIAL I/O This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in clock synchronous mode. The serial I/O block diagram is shown in Figure 18. The synchronous clock I/O pin (SCLK), and data I/O pins (SOUT, SIN), receive enable ____ signal output pin (SRDY) also function as port P4. Bit 2 of the serial I/O mode register (address 00DE16) selects whether the synchronous clock is supplied internally or externally (from the pins SCLK1, SCLK2). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use pins for serial I/O, set the corresponding bits of the port P4 direction register (address 00C916) to “0.” The operation of the serial I/O is described below. The operation differs depending on the clock source; external clock or internal clock. XCIN Data bus XIN CM7 P43 latch SCL2 CSIO SRDY2 SM4 P41 latch SCL3 S CLK2 SM3 P40 latch SOUT2 SM3 SIN2 SM6 SDA2 P40 latch P47 latch SRDY1 SIC7 P45 latch SCL1 S CLK1 SIC5 P44 latch SDA1 SOUT1 SIC5 SIC4 SIC4 SIC3 CM : CPU mode register SM : Serial I/O mode register SIC : Serial I/O control register CSIO : Bit 1 of serial I/O control register PWM8 SM7 CSIO SM7 SDA3 CSIO SM5 : LSB MSB (Note) Serial I/O shift register (8) 8 (Address 00DF 16) CSIO Serial I/O counter (8) Serial I/O interrupt request SM6 Synchronous circuit 1/2 1/2 Frequency divider 1/2 1/4 1/8 1/16 SM2 S SM1 SM0 Selection gate : Connected to black side at reset. SIN1 SIC6 PWM9 P46 latch Note : When the data is set in the serial I/O register (address 00DF 16), the register functions as the serial I/O shift register. Fig. 18. Serial I/O Block Diagram 25 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER ____ Internal clock : The SRDY signal goes to HIGH during the write cycle by writing data into the serial I/O register (address 00DD16). After the ____ write cycle, the SRDY signal goes to “L” (receive enable state). The ____ SRDY signal goes to “H” at the next falling edge of the transfer clock for the serial I/O register. The serial I/O counter is set to “7” during write cycle into the serial I/ O register (address 00DD16), and transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at HIGH. At this time the interrupt request bit is set to “1.” External clock : When an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 1 MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 19. When using an external clock for transfer, the external clock must be held at “H” for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching. Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions such as SEB and CLB. 2: When an external clock is used as the synchronous clock, write transmit data to the serial I/O register when the transfer clock input level is HIGH. Synchronous clock Transfer clock Serial I/O register write signal (See note) Serial I/O output SOUT Serial I/O input S IN Receive enable signal SRDY Interrupt request bit is set to “1” Note : When an internal clock is selected, the S OUT pin is at high-impedance after transfer is completed. D0 D1 D2 D3 D4 D5 D6 D7 Fig. 19. Serial I/O Timing (for LSB first) 26 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Serial I/O Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O mode register (SM) [Address 00DE16] B Name b1 0 0 1 1 Functions b0 0: f(X IN)/4 or f(XCIN)/4 1: f(X IN)/16 or f(XCIN)/16 0: f(X IN)/32 or f(XCIN)/32 1: f(X IN)/64 or f(XCIN)/64 After reset R W 0 RW 0, 1 Internal synchronous clock selection bits (SM0, SM1) (See note 1) 2 Synchronous clock selection bit (SM2) 0: External clock 1: Internal clock b7 b3 P40/SOUT2/ P41/SCLK2/ SDA3/XCIN SCL3/X COUT !0 P40 P41 01 SOUT2 SCLK2 SDA3 SCL3 1 P43/SRDY2/ SCL2/AD7 P43 SRDY2 SDA2 0 RW 3, 7 Ports P40, P41 function selection bits (SM3, SM7) (See note 2) 0 RW b6 b4 P42/SIN2/ 4, 6 Ports P42, P43 SDA2/AD8 function selection bits 00 P42 (SM4, SM6) 1 SDA2 (See note 2) 01 P42 1 SDA2 0: LSB first 5 Transfer direction 1: MSB first selection bit (SM5) 0 RW 0 RW Notes 1: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. 2: When using ports P4 0–P4 3 as serial I/O pins, set bit 1 of the serial control register to “1.” Fig. 20. Serial I/O Mode Register Serial I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIC) [Address 0207 16] B 0 Name Input signal to sift register selection bit (SIC0) Functions CSIO b0 0 0: Input signal from S IN1 0 1: Input signal from S OUT1 (See note 1) 1 0: Input signal from S IN2 1 1: Input signal from S OUT2 (See note 1) 0: SOUT1,SCLK1, SIN1, SRDY1 1: SOUT2,SCLK2, SIN2, SRDY2 0: SDA2, SCL2, SDA1, SCL1 1: SDA3, SCL3 b7 b3 0! 10 1 P47/SRDY1/PWM8 P47 SRDY1 PWM8 After reset R W RW 0 1 2 Serial I/O pin switch bit (CSIO) I2C-BUS connection ports switch bit (SIC2) 0 0 RW RW 3, 7 Ports P47 function selection bits (SM3, SM7) (See note 2) 0 RW b5 b4 P44/SOUT1/ P45/SCLK1/ 4, 5 Ports P44, P45 SDA1 SCL1 function selection bits 0! P44 P45 (SM4, SM6) 10 SOUT1 SCLK1 (See note 2) 1 SDA1 SCL1 b6 P46/SIN1/PWM9 6 Ports P46 function 0 P46 selection bits 1 PWM9 (SIC6) (See note 2) 0 RW 0 RW Notes 1: When inputting data from the S out pin, set “FF 16” to the serial I/O register. 2: When using ports P4 4–P4 7 as serial I/O pins, set bit 1 of the serial I/O control register to “0.” Fig. 21. Serial I/O Control Register 27 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Serial I/O Common Transmission/Reception Mode By writing “1” to bit 0 of the serial I/O control register, signals SIN and SOUT are switched internally to be able to transmit or receive the serial data. Figure 22 shows signals on serial I/O common transmission/reception mode. Note : When receiving the serial data after writing “FF16” to the serial I/O register. SCLK2 “1” Clock “0” CSIO SOUT2 “1” “0” “1” Serial I/O shift register (8) “0” “0” SIC0 SIN2 “1” SCLK1 CSIO SOUT1 SIC0 : Bit 0 of serialI/O control register CSIO : Bit 1 of serial I/O control register SIN1 Fig. 22. Signals on Serial I/O Common Transmission/Reception Mode 28 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER MULTI-MASTER I2C-BUS INTERFACE The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 23 shows a block diagram of the multi-master I2C-BUS interface and Table 2 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits. Table 2. Multi-master I2C-BUS Interface Functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ = 4 MHz) Format Communication mode SCL clock frequency φ : System clock = f(XIN)/2 Note: We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00F916) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2). b7 I2C address register (S0D) b0 Interrupt generating circuit Interrupt request signal (IICIRQ) SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW Address comparator Serial data (SDA) Noise elimination circuit Data control circuit b7 I 2 C data shift register S0 b0 b7 MST TRX BB PIN b0 AL AAS AD0 LRB AL circuit Internal data bus I 2 C status register (S1) BB circuit Serial clock (SCL) Noise elimination circuit Clock control circuit b7 ACK b0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE b7 BSEL1 BSEL0 10BIT SAD ALS b0 ESO BC2 BC1 BC0 I2 C clock control register (S2) Clock division I2C clock control register (S1D) System clock (φ) Bit counter Fig. 23. Block Diagram of Multi-master I2C-BUS Interface 29 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (1) I2C Data Shift Register The data shift register (S0 : address 00D916) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00DC16) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00F816) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value. Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. I2C (2) I2C Address Register The I2C address register (address 00DA16) consists of a 7-bit slave ___ address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected. ____ s Bit 0: Read/Write Bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. sBits 1 to 7: Slave Address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. I2C Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register1(S0) [Address 00D9 16] 2 B 0 to 7 Name D0 to D7 Functions This is an 8-bit shift register to store receive data and write transmit data. After reset RW Indeterminate R W Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. Fig. 24. I2C Data Shift Register I2C Address Register b7 b6 b5 b4 b3 b2 b1 b0 I2C address register (S0D) [Address 00DA16] B 0 1 to 7 Name Read/write bit (RBW) Slave address (SAD0 to SAD6) 0: Read 1: Write Functions After reset R W 0 0 R— RW The address data transmitted from the master is compared with the contents of these bits. Fig. 25. I2C Address Register 30 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (3) I2C Clock Control Register The I2C clock control register (address 00DD16) is used to set ACK control, SCL mode and SCL frequency. sBits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Figure 26. s Bit 5: SCL Mode Specification Bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. s Bit 6: ACK Bit (ACK BIT) This bit sets the SDA status when an ACK clockV is generated. When this bit is set to “0,” the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). V ACK clock: Clock for acknowledgement sBit 7: ACK Clock Bit (ACK) This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally. I2C Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2 C clock control register (S2 : address 00DD 16 ) B 0 to 4 Name Functions High speed clock mode After reset R W 0 SCL frequency control bits Setup value of Standard clock (CCR0 to CCR4) CCR4–CCR0 mode 00 to 02 03 04 05 06 1D 1E 1F RW Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3 500/CCR value 333 250 400 (See note) 166 1000/CCR value ... 17.2 16.6 16.1 34.5 33.3 32.3 0 (at φ = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0 : Standard clock mode 1 : High-speed clock mode 0 : ACK is returned. 1 : ACK is not returned. 0 : No ACK clock 1 : ACK clock RW RW RW 6 7 0 0 Note: At 400 kHz in the high-speed clock mode, the duty is as below . “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 Fig. 26. I2C Clock Control Register 31 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (4) I2C Control Register The I2C control register (address 00DC16) controls the data communication format. s Bits 0 to 2: Bit Counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits. s Bit 3: I2C Interface Use Enable Bit (ESO) This bit enables usage of the multimaster I2C BUS interface. When this bit is set to “0,” the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ESO = “0,” the following is performed. PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C status register at address 00F816 ). Writing data to the I2C data shift register (address 00F616) is disabled. s Bit 4: Data Format Selection Bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to “(5) I2C Status Register,” bit 1) is received, transmission processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recognized. sBit 5: Addressing Format Selection Bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 00F716) are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. s Bits 6 and 7: Connection Control Bits between I2C-BUS Interface and Ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 28). “0” “1” BSEL0 “0” “1” BSEL1 SCL1/P45 SCL2/P43 SCL3/P41 SDA1/P4 4 SDA2/P4 2 SDA3/P4 0 • • SCL Multi-master I2C-BUS interface “0” “1” CIIC (Note 2) “0” “1” BSEL0 “0” “1” BSEL1 SDA “0” “1” CIIC (Note 2) Notes 1 : When using multi-master I2C-BUS interface, set bits 3 to 7 of the serial I/O mode register (address 00DE16) to “1.” 2 : CIIC is bit 2 of the serial I/O control register (address 020716) (refer to Figure 21). Fig. 27. Connection Port Control by BSEL0 and BSEL1 I2C Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D : address 00DC 16 ) B 0 to 2 Name Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0:8 1:7 0:6 1:5 0:4 1:3 0:2 1:1 After reset R W 0 RW 3 4 5 I2 C-BUS interface use enable bit (ESO) Data format selection bit (ALS) Addressing format selection bit (10BIT SAD) 0 : Disabled 1 : Enabled 0 : Addressing mode 1 : Free data format 0 : 7-bit addressing format 1 : 10-bit addressing format b7 b6 Connection port (See note) 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1 SCL2, SDA2 0 0 0 0 RW RW RW RW 6, 7 Connection control bits between I2C-BUS interface and ports Note: When using ports P1 1 -P14 as I 2 C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output. Fig. 28. I2C Control Register 32 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (5) I2C Status Register The I2C status register (address 00DB16) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to. s Bit 0: Last Receive Bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00D916). s Bit 1: General Call Detecting Flag (AD0) This bit is set to “1” when a general callV whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition. V General call: The master transmits the general call address “0016” to all slaves. s Bit 2: Slave Address Comparison Flag (AAS) This flag indicates a comparison result of address data. In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions. The address data immediately after occurrence of a START condition matches the slave address stored in the high-order 7 bits of the I2C address register (address 00DA16). A general call is received. In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition. When the address data is compared with the I 2C address register (8 bits consists of slave address and RBW), the first bytes match. The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00D916). s Bit 3: Arbitration LostV Detecting Flag (AL) In the master transmission mode, when a device other than the microcomputer sets the SDA to “L,”, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.” When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. V Arbitration lost: The status in which communication as a master is disabled. sBit 4: I2C-BUS Interface Interrupt Request Bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 30 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in any one of the following conditions. Executing a write instruction to the I2C data shift register (address 00F616). When the ESO bit is “0” At reset The conditions in which the PIN bit is set to “0” are shown below: Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) Immediately after completion of 1-byte data reception In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception In the slave reception mode, with ALS = “1” and immediately after completion of address data reception • • • • • • • • • • 33 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER s Bit 5: Bus Busy Flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (Note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit of the I2C control register (address 00DC16) is “0” and at reset, the BB flag is kept in the “0” state. s Bit 6: Communication Mode Specification Bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2C control register (address 00DC16) is “0” in the slave reception mode is selected, the TRX bit is set to “1” __ (transmit) if the least significant bit (R/W bit) of the address data_ trans_ mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions. When arbitration lost is detected. When a STOP condition is detected. When occurence of a START condition is disabled by the START condition duplication prevention function (Note). With MST = “0” and when a START condition is detected. With MST = “0” and when ACK non-return is detected. At reset s Bit 7: Communication Mode Specification Bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to “0” in one of the following conditions. Immediately after completion of 1-byte data transmission when arbitration lost is detected When a STOP condition is detected. When occurence of a START condition is disabled by the START condition duplication preventing function (Note). At reset • • • • Note: The START condition duplication prevention function disables the START condition generation, reset of bit counter reset, and SCL output, when the following condition is satisfied: • a START condition is set by another master device. • • • • • • 34 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER I2C Status Register b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1) [Address 00DB16] B 0 1 2 3 4 5 Name Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB) Functions 0 : Last bit = “0 ” 1 : Last bit = “1 ” 0 : No general call detected 1 : General call detected 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode After reset R W Indeterminate 0 0 0 0 0 0 R— R— R— R— R— RW RW 6, 7 Communication mode specification bits (TRX, MST) Note : These bits and flags can be read out, but cannnot be written. Fig. 29. I2C Status Register SCL PIN IICIRQ Fig. 30. Interrupt Request Signal Generation Timing 35 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (6) START Condition Generation Method When the ESO bit of the I2C control register (address 00DC16) is “1,” execute a write instruction to the I2C status register (address 00DB16) to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generation timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 31 for the START condition generation timing diagram, and Table 3 for the START condition/STOP condition generation timing table. Table 3. START Condition/STOP Condition Generation Timing Table Item Standard Clock Mode High-speed Clock Mode Setup time 5.0 µs (20 cycles) 2.5 µs (10 cycles) Hold time 5.0 µs (20 cycles) 2.5 µs (10 cycles) Set/reset time 3.0 µs (12 cycles) 1.5 µs (6 cycles) for BB flag Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. (9) START/STOP Condition Detect Conditions I2C status register write signal SCL SDA BB flag Setup time Setup time Hold time Set time for BB flag The START/STOP condition detect conditions are shown in Figure 33 and Table 4. Only when the 3 conditions of Table 4 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” is generated to the CPU. Fig. 31. START Condition Generation Timing Diagram SCL release time (7) RESTART Condition Generation Method To generate the RESTART condition, take the following sequence: Set “2016” to the I2C status register (S1). Write a transmit data to the I2C data shift register. Set “F016” to the I2C status register (S1) again. ; S1 = 2016 I2C status register I2C data shift register ; S0 = transmit data after restart I2C status register ; S1 = F016 SCL SDA (START condition) SDA (STOP condition) Setup time Setup time Hold time Hold time Fig. 33. START Condition/STOP Condition Detect Timing Diagram (8) STOP Condition Generation Method When the ES0 bit of the I2C control register (address 00DC16) is “1,” execute a write instruction to the I2C status register (address 00DB16) for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be generated. The STOP condition generation timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 32 for the STOP condition generation timing diagram, and Table 3 for the START condition/STOP condition generation timing table. Table 4. START Condition/STOP Condition Detect Conditions High-speed Clock Mode Standard Clock Mode 1.0 µs (4 cycles) < SCL 6.5 µs (26 cycles) < SCL release time release time 3.25 µs (13 cycles) < Setup time 0.5 µs (2 cycles) < Setup time 3.25 µs (13 cycles) < Hold time 0.5 µs (2 cycles) < Hold time Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. I2C status register write signal SCL SDA BB flag Setup time Hold time Reset time for BB flag Fig. 32. STOP Condition Generation Timing Diagram 36 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (10) Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below. 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DC16) to “0.” The first 7-bit address data transmitted from the master is compared with the highorder 7-bit slave address stored in the I2C address register (address 00DA16). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00DA16) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 34, (1) and (2). 10-bit addressing format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DC16) to “1.” An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00DA16). At the time of this comparison, an address comparison between the RBW bit of the I2C address regis__ ter (address 00DA16) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit __ addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00DB16) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 00D916), make an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I2C address register (address 00DA16) to “1” by __ software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00DA16). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 34, (3) and (4). Set transmit data in the I2C data shift register (address 00D916). At this time, an SCL and an ACK clock automatically occurs. When transmitting control data of more than 1 byte, repeat step . Set “D016” in the I2C status register (address 00DB16). After this, if ACK is not returned or transmission ends, a STOP condition will be generated. (12) Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode, using the addressing format, is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00DA16) and “0” in the RBW bit. Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 00DD16). Set “1016” in the I2C status register (address 00DB16) and hold the SCL at the HIGH. Set a communication enable status by setting “4816” in the I2C control register (address 00DC16). When a START condition is received, an address comparison is made. •When all transmitted addresses are “0” (general call) : AD0 of the I2C status register (address 00DB16) is set to “1” and an interrupt request signal occurs. •When the transmitted addresses match the address set in : AAS of the I2C status register (address 00DB16) is set to “1” and an interrupt request signal occurs. •In the cases other than the above : AD0 and AAS of the I2C status register (address 00DB16) are set to “0” and no interrupt request signal occurs. Set dummy data in the I2C data shift register (address 00D916). When receiving control data of more than 1 byte, repeat step . When a STOP condition is detected, the communication ends. (11) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00DA16) and “0” in the RBW bit. Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 00DD16). Set “1016” in the I2C status register (address 00DB16) and hold the SCL at the HIGH. Set a communication enable status by setting “4816” in the I2C control register (address 00DC16). Set the address data of the destination of transmission in the highorder 7 bits of the I2C data shift register (address 00D916) and set “0” in the least significant bit. Set “F016” in the I2C status register (address 00DB16) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. 37 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER S Slave address R/W A Data A Data A/A P 7 bits “0” 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver S Slave address R/W A Data A Data A P 7 bits “1” 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address R/W 1st 7 bits Slave address 2nd byte S A A Data A Data A/A P 7 bits “0” 8 bits 1 to 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address R/W 1st 7 bits Slave address 2nd byte Slave address R/W 1st 7 bits S A A Sr Data A Data 1 to 8 bits A P 7 bits “0” 8 bits 7 bits “1” 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit From master to slave From slave to master Fig. 34. Address Data Communication Format 38 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER PWM OUTPUT FUNCTION This microcomputer is equipped with a 14-bit PWM (DA) and ten 8bit PWMs (PWM0–PWM9). DA has a 14-bit resolution with the minimum resolution bit width of 250 ns and a repeat period of 4096 µs (for f(XIN) = 8 MHz). PWM0–PWM9 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 µs and repeat period of 1024 µs (for f(XIN) = 8 MHz). Figure 35 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0–PWM9 using f(XIN) divided by 2 as a reference signal. Figure 36 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of entirely HIGH output cannot be output, i.e. 256/256. (4) Operating of 14-bit PWM As with 8-bit PWM, set the bit 0 of PWM output control register 1 (address 00D516) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. Next, select the output polarity by bit 2 of PWM output control register 2 (address 00D616). Then, the 14-bit PWM outputs from the D-A output pin by setting bit 1 of PWM output control register 1 to “0” (at reset, this bit already set to “0” automatically) to select the DA output. The output example of the 14-bit PWM is shown in Figure 37. The 14-bit PWM divides the data of the DA latch into the low-order 6 bits and the high-order 8 bits. The fundamental waveform is determined with the high-order 8-bit data “DH.” A HIGH area with a length τ ! DH (HIGH area of fundamental waveform) is output every short area of “t” = 256 τ = 64 µs (τ is the minimum resolution bit width of 250 ns). The “H” level area increase interval (tm) is determined with the low-order 6-bit data “DL.” The HIGH are of smaller intervals “tm” shown in Table 5 is longer by τ than that of other smaller intervals in PWM repeat period “T” = 64t. Thus, a rectangular waveform with the different HIGH width is output from the D-A pin. Accordingly, the PWM output changes by τ unit pulse width by changing the contents of the DA-H and DA-L registers. A length of entirely HIGH cannot be output, i. e. 256/256. (1) Data Setting When outputting DA, first set the high-order 8 bits to the DA-H register (address 00CE16), then the low-order 6 bits to the DA-L register (address 00CF16). When outputting PWM0–PWM9, set 8-bit output data to the PWMi register (i means 0 to 9; addresses 00D016 to 00D416, 00F616 to 00FA16). (2) Transferring Data from Registers to Latches The data written to the 8-bit PWM register is transferred to the PWM latch in each 8-bit PWM cycle period. For 14-bit PWM, the data is transferred in the next high-order 8-bit period after the write. The signals output to the PWM pins correspond to the contents of these latches. When data in each PWM register is read, data in these latches has already been read allowing the data output by the PWM to be confirmed. However, bit 7 of the DA-L register indicated the completion of the data transfer from the DA register to the DA latch. When bit 7 is “0,” the transfer has been completed. When bit 7 is “1,” the transfer has not yet begun. (5) Output after Reset At reset, the output of ports P60–P67, P46 and P47 are in the highimpedance state, and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register. (3) Operating of 8-bit PWM The following explains PWM operation. First, set the bit 0 of PWM output control register 1 (address 00D516) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. PWM0–PWM7 are also used as pins P60–P67, PWM8, PWM9 are also used as ports pins P47, P46, respectively. For PWM0–PWM9, set the corresponding bits of the ports P4 or P6 direction register to “1” (output mode). And select each output polarity by bit 3 of PWM output control register 2(address 00D616). Then, for PWM0–PWM5, set bits 2 to 7 of PWM output control register 1 to “1” (PWM output). For PWM6 and PWM7, set bits 0 and 1 of the PWM output control register 2 to “1.” For PWM8 and PWM9, set bits 3, 6 and 7 of the serial I/O control register to “1.” The PWM waveform is output from the PWM output pins by setting these registers. Figure 36 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (28) segments. The 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. Refer to Figure 36 (a). The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in 39 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Table 5. Relation Between the Low-order 6-bit Data and Highlevel Area Increase Interval Low-order 6 bits of Data Area Longer by τ than That of Other tm (m = 0 to 63) LSB 000000 000001 000010 000100 001000 010000 100000 Nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7, ................................. 57, 59, 61, 63 Data bus DA-L register (Address : 00CF16 ) DA-H register (Address : 00CE16 ) b7 b7 b0 b5 b0 DA latch (14-bits) MSB LSB 8 7 14 6 A-D PN2 PN4 D-A D-A/AD3 PW1 14-bit PWM circuit XIN 1/2 PW0 PWM0 register (Address : 00D0 16) Timing generator for PWM b7 b0 PWM0 latch MSB LSB 8 PN3 8-bit PWM circuit P60 PW2 P61 D60 PWM0 D61 PWM1 PWM1 register (Address : 00D1 16) PW3 P62 D62 PWM2 PWM2 register (Address : 00D2 16) Selection gate : Connected to black side at reset. Pass gate Inside of the others. is as same contents with PW4 P63 D63 PWM3 PWM3 register (Address : 00D3 16) PW5 P64 D64 PWM4 PWM4 register (Address : 00D4 16) PW : PWM output countrol register 1 PN : PWM output control register 2 D6 : Port P6 direction register D4 : port P4 direction register SIC : Serial I/O control register PW6 P65 D65 PWM5 PWM5 register (Address : 00F6 16) PW7 P66 D66 PWM6 PWM6 register (Address : 00F7 16) PN0 P67 D67 PWM7 PWM7 register (Address : 00F8 16) PN1 SRDY1 P47 D47 PWM8 PWM8 register (Address : 00F9 16) SIC3 P46 SIC6 SIC7 D46 PWM9 PWM9 register (Address : 00FA 16) Fig. 35. PWM Block Diagram 40 13579 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 20 30 40 Bit 7 46 50 54 58 86 90 94 62 66 78 82 74 70 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 2 6 10 14 18 22 26 30 34 38 42 Fig. 36. 8-bit PWM Timing 52 60 116 148 180 220 236 212 68 172 92 100 244 108 164 204 124 132 140 156 196 76 228 84 188 252 56 136 72 88 168 120 200 152 232 104 184 216 248 48 208 80 112 144 176 240 96 160 224 64 192 128 Bit 6 4 12 20 28 36 44 Bit 5 8 24 40 Bit 4 16 Bit 3 32 Bit 2 Bit 1 Bit 0 (a) Pulses showing the weight of each bit 0016 (0) 0116 (1) 1816 (24) FF16 (255) t T = 256 t PWM output t = 4 µs T = 1024 µs f(XIN) = 8 MHz (b) Example of 8-bit PWM MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER 41 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Set “2C16” to DA-H register. 0 1 b7 b6 b5 b4 b3 b2 b1 b0 [DA-H 0 0 1 0 1 1 0 0 DH register] At writing of DA-L b13 [DA latch] 0 0 1 0 1 1 0 Set “2816” to DA-L register. Latch transfer complete bit Transfer complete Transfer is not completed (Automatically set at writing) b7 b6 b5 b4 b3 b2 b1 b0 [DA-L register] 1 Undefined 0 1 0 0 0 DL At writing of DA-L b6 b5 0 b0 0 1 0 0 0 1 These bits decide “H” level area of fundamental waveform. “H” level area of fundamental waveform These bits decide smaller interval “tm” in which “H” leval area is [“H” level area of fundamental waveform + τ ]. = Minimum resolution bit width 250 ns ! High-order 8-bit value of DA latch Fundamental waveform 250 ns!44 14-bit PWM output 2C 2B 2A … 03 02 01 00 8-bit counter Waveform of smaller interval “tm” specified by low-order 6 bits 250 ns!44 14-bit PWM output 2C 2B 2A … 03 02 01 00 8-bit counter 250 ns 2D 2D FF FE FD … D6 D5 D4 D3 … 02 01 00 FF FE FD … D6 D5 D4 D3 … 02 01 00 Fundamental waveform of smaller interval “tm” which is not specified by low-order 6 bits is not changed. 250 ns!44 τ = 250 ns 14-bit PWM output t0 Low-order 6-bit output of DA latch Repeat period T = 4096 µs t1 t2 t3 t4 t5 t59 t60 t61 t62 t63 Fig. 37. 14-bit PWM (DA) Output Example (at f(XIN) = 8 MHz) 42 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER PWM Output Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 1 (PW) [Address 00D516] B Name Functions 0 DA, PWM count source 0 : Count source supply 1 : Count source stop selection bit (PW0) 1 2 3 4 5 6 7 DA/PN4 output selection bit (PW1) P60/PWM0 output selection bit (PW2) P61/PWM1 output selection bit (PW3) P62/PWM2 output selection bit (PW4) P63/PWM3 output selection bit (PW5) P64/PWM4 output selection bit (PW6) P65/PWM5 output selection bit (PW7) 0 : DA output 1 : PN4 output 0: P60 output 1: PWM0 output 0: P61 output 1: PWM1 output 0: P62 output 1: PWM2 output 0: P63 output 1: PWM3 output 0: P64 output 1: PWM4 output 0: P65 output 1: PWM5 output After reset R W RW 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW Fig. 38. PWM Output Control Register 1 PWM Output Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 2 (PN) [Address 00D6 16] B 0 1 2 3 4 Name P66/PWM6 output selection bit (PN0) P67/PWM7 output selection bit (PN1) DA output polarity selection bit (PN3) PWM output polarity selection bit (PN4) DA general-purpose output bit (PN5) Functions 0 : P6 6 output 1 : PWM6 output 0 : P6 7 output 1 : PWM7 output 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Output LOW 1 : Output HIGH After reset R W 0 0 0 0 0 RW RW RW RW RW 5 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are “0.” 7 0 R— Fig. 39. PWM Output Control Register 2 43 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER A-D COMPARATOR A-D comparator consists of 6-bit D-A converter and comparator. A-D comparator block diagram is shown in Figure 40. The reference voltage “Vref” for D-A conversion is set by bits 0 to 5 of the A-D control register 2 (address 020A16). The comparison result of the analog input voltage and the reference voltage “Vref” is stored in bit 4 of the A-D control register 1 (address 00EF16). For A-D comparison, set “0” to corresponding bits of the direction register to use ports as analog input pins. Write the data for select of analog input pins to bits 0 to 2 of the A-D control register 1 and write the digital value corresponding to Vref to be compared to the bits 0 to 5 A-D control register 2. The voltage comparison starts by writing to the A-D control register 2, and it is completed after 16 machine cycles (NOP instruction ! 8). Data bus A-D control register 1 Comparator control Bits 0 to 2 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 A-D control register 1 Analog signal switch Comparator A-D control register 2 Bit 4 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Switch tree Resistor ladder Fig. 40. A-D Comparator Block Diagram 44 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER A-D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (ADM) [Address 00EF16] B 0 to 2 Name Analog input pin selection bits (ADM0 to ADM2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0 : AD1 1 : AD2 0 : AD3 1 : AD4 0 : AD5 1 : AD6 0 : AD7 1 : AD8 After reset R W 0 RW 3, Nothing is assigned. These bits are write disable bits. 5 to 7 When these bits are read out, the values are “0.” 4 Storage bit of comparison result (ADM4) 0: Input voltage < reference voltage 1: Input voltage > reference voltage 0 Indeterminate R— R— Fig. 41. A-D Control Register 1 A-D Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2(ADC) [Address 020A16] B 0 to 5 Name D-A converter set bits (ADC0 to ADC5) b5 0 0 0 b4 0 0 0 b3 0 0 0 Functions b2 0 0 0 b1 0 0 1 b0 0 : 1/128Vcc 1 : 3/128Vcc 0 : 5/128Vcc After reset Indeterminate RW RW 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 : 123/128Vcc 0 : 125/128Vcc 1 : 127/128Vcc 0 R— 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are “ 0.” Fig. 42. A-D Control Register 2 45 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER CRT DISPLAY FUNCTIONS (1) Outline of CRT Display Functions Table 6 outlines the CRT display functions of this microcomputer. This microcomputer incorporates a CRT display circuit of 24 characters ! 3 lines. CRT display is controlled by the CRT control register. Up to 256 kinds of characters can be displayed. The colors can be specified for each character and up to 4 kinds of colors can be displayed on one screen. A combination of up to 15 colors can be obtained by using each output signal (R, G, B and I). Characters are displayed in a 12 ! 16 dots configuration to obtain smooth character patterns (refer to Figure 43). The following shows the procedure how to display characters on the CRT screen. Write the display character code in the display RAM. Specify the display color by using the color register. Write the color register in which the display color is set in the display RAM. Specify the vertical position by using the vertical position register. Specify the character size by using the character size register. Specify the horizontal position by using the horizontal position register. Write the display enable bit to the designated block display flag of the CRT control register 1. When this is done, the CRT display starts according to the input of the VSYNC signal. The CRT display circuit has an extended display mode. This mode allows multiple lines (4 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Figure 44 shows the CRT display control register 1. Figure 45 shows the block diagram of the CRT display circuit. Table 6. Outline of CRT Display Functions Parameter Number of display characters Character display area Kinds of characters Kinds of character sizes Kinds of colors Color Coloring unit Display expansion Raster coloring Character background coloring Functions 24 characters ! 3 lines 12 ! 16 dots (refer to Figure 43) 256 kinds 4 kinds 1 screen : 4 kinds, maximum 15 kinds A character Possible (multiline display) Possible (maximum 15 kinds) Possible (a character unit, 1 screen : 4 kinds, maximum 7 kinds) 46 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER 12 dots 16 dots Fig. 43. CRT Display Character Configuration CRT Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 CRT control register 1 (CC) [Address 00EA16] B 0 1 2 3 4 Name All-blocks display control bit (CC0) (See note) Block 1 display control bit (CC1) Block 2 display control bit (CC2) Block 3 display control bit (CC3) Block 1 color specification mode switch bit (CC4) Display oscillation stop bit (CC5) Scanning line double count mode flag(CC6) Fix this bit to “0.” Functions 0 : All-blocks display off 1 : All-blocks display on 0 : Block 1 display off 1 : Block 1 display on 0 : Block 2 display off 1 : Block 2 display on 0 : Block 3 display off 1 : Block 3 display on 0 : Ordinary mode 1 : 1/2-character unit color specification mode 0 : Oscillation stopped 1 : Oscillation enabled 0 : Ordinary 256 count mode 1 : Double count mode After reset R W 0 0 0 0 0 RW RW RW RW RW 5 0 RW 6 0 RW 7 0 RW Note: Display is controlled by logical product (AND) between the all-blocks display control bit and each block control bit. Fig. 44. CRT Control Register 1 47 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER OSC1 OSC2 H SYNC VSYNC (Address 00EA 16, 0208 16) CRT control register (Addresses 00E1 16 to 00E3 16) Display oscillation circuit Vertical position registers (Address 00E4 16) Character size register (Address 00E0 16) Horizontal position register (Address 00E5 16) Border selection register Display position control circuit Display control circuit RAM for display 13 bytes ! 24 characters ! 1 line + 11bytes ! 24 characters ! 2 lines ROM for display 12 dots ! 16 dots ! 256 characters Border RAM (Addresses 00E6 16 to 00E916) Color registers Shift register 12 bits Shift register 12 bits (Address 00EC 16) Output circuit CRT port control register Data bus R G B I OUT Fig. 45. Block Diagram of CRT Display Circuit 48 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (2) Display Position The display positions of characters are specified in units called a “block.” There are 3 blocks, blocks 1 to 3. Up to 24 characters can be displayed in each block (refer to (4) Memory for Display). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 64-step display positions in units of 4TC (TC = oscillating cycle for display). The display position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines. Block 2 is displayed after the display of block 1 is completed (refer to Figure 46 (a)). Accordingly, if the display of block 2 starts during the display of block 1, only block 1 is displayed. Similarly, when multiline display, block 1 is displayed after the display of block 2 is completed (refer to Figure 46 (b)). The vertical position can be specified from 128-step positions (4 scanning lines per a step) for each block by setting values “0016” to “7F16” to bits 0 to 6 in the vertical position register (addresses 00E116 to 00E316). Figure 48 shows the vertical position register. (HR) CV1 Block 1 CV2 Block 2 CV3 Block 3 (a)Example when each block is separated CV1 Block 1 CV2 Block 2 No display CV1 Block 1 (second) No display (b)Example when block 2 overlaps with block 1 Fig. 46. Display Position 49 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can select with the CRT port control register (address 00EC16). 8 machine cycles or more VSYNC signal input 0.125 to 0.50 [ µs] ( at f(XIN) = 8MHz) VSYNC control signal in microcomputer Period of counting HSYNC signal (Note 2) HSYNC signal input 8 machine cycles or more 1 2 3 4 5 Not count When bits 0 and 1 of the CRT port control register (address 00EC 16) are set to “1” (negative polarity) Notes 1 : The vertical position is determined by counting falling edge of HSYNC signal after rising edge of V SYNC control signal in the microcomputer. 2 : Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. Fig. 47. Supplement Explanation for Display Position Vertical Position Register i b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (CVi) (i = 1 to 3) [Addresses 00E116 to 00E316] B 0 to 6 7 Name Vertical display start positions (CVi : CVi0 to CVi6) Functions 128 steps (00 16 to 7F16 ) After reset RW Indeterminate R W Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” 0 R— Fig. 48. Vertical Position Register i 50 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER The horizontal position is common to all blocks, and can be set in 64 steps (where 1 step is 4TOSC, TOSC being the display oscillation period) as values “0016” to “3F16” in bits 0 to 5 of the horizontal position register (address 00E016). The structure of the horizontal position register is shown in Figure 49. Horizontal Position Register b7 b6 b5 b4 b3 b2 b1 b0 0 Horizontal position register (HR) [Address 00E016 ] B 0 to 5 6 7 Name Horizontal display start positions (HR0 to HR5) Functions 64 steps (0016 to 3F16) After reset 0 0 0 RW RW R— RW Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Fix this bit to “0.” Fig. 49. Horizontal Position Register 51 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (3) Character Size The size of characters to be displayed can be from 4 sizes for each block. Use the character size register (address 00E416) to set a character size. The character size of block 1 can be specified by using bits 0 and 1 of the character size register; the character size of block 2 can be specified by using bits 2 and 3; the character size of block 3 can be specified by using bits 4 and 5. Figure 51 shows the character size register. The character size can be selected from 4 sizes: minimum size, medium size, large size and extra large size. Each character size is determined by the number of scanning lines in the height (vertical) direction and the oscillating cycle for display (TC) in the width (horizontal) direction. The minimum size consists of [1 scanning line] ! [1TC]; the medium size consists of [2 scanning lines] ! [2TC]; the large size consists of [3 scanning lines] ! [3TC]; and the extra large size consists of [4 scanning lines] ! [4TC]. Table 7 shows the relation between the set values in the character size register and the character sizes. Minimum Medium Large Extra large Horizontal display start position Fig. 50. Display Start Position of Each Character Size (horizontal direction) 52 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Character Size Register b7 b6 b5 b4 b3 b2 b1 b0 Character size register (CS) [Address 00E4 16] B Name b1 0 0 1 1 b3 0 0 1 1 b5 0 0 1 1 Functions b0 0 : Minimum size 1 : Medium size 0 : Large size 1 : Extra large size b2 0 : Minimum size 1 : Medium size 0 : Large size 1 : Extra large size b4 0 : Minimum size 1 : Medium size 0 : Large size 1 : Extra large size After reset RW 0, 1 Character size of block 1 selection bits (CS10, CS11) Indeterminate R W 2, 3 Character size of block 2 selection bits (CS20, CS21) Indeterminate R W 4, 5 Character size of block 2 selection bits (CS30, CS31) Indeterminate R W 6 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. OUT signal output switch bit (CS7) 0 : OUT signal output 1 : MUTE signal output (See note) Indeterminate R — Indeterminate R W Note: This erases a video signal on an entire screen. Fig. 51. Character Size Register Table 7. Relation between Set Values in Character Size Register and Character Sizes Set Values of Character Size Register CSn0 0 0 1 1 CSn1 0 1 0 1 Character Size Minimum Medium Large Extra large Width (horizontal) Direction TC: Oscillating Cycle for Display 1TC 2TC 3TC 4TC Height (Vertical) Direction Scanning Lines 1 2 3 4 Note: The display start position in the horizontal direction is not affected by the character size. In other words, the horizontal display start position is common to all blocks even when the character size varies with each block (refer to Figure 50). 53 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (4) Memory for Display There are 2 types of memory for display : CRT display ROM (addresses 10000 16 t o 12FFF 16) used to store character dot data (masked) and CRT display RAM (addresses 060016 to 06D716) used to specify the colors and characters to be displayed. The following describes each type of display memory. ROM for display (addresses 1000016 to 12FFF16) The CRT display ROM contains dot pattern data for characters to be displayed. For characters stored in this ROM to be actually displayed, it is necessary to specify them by writing the character code inherent to each character (code based on the addresses in the CRT display ROM) into the CRT display RAM. The character code list is shown in Table 8. The CRT display ROM has a capacity of 12 K bytes. Since 32 bytes are required for 1 character data, the ROM can stores up to 384 kinds of characters. The CRT display ROM space is broadly divided into 2 areas. The [vertical 16 dots] ! [horizontal (left side) 8 dots] data of display characters are stored in addresses 1000016 to 107FF16, 1100016 to 117FF16 and 1200016 to 127FF16 ; the [vertical 16 dots] ! [horizontal (right side) 4 dots] data of display characters are stored in addresses 1080016 to 10FFF16, 1180016 to 11FFF16 and 1280016 to 12FFF16 (refer to Figure 52). Note however that the high-order 4 bits in the data to be written to addresses 1080016 to 10FFF16, 1180016 to 11FFF16 and 1280016 to 12FFF16 must be set to “1” (by writing data “FX16”). b7 10XX016, 11XX016, or 12XX016 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 b0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 b7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b3 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10XX016+80016, 11XX016+80016, or 12XX016+80016 10XXF 16, 11XXF16, or 12XXF 16 10XXF 16+80016, 11XXF 16+80016, or 12XXF 16+80016 Fig. 52. Display Character Stored Data 54 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Table 8. Character Code List (partially abbreviated) Character code Character data storage address Left 8 dots lines 00016 1000016 to 1000F16 1001016 to 1001F16 1002016 to 1002F16 1003016 to 1003F16 : 107E016 to 107EF16 107F016 to 107FF16 1100016 to 1100F16 1101016 to 1101F16 : 127D016 to 127DF16 127E016 to 127EF16 127F016 to 127FF16 Right 4 dots lines 1080016 to 1080F16 1081016 to 1081F16 1082016 to 1082F16 1083016 to 1083F16 : 10FE016 to 10FEF16 10FF016 to 10FFF16 1180016 to 1180F16 1181016 to 1181F16 : 12FD016 to 12FDF16 12FE016 to 12FEF16 12FF016 to 12FFF16 00116 00216 00316 : 07E16 07F16 08016 08116 : 17D16 17E16 17F16 55 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER RAM for display (addresses 060016 to 06D716) The CRT display RAM is allocated at addresses 060016 to 06D716, and is divided into a display character code specification part and display color specification part for each block. Table 9 shows the contents of the CRT display RAM. For example, to display 1 character position (the left edge) in block 1, write the character code in address 060016 and write the color register No. to the low-order 2 bits (bits 0 and 1) in address 068016. The color register No. to be written here is one of the 4 color registers in which the color to be displayed is set in advance. For details on color registers, refer to (5) Color Registers. The structure of the CRT display RAM is shown in Figure 53. Table 9. Contents of CRT Display RAM Block Display Position (from left) 1st character 2nd character Block 1 3rd character ; 22nd character 23rd character 24th character Not used 1st character 2nd character Block 2 3rd character ; 22nd character 23rd character 24th character Not used 1st character 2nd character Block 2 3rd character ; 22nd character 23rd character 24th character Not used Character Code Specification Most Significant Bit Low-order 8 bits Bit 4 at 068016 Bit 4 at 068116 Bit 4 at 068216 ; Bit 4 at 069516 Bit 4 at 069616 Bit 4 at 069716 069816 to 069F16 Bit 4 at 06A016 Bit 4 at 06A116 Bit 4 at 06A216 ; Bit 4 at 06B516 Bit 4 at 06B616 Bit 4 at 06B716 06B816 to 06BF16 Bit 4 at 06C016 Bit 4 at 06C116 Bit 4 at 06C216 ; Bit 4 at 06D516 Bit 4 at 06D616 Bit 4 at 06D716 06D816 to 06FF16 060016 060116 060216 ; 061516 061616 061716 061816 to 061F16 062016 062116 062216 ; 063516 063616 063716 063816 to 063F16 064016 064116 064216 ; 065516 065616 065716 065816 to 067F16 Color Specification 068016 068116 068216 ; 069516 069616 069716 069816 to 069F16 06A016 06A116 06A216 ; 06B516 06B616 06B716 06B816 to 06BF16 06C016 06C116 06C216 ; 06D516 06D616 06D716 06D816 to 06FF16 56 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER 7 Block 1 [Character specification] 1 st character : 0600 16 to 24th character : 0617 16 0 Character code Specify 384 characters (“000 16” to “17F16”) (Note) 0 [Color specification] 1 st character : 0680 16 to 24th character : 0697 16 4 Color register specification on left side (In ordinary · 1/2-character unit color specification mode ) b1 b0 0 0 : Color register 0 specification 0 1 : Color register 1 specification 1 0 : Color register 2 specification 1 1 : Color register 3 specification Color register specification on right side (In 1/2-character unit color specification mode) b3 b2 0 0 : Color register 0 specification 0 1 : Color register 1 specification 1 0 : Color register 2 specification 1 1 : Color register 3 specification 7 Block 2 [Character specification] 1 st character : 0620 16 to 24th character : 0637 16 (Block 3 : 064016 to 065716) 0 Character code Specify 384 characters (“000 16” to “17F16”) (Note) 0 [Color specification] 1 st character : 06A0 16 to 24th character : 06B7 16 (Block 3 : 06C016 to 06D7 16) 4 Color register specification b1 b0 0 0 : Color register 0 specification 0 1 : Color register 1 specification 1 0 : Color register 2 specification 1 1 : Color register 3 specification Note : Set values except “07E 16,” “07F16.” Fig. 53. Structure of RAM for Display 57 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (5) Color Registers The color of a displayed character can be specified by setting the color to one of the 4 registers (CO0 to CO3: addresses 00E6 16 to 00E916) and then specifying that color register with the CRT display RAM. There are 4 color outputs; R, G, B and I. By using a combination of these outputs, it is possible to set 24–1 (when no output) = 15 colors. However, since only 4 color registers are available, up to 4 colors can be disabled at one time. R, G, B and I outputs are set by using bits 0 to 3 in the color register. Bit 5 is used to specify whether a character output or blank output. Bits 4, 6 and 7 are used to specify character background color. Figure 54 shows the structure of the color register. Color Register n b7 b6 b5 b4 b3 b2 b1 b0 Color register n (CO0 to CO3) (n = 0 to 3) [Addresses 00E6 16 to 00E9 16] B 0 1 2 3 4 5 6 7 Name I signal output selection bit (COn0) B signal output selection bit (COn1) G signal output selection bit (COn2) R signal output selection bit (COn3) Functions 0 : No character is output 1 : Character is output 0 : No character is output 1 : Character is output 0 : No character is output 1 : Character is output 0 : No character is output 1 : Character is output After reset R W 0 0 0 0 0 0 (See notes 1, 2) 0 0 RW RW RW RW RW RW RW RW B signal output (background) 0 : No background color is output 1 : Background color is output (See notes 1,2) selection bit (COn4) OUT signal output control bit (COn5) 0 : Character is output 1 : Blank is output G signal output (background) 0 : No background color is output selection bit (COn6) 1 : Background color is output R signal output (background) 0 : No background color is output 1 : Background color is output selection bit (COn7) Notes 1: When bit 5 = “0” and bit 4 = “1,” there is output same as a character or border output from the OUT pin. 2: When bit 5 = “0” and bit 4= “0,” there is no output from the OUT pin. Fig. 54. Color Register n 58 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Table 10. Colorling to Character Background by R,G,B Output Signals Color Register Bit 7 (B) 0 0 0 0 1 1 1 1 Bit 6 (G) 0 0 1 1 0 0 1 1 Bit 3 (R) 0 1 0 1 0 1 0 1 RGB Output Color Black Red Green Yellow Blue Magenta Cyan White TV screen G (Green) G+B (Cyan) B (Blue) R (Red) 1 2 3 4 A Character background B (Blue) G+B (Cyan) B R (Red) C R (Red) Color registers (addresses 00E6 16 to 00E9 16) Character 1 2 3 4 A B C Bit 7 0 0 0 0 Bit 6 0 0 0 0 Bit 5 1 1 0 0 Bit 4 1 1 0 0 Bit 3 0 0 0 1 Bit 2 1 1 0 0 Bit 1 0 1 1 0 Bit 0 0 0 0 0 (R (G (OUT) background) background) (B (R) background) (G) (B) (I) Note : If border and background color are applied to a character in contact with a 12 ! 16 -dot frame in the same block, the border (1 dot) is protruded from the frame. Unwanted dots Example 12 16 Fig. 55. Display Example 59 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Table 11. Display Example of Character Background Coloring (when green is set for a character and blue is set for background color) Color registers G output COn 7 COn 6 COn 5 COn 4 COn 3 COn 2 COn1 COn0 Green B output OUT output Character output ! ! 0 0 (Note 1) 0 1 0 0 No output No output TV image is displayed on the character background. Green ! ! 0 1 (Note 1) 0 1 0 0 No output Same output Video signal and character as character A color (green) are not mixed. Green 0 0 1 1 0 1 0 0 Background —character A Blank output Blue TV image on the character background is not displayed. Green 0 0 1 0 0 1 0 0 No output Blank output Black TV image on the character background is not displayed. Notes 1: When COn5 = “0” and COn4 = “1,” there is output same as a character or border output from the OUT pin. When COn5 = “0” and COn4 = “0,” there is no output from the OUT pin. 2: The portion “A” in which character dots are displayed is not mixed with any TV video signal. 3: The wavy-lined arrows in the table denote video signals. 4: n : 0 to 3, ! : 0 or 1 60 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (6) 1/2-character Unit Color Specification Mode By setting “1” to bit 4 of CRT control register 1 (address 00EA16) it is possible to specify colors, in units of a 1/2-character size (16 dots high ! 6 dots wide), to characters in only block 1. In the 1/2-character unit color specification mode, colors of display characters in block 1 are specified as follows: • The color on the left side : this is set to the color of the color register which is specified by bits 0 and 1 at the color specification addresses (addresses 068016 to 069716) in the CRT display RAM. • The color on the right side : this is set to the color of the color register which is specified by bits 2 and 3 at the color specification addresses (addresses 068016 to 069716) in the CRT display RAM. Color of the color register specified by bits 0 and 1 at address 0680 16. Color of the color register specified by bits 0 and 1 at address 0681 16. Block 1 (a) Display in the ordinary mode Color of the color register specified by bits 0 and 1 at address 0680 16. Color of the color register specified by bits 2 and 3 at address 068016 . Color of the color register specified by bits 0 and 1 at address 068116. Color of the color register specified by bits 2 and 3 at address 0681 16. Block 2 (b) Display in the 1/2-character unit color specification mode Fig. 56. Difference between Ordinary Color Specification Mode and 1/2-character Unit Color Specification Mode 61 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (7) Character Border Function An border of 1 clock (1 dot) equivalent size can be added to a character to be displayed in both horizontal and vertical directions. The border is output from the OUT pin. Border can be specified in units of block by using the border selection register (address 00E516). The setting of the border takes priority of the setting by bit 5 of the color register, however, the border of the character to which a background color has been set cannot be output. Figure 58 shows the border selection register. Table 12 shows the relationship between the values set in the border selection register and the character border function. Fig. 57. Example of Border 62 MITSUBISHI MICR OCOMPUTERS M37207MF-XXXSP/FP , M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Border Selection Register b7 b6 b5 b4 b3 b2 b1 b0 Border selection register (MD) [Address 00E5 16] B 0 1 2 3 4 5 Name Functions After reset RW Block 1 OUT output 0 : Same output as character output border selection bit (MD10) 1 : Border output Block 1 OUT output switch bit (MD11) 0 : Border including character 1 : Border only Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W 0 R— Block 2 OUT output 0 : Same output as character output border selection bit (MD20) 1 : Border output Block 2 OUT output switch bit (MD21) 0 : Border including character 1 : Border only Block 3 OUT output 0 : Same output as character output border selection bit (MD30) 1 : Border output Block 3 OUT output switch bit (MD31) 0 : Border including character 1 : Border only 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Fig. 58. Border Selection Register Table 12. Relationship between Set Value in Border Selection Register and Character Border Function Border Selection Register MDn1 MDn1 ! 0 Functions Ordinary Example of Output R, G, B, I output OUT output R, G, B, I output OUT output R, G, B, I output OUT output 0 1 Border including character output 1 1 Border only output 63 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (8) Multiline Display This microcomputer can ordinarily display 3 lines on the CRT screen by displaying 3 blocks at different vertical positions. In addition, it can display up to 16 lines by using CRT interrupts. A CRT interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block. Note: A CRT interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display with the display control bit of the CRT control register 1 (address 00EA16), a CRT interrupt request does not occur (refer to Figure 59). Block 1 (on display) Block 2 (on display) Block 1' (on display) Block 2' (on display) “CRT interrupt request” “CRT interrupt request” “CRT interrupt request” “CRT interrupt request” On display (CRT interrupt request occurs at the end of block display) Block 1 (on display) Block 2 (on display) Block 1' (off display) Block 2' (off display) “CRT interrupt request” “CRT interrupt request” No “CRT interrupt request” No “CRT interrupt request” Off display (CRT interrupt request does not occur at the end of block display) Fig. 59. Timing of CRT Interrupt Request 64 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER The display block counter counts the number of times the display of a block has been completed, and its contents are incremented by 1 each time the display of one block is completed. To provide multi-line display, enable CRT interrupts by clearing the interrupt disable flag to “0” and setting the CRT interrupt enable bit (bit 4 of address 00FE16) to “1.” After that, process the following sequence within the CRT interrupt processing routine: ead the value of the display block counter. The block for which display is terminated (i.e., the cause of CRT interrupt generation) can be determined by the value read in . Replace the display character data and vertical display position of that block with the character data (contents of CRT display RAM) and vertical display position (contents of vertical position register) to be displayed next. Figure 60 shows the structure of the display block counter. Display Block Counter b7 b6 b5 b4 b3 b2 b1 b0 Display block counter (CBC) [Address 00EB 16] B 0 to 3 4 to 7 Name Functions After reset RW Number of blocks which are being displayed or has displayed (Incremented each time a block is displayed) Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Indeterminate R W 0 R— Fig. 60. Display Counter Count value Interrupt position Block 1 Block 2 0 1 2 Block 3 Block 1’ 3 4 Fig. 61. Timing of CRT Interrupt Request and Display Counter Value 65 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (9) Scanning Line Double Count Mode 1 dot in a displayed character is normally shown with 1 scanning line. In the scanning double count mode, 1 dot can be shown with 2 scanning lines. As a result, the displayed dot is extended 2 times the normal size in the vertical direction only (that is to say, the height of a character is extended twofold.) In addition, because the scanning line count is doubled, the display start position of a character becomes also twofold position in the vertical direction. In other words, the contents of the vertical position register is as follows: • In ordinary mode 256 steps as values “0016” to “FF16” (4 scanning lines per step) • In scanning line double count mode 128 steps as values “0016” to “7F16” (8 scanning lines per step) If the contents of the vertical position register for a block are set in the range of “8016” to “FF16” in the scanning line double count mode, that block cannot be displayed (not output to the CRT screen). The scanning line double count mode is specified by setting bit 6 of the CRT control register 1 (address 00EA16) to “1.” Since this function works in units of a screen, even if the mode is changed during display of 1 screen, the mode before the change remains until the display of the next screen. Vertical position A Scanning line 16 lines A!2 Vertical position A ! 2 Scanning line 32 lines (a) Display in the ordinary mode (b) Display in the scanning line double count mode Fig. 62. Display in Ordinary Mode and in Scanning Line Double Count Mode 66 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (10) Wipe Function Wipe mode This microcomputer allows the display area to be gradually expanded or shrunk in the vertically direction in units of 1H (H: HSYNC signal). There are 3 modes for this scroll method. Each mode has DOWN and UP modes, providing a total of 6 modes. Table 13 shows the contents of each wipe mode. Table 13. Wipe Operation in Each Mode and Values of Wipe Mode Register Wipe Mode Register Mode Wipe Operation Bit 2 Bit 1 Bit 0 DOWN 1 UP Appear from upper side Down Up Erase from lower side A G M S B H N T C I O U D J P V E K Q W F L R X 0 0 1 ON OFF 1 0 1 DOWN 2 UP Erase from upper side Down Up Appear from lower side A G M S B H N T C I O U D J P V E K Q W F L R X 0 1 0 OFF ON 1 1 0 DOWN 3 UP Erase from both upper and lower sides Down Up Appear to both upper and lower sides A G M S B H N T C I O U D J P V E K Q W F L R X 0 1 1 OFF ON OFF 1 1 1 67 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Wipe speed The wipe speed is determined by the vertical synchronization (VSYNC) signal. For the NTSC interlace method, assuming that VSYNC = 16.7 ms, 262.5 HSYNC signals (per field) we obtain the wipe speed as shown in Table 14. Wipe resolution varies with each wipe mode. In mode 1 and mode 2, one of 3 resolutions (1H, 2H, 4H) can be selected. In mode 3, wipe is done in units of 4H only. Table 14. Wipe Speed (NTSC interlace method, H = 262.5) Wipe Resolution 1H Unit 2H Unit 4H Unit Wipe Speed (entire screen) 16.7 (ms) ! 262.5 ÷ 1 16.7 (ms) ! 262.5 ÷ 2 16.7 (ms) ! 262.5 ÷ 4 4 (s) 2 (s) 1 (s) Table 15. Wipe Mode and Wipe Resolution Mode Mode 1 Mode 2 Wipe Resolution 1H Unit 2H Unit 4H Unit Mode 3 4H Unit Wipe Speed about 4 (s) about 2 (s) about 1 (s) about 1 (s) Wipe Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Wipe mode register (SL) [Address 00ED 16] B Name b1 0 0 1 1 Functions b0 0 : Wipe is not available 1 : Mode 1 0 : Mode 2 1 : Mode 3 After reset 0 RW RW 0, 1 Wipe mode selection bits (SL0, SL1) 2 Direction mode selection bits (SL2) 0: DOWN mode 1: UP mode b4 0 0 1 1 b6 0 0 1 1 b3 0 : 1H unit 1 : 2H unit 0 : 3H unit 1 : Do not set b5 0 : Stop at the 312nd H 1 : Stop at the 156th H 0 : Stop at the 256th H 1 : Stop at the 128th H 0 0 RW RW 3, 4 Wipe unit selection bits (SL3, SL4) 5, 6 Stop mode selection bits (SL5, SL6) 0 RW 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. 0 R— Fig. 63. Structure of Wipe Mode Register 68 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (11) CRT Output Pin Control The CRT output pins R, G, B, I and OUT can also function as ports P52, P53, P54, P55 and P56. Set the corresponding bit of the port P5 control register (address 00CB16) to “0” to specify these pins as CRT output pins, or set it to “1” to specify it as a general-purpose port P5 pins. The input polarity of signals HSYNC and VSYNC and output polarity of signals R, G, B, I and OUT can be specified with the bits of the CRT port control register (address 00EC16). Set a bit to “0” to specify positive polarity; set it to “1” to specify negative polarity. The CRT clock I/O pins OSC1, OSC2 are controlled with the port control register (address 020616). The CRT port control register is shown in Figure 64. The port control register is shown in Figure 65. CRT Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 CRT port control register (CRTP) [Address 00EC 16] B 0 1 2 3 4 5 6 7 Name HSYNC input polarity switch bit (HSYC) VSYNC input polarity switch bit (VSYC) R, G, B output polarity switch bit (R/G/B) I output polarity switch bit (I) OUT output polarity switch bit (OUT) R signal output switch bit (R) G signal output switch bit (G) B signal output switch bit (B) Functions 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : R signal output 1 : MUTE signal output 0 : G signal output 1 : MUTE signal output 0 : B signal output 1 : MUTE signal output After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW Fig. 64. CRT Port Control Register Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 Port control register (P7D) [Address 0206 16 ] B Name Functions When only OP1 = “0” and OP0 = ”1,” input data is valid. (See note) 0: AD3 1: D-A After reset RW 0, 1 Port P7 data input bits (P7D0, P7D1) 2 D-A/AD3 function selection bit (P7D2) Indeterminate R W 0 RW 3, Nothing is assigned. These bits are write disable bits. 5 to 7 When these bits are read out, the values are indeterminate. 4 P40/XCIN , P41/XCOUT function selection bit (P7D4) 0 : P40, P41 1 : XCIN, XCOUT 0 R— 0 RW Note: OP is the CRT clock selection register. Fig. 65. Port Control Register 69 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (12) Raster Coloring Function An entire screen (raster) can be colored by switching each of the R, G, and B pins to MUTE output. R, G, B are controlled with the CRT port control register; I is controlled with the CRT control register 2; OUT is controlled with the character size register. 15 raster colors can be obtained. If the OUT pin has been set to raster coloring output, a raster coloring signal is always output during 1 horizontal scanning period. This setting is necessary for erasing a background TV image. If the R, G, and B pins have been set to MUTE signal output, a raster coloring signal is output in the part except a no-raster colored character (in Figure 66, a character “O”) during 1 horizontal scanning period. This ensures that character colors do not mix with the raster color. In this case, MUTE signal is output from the OUT pin. An example in which a magenta character “I” and a red character “O” are displayed with blue raster coloring is shown in Figure 66. “RED” “BLUE” A A' HSYNC R B OUT Signals across A – A' Fig. 66. Example of Raster Coloring CRT Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 CRT control register 2 (CBR) [Address 0208 16] B 0 Name I signal output switch bit (CBR0) I/TIM1 function switch bit (CBR1) Functions 0: I signal output 1: MUTE signal output 0: I output or MUTE output 1: 1/2 clock ouput of timer 1 After reset 0 RW RW 1 0 RW 2 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are indeterminate. 0 R— Fig. 67. CRT Control Register 2 70 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER (13) Clock for Display As a clock for display to be used for CRT display, it is possible to select one of the following 3 types. Main clock supplied from the XIN pin Clock from the LC or RC supplied from the pins OSC1 and OSC2. Clock from the ceramic resonator or quartz-crystal oscillator supplied from the pins OSC1 and OSC2. This clock for display can be selected for each block by the CRT clock selection register (address 020916). When selecting the main clock, set the oscillation frequency to 8 MHz. • • • CRT Clock Selection Register b7 b6 b5 b4 b3 b2 b1 b0 0 CRT clock selection register (OP) [Address 020916] B Name b1 b0 1 0 Functions Functions CC6 CC6 = “0” or “1” CC6 = “0” 0 The clock for display is supplied by connecting RC or LC across the pins OSC1 and OSC2. 1 Since the main clock is used as the clock for CRT oscillation display, the oscillation frequency is limited. frequency Because of this, the character size in width = f(X IN) (horizontal) direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P7 0 and P71 respectively. 0 Do not set. After reset R W 0 RW 0, 1 CRT clock selection bits (OP0, OP1) 1 1 — CC6 = “0” 1 The clock for display is supplied by connecting the following across the pins OSC1 and OSC2. • a ceramic resonator only for CRT display and a feedback resistor • a quartz-crystal oscillator only for CRT display and a feedback resistor (See note) 0 R— 2 to 6 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Fix this bits to “0.” 0 RW Notes 1: It is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins XIN and XOUT . 2: CC6 is the scnanning line double count mode flag. Fig. 68. CRT Clock Selection Register 71 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICR OCOMPUTER f or VOL TAGE SYNTHESIZ and ON-SCREEN DISPLA Y CONTR OLLER INTERRUPT INTERVAL DETERMINATION FUNCTION This microcomputer incorporates an interrupt interval determination circuit. This interrupt interval determination circuit has an 8-bit binary up counter as shown in Figure 69. Using this counter, it determines an interval on the INT1 or INT2 (refer to Figure 72) The following describes how the interrupt interval is determined. 1. The interrupt input to be determined (INT1 input or INT2 input) is selected by using bit 2 in the interrupt interval determination control register (address 00D816). When this bit is cleared to “0,” the INT1 input is selected ; when the bit is set to “1,” the INT2 input is selected. 2. When the INT1 input is to be determined, the polarity is selected by using bit 3 of the interrupt interval determination control register ; when the INT2 input is to be determined, the polarity is selected by using bit 4 of the interrupt interval determination control register. When the relevant bit is cleared to “0,” determination is made of the interval of a positive polarity (rising transition) ; when the bit is set to “1,” determination is made of the interval of a negative polarity (falling transition). 3. The reference clock is selected by using bit 1 of the interrupt interval determination control register. When the bit is cleared to “0,” a 32 m s clock is selected ; when the bit is set to “1,” a 16 m s clock is selected (based on an oscillation frequency of 8MHz in either case). . 4. Simultaneously when the input pulse of the specified polarity (rising or falling transition) occurs on the INT1 pin (or INT2 pin), the 8-bit binary up counter starts counting up with the selected reference clock (32 m s or 16 m s). 5. Simultaneously with the next input pulse, the value of the 8-bit binary up counter is loaded into the interrupt interval determination register (address 00D716) and the counter is immediately reset (“0016”). The reference clock is input in succession even after the counter is reset, and the counter restarts counting up from “0016.” 6. When count value “FE16” is reached, the 8-bit binary up counter stops counting. Then, simultaneously when the next reference clock is input, the counter sets value “FF16” to the interrupt interval determination register. The reference clock is generated by setting bit 0 of PWM mode register 1 to “0.” 16µs 32µs RE1 INT2 (Note) INT1 (Note) RE2 8 Selection gate : Connected to black colored side at rest. Control circuit 8-bit binary up counter (8) RE0 8 Interrupt interval determination register (8) (Address 00D7 16) Data bus RE : Interrupt interval determination control register Note: The pulse width of external interrupt INT1 and INT2 needs 5 or more machine cycles. Fig. 69. Block Diagram of Interrupt Interval Determination Circuit 72 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Interrupt Interval Determination Control Register b7 b6 b5 b4 b3 b2 b1 b0 interrupt interval determination control register (RE) [Address 00D8 16] B 0 Name Interrupt interval determination circuit operation control bit (RE0) Reference clock selection bit (RE1) External interrupt input pin selection bit (RE2) INT1 pin input polarity switch bit (RE3) INT2 pin input polarity switch bit (RE4) Functions 0 : Stopped 1 : Operating 0 : 16 µs 1 : 32 µs (at f(X IN ) = 8 MHz) 0 : INT1 input 1 : INT2 input 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input After reset R W 0 RW 1 0 RW 2 3 4 5 to 7 0 0 0 0 RW RW RW R— Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Fig. 70. Interrupt Interval Determination Control Register INT1 or INT2 input Count interval Fig. 71. Measuring Interval 73 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER ROM CORRECTION FUNCTION This can correct program data in ROM. Up to 2 addresses (2 blocks) can be corrected, a program for correction is stored in the ROM correction memory in RAM. The ROM memory for correction is 32 bytes ! 2 blocks. Block 1 : addresses 02C016 to 02DF16 Block 2 : addresses 02E016 to 02FF16 Set the address of the ROM data to be corrected into the ROM correction address register. When the value of the counter matches the ROM data address in the ROM correction address, the main program branches to the correction program stored in the ROM memory for correction. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. When the blocks 1 and 2 are used in series, the above instruction is not needed at the end of the block 1. The ROM correction function is controlled by the ROM correction enable register. Notes 1 : S pecify the first address (op code address) of each instruction as the ROM correction address. 2 : Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program. 3 : Do not set the same ROM correction address to the blocks 1 and 2. ROM correction address 1 (high-order) 021716 ROM correction address 1 (low-order) 021816 ROM correction address 2 (high-order) 021916 ROM correction address 2 (low-order) 021A16 Fig. 72. ROM Correction Address Registers ROM Correction Enable Register b7 b6 b5 b4 b3 b2 b1 b0 00 ROM correction enable register (RCR) [Address 021B16] B 0 1 Name Block 1 enable bit (RC0) Block 2 enable bit (RC1) Functions 0: Disabled 1: Enabled 0: Disabled 1: Enabled After reset R W 0 0 RW RW RW R— 2, 3 Fix these bits to“0.” 4 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 0 Fig. 73. ROM Correction Enable Register 74 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER RESET CIRCUIT When the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and the power source voltage is 5 V ± 10 %, hold the ______ RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as shown in Figure 75, reset is released and the program starts from the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal state of microcomputer at reset are shown in Figure 75. An example of the reset circuit is shown in Figure 74. The reset input voltage must be kept 0.6 V or less until the power source voltage surpasses 4.5 V. Poweron 4.5 V Power source voltage 0 V Reset input voltage 0 V 0.6 V Vcc 1 5 M51953AL RESET 4 3 0.1µF Vss Microcomputer Fig. 74. Example of Reset Circuit XIN φ RESET Internal RESET SYNC Address Data 32768 count of X IN clock cycle (Note 3) ? ? ? ? 01, S 01, S-1 01, S-2 FFFE FFFF AD H, AD L Reset address from the vector table ? ? ? AD L ADH Notes 1 : f(XIN) and f( φ) are in the relation : f(X IN) = 2·f (φ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, “FF 16” is set in timer 3 and “07 16” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal. Fig. 75. Reset Sequence 75 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER CLOCK GENERATING CIRCUIT This microcomputer has 2 built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and X COUT). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and X COUT. When using X CIN-XCOUT as sub-clock, clear bits 7 and 6 of the mixing control register to “0.” To supply a clock signal externally, input it to the XIN (XCIN) pin and make the XOUT (XCOUT) pin open. When not using XCIN clock, connect the XCIN to VSS and make the X COUT pin open. After reset has completed, the internal clock φ is half the frequency of XIN. Immediately after poweron, both the X IN and XCIN clock start oscillating. To set the internal clock φ to low-speed operation mode, set bit 7 of the CPU mode register (address 00FB16) to “1.” (3) Low-Speed Mode If the internal clock is generated from the sub-clock (XCIN), a low power consumption operation can be realized by stopping only the main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU mode register (00FB16) to “1.” When the main clock XIN is restarted, the program must allow enough time to for oscillation to stabilize. Note that in low-power-consumption mode the XCIN -XCOUT drivability can be reduced, allowing even lower power consumption (20µA with f (XCIN) = 32kHz). To reduce the XCIN-X COUT drivability, clear bit 5 (CM5) of the CPU mode register (00FB16) to “0.” At reset, this bit is set to “1” and strong drivability is selected to help the oscillation to start. When an STP instruction is executed, set this bit to “1” by software before executing. Oscillation Control (1) Stop mode The built-in clock generating circuit is shown in Figure 78. When the STP instruction is executed, the internal clock φ stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and “FF16” is set in timer 3 and “0716” is set in the timer 4. Select f(XIN )/16 or f(XCIN)/16 as the timer 3 count source (set bit 0 of the timer mode register 2 to “0” before the execution of the STP instruction). Moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before execution of the STP instruction. The oscillator restarts when external interrupt is accepted. However, the internal clock φ keeps its HIGH until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. XCIN 26 Rf Microcomputer X COUT 25 Rd XIN 30 XOUT 31 CCIN CCOUT CIN COUT Fig. 76. Ceramic Resonator Circuit Example When the WIT instruction is executed, the internal clock φ stops in the “H” level but the oscillator continues running. This wait state is released at reset or when an interrupt is accepted (Note). Since the oscillator does not stop, the next instruction can be executed at once. Note: In the wait mode, the following interrupts are invalid. (1) VSYNC interrupt (2) CRT interrupt (3) f(XIN )/4096 interrupt (4) Timer 1 and 2 interrupts using TIM2 pin input as count source (5) Timer 1 interrupt using f(XIN)/4096 or f(XCIN )/4096 as count source (6) Timer 3 interrupt using TIM3 pin input as count source (7) Multi-master I2C-BUS interface interrupt (8) Timer 4 interrupt using f(XIN)/2 or f(XCIN)/2 as count souce (2) Wait mode Microcomputer XCIN XCOUT XIN Open External oscillation circuit or external pulse Vcc Vss XOUT Open External oscillation circuit Vcc Vss Fig. 77. External Clock Input Circuit Example 76 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER XCIN XCOUT P40/XCIN, P41/XCOUT function selection bit (Notes 1, 4) XIN XOUT “1” 1/2 “0” Internal system clock selection bit (Notes 1, 3) 1/8 “1” “0” Timer 3 count stop bit (Notes 1, 2) Timer 3 Timer 4 count stop bit (Notes 1, 2) Timer 4 Timer 3 count source selection bit (Notes 1,2) Timing (Internal clock) Main clock (XIN–XOUT) stop bit (Notes 1, 3) Internal system clock selection bit (Notes 1, 3) Q S S Q Q S Reset STP instruction R STP instruction WIT instruction R R Reset Interrupt disable flag I Interrupt request Notes 1: 2: 3: 4: The value at reset is “0.” Refer to the structure of timer mode register 2. Refer to the structure of CPU mode register (next page). Refer to the structure of port control register. Fig. 78. Clock Generating Circuit Block Diagram 77 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Reset High-speed operation start mode WIT instruction 8MHz oscillating 32kHz oscillating φ is stopped (HIGH) Timer operating Interrupt External INT, timer interrupt, or SI/O interrupt 8MHz oscillating 32kHz oscillating f(φ) = 4MHz STP instruction 8MHz stopped 32kHz stopped φ is stopped (HIGH) Interrupt (Note 1) External INT, or SI/O interrupt XC = 0 XC = 1 WIT instruction 8MHz oscillating 32kHz oscillating φ is stopped (HIGH) Timer operating Interrupt External INT, timer interrupt, or SI/O interrupt 8MHz oscillating 32kHz oscillating f(φ) = 4MHz STP instruction 8MHz stopped 32kHz stopped φ is stopped (HIGH) Interrupt (Note 1) External INT CM7 = 0 CM7 = 1 WIT instruction 8MHz oscillating 32kHz oscillating φ is stopped (HIGH) Timer operating (Note 3) 8MHz oscillating 32kHz oscillating f(φ) = 16kHz Interrupt STP instruction 8MHz stopped 32kHz stopped φ is stopped (HIGH) Interrupt (Note 2) CM6 = 0 The program must allow time for 8MHz oscillation to stabilize CM6 = 1 8MHz stopped 32kHz oscillating φ is stopped (HIGH) Timer operating (Note 3) WIT instruction 8MHz stopped 32kHz oscillating f(φ) = 16kHz Interrupt STP instruction 8MHz stopped 32kHz stopped φ = stopped (HIGH) Interrupt (Note 2) Port control register (Address : 0206 16) XC: P4 0/XCIN, P41/XCOUT function selection bit 0 : P4 0, P41 1 : X CIN, XCOUT CPU mode register (Address : 00FB 16) CM6 : Main clock (X IN–XOUT) stop bit 0 : Oscillating 1 : Stopped CM7 : Internal system clock selection bit 0 : X IN–XOUT selected (high-speed mode) 1 : X CIN–XCOUT selected (low-speed mode) The example assumes that 8 MHz is being applied to the X IN pin and 32 kHz to the X CIN pin. The φ indicates the internal clock. Notes 1: When the STP state is ended, a delay of approximately 8ms is automatically generated by timer 3 and timer 4. 2: The delay after the STP state ends is approximately 2s. 3: When the internal clock φ divided by 8 is used as the timer count source, the frequency of the count source is 2kHz. Fig. 79. State Transitions of System Clock 78 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER DISPLAY OSCILLATION CIRCUIT The CRT display clock oscillation circuit has a built-in clock oscillation circuits, so that a clock for CRT display can be obtained simply by connecting an LC, an RC, a quartz-crystal oscillator or a ceramic resonator across the pins OSC1 and OSC2. Which of the sub-clock or the display oscillation circuit is selected by setting bits 0 and 1 of the CRT clock selection register (address 020916). ADDRESSING MODE The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 User’s Manual for details. MACHINE INSTRUCTIONS There are 71 machine instructions. Refer to SERIES 740 User’s Manual for details. PROGRAMMING NOTES OSC1 OSC2 L C1 C2 Fig. 80. Display Oscillation Circuit AUTO-CLEAR CIRCUIT When a power source is supplied, the auto-clear function will oper______ ate by connecting the following circuit to the RESET pin. (1) The divide ratio of the timer is 1/(n+1). (2) Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. (4) An NOP instruction is needed immediately after the execution of a PLP instruction. (5) In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1 µF) directly between the VCC pin–VSS pin and the VCC pin– CNVSS pin, using a thick wire. Circuit example 1 Vcc RESET Vss Circuit example 2 RESET Vcc Vss Note : Make the level change from LOW to HIGH at the point at which the power source voltage exceeds the specified voltage. Fig. 81. Auto-clear Circuit Example 79 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (32-pin DIP type 27C101, three identical copies) PROM Programming Method The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Product M37207EFSP M37207EFFP Name of Programming Adapter PCA4762 PCA7417 The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes. To ensure proper operation after programming, the procedure shown in Figure 82 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours. Fig. 82. Programming and Testing of One Time PROM Version 80 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VI Input voltage Input voltage Parameter Power source voltage VCC CNVSS P00–P07, P10–P17, P20–P27, P30–P36, P40–P47, P60–P67, P70, P71,OSC1, XIN, HSYNC, ______ VSYNC, RESET, XCIN, AD1–AD8 P00–P07, P10–P17, P20–P27, P30–P36, P40–P45, R, G, B, I, OUT, D-A, XOUT, XCOUT, OSC2 P46, P47, P60–P67 R, G, B, I, OUT, P00–P07, P10–P17, P20–P27, P30, P31, D-A R, G, B, I, OUT, P00–P07, P10–P17, P20–P23,P30–P36, D-A P46, P47, P60–P67 P24–P27 P40–P45 Ta = 25 °C Conditions All voltages are based on VSS. Output transistors are cut off. Ratings –0.3 to 6 –0.3 to 6 –0.3 to VCC + 0.3 Unit V V V VO Output voltage –0.3 to VCC + 0.3 V VO IOH Output voltage Circuit current –0.3 to 13 0 to 1 (Note 1) V mA IOL1 Circuit current 0 to 2 (Note 2) mA IOL2 IOL3 IOL4 Pd Topr Tstg Circuit current Circuit current Circuit current Power dissipation Operating temperature Storage temperature 0 to 1 (Note 2) 0 to 10 (Note 3) 0 to 6 (Note 2) 550 –10 to 70 –40 to 125 mA mA mA mW °C °C RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) Symbol VCC VSS VIH1 Parameter Power source voltage (Note 4), During CPU, CRT operation Power source voltage HIGH input voltage P00–P07, P10–P17, P20–P27, P30–P36, P60–P67, P70, P71, HSYNC, VSYNC, ______ RESET, XIN, XCIN, OSC1, P40–P47 (including when using serial I/O) HIGH input voltage SDA3, SCL3, S DA2, SCL2, SDA1, SCL1 (When using I2C-BUS) LOW input voltage P00–P07, P10–P17, P20–P27, P30, P31, P35, P40–P47, P70, P71 LOW input voltage SDA3, SCL3, SDA2, SCL2, SDA1, SCL1 (When using I2C-BUS) ______ LOW input voltage HSYNC, VSYNC, RESET, P32–P34, P36, P41, P42, P44–P46, XIN, XCIN, OSC1 When using serial I/O; SOUT2, SCLK2, SIN2, SOUT1, SCLK1, SIN1 HIGH average output current (Note 1) R, G, B, I, OUT, D-A, P00–P07, P10–P17, P20–P27, P30, P31 LOW average output current (Note 2) R, G, B, I, OUT, D-A, P00–P07, P10–P17, P20–P23, P30–P36 LOW average output current (Note 2) P46, P47, P60–P67 LOW average output current (Note 3) P24–P27 LOW average output current (Note 2) P40–P45 Oscillation frequency (for CPU operation) (Note 5) XIN Oscillation frequency (for sub-clock operation) (Note 7)XCIN Oscillation frequency (for CRT display) (Note 6) OSC1 Input frequency TIM2, TIM3, INT1, INT2 Input frequency SCLK1, SCLK2 Input frequency SCL1, SCL2, SCL3 Min. 4.5 0 0.8VCC Limits Typ. 5.0 0 Max. 5.5 0 VCC Unit V V V VIH2 VIL1 VIL2 VIL3 0.7VCC 0 0 0 VCC 0.4 VCC 0.3 VCC 0.2 VCC V V V V IOH IOL1 IOL2 IOL3 IOL4 f(XIN) f(XCIN) fOSC fhs1 fhs2 fhs3 1 2 1 10 6 8.1 35 13 100 1 400 mA mA mA mA mA MHz kHz MHz kHz MHz kHz 7.9 29 6.0 8.0 32 81 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Symbol ICC Parameter Power source current System operation Test conditions VCC = 5.5 V, CRT OFF f(XIN) = 8 MHz CRT ON VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, CRT OFF, Low-power dissipation mode set (CM5 = “0,” CM6 = “1”) Wait mode VCC = 5.5 V, f(XIN) = 8 MHz VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 32kHz, Low-power dissipation mode set (CM5 = “0,” CM6 = “1”) Stop mode VOH HIGH output voltage R, G, B, I, OUT, P00–P07, P10–P17, P20–P27, D-A, P30, P31 LOW output voltage R, G, B, I, OUT, P00–P07, P10–P17, P20–P23, P30–P36, D-A LOW output voltage P46, P47, P60–P67 LOW output voltage P24–P27 LOW output voltage P40–P45 ______ Limits Min. Typ. 15 30 100 Max. 30 Unit mA 45 200 µA 2 60 4 100 mA µA 1 2.4 10 V 0.4 VCC = 5.5 V, f(XIN) = 0, f(XCIN) = 0 VCC = 4.5 V IOH = –0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 10.0 mA VCC = 4.5 V VCC = 5.0 V VCC = 5.0 V VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 5.5 V VO = 12 V VCC = 4.5 V IOL = 3 mA IOL = 6 mA VOL 0.4 3.0 0.4 0.5 0.5 0.6 0.7 1.3 5 V VT+–VT– Hysteresis RESET V Hysteresis (Note 8) HSYNC, VSYNC, P32, P33, P34, P36, P40–P46, ______ IIZH HIGH input leak current RESET, P00–P07, P10–P17, P20–P27, P30–P36, P40–P47, AD1–AD8 ______ µA IIZL LOW input leak current RESET, P00–P07, P10–P17, P20–P27, P30–P36, P40–P46, P60–P67, AD1–AD8 5 µA IOZH RBS HIGH output leak current P46, P47, P60–P67 I2C-BUS·BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) 10 130 µA Ω Notes 1: The total current that flows out of the IC must be 20 mA or less. 2: The total input current to IC (IOL1 + IOL2 + IOL4) must be 30 mA or less. 3: The total average input current for ports P24–P27 to IC must be 20 mA or less. 4: Connect 0.022 m F or more capacitor externally between the power source pins VCC–VSS so as to reduce power source noise. Also connect 0.068 m F or more capacitor externally between the pins VCC–CNVSS. 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. 6: Use a RC or an LC for the CRT oscillation circuit. 7: When using the sub-clock, set fCLK < fCPU/3. 8: P32–P34 ,P36 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P40–P46 have the hysteresis when these pins are used as serial I/O pins. 82 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER A-D COMPARATOR CHARACTERISTICS Symbol — — Resolution Absolute accuracy Parameter (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Test conditions Limits Min. 0 Typ. ±1 Max. 6 ±2 Unit bits LSB Note: When Vcc = 5 V, 1 LSB = 5/64 V. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS Symbol tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA tSU:STO Bus free time Hold time for START condition “L” period of SCL clock Rising time of both SCL and SDA signals Data hold time “H” period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition 250 4.7 4.0 0 4.0 300 Parameter Standard clock mode High-speed clock mode Min. 4.7 4.0 4.7 1000 Max. Min. 1.3 0.6 1.3 20+0.1Cb 0 0.6 20+0.1Cb 100 0.6 0.6 300 300 0.9 Max. Unit µs µs µs ns µs µs ns ns µs µs Note: Cb = total capacitance of 1 bus line SDA tHD:STA tSU:STO tBUF tLOW P SCL S tR tF Sr P tHD:STA tHD:DAT tHIGH tSU:DAT tSU:STA S : Start condition Sr : Restart condition P : Stop condition Fig. 83. Definition diagram of timing on multi-master I2C-BUS 83 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER PACKAGE OUTLINE 64P4B 80P6N–A 84 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH08–83B < 48B0 > Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37207MF-XXXSP/FP MITSUBISHI ELECTRIC Date : Note : Please fill in all items marked g. Receipt Section head signature Supervisor signature g ( Date : ) Customer Date issued g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37207MF-XXXSP M37207MF-XXXFP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27C101 EPROM address 000016 Product name 000F16 080016 FFFF 16 10000 16 10800 16 11000 16 11800 16 12000 16 12800 16 13000 16 1FFFF 16 ASCII code : ‘M37207MF –’ data ROM 62K bytes Character ROM 1-a Character ROM 1-b Character ROM 2-a Character ROM 2-b Character ROM 3-a Character ROM 3-b Set “FF 16” in the shaded area. (1) Write the ASCII codes that indicates the product name of “M37207MF–” to addresses 0000 16 to 000F 16. (2) EPROM data check item (Refer the EPROM data and check “ ” in the appropriate box) → Yes q Do you set “FF 16” in the shaded area (set “F 16” in the low-order 4-bit shaded area) ? q Do you write the ASCII codes that indicates the product → Yes name of “M37207MF–” to addresses 0000 16 to 000F 16 ? g 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (64P4B for M37207MF-XXXSP, 80P6N for M37207MF-XXXFP) and attach to the mask ROM confirmation form. (1/3) signature Issuance Company name TEL Submitted by Supervisor 85 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH08–83B 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37207MF-XXXSP/FP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 0000 16 to 000F 16 store the product name, and addresses 10000 16 to 12FFF 16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Write the data correctly. 1. Inputting the name of the product with the ASCII code ASCII codes ‘M37207MF-’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = ‘3’ = ‘7’ = ‘2’ = ‘0’ = ‘7’ = ‘M’ = ‘F’ = 4D 33 37 32 30 37 4D 46 16 16 16 16 16 16 16 16 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘–’ = 2 D FF FF FF FF FF FF FF 16 16 16 16 16 16 16 16 2. Inputting the character ROM Input the character ROM data by dividing it into character ROM1, character ROM2 and character ROM3. For the character ROM data, see the next page and on. (2/3) 86 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH08–83B< 48B0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37207MF-XXXSP/FP MITSUBISHI ELECTRIC The structure of character ROM (divided of 12 !16 dots font) Example Character code “k16” (k = “016” to “17F 16”) (m = “0 16” to “216”) (n= “0 16” to “7F 16”) Character ROM1 Character ROM2 Character ROM address 10000 16+m00016+n0 16+016 10000 16+m00016+n0 16+116 10000 16+m00016+n0 16+216 10000 16+m00016+n0 16+316 10000 16+m00016+n0 16+416 10000 16+m00016+n0 16+516 10000 16+m00016+n0 16+616 10000 16+m00016+n0 16+716 10000 16+m00016+n0 16+816 10000 16+m00016+n0 16+916 10000 16+m00016+n0 16+A16 10000 16+m00016+n0 16+B16 10000 16+m00016+n0 16+C16 10000 16+m00016+n0 16+D16 10000 16+m00016+n0 16+E16 10000 16+m00016+n0 16+F16 Character ROM data b7 b6 b5 b4 b3 b2 b1 b0 0016 0416 0416 0A16 0A16 1116 1116 1116 2016 2016 3F16 4016 4016 4016 0016 0016 ⇐ Character ROM address 10800 16+m00016+n016+016 10800 16+m00016+n016+116 10800 16+m00016+n016+216 10800 16+m00016+n016+316 10800 16+m00016+n016+416 10800 16+m00016+n016+516 10800 16+m00016+n016+616 10800 16+m00016+n016+716 10800 16+m00016+n016+816 10800 16+m00016+n016+916 10800 16+m00016+n016+A16 10800 16+m00016+n016+B16 10800 16+m00016+n016+C16 10800 16+m00016+n016+D16 10800 16+m00016+n016+E16 10800 16+m00016+n016+F16 ⇐ Character ROM data b 7 b6 b 5 b4 b 3 b2 b 1 b0 F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016 F16 (3/3) 87 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–49B < 61A0 > Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37207M8-XXXSP MITSUBISHI ELECTRIC Date : Receipt Section head signature Supervisor signature Note : Please fill in all items marked g. signature Issuance Company name TEL ( Date : ) Submitted by Supervisor g Customer Date issued g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37207M8-XXXSP (hexadecimal notation) Checksum code for entire EPROM EPROM type (indicate the type used) 27C101 EPROM address 000016 Product name 000F16 800016 FFFF 16 10000 16 10800 16 11000 16 11800 16 12000 16 ASCII code : ‘M37207M8 –’ data ROM 32 K bytes Character ROM 1-a Character ROM 1-b Character ROM 2-a Character ROM 2-b 1FFFF 16 Set “FF 16” (“F16” in the high-order 4-bit shaded area) in the shaded area. (1) Write the ASCII codes that indicate the product name of “M37207M8–” to addresses 0000 (2) EPROM data check item (Confirm the EPROM data and check “ ” the appropriate box) → Yes q Is “FF16” in the shaded area (set “F 16” in the high-order 4-bit shaded area) ? q Are the ASCII codes that indicates the product → Yes name of “M37207M8–” to addresses 0000 16 to 000F 16 ? g 2. Mark specification 16 to 000F 16. Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the appropriate mark specification form (64P4B for M37207M8-XXXSP) and attach to the mask ROM confirmation form. (1/3) 88 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–49B 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37207M8-XXXSP MITSUBISHI ELECTRIC How to Write the Product Name and Character ROM Data onto EPROMs Addresses 0000 16 to 000F 16 store the product name, and addresses 10000 16 to 11FFF 16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Please make sure the data is written correctly. 1. How to input the name of the product with the ASCII code : ASCII codes ‘M37207M8-’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = ‘3’ = ‘7’ = ‘2’ = ‘0’ = ‘7’ = ‘M’ = ‘8’ = 4D 33 37 32 30 37 4D 38 16 16 16 16 16 16 16 16 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘–’ = 2 D FF FF FF FF FF FF FF 16 16 16 16 16 16 16 16 2. Inputting the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data, see the next page and on. (2/3) 89 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER GZZ–SH10–49B< 61A0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37207M8-XXXSP MITSUBISHI ELECTRIC The structure of character ROM (divided of 12 !16 dots font) Example Character code “k16” (k = “0 16” to “17F 16”) (m = “0 16” to “116”) (n= “0 16” to “7F 16”) Character ROM1 Character ROM2 Character ROM address 10000 16+m00016+n0 16+016 10000 16+m00016+n0 16+116 10000 16+m00016+n0 16+216 10000 16+m00016+n0 16+316 10000 16+m00016+n0 16+416 10000 16+m00016+n0 16+516 10000 16+m00016+n0 16+616 10000 16+m00016+n0 16+716 10000 16+m00016+n0 16+816 10000 16+m00016+n0 16+916 10000 16+m00016+n0 16+A16 10000 16+m00016+n0 16+B16 10000 16+m00016+n0 16+C16 10000 16+m00016+n0 16+D16 10000 16+m00016+n0 16+E16 10000 16+m00016+n0 16+F16 Character ROM data b7 b6 b5 b4 b3 b2 b1 b0 0016 0416 0416 0A16 0A16 1116 1116 1116 2016 2016 3F16 4016 4016 4016 0016 0016 ⇐ Character ROM address 10800 16+m00016+n016+016 10800 16+m00016+n016+116 10800 16+m00016+n016+216 10800 16+m00016+n016+316 10800 16+m00016+n016+416 10800 16+m00016+n016+516 10800 16+m00016+n016+616 10800 16+m00016+n016+716 10800 16+m00016+n016+816 10800 16+m00016+n016+916 10800 16+m00016+n016+A16 10800 16+m00016+n016+B16 10800 16+m00016+n016+C16 10800 16+m00016+n016+D16 10800 16+m00016+n016+E16 10800 16+m00016+n016+F16 ⇐ Character ROM data b7 b6 b5 b4 b3 b2 b1 b0 F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016 F16 (3/3) 90 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER 64P4B (64-PIN SHRINK DIP) MARK SPECIFICATION FORM 91 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER 80P6N (80-PIN QFP) MARK SPECIFICATION FORM 92 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER APPENDIX Pin Configuration (TOP VIEW) OSC1/P7 0/AD4 OSC2/P7 1/AD5 P36/INT2/AD2 P35/AD1 P34/INT1 D-A/AD3 P60/PWM0 P61/PWM1 P62/PWM2 P63/PWM3 P64/PWM4 P65/PWM5 P66/PWM6 P67/PWM7 P33/TIM3 P32/TIM2/AD6 P31 P30 P47/SRDY1 /PWM8 P46/SIN1/PWM9 P45/SCLK1/SCL1 P44/SOUT1/SDA1 P43/SRDY2 /SCL2/AD7 P42/SIN2/SDA2/AD8 P41/SCLK2/SCL3/XCOUT P40/SOUT2/SDA3/X CIN CNV SS φ RESET 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 VCC HSYNC VSYNC R/P52 G/P53 B/P5 4 I/P5 5/TIM1 OVERFLOW OUT/P5 6 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 M37207MF-XXXSP, M37207M8-XXXSP M37207EFSP 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 XIN XOUT VSS Outline 64P4B 93 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Pin Configuration (TOP VIEW) NC I/P5 5/TIM1 OVERFLOW OUT/P5 6 P00 P01 P02 P03 P04 P05 P06 P07 NC NC 55 59 57 50 48 47 56 53 46 54 44 62 63 60 52 49 64 61 51 58 45 43 42 41 NC P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 NC B/P54 G/P53 R/P52 VSYNC HSYNC NC VCC NC OSC1/P70/AD4 OSC2/P71/AD5 NC P36/INT2/AD2 P35/AD1 P34/INT1 D-A/AD3 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 NC NC P22 P23 P24 P25 P26 P27 VSS XOUT XIN RESET φ CNVSS NC NC M37207MF-XXXFP, M37207EFFP 32 31 30 29 28 27 26 25 13 14 4 16 22 23 2 3 5 7 15 17 10 12 20 18 11 19 21 Outline 80P6N-A 94 P42/SIN2/SDA2/AD8 P41/SCLK2/SCL3/XCOUT P4φ/SOUT2/SDA3/X CIN P66/PWM6 P67/PWM7 NC NC P33/TIM3 P32/TIM2/AD6 P31 P30 P47/SRDY1 /PWM8 P46/SIN1/PWM9 NC NC P60/PWM0 P61/PWM1 P62/PWM2 P63/PWM3 P64/PWM4 P65/PWM5 P45/SCLK1/SCL1 P44/SOUT1/SDA1 P43/SRDY2 /SCL2/AD7 NC: Unconnected 24 1 6 8 9 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Memory Map 000016 ROM for display (8 K bytes) for M37207M8 1000016 RAM (960 bytes) for M37207MF RAM 00C016 (512 bytes) for M37207M8 00FF16 01FF16 Zero page SFR area ROM for display (12 K bytes) for M37207MF 11FFF16 12FFF16 Not used 020416 021B16 02C016 02FF16 030016 ROM correction memory (64 bytes) Block 1: addresses 02C0 16 to 02DF16 Block 2: addresses 02E0 16 to 02FF 16 2 page register Not used 033F16 04FF16 RAM for display (144 bytes) (See note) Not used 060016 06D716 Not used 080016 ROM (62 K bytes) for M37207MF ROM (32 K bytes) for M37207M8 800016 Not used FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF 16 Note: Refer to Table 9. Contents of CRT display RAM. 95 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Memory Map of Special Function Register (SFR) sSFR Area (addresses C016 to DF16) < Bit allocation > 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Undefined immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register b7 Bit allocation b0 b7 State immediately after reset ? 0016 ? 0016 ? 0016 ?? 0016 ? ? ?? 0016 ? 0016 ? ?? ? ? ? ? ? 0016 0016 ? 0016 ? 0016 10 0016 0016 0016 ? b0 Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) Port P4 (P4) Port P4 direction register (D4) Port P5 (P5) Port P5 control register (D5) Port P6 (P6) Port P6 direction register (D6) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) Interrupt interval determination register (??) Interrupt interval determination control register (RE) RE5 RE4 RE3 RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0 PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 PN4 PN3 PN2 PN1 PN0 0 ? ? ? ? ? 0 ? ? ? ? ? 0 0 ? ? ? ? I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2 C control register (S1D) I2C clock control register (S2) Serial I/O mode register (SM) Serial I/O regsiter (SIO) SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB PIN AL AAS AD0 LRB 0 0 0 0 0 ? 10BIT BSEL1 BSEL0 ALS ESO BC2 BC1 BC0 SAD ACK FAST ACK BIT MODE CCR4 CCR3 CCR2 CCR1 CCR0 SM6 SM5 0 SM3 SM2 SM1 SM0 96 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER s SFR Area (addresses E016 to FF16) < Bit allocation > 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Undefined immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register b7 Bit allocation b0 b7 State immediately after reset 0016 ?? ?? ?? ?? ?? 0016 0016 0016 0016 0016 0016 0016 0016 0016 ?0 FF16 0716 FF16 0716 0016 0016 ? ? ? ? ? CK0 1 1 0016 0016 0016 0016 b0 Horizontal register (HR) Vertical register 1 (CV1) Vertical register 2 (CV2) Vertical register 3 (CV3) Character size register (CS) Border selection register (MD) Color register 0 (CO0) Color register 1 (CO1) Color register 2 (CO2) Color register 3 (CO3) CRT control register 1 (CC) Display block counter (CBC) CRT port control register (CRTP) Wipe mode register (SL) Wipe start register (??) A-D control register 1 (ADM) Timer 1 (TM1) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer mode register 1 (TMR1) Timer mode register 2 (TMR2) PWM5 register (PWM5) PWM6 register (PWM6) PWM7 register (PWM7) PWM8 register (PWM8) PWM9 register (PWM9) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0 HR5 HR4 HR3 HR2 HR1 HR0 CV16 CV15 CV14 CV13 CV12 CV11 CV10 CV26 CV25 CV24 CV23 CV22 CV21 CV20 CV36 CV35 CV34 CV33 CV32 CV31 CV30 CS7 CS31 CS30 CS21 CS20 CS11 CS10 MD31 MD30 MD21 MD20 MD11 MD10 0 0 0 0 0 ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CO07 CO06 CO05 CO04 CO03 CO02 CO01 CO00 CO17 CO16 CO15 CO14 CO13 CO12 CO11 CO11 CO27 CO26 CO25 CO24 CO23 CO22 CO21 CO22 CO37 CO36 CO35 CO34 CO33 CO32 CO31 CO33 0 B CC6 CC5 CC4 CC3 CC2 CC1 CC0 G R I R/G/B VSYC HSYC SL6 SL5 SL4 SL3 SL2 SL1 SL0 ADM4 ADM2 ADM1 ADM0 0 0 0 0 0 0 TMR17 TMR16 TMR15 TMR14 TMR13 TMR12 TMR11 TMR10 TMR27 TMR26 TMR25 TMR24 TMR23 TMR22 TMR21 TMR20 CM7 CM6 CM5 1 1 CM2 0 0 0 0 1 1 0 0 IICR VSCR CRTR TM4R TM3R TM2R TM1R 0 TM56C TM56R MSR CK0 S1R IT2R IT1R IICE VSCE CRTE TM4E TM3E TM2E TM1E 0 TM56E MSE 0 SIE IT2E IT1E 97 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER sSFR Area (addresses 20416 to 21B16) < Bit allocation > < State immediately after reset > 0 : “0” immediately after reset Function bit 1 : “1” immediately after reset ? : Undefined immediately after reset : Name : : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Address 20416 20516 20616 20716 20816 20916 20A16 20B16 20C16 20D16 20E16 20F16 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 Register b7 Bit allocation b0 b7 State immediately after reset 0016 0016 00 0016 0016 0016 ?? 0016 ? ? ? ? ? ? ? ? ? ? ? 0016 0016 0016 0016 ?0 b0 Timer 5 (T5) Timer 6 (T6) Port control register (P7D) Serial I/O control register (SIC) CRT control register 2 (CBR) CRT clock selection register (OP) A-D control register (ADC) Timer mode register (TMR3) P7D4 P7D2 P7D1 P7D0 0 0 0 0 ? ? SIC7 SIC8 SIC5 SIC4 SIC3 SIC2 SIC1 SIC0 CBR1 CBR0 0 OP1OP0 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 TMR30 0 0 ? ? ? ? ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) 0 0 RC1 RC0 ? ? ? 0 0 0 98 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Internal State of Processor Status Register and Program Counter at Reset < Bit allocation > < State immediately after reset > 0 : “0” immediately after reset : Name : Function bit 1 : “1” immediately after reset ? : Undefined immediately after reset : No function bit 0 : Fix this bit to “0” (do not write “1”) 1 : Fix this bit to “1” (do not write “0”) Register b7 Processor status register (PS) Program counter (PCH) Program counter (PCL) Bit allocation b0 b7 State immediately after reset b0 N V T B D I Z C ? ????1?? Contents of address FFFF 16 Contents of address FFFE 16 99 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Structure of Register The figure of each register structure describes its functions, contents at reset, and attributes as follows: [Example] CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 11 00 Bit attributes (Note 2) Bits Values immediately after reset release (Note 1) CPU mode register (CPUM) (CM) [Address FB 16] Name 0, 1 Processor mode bits (CM0, CM1) B Functions b1 b0 After reset R W 0 RW 0 0 1 1 0: Single-chip mode 1: 0: Not available 1: 0 1 1 2 Stack page selection bit (Note) (CM2) 0: 0 page 1: 1 page RW RW RW RW 3, 4 Fix these bits to “1.” Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is “0.” b7 b6 Clock switch bits 6, 7 (CM6, CM7) 0 0: f(X IN) = 8 MHz 0 1: f(X IN) = 12 MHz 1 0: f(X IN) = 16 MHz 1 1: Do not set : Bit in which nothing is assigned Notes 1: Values immediately after reset release 0••••••“0” after reset release 1••••••“1” after reset release ?••••••Indeterminate after reset release 5 0 2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : W••••••Write R••••••Read ••••••Write enabled ••••••Read enabled ! ••••••Read disabled ! ••••••Write disabled V ••••••“0” can be set by software, but “1” cannot be set. 100 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Port Pi Direction Register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (Di) (i=0,1,2, 6) [Addresses 00C116, 00C316 , 00C516, 00CD16] B 0 1 2 3 4 5 6 7 Name Port Pi direction register Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW Port Pi Direction Register Addresses 00C116, 00C316, 00C516, 00CD16 Port P3 Direction Register b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (D3) [Address 00C716] B 0 1 2 3 4 5 6 7 Name Port P3 direction register Functions 0 : Port P30 input mode 1 : Port P30 output mode 0 : Port P31 input mode 1 : Port P31 output mode 0 : Port P32 input mode 1 : Port P32 output mode 0 : Port P33 input mode 1 : Port P33 output mode 0 : Port P34 input mode 1 : Port P34 output mode 0 : Port P35 input mode 1 : Port P35 output mode 0 : Port P36 input mode 1 : Port P36 output mode After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW R— Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Port P3 Direction Register Address 00C716 101 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Port P5 Control Register b7 b6 b5 b4 b3 b2 b1 b0 Port P5 control register (D5) [Address 00CB 16 ] B Name Functions After reset R W 0 0 0 0 0 0 R— RW RW RW RW RW 0, 1, Nothing is assigned. These bits are write disable bits. 7 When these bits are read out, the values are “0.” 2 3 4 5 6 Port P5 2 output signal selection bit (R) Port P5 3 output signal selection bit (G) Port P5 4 output signal selection bit (B) Port P5 5 output signal selection bit (I) Port P5 6 output signal selection bit (OUT) 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : I/TIM1 OVERFLOW signal output 1 : Port P55 output 0 : OUT signal output 1 : Port P56 output Port P5 Control Register Address 00CB16 PWM Output Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 1 (PW) [Address 00D516] B Name Functions 0 DA, PWM count source 0 : Count source supply 1 : Count source stop selection bit (PW0) 1 2 3 4 5 6 7 DA/PN4 output selection bit (PW1) P60/PWM0 output selection bit (PW2) P61/PWM1 output selection bit (PW3) P62/PWM2 output selection bit (PW4) P63/PWM3 output selection bit (PW5) P64/PWM4 output selection bit (PW6) P65/PWM5 output selection bit (PW7) 0 : DA output 1 : PN4 output 0: P60 output 1: PWM0 output 0: P61 output 1: PWM1 output 0: P62 output 1: PWM2 output 0: P63 output 1: PWM3 output 0: P64 output 1: PWM4 output 0: P65 output 1: PWM5 output After reset R W RW 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW PWM Output Control Register 1 Address 00D516 102 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER PWM Output Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 2 (PN) [Address 00D6 16] B 0 1 2 3 4 Name P66/PWM6 output selection bit (PN0) P67/PWM7 output selection bit (PN1) DA output polarity selection bit (PN3) PWM output polarity selection bit (PN4) DA general-purpose output bit (PN5) Functions 0 : P6 6 output 1 : PWM6 output 0 : P6 7 output 1 : PWM7 output 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Output LOW 1 : Output HIGH After reset R W 0 0 0 0 0 RW RW RW RW RW 5 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are “0.” 7 0 R— PWM Output Control Register Address 00D616 Interrupt Interval Determination Control Register b7 b6 b5 b4 b3 b2 b1 b0 interrupt interval determination control register (RE) [Address 00D8 16] B 0 Name Interrupt interval determination circuit operation control bit (RE0) Reference clock selection bit (RE1) External interrupt input pin selection bit (RE2) INT1 pin input polarity switch bit (RE3) INT2 pin input polarity switch bit (RE4) Functions 0 : Stopped 1 : Operating 0 : 16 µs 1 : 32 µs (at f(X IN ) = 8 MHz) 0 : INT1 input 1 : INT2 input 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input After reset R W 0 RW 1 0 RW 2 3 4 5 to 7 0 0 0 0 RW RW RW R— Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Interrupt Interval Determination Control Register Address 00D816 103 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER I2C Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 I C data shift register1(S0) [Address 00D9 16] 2 B 0 to 7 Name D0 to D7 Functions This is an 8-bit shift register to store receive data and write transmit data. After reset RW Indeterminate R W Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. I2C Data Shift Register Address 00D916 I2C Address Register b7 b6 b5 b4 b3 b2 b1 b0 I2C address register (S0D) [Address 00DA16] B 0 1 to 7 Name Read/write bit (RBW) Slave address (SAD0 to SAD6) 0: Read 1: Write Functions After reset R W 0 0 R— RW The address data transmitted from the master is compared with the contents of these bits. I2C Adress Register Address 00DA16 104 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER I2C Status Register b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1) [Address 00DB16] B 0 1 2 3 4 5 Name Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB) Functions 0 : Last bit = “0 ” 1 : Last bit = “1 ” 0 : No general call detected 1 : General call detected 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode After reset R W Indeterminate 0 0 0 0 0 0 R— R— R— R— R— RW RW 6, 7 Communication mode specification bits (TRX, MST) Note : These bits and flags can be read out, but cannnot be written. I2C Status Register Address 00DB16 I2C Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D : address 00DC 16 ) B 0 to 2 Name Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0:8 1:7 0:6 1:5 0:4 1:3 0:2 1:1 After reset R W 0 RW 3 4 5 I2 C-BUS interface use enable bit (ESO) Data format selection bit (ALS) Addressing format selection bit (10BIT SAD) 0 : Disabled 1 : Enabled 0 : Addressing mode 1 : Free data format 0 : 7-bit addressing format 1 : 10-bit addressing format b7 b6 Connection port (See note) 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1 SCL2, SDA2 0 0 0 0 RW RW RW RW 6, 7 Connection control bits between I2C-BUS interface and ports Note: When using ports P1 1 -P14 as I2C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output. I2C Control Register Address 00DC16 105 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER I2C Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2 C clock control register (S2 : address 00DD 16 ) B 0 to 4 Name Functions High speed clock mode After reset R W 0 SCL frequency control bits Setup value of Standard clock (CCR0 to CCR4) CCR4–CCR0 mode 00 to 02 03 04 05 06 1D 1E 1F ... RW Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3 500/CCR value 333 250 400 (See note) 166 1000/CCR value 17.2 16.6 16.1 34.5 33.3 32.3 0 (at φ = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0 : Standard clock mode 1 : High-speed clock mode 0 : ACK is returned. 1 : ACK is not returned. 0 : No ACK clock 1 : ACK clock RW RW RW 6 7 0 0 Note: At 400 kHz in the high-speed clock mode, the duty is as below . “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 I2C Clock Control Register Address 00DD16 Serial I/O Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O mode register (SM) [Address 00DE16] B Name b1 0 0 1 1 Functions b0 0: f(X IN)/4 or f(XCIN)/4 1: f(X IN)/16 or f(XCIN)/16 0: f(X IN)/32 or f(XCIN)/32 1: f(X IN)/64 or f(XCIN)/64 After reset R W 0 RW 0, 1 Internal synchronous clock selection bits (SM0, SM1) (See note 1) 2 Synchronous clock selection bit (SM2) 0: External clock 1: Internal clock b7 b3 P40/SOUT2/ P41/SCLK2/ SDA3/XCIN SCL3/X COUT !0 P40 P41 01 SOUT2 SCLK2 1 SDA3 SCL3 P43/SRDY2/ SCL2/AD7 P43 SRDY2 SDA2 0 RW 3, 7 Ports P4 0, P41 function selection bits (SM3, SM7) (See note 2) 0 RW b6 b4 P42/SIN2/ 4, 6 Ports P4 2, P43 SDA2/AD8 function selection bits 00 P42 (SM4, SM6) 1 SDA2 (See note 2) 01 P42 1 SDA2 0: LSB first 5 Transfer direction 1: MSB first selection bit (SM5) 0 RW 0 RW Notes 1: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. 2: When using ports P4 0–P4 3 as serial I/O pins, set bit 1 of the serial control register to “1.” Serial I/O Mode Register Address 00DE16 106 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Horizontal Position Register b7 b6 b5 b4 b3 b2 b1 b0 0 Horizontal position register (HR) [Address 00E0 16 ] B 0 to 5 6 7 Name Horizontal display start positions (HR0 to HR5) Functions 64 steps (0016 to 3F16) After reset 0 0 0 RW RW R— RW Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Fix this bit to “0.” Horizontal Position Register Address 00E016 Vertical Position Register i b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (CVi) (i = 1 to 3) [Addresses 00E1 16 to 00E316] B 0 to 6 7 Name Vertical display start positions (CVi : CVi0 to CVi6) Functions 128 steps (00 16 to 7F16 ) After reset RW Indeterminate R W Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” 0 R— Vertical Position Register i Addresses 00E116, 00E316 107 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Character Size Register b7 b6 b5 b4 b3 b2 b1 b0 Character size register (CS) [Address 00E4 16] B Name b1 0 0 1 1 b3 0 0 1 1 b5 0 0 1 1 Functions b0 0 : Minimum size 1 : Medium size 0 : Large size 1 : Extra large size b2 0 : Minimum size 1 : Medium size 0 : Large size 1 : Extra large size b4 0 : Minimum size 1 : Medium size 0 : Large size 1 : Extra large size After reset RW 0, 1 Character size of block 1 selection bits (CS10, CS11) Indeterminate R W 2, 3 Character size of block 2 selection bits (CS20, CS21) Indeterminate R W 4, 5 Character size of block 2 selection bits (CS30, CS31) Indeterminate R W 6 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. OUT signal output switch bit (CS7) 0 : OUT signal output 1 : MUTE signal output (See note) Indeterminate R — Indeterminate R W Note: This erases a video signal on an entire screen. Character Size Register Address 00E416 Border Selection Register b7 b6 b5 b4 b3 b2 b1 b0 Border selection register (MD) [Address 00E5 16] B 0 1 2 3 4 5 Name Functions After reset RW Block 1 OUT output 0 : Same output as character output border selection bit (MD10) 1 : Border output Block 1 OUT output switch bit (MD11) 0 : Border including character 1 : Border only Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W 0 R— Block 2 OUT output 0 : Same output as character output border selection bit (MD20) 1 : Border output Block 2 OUT output switch bit (MD21) 0 : Border including character 1 : Border only Block 3 OUT output 0 : Same output as character output border selection bit (MD30) 1 : Border output Block 3 OUT output switch bit (MD31) 0 : Border including character 1 : Border only 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Border Selection Register Address 00E516 108 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Color Register n b7 b6 b5 b4 b3 b2 b1 b0 Color register n (CO0 to CO3) (n = 0 to 3) [Addresses 00E616 to 00E9 16] B 0 1 2 3 4 5 6 7 Name I signal output selection bit (COn0) B signal output selection bit (COn1) G signal output selection bit (COn2) R signal output selection bit (COn3) Functions 0 : No character is output 1 : Character is output 0 : No character is output 1 : Character is output 0 : No character is output 1 : Character is output 0 : No character is output 1 : Character is output After reset R W 0 0 0 0 0 0 (See notes 1, 2) 0 0 RW RW RW RW RW RW RW RW B signal output (background) 0 : No background color is output 1 : Background color is output (See notes 1,2) selection bit (COn4) OUT signal output control bit (COn5) 0 : Character is output 1 : Blank is output G signal output (background) 0 : No background color is output selection bit (COn6) 1 : Background color is output R signal output (background) 0 : No background color is output 1 : Background color is output selection bit (COn7) Notes 1: When bit 5 = “0” and bit 4 = “1,” there is output same as a character or border output from the OUT pin. 2: When bit 5 = “0” and bit 4= “0,” there is no output from the OUT pin. Color Register n Addresses 00E616, 00E916 CRT Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 0 CRT control register 1 (CC) [Address 00EA 16] B 0 1 2 3 4 Name All-blocks display control bit (CC0) (See note) Block 1 display control bit (CC1) Block 2 display control bit (CC2) Block 3 display control bit (CC3) Block 1 color specification mode switch bit (CC4) Display oscillation stop bit (CC5) Scanning line double count mode flag(CC6) Fix this bit to “0.” Functions 0 : All-blocks display off 1 : All-blocks display on 0 : Block 1 display off 1 : Block 1 display on 0 : Block 2 display off 1 : Block 2 display on 0 : Block 3 display off 1 : Block 3 display on 0 : Ordinary mode 1 : 1/2-character unit color specification mode 0 : Oscillation stopped 1 : Oscillation enabled 0 : Ordinary 256 count mode 1 : Double count mode After reset R W 0 0 0 0 0 RW RW RW RW RW 5 0 RW 6 0 RW 7 0 RW Note: Display is controlled by logical product (AND) between the all-blocks display control bit and each block control bit. CRT Contol Register 1 Address 00EA16 109 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Display Block Counter b7 b6 b5 b4 b3 b2 b1 b0 Display block counter (CBC) [Address 00EB 16] B 0 to 3 4 to 7 Name Functions After reset RW Number of blocks which are being displayed or has displayed (Incremented each time a block is displayed) Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Indeterminate R W 0 R— Display Block Counter Address 00EB16 CRT Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 CRT port control register (CRTP) [Address 00EC 16] B 0 1 2 3 4 5 6 7 Name HSYNC input polarity switch bit (HSYC) VSYNC input polarity switch bit (VSYC) R, G, B output polarity switch bit (R/G/B) I output polarity switch bit (I) OUT output polarity switch bit (OUT) R signal output switch bit (R) G signal output switch bit (G) B signal output switch bit (B) Functions 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : R signal output 1 : MUTE signal output 0 : G signal output 1 : MUTE signal output 0 : B signal output 1 : MUTE signal output After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW CRT Port Control Register Address 00EC16 110 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Wipe Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Wipe mode register (SL) [Address 00ED16] B Name b1 0 0 1 1 Functions b0 0 : Wipe is not available 1 : Mode 1 0 : Mode 2 1 : Mode 3 After reset 0 RW RW 0, 1 Wipe mode selection bits (SL0, SL1) 2 Direction mode selection bits (SL2) 0: DOWN mode 1: UP mode b4 0 0 1 1 b6 0 0 1 1 b3 0 : 1H unit 1 : 2H unit 0 : 3H unit 1 : Do not set b5 0 : Stop at the 312nd H 1 : Stop at the 156th H 0 : Stop at the 256th H 1 : Stop at the 128th H 0 0 RW RW 3, 4 Wipe unit selection bits (SL3, SL4) 5, 6 Stop mode selection bits (SL5, SL6) 0 RW 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. 0 R— Wipe Mode Register Address 00ED16 A-D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (ADM) [Address 00EF16] B 0 to 2 Name Analog input pin selection bits (ADM0 to ADM2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0 : AD1 1 : AD2 0 : AD3 1 : AD4 0 : AD5 1 : AD6 0 : AD7 1 : AD8 After reset R W 0 RW 3, Nothing is assigned. These bits are write disable bits. 5 to 7 When these bits are read out, the values are “0.” 4 Storage bit of comparison result (ADM4) 0: Input voltage < reference voltage 1: Input voltage > reference voltage 0 Indeterminate R— R— A-D Control Register 1 Address 00EF16 111 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Timer Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TMR1) [Address 00F416] B Name 0 Timer 1 count source selection bit 1 (TMR10, TMR15) Functions b5 b0 After reset R W 0 RW 0 0 1 1 0: f(X IN)/16 or f(XCIN)/16 (See note) 1: f(X IN)/4096 or f(X CIN)/4096 (See note) 0: f(Xc IN) 1: External clock from TIM2 pin 0 RW 1 Timer 2 count source selection bit 1 (TMR11) Timer 1 count stop bit (TMR12) Timer 2 count stop bit (TMR13) Timer 2 count source selection bit 2 (TMR14) Timer 5 count source selection bit 2 (TMR16) Timer 6 internal count source selection bit (TMR17) 0: Count source selected by bit 4 of TM1 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 or f(X CIN)/16 (See note) 1: Timer 1 overflow 0: Timer 2 overflow 1: Timer 4 overflow 0: f(XIN)/16 or f(X CIN)/16 (See note) 1: Timer 5 overflow 2 3 4 0 0 0 RW RW RW 6 7 0 0 RW RW Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. Timer Mode Register 1 Address 00F416 Timer Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TMR2) [Address 00F516] B Name 0 Timer 3 count source selection bit (TMR20) 1 Timer 4 count source selection bit 2 (TMR21) Timer 3 count stop bit (TMR22) Timer 4 count stop bit (TMR23) Timer 4 count source selection bit 1 (TMR24) Timer 5 count stop bit (TMR25) Timer 6 count stop bit (TMR26) Timer 5 count source selection bit 1 (TMR27) Functions 0 : f(XIN)/16 or f(X CIN)/16 (See note) 1 : External clock from TIM3 pin 0 : Timer 3 overflow signal 1 : f(XIN)/16 or f(X CIN)/16 (See note) 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count source selected by bit 1 of TMR2 1 : f(X IN)/2 or f(XCIN)/2 (See note) 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Count source selected by bit 0 of TMR3 1: Count source selected by bit 6 of TMR1 After reset R W 0 RW 0 RW 2 3 4 0 0 0 RW RW RW 5 6 7 0 0 0 RW RW RW Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. Timer Mode Register 2 Address 00F516 112 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 00 1 CPU mode register (CPUM) (CM) [Address 00FB16] B Name 0, 1 Processor mode bits (CM0, CM1) Functions b1 b0 After reset R W 0 RW 0 0 1 1 0: Single-chip mode 1: 0: Not available 1: 1 1 RW RW RW 2 3 4 0: 0 page Stack page selection bit (CM2) (See note 1) 1: 1 page Fix these bits to “1.” Internal system clock output selection bit (CM4) (See note 2) 0: Output is stopped 1: Internal system clock φ output 0: LOW drive 1: HIGH drive 0: Oscillating 1: Stopped 0: X IN–XOUT selected (high-speed mode) 1: X CIN–XCOUT selected (high-speed mode) 1 5 XCOUT drivability selection bit (CM5) 6 Main Clock (X IN–XOUT) stop bit (CM6) 7 Internal system clock selection bit (CM7) 1 0 RW RW 0 RW Notes 1: This bit is set to “1” after the reset release. 2: The internal system clock φ stops at HIGH. CPU Mode Register Address 00FB16 113 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Interrupt Request Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B 0 1 2 3 4 5 6 Name Timer 1 interrupt request bit (TM1R) Timer 2 interrupt request bit (TM2R) Timer 3 interrupt request bit (TM3R) Timer 4 interrupt request bit (TM4R) CRT interrupt request bit (CRTR) V SYNC interrupt request bit (VSCR) Multi-master I 2C-BUS interface interrupt request bit (IICR) Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued After reset R W 0 0 0 0 0 0 0 RV RV RV RV RV RV RV 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” 0 R— Interrupt Reguest Register 1 Address 00FC16 Interrupt Request Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B 0 Name Functions After reset R W 0 0 0 0 0 0 0 RV RV RV R— RV RV RW INT1 interrupt 0 : No interrupt request issued request bit (ITIR) 1 : Interrupt request issued INT2 interrupt 1 0 : No interrupt request issued request bit (IT2R) 1 : Interrupt request issued 0 : No interrupt request issued 2 Serial I/O interrupt request bit (SIR) 1 : Interrupt request issued 3,6 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 4 f(XIN)/4096 interrupt 0 : No interrupt request issued request bit (MSR) 1 : Interrupt request issued Timer 5 • 6 interrupt 5 0 : No interrupt request issued request bit (TM56R) 1 : Interrupt request issued 7 Fix this bit to “0.” V: “0” can be set by software, but “1” cannot be set. Interrupt Reguest Register 2 Address 00FD16 114 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Interrupt Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B 0 1 2 3 4 5 6 Name Timer 1 interrupt enable bit (TM1E) Timer 2 interrupt enable bit (TM2E) Timer 3 interrupt enable bit (TM3E) Timer 4 interrupt enable bit (TM4E) CRT interrupt enable bit (CRTE) VSYNC interrupt enable bit (VSCE) Multi-master I 2C-BUS interface interrupt enable bit (IICE) Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 RW RW RW RW RW RW RW 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” 0 R— Interrupt Control Register 1 Address 00FE16 Interrupt Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 0 Interrupt control register 2 (ICON2) [Address 00FF16] B 0 Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Timer 5 1 : Timer 6 0 0 0 RW RW RW RW RW RW RW INT1 interrupt enable bit (IT1E) 1 INT2 interrupt enable bit (IT2E) 2 Serial I/O interrupt enable bit (SIE) 3, 6 Fix these bits to “0.” 4 5 f(XIN)/4096 interrupt enable bit (MSE) Timer 5 • 6 interrupt enable bit (TM56E) 7 Timer 5 • 6 interrupt switch bit (TM56C) Interrupt Control Register 2 Address 00FF16 115 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 Port control register (P7D) [Address 0206 16 ] B Name Functions When only OP1 = “0” and OP0 = ”1,” input data is valid. (See note) 0: AD3 1: D-A After reset RW 0, 1 Port P7 data input bits (P7D0, P7D1) 2 D-A/AD3 function selection bit (P7D2) Indeterminate R W 0 RW 3, Nothing is assigned. These bits are write disable bits. 5 to 7 When these bits are read out, the values are indeterminate. 4 P40/XCIN , P41/XCOUT function selection bit (P7D4) 0 : P40, P41 1 : XCIN, XCOUT 0 R— 0 RW Note: OP is the CRT clock selection register. Port Control Register Address 020616 Serial I/O Control Register b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIC) [Address 020716] B 0 Name Input signal to sift register selection bit (SIC0) Functions CSIO b0 0 0: Input signal from S IN1 0 1: Input signal from S OUT1 (See note 1) 1 0: Input signal from S IN2 1 1: Input signal from S OUT2 (See note 1) 0: SOUT1,SCLK1, SIN1, SRDY1 1: SOUT2,SCLK2, SIN2, SRDY2 0: SDA2, SCL2, SDA1, SCL1 1: SDA3, SCL3 b7 b3 0! 10 1 P47/SRDY1/PWM8 P47 SRDY1 PWM8 After reset R W 0 RW 1 2 Serial I/O pin switch bit (CSIO) I2C-BUS connection ports switch bit (SIC2) 0 0 RW RW 3, 7 Ports P47 function selection bits (SM3, SM7) (See note 2) 0 RW b5 b4 P44/SOUT1/ P45/SCLK1/ 4, 5 Ports P44, P45 SDA1 SCL1 function selection bits 0! P44 P45 (SM4, SM6) 10 SOUT1 SCLK1 (See note 2) 1 SDA1 SCL1 b6 P46/SIN1/PWM9 Ports P46 function 6 0 P46 selection bits 1 PWM9 (SIC6) (See note 2) 0 RW 0 RW Notes 1: When inputting data from the S out pin, set “FF 16” to the serial I/O register. 2: When using ports P4 4–P4 7 as serial I/O pins, set bit 1 of the serial I/O control register to “0.” Serial I/O Control Register Address 020716 116 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER CRT Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 CRT control register 2 (CBR) [Address 020816] B 0 Name I signal output switch bit (CBR0) I/TIM1 function switch bit (CBR1) Functions 0: I signal output 1: MUTE signal output 0: I output or MUTE output 1: 1/2 clock ouput of timer 1 After reset 0 RW RW 1 0 RW 2 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are indeterminate. 0 R— CRT Control Register 2 Address 020816 CRT Clock Selection Register b7 b6 b5 b4 b3 b2 b1 b0 0 CRT clock selection register (OP) [Address 020916] B Name b1 b0 1 0 Functions Functions CC6 CC6 = “0” or “1” CC6 = “0” 0 The clock for display is supplied by connecting RC or LC across the pins OSC1 and OSC2. 1 Since the main clock is used as the clock for CRT oscillation display, the oscillation frequency is limited. frequency Because of this, the character size in width = f(X IN) (horizontal) direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P7 0 and P71 respectively. 0 Do not set. After reset R W 0 RW 0, 1 CRT clock selection bits (OP0, OP1) 1 1 — CC6 = “0” 1 The clock for display is supplied by connecting the following across the pins OSC1 and OSC2. • a ceramic resonator only for CRT display and a feedback resistor • a quartz-crystal oscillator only for CRT display and a feedback resistor (See note) 0 R— 2 to 6 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Fix this bits to “0.” 0 RW Notes 1: It is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins XIN and XOUT . 2: CC6 is the scnanning line double count mode flag. CRT Clock Selection Register Address 020916 117 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER A-D Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2(ADC) [Address 020A 16] B 0 to 5 Name D-A converter set bits (ADC0 to ADC5) b5 0 0 0 b4 0 0 0 b3 0 0 0 Functions b2 0 0 0 b1 0 0 1 b0 0 : 1/128Vcc 1 : 3/128Vcc 0 : 5/128Vcc After reset Indeterminate RW RW 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 : 123/128Vcc 0 : 125/128Vcc 1 : 127/128Vcc 0 R— 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are “ 0.” A-D Control Register 2 Address 020A16 Timer Mode Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 3 (TMR3) [Address 020B16 ] B Name 0 Timer 5 count source selection bit 3 (TMR30) Functions 0 : f(XIN)/16 or f(X CIN)/16 (See note) 1 : f(XCIN) After reset R W 0 RW 1 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are “0.” 7 0 R— Note: Either f(X IN) or f(X CIN) is selected by bit 7 of the CPU mode register. Timer Mode Register 3 Address 020B16 118 MITSUBISHI MICROCOMPUTERS M37207MF-XXXSP/FP, M37207M8-XXXSP M37207EFSP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER and ON-SCREEN DISPLAY CONTROLLER ROM Correction Enable Register b7 b6 b5 b4 b3 b2 b1 b0 00 ROM correction enable register (RCR) [Address 021B 16] B 0 1 Name Block 1 enable bit (RC0) Block 2 enable bit (RC1) Functions 0: Disabled 1: Enabled 0: Disabled 1: Enabled After reset R W 0 0 RW RW RW R— 2, 3 Fix these bits to“0.” 4 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 0 ROM Correction Enable Register Address 021B16 119 Keep safety first in your circuit designs! • Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials • • • These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. • • • • © 1997 MITSUBISHI ELECTRIC CORP. New publication, effective Dec. 1997. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 1.1 First Edition Correct note (P76) M37207MF-XXXSP/FP, M37207M8-XXXSP, M37207EFSP/FP DATA SHEET Revision Description Rev. date 971212 980731 (1/1)