M37221M6

To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI MICROCOMPUTERS MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER with ON-SCREEN DISPLAY CONTROLLER DESCRIPTION The M37221M6-XXXSP is a single-chip microcomputer designed with CMOS silicon gate technology. It is housed in a 42-pin shrink plastic molded DIP. In addition to their simple instruction sets, the ROM, RAM and I/O addresses are placed on the same memory map to enable easy programming. The M37221M6-XXXSP has a PWM output function and a OSD display function, so it is useful for a channel selection system for TV. PIN CONFIGURATION (TOP VIEW) HSYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNVSS XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5 P31/A-D6 RESET OSC1/P33 OSC2/P34 VCC M37221M6-XXXSP FEATURES • Number of basic instructions ..................................................... 71 • Memory size ROM ........................................................ 24 K bytes RAM .......................................................... 384 bytes ROM for display ......................................... 8 K bytes RAM for display .......................................... 96 bytes The minimum instruction execution time .......................................... 0.5 s (at 8 MHz oscillation frequency) Power source voltage .................................................. 5 V ± 10 % Power dissipation............................................................. 165 mW (at 8 MHz oscillation frequency, VCC =5.5V, at CRT display) Subroutine nesting ....................................... 96 levels (maximum) Interrupts ....................................................... 14 types, 14 vectors 8-bit timers .................................................................................. 4 Programmable I/O ports (Ports P0, P1, P2, P30–P32 ) .............. 27 Input ports (Ports P33, P3 4) ......................................................... 2 Output ports (Ports P52–P55) ...................................................... 4 12 V withstand ports .................................................................... 6 LED drive ports ........................................................................... 4 Serial I/O ............................................................ 8-bit ! 1 channel Multi-master I2C-BUS interface ............................... 1 (2 systems) A-D comparator (6-bit resolution) ................................ 6 channels PWM output circuit ......................................... 14-bit ! 1, 8-bit ! 6 • • • • • • • • • • • • • • • Outline 42P4B • CRT display function Number of display characters ................ 24 characters ! 2 lines (16 lines maximum) Kinds of characters ..................................................... 256 kinds Dot structure .......................................................... 12 ! 16 dots Kinds of character sizes .................................................. 3 kinds Kinds of character colors (It can be specified by the character) maximum 7 kinds (R, G, B) Kinds of character background colors (It can be specified by the character) maximum 7 kinds (R, G, B) Kinds of raster colors (maximum 7 kinds) Display position Horizontal .................................................................. 64 levels Vertical .................................................................... 128 levels Bordering (horizontal and vertical) APPLICATION TV 1 SDA SCL SIN SCLK SOUT PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 P0 (8 ) INT3 P1 (8 ) P3 (3 ) P2 (8 ) INT2 INT1 OUT2 OUT1 B G R 17 26 27 39 40 41 42 10 9 8 7 6 5 4 3 28 29 30 31 32 33 34 35 15 14 13 12 11 36 37 38 16 MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER M37221M6-XXXSP I/O port P0 I/O port P1 I/O port P2 D-A I/O ports P30–P32 Output ports P52–P55 VSYNC HSYNC 21 2 VCC VSS 21 18 24 23 FUNCTIONAL BLOCK DIAGRAM of M37221M6-XXXSP Clock input Clock output XIN XOUT ( ) Timing output CNVSS 25 22 Reset input RESET Input ports P33, P34 Clock input for display Clock output for display OSC1 OSC2 19 20 Clock generating circuit TIM2 TIM3 Data bus Timer count source selection circuit Timer 1 T1 (8) Timer 2 T2 (8) Timer 3 T3 (8) Control signal Instruction decoder Instruction register (8) CRT circuit Timer 4 T4 (8) RAM 384 bytes Program counter Program counter ROM 24 K bytes PCH (8) PCL (8) Address bus 8-bit arithmetic and logical unit Index register X (8) Index register Y (8) Stack pointer S (8) Accumulator A (8) Processor status register PS (8) A-D comparator 14-bit PWM circuit Multi-master I2C-BUS interface SI/O(8) 8-bit PWM circuit P5 (4) MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER FUNCTIONS Parameter Number of basic instructions Instruction execution time Clock frequency Memory size ROM RAM CRT ROM CRT RAM Input/Output ports P0 P10, P15–P1 7 P11–P14 P20, P21 P22–P27 P30, P31 P32 P33, P34 P52–P55 Serial I/O Multi-master I2C-BUS interface A-D comparator PWM output circuit Timers Subroutine nesting Interrupt I/O I/O I/O I/O I/O I/O I/O Input Output 71 0.5 µs (the minimum instruction execution time, at 8 MHz oscillation frequency) 8 MHz (maximum) 24 K bytes 384 bytes 8 K bytes 96 bytes 8-bit ! 1 (N-channel open-drain output structure, can be used as PWM output pins, INT input pins, A-D input pin) 4-bit ! 1 (CMOS input/output structure, can be used as CRT output pin, A-D input pins, INT input pin) 4-bit ! 1 (CMOS input/output or N-channel open-drain output structure, can be used as multi-master I2 C-BUS interface) 2-bit ! 1 (CMOS input/output or N-channel open-drain output structure, can be used as serial output pins) 6-bit ! 1 (CMOS input/output structure, can be used as serial input pin, external clock input pins) 2-bit ! 1 (CMOS input/output or N-channel open-drain output structure, can be used as A-D input pins) 1-bit ! 1 (N-channel open-drain output structure) 2-bit ! 1 (can be used as CRT display clock I/O pins) 4-bit ! 1 (CMOS output structure, can be used as CRT output pins) 8-bit ! 1 1 (2 systems) 6 channels (6-bit resolution) 14-bit ! 1, 8-bit ! 6 8-bit timer ! 4 96 levels (maximum) External interrupt ! 3, Internal timer interrupt ! 4, Serial I/O interrupt ! 1, CRT interrupt ! 1 , Multi-master I 2C-BUS interface interrupt ! 1 , f(XIN)/4096 interrupt ! 1, VSYNC interrupt ! 1, BRK interrupt ! 1 2 built-in circuits (externally connected a ceramic resonator or a quartzcrystal oscillator) 5 V ± 10 % CRT ON CRT OFF In stop mode Operating temperature range Device structure Package CRT display function Number of display characters Dot structure Kinds of characters Kinds of character sizes Kinds of character colors Display position (horizontal, vertical) 165 mW typ. (at oscillation frequency f CPU = 8 MHz, fCRT = 8 MHz) 110 mW typ. (at oscillation frequency f CPU = 8 MHz) 1.65 mW (maximum) –10 °C to 70 °C CMOS silicon gate process 42-pin shrink plastic molded DIP 24 characters ! 2 lines (maximum 16 lines by software) 12 ! 16 dots 256 kinds 3 kinds Maximum 7 kinds (R, G, B); can be specified by the character 64 levels (horizontal) ! 128 levels (vertical) Functions Clock generating circuit Power source voltage Power dissipation 3 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PIN DESCRIPTION Pin VCC , VSS. CNVSS RESET Name Power source Input/ Output Functions Apply voltage of 5 V ± 10 % (typical) to V CC, and 0 V to VSS. CNVSS Reset input Input This is connected to V SS. To enter the reset state, the reset input pin must be kept at a “L” for 2 µ s or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this “L” condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins X IN and XOUT. If an external clock is used, the clock source should be connected to the XIN pin and the X OUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is N-channel open-drain output. The note out of this Table gives a full of port P0 function. Pins P00 –P05 are also used as PWM output pins PWM0–PWM5 respectively. The output structure is N-channel open-drain output. Pins P06 , P07 are also used as external interrupt input pins INT2, INT1 respectively. P06 pin is also used as analog input pin A-D4. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P10 is also used as CRT output pin OUT2. The output structure is CMOS output. Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I 2C-BUS interface is used. The output structure is N-channel open-drain output. Pins P1 5–P17 are also used as analog input pins A-D1 to A-D3 respectively. P15 pin is also used as external interrupt input pin INT3. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P23 , P24 are also used as external clock input pins TIM3, TIM2 respectively. P20 pin is also used as serial I/O synchronizing clock input/output pin SCLK. XIN XOUT P00/PWM0– P05/PWM5, P06/INT2/ A-D4, P07/INT1 Clock input Clock output I/O port P0 Input Output I/O PWM output External interrupt input Analog input Output Input Input I/O Output I/O Input Input I/O Input I/O P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/A-D1/ INT3, P16/A-D2, P17/A-D3 P20/SCLK, P21/SOUT, P22/SIN, P23/TIM3, P24/TIM2, P25–P2 7 I/O port P1 CRT output Multi-master I 2C-BUS interface Analog input External interrupt input I/O port P2 External clock input Serial I/O synchronizing clock input/ output Serial I/O data input/output I/O I/O Pins P2 1, P22 are also used as serial I/O data input/output pins SOUT, S IN respectively. The output structure is N-channel open-drain output. Ports P3 0–P32 are a 3-bit I/O port and has basically the same functions as port P0. Either CMOS output or N-channel open-drain output structure can be selected as the port P30 and P31. The output structure of port P32 is N-channel open-drain output. Pins P3 0, P31 are also used as analog input pins A-D5, A-D6 respectively. Ports P3 3, P3 4 are a 2-bit input port. P33 pin is also used as CRT display clock input pin OSC1. P3 4 pin is also used as CRT display clock output pin OSC2. The output structure is CMOS output. P30/A-D5, P31/A-D6, P32 I/O port P3 Analog input P33/OSC1, Input port P3 P34/OSC2 Clock input for CRT display Clock output for CRT display Input Input Input Output 4 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PIN DESCRIPTION (continued) P52/R, P53/G, P54/B, P55/OUT1 HSYNC VSYNC D-A Output port P5 CRT output HSYNC input VSYNC input DA output Output Output Input Input Output Ports P52–P5 5 are a 4-bit output port. The output structure is CMOS output. Pins P52–P55 are also used as CRT output pins R, G, B, OUT1 respectively. The output structure is CMOS output. This is a horizontal synchronizing signal input for CRT. This is a vertical synchronizing signal input for CRT. This is a 14-bit PWM output pin. Note : As shown in the memory map (Figure 3), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0 direction register (address 00C116 of zero page) which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. 5 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The M37221M6-XXXSP uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 User’s Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instruction can be used. CPU Mode Register The CPU mode register contains the stack page selection bit. The CPU mode register is allocated at address 00FB 16. 7 11 1 11 0 00 CPU mode register (CPUM : address 00FB16) Fix these bits to “0.” Stack page selection bit (Note) 0 : Zero page 1 : 1 page Fix these bits to “1.” Note : Please beware of this bit when programming because it is set to “1” after the reset release. Fig. 1. Structure of CPU mode register 6 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER MEMORY Special Function Register (SFR) Area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM ROM is used for storing user programs as well as the interrupt vector area. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. RAM for Display RAM for display is used for specifying the character codes and colors to display. ROM for Display ROM for display is used for storing character data. 000016 Zero page RAM (384 bytes) 00C016 SFR area 00FF16 ROM for display (8 K bytes) 1000016 11FFF16 01BF16 Not used RAM for display (Note) (96 bytes) 060016 06B716 Not used A00016 Not used ROM (24 K bytes) FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 11. Contents of CRT display RAM. Fig. 2. Memory map 7 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16 Port P0 Port P0 direction register Port P1 Port P1 direction register Port P2 Port P2 direction register Port P3 Port P3 direction register Port P5 Port P5 direction register Port P3 output mode control register DA-H register DA-L register PWM0 register PWM1 register PWM2 register PWM3 register PWM4 register PWM output control register 1 PWM output control register 2 I2C data shift register I 2C address register I 2C status register I2 C control register I2C clock control register Serial I/O mode register Serial I/O register 00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 Horizontal position register Vertical position register 1 Vertical position register 2 Character size register Border selection register Color register 0 Color register 1 Color register 2 Color register 3 CRT control register CRT port control register CRT clock selection register A-D control register 1 A-D control register 2 ^} C Timer 11 Timer 2 ^} C 2 ^} C 3 Timer 3 Timer 4 ^} C 4 Timer 12 mode register Timer 34 mode register PWM5 register PWM5 Interrupt input polarity register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Fig. 3. Memory map of special function register (SFR) 8 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER INTERRUPTS Interrupts can be caused by 14 different sources consisting of 4 external, 8 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities shown in Table 1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, (1) The contents of the program counter and processor status register are automatically stored into the stack. (2) The interrupt disable flag I is set to “1” and the corresponding interrupt request bit is set to “0.” (3) The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to “1.” All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figure 4 shows the structure of the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,” and the interrupt disable flag is “0.” The interrupt request bit can be set to “0” by a program, but not set to “1.” The interrupt enable bit can be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 5 shows interrupt control. Interrupt Causes (1) VSYNC and CRT interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The CRT interrupt occurs after character block display to the CRT is completed. (2) INT1, INT2, INT3 interrupts With an external interrupt input, the system detects that the level of a pin changes from “L” to “H” or from “H” to “L,” and generates an interrupt request. The input active edge can be selected by bits 3, 4 and 5 of the interrupt input polarity register (address 00F9 16) : when this bit is “0,” a change from “L” to “H” is detected; when it is “1,” a change from “H” to “L” is detected. Note that all bits are cleared to “0” at reset. (3) Timer 1, 2, 3 and 4 interrupts An interrupt is generated by an overflow of timer 1, 2, 3 or 4. (4) Serial I/O interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(XIN)/4096 interrupt This interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM output control register 1 to “0.” (6) Multi-master I2C-BUS interface interrupt This is an interrupt request related to the multimaster I 2C-BUS interface. (7) BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable). Table 1. Interrupt vector addresses and priority Interrupt source Reset CRT interrupt INT2 interrupt INT1 interrupt Timer 4 interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt Serial I/O interrupt Multi-master I2C-BUS interface interrupt INT3 interrupt BRK instruction interrupt Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Vector addresses FFFF16 , FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16 , FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFDF16 , FFDE16 Active edge selectable Non-maskable (software interrupt) Active edge selectable Active edge selectable Active edge selectable Non-maskable Remarks 9 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 7 0 Interrupt request register 1 (IREQ1 : address 00FC16) Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit CRT interrupt request bit VSYNC interrupt request bit Multi-master I 2 C-BUS interface interrupt request bit INT3 interrupt request bit 7 0 0 Interrupt request register 2 (IREQ2 : address 00FD16) INT1 interrupt request bit INT2 interrupt request bit Serial I/O interrupt request bit f(XIN)/4096 interrupt request bit Fix this bit to “0.” 0 : No interrupt request issued 1 : Interrupt request issued 7 0 Interrupt control register 1 (ICON1 : address 00FE16) Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit CRT interrupt enable bit VSYNC interrupt enable bit Multi-master I2C-BUS interface interrupt enable bit INT3 interrupt enable bit 7 000 0 0 Interrupt control register 2 (ICON2 : address 00FF16) INT1 interrupt enable bit INT2 interrupt enable bit Serial I/O interrupt enable bit Fix this bit to “0.” f(XIN)/4096 interrupt enable bit Fix these bits to “0.” 0 : Interrupt disabled 1 : Interrupt enabled 7 0 00 0 Interrupt input polarity register (RE : address 00F916) Fix these bits to “0.” INT1 polarity switch bit 0 : Positive polarity 1 : Negative polarity INT2 polarity switch bit 0 : Positive polarity 1 : Negative polarity INT3 polarity switch bit 0 : Positive polarity 1 : Negative polarity Fix this bit to “0.” Fig. 4. Structure of interrupt-related registers 10 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Fig. 5. Interrupt control 11 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER TIMERS The M37221M6-XXXSP has 4 timers: timer 1, timer 2, timer 3, and timer 4. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 7. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. The value is set to a timer at the same time by writing a count value to the corresponding timer latch (addresses 00F016 to 00F316). The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse after the count value reaches “0016”. (1) Timer 1 Timer 1 can select one of the following count sources: f(XIN)/16 f(XIN)/4096 The count source of timer 1 is selected by setting bit 0 of the timer 12 mode register (address 00F416). Timer 1 interrupt request occurs at timer 1 overflow. At reset, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. The f(X IN)/16 is selected as the timer 3 count source. The internal reset is released by timer 4 overflow at these state, the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF16 ” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN)/16 is not selected as the timer 3 count source. So set bit 0 of the timer 34 mode register (address 00F516) to “0” before the execution of the STP instruction (f(XIN)/16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow at these state, the internal clock is connected. Because of this, the program starts with the stable clock. The structure of timer-related registers is shown in Figure 6. • • (2) Timer 2 Timer 2 can select one of the following count sources: f(XIN)/16 Timer 1 overflow signal External clock from the P24 /TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of the timer 12 mode register (address 00F416 ). When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow. • • • (3) Timer 3 Timer 3 can select one of the following count sources: f(XIN)/16 External clock from the HSYNC pin External clock from the P23 /TIM3 pin The count source of timer 3 is selected by setting bits 5 and 0 of the timer 34 mode register (address 00F516 ) Timer 3 interrupt request occurs at timer 3 overflow. • • • (4) Timer 4 Timer 4 can select one of the following count sources: f(XIN)/16 f(XIN)/2 Timer 3 overflow signal The count source of timer 3 is selected by setting bits 4 and 1 of the timer 34 mode register (address 00F516 ). When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. • • • 12 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 7 0 0 Timer 12 mode register (T12M : address 00F416) 7 0 Timer 34 mode register (T34M : address 00F516) Timer 1 count source selection bit 0 : f(XIN)/16 1 : f(XIN)/4096 Timer 3 count source selection bit 0 : f(XIN)/16 1 : External clock Timer 2 count source selection bit 0 : Internal clock 1 : External clock from P24/TIM2 pin Timer 4 internal count source selection bit 0 : Timer 3 overflow 1 : f(XIN)/16 Timer 1 count stop bit 0 : Count start 1 : Count stop Timer 3 count stop bit 0 : Count start 1 : Count stop Timer 4 count stop bit 0 : Count start 1 : Count stop Timer 2 count stop bit 0 : Count start 1 : Count stop Timer 2 internal count source selection bit 0 : f(XIN)/16 1 : Timer 1 overflow Timer 4 count source selection bit 0 : Internal clock 1 : f(XIN)/2 Fix this bit to “0.” Timer 3 external count source selection bit 0 : External clock from P23/TIM3 pin 1 : External clock from HSYNC pin Fig. 6. Structure of timer-related registers 13 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Data bus 8 1/4096 Timer 1 latch (8) 8 XIN 1/2 1/8 T12M0 T12M2 Timer 1 (8) 8 T12M4 8 Timer 1 interrupt request Timer 2 latch (8) 8 P24/TIM2 T12M1 T12M3 8 8 FF16 P23/TIM3 T34M5 Timer 3 latch (8) 8 Timer 3 (8) T34M0 T34M2 8 8 0716 Timer 4 latch (8) 8 Timer 4 (8) T34M4 T34M3 8 Timer 4 interrupt request Timer 3 interrupt request Timer 2 (8) Timer 2 interrupt request HSYNC Reset STP instruction Selection gate : Connected to black colored side at reset T34M1 T12M : Timer 12 mode register T34M : Timer 34 mode register Notes 1: “H” pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used. Fig. 7. Timer block diagram 14 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER SERIAL I/O The M37221M6-XXXSP has a built-in serial I/O which can either transmit or receive 8-bit data in serial in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8. The synchronizing clock I/O pin (SCLK), and data I/O pins (SOUT, SIN) also function as port P2. Bit 2 of the serial I/O mode register (address 00DC16) selects whether the synchronizing clock is supplied internally or externally (from the P2 0/SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN ) is divided by 4, 16, 32, or 64. Bit 3 selects whether port P2 is used for serial I/O or not. To use the P22/SIN pin as the SIN pin, set the bit 2 of the port P2 direction register (address 00C5 16) to “0.” The operation of the serial I/O function is described below. The function of the serial I/O differs depending on the clock source; external clock or internal clock. Data bus XIN 1/2 1/2 Frequency divider 1/4 1/8 1/16 SM2 S SM1 SM0 Synchronization circuit Selection gate : Connected to black colored side at reset. SM : Serial I/O mode register P20 latch P20/SCLK SM3 P21 latch P21/SOUT SM3 P22/SIN SM6 SM5 : LSB MSB (Note) Serial I/O shift register (8) (Address 00DD16) 8 Serial I/O counter (8) Serial I/O interrupt request Note : When the data is set in the serial I/O register (address 00DD16), the register functions as the serial I/O shift register. Fig. 8. Serial I/O block diagram 15 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Internal clock—the serial I/O counter is set to “7” during write cycle into the serial I/O register (address 00DD16), and transfer clock goes “H” forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at “H.” At this time the interrupt request bit is set to “1.” External clock—when an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has counted 8 times. However, transfer operation does not stop, so control the clock externally. Use the external clock of 1MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 10. When using an external clock for transfer, the external clock must be held at “H” for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching. Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions as SEB and CLB instructions. 2: When an external clock is used as the synchronizing clock, write transmit data to the serial I/O register at “H” of the transfer clock input level. 7 0 0 Serial I/O mode register (SM : address 00DC16) Internal synchronizing clock selection bits b1 b0 0 0 : f(XIN)/4 0 1 : f(XIN)/16 1 0 : f(XIN)/32 1 1 : f(XIN)/64 Synchronizing clock selection bit 0 : External clock 1 : Internal clock Serial I/O port selection bit 0 : P20, P21 functions as port 1 : SCLK, SOUT Fix this bit to “0.” Transfer direction selection bit 0 : LSB first 1 : MSB first Serial input pin selection bit 0 : Input signal from SIN pin 1 : Input signal from SOUT pin Fig. 9. Structure of serial I/O mode register Synchroninzing clock Transfer clock Serial I/O register write signal Serial I/O output SOUT Serial I/O input SIN D0 D1 D2 D3 D4 D5 D6 D7 (Note) Interrupt request bit is set to “1” Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed. Fig. 10. Serial I/O timing (for LSB first) 16 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (1) Serial I/O Common Transmission/Reception Mode By writing “1” to bit 6 of the serial I/O mode register, signals SIN and SOUT are switched internally to be able to transmit or receive the serial data. Figure 11 shows signals on serial I/O common transmission/reception mode. Note: When receiving the serial data after writing “FF16” to the serial I/O register. P20/SCLK Clock P21/SOUT “1” Serial I/O shift register (8) P22/SIN “0” SM6 SM : Serial I/O mode register Fig. 11. Signals on serial I/O common transmission/reception mode 17 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER The multi-master I2C-BUS interface is a circuit for serial communications conformed with the Philips I2C-BUS data transfer format. This interface, having an arbitration lost detection function and a synchronous function, is useful for serial communications of the multi-master. Figure 12 shows a block diagram of the multi-master I2C-BUS interface and Table 2 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits. MULTI-MASTER I2C-BUS INTERFACE Table 2. Multi-master I2C-BUS interface functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ = 4 MHz) Format Communication mode SCL clock frequency φ : System clock = f(XIN)/2 Note: We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00DA16) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2). b7 I2C address register b0 Interrupt generating circuit Interrupt request signal (IICIRQ) SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW S0D Address comparator Serial data (SDA) Noise elimination circuit Data control circuit b7 I2C data shift register S0 b0 b7 b0 AL AAS AD0 LRB MST TRX BB PIN AL circuit Internal data bus BB circuit S1 I2C status register Serial clock (SCL) Noise elimination circuit Clock control circuit b7 ACK b0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE b7 b0 10BIT ALS ESO BC2 BC1 BC0 BSEL1 BSEL0 SAD S2 I2C clock control register Clock division S1D I2C control register System clock (φ) Bit counter Fig. 12. Block diagram of multimaster I2C-BUS interface 18 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER The I 2C data shift register (S0 : address 00D716 ) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2 C data shift register is in a write enable status only when the ES0 bit of the I 2C control register (address 00DA16 ) is “1.” The bit counter is reset by a write instruction to the I 2C data shift register. When both the ES0 bit and the MST bit of the I2C status register (address 00D916 ) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ES0 bit value. Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. (1) I 2C Data Shift Register 7 0 I2 C address register (S0D: address 00D816) Read/write bit Slave address SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW Fig. 13. Structure of I2C address register (3) I2C Clock Control Register The I2C clock control register (address 00DB 16) is used to set ACK control, SCL mode and SCL frequency. s Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. Refer to Table 3. s Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. s Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clockV is generated. When this bit is set to “0,” the ACK return mode is set and make SDA “L” at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the “H” status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made “L” (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made “H”(ACK is not returned). VACK clock: Clock for acknowledgement s Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA “H”) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I 2C clock control register during transmitting. If data is written during transmitting, the I2C clock generator is reset, so that data cannot be transmitted normally. The I2C address register (address 00D816 ) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected. s Bit 0: Read/write bit (RBW) Not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I 2C address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. s Bits 1 to 7: Slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. (2) I 2C Address Register 19 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 7 ACK 0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE I2C clock control register (S2 : address 00DB16) SCL frequency control bits Refer to Table 3. SCL mode specification bit 0 : Standard clock mode 1 : High-speed clock mode ACK bit 0 : ACK is returned. 1 : ACK is not returned. ACK clock bit 0 : No ACK clock 1 : ACK clock Fig. 14. Structure of I2C clock control register Table 3. Set values of I2C clock control register and SCL frequency Setting value of CCR4–CCR0 CCR4 CCR3 CCR2 CCR1 CCR0 0 0 0 0 0 0 0 … 0 0 0 0 0 0 0 … 0 0 0 0 1 1 1 … 0 0 1 1 0 0 1 … 0 1 0 1 0 1 0 … SCL frequency (at φ = 4MHz, unit : kHz) Standard clock High-speed clock mode mode Setting disabled Setting disabled Setting disabled Setting disabled Setting disabled 100 83.3 500/CCR value 17.2 16.6 16.1 Setting disabled Setting disabled Setting disabled 333 250 400(Note) 166 1000/CCR value 34.5 33.3 32.3 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 The I2C control register (address 00DA16) controls data communication format. s Bits 0 to 2: Bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits. s Bit 3: I2C interface use enable bit (ES0) This bit enables to use the multimaster I2C BUS interface. When this bit is set to “0,” the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ES0 = “0,” the following is performed. PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C status register at address 00D916 ). Writing data to the I2C data shift register (address 00D716) is disabled. s Bit 4: Data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to “(5) I 2C Status Register,” bit 1) is received, transmission processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recognized. s Bit 5: Addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 00D816) are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. s Bits 6 and 7: Connection control bits between I 2C-BUS interface and ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 15). (4) I2C Control Register • • Note: At 400 kHz in the high-speed clock mode, the duty is 40%. In the other cases, the duty is 50%. 20 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER “0” “1” BSEL0 SCL1/P11 SCL Multi-master I2C-BUS interface SDA “0” “1” BSEL1 SCL2/P12 “0” “1” BSEL0 SDA1/P13 “0” “1” BSEL1 SDA2/P14 7 BSEL1 BSEL0 10 BIT ALS SAD 0 ES0 BC2 BC1 BC0 I2C control register (S1D : address 00DA16) Bit counter (Number of transmit/receive bits) b2 b1 b0 0 0 0:8 0 0 1:7 0 1 0:6 0 1 1:5 1 0 0:4 1 0 1:3 1 1 0:2 1 1 1:1 I2C-BUS interface use enable bit 0 : Disabled 1 : Enabled Data format selection bit 0 : Addressing format 1 : Free data format Addressing format selection bit 0 : 7-bit addressing format 1 : 10-bit addressing format Connection control bits between I2C-BUS interface and ports b7 b6 Connection port 0 0 : None 0 1 : SCL1, SDA1 1 0 : SCL2, SDA2 1 1 : SCL1, SDA1, SCL2, SDA2 Fig. 15. Connection port control by BSEL0 and BSEL1 The I2C status register (address 00D916) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to. s Bit 0: Last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register (address 00D716). s Bit 1: General call detecting flag (AD0) This bit is set to “1” when a general call V whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition. VGeneral call: The master transmits the general call address “0016” to all slaves. s Bit 2: Slave address comparison flag (AAS) This flag indicates a comparison result of address data. Œ In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions. The address data immediately after occurrence of a START condition agrees with the slave address stored in the high-order 7 bits of the I2C address register (address 00D816). A general call is received.  In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition. When the address data is compared with the I 2 C address register (8 bits consisted of slave address and RBW), the first bytes agree. Ž The state of this bit is changed from “1” to “0” by executing a write instruction to the I 2C data shift register (address 00D716). (5) I 2C Status Register Fig. 16. Structure of I2 C control register • • • 21 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER s Bit 3: Arbitration lostV detecting flag (AL) In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.” In the case arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. VArbitration lost: The status in which communication as a master is disabled. s Bit 4: I2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal occurs to the CPU. The PIN bit is set to “0” in synchronization with a falling of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 18 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in one of the following conditions. Executing a write instruction to the I2C data shift register (address 00D716). When the ES0 bit is “0” At reset The conditions in which the PIN bit is set to “0” are shown below: Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) Immediately after completion of 1-byte data reception In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception In the slave reception mode, with ALS = “1” and immediately after completion of address data reception s Bit 5: Bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (Note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ES0 bit of the I2 C control register (address 00DA16 ) is “0” and at reset, the BB flag is kept in the “0” state. s Bit 6: Communication mode specification bit (transfer direction specification bit: TRX) This bit decides a direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output onto the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I 2C control register (address 00DA16) is “0” in the slave reception mode is selected, the TRX bit is set to “1” (transmit) if the least significant bit (R/W bit) of the address data trans- • • • • • • • • • • • • • • • • • mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions. When arbitration lost is detected. When a STOP condition is detected. When occurence of a START condition is disabled by the START condition duplication preventing function (Note). With MST = “0” and when a START condition is detected. With MST = “0” and when ACK non-return is detected. At reset s Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to “0” in one of the following conditions. Immediately after completion of 1-byte data transmission when arbitration lost is detected When a STOP condition is detected. When occurence of a START condition is disabled by the START condition duplication preventing function (Note). At reset Note: The START condition duplication prevention function disables the occurence of a START condition, reset of bit counter and SCL output when the following condition is satisfied: • a START condition is set by another master device. 22 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (6) START Condition Generating Method 7 0 I2C status register (S1 : address 00D916) Last receive bit (Note) 0 : Last bit = “0” 1 : Last bit = “1” General call detecting flag (Note) 0 : No general call detected 1 : General call detected Slave address comparison flag (Note) 0 : Address disagreement 1 : Address agreement Arbitration lost detecting flag (Note) 0 : Not detected 1 : Detected I2C-BUS interface interrupt request bit 0 : Interrupt request issued 1 : No interrupt request issued Bus busy flag 0 : Bus free 1 : Bus busy Communication mode specification bits 00 : Slave receive mode 01 : Slave transmit mode 10 : Master receive mode 11 : Master transmit mode Note: These bit and flags can be read out but cannot be written. Fig. 17. Structure of I2 C status register I2C status register write signal SCL SDA SCL PIN BB flag Setup time Hold time Reset time for BB flag MST TRX BB PIN AL AAS AD0 LRB When the ES0 bit of the I2 C control register (address 00DA16) is “1,” execute a write instruction to the I2C status register (address 00D916) for setting the MST, TRX and BB bits to “1.” Then a START condition occurs. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generating timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 19, the START condition generating timing diagram, and Table 4, the START condition/STOP condition generating timing table. I2C status register write signal SCL SDA BB flag Setup time Fig. 19. START condition generating timing diagram Setup time Hold time Set time for BB flag (7) STOP Condition Generating Method When the ES0 bit of the I2 C control register (address 00DA16) is “1,” execute a write instruction to the I2C status register (address 00D916) for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. Then a STOP condition occurs. The STOP condition generating timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 20, the STOP condition generating timing diagram, and Table 4, the START condition/STOP condition generating timing table. Fig. 20. STOP condition generating timing diagram Table 4. START condition/STOP condition generating timing table IICIRQ Item Standard clock mode Setup time 5.0 µs (20 cycles) Hold time 5.0 µs (20 cycles) Set/reset time 3.0 µs (12 cycles) for BB flag High-speed clock mode 2.5 µs (10 cycles) 2.5 µs (10 cycles) 1.5 µs (6 cycles) Fig. 18. Interrupt request signal generating timing Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. 23 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (8) START/STOP Condition Detecting Conditions The START/STOP condition detecting conditions are shown in Figure 21 and Table 5. Only when the 3 conditions of Table 5 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” occurs to the CPU. (9) Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below. Œ 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I 2C control register (address 00DA16) to “0.” The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I 2C address register (address 00D816 ). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00D8 16) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 22, (1) and (2).  10-bit addressing format To meet the 10-bit addressing format, set the 10BIT SAD bit of the I 2C control register (address 00DA16) to “1.” An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I 2C address register (address 00D816). At the time of this comparison, an address comparison between the RBW bit of the I 2C address register (address 00D8 16) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. SCL release time SCL SDA (START condition) SDA (STOP condition) Fig. 21. START condition/STOP condition detecting timing diagram Setup time Setup time Hold time Hold time Table 5. START condition/STOP condition detecting conditions Standard clock mode High-speed clock mode 6.5 µs (26 cycles) < SCL release 1.0 µ s (4 cycles) < SCL release time time 3.25 µs (13 cycles) < Setup time 0.5 µ s (2 cycles) < Setup time 3.25 µs (13 cycles) < Hold time 0.5 µ s (2 cycles) < Hold time Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. S Slave address R/W A Data A Data A/A P 7 bits “0” 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver S Slave address R/W A Data A Data A P 7 bits “1” 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address R/W 1st 7 bits Slave address 2nd byte S A A Data A Data A/A P 7 bits “0” 8 bits 1 to 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address R/W 1st 7 bits Slave address 2nd byte Slave address R/W 1st 7 bits S A A Sr Data A Data 1 to 8 bits A P 7 bits “0” 8 bits 7 bits “1” 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit From master to slave From slave to master Fig. 22. Address data communication format 24 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER When the first-byte address data matches the slave address, the AAS bit of the I 2C status register (address 00D916) is set to “1.” After the second-byte address data is stored into the I 2C data shift register (address 00D7 16), make an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd byte matches the slave address, set the RBW bit of the I2 C address register (address 00D816) to “1” by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I 2C address register (address 00D816 ). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 22, (3) and (4). ‘ ’ “ ” •When all transmitted addresses are “0” (general call) AD0 of the I2C status register (address 00D916) is set to “1” and an interrupt request signal occurs. •When the transmitted addresses match the address set in Œ AAS of the I2C status register (address 00D916 ) is set to “1” and an interrupt request signal occurs. •In the cases other than the above AD0 and AAS of the I2C status register (address 00D9 16) are set to “0” and no interrupt request signal occurs. Set dummy data in the I2C data shift register (address 00D716). When receiving control data of more than 1 byte, repeat step ’. When a STOP condition is detected, the communication ends. (10) Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Œ Set a slave address in the high-order 7 bits of the I2 C address register (address 00D816) and “0” in the RBW bit.  Set the ACK return mode and SCL = 100 kHz by setting “8516 ” in the I2C clock control register (address 00DB16). Ž Set “1016” in the I2 C status register (address 00D916) and hold the SCL at the “H” level.  Set a communication enable status by setting “4816” in the I 2C control register (address 00DA16).  Set the address data of the destination of transmission in the highorder 7 bits of the I2C data shift register (address 00D716) and set “0” in the least significant bit. ‘ Set “F016” in the I2C status register (address 00D916) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. ’ Set transmit data in the I2C data shift register (address 00D716 ). At this time, an SCL and an ACK clock automatically occurs. “ When transmitting control data of more than 1 byte, repeat step ’. ” Set “D016” in the I2C status register (address 00D916). After this, if ACK is not returned or transmission ends, a STOP condition occurs. (11) Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode and using the addressing format is shown below. Œ Set a slave address in the high-order 7 bits of the I2 C address register (address 00D816) and “0” in the RBW bit.  Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 00DB16). Ž Set “1016” in the I2 C status register (address 00D916) and hold the SCL at the “H” level.  Set a communication enable status by setting “4816” in the I 2C control register (address 00DA16).  When a START condition is received, an address comparison is made. 25 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PWM OUTPUT FUNCTION The M37221M6-XXXSP is equipped with a 14-bit PWM (DA) and six 8-bit PWMs (PWM0–PWM5). DA has a 14-bit resolution with the minimum resolution bit width of 0.25 µ s (for f(XIN) = 8 MHz) and a repeat period of 4096 µs. PWM0–PWM5 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 µs (for f(XIN) = 8 MHz) and repeat period of 1024 µs. Figure 23 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to PWM0–PWM5 using f(XIN) divided by 2 as a reference signal. (4) Operating of 14-bit PWM As with 8-bit PWM, set the bit 0 of the PWM output control register 1 (address 00D516) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. Next, select the output polarity by bit 2 of the PWM output control register 2 (address 00D616). Then, the 14-bit PWM outputs from the D-A output pin by setting bit 1 of the PWM output control register 1 to “0” (at reset, this bit already set to “0” automatically) to select the DA output. The output example of the 14-bit PWM is shown in Figure 25. The 14-bit PWM divides the data of the DA latch into the low-order 6 bits and the high-order 8 bits. The fundamental waveform is determined with the high-order 8-bit data “DH .” A “H” level area with a length τ ! DH(“H” level area of fundamental waveform) is output every short area of “t” = 256τ = 64 µs ( τ is the minimum resolution bit width of 0.25 µs). The “H” level area increase interval (tm) is determined with the low-order 6-bit data “DL.” The “H” level are of smaller intervals “tm” shown in Table 6 is longer by τ than that of other smaller intervals in PWM repeat period “T” = 64t. Thus, a rectangular waveform with the different “H” width is output from the D-A pin. Accordingly, the PWM output changes by τ unit pulse width by changing the contents of the DA-H and DA-L registers. A length of entirely “H” output cannot be output, i. e. 256/ 256. (1) Data Setting When outputting DA, first set the high-order 8 bits to the DA-H register (address 00CE16), then the low-order 6 bits to the DA-L register (address 00CF16 ). When outputting PWM0–PWM5, set 8-bit output data in the PWMi register (i means 0 to 5; addresses 00D016 to 00D416, 00F6 16). (2) Transmitting Data from Register to PWM circuit Data transfer from the 8-bit PWM register to 8-bit PWM circuit is executed at writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register. Also, data transfer from the DA register (addresses 00CE16 and 00CF16) to the 14-bit PWM circuit is executed at writing data to the DA-L register (address 00CF16 ). Reading from the DA-H register (address 00CE16 ) means reading this transferred data. Accordingly, it is possible to confirm the data being output from the D-A output pin by reading the DA register. (5) Output after Reset At reset, the output of port P00–P05 is in the high-impedance state, and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register. (3) Operating of 8-bit PWM The following is the explanation about PWM operation. At first, set the bit 0 of PWM output control register 1 (address 00D516) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. PWM0–PWM5 are also used as pins P00–P0 5 respectively. For PWM0–PWM5, set the corresponding bits of the port P0 direction register to “1” (output mode). And select each output polarity by bit 3 of the PWM output control register 2(address 00D616 ). Then, set bits 2 to 7 of the PWM output control register 1 to “1” (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 24 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (28) segments. The 8 kinds of pulses relative to the weight of each bit (bits 0 to 7) are output inside the circuit during 1 cycle. Refer to Figure 24 (a). The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 24 (b). 256 kinds of output (“H” level area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of entirely “H” output cannot be output, i.e. 256/256. 26 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Table 6. Relation between the low-order 6-bit data and high-level area increase interval Low-order 6 bits of data Area longer by τ than that of other tm (m = 0 to 63) 000000 000001 000010 000100 001000 010000 100000 LSB Nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7, ................................ 57, 59, 61, 63 Data bus DA-H register (Address : 00CE16) b7 DA latch (14 bits) MSB 8 6 6 14 LSB b0 DA-L register (Note) (Address : 00CF16) PN2 14-bit PWM circuit PN4 PW1 DA D-A XIN 1/2 PW0 PWM timing generating circuit PWM register (Address : 00D016) b7 8 b0 PN3 8-bit PWM circuit P00 PW2 P01 D00 PWM0 D01 PWM1 PWM1 register (Address : 00D116) PW3 P02 D02 PWM2 Selection gate : Connected to black colored side when reset. Pass gate Inside of with the others. is as same contents PWM2 register (Address : 00D216) PW4 P03 PW5 P04 PW6 P05 PW7 D05 PWM5 D04 PWM4 D03 PWM3 PWM3 register (Address : 00D316) PWM4 register (Address : 00D416) PW : PWM output control register 1 PN : PWM output control register 2 D0 : Port P0 direction register PWM5 register (Address : 00F616) Note: The DA-L register also functions as the low-order 6 bits of the DA latch. Fig. 23. PWM block diagram 27 28 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 13579 20 30 40 50 Fig. 24. 8-bit PWM timing 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 56 72 104 136 168 200 232 216 184 152 120 88 248 80 112 144 176 208 240 96 160 224 64 192 128 Bit 7 2 6 10 14 18 22 26 30 34 38 42 46 50 Bit 6 4 12 20 28 36 44 Bit 5 8 24 40 Bit 4 16 48 Bit 3 32 Bit 2 Bit 1 Bit 0 (a) Pulses showing the weight of each bit 0016 (0) 0116 (1) 1816 (24) FF16 (255) t T = 256 t PWM output t = 4 s T = 1024 s f(XIN) = 8 MHz (b) Example of 8-bit PWM MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Set “2C16” to DA-H register. Set “2816” to DA-L register. b7 b6 b5 b4 b3 b2 b1 b0 [DA-H 0 0 1 0 1 1 0 0 DH register] At writing of DA-L b13 [DA latch] 0 0 1 0 1 1 0 b6 b5 0 1 0 1 b7 b6 b5 b4 b3 b2 b1 b0 [DA-L register] Undefined 1 0 1 0 0 0 DL At writing of DA-L b0 0 0 0 These bits decide “H” level area of fundamental waveform. “H” level area of fundamental waveform These bits decide smaller interval “tm” in which “H” leval area is [“H” level area of fundamental waveform + τ ]. = Minimum resolution bit width 0.25µs ! High-order 8-bit value of DA latch Fundamental waveform Waveform of smaller interval “tm” specified by low-order 6 bits 0.25 µs !44 0.25 µs !45 0.25 µs 14-bit PWM output 2C 2B 2A … 03 02 01 00 8-bit counter FF FE FD … D6 D5 D4 D3 … 02 01 00 14-bit PWM output 2C 2B 2A … 03 02 01 00 8-bit counter FF FE FD … D6 D5 D4 D3 … 02 01 00 Fundamental waveform of smaller interval “tm” which is not specified by low-order 6 bits is not changed. 0.25µs!44 τ = 0.25µs 14-bit PWM output t0 Low-order 6-bit output of DA latch Repeat period T = 4096µs t1 t2 t3 t4 t5 t59 t60 t61 t62 t63 Fig. 25. 14-bit PWM output example (f(XIN) = 8 MHz) 29 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 7 0 PWM output control register 1 (PW: address 00D516) DA, PWM count source selection bit 0 : Count source supply 1 : Count source stop DA/PN4 output selection bit 0 : DA output 1 : PN4 output P00/PWM0 output selection bit 0 : P00 output 1 : PWM0 output P01/PWM1 output selection bit 0 : P01 output 1 : PWM1 output P02/PWM2 output selection bit 0 : P02 output 1 : PWM2 output P03/PWM3 output selection bit 0 : P03 output 1 : PWM3 output P04/PWM4 output selection bit 0 : P04 output 1 : PWM4 output P05/PWM5 output selection bit 0 : P05 output 1 : PWM5 output 7 0 PWM output control register 2 (PN: address 00D616) DA output polarity selection bit 0 : Positive polarity 1 : Negative polarity PWM output polarity selection bit 0 : Positive polarity 1 : Negative polarity DA general-purpose output bit 0 : Output “L” 1 : Output “H” Fig. 27. Structure of PWM output control register 2 Fig. 26. Structure of PWM output control register 1 30 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER A-D COMPARATOR A-D comparator consists of 6-bit D-A converter and comparator. A-D comparator block diagram is shown in Figure 30. The reference voltage “Vref” for D-A conversion is set by bits 0 to 5 of the A-D control register 2 (address 00EF16). The comparison result of the analog input voltage and the reference voltage “Vref” is stored in bit 4 of the A-D control register (address 00EE16). For A-D comparison, set “0” to corresponding bits of the direction register to use ports as analog input pins. Write the data for select of analog input pins to bits 0 to 2 of the A-D control register 1 and write the digital value corresponding to Vref to be compared to the bits 0 to 5 A-D control register 2. The voltage comparison starts by writing to the A-D control register 2, and it is completed after 16 machine cycles (NOP instruction ! 8). 7 0 A-D control register 2 (AD2: address 00EF16) D-A converter set bits Refer to Table 7. Fig. 29. Structure of A-D control register 2 7 0 A-D control register 1 (AD1: address 00EE16) Table 7. Relation between contents of A-D control register 2 and reference voltage “Vref” Bit 5 0 0 0 … A-D control register 2 Bit 4 Bit 3 Bit 2 Bit 1 0 0 0 0 0 0 0 0 0 0 0 1 … … … … Bit 0 0 1 0 … Reference voltage “Vref” 1/128 VCC 3/128 VCC 5/128 VCC … 123/128 VCC 125/128 VCC 127/128 VCC Bit 1 Bit 0 Analog input pin selection bits b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0 : A-D1 1 : A-D2 0 : A-D3 1 : A-D4 0 : A-D5 1 : A-D6 0: Do not set. 1: Storage bit of comparison result 0 : Input voltage < reference voltage 1 : Input voltage > reference voltage 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 Fig. 28. Structure of A-D control register 1 Data bus A-D control register 1 Bits 0 to 2 Comparator control P15/A-D1/INT3 P16/A-D2 P17/A-D3 P06/INT2/A-D4 P30/A-D5 P31/A-D6 A-D control register 1 Analog signal switch Comparator Bit 4 Bit 5 Bit 4 A-D control register 2 Bit 3 Bit 2 Switch tree Resistor ladder Fig. 30. A-D comparator block diagram 31 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER CRT DISPLAY FUNCTIONS (1) Outline of CRT Display Functions Table 8 outlines the CRT display functions of the M37221M6-XXXSP. The M37221M6-XXXSP incorporates a CRT display control circuit of 24 characters ! 2 lines. CRT display is controlled by the CRT control register. Up to 256 kinds of characters can be displayed. The colors can be specified for each character and up to 4 kinds of colors can be displayed on one screen. A combination of up to 7 colors can be obtained by using each output signal (R, G, and B). Characters are displayed in a 12 ! 16 dots configuration to obtain smooth character patterns (refer to Figure 31). The following shows the procedure how to display characters on the CRT screen. Œ Write the display character code in the display RAM.  Specify the display color by using the color register. Ž Write the color register in which the display color is set in the display RAM.  Specify the vertical position by using the vertical position register.  Specify the character size by using the character size register. ‘ Specify the horizontal position by using the horizontal position register. ’ Write the display enable bit to the designated block display flag of the CRT control register. When this is done, the CRT display starts according to the input of the VSYNC signal. The CRT display circuit has an extended display mode. This mode allows multiple lines (3 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Figure 32 shows the structure of the CRT display control register. Figure 33 shows the block diagram of the CRT display control circuit. 12 dots 16 dots Fig. 31. CRT display character configuration 7 0 CRT control register (CC: address 00EA16) Table 8. Outline of CRT display functions Parameter Number of display characters Dot structure Kinds of characters Kinds of character sizes Kinds of colors Color Coloring unit Display expansion Raster coloring Character background coloring Functions 24 characters ! 2 lines 12 ! 16 dots (refer to Figure 31) 256 kinds 3 kinds 1 screen : 4 kinds, maximum 7 kinds A character Possible (multiline display) Possible (maximum 7 kinds) Possible (a character unit, 1 screen : 4 kinds, maximum 7 kinds) All-blocks display control bit (Note) 0 : All-blocks display off 1 : All-blocks display on Block 1 display control bit 0 : Block 1 display off 1 : Block 1 display on Block 2 display control bit 0 : Block 2 display off 1 : Block 2 display on P10/OUT2 pin switch bit 0 : P10 1 : OUT2 Note: Display is controlled by logical product (AND) between the all-blocks display control bit and each block control bit. Fig. 32. Structure of CRT control register 32 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER OSC1 OSC2 HSYNC VSYNC (Address 00EA16) CRT control register (Addresses 00E116, 00E216) Display oscillation circuit Vertical position registers (Address 00E416) Character size register Display position control circuit (Address 00E016) Horizontal position register (Address 00E516) Border selection register Display control circuit RAM for display 10 bits ! 24 ! 2 (Addresses 00E616 to 00E916) ROM for display 12 bits ! 16 ! 256 Color registers Shift register 12 bits Shift register 12 bits (Address 00EC16) Output circuit CRT port control register Data bus R Fig. 33. Block diagram of CRT display control circuit G B OUT1 OUT2 33 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (2) Display Position The display positions of characters are specified in units called a “block.” There are 2 blocks, block 1 and block 2. Up to 24 characters can be displayed in each block (refer to (4) Memory for Display). The display position of each block can be set in both horizontal and vertical directions by software. The display position in the horizontal direction can be selected for all blocks in common from 64-step display positions in units of 4TC (TC = oscillating cycle for display). The display position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines. Block 2 is displayed after the display of block 1 is completed (refer to Figure 34 (a)). Accordingly, if the display of block 2 starts during the display of block 1, only block 1 is displayed. Similarly, when multiline display, block 1 is displayed after the display of block 2 is completed (refer to Figure 34 (b)). The vertical position can be specified from 128-step positions (4 scanning lines per a step) for each block by setting values “0016” to “7F16” to bits 0 to 6 in the vertical position register (addresses 00E116 and 00E216). Figure 36 shows the structure of the vertical position register. (HR) CV1 Block 1 CV2 Block 2 (a) Example when each block is separated CV1 Block 1 CV2 Block 2 No display CV1 Block 1 (second) No display (b) Example when block 2 overlaps with block 1 Fig. 34. Display position 34 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER The display position in the vertical direction is determined by counting the horizontal sync signal (HSYNC). At this time, it starts to count the rising edge (falling edge) of HSYNC signal from after about 1 machine cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can select with the CRT port control register (address 00EC16). For details. refer to (8) CRT Output Pin Control. Note: When bits 0 and 1 of the CRT port control register (address 00EC16) are set to “1” (negative polarity), the vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer (refer to Figure 35). 7 0 Vertical position registers 1, 2 (CV1 : address 00E116) (CV2 : address 00E216) Vertical display start positions 128 steps from “0016” to “7F16” Fig. 36. Structure of vertical position register VSYNC signal input 0.125 to 0.25 [µs] ( at f(XIN) = 8MHz) VSYNC control signal in microcomputer Period of counting HSYNC signal (Note) HSYNC signal input 1 2 3 4 5 The horizontal position is common to all blocks, and can be set in 64 steps (where 1 step is 4TC, TC being the display oscillation period) as values “0016” to “3F16” in bits 0 to 5 of the horizontal position register (address 00E016). The structure of the horizontal position register is shown in Figure 37. 7 0 Horizontal position register (HR : address 00E016) Horizontal display start positions 64 steps from “0016” to “3F16” (1 step is 4TC) Not count When bits 0 and 1 of the CRT port control register (address 00EC16) are set to “1” (negative polarity) Note: Do not generate falling edge of H SYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. Fig. 37. Structure of horizontal position register Fig. 35. Supplement explanation for display position 35 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (3) Character Size The size of characters to be displayed can be from 3 sizes for each block. Use the character size register (address 00E416) to set a character size. The character size of block 1 can be specified by using bits 0 and 1 of the character size register; the character size of block 2 can be specified by using bits 2 and 3. Figure 38 shows the structure of the character size register. The character size can be selected from 3 sizes: minimum size, medium size and large size. Each character size is determined by the number of scanning lines in the height (vertical) direction and the oscillating cycle for display (TC) in the width (horizontal) direction. The minimum size consists of [1 scanning line] ! [1TC]; the medium size consists of [2 scanning lines] ! [2TC]; and the large size consists of [3 scanning lines] ! [3TC]. Table 9 shows the relation between the set values in the character size register and the character sizes. 7 0 Character size register (CS : address 00E416) Character size of block 1 selection bits 0 0 : Minimum size 0 1 : Medium size 1 0 : Large size 1 1 : Do not set. Character size of block 2 selection bits 0 0 : Minimum size 0 1 : Medium size 1 0 : Large size 1 1 : Do not set. Fig. 38. Structure of character size register Minimum Medium Large Horizontal display start position Fig. 39. Display start position of each character size (horizontal direction) Table 9. Relation between set values in character size register and character sizes Set values of character size register CSn1 0 0 1 1 CSn0 0 1 0 1 Character size Minimum Medium Large Width (horizontal) direction TC: oscillating cycle for display 1TC 2TC 3TC This is not available Height (vertical) direction scanning lines 1 2 3 Note: The display start position in the horizontal direction is not affected by the character size. In other words, the horizontal display start position is common to all blocks even when the character size varies with each block (refer to Figure 39). 36 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (4) Memory for Display There are 2 types of memory for display : CRT display ROM (addresses 1000016 t o 11FFF 16) used to store character dot data (masked) and CRT display RAM (addresses 060016 to 06B716) used to specify the colors of characters to be displayed. The following describes each type of display memory. Œ ROM for display (addresses 1000016 to 11FFF16) The CRT display ROM contains dot pattern data for characters to be displayed. For characters stored in this ROM to be actually displayed, it is necessary to specify them by writing the character code inherent to each character (code determined based on the addresses in the CRT display ROM) into the CRT display RAM. The character code list is shown in Table 10. The CRT display ROM has a capacity of 8K bytes. Since 32 bytes are required for 1 character data, the ROM can stores up to 256 kinds of characters. The CRT display ROM space is broadly divided into 2 areas. The [vertical 16 dots] ! [horizontal (left side) 8 dots] data of display characters are stored in addresses 1000016 to 107FF16 and 1100016 to 117FF16 ; the [vertical 16 dots] ! [horizontal (right side) 4 dots] data of display characters are stored in addresses 1080016 to 10FFF16 and 1180016 to 11FFF16 (refer to Figure 40). Note however that the high-order 4 bits in the data to be written to addresses 1080016 to 10FFF16 and 1180016 to 11FFF16 must be set to “1” (by writing data “FX16”). b7 10XX016 or 11XX016 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 b0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 b7 10XX016 + 80016 or 11XX016 + 80016 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b3 000 000 000 000 000 000 000 000 100 100 100 010 010 010 000 000 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10XXF16 or 11XXF16 10XXF16 + 80016 or 11XXF16 + 80016 Fig. 40. Display character stored data 37 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Table 10. Character code list (partially abbreviated) Character code 0016 Character data storage address Left 8 dots lines Right 4 dots lines 1000016 1080016 to to 1000F16 1080F16 1001016 1081016 to to 1001F16 1081F16 1002016 1082016 to to 1002F16 1082F16 1003016 1083016 to to 1003F16 1083F16 : : 107E016 to 107EF16 107F016 to 107FF16 1100016 to 1100F16 1101016 to 1101F16 : 117D016 to 117DF16 117E016 to 117EF16 117F016 to 117FF16 10FE016 to 10FEF16 10FF016 to 10FFF16 1180016 to 1180F16 1181016 to 1181F16 : 11FD016 to 11FDF16 11FE016 to 11FEF16 11FF016 to 11FFF16  RAM for display (addresses 060016 to 06B716) The CRT display RAM is allocated at addresses 060016 to 06B716, and is divided into a display character code specification part and display color specification part for each block. Table 11 shows the contents of the CRT display RAM. For example, to display 1 character position (the left edge) in block 1, write the character code in address 060016 and write the color register No. to the low-order 2 bits (bits 0 and 1) in address 068016. The color register No. to be written here is one of the 4 color registers in which the color to be displayed is set in advance. For details on color registers, refer to (5) Color Registers. The structure of the CRT display RAM is shown in Figure 41. 0116 0216 0316 : 7E16 7F16 8016 8116 : FD16 FE16 FF16 Table 11. Contents of CRT display RAM Block Display position (from left) 1st character 2nd character 3rd character : 22nd character 23rd character 24th character Not used 1st character 2nd character 3rd character : 22nd character 23rd character 24th character Character code specification 060016 060116 060216 : 061516 061616 061716 061816 to 061F16 062016 062116 062216 : 063516 063616 063716 Color specification 068016 068116 068216 : 069516 069616 069716 069816 to 069F16 06A016 06A116 06A216 : 06B516 06B616 06B716 Block 1 Block 2 38 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Block 1 [Character specification] 1st character : 060016 to 24th character : 061716 Character code Specify 256 characters (“0016” to “FF16”) [Color specification] 1st character : 068016 to 24th character : 069716 Color register specification 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 Block 2 [Character specification] 1st character : 062016 to 24th character : 063716 Character code Specify 256 characters (“0016” to “FF16”) [Color specification] 1st character : 06A016 to 24th character : 06B716 Color register specification 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 1 0 7 0 1 0 7 0 Fig. 41. Structure of CRT display RAM 39 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (5) Color Registers The color of a displayed character can be specified by setting the color to one of the 4 registers (CO0 to CO3: addresses 00E616 to 00E916) and then specifying that color register with the CRT display RAM. There are 3 color outputs; R, G and B. By using a combination of these outputs, it is possible to set 23–1 (when no output) = 7 colors. However, since only 4 color registers are available, up to 4 colors can be disabled at one time. R, G and B outputs are set by using bits 1 to 3 in the color register. Bit 5 is used to specify whether a character output or blank output. Bits 4, 6 and 7 are used to specify character background color. Figure 42 shows the structure of the color register. 7 0 Color register 0, 1, 2, 3 (CO0 : address 00E616) (CO1 : address 00E716) (CO2 : address 00E816) (CO3 : address 00E916) B signal output selection bit 0 : No character is output 1 : Character is output G signal output selection bit 0 : No character is output 1 : Character is output R signal output selection bit 0 : No character is output 1 : Character is output B signal output (background) selection bit (Note 1) 0 : No background color is output 1 : Background color is output OUT1 signal output control bit (Notes 1,2) 0 : Character is output 1 : Blank is output G signal output (background) selection bit 0 : No background color is output 1 : Background color is output R signal output (background) selection bit (Note 2) 0 : No background color is output 1 : Background color is output Notes 1 : When bit 5 = “0” and bit 4 = “1,” there is output same as a character or border output from the OUT1 pin. Do not set bit 5 = “0” and bit 4 = “0.” 2 : When only bit 7 = “1” and bit 5 = “0,” there is output from the OUT2 pin. Fig. 42. Structure of color registers 40 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Table 12. Display example of character background coloring (when green is set for a character and blue is set for background color) Border selection register Color register G output B output OUT1 output Character output Green No output (Note 2) Same output as character A Video signal and character color (green) are not mixed. OUT2 output MD0 COn7 COn6 COn5 COn4 COn3 COn2 COn1 0 0 ! 0 1 0 (Note 1) 1 0 No output Green 0 1 ! 0 1 0 1 0 No output Same output as Video signal and character color (green) are not mixed. character A Green 0 0 0 1 0 0 1 0 No output Blank output TV image of character background is not displayed. Blank output No output (Note 2) Green 0 0 0 1 1 0 1 0 Background color Blank output Blue TV image of character background is not displayed. No output (Note 2) 1 ! ! 0 1 0 1 0 No output Border output (Black) Border output (Black) Green No output (Note 2) Video signal and character color (green) are not mixed. Green 1 0 0 1 0 0 1 0 No output Blank output Black TV image of character background is not displayed. No output (Note 2) 1 0 0 1 1 0 1 0 Background color – border Border output (Black) Blank output Green No output (Note 2) Blue TV image of character background is not displayed. Notes1 : When COn 5 = “0” and COn 4 = “1,” there is output same as a character or border output from the OUT1 pin. Do not set COn5 = “0” and COn 4 = “0.” 2 :When only COn7 = “1” and COn 5 = “0,” there is output from the OUT2 pin. 3 :The portion “A” in which character dots are displayed is not mixed with any TV video signal. 4 :The wavy-lined arrows in the Table denote video signals. 5 :n : 0 to 3, ! : 0 or 1 41 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (6) Character Border Function An border of 1 clock (1 dot) equivalent size can be added to a character to be displayed in both horizontal and vertical directions. The border is output from the OUT pin. In this case, set bit 5 of a color register to “0” (character is output). Border can be specified in units of block by using the border selection register (address 00E516). Figure 43 shows the structure of the border selection register. Table 13 shows the relationship between the values set in the border selection register and the character border function. 7 0 Border selection register (MD : address 00E516) Block 1 OUT1 output border selection bit 0 : Same output as R, G, B is output 1 : Border output Block 2 OUT1 output border selection bit 0 : Same output as R, G, B is output 1 : Border output Fig. 43. Structure of border selection register Fig. 44. Example of border Table 13. Relationship between set value in border selection register and character border function Border selection register MDn0 0 Functions Ordinary Example of output R, G, B output OUT1 output R, G, B output OUT1 output 1 Border including character 42 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (7) Multiline Display The M37221M6-XXXSP can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addition, it can display up to 16 lines by using CRT interrupts. A CRT interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block. Note: A CRT interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display with the display control bit of the CRT control register (address 00EA16 ), a CRT interrupt request does not occur (refer to Figure 45). Block 1 (on display) Block 2 (on display) Block 1' (on display) Block 2' (on display) “CRT interrupt request” “CRT interrupt request” “CRT interrupt request” “CRT interrupt request” On display (CRT interrupt request occurs at the end of block display) Block 1 (on display) Block 2 (on display) Block 1' (off display) Block 2' (off display) “CRT interrupt request” “CRT interrupt request” No “CRT interrupt request” No “CRT interrupt request” Off display (CRT interrupt request does not occur at the end of block display) Fig. 45. Timing of CRT interrupt request 43 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (8) CRT Output Pin Control The CRT output pins R, G, B, and OUT1 can also function as ports P52 , P53, P54 and P55. Set the corresponding bit of the port P5 direction register (address 00CB16) to “0” to specify these pins as CRT output pins, or set it to “1” to specify it as a general-purpose port P5 pins. The OUT2 can also function as port P10. Set bit 7 of the CRT control register (address 00EA16) to “0” to specify it as port P10, set it to “1” to specify it as OUT2 pin. The input polarity of signals HSYNC and VSYNC and output polarity of signals R, G, B, OUT1 and OUT2 can be specified with the bits of the CRT port control register (address 00EC16) . Set a bit to “0” to specify positive polarity; set it to “1” to specify negative polarity. The structure of the CRT port control register is shown in Figure 46. 7 0 CRT port control register (CRTP : address 00EC16) HSYNC input polarity switch bit 0 : Positive polarity 1 : Negative polarity VSYNC input polarity switch bit 0 : Positive polarity 1 : Negative polarity R, G, B output polarity switch bit 0 : Positive polarity 1 : Negative polarity OUT2 output polarity switch bit 0 : Positive polarity 1 : Negative polarity OUT1 output polarity switch bit 0 : Positive polarity 1 : Negative polarity R signal output switch bit 0 : R signal output 1 : MUTE signal output G signal output switch bit 0 : G signal output 1 : MUTE signal output (9) Raster Coloring Function An entire screen (raster) can be colored by setting the bits 5 to 7 of the CRT port control register. Since each of the R, G, and B pins can be switched to raster coloring output, 7 raster colors can be obtained. If the R, G, and B pins have been set to MUTE signal output, a raster coloring signal is output in the part except a no-raster colored character (in Figure 47, a character “O”) during 1 horizontal scanning period. This ensures that character colors do not mix with the raster color. In this case, MUTE signal is output from the OUT1 pin. An example in which a magenta character “I” and a red character “O” are displayed with blue raster coloring is shown in Figure 47. “RED” “BLUE” A A' B signal output switch bit 0 : B signal output 1 : MUTE signal output Fig. 46. Structure of CRT port control register HSYNC R B OUT1 Signals across A – A' Fig. 47. Example of raster coloring 44 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER (10) Clock for Display As a clock for display to be used for CRT display, it is possible to select one of the following 4 types. Main clock supplied from the XIN pin Main clock supplied from the XIN pin divided by 1.5 Clock from the LC or RC supplied from the pins OSC1 and OSC2. Clock from the ceramic resonator or quartz-crystal oscillator supplied from the pins OSC1 and OSC2. This clock for display can be selected for each block by the CRT clock selection register (address 00ED16 ). When selecting the main clock, set the oscillation frequency to 8 MHz. • • • • 7 000000 0 CRT clock selection register (CK : address 00ED16) Display clock selection bits Refer to Table 14. Fix these bits to “0.” Fig. 48. Structure of CRT clock selection register Table 14. Set value of CRT clock selection register and clock for display b1 0 0 1 1 b0 0 1 0 1 Functions The clock for display is supplied by connecting RC or LC across the pins OSC1 and OSC2. CRT oscillation frequency = Since the main clock is used as the clock for display, the oscillation frequency is limited. Because f(X IN) of this, the character size in width (horizontal) direction is also limited. In this case, pins OSC1 CRT oscillation frequency = and OSC2 are also used as input ports P33 and P34 respectively. f(X IN)/1.5 The clock for display is supplied by connecting the following across the pins OSC1 and OSC2. • a ceramic resonator only for CRT display and a feedback resistor • a quartz-crystal oscillator only for CRT display and a feedback resistor (Note) Note: It is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins XIN and XOUT. 45 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER RESET CIRCUIT The M37221M6-XXXSP is reset according to the sequence shown in Figure 49. It starts the program from the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address, when the RESET pin is held at “L” level for 2 ms or more while the power source voltage is 5 V ± 10 % and the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and then returned to “H” level. The internal state of microcomputer at reset are shown in Figure 51. An example of the reset circuit is shown in Figure 50. The reset input voltage must be kept 0.6 V or less until the power source voltage surpasses 4.5 V. X IN φ RESET Internal RESET SYNC Address Data ? ? ? ? 01, S 01, S-1 01, S-2 FFFE FFFF ADH, ADL Reset address from the vector table ? ? ? AD L ADH 32768 count of X IN clock cycle (Note 3) Notes 1 : f(XIN) and f( φ) are in the relation : f(X IN) = 2·f ( φ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected in hardware. At this time, “FF 16” is set in timer 3 and “0716” is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal. Fig. 49. Reset sequence Poweron 4.5 V Power source voltage 0 V Reset input voltage 0 V 0.6 V 22 1 5 M51953AL Vcc 25 RESET 4 3 0.1 µF 21 Vss M37221M6-XXXSP Fig. 50. Example of reset circuit 46 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Address Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P5 Port P5 direction register Contents of register 0016 0016 0016 000 VVVV Color register 0 Color register 1 Color register 2 Color register 3 CRT control register CRT port control register CRT clock selection register A-D control register 1 A-D control register 2 Timer 1 Timer 2 Timer 3 Timer 4 Timer 12 mode register Timer 34 mode register Interrupt input polarity register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register Program counter Address Contents of register (00E616) (00E716) (00E816) (00E916) (00EA16) (00EC16) (00ED16) (00EE16) (00EF 16) (00F016) (00F116) (00F216) (00F316) (00F416) (00F516) (00F916) (00FB 16) (00FC16) (00FD16) (00FE 16) (00FF16) (PS) (PCH) (PC L) 0 V (00C1 16) (00C3 16) (00C5 16) (00C7 16) (00CA16) (00CB16) 000000 0 000000 0 000000 0 000000 0 0 000 00 000 0 0 000 00 0 00 0 0 0 00 0 VVVVVV Port P3 output mode control register (00CD16) DA-L register PWM output control register 1 PWM output control register 2 I2 C address register (00CF16) (00D5 16) (00D6 16) (00D8 16) (00D9 16) (00DA16) (00DB16) (00DC16) (00E016) (00E116) (00E216) (00E416) (00E516) 0016 000 0016 00010 00V 0016 0016 0000000 000000 VVV VVV V VV V VVV V VVVV V V 000000 FF16 0716 FF16 0716 00000 000000 000 1 00000000 000 00000000 0 0 00 VVVVV1 VV Contents of addressFFFF16 Contents of addressFFFE16 I2 C status register I2 C control register I2 C clock control register Serial I/O mode register Horizontal register Vertical position register 1 Vertical position register 2 Character size register Border selection register Note : The contents of all other registers and RAM are undefined at reset, so their initial values. V : Undefined : Unused bit Fig. 51. Internal state of microcomputer at reset 47 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER Ports P00–P05, P32 Direction register N-channel open-drain output Ports P00–P05, P32 Data bus Port latch Note: Each port is also used as below: P00–P05 : PWM0–PWM5 Ports P1, P2, P30, P31 Direction register CMOS output Data bus Port latch Ports P1, P2, P30, P31 Note: Each port is also used as below: P20 : SCLK P10 : OUT2 P11 : SCL1 P21 : SOUT P12 : SCL2 P22 : SIN P13 : SDA1 P23 : TIM3 P24 : TIM2 P14 : SDA2 P15 : A-D1/INT3 P30 : A-D5 P31 : A-D6 P16 : A-D2 P17 : A-D3 Ports P06, P07 Direction register N-channel open-drain output Ports P06, P07 Data bus Port latch Note: Each port is also used as below: P06 : INT2/A-D4 P07 : INT1 Fig. 52. I/O pin block diagram (1) 48 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER HSYNC, VSYNC Schmidt input D-A, R, G, B, OUT1, OUT2 Internal circuit HSYNC, VSYNC CMOS output Internal circuit D-A, R, G, B, OUT1, OUT2 Note : Each pin is also used as below : R : P52 G : P5 3 B : P54 OUT1 : P55 OUT2 : P10 Fig. 53. I/O pin block diagram (2) 49 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER CLOCK GENERATING CIRCUIT The built-in clock generating circuit is shown in Figure 56. When the STP instruction is executed, the internal clock φ stops at “H” level. At the same time, timers 3 and 4 are connected in hardware and “FF16” is set in the timer 3, “0716” is set in the timer 4. Select f(XIN)/16 as the timer 3 count source (set bit 0 of the timer 34 mode register to “0” before the execution of the STP instruction). And besides, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before execution of the STP instruction. The oscillator restarts when external interrupt is accepted, however, the internal clock φ keeps its “H” level until timer 4 overflows. Because this allows time for oscillation stabilizing when a ceramic resonator or a quartz-crystal oscillator is used. When the WIT instruction is executed, the internal clock φ stops in the “H” level but the oscillator continues running. This wait state is released when an interrupt is accepted (Note). Since the oscillator does not stop, the next instruction can be executed at once. When returning from the stop or the wait state, to accept an interrupt, set the corresponding interrupt enable bit to “1” before executing the STP or the WIT instructions. The circuit example using a ceramic resonator (or a quartz-crystal oscillator) is shown in Figure 54. Use the circuit constants in accordance with the resonator manufacture’s recommended values. The circuit example with external clock input is shown in Figure 55. Input the clock to the XIN pin, and open the XOUT pin. Note: In the wait mode, the following interrupts are invalid. (1) VSYNC interrupt (2) CRT interrupt (3) f(XIN)/4096 interrupt (4) Timer 1 interrupt using f(XIN)/4096 as count source (5) Timer 2 interrupt using P24/TIM2 pin input as count source (6) Timer 3 interrupt using P23/TIM3 pin input as count source (7) Timer 4 interrupt using f(XIN)/2 as count source (8) Multi-master I2C-BUS interface interrupt M37221M6-XXXSP X IN 19 XOUT 20 CIN COUT Fig. 54. Ceramic resonator circuit example M37221M6-XXXSP XIN 19 Vcc External oscillation circuit Vss Fig. 55. External clock input circuit example Interrupt request S Q Q S Reset Interrupt disable flag I S Q Reset WIT instruction R R STP instruction R STP instruction Internal clock φ . Selection gate : Connected to black colored side at reset. 1/2 1/8 T34M0 T34M2 Timer 3 Timer 4 XIN T34M : Timer 34 mode register XOUT Fig. 56. Clock generating circuit block diagram 50 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER DISPLAY OSCILLATION CIRCUIT The CRT display clock oscillation circuit has a built-in clock oscillation circuits, so that a clock for CRT display can be obtained simply by connecting an LC, an RC, a ceramic resonator or a quartz-crystal oscillator circuit across the pins OSC 1 and OSC 2. Select the clock for display with bits 0 and 1 of the CRT clock selection register (address 00ED16). ADDRESSING MODE The memory access is reinforced with 17 kinds of addressing modes. Refer to the SERIES 740 User’s Manual for details. MACHINE INSTRUCTIONS There are 71 machine instructions. Refer to the SERIES 740 User’s Manual for details. PROGRAMMING NOTES OSC1 OSC2 L C1 C2 Fig. 57. Display oscillation circuit AUTO-CLEAR CIRCUIT When power source is supplied, the auto-clear function can be performed by connecting the following circuit to the RESET pin. (1) The divide ratio of the timer is 1/(n+1). (2) Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. (3) After the ADC and SBC instructions are executed (in decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. (4) An NOP instruction is needed immediately after the execution of a PLP instruction. (5) In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1 µ F) directly between the VCC pin–VSS pin and the VCC pin– CNVSS pin using a thick wire. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: Circuit example 1 (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (32-pin DIP type 27C101 three identical copies) Vcc RESET Vss Circuit example 2 RESET Vcc Vss Note : Make the level change from “L” to “H” at the point at which the power source voltage exceeds the specified voltage. Fig. 58. Auto-clear circuit example 51 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VI Input voltage Input voltage Parameter Power source voltage VCC CNVSS P00–P07,P10–P1 7, P2 0–P27, P30–P34, OSC1, XIN, H SYNC, VSYNC, RESET P06, P07, P1 0–P17 , P20–P2 7, P30–P32, R, G, B, OUT1, D-A, XOUT, OSC2 P00–P05 R, G, B, OUT1, P10–P17, P20–P27, P3 0, P31, D-A R, G, B, OUT1, P06, P07, P1 0, P15–P17, P2 0–P23 , P30–P3 2, D-A P1 1–P14 P00–P05 P24–P27 Ta = 25 °C Conditions All voltages are based on VSS. Output transistors are cut off. Ratings –0.3 to 6 –0.3 to 6 –0.3 to VCC + 0.3 Unit V V V VO Output voltage –0.3 to VCC + 0.3 V VO IOH IOL1 Output voltage Circuit current Circuit current –0.3 to 13 0 to 1 (Note 1) 0 to 2 (Note 2) V mA mA IOL2 IOL3 IOL4 Pd Topr Tstg Circuit current Circuit current Circuit current Power dissipation Operating temperature Storage temperature 0 to 6 (Note 2) 0 to 1 (Note 2) 0 to 10 (Note 3) 550 –10 to 70 –40 to 125 mA mA mA mW °C °C RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) Symbol VCC VSS VIH1 Parameter Power source voltage (Note 4), During CPU, CRT operation Power source voltage “H” input voltage P00–P0 7,P10–P1 7, P20–P2 7, P30 –P34, SIN, SCLK, HSYNC, VSYNC, RESET, XIN, OSC1, TIM2, TIM3, INT1, INT2, INT3 “H” input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) “L” input voltage P00–P0 7,P10–P1 7, P20–P2 7, P30 –P34 “L” input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) “L” input voltage HSYNC, VSYNC, RESET, TIM2, TIM3, INT1, INT2, INT3, XIN, OSC1, SIN, SCLK “H” average output current (Note 1) R, G, B, OUT1, D-A, P10–P17, P2 0–P27 , P30, P3 1 “L” average output current (Note 2) R, G, B, OUT1, D-A, P06, P07, P1 0, P15–P1 7, P20 –P27, P3 0–P32 “L” average output current (Note 2) P11–P1 4 “L” average output current (Note 2) P00–P0 5 “L” average output current (Note 3) P24–P2 7 Oscillation frequency (for CPU operation) (Note 5) XIN Oscillation frequency (for CRT display) (Note 5) OSC1 Input frequency TIM2, TIM3 Input frequency SCLK Input frequency SCL1, SCL2 Min. 4.5 0 0.8VCC Limits Typ. 5.0 0 Max. 5.5 0 VCC Unit V V V VIH2 VIL1 VIL2 VIL3 I OH I OL1 I OL2 I OL3 I OL4 f CPU f CRT f hs1 f hs2 f hs3 0.7VCC 0 0 0 VCC 0.4 VCC 0.3 VCC 0.2 VCC 1 2 6 1 10 8.1 8.0 100 1 400 V V V V mA mA mA mA mA MHz MHz kHz MHz kHz 7.9 5.0 8.0 Notes 1: The total current that flows out of the IC must be 20 mA (max.). 2: The total input current to IC (IOL1 + IOL2 + IOL3) must be 30 mA or less. 3: The total average input current for ports P24–P2 7 to IC must be 20 mA or less. 4: Connect 0.1 µF or more capacitor externally across the power source pins VCC–VSS so as to reduce power source noise. Also connect 0.1 µF or more capacitor externally across the pins VCC–CNVSS. 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. 52 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Symbol ICC Parameter Power source current System operation VCC = 5.5 V, f(X IN) = 8 MHz Stop mode VOH VOL “H” output voltage “L” output voltage Test conditions CRT OFF CRT ON Limits Min. Typ. 20 30 Max. 40 60 300 2.4 0.4 µA V V Unit mA VCC = 5.5 V, f(XIN) = 0 “L” output voltage “L” output voltage VT+–VT– Hysteresis Hysteresis (Note) R, G, B, OUT1, D-A, P10–P1 7, VCC = 4.5 V I OH = –0.5 mA P20–P2 7, P30, P3 1 R, G, B, OUT1, D-A, P00–P0 7, VCC = 4.5 V I OL = 0.5 mA P10, P1 5–P17, P2 0–P23 , P30–P3 2 VCC = 4.5 V I OL = 3 mA P11–P1 4 I OL = 6 mA P24–P2 7 RESET VCC = 4.5 V I OL = 10.0 mA VCC = 5.0 V 0.4 0.6 3.0 0.5 0.5 0.7 1.3 V IIZH IIZL IOZH RBS VCC = 5.0 V HSYNC, VSYNC, TIM2, TIM3, INT1, INT2, INT3, SCL1, SCL2, SDA1, SDA2, SIN, SCLK VCC = 5.5 V “H” input leak current RESET, P00–P0 7, P10 –P17, VI = 5.5 V P20–P2 7, P30–P3 4, HSYNC, VSYNC VCC = 5.5 V “L” input leak current RESET, P00–P0 7, P10 –P17, VI = 0 V P20–P2 7, P30–P3 4, HSYNC, VSYNC VCC = 5.5 V “H” output leak current P00–P0 5 VO = 12 V I2 C-BUS·BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) VCC = 4.5 V 5 µA 5 µA 10 130 µA Ω Note: P06, P0 7, P1 5, P23 , P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P2 0–P22 have the hysteresis when these pins are used as serial I/O pins. P11–P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface pins. 53 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER A-D COMPARATOR CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Symbol — — Resolution Absolute accuracy 0 ±1 Parameter Test conditions Limits Min. Typ. Max. 6 ±2 Unit bits LSB Note: When VCC = 5 V, 1 LSB = 5/64 V. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS Symbol tBUF tHD:STA tLOW tR tHD:DAT tHIGH tF tSU:DAT tSU:STA tSU:STO Bus free time Hold time for START condition “L” period of SCL clock Rising time of both SCL and SDA signals Data hold time “H” period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition 250 4.7 4.0 0 4.0 300 Standard clock mode High-speed clock mode Parameter Min. 4.7 4.0 4.7 1000 Max. Min. 1.3 0.6 1.3 20+0.1Cb 0 0.6 20+0.1Cb 100 0.6 0.6 300 300 0.9 Max. Unit µs µs µs ns µs µs ns ns µs µs Note: Cb = total capacitance of 1 bus line SDA tHD:STA tSU:STO tBUF tLOW p SCL S tR tF Sr p tHD:STA tHD:DAT tHIGH tSU:DAT tSU:STA Fig. 59. Definition diagram of timing on multi-master I2C-BUS 54 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER PACKAGE OUTLINE 55 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER GZZ–SH09–46B < 52B0 > Mask ROM number 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M6-XXXSP MITSUBISHI ELECTRIC Date : Receipt Section head signature Supervisor signature Note : Please fill in all items marked g. signature Issuance Company name TEL ( Date : ) Submitted by Supervisor g Customer Date issued g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern. If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM EPROM type (indicate the type used) (hexadecimal notation) 27C101 EPROM address 000016 Product name 000F16 A00016 FFFF 16 1000016 107FF16 10800 16 10FFF16 11000 16 117FF16 11800 16 11FFF16 1FFFF 16 ASCII code : ‘M37221M6 –’ data ROM 24K bytes Character ROM 1-a Character ROM 2-a Character ROM 1-b Character ROM 1-b (1) (2) Set “FF 16” in the shaded area. Write the ASCII codes that indicates the product name of “M37221M6–” to addresses 0000 16 to 000F 16. EPROM data check item (Refer the EPROM data and check “ ” in the appropriate box) → Yes q Do you set “FF 16” in the shaded area ? q Do you write the ASCII codes that indicates the product → Yes name of “M37221M6–” to addresses 0000 16 to 000F 16 ? g 2. Mark specification Mark specification must be submitted using the correct form for the type package being ordered fill out the appropriate mark specification form (42P4B for M37221M6-XXXSP) and attach to the mask ROM confirmation form. g 3. Comments (1/3) 56 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER GZZ–SH09–46B 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M6-XXXSP MITSUBISHI ELECTRIC Writing the product name and character ROM data onto EPROMs Addresses 0000 16 to 000F 16 store the product name, and addresses 10000 16 to 11FFF 16 store the character pattern. If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Write the data correctly. 1. Inputting the name of the product with the ASCII code ASCII codes ‘M37221M6-’ are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 ‘M’ = ‘3’ = ‘7’ = ‘2’ = ‘2’ = ‘1’ = ‘M’ = ‘6’ = 4D 33 37 32 32 31 4D 36 16 16 16 16 16 16 16 16 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 ‘–’ = 2 D FF FF FF FF FF FF FF 16 16 16 16 16 16 16 16 2. Inputting the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2. For the character ROM data, see the next page and on. (2/3) 57 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER GZZ–SH09–46B< 52B0 > 740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37221M6-XXXSP MITSUBISHI ELECTRIC The structure of character ROM (divided of 12 !16 dots font) Example Character code “1A16” (Note) Write the character code “00 16” to “7F 16” to addreses 10000 16 to 10FFF 16. Write the character code “80 16” to “FF 16” to addreses 11000 16 to 11FFF 16. Character ROM1 Character ROM2 ⇐ Example 101A016 0 to 1 101AF16 2 3 4 5 6 7 8 9 A B C D E F b 7 b6 b 5 b 4 b 3 b2 b 1 b 0 0016 0416 0416 0A16 0A16 1116 1116 1116 2016 2016 3F16 4016 4016 4016 0016 0016 ⇐ Example 109A016 0 to 1 109AF16 2 3 4 5 6 7 8 9 A B C D E F b 7 b6 b 5 b4 b 3 b2 b 1 b0 F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016 F16 (3/3) 58 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER 59 MITSUBISHI MICROCOMPUTERS M37221M6-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER MITSUBISHI DATA BOOK SINGLE-CHIP 8-BIT MICROCOMPUTERS Vol.3 Sep. First Edition 1996 H-DF319-B Editioned by Committee of editing of Mitsubishi Semiconductor Data Book Published by Mitsubishi Electric Corp., Semiconductor Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. ©1996 MITSUBISHI ELECTRIC CORPORATION Printed in Japan REVISION DESCRIPTION LIST Rev. No. 1.0 2.0 2.1 First Edition M37221M6–XXXSP DATA SHEET Revision Description Rev. date 9708 971130 980731 Information about copywright note, revision number, release data added (last page). Correct note (P50). (1/1)