M37225M6

M37225M6/M8/MA/MC–XXXSP, M37225ECSP SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER REJ03B0136-0100Z Rev.1.00 Nov 01, 2000 1. DESCRIPTION The M37225M6/M8/MA/MC–XXXSP are single-chip microcomputers designed with CMOS silicon gate technology. They have a OSD, I2C-BUS interface, PWM output, and 12 V withstand, so it is useful for a channel selection system for TV. The features of the M37225ECSP are similar to those of the M37225M6-XXXSP except that the chip has a built-in PROM which can be written electrically. The differences amang M37225M6/M8/ MA/MC–XXXSP are the ROM, RAM size. Accordingly, the following descriptions will be for the M37225M6-XXXSP. 2. FEATURES q Number of basic instructions .................................................... 71 q Memory size ROM ......... 24K bytes (M37225M6-XXXSP) 32K bytes (M37225M8-XXXSP) 40K bytes (M37225MA–XXXSP) 48K bytes (M37225MC–XXXSP, M37225ECSP) RAM ......... 1024 bytes (M37225M6/M8-XXXSP) 2048 bytes (M37225MA/MC–XXXSP, M37225ECSP) (✽ ROM correction memory included) q Minimum instruction execution time ......................................... 0.5 µs (at 8 MHz oscillation frequency) q Power source voltage ................................................. 5 V ± 10 % q Subroutine nesting ............................................. 128 levels (Max.) q Interrupts ....................................................... 16 types, 16 vectors q 8-bit timers .................................................................................. 4 q Programmable I/O ports (Ports P0, P1, P2, P30–P32, P35) ..... 28 q Input ports (Ports P33, P34, P50, P51) ........................................ 4 q Output ports (Ports P52–P55) ..................................................... 4 q 12 V withstand ports ................................................................... 6 q LED drive ports ........................................................................... 4 qSerial I/O ............................................................ 8-bit ✕ 1 channel q Multi-master I2C-BUS interface .............................. 1 (2 systems) q A-D converter (8-bit resolution) .................................... 8 channels q PWM output circuit ........................................ 14-bit ✕ 2, 8-bit ✕ 6 q Power dissipation In operating ...................................................................... 165 mW (at VCC = 5.5V, 8 MHz oscillation frequency, and OSD on) q ROM correction function ................................................ 3 vectors q Immediate return mode from wait state q OSD function Display characters ............................................... 24 characters ✕ 2 lines (It is possible to display 3 lines or more by software) Kinds of characters ......... 381 kinds Character display area 16 ✕ 20 dots Kinds of character sizes .............................. Block display: 3 kinds SPRITE display: 1 kinds Kinds of character colors. ................................. 8 colors (R, G, B) Coloring unit ................... character, character background, raster Display position Horizontal: 64 levels Vertical :255 levels Attribute ........ Border (all-bordered, shadow-bordered), BUTTON SPRITE display function Wallpaper function Window function Corresponding to bi-scan mode 3. APPLICATION TV Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 1 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP TABLE OF CONTENTS 1. DESCRIPTION .......................................................................... 1 2. FEAUTURES ............................................................................. 1 3. APPLICATION ............................................................................ 1 4. PIN CONFIGURATION .............................................................. 3 5. FUNCTIONAL BLOCK DIAGRAM ............................................. 4 6. PERFORMANCE OVERVIEW ................................................... 5 7. PIN DESCRIPTION ................................................................... 7 8. FUNCTIONAL DESCRIPTION ................................................. 11 8.1 CENTRAL PROCESSING UNIT (CPU) .................... 11 8.2 MEMORY .................................................................. 12 8.3 INTERRUPTS ........................................................... 19 8.4 TIMERS ..................................................................... 24 8.5 SERIAL I/O ................................................................ 27 8.6 MULTI-MASTER I2C-BUS INTERFACE .................... 31 8.7 PWM OUTPUT CIRCUIT .......................................... 44 8.8 A-D CONVERTER ..................................................... 49 8.9 ROM CORRECTION FUNCTION ............................. 53 8.10 OSD FUNCTIONS ................................................... 54 (1) Clock for OSD .................................................... 57 (2) Scan mode ......................................................... 58 (3) OSD input/output pin control .............................. 59 8.10.1 Block Display .................................................... 60 (1) Display position .................................................. 61 (2) Dot size .............................................................. 65 (3) Memory For OSD ............................................... 66 (4) Character Color .................................................. 69 (5) Character Background Color .............................. 69 (6) OUT1, OUT2 Signals ......................................... 69 (7) Attribute .............................................................. 72 (8) Multiple Display .................................................. 76 (9) Window Function ................................................ 77 8.10.2 SPRITE Display ................................................ 80 8.10.3 Raster Display ................................................... 83 8.11. SOFTWARE RUNAWAY DETECT FUNCTION ...... 85 8.12. RESET CIRCUIT .................................................... 86 8.13. CLOCK GENERATING CIRCUIT ........................... 87 8.14. DISPLAY OSCILLATION CIRCUIT ........................ 88 8.15. AUTO-CLEAR CIRCUIT ......................................... 88 8.16. ADDRESSING MODE ............................................ 88 8.17. MACHINE INSTRUCTIONS ................................... 88 9. PROGRAMMING NOTES ........................................................ 88 10. ABSOLUTE MAXIMUM RATINGS ......................................... 89 11. RECOMMENDED OPERATING CONDITIONS ..................... 89 12. ELECTRIC CHARACTERISTICS .......................................... 90 13. A-D CONVERTER CHARACTERISTICS ............................... 92 14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS ........... 92 15. PROM PROGRAMMING METHOD ....................................... 93 16. DATA REQUIRED FOR MASK ORDERS .............................. 94 17. ONE TIME PROM VERSIONS M37225ECSP MARKING ..... 95 18. APPENDIX ............................................................................. 96 19. PACKAGE OUTLINE ........................................................... 124 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 2 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 4. PIN CONFIGURATION HSYNC/P50 VSYNC/P51 P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 DA1/P35 P32/A-D7 CNVSS XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 R/P52 G/P53 B/P54 OUT1/P55 P20/SCLK P21/SOUT(/SIN) P22/SIN P10/OUT2/A-D8 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/INT3/A-D1 P16/A-D2 P17/DA2/A-D3 P30/A-D5 P31/A-D6 RESET OSC1/P33 OSC2/P34 VCC Outline 42P4B M37225M6/M8/MA/MC-XXXSP M37225ECSP Fig. 4.1 Pin Configuration (Top View) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 3 of 124 Input ports P33, P34 Clock input for OSD Clock output for OSD OSC2 23 Clock input Clock output XIN XOUT VCC VSS CNVSS OSC1 24 21 18 22 25 Reset input RESET INT3 INT2 INT1 SIN SCLK SOUT PWM5 PWM4 PWM3 PWM2 PWM1 SDA2 SDA1 SCL2 SCL1 PWM0 OUT2 OUT1 B G R 10 9 8 7 6 5 4 3 28 29 30 31 32 33 34 35 15 14 13 12 11 36 37 38 16 17 26 27 39 40 41 42 I/O port P0 I/O port P2 I/O ports P30–P32, P35 I/O port P1 Output ports P52–P55 OSD output Sync signal input Input ports P50, P51 VSYNC HSYNC Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z TIM2 TIM3 19 20 Clock generating circuit Timer count source selection circuit Fig. 5.1 Functional Block Diagram of M37225 Program counter Data bus 5. FUNCTIONAL BLOCK DIAGRAM M37225M6/M8/MA/MC-XXXSP, M37225ECSP page 4 of 124 ROM Timer 1 T1 (8) PCL (8) Timer 2 T2 (8) Timer 3 T3 (8) Control signal Instruction decoder Instruction register (8) OSD circuit Timer 4 T4 (8) Index register Y (8) Stack pointer S (8) 14-bit PWM circuit 1 P2 (8) P3 (6) RAM Program counter PCH (8) Address bus 8-bit arithmetic and logical unit Accumulator A (8) Processor status register PS (8) Index register X (8) 14-bit PWM circuit 2 A-D converter Multi-master I2C-BUS interface SI/O(8) 8-bit PWM circuit ROM correction function P 5 ( 6) P0 (8) P1 (8) 2 1 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 6. PERFORMANCE OVERVIEW Table 6.1 Performance Overview Parameter Number of basic instructions Instruction execution time Clock frequency Memory size Functions 71 0.5 µs (the minimum instruction execution time, at 8 MHz oscillation frequency) 8 MHz (maximum) 24K bytes 32K bytes 40K bytes 48K bytes 1024 bytes (ROM correction memory included) 2048 bytes (ROM correction memory included) 15K bytes 96 bytes 6-bit ✕ 1 (N-channel open-drain output structure, can be used as PWM output pins) 2-bit ✕ 1 (N-channel open-drain output structure, can be used as INT input pins, A-D input pin) 8-bit ✕ 1 (CMOS input/output structure, can be used as OSD output pin, INT input pin, A-D input pins, DA output pin, multi-master I2C-BUS interface) 8-bit ✕ 1 (CMOS input/output structure, can be used as serial I/O pins, timer external clock input pins) 3-bit ✕ 1 (CMOS output structure, or N-channel open-drain output structure, can be used as A-D input pins, DA output pin) 1-bit ✕ 1 (N-channel open-drain output structure, can be used as A-D input pin) 2-bit ✕ 1 (Can be used as OSD clock input/output pins) 2-bit ✕ 1 (N-channel open-drain output structure, can be used as horizonal • vertical synchronous sibnal input pins) 4-bit ✕ 1 (CMOS output structure, can be used as OSD output pins) 8-bit ✕ 1 1 (2 systems) 8 channels (8-bit resolution) 14-bit ✕ 2, 8-bit ✕ 6 8-bit timer ✕ 4 3 vectors 128 levels (maximum) INT external interrupt ✕ 3, Internal timer interrupt ✕ 6, Serial I/O interrupt ✕ 1, OSD interrupt ✕ 1 , Multi-master I2 C-BUS interface interrupt ✕ 1 , f(XIN)/4096 interrupt ✕ 1, SPRITE OSD interrupt ✕ 1, A-D conversion interrupt ✕ 1, VSYNC interrupt ✕ 1, BRK instruction interrupt ✕ 1, reset ✕ 1 2 built-in circuits (externally connected to a ceramic resonator or a quartzcrystal oscillator) ROM M37225M6-XXXSP M37225M8-XXXSP M37225MA-XXXSP M37225MC-XXXSP, M37225ECSP RAM M37225M6/M8-XXXSP M37225MA/MC-XXXSP, M37225ECSP OSD ROM OSD RAM P00–P05 I/O P06, P07 P1 P2 P30, P31, P35 P32 P33, P34 P50, P51 I/O I/O I/O I/O I/O Input Input Output Input/Output ports P52–P55 Serial I/O Multi-master I2C-BUS interface A-D converter PWM output circuit Timers ROM correction function Subroutine nesting Interrupt Clock generating circuit Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 5 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Table 6.2 Performance Overview (Continued) Parameter Number of display characters Dot structure Kinds of characters Kinds of character sizes Character font coloring Display position Functions 24 characters ✕ 2 lines 16 ✕ 20 dots 381 kinds 3 kinds 1 screen : 8 kinds (per character unit) Horizontal : 64 levels, Vertical : 255 levels 5V ± 10% 165 mW typ. ( at oscillation frequency f(XIN) = 8 MHz, fOSC = 8 MHz) 110 mW typ. ( at oscillation frequency f(XIN) = 8 MHz) 1.65 mW ( maximum ) –10 °C to 70 °C CMOS silicon gate process 42-pin plastic molded SDIP OSD function Power source voltage OSD ON Power dissipation OSD OFF In stop mode Operating temperature range Device structure Package Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 6 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 7. PIN DESCRIPTION Table 7.1 Pin Description Pin VCC, VSS CNVSS ______ Name Power source CNVSS Reset input Input/ Output Functions Apply voltage of 5 V ± 10 % to (typical) VCC, and 0 V to VSS. This is connected to VSS. RESET Input To enter the reset state, the reset input pin must be kept at a LOW for 2 µs or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT. If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is N-channel open-drain output. (See note 1) Pins P00–P05 are also used as PWM output pins PWM0–PWM5 respectively. The output structure is N-channel open-drain output. Pins P06 a nd P0 7 a re also used as INT external interrupt input pins INT2 and INT1 respectively. P06 pin is also used as analog input pin A-D4. Port P1 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. (See note 1) Pins P10 is also used as OSD output pin OUT2. The output structure is CMOS output. Pins P11–P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-BUS interface is used. The output structure is N-channel open-drain output. Pins P10, P15–P17 are also used as analog input pin A-D8, A-D1–A-D3 respectively. P15 pin is also used as INT external interrupt input pin INT3. Pins P17 is also used as 14-bit PWM output pin DA2. The output structure is CMOS output. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The P21/SOUT(/SIN), output structure is CMOS output. (See note 1) P20 pin is also used as serial I/O synchronous clock input/output pin S CLK. The output structure is N-channel open-drain output. P2 1 p in is also used as serial I/O data input/output pin S OUT ( /S IN ). The output structure is N-channel open-drain output. P22 pin is also used as serial I/O data input pin SIN. Pins P2 3 a nd P2 4 a re also used as timer external clock input pins TIM3 and TIM2 respectively. Ports P30–P32 and P35 are a 3-bit I/O port and has basically the same functions as port 0 (see note 1). Either CMOS output or N-channel open-drain output structure can be selected as ports P3 0 , P3 1 a nd P3 5 . The output structure of port P3 2 i s N-channel open-drain output structure.(See notes 1, 2) Pins P30–P32 are also used as analog input pins A-D5–A-D7 respectively. P35 pin is also used as 14-bit PWM output pin DA1. The output structure is CMOS output. At reset, output is undefined. Pins P33 and P34 are a 2-bit input port. P33 pin is also used as OSD clock input pin OSC1. P34 pin is also used as OSD clock output pin OSC2. The output structure is CMOS output. XIN XOUT Clock input Clock output Input Output I/O P00/PWM0– I/O port P0 P05/PWM5, P06/INT2/A-D4, P07/INT1 PWM output External interrupt input Analog input P10/OUT2/A-D8, I/O port P1 P11/SCL1, P12/SCL2, OSD output P13/SDA1, Multi-master P14/SDA2, I2C-BUS interface P15/INT3/A-D1, Analog input P16/A-D2, External interrupt P17/DA2/A-D3 input DA output P20/SCLK, P22/SIN, P23/TIM3, P24/TIM2, P25–P27 I/O port P2 Serial I/O synchronous clock input/output port Serial I/O data input/output Serial I/O data input External clock input for timer P30/A-D5, P31/A-D6, P32/A-D7, DA1/P35 I/O port P3 Output Input Input I/O Output I/O Input Input Output I/O I/O I/O Input Input I/O Analog input DA output OSC1/P33, Input port P3 OSC2/P34, Clock input for OSD Clock output for OSD Input Output Input Input Output Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 7 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Table 7.2 Pin Description (continued) Pin Name Input/ Output Input Input Input Output Output Ports P50 and P51 are a 2-bit input port. This is a horizontal synchronizing signal input for OSD. This is a vertical synchronizing signal input for OSD. Ports P52–P55 are a 4-bit output port. The output structure is CMOS output. Pins P52–P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output structure is CMOS output. At reset, output is LOW. Functions HSYNC/P50, Input port P5 VSYNC/P51 R/P52, G/P53, B/P54, OUT1/P55 HSYNC input VSYNC input Output port P5 OSD output Notes 1: Port Pi (i = 0 to 3) has the port Pi direction register which can be used to program each bit as an input (“0”) or an output (“1”). The pins programmed as “1” in the direction register are output pins. When pins are programmed as “0,” they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output LOW voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state. 2: To switch output structures, set by the following bits. P30 : bit 6 of port P3 direction register P31 : bit 7 of port P3 direction register P35 : bit 5 of port P35 output mode control register When “0,” CMOS output; when “1,” N-channel open-drain output. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 8 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Ports P00–P05 N-channel open-drain output Direction register Ports P00–P05 Data bus Port latch Note : Each port is also used as follows : P0 0–P05 : PWM0–PWM5 Ports P1, P2, P30, P31 Direction register CMOS output Ports P1, P2, P30, P31, P35 Notes 1: Each port is also used as follows : P10 : OUT2/AD8 P22 : SIN P11 : SCL1 P23 : TIM3 P12 : SCL2 P24 : TIM2 P13 : SDA1 P30 : A-D5 P14 : SDA2 P31 : A-D6 P15 : INT3/A-D1 P35 : DA1 P16 : A-D2 P17 : DA2/A-D3 P20 : SCLK P21 : SOUT/(SIN) 2: Either CMOS output or N-channel opendrain output structure can be selected as ports P30, P31 and P35 (when selecting N-channel open-drain, it is the same with N-channel open-drain output below). Data bus Port latch Ports P06, P07, P32 N-channel open-drain output Direction register Ports P06, P07, P32 Data bus Port latch Note : Each port is also used as follows : P06 : INT2/A-D4 P07 : INT1 Fig. 7.1 I/O Pin Block Diagram (1) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 9 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP P52–P55 Data bus Internal circuit Port latch CMOS output Ports P52–P55 Note : Each pin is also used as follows : P52 : R P53 : G P54 : B P55 : OUT1 P50, P51 Data bus Internal circuit Schmidt input Ports P50, P51 Note : Each pin is also used as follows : P50 : HSYNC P51 : VSYNC P33, P34 Input Data bus Ports P33, P34 Note : Each pin is also used as follows : P33 : OSC1 P34 : OSC2 Fig. 7.2 I/O Pin Block Diagram (2) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 10 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8. FUNCTIONAL DESCRIPTION 8.1 CENTRAL PROCESSING UNIT (CPU) This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 User’s Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instructions can be used. 8.1.1 CPU Mode Register The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated at address 00FB16. CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 00111 00 CPU mode register (CM) [Address 00FB16] B Name b1 b0 Functions 0 0 1 1 0: Single-chip mode 1: 0: Not available 1: After reset R W 0 RW 0, 1 Processor mode bits (CM0, CM1) 2 Stack page selection bit (CM2) (See note) 3 to 5 Fix these bits to “1.” 6, 7 Fix these bits to “0.” 0: 0 page 1: 1 page 1 1 0 RW RW RW Note: This bit is set to “1” after the reset release. Fig. 8.1.1 CPU Mode Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 11 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.2 MEMORY 8.2.1 Special Function Register (SFR) Area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. 8.2.2 RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. 8.2.3 ROM ROM is used for storing user programs as well as the interrupt vector area. 8.2.4 OSD RAM RAM for display is used for specifying the character codes and colors to display. 8.2.5 OSD ROM ROM for display is used for storing character data. 8.2.6 Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. 8.2.7 Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. 8.2.8 Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. 8.2.9 ROM Correction Vector This is used as the program jump destination addresses for ROM correction. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 12 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP sM37225M6/M8-XXXSP 000016 00BF16 00C016 SFR area 00FF16 010016 01FF16 Not used 021716 021D 16 (1024 bytes) 024016 2 page register (2) 024F16 02C016 ROM correction function 02E016 030016 Vector 1: address 02C016 Vector 2: address 02E016 Vector 3: address 030016 15C0016 15CFF16 Not used 04FF16 OSD RAM (96 byres) (See note) Not used 080016 087716 1600016 160FF16 Not used 1620016 162FF16 Not used 1640016 164FF16 Not used 1660016 166FF16 Not used 1680016 168FF16 Not used 16A0016 16AFF16 Not used 16C0016 16CFF16 Not used 16E0016 Not used 16EFF16 Not used 1700016 170FF16 Not used 1720016 172FF16 Not used 1740016 174FF16 Not used 1760016 176FF16 Not used 1780016 178FF16 Not used 17A0016 17AFF16 15E0016 15EFF16 Not used 15A0016 15AFF16 Not used Not used 1580016 158FF16 Not used 2 page register (1) Not used 1000016 1140016 Zero page OSD ROM (15K bytes) 13BFF16 Not used 1540016 154FF16 Not used 1560016 156FF16 Not used Not used M37225M8XXXSP ROM (32K bytes) M37225M6XXXSP ROM (24K bytes) 800016 A00016 Not used FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.10.3 OSD RAM. Fig. 8.2.1 Memory Map (M37225M6/M8-XXXSP) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 13 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP sM37225MA/MC-XXXSP, M37225ECSP 000016 00BF16 00C016 00FF16 010016 01FF16 Not used R AM (2048 bytes) 021716 021D 16 024016 2 page register (2) 024F16 02C016 ROM correction function 02E016 030016 Vector 1: address 02C016 Vector 2: address 02E016 Vector 3: address 030016 15C0016 15CFF16 Not used OSD RAM (96 bytes) (See note) 07FF16 080016 087716 Not used 090016 09FF16 1620016 162FF16 Not used 1640016 164FF16 Not used 1660016 166FF16 Not used 1680016 168FF16 Not used 16A0016 16AFF16 Not used 16C0016 16CFF16 Not used Not used 16E0016 16EFF16 Not used 1700016 170FF16 Not used 1720016 172FF16 Not used 1740016 174FF16 Not used 1760016 176FF16 Not used 1780016 178FF16 Not used 17A0016 17AFF16 M37225MC-XXXSP M37225ECSP ROM (48K bytes) 400016 600016 M37225MA-XXXSP ROM (40K bytes) Not used 15E0016 15EFF16 Not used 1600016 160FF16 Not used 15A0016 15AFF16 Not used Not used 1580016 158FF16 Not used 2 page register (1) Not used 1000016 1140016 Zero page SFR area OSD ROM (15K bytes) 13BFF16 Not used 1540016 154FF16 Not used 1560016 156FF16 Not used Not used FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.10.3 OSD R AM. Fig. 8.2.2 Memory Map (M37225MA/MC-XXXSP, M37225ECSP) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 14 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP s SFR area (addresses C016 to DF16) < Bit allocation > < State immediately after reset > : Name Function bit 0 : “0” immediately after reset 1 : “1” immediately after reset ? : Indeterminate immediately after reset : : No function bit 0 : Fix to this bit to “0” (do not write to “1”) 1 : Fix to this bit to “1” (do not write to “0”) Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) Port P35 output mode control register (P3S) Port P5 (P5) OSD port control register (PF) Test register Interrupt input polarity register (IP) DA1-H register (DA1-H) DA1-L register (DA1-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2C control register (S1D) I2C clock control register (S2) Serial I/O mode register (SM) Serial I/O register (SIO) AD conversion register (AD) AD control register (ADCON) PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 P35 P34IN P33IN P32 P31S P30S P35D P31 P30 P32D P31D P30D Bit allocation b7 State immediately after reset b0 b7 b0 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 P35S P50 IN P55 P54 P53 P52 P51 OUT OUT OUT OUT IN OUT2 P55 P54 P53 P52 SEL SEL SEL SEL SEL 0 0 1 0 POL3 POL2 POL1 1 0 OCG1OCG0 0 0 ? 0 D7 0 D6 PN5 PN4 PN3 PN2 D5 D4 D3 D2 0 D1 0 D0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB PIN AL AAS AD0 LRB 0 0 0 BSEL1 BSEL0 10BIT ALS ESO BC2 BC1 BC0 SAD FAST ACK ACK MODE CCR4 CCR3 CCR2 CCR1 CCR0 BIT SM6 SM5 0 SM3 SM2 SM1 SM0 0 0 ADVREF ADSTR ADIN2 ADIN1 ADIN0 ? 0016 ? 0016 ? 0016 ? ?? ? 0? ?? 0016 01 0016 ? ?? ? ? ? ? ? 0016 0016 ? 0016 10 0016 0016 0016 ? ? 0816 0 ? ? 1 0 ? ? ? 0 ? ? ? ? ? ? 0 0 ? Fig. 8.2.3 Memory Map of Special Function Register (SFR) (1) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 15 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP s SFR area (addresses E016 to FF16) < Bit allocation > < State immediately after reset > : Name Function bit 0 : “0” immediately after reset 1 : “1” immediately after reset ? : Indeterminate immediately after reset : : No function bit 0 : Fix to this bit to “0” (do not write to “1”) 1 : Fix to this bit to “1” (do not write to “0”) Address Register b7 Bit allocation BHP5 BHP4 BHP3 BHP2 BHP1 BHP0 B1VP7 B1VP6 B1VP5 B1VP4 B1VP3 B1VP2 B1VP1 B1VP0 B2VP7 B2VP6 B2VP5 B2VP4 B2VP3 B2VP2 B2VP1 B2VP0 SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 SHP7 SHP6 SHP5 SHP4 SHP3 SHP2 SHP1 SHP0 SVP7 SVP6 SVP5 SVP4 SVP3 SVP2 SVP1 SVP0 CO16 CO15 CO14 CO13 CO12 CO11 CO10 CO26 CO25 CO24 CO23 CO22 CO21 CO20 CO36 CO35 CO34 CO33 CO32 CO31 CO30 CO46 CO45 CO44 CO43 CO42 CO41 CO40 State immediately after reset b0 b7 b0 E016 Block H register (BHP) E116 Block 1V register (B1VP) E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Block 2V register (B2VP) SPRITE control register (SC) SPRITE H register (SHP) SPRITE V register (SVP) Color register 1 (CO1) Color register 2 (CO2) Color register 3 (CO3) Color register 4 (CO4) OSD control register (OC) OSD I/O polarity control register (OPC) Color register 5 (CO5) Color register 6 (CO6) Color register 7 (CO7) Color register 8 (CO8) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer mode register 1 (TM1) Timer mode register 2 (TM2) PWM5 register (PWM5) Test register Test register Block 1 control register (B1C) Block 2 control register (B2C) CPU mode register (CM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0 0 0 0 ? ? ? ? ? ? ? ? OC7 OC6 OC5 OC4 OC3 OC2 OC1 OC0 OPC7 OPC6 OPC5 OPC4 OPC3 OPC2 OPC1 OPC0 CO56 CO55 CO54 CO53 CO52 CO51 CO50 CO66 CO65 CO64 CO63 CO62 CO61 CO60 CO76 CO75 CO74 CO73 CO72 CO71 CO70 CO86 CO85 CO84 CO83 CO82 CO81 CO80 0 0 0 0 ? ? ? ? ? ? ? ? TM15 TM14 TM13 TM12 TM11 TM10 TM25 TM24 TM23 TM22 TM21 TM20 0016 0016 B1C4 B1C3 B1C2 B1C1 B1C0 B2C4 B2C3 B2C2 B2C1 B2C0 0 0 0 0 0 0 0 0 0 ADR 1 1 1 CM2 0 0 IT3R IICR VSCR OSDR TM4R TM3R TM2R TM1R MSR SPR S1R IT2R IT1R CK 0 IT3E IICE VSCE OSDE TM4E TM3E TM2E TM1E ADE 0 MSE SPE S1E IT2E IT1E 0016 ? ? 0016 0016 ? ?? ?? ?? ?? 0016 0016 ?? ?? ?? ?? FF16 0716 FF16 0716 0016 0016 ? ? ? CK 0 ? ? CK 0 ? ? 3C16 0016 0016 0016 0016 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Fig. 8.2.4 Memory Map of Special Function Register (SFR) (2) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 16 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP s 2 page register area (addresses 21016 to 21F16, 24016 to 24F16) < Bit allocation > < State immediately after reset > : Name Function bit 0 : “0” immediately after reset 1 : “1” immediately after reset ? : Indeterminate immediately after reset : : No function bit 0 : Fix to this bit to “0” (do not write to “1”) 1 : Fix to this bit to “1” (do not write to “0”) Address 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 21C16 21D16 21E16 21F16 24016 24116 24216 24316 24416 24516 24616 24716 24816 24916 24A16 24B16 24C16 24D16 24E16 24F16 Register Bit allocation b7 State immediately after reset b0 b7 b0 ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) ROM correction address 3 (high-order) ROM correction address 3 (low-order) 0 0 0 0 0 RCR2 RCR1RCR0 Left border control register (LBR) Right border control register (RBR) LBR6 LBR5 LBR4 LBR3 LBR2 LBR1 LBR0 RBR6 RBR5 RBR4 RBR3 RBR2 RBR1 RBR0 Top border control register (TBR) TBR7 TBR6 TBR5 TBR4 TBR3 TBR2 TBR1 TBR0 Bottom border control register (BBR) BBR7 BBR6 BBR5 BBR4 BBR3 BBR2 BBR1 BBR0 0016 Test register DA2-H register (DA2H) DA2-L register (DA2L) 0 0 ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 0016 0016 ? ? 0016 0016 ? ? ? ? ? 0016 ? ? ? ? ? ? ? ?? ? ? ? Fig. 8.2.5 Memory Map of 2 Page Register Area Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 17 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP < Bit allocation > < State immediately after reset > : Name Function bit 0 : “0” immediately after reset 1 : “1” immediately after reset ? : Indeterminate immediately after reset : : No function bit 0 : Fix to this bit to “0” (do not write to “1”) 1 : Fix to this bit to “1” (do not write to “0”) Register b7 Processor status register (PS) Program counter (PCH) Program counter (PCL) Bit allocation N V T B D I Z C State immediately after reset b0 b7 b0 ?????1?? Contents of address FFFF16 Contents of address FFFE16 Fig. 8.2.6 Internal State of Processor Status Register and Program Counter at Reset Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 18 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.3 INTERRUPTS Interrupts can be caused by 16 different sources consisting of 3 external, 14 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in Table 8.3.1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, x The contents of the program counter and processor status register are automatically stored into the stack. ➁ The interrupt disable flag I is set to “1” and the corresponding interrupt request bit is set to “0.” ➂ The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to “1.” All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is “1,” interrupt request bit is “1,” and the interrupt disable flag is “0.” The interrupt request bit can be set to “0” by a program, but not set to “1.” The interrupt enable bit can be set to “0” and “1” by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 8.3.1 shows interrupt control. 8.3.1 Interrupt Causes (1) VSYNC, OSD, SPRITE OSD Interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed. The SPRITE OSD interrupt occurs at the completion of SPRITE display. (2) INT1 to INT3 External Interrupts The INT1 to INT3 interrupts are external interrupt inputs, the system detects that the level of a pin changes from LOW to HIGH or from HIGH to LOW, and generates an interrupt request. The input active edge can be selected by bits 3 to 5 of the interrupt input polarity register (address 00CD16) : when this bit is “0,” a change from LOW to HIGH is detected; when it is “1,” a change from HIGH to LOW is detected. Note that both bits are cleared to “0” at reset. (3) Timers 1 to 4 Interrupts An interrupt is generated by an overflow of timers 1 to 4. Table 8.3.1 Interrupt Vector Addresses and Priority Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Interrupt Source Reset OSD interrupt INT2 external interrupt INT1 external interrupt SPRITE OSD interrupt Timer 4 interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt Serial I/O interrupt Multi-master I2C-BUS interface interrupt INT3 external interrupt A-D conversion interrupt BRK instruction interrupt Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF716, FFF616 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFE316, FFE216 FFDF16, FFDE16 Remarks Non-maskable Active edge selectable Active edge selectable Active edge selectable Non-maskable Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 19 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (4) Serial I/O Interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(XIN)/4096 Interrupt The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of the PWM mode register 1 to “0.” Interrupt request bit Interrupt enable bit (6) Multi-master I2C-BUS Interface Interrupt This is an interrupt request related to the multi-master I2C-BUS interface. Interrupt disable flag I BRK instruction Reset Interrupt request (7) A-D Conversion Interrupt The A-D conversion interrupt occurs at the completion of A-D conversion. (8) BRK Instruction Interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable). Fig. 8.3.1 Interrupt Control Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 20 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Interrupt Request Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B Name 0 Timer 1 interrupt request bit (TM1R) 1 2 3 4 5 6 7 Functions After reset 0 0 : No interrupt request issued 1 : Interrupt request issued 0 Timer 2 interrupt 0 : No interrupt request issued request bit (TM2R) 1 : Interrupt request issued 0 Timer 3 interrupt 0 : No interrupt request issued request bit (TM3R) 1 : Interrupt request issued 0 Timer 4 interrupt 0 : No interrupt request issued request bit (TM4R) 1 : Interrupt request issued OSD interrupt request 0 : No interrupt request issued 0 1 : Interrupt request issued bit (OSDR) VSYNC interrupt 0 0 : No interrupt request issued request bit (VSCR) 1 : Interrupt request issued 0 Multi-master I2C-BUS interface 0 : No interrupt request issued interrupt request bit (IICR) 1 : Interrupt request issued INT3 external interrupt 0 : No interrupt request issued 0 request bit (IT3R) 1 : Interrupt request issued RW R✽ R✽ R✽ R✽ R✽ R✽ R✽ R✽ ✽: “0” can be set by software, but “1” cannot be set. Fig. 8.3.2 Interrupt Request Register 1 Interrupt Request Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B Name Functions After reset 0 INT1 external interrupt 0 : No interrupt request issued 0 1 : Interrupt request issued request bit (IT1R) 0 1 INT2 external interrupt 0 : No interrupt request issued 1 : Interrupt request issued request bit (IT2R) 2 Serial I/O interrupt 0 0 : No interrupt request issued request bit (S1R) 1 : Interrupt request issued 0 3 SPRITE OSD interrupt 0 : No interrupt request issued request bit (SPR) 1 : Interrupt request issued 0 4 f(XIN)/4096 interrupt 0 : No interrupt request issued request bit (MSR) 1 : Interrupt request issued 5 Nothing is assigned. This bit is a write disable bit. 0 When this bit is read out, the value is “0.” 0 6 A-D conversion interrupt 0 : No interrupt request issued request bit (ADR) 1 : Interrupt request issued 7 Fix this bit to “0.” 0 RW R✽ R✽ R✽ R✽ R✽ R— R✽ RW ✽: “0” can be set by software, but “1” cannot be set. Fig. 8.3.3 Interrupt Request Register 2 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 21 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Interrupt Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW 0 Timer 1 interrupt enable bit (TM1E) 1 Timer 2 interrupt enable bit (TM2E) 2 Timer 3 interrupt enable bit (TM3E) 3 Timer 4 interrupt enable bit (TM4E) 4 OSD interrupt enable bit (OSDE) 5 VSYNC interrupt enable bit (VSCE) 6 Multi-master I2C-BUS interface interrupt enable bit (IICE) 7 INT3 external interrupt enable bit (IT3E) Fig. 8.3.4 Interrupt Control Register 1 Interrupt Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2) [Address 00FF16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW R— 0 INT1 external interrupt enable bit (IT1E) 1 INT2 external interrupt enable bit (IT2E) 2 Serial I/O interrupt enable bit (S1E) 3 SPRITE OSD interrupt enable bit (SPE) 4 f(XIN)/4096 interrupt enable bit (MSE) 5 Fix this bit to “0.” 6 A-D conversion interrupt 0 : Interrupt disabled enable bit (ADE) 1 : Interrupt enabled Nothing is assigned. This bit is a write disable 7 bit. When this bit is read out, the value is “0.” Fig. 8.3.5 Interrupt Control Register 2 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 22 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Interrupt Input Polarity Register b7 b6 b5 b4 b3 b2 b1 b0 00 0 Interrupt input polarity register (IP) [Address 00CD16] b Name Function Function b1 b0 0 0 The clock for OSD is supplied by connecting RC or LC across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode. 0 1 Since the main clock is used as the clock for OSD, the oscillation frequency is limited. Because of this, the character size in width (horizonal) direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P33 and P34 respectively. 0 After reset R W 0 RW 0, 1 OSD clock selection bits (OCG0, OCG1) OSD oscillation frequency = f(XIN) 1 The clock for OSD is supplied by connecting LC across the pins OSC1 and OSC2. In the bi-scan mode, be sure to set this. The clock for OSD is supplied by connecting the following across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode. • a ceramic resonator only for OSD and a feedback resistor • a quartz-crystal oscillator only for OSD and a feedback resistor 0 0 0 0 0 RW RW RW RW RW 1 1 2 3 4 5 Fix this bit to “0.” INT1 polarity switch bit (POL1) INT2 polarity switch bit (POL2) INT3 polarity switch bit (POL3) 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 6, 7 Fix these bits to “0.” Fig. 8.3.6 Interrupt Input Polarity Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 23 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.4 TIMERS This microcomputer has 4 timers: timers 1 to 4. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8.4.3. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to “1” by a timer overflow at the next count pulse, after the count value reaches “0016.” At reset, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. The f(XIN)/16 is selected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and “FF16” is automatically set in timer 3; “0716” in timer 4. However, the f(XIN)/16 is not selected as the timer 3 count source. So set both bit 0 of timer mode register 2 (address 00F516) and bit 6 at address 00C716 to “0” before execution of the STP instruction (f(XIN)/16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected. As a result of the above procedure, the program can start under a stable clock. However, when setting “1” to bit 5 of timer mode register 1 (address 00F416), timers 3 and 4 are not set the above value, the STP state is set by executing the STP instruction. This allows to program the time to return from the STP state. The timer-related registers is shown in Figures 8.4.1 and 8.4.2. 8.4.1 Timer 1 Timer 1 can select one of the following count sources: • f(XIN)/16 • f(XIN)/4096 or f(XCIN)/4096 The count source of timer 1 is selected by setting bit 0 of timer mode register 1 (address 00F416). Timer 1 interrupt request occurs at timer 1 overflow. 8.4.2 Timer 2 Timer 2 can select one of the following count sources: • f(XIN)/16 • Timer 1 overflow signal • External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer mode register 1 (address 00F416). When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8-bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow. 8.4.3 Timer 3 Timer 3 can select one of the following count sources: • f(XIN)/16 • External clock from the HSYNC pin • External clock from the TIM3 pin The count source of timer 3 is selected by setting bits 5 and 0 of timer mode register 2 (address 00F516). Timer 3 interrupt request occurs at timer 3 overflow. 8.4.4 Timer 4 Timer 4 can select one of the following count sources: • f(XIN)/16 • f(XIN)/2 • Timer 3 overflow signal The count source of timer 3 is selected by setting bits 1 and 4 of timer mode register 2 (address 00F516). When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8-bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 24 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Timer Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TM1) [Address 00F416] B 0 1 Name Timer 1 count source selection bit 1 (TM10) Timer 2 count source selection bit 1 (TM11) Functions 0: f(XIN)/16 1: f(XIN)/4096 0: Interrupt clock source 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop After reset R W 0 0 0 0 0 0 RW RW RW RW RW RW 2 Timer 1 count stop bit (TM12) 3 Timer 2 count stop bit (TM13) 4 Timer 2 internal count source 0: f(XIN)/16 1: Timer 1 overflow selection bit 2 (TM14) 5 Timers 3 and 4 auto set disable bit (TM15) 0: Auto set enabled 1: Auto set disabled 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 R— Fig. 8.4.1 Timer Mode Register 1 Timer Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TM2) [Address 00F516] B Name 0 Timer 3 count source selection bit (TM20) 1 Timer 4 internal interrupt count source selection bit (TM21) Functions 0 : f(XIN)/16 1 : External clock source 0 : Timer 3 overflow signal 1 : f(XIN)/16 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Internal clock source 1: f(XIN)/2 After reset R W 0 RW 0 RW 2 Timer 3 count stop bit (TM22) 3 Timer 4 count stop bit (TM23) 4 Timer 4 count source selection bit (TM24) 5 0 0 0 0 0 RW RW RW RW R— Timer 3 external count 0: TIM3 pin input source selection bit (TM25) 1: HSYNC pin input 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Fig. 8.4.2 Timer Mode Register 2 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 25 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Data bus 8 1/4096 Timer 1 latch (8) 8 XIN 1 /2 1/8 TM10 TM12 Timer 1 (8) 8 TM14 8 Timer 1 interrupt request Timer 2 latch (8) 8 TIM2 TM11 TM13 8 8 FF16 TIM3 TM25 Timer 3 latch (8) 8 Timer 3 (8) TM20 TM22 8 8 0716 Timer 4 latch (8) 8 Timer 4 (8) TM24 TM23 8 Timer 4 interrupt request Timer 3 interrupt request STP instruction TM15 Timer 2 (8) Timer 2 interrupt request HSYNC Reset Selection gate : Connected to black side at reset TM21 TM1 : Timer mode register 1 TM2 : Timer mode register 2 Notes 1: HIGH pulse width of timer external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 1, 2, and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used. Fig. 8.4.3 Timer Block Diagram Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 26 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.5 SERIAL I/O This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8.5.1. The synchronous clock I/O pin (SCLK), and data output pin (SOUT) also function as port P4, data input pin (SIN) also functions as port P2. Bit 3 of the serial I/O mode register (address 00DC16) selects whether the synchronous clock is supplied internally or externally (from the SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 4, 16, 32, or 64. To use SIN pin for serial I/O, set the corresponding bit of the port P2 direction register (address 00C516) to “0.” The operation of the serial I/O is described below. The operation of the serial I/O differs depending on the clock source; external clock or internal clock. Data bus XIN 1/2 1/2 Frequency divider 1/4 1/16 1/32 1/64 Synchronous circuit P20 latch SCLK SM3 P21 latch SOUT SM3 SIN SM6 SM5 : LSB SM2 S SM1 SM0 Selection gate : Connected to black side at reset SM : Serial I/O mode register Serial I/O counter (8) Serial I/O interrupt request MSB (See note) Serial I/O shift register (8) 8 (Address 00DD16) Note : When the data is set in the serial I/O register (address 00DD16), the register functions as the serial I/O shift register. Fig. 8.5.1 Serial I/O Block Diagram Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 27 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Internal clock : The serial I/O counter is set to “7” during the write cycle into the serial I/O register (address 00DD16), and the transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes “0” and the transfer clock stops at HIGH. At this time the interrupt request bit is set to “1.” External clock : The an external clock is selected as the clock source, the interrupt request is set to “1” after the transfer clock has been counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 1 MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 8.5.2. When using an external clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching. Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions, such as SEB and CLB. 2: When an external clock is used as the synchronous clock, write transmit data to the serial I/O register when the transfer clock input level is HIGH. Synchronous clock Transfer clock Serial I/O register write signal (Note) Serial I/O output SOUT Serial I/O input SIN D0 D1 D2 D3 D4 D5 D6 D7 Interrupt request bit is set to “1” Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed. Fig. 8.5.2 Serial I/O Timing (for LSB first) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 28 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Serial I/O Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 Serial I/O mode register (SM) [Address 00DC16] B Name Functions b1 b0 0 0: f(XIN)/4 0 1: f(XIN)/16 1 0: f(XIN)/32 1 1: f(XIN)/64 0: External clock 1: Internal clock 0: P20, P21 1: SCLK, SOUT After reset R W 0 RW 0, 1 Internal synchronous clock selection bits (SM0, SM1) 2 3 Synchronous clock selection bit (SM2) Serial I/O port selection bit (SM3) 0 0 RW RW 4 Fix this bit to “0.” 5 6 7 Transfer direction selection bit (SM5) Serial input pin selection bit (SM6) 0: LSB first 1: MSB first 0: Input signal from SIN pin. 1: Input signal from SOUT pin. 0 0 0 0 RW RW RW R— Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Fig. 8.5.3 Serial I/O Mode Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 29 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.5.1 Serial I/O Common Transmission/Reception mode By writing “1” to bit 6 of the serial I/O mode register, signals SIN and SOUT are switched internally to be able to transmit or receive the serial data. Figure 8.5.4 shows signals on serial I/O common transmission/reception mode. Note: When receiving the serial data after writing “FF16” to the serial I/O register. SCLK Clock SOUT “1” Serial I/O shift register (8) SIN “0” SM6 SM : Serial I/O mode register Fig. 8.5.4 Signals on Serial I/O Common Transmission/Reception Mode Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 30 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.6 MULTI-MASTER I2C-BUS INTERFACE The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 8.6.1 shows a block diagram of the multi-master I2C-BUS interface and Table 8.6.1 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits. Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at φ = 4 MHz) Format Communication mode SCL clock frequency φ : System clock = f(XIN)/2 Note : We are not responsible for any third party’s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00DA16) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2). b7 I2C address register (S0D) b0 Interrupt generating circuit Interrupt request signal (IICIRQ) SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW Address comparator Serial data (SDA) Noise elimination circuit Data control circuit b7 I C data shift register S0 2 b0 b7 MST TRX BB PIN b0 AL AAS AD0 LRB AL circuit Internal data bus I C status register (S1) 2 BB circuit Serial clock (SCL) Noise elimination circuit Clock control circuit b7 ACK b0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE BIT b7 BSEL1 BSEL0 10BIT SAD ALS b0 ESO BC2 BC1 BC0 I2C clock control register (S2) Clock division I2C control register (S1D) System clock (φ) Bit counter Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 31 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.6.1 I2C Data Shift Register The I2C data shift register (S0 : address 00D716) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00DA16) is “1.” The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00D916) are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value. Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. I2C Address Register b7 b6 b5 b4 b3 b2 b1 b0 I2C address register (S0D) [Address 00D816] B 0 Name Read/write bit (RBW) Functions The last significant bit of address data is compared. 0: Wait the first byte of slave address after START condition (read state) 1: Wait the first byte of slave address after RESTART condition (write state) The address data is compared. After reset R W 0 R— 1 to 7 Slave address (SAD0 to SAD6) 0 RW Fig. 8.6.2 Data Shift Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 32 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.6.2 I2C Address Register The I2C address register (address 00D816) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected. (1) Bit 0: read/write bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to “0” automatically when the stop condition is detected. (2) Bits 1 to 7: slave address (SAD0–SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. I2C Address Register b7 b6 b5 b4 b3 b2 b1 b0 I2C address register (S0D) [Address 00D816] B 0 Name Read/write bit (RBW) Functions The last significant bit of address data is compared. 0: Wait the first byte of slave address after START condition (read state) 1: Wait the first byte of slave address after RESTART condition (write state) The address data is compared. After reset R W 0 R— 1 to 7 Slave address (SAD0 to SAD6) 0 RW Fig. 8.6.3 I2C Address Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 33 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.6.3 I2C Clock Control Register The I2C clock control register (address 00DB16) is used to set ACK control, SCL mode and SCL frequency. (4) Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally. (1) Bits 0 to 4: SCL frequency control bits (CCR0–CCR4) These bits control the SCL frequency. (2) Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When the bit is set to “1,” the high-speed clock mode is set. (3) Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock✽ is generated. When this bit is set to “0,” the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). ✽ACK clock: Clock for acknowledgement I2C Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2) [Address 00DB16] B 0 to 4 Name Functions After reset R W 0 SCL frequency control bits Setup value of Standard clock High speed (CCR0 to CCR4) CCR4–CCR0 mode clock mode 00 to 02 03 04 05 06 1D 1E 1F ... RW Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3 17.2 16.6 16.1 333 250 400 (See note) 166 34.5 33.3 32.3 500/CCR value 1000/CCR value (at φ = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock 0 RW RW RW 6 7 0 0 Note: At 400 kHz in the high-speed clock mode, the duty is as below . “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 Fig. 8.6.4 I2C Address Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 34 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.6.4 I2C Control Register The I2C control register (address 00DA16) controls the data communication format. (3) Bit 4: data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to “8.6.5 I2C Status Register,” bit 1) is received, transmission processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses are not recognized. (1) Bits 0 to 2: bit counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become “0002” and the address data is always transmitted and received in 8 bits. (2) Bit 3: I2C interface use enable bit (ESO) This bit enables usage of the multimaster I2C BUS interface. When this bit is set to “0,” the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is enabled. When ESO = “0,” the following is performed. • PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C status register at address 00D916 ). • Writing data to the I2C data shift register (address 00D716) is disabled. (4) Bit 5: addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 00D816) are compared with address data. When this bit is set to “1,” the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data. (5) Bits 6 and 7: connection control bits between I 2 C-BUS interface and ports (BSEL0, BSEL1) These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 8.6.5). “0” “1” BSEL0 P11/SCL1 SCL Multi-master I2C-BUS interface SDA “0” “1” BSEL1 P12/SCL2 “0” “1” BSEL0 P13/SDA1 “0” “1” BSEL1 P14/SDA2 Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 35 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP I2C Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D) [Address 00DA16] B 0 to 2 Name Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0: 8 1: 7 0: 6 1: 5 0: 4 1: 3 0: 2 1: 1 After reset R W 0 RW 3 4 5 I2C-BUS interface use enable bit (ESO) Data format selection bit(ALS) Addressing format selection bit (10BIT SAD) 0: Disabled 1: Enabled 0: Addressing format 1: Free data format 0: 7-bit addressing format 1: 10-bit addressing format b7 b6 Connection port (See note) 0 0: None 0 1: SCL1, SDA1 1 0: SCL2, SDA2 1 1: SCL1, SDA1, SCL2, SDA2 0 0 0 0 RW RW RW RW 6, 7 Connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1) Note: When using ports P11-P14 as I2C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output. Fig. 8.6.6 I2C Control Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 36 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.6.5 I2C Status Register The I2C status register (address 00D916) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to. (5) Bit 4: I2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to “0” in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the PIN bit. When detecting the STOP condition in slave, the multi-master I2C-BUS interface interrupt request bit (IR) is set to “0” (interrupt request) regardless of falling of PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is disabled. Figure 8.6.8 shows an interrupt request signal generating timing chart. The PIN bit is set to “1” in any one of the following conditions. • Writing “1” to the PIN bit • Executing a write instruction to the I2C data shift register (address 00D716). • When the ESO bit is “0” • At reset Note: It takes 8 BCLK cycles or more until PIN bit become “1” after write instructions are executed to these registers. (1) Bit 0: last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00D716). (2) Bit 1: general call detecting flag (AD0) This bit is set to “1” when a general call✽ whose address data is all “0” is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to “0” by detecting the STOP condition or START condition. ✽General call: The master transmits the general call address “0016” to all slaves. (3) Bit 2: slave address comparison flag (AAS) This flag indicates a comparison result of address data. s In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following conditions. • The address data immediately after occurrence of a START condition matches the slave address stored in the high-order 7 bits of the I2C address register (address 00D816). • A general call is received. s In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following condition. • When the address data is compared with the I2C address register (8 bits consists of slave address and RBW), the first bytes match. s The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register (address 00D716). The conditions in which the PIN bit is set to “0” are shown below: • Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) • Immediately after completion of 1-byte data reception • In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call address reception • In the slave reception mode, with ALS = “1” and immediately after completion of address data reception (6) Bit 5: bus busy flag (BB) This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (See note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to “1” by detecting a START condition and set to “0” by detecting a STOP condition. When the ESO bit of the I2C control register (address 00DA 16) is “0” and at reset, the BB flag is kept in the “0” state. (4) Bit 3: arbitration lost✽ detecting flag (AL) n the master transmission mode, when a device other than the microcomputer sets the SDA to “L,”, arbitration is judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.” When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. ✽Arbitration lost: The status in which communication as a master is disabled. (7) Bit 6: communication mode specification bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is “0,” the reception mode is selected and the data of a transmitting device is received. When the bit is “1,” the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2C control register (address 00DA16) is “0” in the slave reception mode is selected, the TRX bit is set to “1” ___ (transmit) if the least significant bit (R/W bit) of the address data trans___ mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive). The TRX bit is cleared to “0” in one of the following conditions. • When arbitration lost is detected. • When a STOP condition is detected. • When occurence of a START condition is disabled by the START condition duplication prevention function (Note). • With MST = “0” and when a START condition is detected. • With MST = “0” and when ACK non-return is detected. • At reset Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 37 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (8) Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “1,” the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to “0” in one of the following conditions. • Immediately after completion of 1-byte data transmission when arbitration lost is detected • When a STOP condition is detected. • When occurence of a START condition is disabled by the START condition duplication preventing function (Note). • At reset Note: The START condition duplication prevention function disables the START condition generation, reset of bit counter reset, and SCL output, when the following condition is satisfied: a START condition is set by another master device. I2C Status Register b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1) [Address 00D916] B 0 1 2 3 4 5 Name Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB) Functions 0 : Last bit = “0 ” 1 : Last bit = “1 ” (See note) After reset R W Indeterminate 0 0 R— R— R— R— RW RW RW 0 : No general call detected 1 : General call detected (See note) 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected (See note) 0 1 0 0 (See note) 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode 6, 7 Communication mode specification bits (TRX, MST) Note : These bits and flags can be read out, but cannnot be written. Fig. 8.6.7 I2C Status Register SCL PIN IICIRQ Fig. 8.6.8 Interrupt Request Signal Generation Timing Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 38 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.6.6 START Condition Generation Method When the ESO bit of the I2C control register (address 00DA16) is “1,” execute a write instruction to the I2C status register (address 00D916) to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit counter becomes “0002” and an SCL for 1 byte is output. The START condition generation timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 8.6.9 for the START condition generation timing diagram, and Table 8.6.2 for the START condition/ STOP condition generation timing table. I2C status register write signal SCL SDA BB flag Setup time Setup time Hold time Set time for BB flag Fig. 8.6.9 START Condition Generation Timing Diagram 8.6.7 STOP Condition Generation Method When the ESO bit of the I2C control register (address 00DA16) is “1,” execute a write instruction to the I2C status register (address 00D916) for setting the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be generated. The STOP condition generation timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 8.6.10 for the STOP condition generation timing diagram, and Table 8.6.2 for the START condition/STOP condition generation timing table. I2C status register write signal SCL SDA BB flag Setup time Hold time Reset time for BB flag Fig. 8.6.10 STOP Condition Generation Timing Diagram Table 8.6.2 START Condition/STOP Condition Generation Timing Table Item Standard Clock Mode Setup time 5.0 µs (20 cycles) (START condition) Setup time 4.25 µs (17 cycles) (STOP condition) 5.0 µs (20 cycles) Hold time Set/reset time 3.0 µs (12 cycles) for BB flag High-speed Clock Mode 2.5 µs (10 cycles) 1.75 µs (7 cycles) 2.5 µs (10 cycles) 1.5 µs (6 cycles) Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 39 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.6.8 START/STOP Condition Detect Conditions The START/STOP condition detect conditions are shown in Figure 8.6.11 and Table 8.6.3. Only when the 3 conditions of Table 8.6.3 are satisfied, a START/STOP condition can be detected. Note: W hen a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “IICIRQ” is generated to the CPU. 8.6.9 Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below. (1) 7-bit addressing format To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DA16) to “0.” The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 00D816). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00D816) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 8.6.12, (1) and (2). SCL release time SCL SDA (START condition) SDA (STOP condition) Setup time Setup time Hold time (2) 10-bit addressing format Hold time To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DA16) to “1.” An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00D816). At the time of this comparison, an address comparison between the RBW bit of the I2C address register (address 00D816) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00D916) is set to “1.” After the second-byte address data is stored into the I2C data shift register (address 00D716), make an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I2C address register (address 00D816) to “1” by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00D816). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 8.6.12, (3) and (4). Fig. 8.6.11 START Condition/STOP Condition Detect Timing Diagram Table 8.6.3 START Condition/STOP Condition Detect Conditions Standard Clock Mode 6.5 µs (26 cycles) < SCL release time 3.25 µs (13 cycles) < Setup time 3.25 µs (13 cycles) < Hold time High-speed Clock Mode 1.0 µs (4 cycles) < SCL release time 0.5 µs (2 cycles) < Setup time 0.5 µs (2 cycles) < Hold time Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the number of φ cycles. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 40 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.6.10 Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. ➀ Set a slave address in the high-order 7 bits of the I2C address register (address 00D816) and “0” in the RBW bit. ➁ Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register (address 00DB16). ➂ Set “1016” in the I2C status register (address 00D916) and hold the SCL at the HIGH. ➃ Set a communication enable status by setting “4816” in the I2C control register (address 00DA16). ➄ Set the address data of the destination of transmission in the highorder 7 bits of the I2C data shift register (address 00D716) and set “0” in the least significant bit. ➅ Set “F016” in the I2C status register (address 00D916) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. ➆ Set transmit data in the I2C data shift register (address 00D716). At this time, an SCL and an ACK clock automatically occurs. ➇ When transmitting control data of more than 1 byte, repeat step ➆. ➈ Set “D016” in the I2C status register (address 00D916). After this, if ACK is not returned or transmission ends, a STOP condition will be generated. 8.6.11 Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode, using the addressing format, is shown below. ➀ Set a slave address in the high-order 7 bits of the I 2C address register (address 00D816) and “0” in the RBW bit. ➁ Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register (address 00DB16). ➂ Set “1016” in the I2C status register (address 00D916) and hold the SCL at the HIGH. ➃ Set a communication enable status by setting “4816” in the I2C control register (address 00DA16). ➄ When a START condition is received, an address comparison is made. ➅ •When all transmitted address are“0” (general call): AD0 of the I2C status register (address 00D916) is set to “1”and an interrupt request signal occurs. •When the transmitted addresses match the address set in ➀: ASS of the I2C status register (address 00D916) is set to “1” and an interrupt request signal occurs. •In the cases other than the above: AD0 and AAS of the I2C status register (address 00D916) are set to “0” and no interrupt request signal occurs. ➆ Set dummy data in the I2C data shift register (address 00D716). ➇ When receiving control data of more than 1 byte, repeat step ➆. ➈ When a STOP condition is detected, the communication ends. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 41 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP S Slave address R/W A Data A Data A/A P 7 bits “0” 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver S Slave address R/W A Data A Data A P 7 bits “1” 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address R/W 1st 7 bits Slave address 2nd byte S A A Data A Data A/A P 7 bits “0” 8 bits 1 to 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address R/W 1st 7 bits Slave address 2nd byte Slave address R/W 1st 7 bits S A A Sr Data A Data 1 to 8 bits A P 7 bits “0” 8 bits 7 bits “1” 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit From master to slave From slave to master Fig. 8.6.12 Address Data Communication Format 8.6.12 Precautions when using multi-master I2C-BUS interface (1) Read-modify-write instruction The precautions when the raead-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I2C-BUS interface are described below. •I2C data shift register (S0) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. •I2C address register (S0D) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not ______ intended. It is because hardware changes the read/write bit (RBW) at the above timing. •I2C status register (S1) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. •I2C control register (S1D) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because hardware changes the bit counter (BC0–BC2) at the above timing. •I2C clock control register (S2) The read-modify-write instruction can be executed for this register. (2) START condition generating procedure using multi-master ➀Procedure example (The necessary conditions of the generating procedure are described as the following ➁ to ➄). • • — LDA SEI BBS 5,S1,BUSBUSY BUSFREE: STA S0 LDM #$F0, S1 CLI • • BUSBUSY: CLI • • (Taking out of slave address value) (Interrupt disabled) (BB flag confirming and branch process) (Writing of slave address value) (Trigger of START condition generating) (Interrupt enabled) (Interrupt enabled) ➁Use “STA,” “STX” or “STY” of the zero page addressing instruction for writing the slave address value to the I2C data shift register. ➂Use “LDM” instruction for setting trigger of START condition generating. ➃Write the slave address value of above ➁ and set trigger of START condition generating of above ➂ continuously shown the above procedure example. ➄Disable interrupts during the following three process steps: • BB flag confirming • Writing of slave address value • Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 42 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (3) RESTART condition generating procedure ➀Procedure example (The necessary conditions of the generating procedure are described as the following ➁ to ➅.) Execute the following procedure when the PIN bit is “0.” • • #$00, S1 — S0 #$F0, S1 • • ➁Select the slave receive mode when the PIN bit is “0.” Do not write “1” to the PIN bit. Neither “0” nor “1” is specified for the writing to the BB bit. The TRX bit becomes “0” and the SDA pin is released. ➂The SCL pin is released by writing the slave address value to the I2C data shift register. Use “STA,” “STX” or “STY” of the zero page addressing instruction for writing. ➃Use “LDM” instruction for setting trigger of RESTART condition generating. ➄Write the slave address value of above ➂ and set trigger of RESTART condition generating of above ➃ continuously shown the above procedure example. ➅Disable interrupts during the following two process steps: • Writing of slave address value • Trigger of RESTART condition generating (4) STOP condition generating procedure ➀Procedure example (The necessary conditions of the generating procedure are described as the following ➁ to ➃.) • • LDM LDA SEI STA LDM CLI (Select slave receive mode) (Taking out of slave address value) (Interrupt disabled) (Writing of slave address value) (Trigger of RESTART condition generating) (Interrupt enabled) SEI LDM #$C0, S1 NOP LDM #$D0, S1 CLI • • (Interrupt disabled) (Select master transmit mode) (Set NOP) (Trigger of STOP condition generating) (Interrupt enabled) ➁Write “0” to the PIN bit when master transmit mode is select. ➂Execute “NOP” instruction after setting of master transmit mode. Also, set trigger of STOP condition generating within 10 cycles after selecting of master trasmit mode. ➃Disable interrupts during the following two process steps: • Select of master transmit mode • Trigger of STOP condition generating (5) Writing to I2C status register Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1.” It is because it may become the same as above. (6) Process of after STOP condition generating Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes “0” after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers do not have the problem. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 43 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.7 PWM OUTPUT FUNCTION This microcomputer is equipped with two 14-bit PWMs (DA1, DA2) and six 8-bit PWMs (PWM0–PWM5). DA1 and DA2 have a 14-bit resolution with the minimum resolution bit width of 0.25 µs and a repeat period of 4096 µs (for f(XIN) = 8 MHz). PWM0–PWM5 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 µs and repeat period of 1024 µs (for f(XIN) = 8 MHz). Figure 8.7.1 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to DA1, DA2 and PWM0–PWM5 using f(XIN) divided by 2 as a reference signal. shown in Figure 8.7.2 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of entirely HIGH output cannot be output, i.e. 256/256. 8.7.4 Operating of 14-bit PWM For DA1, as with 8-bit PWM, set the bit 0 of PWM output control register 1 (address 00D516) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. Next, select the output polarity by bit 2 of PWM output control register 2 (address 00D616). Then, the 14-bit PWM outputs from the DA1 output pin by setting bit 1 of PWM output control register 1 to “0” (at reset, this bit already set to “0” automatically) to select the DA1 output. For DA2 as with DA1, set the bit 0 of PWM output control register 1 (address 00D516) to “0” (at reset, bit 0 is already set to “0” automatically), so that PWM count source is supplied. Next, select the output polarity by bit 4 of PWM output control register 2 (address 00D616). Then, the 14-bit PWM outputs from the DA2 output pin by setting bit 5 of PWM output control register 1 to “0” (at reset, this bit already set to “0” automatically) to select the DA2 output. The output example of the 14-bit PWM is shown in Figure 8.7.3. The 14-bit PWM divides the data of the DAi latch (i = 1, 2) into the low-order 6 bits and the high-order 8 bits. The fundamental waveform is determined with the high-order 8-bit data “DH.” A HIGH area with a length t ✕ DH (HIGH area of fundamental waveform) is output every short area of “t” = 256 τ = 64 µs (τ is the minimum resolution bit width of 250 ns). The HIGH level area increase interval (tm) is determined with the low-order 6-bit data “DL.” The HIGH are of smaller intervals “tm” shown in Table 5 is longer by t than that of other smaller intervals in PWM repeat period “T” = 64t. Thus, a rectangular waveform with the different HIGH width is output from the DAi pins (i = 1, 2). Accordingly, the PWM output changes by τ unit pulse width by changing the contents of the DAi-H and DAi-L registers (i = 1, 2). A length of entirely HIGH cannot be output, i. e. 256/256. 8.7.1 Data Setting When outputting DA1, first set the high-order 8 bits to the DA1-H register (address 00CE16), then the low-order 6 bits to the DA1-L register (address 00CF16). When outputting DA1, first set the highorder 8 bits to the DA2-H register (address 024E16), then the loworder 6 bits to the DA2-L register (address 024F16). When outputting PWM0–PWM5, set 8-bit output data to the PWMi register (i means 0 to 5; addresses 00D016 to 00D416, 00F616). 8.7.2 Transferring Data from Registers to PWM Circuit Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is executed at writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register. Also, data transfer from the DA1 register (addresses 00CE16 and 00CF16) to the 14-bit PWM circuit is executed at writing data to the DA1-L register (address 00CF16). Reading from the DA1-H register (address 00CE16) means reading this transferred data. Data transfer from the DA2 register (addresses 024E16 and 024F16) to the 14bit PWM circuit is executed at writing data to the DA2-L register (address 024F16). Reading from the DA2-H register (address 024E16) means reading this transferred data. Accordingly, it is possible to confirm the data being output from the DAi (i = 1, 2) output pin by reading the DAi (i = 1, 2) register. 8.7.5 Output after Reset At reset, the output of ports P00–P05 and P17 are in the high-impedance state, and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register. Table 8.7.1 Relation Between the Low-order 6-bit Data and Highlevel Area Increase Interval Low-order 6 bits of Data Area Longer by τ than That of Other tm (m = 0 to 63) LSB 8.7.3 Operating of 8-bit PWM The following explains PWM operation. First, set the bit 0 of PWM output control register 1 (address 00D516) to “0” (at reset, bit 0 is already set to “0” automatically), so that the PWM count source is supplied. PWM0–PWM5 are also used as pins P00–P05, respectively. For PWM0–PWM5, set the corresponding bits of the ports P0 direction register to “1” (output mode). And select each output polarity by bit 3 of PWM output control register 2 (address 00D616). Then, set bits 2 to 7 of PWM output control register 1 to “1” (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 8.7.2 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (28) segments. The 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. Refer to Figure 8.7.2 (a). The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are 000000 000001 000010 000100 001000 010000 100000 Nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7, ................................. 57, 59, 61, 63 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 44 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Data bus DA1-H register (Address 00CE16) b7 DA1 latch (14 bits) MSB 8 6 6 14 LS B b0 DA1-L register (See note) (Address 00CF16) PN2 14-bit PWM circuit P35 DA1 PW1 DA2-H register (Address 024E16 ) b7 DA2 latch (14 bits) MSB 8 6 6 14 LS B b0 DA2-L register (See note) (Address 024F16) PN4 14-bit PWM circuit PWM timing generating circuit P17 DA2 PW1 XIN 1/2 PW0 PWM register (Address 00D0 16) b7 8 b0 PN3 8-bit PWM circuit P00 PW2 P01 PW3 P02 D00 PWM0 D01 PWM1 Selection gate: Connected to black side at reset. Pass gate Inside of with the others. is as same contents PWM1 register (Address 00D116) PWM2 register (Address 00D216) PWM3 register (Address 00D316) PWM4 register (Address 00D416) PWM5 register (Address 00F616) D02 PWM2 PW4 P03 PW5 P04 PW6 P05 PW7 D05 PWM5 D04 PWM4 D03 PWM3 PW : PWM mode register 1 [address 00D516] PN : PWM mode register 2 [address 00D616] D0 : Port P0 direction register [address 00C116] P0 : Port P0 register [address 00C016] P1 : Port P1 register [address 00C216] P3 : Port P3 register [address 00C416] Note: DAi-L register is also used as low-order 6 bits of DAi latch (i = 1, 2). Fig. 8.7.1 PWM Block Diagram Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 45 of 124 1 3579 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240 250 255 20 30 40 50 Bit 7 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 Fig. 8.7.2 PWM Timing 52 60 68 76 84 92 100 108 116 124 132 140 148 156 164 172 180 188 196 204 212 220 228 236 244 252 56 72 88 104 120 136 152 168 184 200 216 232 248 80 112 144 176 208 240 96 160 224 64 192 128 2 6 10 14 18 22 26 30 34 38 42 46 50 Bit 6 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z (a) Pulses showing the weight of each bit T = 256 t PWM output t = 4 µs T = 1024 µs f(XIN) = 8 MHz (b) Example of 8-bit PWM 4 12 20 28 36 44 Bit 5 8 24 40 Bit 4 16 48 Bit 3 M37225M6/M8/MA/MC-XXXSP, M37225ECSP page 46 of 124 32 Bit 2 Bit 1 Bit 0 0016 (0) 0116 (1) 1816 (24) FF16 (255) t M37225M6/M8/MA/MC-XXXSP, M37225ECSP Set “2C16” to DAi-H register. Set “2816” to DAi-L register. b7 b6 b5 b4 b3 b2 b1 b0 [DAi-H 0 0 1 0 1 1 0 0 DH register] At writing of DAi-L b13 [DAi latch] 0 0 1 0 1 1 0 b6 b5 0 1 0 1 b7 b6 b5 b4 b3 b2 b1 b0 [DAi-L register] 1 0 1 0 0 0 DL At writing of DAi-L b0 0 0 0 These bits decide HIGH level area of fundamental waveform. HIGH level area of fundamental waveform These bits decide smaller interval “tm” in which HIGH leval area is [HIGH level area of fundamental waveform + τ ]. = Minimum resolution bit width 0.25 µs ✕ High-order 8-bit value of DAi latch Fundamental waveform Waveform of smaller interval “tm” specified by low-order 6 bits 0.25 µs✕44 0.25 µs✕45 0.25 µs 14-bit 2C 2B 2A … 03 02 01 00 PWM output 8-bit counter FF FE FD … D6 D5 D4 D3 … 02 01 00 14-bit … 03 02 01 00 PWM output 2C 2B 2A 8-bit counter FF FE FD … D6 D5 D4 D3 … 02 01 00 Fundamental waveform of smaller interval “tm” which is not specified by low-order 6 bits is not changed. 0.25 µs✕44 τ = 0.25 µs 14-bit PWM output t0 Low-order 6-bit output of DAi latch Repeat period T = 4096 µs t1 t2 t3 t4 t5 t59 t60 t61 t62 t63 Note: i indicates 0 or 1. Fig. 8.7.3 14-bit PWM Timing (f(XIN) = 8 MHz) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 47 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP PWM Output Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 1 (PW) [Address 00D5 ] 16 B Name Functions 0 : Count source supply 0 DA1, DA2, PWM count source selection bit (PW0) 1 : Count source stop 0 : DA1 output 1 DA1 output/P35 1 : P35 output selection bit (PW1) 2 P00/PWM0 output selection bit (PW2) 3 P01/PWM1 output selection bit (PW3) 4 P02/PWM2 output selection bit (PW4) 5 P03/PWM3 output selection bit (PW5) 6 P04/PWM4 output selection bit (PW6) 7 P05/PWM5 output selection bit (PW7) 0: P00 output 1: PWM0 output 0: P01 output 1: PWM1 output 0: P02 output 1: PWM2 output 0: P03 output 1: PWM3 output 0: P04 output 1: PWM4 output 0: P05 output 1: PWM5 output After reset R W 0 RW 0 0 0 0 0 0 0 RW RW RW RW RW RW RW Fig. 8.7.4 PWM Output Control Register 1 PWM Output Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 00 00 PWM output control register 2 (PN) [Address 00D6 ] 16 B Name 0, 1 Fix these bits to “0.” 2 DA1 output polarity selection bit (PN3) 3 PWM output polarity selection bit (PN4) 4 DA2 output polarity selection bit (PN5) 5 P17/DA2 output selection bit (PN5) 6, 7 Fix these bits to “0.” Functions After reset R W 0 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Output LOW 1 : Output HIGH 0 : P17 1 : DA2 0 0 0 0 0 RW RW RW RW RW RW Fig. 8.7.5 PWM Output Control Register 2 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 48 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.8 A-D CONVERTER 8.8.1 A-D Conversion Register (AD) A-D conversion reigister is a read-only register that stores the result of an A-D conversion. This register should not be read during A-D conversion. 8.8.3 Comparison Voltage Generator (Resistor Ladder) The voltage generator divides the voltage between VSS and VCC by 256, and outputs the divided voltages to the comparator as the reference voltage Vref. 8.8.2 A-D Control Register (ADCON) The A-D control register controls A-D conversion. Bits 2 to 0 of this register select analog input pins. When these pins are not used as anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D conversion completion bit, A-D conversion is started by writing “0” to this bit. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the A-D conversion is completed. Bit 4 controls connection between the resistor ladder and VCC. When not using the A-D converter, the resistor ladder can be cut off from the internal VCC by setting this bit to “0,” accordingly providing lowpower dissipation. 8.8.4 Channel Selector The channel selector connects an analog input pin, selected by bits 2 to 0 of the A-D control register, to the comparator. 8.8.5 Comparator and Control Circuit The conversion result of the analog input voltage and the reference voltage “Vref” is stored in the A-D conversion register. The A-D conversion completion bit and A-D conversion interrupt request bit are set to “1” at the completion of A-D conversion. Data bus b7 A-D control register (address 00DF16) 3 b0 A-D control circuit A-D1 A-D2 A-D3 A-D4 A-D5 A-D6 A-D7 A-D8 VSS VCC Comparator A-D conversion register 8 (address 00DE16) A-D conversion interrupt request Channel selector Switch tree Resistor ladder Fig. 8.8.1 A-D Converter Block Diagram Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 49 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP A-D Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 A-D control register (ADCON) [Address 00DF16] B 0 to 2 Name Analog input pin selection bits (ADIN0 to ADIN2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0 : A-D1 1 : A-D2 0 : A-D3 1 : A-D4 0 : A-D5 1 : A-D6 0 : A-D7 1 : A-D8 After reset R W 0 RW 3 4 5 6 7 A-D conversion completion bit (ADSTR) VCC connection selection bit (ADVREF) Fix this bit to “0.” 0: Conversion in progress 1: Convertion completed 0: OFF 1 : ON 1 0 0 Indeterm inate 0 RW RW RW R— RW Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. Fix this bit to “0.” Fig. 8.8.2 A-D Control Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 50 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.8.6 Conversion Method ➀ Set the A-D conversion interrupt request bit to “0” (even when AD conversion is started, the A-D conversion interrupt reguest bit is not set to “0” automatically). ➁ When using A-D conversion interrupt, enable interrupts by setting A-D conversion interrupt enable bit to “1” and setting the interrupt disable flag to “0.” ➂ Set the VCC connection selection bit to “1” to connect VCC to the resistor ladder. ➃ Select analog input pins by the analog input selection bit of the A-D control register. ➄ Set the A-D conversion completion bit to “0.” This write operation starts the A-D conversion. Do not read the A-D conversion register during the A-D conversion. ➅ Verify the completion of the conversion by the state (“1”) of the A-D conversion completion bit, the state (“1”) of A-D conversion interrupt reguest bit, or the occurrence of an A-D conversion interrupt. ➆ Read the A-D conversion register to obtain the conversion results. Note : When the ladder resistor is disconnect from VCC, set the VCC connection selection bit to “0” between steps ➅ and ➆. 8.8.7 Internal Operation When the A-D conversion starts, the following operations are automatically performed. ➀ The A-D conversion register is set to “0016.” ➁ The most significant bit of the A-D conversion register becomes “1, ” and the comparison voltage “Vref” is input to the comparator. At this point, Vref is compared with the analog input voltage “VIN .” ➂ Bit 7 is determined by the comparison results as follows. When Vref < VIN : bit 7 holds “1” When Vref > VIN : bit 7 becomes “0” With the above operations, the analog value is converted into a digital value. The A-D conversion terminates in a maximum of 50 machine cycles (8.5 µs at f(XIN) = 8 MHz) after it starts, and the conversion result is stored in the A-D conversion register. An A-D conversion interrupt request occurs at the same time as A-D conversion completion, the A-D conversion interrupt request bit becomes “1.” The A-D conversion completion bit also becomes “1.” Table 8.8.1 Expression for Vref and VREF A-D conversion register contents “n” (decimal notation) 0 1 to 255 Note: VREF indicates the reference voltage (= Vcc). Vref (V) 0 VREF ✕ (n – 0.5) 256 Contents of A-D conversion register A-D conversion start Reference voltage (Vref) [V] 00000 000 0 VREF VREF – 2 512 VREF VREF VREF ± – 2 4 512 VREF VREF ± VREF ± VREF – 2 4 8 512 VREF ± VREF ± VREF ± ..... 2 4 8 ....... ± VREF – VREF 512 256 1st comparison start 2nd comparison start 3rd comparison start 10000000 11000000 12100000 12345671 8th comparison start A-D conversion completion (8th comparison completion) 12345678 Digital value corresponding to analog input voltage. m : Value determined by mth (m = 1 to 8) result Fig. 8.8.3 Changes in A-D Conversion Register and Comparison Voltage during A-D Conversion Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 51 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.8.8 Definition of A-D Conversion Accuracy The definition of A-D conversion accuracy is described below (refer to Figure 8.8.4). • EDifferential non-linearity error The deviation of the input voltage required to change output data by “1,” from the corresponding ideal A-D conversion characteristics between 0 and VREF. (Vn+1 – Vn) – 1LSB 1LSB (1) Relative Accuracy •Zero transition error (V0T) The deviation of the input voltage at which A-D conversion output data changes from “0” to “1,” from the corresponding ideal A-D conversion characteristics between 0 and VREF. V0T = (V0 – 1/2 ✕ VREF/256) 1LSB [LSB] Differential non-linearity error = [LSB] (2) Absolute Accuracy • EAbsolute accuracy error The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between 0 and VREF. Vn – 1LSBA ✕ (n + 1/2) Absolute accuracy error = 1LSBA [LSB] • Full-scale transition error (VFST) The deviation of the input voltage at which A-D conversion output data changes from “255” to “254,” from the corresponding ideal AD conversion characteristics between 0 and VREF. VFST = (VREF – 3/2 ✕ VREF/256) – V254 1LSB [LSB] Note: The analog input voltage “Vn” at which A-D conversion output data changes from “n” to “n + 1” (n ; 0 to 254) is as follows (refer to Figure 8.8.4) : • Non-linearity error The deviation of the actual A-D conversion characteristics, from the ideal A-D conversion characteristics between V0 and V254. Vn – (1LSB ✕ n + V0) 1LSB 1LSB with respect to relative accuracy = V254 – V0 254 VREF [V] Non-linearity error = [LSB] 1LSBA with respect to absolute accuracy = 256 [V] Output code 0916 0816 Absolute accuracy 0716 0616 0516 0416 0316 – 2LSB 0216 0116 0016 0 20 40 60 80 100 120 140 160 180 200 220 Analog input voltage (mV) Fig. 8.8.4 Definition of A-D Conversion Accuracy + 2LSB Ideal A-D conversion characteristics Limitless resolution A-D conversion characteristics Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 52 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.9 ROM CORRECTION FUNCTION This can correct program data in ROM. Up to 3 addresses can be corrected, a program for correction is stored in the ROM correction vector in RAM as the top address. The ROM correction vectors are 3 vectors. Vector 1 : address 02C016 Vector 2 : address 02E016 Vector 3 : address 030016 Set the address of the ROM data to be corrected into the ROM correction address register. When the value of the counter matches the ROM data address in the ROM correction vector as the top address, the main program branches to the correction program stored in the ROM memory for correction. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. The ROM correction function is controlled by the ROM correction enable register. Notes 1: S p e c i f y t h e f i r s t a d d r e s s ( o p c o d e a d d r e s s ) o f e a c h instruction as the ROM correction address. 2: Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program. 3: Do not set the same ROM correction address to vectors 1 to 3. ROM correction address 1 (high-order) 021716 ROM correction address 1 (low-order) 021816 ROM correction address 2 (high-order) 021916 ROM correction address 2 (low-order) 021A16 ROM correction address 3 (high-order) 021C16 ROM correction address 3 (low-order) 021D16 Fig. 8.9.1 ROM Correction Address Registers ROM Correction Enable Register b7 b6 b5 b4 b3 b2 b1 b0 00000 ROM correction enable register (RCR) [Address 021B16] B 0 1 2 3 to 7 Name Vector 1 enable bit (RCR0) Vector 2 enable bit (RCR1) Vector 3 enable bit (RCR2) Fix these bits to “0.” Functions 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled After reset R W 0 0 0 RW RW RW RW 0 Fig. 8.9.2 ROM Correction Enable Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 53 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.10 OSD FUNCTIONS This OSD function can display the following 3 types: • “Block display ” (24 characters ✕ 2 lines) • “SPRITE display” (display only a character) or “Raster patterning display” (display a character on entire screen side by side) • “Raster flat display” (coloring entire screen) The above displays can be overlapped at the same time. The priority is : SPRITE display > Block display > Raster flat display or Block display > Raster patterning display > Raster flat display Note that raster patterning display and SPRITE display cannot be used simultaneously. Figure 8.10.2 shows the block diagram of OSD circuit, Figure 8.10.3 shows the configuration of OSD character display area, Figure 8.10.4 shows the OSD control register. Di spla y Type Di sp la y M od e (See note) Dis p la y Le ve l ( Dis pla y Priorit y) Int errupt R eques t OSD Function SPRITE display (see note) Block display OSD mode All bordered Shadow bordered Top — SPRITE OSD interrupt Middle BUTTON mode All bordered Shadow bordered Raster patterning display (See note) Top OSD interrupt — Bottom Middle Bottom — — Raster flat display Note: Raster patterning display and SPRITE display cannot be used simultaneously. Fig. 8.10.1 Display Types of OSD Function Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 54 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Clock for OSD OSC1 HSYNC VSYNC Main clock XIN Display ocsillation circuit Control registers for OSD OSD control circuit OSD port control register Interrupt input polarity register Block H register Block i V register SPRITE control register SPRITE H register SPRITE V register Color register i OSD control register OSD I/O polarity register Block i control register Left border register Right border register Top border register Bottom border register (Address 00CB16) (Address 00CD16) (Address 00E016) (Addresses 00E116, 00E216) (Address 00E316) (Address 00E416) (Address 00E516) (Addresses 00E616 to 00E916, 00EC16 to 00EF16) (Address 00EA16) (Address 00EB16) (Addresses 00F916, 00FA16) (Address 024016) (Address 024116) (Address 024516) (Address 024616) OSD RAM 15 bits ✕ 24 characters ✕ 2 lines OSD ROM 16 dots ✕ 20 dots ✕ 381 characters Shift register Output circuit R G B OUT1 OUT2 Data bus Fig. 8.10.2 Block Diagram of OSD Circuit Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 55 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP • SPRITE Display • Block Display (OSD Mode) 16 dots • Block Display (BUTTON Mode) 16 dots 2 d o ts 20 dots 20 dots 2 d o ts : BUTTON display area (displayed only in BUTTON mode) Fig. 8.10.3 Configuration of OSD Character Display Area OSD Control Register b7 b6 b5 b4 b3 b2 b1 b0 OSD control register (OC) [Address 00EA16] B 0 1 Name OSD control bit (OC0) (See note 1) Border type selection bit (OC1) Functions 0 : All-blocks display OFF 1 : All-blocks display ON 0 : All bordered 1 : Shadow bordered (See note 2) b3 0 0 1 1 b2 (See notes 3 and 4) 0 : Standard 1 : Standard + 1TOSC 0 : Standard + 2TOSC 1 : Standard + 3TOSC After reset R W 0 0 0 RW RW RW 2, 3 Window horizontal position minute adjustment bit (OC2, OC3) 4 Window control bit (OC4) 0 : Window OFF 1 : Window ON 0 0 RW RW 5 Scan mode selection 0 : Normal scan mode bit (OC5) 1 : Bi-scan mode (See note 5) 6 Raster color OUT1 control bit (OC6) 7 Raster color OUT2 control bit (OC7) 0 : No output 1 : Output 0 : No output 1 : Output 0 0 RW RW Notes 1 : Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next VSYNC. 2 : Shadow border is output at right and bottom side of the font. 3 : TOSC = OSD oscillation cycle 4 : These bits are vallid for both left border and right border (for detail, refer to “(8) Window Function.”) 5 : When setting to bi-scan mode, connect LC between pins OSC1 and OSC2. Fig. 8.10.4 OSD Control Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 56 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (1) Clock for OSD As a clock for display to be used for OSD, it is possible to select one of the following 3 types. • Main clock from the pins XIN and XOUT • Clock from the LC or RC oscillator supplied from the pins OSC1 and OSC2 • Clock from the ceramic resonator or the quartz-crystal oscillator from the pins OSC1 and OSC2 The clock for display to be used for OSD can be selected by bits 0 and 1 of the interrupt input polarity register (address 00CD16). And besides, when selecting main clock, set the oscillation frequency to 8 MHz. Interrupt Input Polarity Register b7 b6 b5 b4 b3 b2 b1 b0 00 0 Interrupt input polarity register (IP) [Address 00CD16] b Name Function Function b1 b0 0 0 The clock for OSD is supplied by connecting RC or LC across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode. 0 1 Since the main clock is used as the clock for OSD, the oscillation frequency is limited. Because of this, the character size in width (horizonal) direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P33 and P34 respectively. 0 After reset R W 0 RW 0, 1 OSD clock selection bits (OCG0, OCG1) OSD oscillation frequency = f(XIN) 1 The clock for OSD is supplied by connecting LC across the pins OSC1 and OSC2. In the bi-scan mode, be sure to set this. The clock for OSD is supplied by connecting the following across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode. • a ceramic resonator only for OSD and a feedback resistor • a quartz-crystal oscillator only for OSD and a feedback resistor 0 0 0 0 0 RW RW RW RW RW 1 1 2 3 4 5 Fix this bit to “0.” INT1 polarity switch bit (POL1) INT2 polarity switch bit (POL2) INT3 polarity switch bit (POL3) 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 6, 7 Fix these bits to “0.” Fig. 8.10.5 Interrupt Input Polarity Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 57 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (2) Scan mode This microcomputer has the bi-scan mode for corresponding to HSYNC of double-speed frequency. In the bi-scan mode, the vertical start display position and the vertical dot size is two times as compared with the normal scan mode. The scan mode is selected by bit 5 of the OSD control register (refer to Figure 8.10.3). Table 8.10.1 Setting for Scan Mode Scan Mode Parameter Bit 5 of OSD Control Register Vertical Display Start Position Vertical Dot Size Normal Scan 0 Value of vertical position register ✕ 1H 1TOSC ✕ 1H 2TOSC ✕ 2H 3TOSC ✕ 3H Bi-Scan 1 Value of vertical position register ✕ 2H 1TOSC ✕ 2H 2TOSC ✕ 4H 3TOSC ✕ 6H Notes 1: TOSC = OSD oscillation cycle 2: H = HSYNC Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 58 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (3) OSD input/output pin control The OSD output pins R, G, B, OUT1 and OUT2 can also function as ports P52, P53, P54, P55, P10 respectively. Switch either OSD output function or port function by the OSD port control register (address 00CB16). The input polarity of the HSYNC, VSYNC and output polarity of signals R, G, B, OUT1 and OUT2 can be specified with the OSD I/O polarity register (address 00EB16). Set a bit to “0” to specify positive polarity; set it to “1” to specify negative polarity. Figure 8.10.6 shows the OSD I/O polarity register and Figure 8.10.7 shows the OSD port control register. OSD I/O Polarity Register b7 b6 b5 b4 b3 b2 b1 b0 OSD I/O polarity register (OPC) [Address 00EB16] B 0 1 2 3 4 5 6 7 Name HSYNC input polarity switch bit (OPC0) VSYNC input polarity switch bit (OPC1) Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input Af t er r e R W 0 0 0 0 0 0 0 0 RW RW RW R W R/G/B output polarity switch 0 : Positive polarity output 1 : Negative polarity output bit (OPC2) OUT1 output polarity switch bit (OPC3) OUT2 output polarity switch bit (OPC4) Raster color R control bit (OPC5) Raster color G control bit (OPC6) Raster color B control bit (OPC7) 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output RW RW RW RW Fig. 8.10.6 OSD I/O Polarity Register OSD Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 00 OSD port control register (PF ) [Address 00CB16] b Name Functions After reset R W 0 RW RW RW RW RW RW RW 0, 1 Fix these bits to “0” 2 3 4 5 6 7 Port P52 output signal selection bit (P52SEL) Port P53 output signal selection bit (P53SEL) Port P54 output signal selection bit (P54SEL) Port P55 output signal selection bit (P55SEL) Port P10 output signal selection bit (OUT2SEL) Fix this bit to “0” 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P55 output 0 : Port P10 signal output 1 : OUT2 output 0 0 0 0 0 0 Fig. 8.10.7 OSD Port Control Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 59 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.10.1 Block Display There are 2 display modes and they are selected by a block unit. The display modes are selected by bits 0 to 2 of block i control register (i = 1, 2). The features of each mode are described below. There are an extended display mode. This mode allows multiple lines (3 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Table 8.10.2 Features of Each Display Style of Block Display Display style Display mode Parameter Number of display characters Dot structure Kinds of characters Kinds of character sizes Dot size Attribute Character font coloring Character background coloring OSD output Raster coloring Other functions Display position Display expansion (multiline display) Notes 1: TOSC = OSD oscillation cycle 2: H = HSYNC 3: The SPRITE display is not effected by the window function. 16 ✕ 20 dots OSD mode (On-screen display mode) 24 characters ✕ 2 lines 16 ✕ 20 dots Character display area: (16 dots + 4 dots ) ✕ (20 dots + 4 dots) 381 kinds 3 kinds 1TOSC ✕ 1H, 2TOSC ✕ 2H, 3TOSC ✕ 3H (per block unit) (See notes 1, 2) Border (per block unit) s Border (per block unit) s BUTTON display (per character unit) s Block shadow display (per character unit) 1 screen: 8 kinds (per character unit) 1 screen: 8 kinds (per character unit) R, G, B Possible (per screen unit) s Corresponding to bi-scan s Window function (See note 3) Horizontal: 64 levels, Vertical: 255 levels Possible Block display BUTTON mode (BUTTON display mode) Block i Control Register b7 b6 b5 b4 b3 b2 b1 b0 Block i control register (BiC) (i = 1, 2) [Addresses 00F916, 00FA16] Functions After reset b2 b1 b0 Display mode Indeterminate ✕ 0 0 Display OFF 0 0 1 OSD mode (no border) 0 1 0 BUTTON mode (no border) 1 0 1 OSD mode (border) 1 1 0 BUTTON mode (border) Indeterminate Dot size selection bit b4 b3 Dot size 3, 4 (BiC3, BiC4) 00 1TOSC ✕ 1H 01 Do not set 10 2TOSC ✕ 2H 11 3TOSC ✕ 3H 5 Nothing is assigned. These bits are write disable bits. 0 to When these bits are read out, the values are “0.” 7 B Name 0 Display mode to selection bits 2 (BiC0 to BiC2) Notes 1 : TOSC = OSD oscillation cycle 2 : H = HSYNC RW RW RW R— Fig. 8.10.8 Block i Control Register (i = 1, 2) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 60 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (1) Display position The display positions of characters are specified by a block. There are 2 blocks, blocks 1 and 2. Up to 24 characters can be displayed in each block (refer to “(3) Memory for OSD”). The display position of each block can be set in both horizontal and vertical directions by software. The display start position in the horizontal direction can be set for all blocks in common in 64-step display positions in units of 4TOSC (TOSC = OSD oscillation cycle). The display start position in the vertical direction for each block can be set in 255-step display positions in units of 1 H ( H = HSYNC cycle). Blocks are displayed in conformance with the following rules: • When the display position of block 1 is overlapped with block 2 (Figure 8.10.9 (b)), block 1 is displayed on the front. • When another block display position appears while one block is . displayed (Figure 8.10.9 (c)), the block with a larger set value as the vertical display start position is displayed. For the display position of SPRITE display, it is necessary to set independently, and it is possible to set display positions independently. Refer to “8.10.2 SPRITE Display.” BHP B1VP Block 1 B2VP Block 2 (a) Example when each block is separated BHP B1VP = B2VP Block 1 (Block 2 is not displayed) (b) Example when block 2 overlaps with block 1 BHP B1VP B2VP Block 1 Block 2 (c) Example when block 2 overlaps in process of block 1 Notes 1: B1VP or B2VP indicates the vertical display start position of display blocks 1 and 2. 2: BHP indicates the horizontal display start position of display blocks 1 and 2. Fig. 8.10.9 Display Position Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 61 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP The vertical display start position is determined by counting the horizontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can select with the OSD I/ O polarity register (address 00EB16). 8 machine cycles or more VSYNC signal input 0.25 to 0.50 [µs] ( at f(XIN) = 8MHz) VSYNC control signal in microcomputer Period of counting HSYNC signal HSYNC signal input 8 machine cycles or more 1 2 3 4 5 (See note 2) Not count When bits 0 and 1 of the I/O polarity control register (address 00EB16) are set to “1” (negative polarity) Notes 1 : The vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer. 2 : Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. 3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or more. Fig. 8.10.10 Supplement Explanation for Display Position The vertical display start position for each block can be set in 255 steps (where each step is 1H (H: HSYNC cycle)) as values “0116” to “FF16” in block i V register (i = 1, 2) (addresses 00E116 to 00E216). When setting the block i V register to “0116,” the display is started at 18H of count value of HSYNC signal. The vertical display start position here indicates the top position of character display area in OSD/ BUTTON mode. The block i V register is shown in Figures 8.10.11. Block i V Register b7 b6 b5 b4 b3 b2 b1 b0 Block i V register (BiVP) (i = 1, 2) [Addresses 00E116 and 00E216] B Name Functions 0 Control bits of Vertical display start positions = Hdef + H ✕ n to vertical display (n: setting value, Hdef: 17H, H: HSYNC) 7 start positions (BiVP0 to BiVP7) (See note 1) Note: Set values except “0016” to BiVP. After reset R W Indeterminate R W Fig. 8.10.11 Block i V Register (i = 1, 2) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 62 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP VSYNC HSYNC (When setting “0116” to block i V register, vertical display start position for each mode) 1 2 3 screen Hdef 17 18 NV Vertical display start position Nv Hdef :Value of block V register i (decimal) :17H OSD mode BUTTON mode When bits 0 and 1 of OSD I/O polarity register (address 00EB16) are “1” (negative polarity) Fig. 8.10.12 Notes on Vertical Display Start Position The horizontal display start position is common to all blocks, and can be set in 64 steps (where 1 step is 4TOSC , TOSC being the OSD oscillation cycle) as values “0016” to “3F16” in the block H register (address 00E016). The block H register is shown in Figure 8.10.13. Block H Register b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HP) [Address 00E016] B Name Functions After reset R W 0 RW 0 Control bits of horizontal Horizontal display start positions = Tdef1 + 4TOSC ✕ n to display start positions (n: setting value, Tdef1: 31TOSC, 5 (BHP0 to BHP5) TOSC: OSD oscillation cycle) (See note 1) 6, 7 Nothing is assigned. These bits are write disable bits. W h en t h e s e b i t s a r e re a d o u t, t h e v a l u e s a r e “0 . ” Note: The setting value synchronizes with the VSYNC. 0 R— Fig. 8.10.13 Block H Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 63 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP When setting the block H register to “0016,” it needs 31TOSC (= Tdef1) from a rising edge (negative polarity) of HSYNC signal to horizontal display start position. The horizontal display start position here indicates the left position of the 1st character’s BUTTON display area in BUTTON mode. When also changing character size, the horizontal display start position is the same. In OSD mode, display position is shifted for BUTTON display area (for 2 dots) from that of the same character size in BUTTON mode. Horizontal display start position HSYNC Tdef1 4TOSC ✕ NH BUTTON mode (1TOSC ✕ 1H) ••• BUTTON mode (2TOSC ✕ 2H) NH : Value of block H register (decimal) TOSC : OSD oscillation cycle Tdef1 : 31TOSC ••• BUTTON mode (3TOSC ✕ 3H) ••• OSD mode ••• Width of BUTTON display area (2 dots) Fig. 8.10.14 Notes on Horizontal Display Start Position Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 64 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (2) Dot size The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing HSYNC in the vertical dot size control circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (OSC1, main clock from pin XIN) in the pre-divide circuit. The dot size is specified by bits 3 and 4 of the block i control register. Refer to Figure 8.10.8 (the block i control register). The block diagram of dot size control circuit is shown in Figure 8.10.15. OSC1 Synchronous circuit OCG0 = “1” OCG1 = “0” Clock cycle = 1TOSC Horizontal dot size control circuit Main clock XIN HSYNC Vertical dot size control circuit OSD control circuit Fig. 8.10.15 Block Diagram of Dot Size Control Circuit 1 dot 1TOSC 1H 2H 2TOSC 3TOSC Scanning line of F1(F2) Scanning line of F2(F1) 3H Fig. 8.10.16 Definition of Dot Sizes Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 65 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (3) Memory for OSD There are 2 types of memory for OSD : OSD ROM (addresses 1140016 to 13BFF16 and 1540016 to 17AFF16) used to specify character dot data and OSD RAM (addresses 080016 to 0877) used to specify the characters, colors, and attribute. The following describes each type of memory. ➀ OSD ROM (addresses 1140016 to 13BFF16, 1540016 to 17AFF16) The dot pattern data for OSD characters is stored in the character font area in the OSD ROM. To specify the kinds of the character font, it is necessary to write the character code (based on OSD ROM address) into the OSD RAM. The modes are selected by bit 3 of the OSD control register 3 for each screen. The character font data storing address is shown in Figure 8.10.17. OSD ROM address of character font data OSD ROM address bit Line number / Character code / Font bit AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Font bit 1 0 Character code (highorder 1) Line number Character code (low-order 8 bits) Line number = “0A16” to “1D16” Character code = “00016” to “17F16” (“07F16”, “08016” and “17F16 ” cannot be used.) Font bit = 0: Left area 1: Right area Line number 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D b7 Left area b0 b7 Right area b0 OSD ROM data 000016 7FF016 7FF816 601C16 600C16 600C16 600C16 600C16 601C16 7FF816 7FF016 630016 638016 61C016 60E016 607016 603816 601C16 600C16 000016 Character font Fig. 8.10.17 Character Font Data Storing Address Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 66 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Note: The 120-byte addresses corresponding to the character code “07F16,” “08016” and “17F16” in OSD ROM are the test data storing area. Set “FF16” to the area. (We stores the test data to this area and the different data from “FF16” is stored for the actual products.) • 1100016 + (4 + 2n) ✕ 10016 + FE16 to 1100016 + (5 + 2n) ✕ 10016 + 0116 • 1500016 + (4 + 2n) ✕ 10016 + FE16 and 1500016 + (4 + 2n) ✕ 10016 + 0116 (n = 0 to 19) Address area                addresses 114FE16 to 1150116 addresses 116FE16 to 1170116 addresses 138FE16 to 1390116 addresses 13AFE16 to 13B0116 addresses 154FE16 and 154FF16 addresses 156FE16 and 156FF16 addresses 178FE16 and 178FF16 addresses 17AFE16 and 17AFF16                ➁ OSD RAM (addresses 080016 to 087716) The OSD RAM for character is allocated at addresses 080016 to 084716, 085016 to 085716, 086016 to 086716, 087016 to 087716, and is divided into a display character code specification part 087016 to 087716, and color/attribute specification part for each block. Tables 8.10.3 shows the contents of the OSD RAM. For example, to display 1 character position (the left edge) in block 1, write the character code in address 080016, write color/attribute code at 081016. The structure of the OSD RAM is shown in Figure 8.10.18. Table 8.10.3 Contents of OSD RAM Display Position (from left) Block 1st character 2nd character 3rd character : 16th character 17st character : 24nd character 1st character 2nd character 3rd character : 16th character 17st character : 24nd character … … Character Code Specification 080016 080116 080216 : 080F16 084016 : 084716 082016 082116 082216 : 082F16 086016 : 086716 Color/Attribute Code Specification 081016 081116 081216 : 081F16 085016 : 085716 083016 083116 083216 : 083F16 087016 : 087716 Block 1 Block 2 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 67 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Blocks 1 and 2 b7 0 b0 b7 b0 RA6 RA5 RA4 RA3 RA2 RA1 RF8 RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 OUT2 control Attribute code (See note 1) Mode Color code Character code 1 (See note 2) BUTTON Mode Bit OSD Mode Bit name Character code Character code in OSD ROM Character code in OSD ROM Function Bit name Character code Function RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 RA 1 Color code RA3 RA2 RA1 Color code RA3 RA2 RA1 0 0 RA 2 0 0 1 RA 3 1 1 1 RA 4 Attribute code 0 0 RA 5 RA 6 RA 7 OUT2 control Fix to “0” 1 0 0 0 1 1 0 0 1 1 0: Color register 1 1: Color register 2 0: Color register 3 1: Color register 4 0: Color register 5 1: Color register 6 0: Color register 7 1: Color register 8 Not used 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0: Color register 1 1: Color register 2 0: Color register 3 1: Color register 4 0: Color register 5 1: Color register 6 0: Color register 7 1: Color register 8 RA4 RA4 0: No BUTTON/block shadow display 1: ON BUTTON display 0: OFF BUTTON display 1: Block shadow display OUT2 control Fix to “0” 0: OUT2 blank output OFF 1: OUT2 blank output ON 0: OUT2 blank output OFF 1: OUT2 blank output ON Notes 1: Attribute code is valid in only BUTTON mode. 2: Do not use character codes “07F16,” “08016,” “17F16.” And also, do not use character codes “18016” to “1FF16” (these codes are not included in OSD ROM area). Fig. 8.10.18 Structure of OSD RAM Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 68 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (4) Character color Character colors are specified by RA1 to RA3 of OSD RAM. Color data are set by color register i (CO1 to CO8: addresses 00E616 to 00E916, 00EC16 to 00EF16) in advance, and 8 kinds of color register i are specified by color codes. (6) OUT1, OUT2 signals OUT1 signal is used to erase a back ground TV image. The output waveform of OUT1 signal is controlled by combining the following bits; the display mode selection bits (bits 0 to 2 of the block i control register), the border type selection bit (bit 1 of the OSD control register), and the OUT1 output control bit (bit 6 of color register i). Figure 8.10.20 and 8.10.21 shows the output example of R, G, B, and OUT1. OUT2 signal is used to change the luminance of a background TV image. The output waveform of OUT2 signal is blank output and is controlled per character unit by RA6 of OSD RAM. (5) Character background color Character background are specified by color register i as same as character color. Note : The character background is displayed in the following part: (character display area) – (character font) — (border) – (BUTTON display area) Accordingly, the character background color and the color signal for these sections cannot be mixed. Color Register i b7 b6 b5 b4 b3 b2 b1 b0 Color register i (CO1 to CO8) (i=1 to 8) [Addresses 00E616 to 00E916, 00EC16 to 00EF16] B 0 1 2 3 4 5 6 7 Name R signal output selection bit (COi0) G signal output selection bit (COi1) B signal output selection bit (COi2) Functions 0: No output 1: Output 0: No output 1: Output 0: No output 1: Output After re set RW Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W 0 R— R signal output (background) 0: No output selection bit (COi3) 1: Output G signal output (background) 0: No output selection bit (COi4) 1: Output B signal output (background) 0: No output 1: Output selection bit (COi5) OUT1 output control bit (COi6) 0: Character output 1: Blank output Nothing is assined. This bit is a write disable bit. When this bit is read out, the value is “0.” Fig. 8.10.19 Color register i (i = 1 to 8) Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 69 of 124 OSD color register i G output OUT1 output Display example b3 b2 b1 b0 = FONT = “L” (See note 1) = FONT Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z B output (background output) 0 0 0 1 0 No output = FONT = AREA — FONT = AREA Display mode b6 b5 b4 0 0 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Fig. 8.10.20 Output Example of R, G, B and OUT1 (Character Color: Green, Character Background Color: Blue) (In OSD Mode) page 70 of 124 0 0 0 1 0 = FONT = “L” (See note 1) = FONT + BORDER OS D (Not bordered) 1 1 0 0 0 0 1 0 No output 0 OS D (Bordered) = FONT = AREA— FONT — BORDER =AREA 1 0 0 0 1 0 1 = GREEN (= G) FONT= font pattern output = BLUE (= B) AREA = character display area in OSD mode OSD mode character display area (AREA) BUTTON mode character display area = BLACK ( = OUT1) = WHITE (= R + G + B) BORDER = border pattern output around FONT BUTTON = buttun display output around AREA Notes 1: when positive polarity is selected. 2: Examples of all bordered display are shown. OSD color register i G output OUT1 output Display example = FONT + BUTTON Display mode b6 b5 b4 b3 b2 b1 b0 = FONT + BUTTON = BUTTON Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z B output (background output) 0 0 0 0 0 1 0 = FONT + BUTTON = AREA + BUTTON – FONT = AREA + BUTTON M37225M6/M8/MA/MC-XXXSP, M37225ECSP Fig. 8.10.21 Output Example of R, G, B and OUT1 (Character Color: Green, Character Background Color: Blue) (In BUTTON Mode) page 71 of 124 1 1 0 0 0 1 0 = FONT + BUTTON = BUTTON = FONT + BORDER + BUTTON OS D (Not bordered) 0 0 0 0 0 1 0 OS D (Bordered) = FONT + BUTTON = AREA + BUTTON – FONT –BORDER = AREA + BUTTON 1 1 0 0 0 1 0 = GREEN (= G) FONT= font pattern output = BLUE (= B) AREA = character display area in OSD mode OSD mode character display area (AREA) BUTTON mode character display area = BLACK ( = OUT1) = WHITE (= R + G + B) BORDER = border pattern output around FONT BUTTON = buttun display output around AREA Notes 1: when positive polarity is selected. 2: Examples of all bordered display are shown. 3: Examples of BUTTON display by RA4 and RA5 of OSD RAM are shown. M37225M6/M8/MA/MC-XXXSP, M37225ECSP (7) Attribute (block display) The attributes (border, BUTTON display, block shadow display) are controlled to the character font. The display mode is specified per block unit by bits 0 to 2 of the block i control register. The attributes to be controlled are different depending on each mode. OSD mode .............. Border BUTTON mode ....... Border, BUTTON display, block shadow display ➀ Border The border is output in the OSD and BUTTON modes. The all bordered (bordering around of character font) and the shadow bordered (bordering right and bottom sides of character font) are selected per screen unit by bit 1 of OSD control register (refer to Figure 8.10.4). The ON/OFF switch for borders can be controlled per block unit by bit 2 of the block i control register (refer to Figure 8.10.8). The OUT1 signal is used for border output. The horizontal size (x) of border is 1TOSC (TOSC: OSD oscillation cycle) regardless of the character font dot size. The vertical size (y) is 1H (2H in the bi-scan mode) regardless of character font. Notes 1: The border dot area is the shaded area as shown in Figure 8.10.23. In BUTTON mode, it is possible to display in vertical out of character area of 20 dots. 2: When the border dot overlaps on the next character font, the character font has priority (refer to Figure 8.10.22 A). When the border dot overlaps on the next character back ground, the border has priority (refer to Figure 8.10.22 B). 3: The border in vertical out of character area is not displayed in OSD mode (refer to Figure 8.10.22). Character boundary B Character boundary Character boundary A B Priority level: BUTTON display = block shadow display > FONT display > border display > character background display Fig. 8.10.22 Border Priority Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 72 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP All border Border display area 16 dots Width of border dot ( = 1H) (See note) Character font area 2 0 d o ts Width of border dot ( = 1H) (See note) Shadow border Border dot ( =1TOSC) Border dot ( =1TOSC) Note: It is possible in only BUTTON mode. FONT BORDER This is display example when 1TOSC ✕ 1H of dot size. Fig. 8.10.23 Border Display Example and Border Area Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 73 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP ➁ BUTTON display There are 2 kinds of displays; ON BUTTON display and OFF BUTTON display. The BUTTON display is controlled per character unit by RA4 and RA5 of OSD RAM. The BUTTON display area is around the character display area in the BUTTON mode. The ON/OFF BUTTON is displayed by outputting white (R + G + B) or black (OUT) to this area. The horizontal size (x) of BUTTON display area is for 2 dots regardless of the character font dot size. The vertical size (y) is for 2 dots regardless of the vertical dot size of character font. ➂ Block shadow display The block shadow is displayed to the character display area in the BUTTON mode. The block shadow display is controlled per character unit by RA4 and RA5 of OSD RAM. FIgure 8.10.24 shows each display example. The BUTTON/block shadow can be displayed to the character area where combined arbitrary (within 24 characters for a block). Set each character in this case, too. Set “0” to all attribute codes between ON BUTTON, OFF BUTTON and block shadow displays. BUTTON display area (= 2 dots) 16 dots Shadow display area ( = 2 dots) 16 dots 20 dots 22 dots ON BUTTON OFF BUTTON BUTTON display area (= 2 dots) Shadow display area ( = 2 dots) = Character font display area Fig. 8.10.24 ON/OFF BUTTON Display and Block Shadow Display Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 74 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Attribute code Attribute code RA5 RA4 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1 1 (See note 1) (See notes 2, 3) ••• Notes 1: When RA4 = RA5 = “1,” shadow border can be displayed in character display area. 2: When RA4 = RA5 = “0,” character background color can be colored in all display area. 3: 3 kinds of display (ON button, OFF button and block shadow) can be displayed within the same block. Be sure to set attributes between these display to “0.” = Character display area in OSD mode Fig. 8.10.25 Attribute Codes and Display Examples Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 75 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (8) Multiline display This microcomputer can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addition, it can display 3 lines or more by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the block i V registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block. Notes 1: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display by the display control bit of the block control register i (addresses 00F916 and 00FA16), an OSD interrupt request does not occur (refer to Figure 8.10.26 (A)). 2: When another block display appeares while one block is displayed, an OSD interrupt request occurs only once at the end of the another block display (refer to Figure 8.10.26 (B)). 3: On the screen setting window, an OSD interrupt occurs even at the end of the block (off display) out of window (refer to Figure 12.11.36 (C)). Block 1 (on display) Block 2 (on display) Block 1' (on display) Block 2' (on display) “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” “OSD interrupt request” Block 1 (on display) Block 2 (on display) Block 1' (off display) Block 2' (off display) “OSD interrupt request” “OSD interrupt request” No “OSD interrupt request” No “OSD interrupt request” On display (OSD interrupt request occurs at the end of block display) (A) Off display (OSD interrupt request does not occur at the end of block display) Block 1 “OSD interrupt request” Block 1 Block 2 No “OSD interrupt request” “OSD interrupt request” Block 2 “OSD interrupt request” Block 1' “OSD interrupt request” Window (B) (C) Fig. 8.10.26 Note on Occurence of OSD Interrupt Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 76 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP (9) Window function The window function can be set windows on-screen, and output OSD within only the area where the window is set. The ON/OFF for vertical window function is performed by bit 4 of the OSD control register. The top boundary is set by the top border control register (TBR) and the bottom boundary is set by bottom border control register (BBR). The left boundary is set by the left border control register (LBR), and the right boundary is set by the right border control register (RBR). The left and right boundarys can be adjusted minutely by bits 2 and 3 of the OSD control register (address 00EA16). Note: The SPRITE display is not effected by the window function. HSYNC Tdef4 4TOSC ✕ LBR + 1TOSC ✕ WH 4TOSC ✕ RBR + 1TOSC ✕ WH VSYNC Left boundary of window Hdef TBR Window Right boundary of window Top boundary of window F BBR GH I J Window KL P MNO QRST Bottom boundary of window Screen LBR RBR WH TOSC Tdef4 TBR BBR Hdef H : Value of left border control register : Value of right border control register : Value (0 to 3) of window horizontal position minute adjustment bit : OSD oscillation cycle : 4TOSC : Value of top border control register : Value of bottom border control register : 17H : HSYNC Fig. 8.10.27 Example of window function Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 77 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Top Border Control Register b7 b6 b5 b4 b3 b2 b1 b0 Top border control register (TBR) [Address 024516] B Name Functions 0 Control bits of Top border position = Hdef + H ✕ n to top border (n: setting value, Hdef: 17H, H: HSYNC) 7 (TBR0 to TBR7) Notes 1: Set values except “0016” to TBR. 2: Set values fit for TBR ≤ BBR. After reset R W Indeterminate R W Fig. 8.10.28 Top Border Control Register Bottom Border Control Register b7 b6 b5 b4 b3 b2 b1 b0 Bottom border control register (BBR) [Address 024616] B Name Functions 0 Control bits of Bottom border position = Hdef + H ✕ n to bottom border (n: setting value, Hdef: 17H, H: HSYNC) 7 (BBR0 to BBR7) Notes 1: Set values except “0016” to BBR. 2: Set values fit for TBR ≤ BBR. After reset R W Indeterminate R W Fig. 8.10.29 Bottom Border Control Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 78 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Left Border Control Register b7 b6 b5 b4 b3 b2 b1 b0 Left border control register (LBR) [Address 024016] B 0 to 6 7 Name Control bits of left border (LBR0 to LBR6) Functions Left border position = Tdef4 + 4TOSC ✕ n + 1TOSC ✕ WH (n: setting value, Tdef4: 4TOSC, TOSC: OSD oscillation cycle, WH: value (0 to 3) of window horizontal position minute adjustment bit) After re set R W 0 R W Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is indeterminate. 0 R — Note: Set values fit for LBR ≤ RBR. Fig. 8.10.30 Left BorderControl Register Right Border Control Register b7 b6 b5 b4 b3 b2 b1 b0 Right border control register (RBR) [Address 024116] B 0 to 6 7 Name Control bits of left border (RBR0 to RBR6) Functions Right border position = Tdef4 + 4TOSC ✕ n + 1TOSC ✕WH (n: setting value, Tdef4: 4TOSC, TOSC: OSD oscillation cycle, WH: value (0 to 3) of window horizontal position minute adjustment bit) After re set R W 0 R W Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is indeterminate. 0 R — Note: Set values fit for LBR ≤ RBR. Fig. 8.10.31 Right Border Control Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 79 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.10.2 SPRITE Display This is especially suitable for cursor and other displays as its function allows for display in any position, regardless of the validity of other OSDs or display positions. Each SPRITE font is ROM font consisting of 16 horizontal dots ✕ 20 vertical dots, and there are 4 kinds. When SPRITE display overlaps with other OSDs, SPRITE display is always given priority. To display SPRITE font, OSD ROM font data for 2 characters is used. These 2 fonts can be colored with any color and can be displayed by synthesizing as a character. The features and display example of SPRITE display are shown below. Notes 1: The SPRITE display is not effected by the window function. 2: The SPRITE display cannot output character background color or OUT2. Table 8.10.4 Features of SPRITE Display Parameter Number of display characters Dot structure Kinds of characters Kinds of character sizes Dot size Character font coloring OSD output Other functions Display position Features 1 characters ✕ 1 line (display by synthesizing 2 kinds of characters) 16 ✕ 20 dots (See note 3) 4 kinds (Character code = “F816” to “FF16”) (See note 4) 1 kind 1TOSC ✕ 1H (See notes 5, 7, 8) Synthesis SPRITE fonts 1 and 2 (per SPRITE font unit) R, G, B Corresponding to bi-scan Horizontal: 253 levels (See note 2), Vertical: 255 levels (See note 1) Notes 1: It is possible to set in any position regardless of vertical display positions of the block display. The vertical display start positions of the SPRITE display is the same as that of the block display. 2: It is possible to set in any position regardless of horizontal display position of block display. 3: It is the same display area as OSD mode (refer to “Figure 8.10.3”). 4: As for character font data storing address refer to “8.10.1 Block Display (3) Memory for OSD.” The characters of character codes “F816” to “FF16” can be also used for the block display. 5: Refer to “8.10.1 Block Display (2) Dot size.” The dot size in the bi-scan mode is 1TOSC ✕ 2H. 6: Refer to “8.10.1 Block Display (4) Character color.” Only color registers 1 to 4 can be specified. 7: H = HSYNC 8: TOSC = OSD oscillation cycle USER SELECT BRIGHTNESS TINT SOUND MONAURAL STEREO SPRITE display SPRITE font 1 Note: SPRITE fonts 1 and 2 are displayed by synthesizing. SPRITE font 2 Fig. 8.10.32 SPRITE Display Example Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 80 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP SPRITE H Register b7 b6 b5 b4 b3 b2 b1 b0 SPRITE H register (SHP) [Address 00E416] B Name Functions 0 Horizontal display Horizontal display start position to start position = Tdef2 + 2TOSC ✕ n 7 control bits of (n: setting value, Tdef2: 2TOSC, TOSC: OSD oscillation cycle) SPRITE OSD (SHP0 to SHP7) After reset R W 0 RW Notes 1: Set values except “0016” to “0216” to SHP. 2: When selecting raster patterning display, setting value is synchronized with VSYNC signal; when selecting SPRITE display, it is not synchronized. Fig. 8.10.33 SPRITE H Register When setting the SPRITE H register to “0316,” the interval of Tdef2 + 2TOSC ✕ 3 = 8TOSC is necessary from a rising edge (negative polarity) to horizontal display start position. HSYNC 2TOSC ✕ NH' NH' : value of SPRITE H register (decimal) (see note) TOSC : OSD oscillation cycle Tdef2 : 2TOSC Note: Do not set “0” to “2” to NH'. Tdef2 Fig. 8.10.34 Note on Horizontal Display Start Position of SPRITE Display SPRITE V Register b7 b6 b5 b4 b3 b2 b1 b0 SPRITE V register (SVP) [Address 00E516] B Name Functions After reset R W 0 Horizontal display Horizontal display start position Indeterminate R W to start position = Hdef + H ✕ n 7 control bits of (n: setting value, Hdef: 17H, H: HSYNC) SPRITE OSD (SVP0 to SVP7) (See note 1) Note: Set values except “0016” to the SVP. Fig. 8.10.35 SPRITE V Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 81 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP SPRITE Control Register b7 b6 b5 b4 b3 b2 b1 b0 SPRITE control register (SC) [Address 00E316] B Name SC1 0 0 1 1 SC3 0 0 1 1 Functions SC0 0: Color 1: Color 0: Color 1: Color SC2 0: Color 1: Color 0: Color 1: Color register 1 register 2 register 3 register 4 After reset R W 0 RW 0, 1 SPRITE font 1 color register specification bit (SC0, SC1) 2, 3 SPRITE font 2 color register specification bit (SC2, SC3) 0 register 1 register 2 register 3 register 4 0 RW 4, 5 SPRITE font selection bit (SC4, SC5) SC5 SC4 Character code SPRITE1 SPRITE2 0 0 1 1 0 1 0 1 F816 FA16 FC16 FE16 F916 FB16 FD16 FF16 RW 6, 7 SPRITE/raster patterning control bit (SC6, SC7) (See note) SC7 0 0 1 1 SC6 0: Display OFF 1: Do not set 0: SPRITE display 1: Raster patterning display 0 RW Note : This bit is valid when bit 0 of the OSD control register to “1.” Fig. 8.10.35 SPRITE Control Register Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 82 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.10.3 Raster Display The raster display is displayed on the lower layer than the SPRITE and block layers. There are 2 kinds of displays; the flat display and the patterning display. In the raster flat display, an entire screen (raster) can be colored by setting the following bits; bits 5 to 7 of the OSD I/O polarity register and bits 6 and 7 of the OSD control register. Since each of the R, G, B, OUT1, and OUT2 pins can be switched to raster coloring output, 8 raster colors can be obtained. In the raster patterning display, SPRITE fonts are displayed repeatedly on an entire screen (raster). At this time, set “1” to bits 6 and 7 of the SPRITE control register. Horizontal display start positions of the raster patterning display are set by the SPRITE H register. At this time, setting value is synchronized with VSYNC signal. Characters for patterning are set by bits 4 and 5 of the SPRITE control register and coloring are set by bits 0 to 3. The raster color is output on the background of SPRITE font. Note that the raster patterning display and the SPRITE display cannot be used at the same time. When the character color/the character background color overlaps with the raster color, the color (R, G, B, OUT1, OUT2), specified for the character color/the character background color, takes priority of the raster color. This ensures that the character color/the character background color is not mixed with the raster color. The raster flat display example is shown in Figure 8.10.36, the raster patterning display example is shown in Figure 8.10.37. : Character color “RED” (R + OUT1 + OUT2) : Border color “BLACK” (OUT1 + OUT2) : Background color “MAGENTA” (R + B + OUT1 + OUT2) : Raster color “BLUE” (R + OUT1 + OUT2) A A' HSYNC OUT1 OUT2 R G B Signals across A-A' Fig. 8.10.36 Raster Flat Display Example Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 83 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP When setting “0316” to SPRITE H register, it is need Tdef2 + 2TOSC ✕ 3 = 8TOSC intervals from a rising edge (negative polarity) of HSYNC signal to a horizontal display start position. SPRITE font Raster color “BLUE” (B + OUT1) SPRITE font 1 color “BLACK” (OUT1) SPRITE font 2 color “WHITE” (R + G + B + OUT1) HSYNC Tdef2 2TOSC ✕ NH' (See note) screen NH' : Value of SPRITE H register (decimal) (See note) TOSC : OSD oscillation cycle Tdef2 : 2TOSC Note: Do not set “0” to “2” to NH'. Fig. 8.10.37 Raster Patterning Display Example Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 84 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.11 SOFTWARE RUNAWAY DETECT FUNCTION This microcomputer has a function to decode undefined instructions to detect a software runaway. When an undefined op-code is input to the CPU as an instruction code during operation, the following processing is done. ➀ The CPU generates an undefined instruction decoding signal. ➁ The device is internally reset because of occurrence of the undefined instruction decoding signal. ➂ As a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. Note, however, that the software runaway detecting function cannot be invalid. φ SYNC Address PC ? 01,S 01,S–1 01,S–2 FFFE16 FFFF16 ADH, ADL Data ? PCH PCL PS Reset sequence ADL ADH Undefined instruction decoding signal occurs.Internal reset signal occurs. ? : Undefined instruction decode : Invalid PC : Program counter S : Stack pointer ADL, ADH : Jump destination address of reset Fig.8.11.1 Sequence at Detecting Software Runaway Detection Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 85 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.12. RESET CIRCUIT When the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and the power source voltage is 5 V ± 10 %, hold the RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as shown in Figure 8.12.2, reset is released and the program starts form the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal state of microcomputer at reset are shown in Figures 8.2.3 to 8.2.6. An example of the reset circuit is shown in Figure 8.12.1. The reset input voltage must be kept 0.9 V or less until the power source voltage surpasses 4.5 V. Poweron 4.5 V Power source voltage 0 V Reset input voltage 0 V 0.9 V Vcc 1 5 M51953AL RESET 4 3 0.1 µF Vss Microcomputer Fig.8.12.1 Example of Reset Circuit XIN φ RESET Internal RESET SYNC Address Data ? ? ? ? 01, S 01, S-1 01, S-2 FFFE FFFF ADH , ADL Reset address from the vector table ? ? ? ADL ADH 32768 count of X IN clock cycle (See note 3) Notes 1 : f(XIN) and f(φ) are in the relation : f(X IN) = 2·f (φ). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, “FF 16” is set in timer 3 and “07 16” is set to timer 4. Timer 3 counts down with f(X IN)/16, and reset state is released by the timer 4 overflow signal. Fig.8.12.2 Reset Sequence Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 86 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.13 CLOCK GENERATING CIRCUIT The built-in clock generating circuit is shown in Figure 8.13.3. When the STP instruction is executed, the internal clock φ stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and “FF16” is set in timer 3 and “0716” is set in the timer 4. Select f(XIN)/16 as the timer 3 count source (set bit 0 of the timer mode register 2 to “0” before the execution of the STP instruction). Moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (“0”) before execution of the STP instruction). The oscillator restarts when external interrupt is accepted. However, the internal clock φ keeps its HIGH until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. When the WIT instruction is executed, the internal clock φ stops in the HIGH but the oscillator continues running. This wait state is released when an interrupt is accepted (See note). Since the oscillator does not stop, the next instruction can be executed at once. When returning from the stop or the wait state, to accept an interrupt, set the corresponding interrupt enable bit to “1” before executing the STP or the WIT instructions. Note: In the wait mode, the following interrupts are invalid. • VSYNC interrupt • OSD interrupt • Timer 2 interrupt using external clock input from TIM2 pin as count source • Timer 3 interrupt using external clock input from TIM3 pin as count source • Timer 4 interrupt using f(XIN)/2 as count source • Timer 1 interrupt using f(XIN)/4096 as count source • f(XIN)/4096 interrupt • Multi-master I2C-BUS interface interrupt • A-D conversion interrupt • SPRITE interrupt Microcomputer XIN XOUT CIN COUT Fig.8.13.1 Ceramic Resonator Circuit Example Microcomputer XIN Vcc External oscillation circuit Vss Fig.8.13.2 External Clock Input Circuit Example A circuit example using a ceramic resonator (or a quartz-crystal oscillator) is shown in Figure 8.13.1. Use the circuit constants in accordance with the resonator manufacture’s recommended values. A circuit example with external clock input is shown in Figure 8.13.2. Input the clock to the XIN pin, and open the XOUT pin. Interrupt request S Interrupt disable flag I S Reset WIT instruction Q Q S Reset Q R R Selection gate : Connected to black side at reset. TM2 : Timer mode register 2 STP instruction R STP instruction Internal clock φ 1/2 1/8 TM20 TM22 Timer 3 Timer 4 XIN XOUT Fig.8.13.3 Clock Generating Circuit Block Diagram Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 87 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 8.14 DISPLAY OSCILLATION CIRCUIT The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 0 and 1 of the interrupt input polarity register (address 00CD16). 8.16 ADDRESSING MODE The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 User’s Manual for details. 8.17 MACHINE INSTRUCTIONS There are 71 machine instructions. Refer to SERIES 740 User’s Manual for details. 9. PROGRAMMING NOTES • The divide ratio of the timer is 1/(n+1). • Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. • After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. • An NOP instruction is needed immediately after the execution of a PLP instruction. • In order to avoid noise and latch-up, connect a bypass capacitor (≈ 0.1µF) directly between the VCC pin–VSS pin, AVCC pin–VSS pin, and the VCC pin–CNVSS pin, using a thick wire. OSC1 OSC2 L C1 C2 Fig.8.14.1 Display Oscillation Circuit 8.15 AUTO-CLEAR CIRCUIT When a power source is supplied, the auto-clear function will operate by connecting the following circuit to the RESET pin. Circuit example 1 Vcc RESET Vss Circuit example 2 RESET Vcc Vss Note : Make the level change from “L” to “H” at the point at which the power source voltage exceeds the specified voltage. Fig.8.15.1 Auto-clear Circuit Example Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 88 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 10. ABSOLUTE MAXIMUM RATINGS Symbol VCC, AVCC VI VI Parametear Power source voltage VCC Input voltage Input voltage CNVSS P00–P07, P10–P17, P20–P27, P30–P35, OSC1, XIN, P50, P51, ______ RESET P06, P07, P10–P17, P20–P27, P30–P32, P35, P52–P55, XOUT, OSC2 P00–P05 P52–P55, P10–P17, P20–P27, P30, P31, P35 P52–P55, P06, P07, P10, P15–P17, P20–P23, P30–P32, P35 P11–P14 P00–P05 P24, P27 Conditions All voltages are based on VSS. Output transistors are cut off. Ratings –0.3 to 6 –0.3 to 6 –0.3 to VCC + 0.3 Unit V V V VO Output voltage –0.3 to VCC + 0.3 V VO IOH IOL1 IOL2 IOL3 IOL4 Pd Topr Tstg Output voltage Circuit current Circuit current –0.3 to 13 0 to 1 (See note 1) 0 to 2 (See note 2) 0 to 6 (See note 2) 0 to 1 (See note 2) 0 to 10 (See note 3) 550 –10 to 70 –40 to 125 V mA mA mA mA mA mW °C °C Circuit current Circuit current Circuit current Power dissipation Operating temperature Storage temperature Ta = 25 °C 11. RECOMMENDED OPERATING CONDITIONS (Ta = –10 °C to 70 °C, VCC = 5 V ± 10 %, unless otherwise noted) Symbol VCC VSS VIH1 Parameter Power source voltage (See note 4), During CPU, OSD, data slicer operation Power source voltage HIGH input voltage P00–P07, P10–P17, P20–P27, P30–P35, SIN, SCLK, P50, P51, RESET, XIN, OSC1, TIM2, TIM3, INT1–INT3 HIGH input voltage SCL1, SCL2, SDA1, SDA2 LOW input voltage P00–P07, P10–P17, P20–P27, P30–P35 LOW input voltage SCL1, SCL2, SDA1, SDA2 LOW input voltage (See note 6) P50, P51, RESET, TIM2, TIM3, INT1–INT3, XIN, OSC1, SIN, SCLK HIGH average output current (See note 1) P52–P55, P10–P17, P20–P27, P30, P31, P35 LOW average output current (See note 2) P52–P55, P06, P07, P10, P15–P17, P30–P32, P35 LOW average output current (See note 2) P11–P14 LOW average output current (See note 2) P00–P05 LOW average output current (See note 3) P24–P27 Oscillation frequency (for CPU operation) (See note 5) XIN RC oscillating mode Oscillation frequency (for OSD) OSC1 LC oscillating mode Ceramic oscillating mode Input frequency Input frequency Input frequency TIM2, TIM3 SCLK SCL1, SCL2 Limits Min. 4.5 0 0.8VCC Typ. 5.0 0 Max. 5.5 0 VCC Unit V V V VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 IOL4 f(XIN) fosc 0.7VCC 0 0 0 VCC 0.4 VCC 0.3 VCC 0.2 VCC 1 2 6 1 10 8.1 9.0 17.0 8.1 100 1 400 V V V V mA mA mA mA mA MHz MHz kHz MHz MHz 7.9 5.0 5.0 7.9 8.0 8.0 8.0 8.0 fhs1 fhs2 fhs3 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 89 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 12. ELECTRIC CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Symbol ICC Parameter Power source current System operation Test conditions OSD OFF OSD ON VCC = 5.5 V, f(XIN) = 0 VCC = 4.5 V IOH = –0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 5.5 V, f(XIN) = 8 MHz Min. Limits Typ. 20 30 Max. 40 60 300 Unit mA 1 mA V V 2 Test circuit VOH VOL VCC = 4.5 V IOL = 10.0 mA LOW output voltage P11–P14 VCC = 4.5 V IOL = 3 mA IOL = 6 mA ____________ VT+ – VT– Hysteresis (See note 6) RESET, P50, P51, TIM2, TIM3, VCC = 5.0 V INT1–INT3, SCL1, SCL2, SDA1, SDA2, SIN, SCLK ____________ HIGH input leak current RESET, P00–P07, P10–P17, VCC = 5.5 V IIZH P20–P27, P30–P35, P50, P51 VI = 5.5 V ____________ LOW input leak current RESET, P00–P07, P10–P17, VCC = 5.5 V IIZL P20–P27, P30–P35, P50, P51 VI = 0 V HIGH input leak current P00–P05 VCC = 5.5 V IOZH VI = 12 V I2C-BUS·BUS switch connection resistor VCC = 4.5 V RBS (between SCL1 and SCL2, SDA1 and SDA2) Stop mode HIGH output voltage P52–P55, P10–P17, P20–P27,P30, P31, P35 LOW output voltage P52–P55, P00–P07, P10, P15–P17, P20–P23, P30–P32, P35 LOW output voltage P24–P27 2.4 0.4 3.0 0.4 0.6 1.3 0.5 V 3 5 5 10 130 µA µA µA Ω 4 5 6 Notes 1: The total current that flows out of the IC must be 20 mA or less. 2: The total input current to IC (IOL1 + IOL2 + IOL3) must be 30 mA or less. 3: The total average input current for ports P24–P27 to IC must be 20 mA or less. 4: Connect 0.1 µF or more capacitor externally between the power source pins VCC–VSS so as to reduce power source noise. Also connect 0.1 µF or more capacitor externally between the pins VCC–CNVSS. 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6: P06, P07, P15, P23, P24 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11–P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P20–P22 have the hysteresis when these pins are used as serial I/O pins. 7: Pin names in each parameter is described as below. (1) Dedicated pins: dedicated pin names. (2) Duble-/triple-function ports • When the same limits: I/O port name. • When the limits of functins except ports are different from I/O port limits: function pin name. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 90 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP + Power source voltage 1 A Icc XIN 8.00 MHz OSC1 XOUT Vcc 2 4.5 V Vcc Each output pin OSC2 VOH Vss Vss IOH or IOL V or VO L Pin VCC is made the operation state and is measured the current, with a ceramic resonator. After setting each output pin to HIGH level when measuring VOH and to LOW level when measuring VOL, each pin is measured. 3 5.0 V 4 5.5 V Vcc Vcc IIZH or IIZL A Each input pin Each input pin Vss Vss 5.5 V 5 6 4.5V V cc IOZH Each output pin A 12 V Vcc SCL1 or SDA1 A RB S IBS SCL2 or SDA2 V ss Vss VBS After setting each output pin OFF state, each pin is measured RBS = VBS/IBS Fig.12.1 Measure Circuits Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 91 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 13. A-D CONVERTER CHARACTERISTICS (VCC = 5 V ± 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = –10 °C to 70 °C, unless otherwise noted) Symbol — — TCONV RLADDER VIA Parameter Resolution Absolute accuracy (excludig guantization error) Conversion time Ladder resistor Analog input voltage Test conditions Min. Limits Typ. Max. 8 ±2.5 12.5 VREF Unit bits LSB µs kΩ V Vcc = 5 V 12.25 25 0 14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS Symbol tBUF tHD; STA tLOW tR tHD; DAT tHIGH tF tSU; DAT tSU; STA tSU; STO Parameter Bus free time Hold time for START condition LOW period of SCL clock Rising time of both SCL and SDA signals Data hold time HIGH period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition Standard clock mode High-speed clock mode Unit Min. Max. Min. Max. 4.7 1.3 µs 4.0 0.6 µs 4.7 1.3 µs 1000 20+0.1Cb 300 ns 0 0 0.9 µs 4.0 0.6 µs 300 20+0.1Cb 300 ns 250 100 ns 4.7 0.6 µs 4.0 0.6 µs Note: Cb = total capacitance of 1 bus line SDA tHD;STA tSU;STO tBUF tLOW P SCL S tR tF Sr P tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA S : Start condition Sr : Restart condition P : Stop condition Fig.14.1 Definition Diagram of Timing on Multi-master I2C-BUS Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 92 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 15. PROM PROGRAMMING METHOD The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Product M37225ECSP Name of Programming Adapter PCA7408 The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes. To ensure proper operation after programming, the procedure shown in Figure 15.1 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150°C exceeding 100 hours. Fig. 15.1 Programming and Testing of One Time PROM Version Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 93 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 16. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: • Mask ROM Order Confirmation Form • Mark Specification Form • Data to be written to ROM, in EPROM form (32-pin DIP Type 27C101, three identical copies) or FDK Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 94 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 17. ONE TIME PROM VERSION M37225ECSP MARKING M37225ECSP XXXXXX XXXXXX is lot number Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 95 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 18. APPENDIX Pin Configuration (TOP VIEW) HSYNC/P50 VSYNC/P51 P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 DA1/P35 P32/A-D7 CNVSS XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 R/P52 G/P53 B/P54 OUT1/P55 P20/SCLK P21/SOUT(/SIN) P22/SIN P10/OUT2/A-D8 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/INT3/A-D1 P16/A-D2 P17/DA2/A-D3 P30/A-D5 P31/A-D6 RESET OSC1/P33 OSC2/P34 VCC Outline 42P4B M37225M6/M8/MA/MC-XXXSP M37225ECSP Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 96 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Memory Map sM37225M6/M8-XXXSP 000016 00BF16 00C016 SFR area 00FF16 010016 01FF16 Not used 021716 021D16 (1024 bytes) 024016 2 page register (2) 024F16 02C016 ROM correction function 02E016 030016 Vector 1: address 02C016 Vector 2: address 02E016 Vector 3: address 030016 15C0016 15CFF16 Not used 04FF16 OSD RAM (96 byres) (See note) Not used 080016 087716 1600016 160FF16 Not used 1620016 162FF16 Not used 1640016 164FF16 Not used 1660016 166FF16 Not used 1680016 168FF16 Not used 16A0016 16AFF16 Not used 16C0016 16CFF16 Not used 16E0016 Not used 16EFF16 Not used 1700016 170FF16 Not used 1720016 172FF16 Not used 1740016 174FF16 Not used 1760016 176FF16 Not used 1780016 178FF16 Not used 17A0016 17AFF16 15E0016 15EFF16 Not used 15A0016 15AFF16 Not used Not used 1580016 158FF16 Not used 2 page register (1) Not used 1000016 1140016 Zero page OSD ROM (15K bytes) 13BFF16 Not used 1540016 154FF16 Not used 1560016 156FF16 Not used Not used M37225M8XXXSP ROM (32K bytes) M37225M6XXXSP ROM (24K bytes) 800016 A00016 Not used FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.10.3 OSD RAM. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 97 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP sM37225MA/MC-XXXSP, M37225ECSP 000016 00BF16 00C016 00FF16 010016 01FF16 Not used RAM (2048 bytes) 021716 021D16 024016 2 page register (2) 024F16 02C016 ROM correction function 02E016 030016 Vector 1: address 02C016 Vector 2: address 02E016 Vector 3: address 030016 15C0016 15CFF16 Not used OSD RAM (96 bytes) (See note) 07FF16 080016 087716 Not used 090016 09FF16 1620016 162FF16 Not used 1640016 164FF16 Not used 1660016 166FF16 Not used 1680016 168FF16 Not used 16A0016 16AFF16 Not used 16C0016 16CFF16 Not used Not used 16E0016 16EFF16 Not used 1700016 170FF16 Not used 1720016 172FF16 Not used 1740016 174FF16 Not used 1760016 176FF16 Not used 1780016 178FF16 Not used 17A0016 17AFF16 M37225MC-XXXSP M37225ECSP ROM (48K bytes) 400016 600016 M37225MA-XXXSP ROM (40K bytes) Not used 15E0016 15EFF16 Not used 1600016 160FF16 Not used 15A0016 15AFF16 Not used Not used 1580016 158FF16 Not used 2 page register (1) Not used 1000016 1140016 Zero page SFR area OSD ROM (15K bytes) 13BFF16 Not used 1540016 154FF16 Not used 1560016 156FF16 Not used Not used FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.10.3 OSD RAM. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 98 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Memory Map of Special Function Register (SFR) s SFR area (addresses C016 to DF16) < Bit allocation > < State immediately after reset > : Name Function bit 0 : “0” immediately after reset 1 : “1” immediately after reset ? : Indeterminate immediately after reset : : No function bit 0 : Fix to this bit to “0” (do not write to “1”) 1 : Fix to this bit to “1” (do not write to “0”) Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) Port P35 output mode control register (P3S) Port P5 (P5) OSD port control register (PF) Test register Interrupt input polarity register (IP) DA1-H register (DA1-H) DA1-L register (DA1-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2C control register (S1D) I2C clock control register (S2) Serial I/O mode register (SM) Serial I/O register (SIO) AD conversion register (AD) AD control register (ADCON) PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 P35 P34IN P33IN P32 P31S P30S P35D P31 P30 P32D P31D P30D Bit allocation b7 State immediately after reset b0 b7 b0 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 P35S P52 P51 OUT IN P52 SEL 0 P50 IN P55 P54 P53 OUT OUT OUT OUT2 P55 P54 P53 SEL SEL SEL SEL 0 1 0 POL3 POL2 POL1 1 0 OCG1OCG0 0 0 ? 0 D7 0 D6 PN5 PN4 PN3 PN2 D5 D4 D3 D2 0 D1 0 D0 SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB PIN AL AAS AD0 LRB 0 0 0 BSEL1 BSEL0 10BIT ALS ESO BC2 BC1 BC0 SAD FAST ACK ACK MODE CCR4 CCR3 CCR2 CCR1 CCR0 BIT SM6 SM5 0 SM3 SM2 SM1 SM0 0 0 ADVREF ADSTR ADIN2 ADIN1 ADIN0 ? 0016 ? 0016 ? 0016 ? ?? ? 0? ?? 0016 01 0016 ? ?? ? ? ? ? ? 0016 0016 ? 0016 10 0016 0016 0016 ? ? 0816 0 ? ? 1 0 ? ? ? 0 ? ? ? ? ? ? 0 0 ? Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 99 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP s SFR area (addresses E016 to FF16) < Bit allocation > < State immediately after reset > : Name Function bit 0 : “0” immediately after reset 1 : “1” immediately after reset ? : Indeterminate immediately after reset : : No function bit 0 : Fix to this bit to “0” (do not write to “1”) 1 : Fix to this bit to “1” (do not write to “0”) Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register b7 Block H register (BHP) Block 1V register (B1VP) Block 2V register (B2VP) SPRITE control register (SC) SPRITE H register (SHP) SPRITE V register (SVP) Color register 1 (CO1) Color register 2 (CO2) Color register 3 (CO3) Color register 4 (CO4) OSD control register (OC) OSD I/O polarity control register (OPC) Color register 5 (CO5) Color register 6 (CO6) Color register 7 (CO7) Color register 8 (CO8) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer mode register 1 (TM1) Timer mode register 2 (TM2) PWM5 register (PWM5) Test register Test register Block 1 control register (B1C) Block 2 control register (B2C) CPU mode register (CM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) TM15 TM14 TM13 TM12 TM11 TM10 TM25 TM24 TM23 TM22 TM21 TM20 Bit allocation BHP5 BHP4 BHP3 BHP2 BHP1 BHP0 B1VP7 B1VP6 B1VP5 B1VP4 B1VP3 B1VP2 B1VP1 B1VP0 B2VP7 B2VP6 B2VP5 B2VP4 B2VP3 B2VP2 B2VP1 B2VP0 SC7 SC6 SC5 SC4 SC3 SC2 SC1 SC0 SHP7 SHP6 SHP5 SHP4 SHP3 SHP2 SHP1 SHP0 SVP7 SVP6 SVP5 SVP4 SVP3 SVP2 SVP1 SVP0 CO16 CO15 CO14 CO13 CO12 CO11 CO10 CO26 CO25 CO24 CO23 CO22 CO21 CO20 CO36 CO35 CO34 CO33 CO32 CO31 CO30 CO46 CO45 CO44 CO43 CO42 CO41 CO40 State immediately after reset b0 b7 b0 0 0 0 0 ? ? ? ? ? ? ? ? OC7 OC6 OC5 OC4 OC3 OC2 OC1 OC0 OPC7 OPC6 OPC5 OPC4 OPC3 OPC2 OPC1 OPC0 CO56 CO55 CO54 CO53 CO52 CO51 CO50 CO66 CO65 CO64 CO63 CO62 CO61 CO60 CO76 CO75 CO74 CO73 CO72 CO71 CO70 CO86 CO85 CO84 CO83 CO82 CO81 CO80 0 0 0 0 ? ? ? ? ? ? ? ? 0016 0016 B1C4 B1C3 B1C2 B1C1 B1C0 B2C4 B2C3 B2C2 B2C1 B2C0 0 0 0 0 0 0 0 0 0 A DR 1 1 1 CM2 0 0 IT3R IICR VSCR OSDR TM4R TM3R TM2R TM1R MSR SPR S1R IT2R IT1R CK 0 IT3E IICE VSCE OSDE TM4E TM3E TM2E TM1E A DE 0 MSE SPE S1E IT2E IT1E 0016 ? ? 0016 0016 ? ?? ?? ?? ?? 0016 0016 ?? ?? ?? ?? FF16 0716 FF16 0716 0016 0016 ? ? ? CK 0 ? ? CK0 ? ? 3C16 0016 0016 0016 0016 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 100 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP s 2 page register area (addresses 21016 to 21F16, 24016 to 24F16) < Bit allocation > < State immediately after reset > : Name Function bit 0 : “0” immediately after reset 1 : “1” immediately after reset ? : Indeterminate immediately after reset : : No function bit 0 : Fix to this bit to “0” (do not write to “1”) 1 : Fix to this bit to “1” (do not write to “0”) Address 21016 21116 21216 21316 21416 21516 21616 21716 21816 21916 21A16 21B16 21C16 21D16 21E16 21F16 24016 24116 24216 24316 24416 24516 24616 24716 24816 24916 24A16 24B16 24C16 24D16 24E16 24F16 Register Bit allocation b7 State immediately after reset b0 b7 b0 ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) ROM correction address 3 (high-order) ROM correction address 3 (low-order) 0 0 0 0 0 RCR2 RCR1RCR0 Left border control register (LBR) Right border control register (RBR) LBR6 LBR5 LBR4 LBR3 LBR2 LBR1 LBR0 RBR6 RBR5 RBR4 RBR3 RBR2 RBR1 RBR0 Top border control register (TBR) TBR7 TBR6 TBR5 TBR4 TBR3 TBR2 TBR1 TBR0 Bottom border control register (BBR) BBR7 BBR6 BBR5 BBR4 BBR3 BBR2 BBR1 BBR0 0016 Test register DA2-H register (DA2H) DA2-L register (DA2L) 0 0 ? ? ? ? ? ? ? ? 0016 0016 0016 0016 0016 0016 0016 ? ? 0016 0016 ? ? ? ? ? 0016 ? ? ? ? ? ? ? ?? ? ? ? Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 101 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Internal State of Processor Status Register and Program Counter at Reset < Bit allocation > < State immediately after reset > : Name Function bit 0 : “0” immediately after reset 1 : “1” immediately after reset ? : Indeterminate immediately after reset : : No function bit 0 : Fix to this bit to “0” (do not write to “1”) 1 : Fix to this bit to “1” (do not write to “0”) Register b7 Processor status register (PS) Program counter (PCH) Program counter (PCL) Bit allocation N V T B D I Z C State immediately after reset b0 b7 b0 ?????1?? Contents of address FFFF16 Contents of address FFFE16 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 102 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Structure of Register The figure of each register structure describes its functions, contents at reset, and attributes as follows: CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 00 11 Bit position Bit attributes(Note 2) Values immediately after reset release (Note 1) CPU mode register (CPUM) (CM) [Address 00FB16] B Name 0, 1 Processor mode bits (CM0, CM1) Functions b1 b0 Aft er r e R W RW 0 0 0 1 1 0: Single-chip mode 1: 0: Not available 1: 1 1 1 0 RW RW RW RW 2 Stack page selection bit (See note) (CM2) 0: 0 page 1: 1 page 3, 4 Fix these bits to “1.” 5 Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is “1.” b7 b6 Clock switch bits 6, 7 (CM6, CM7) 0 0: f(XIN) = 8 MHz 0 1: f(XIN) = 12 MHz 1 0: f(XIN) = 16 MHz 1 1: Do not set : Bit in which nothing is assigned Notes 1: Values immediately after reset release 0 ••••••••••••••••••“0” after reset release 1 ••••••••••••••••••“1” after reset release Indeterminate•••Indeterminate after reset release 2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : R••••••Read W••••••Write W ••••••Write enabled R ••••••Read enabled – ••••••Read disabled – ••••••Write disabled ✽ ••••••“0” can be set by software, but “1” cannot be set. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 103 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Addresses 00C116, 00C316, 00C516 Port Pi Direction Register b7b6 b5b4 b3 b2 b1b0 Port Pi direction register (Di) (i=0,1,2) [Addresses 00c116,00C316,00C516] b 0 1 2 3 4 5 6 7 Name Functions After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW Port Pi direction register 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode Address 00C716 Port P3 Direction Register b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (D3) [Address 00C716 ] B 0 1 2 Name Port P3 direction register Functions 0 : Port P30 input mode 1 : Port P30 output mode 0 : Port P31 input mode 1 : Port P31 output mode 0 : Port P32 input mode 1 : Port P32 output mode After reset R W 0 0 0 RW RW RW indeterminate R — 3, 4 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are indeterminate. 5 6 7 Port P3 direction register Port P30 output mode selection bit (P30S) Port P31 output mode selection bit (P31S) 0 : Port P35 input mode 1 : Port P35 output mode 0 : CMOS output 1 : N-channel open-drain output 0 : CMOS output 1 : N-channel open-drain output 0 0 0 RW RW RW Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 104 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00C916 Port P35 Output Mode Control Register b7 b6 b5 b4 b3 b2 b1 b0 00 0 Port P35 output mode control register (P3S) [Address 00C916 ] B Name Functions After reset RW 0 to 3 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are indeterminate. 4 Fix this bit to “0” Port P35 output mode selection bit (P35S) Fix these bits to “0” 0 : CMOS output 1 : N-channel open-drain output Indeterminate R — 0 RW 5 0 RW 6, 7 0 RW Address 00CB16 OSD Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 00 OSD port control register (PF ) [Address 00CB16] b Name Functions After reset R W 0 RW RW RW RW RW RW RW 0, 1 Fix these bits to “0” 2 3 4 5 6 7 Port P52 output signal selection bit (P52SEL) Port P53 output signal selection bit (P53SEL) Port P54 output signal selection bit (P54SEL) Port P55 output signal selection bit (P55SEL) Port P10 output signal selection bit (OUT2SEL) Fix this bit to “0” 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P55 output 0 : Port P10 signal output 1 : OUT2 output 0 0 0 0 0 0 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 105 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00CD16 Interrupt Input Polarity Register b7 b6 b5 b4 b3 b2 b1 b0 00 0 Interrupt input polarity register (IP) [Address 00CD16] b Name Function Function b1 b0 0 0 The clock for OSD is supplied by connecting RC or LC across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode. 0 1 Since the main clock is used as the clock for OSD, the oscillation frequency is limited. Because of this, the character size in width (horizonal) direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P33 and P34 respectively. 0 After reset R W 0 RW 0, 1 OSD clock selection bits (OCG0, OCG1) OSD oscillation frequency = f(XIN) 1 The clock for OSD is supplied by connecting LC across the pins OSC1 and OSC2. In the bi-scan mode, be sure to set this. The clock for OSD is supplied by connecting the following across the pins OSC1 and OSC2. However, it is not corresponding to the bi-scan mode. • a ceramic resonator only for OSD and a feedback resistor • a quartz-crystal oscillator only for OSD and a feedback resistor 0 0 0 0 0 RW RW RW RW RW 1 1 2 3 4 5 Fix this bit to “0.” INT1 polarity switch bit (POL1) INT2 polarity switch bit (POL2) INT3 polarity switch bit (POL3) 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 6, 7 Fix these bits to “0.” Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 106 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00D516 PWM Output Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 1 (PW) [Address 00D5 ] 16 B Name Functions 0 : Count source supply 0 DA1, DA2, PWM count source selection bit (PW0) 1 : Count source stop 0 : DA1 output 1 DA1 output/P35 1 : P35 output selection bit (PW1) 2 P00/PWM0 output selection bit (PW2) 3 P01/PWM1 output selection bit (PW3) 4 P02/PWM2 output selection bit (PW4) 5 P03/PWM3 output selection bit (PW5) 6 P04/PWM4 output selection bit (PW6) 7 P05/PWM5 output selection bit (PW7) 0: P00 output 1: PWM0 output 0: P01 output 1: PWM1 output 0: P02 output 1: PWM2 output 0: P03 output 1: PWM3 output 0: P04 output 1: PWM4 output 0: P05 output 1: PWM5 output After reset R W 0 RW 0 0 0 0 0 0 0 RW RW RW RW RW RW RW Address 00D616 PWM Output Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 00 00 PWM output control register 2 (PN) [Address 00D6 ] 16 B Name 0, 1 Fix these bits to “0.” 2 DA1 output polarity selection bit (PN3) 3 PWM output polarity selection bit (PN4) 4 DA2 output polarity selection bit (PN5) 5 P17/DA2 output selection bit (PN5) 6, 7 Fix these bits to “0.” Functions After reset R W 0 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Output LOW 1 : Output HIGH 0 : P17 1 : DA2 0 0 0 0 0 RW RW RW RW RW RW Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 107 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00D716 I2C Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 I2C data shift register (S0) [Address 00D716 ] B 0 to 7 Name Functions After reset Indeterminate RW RW D0 to D7 This is an 8-bit shift register to store receive data and write transmit data. Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave mode), keep an interval of 8 machine cycles or more. Address 00D816 I2C Address Register b7 b6 b5 b4 b3 b2 b1 b0 I2C address register (S0D) [Address 00D816] B 0 Name Read/write bit (RBW) Functions The last significant bit of address data is compared. 0: Wait the first byte of slave address after START condition (read state) 1: Wait the first byte of slave address after RESTART condition (write state) The address data is compared. After reset R W 0 R— 1 to 7 Slave address (SAD0 to SAD6) 0 RW Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 108 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00D916 I2C Status Register b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1) [Address 00D916] B 0 1 2 3 4 5 Name Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB) Functions 0 : Last bit = “0 ” 1 : Last bit = “1 ” (See note) After reset R W Indeterminate 0 0 R— R— R— R— RW RW RW 0 : No general call detected 1 : General call detected (See note) 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected (See note) 0 1 0 0 (See note) 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode 6, 7 Communication mode specification bits (TRX, MST) Note : These bits and flags can be read out, but cannnot be written. Address 00DA16 I2C Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D) [Address 00DA16] B 0 to 2 Name Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0: 8 1: 7 0: 6 1: 5 0: 4 1: 3 0: 2 1: 1 After reset R W 0 RW 3 4 5 I2C-BUS interface use enable bit (ESO) Data format selection bit(ALS) Addressing format selection bit (10BIT SAD) 0: Disabled 1: Enabled 0: Addressing format 1: Free data format 0: 7-bit addressing format 1: 10-bit addressing format b7 b6 Connection port (See note) 0 0: None 0 1: SCL1, SDA1 1 0: SCL2, SDA2 1 1: SCL1, SDA1, SCL2, SDA2 0 0 0 0 RW RW RW RW 6, 7 Connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1) Note: When using ports P11-P14 as I2C-BUS interface, the output structure changes automatically from CMOS output to N-channel open-drain output. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 109 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00DB16 I2C Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2) [Address 00DB16] B 0 to 4 Name Functions After reset R W 0 SCL frequency control bits Setup value of Standard clock High speed (CCR0 to CCR4) CCR4–CCR0 mode clock mode 00 to 02 03 04 05 06 1D 1E 1F ... RW Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3 17.2 16.6 16.1 333 250 400 (See note) 166 34.5 33.3 32.3 500/CCR value 1000/CCR value (at φ = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock 0 RW RW RW 6 7 0 0 Note: At 400 kHz in the high-speed clock mode, the duty is as below . “0” period : “1” period = 3 : 2 In the other cases, the duty is as below. “0” period : “1” period = 1 : 1 Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 110 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00DC16 Serial I/O Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 Serial I/O mode register (SM) [Address 00DC16] B Name Functions b1 b0 0 0: f(XIN)/4 0 1: f(XIN)/16 1 0: f(XIN)/32 1 1: f(XIN)/64 0: External clock 1: Internal clock 0: P20, P21 1: SCLK, SOUT After reset R W 0 RW 0, 1 Internal synchronous clock selection bits (SM0, SM1) 2 3 Synchronous clock selection bit (SM2) Serial I/O port selection bit (SM3) 0 0 RW RW 4 Fix this bit to “0.” 5 6 7 Transfer direction selection bit (SM5) Serial input pin selection bit (SM6) 0: LSB first 1: MSB first 0: Input signal from SIN pin. 1: Input signal from SOUT pin. 0 0 0 0 RW RW RW R— Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is “0.” Address 00DF16 A-D Control Register b7 b6 b5 b4 b3 b2 b1 b0 0 0 A-D control register (ADCON) [Address 00DF16] B 0 to 2 Name Analog input pin selection bits (ADIN0 to ADIN2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0 : A-D1 1 : A-D2 0 : A-D3 1 : A-D4 0 : A-D5 1 : A-D6 0 : A-D7 1 : A-D8 After reset R W 0 RW 3 4 5 6 7 A-D conversion completion bit (ADSTR) VCC connection selection bit (ADVREF) Fix this bit to “0.” 0: Conversion in progress 1: Convertion completed 0: OFF 1 : ON 1 0 0 Indeterm inate 0 RW RW RW R— RW Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. Fix this bit to “0.” Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 111 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00E016 Block H Register b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HP) [Address 00E016] B Name Functions After reset R W 0 RW 0 Control bits of horizontal Horizontal display start positions = Tdef1 + 4TOSC ✕ n to display start positions (n: setting value, Tdef1: 31TOSC, 5 (BHP0 to BHP5) TOSC: OSD oscillation cycle) (See note 1) 6, 7 Nothing is assigned. These bits are write disable bits. W h en t h e s e b i t s a r e re a d o u t, t h e v a l u e s a r e “0 . ” Note: The setting value synchronizes with the VSYNC. 0 R— Addresses 00E116 and 00E216 Block i V Register b7 b6 b5 b4 b3 b2 b1 b0 Block i V register (BiVP) (i = 1, 2) [Addresses 00E116 and 00E216] B Name Functions 0 Control bits of Vertical display start positions = Hdef + H ✕ n to vertical display (n: setting value, Hdef: 17H, H: HSYNC) 7 start positions (BiVP0 to BiVP7) (See note 1) Note: Set values except “0016” to BiVP. After reset R W Indeterminate R W Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 112 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00E316 SPRITE Control Register b7 b6 b5 b4 b3 b2 b1 b0 SPRITE control register (SC) [Address 00E316] B Name SC1 0 0 1 1 SC3 0 0 1 1 Functions SC0 0: Color 1: Color 0: Color 1: Color SC2 0: Color 1: Color 0: Color 1: Color register 1 register 2 register 3 register 4 After reset R W 0 RW 0, 1 SPRITE font 1 color register specification bit (SC0, SC1) 2, 3 SPRITE font 2 color register specification bit (SC2, SC3) 0 register 1 register 2 register 3 register 4 0 RW 4, 5 SPRITE font selection bit (SC4, SC5) SC5 SC4 Character code SPRITE1 SPRITE2 0 0 1 1 0 1 0 1 F816 FA16 FC16 FE16 F916 FB16 FD16 FF16 RW 6, 7 SPRITE/raster patterning control bit (SC6, SC7) (See note) SC7 0 0 1 1 SC6 0: Display OFF 1: Do not set 0: SPRITE display 1: Raster patterning display 0 RW Note : This bit is valid when bit 0 of the OSD control register to “1.” Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 113 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00E416 SPRITE H Register b7 b6 b5 b4 b3 b2 b1 b0 SPRITE H register (SHP) [Address 00E416] B Name Functions 0 Horizontal display Horizontal display start position to start position = Tdef2 + 2TOSC ✕ n 7 control bits of (n: setting value, Tdef2: 2TOSC, TOSC: OSD oscillation cycle) SPRITE OSD (SHP0 to SHP7) After reset R W 0 RW Notes 1: Set values except “0016” to “0216” to SHP. 2: When selecting raster patterning display, setting value is synchronized with VSYNC signal; when selecting SPRITE display, it is not synchronized. Address 00E516 SPRITE V Register b7 b6 b5 b4 b3 b2 b1 b0 SPRITE V register (SVP) [Address 00E516] B Name Functions After reset R W 0 Horizontal display Horizontal display start position Indeterminate R W to start position = Hdef + H ✕ n 7 control bits of (n: setting value, Hdef: 17H, H: HSYNC) SPRITE OSD (SVP0 to SVP7) (See note 1) Note: Set values except “0016” to the SVP. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 114 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Addresses 00E616 to 00E916 and 00EC16 to 00EF16 Color Register i b7 b6 b5 b4 b3 b2 b1 b0 Color register i (CO1 to CO8) (i=1 to 8) [Addresses 00E616 to 00E916, 00EC16 to 00EF16] B 0 1 2 3 4 5 6 7 Name R signal output selection bit (COi0) G signal output selection bit (COi1) B signal output selection bit (COi2) Functions 0: No output 1: Output 0: No output 1: Output 0: No output 1: Output After re set RW Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W Indeterminate R W 0 R— R signal output (background) 0: No output selection bit (COi3) 1: Output G signal output (background) 0: No output selection bit (COi4) 1: Output B signal output (background) 0: No output 1: Output selection bit (COi5) OUT1 output control bit (COi6) 0: Character output 1: Blank output Nothing is assined. This bit is a write disable bit. When this bit is read out, the value is “0.” Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 115 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00EA16 OSD Control Register b7 b6 b5 b4 b3 b2 b1 b0 OSD control register (OC) [Address 00EA16] B 0 1 Name OSD control bit (OC0) (See note 1) Border type selection bit (OC1) Functions 0 : All-blocks display OFF 1 : All-blocks display ON 0 : All bordered 1 : Shadow bordered (See note 2) b3 0 0 1 1 b2 (See notes 3 and 4) 0 : Standard 1 : Standard + 1TOSC 0 : Standard + 2TOSC 1 : Standard + 3TOSC After reset R W 0 0 0 RW RW RW 2, 3 Window horizontal position minute adjustment bit (OC2, OC3) 4 Window control bit (OC4) 0 : Window OFF 1 : Window ON 0 0 RW RW 5 Scan mode selection 0 : Normal scan mode bit (OC5) 1 : Bi-scan mode (See note 5) 6 Raster color OUT1 control bit (OC6) 7 Raster color OUT2 control bit (OC7) 0 : No output 1 : Output 0 : No output 1 : Output 0 0 RW RW Notes 1 : Even this bit is switched during display, the display screen remains unchanged until a rising (falling) of the next VSYNC. 2 : Shadow border is output at right and bottom side of the font. 3 : TOSC = OSD oscillation cycle 4 : These bits are vallid for both left border and right border (for detail, refer to “(8) Window Function.”) 5 : When setting to bi-scan mode, connect LC between pins OSC1 and OSC2. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 116 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00EB16 OSD I/O Polarity Register b7 b6 b5 b4 b3 b2 b1 b0 OSD I/O polarity register (OPC) [Address 00EB16] B 0 1 2 3 4 5 6 7 Name HSYNC input polarity switch bit (OPC0) VSYNC input polarity switch bit (OPC1) Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input Af t er r e R W 0 0 0 0 0 0 0 0 RW RW RW R W R/G/B output polarity switch 0 : Positive polarity output 1 : Negative polarity output bit (OPC2) OUT1 output polarity switch bit (OPC3) OUT2 output polarity switch bit (OPC4) Raster color R control bit (OPC5) Raster color G control bit (OPC6) Raster color B control bit (OPC7) 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0 : No output 1 : Output 0 : No output 1 : Output 0 : No output 1 : Output RW RW RW RW Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 117 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00F416 Timer Mode Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 1 (TM1) [Address 00F416] B 0 1 Name Timer 1 count source selection bit 1 (TM10) Timer 2 count source selection bit 1 (TM11) Functions 0: f(XIN)/16 1: f(XIN)/4096 0: Interrupt clock source 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop After reset R W 0 0 0 0 0 0 RW RW RW RW RW RW 2 Timer 1 count stop bit (TM12) 3 Timer 2 count stop bit (TM13) 4 Timer 2 internal count source 0: f(XIN)/16 1: Timer 1 overflow selection bit 2 (TM14) 5 Timers 3 and 4 auto set disable bit (TM15) 0: Auto set enabled 1: Auto set disabled 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” 0 R— Address 00F516 Timer Mode Register 2 b7 b6 b5 b4 b3 b2 b1 b0 Timer mode register 2 (TM2) [Address 00F516] B Name 0 Timer 3 count source selection bit (TM20) 1 Timer 4 internal interrupt count source selection bit (TM21) Functions 0 : f(XIN)/16 1 : External clock source 0 : Timer 3 overflow signal 1 : f(XIN)/16 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Internal clock source 1: f(XIN)/2 After reset R W 0 RW 0 RW 2 Timer 3 count stop bit (TM22) 3 Timer 4 count stop bit (TM23) 4 Timer 4 count source selection bit (TM24) 5 0 0 0 0 0 RW RW RW RW R— Timer 3 external count 0: TIM3 pin input source selection bit (TM25) 1: HSYNC pin input 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are “0.” Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 118 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Addresses 00F916 and 00FA16 Block i Control Register b7 b6 b5 b4 b3 b2 b1 b0 Block i control register (BiC) (i = 1, 2) [Addresses 00F916, 00FA16] B Name b2 ✕ 0 0 1 1 b1 0 0 1 0 1 b0 0 1 0 1 0 Functions After reset R W Display mode Indeterminate R W Display OFF OSD mode (no border) BUTTON mode (no border) OSD mode (border) BUTTON mode (border) Indeterminate R W 0 Display mode to selection bits 2 (BiC0 to BiC2) Dot size 3, 4 Dot size selection bit b4 b3 (BiC3, BiC4) 00 1TOSC ✕ 1H 01 Do not set 10 2TOSC ✕ 2H 11 3TOSC ✕ 3H 5 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are “0.” 7 Notes 1 : TOSC = OSD oscillation cycle 2 : H = HSYNC 0 R— Address 00FB16 CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 00111 00 CPU mode register (CM) [Address 00FB16] B Name b1 b0 Functions 0 0 1 1 0: Single-chip mode 1: 0: Not available 1: After reset R W 0 RW 0, 1 Processor mode bits (CM0, CM1) 2 Stack page selection bit (CM2) (See note) 3 to 5 Fix these bits to “1.” 6, 7 Fix these bits to “0.” 0: 0 page 1: 1 page 1 1 0 RW RW RW Note: This bit is set to “1” after the reset release. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 119 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 00FC16 Interrupt Request Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B Name 0 Timer 1 interrupt request bit (TM1R) 1 2 3 4 5 6 7 Functions After reset 0 0 : No interrupt request issued 1 : Interrupt request issued 0 Timer 2 interrupt 0 : No interrupt request issued request bit (TM2R) 1 : Interrupt request issued 0 Timer 3 interrupt 0 : No interrupt request issued request bit (TM3R) 1 : Interrupt request issued 0 Timer 4 interrupt 0 : No interrupt request issued request bit (TM4R) 1 : Interrupt request issued OSD interrupt request 0 : No interrupt request issued 0 1 : Interrupt request issued bit (OSDR) VSYNC interrupt 0 0 : No interrupt request issued request bit (VSCR) 1 : Interrupt request issued 0 Multi-master I2C-BUS interface 0 : No interrupt request issued interrupt request bit (IICR) 1 : Interrupt request issued INT3 external interrupt 0 : No interrupt request issued 0 request bit (IT3R) 1 : Interrupt request issued RW R✽ R✽ R✽ R✽ R✽ R✽ R✽ R✽ ✽: “0” can be set by software, but “1” cannot be set. Address 00FD16 Interrupt Request Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B Name Functions After reset 0 INT1 external interrupt 0 : No interrupt request issued 0 1 : Interrupt request issued request bit (IT1R) 0 1 INT2 external interrupt 0 : No interrupt request issued 1 : Interrupt request issued request bit (IT2R) 2 Serial I/O interrupt 0 0 : No interrupt request issued request bit (S1R) 1 : Interrupt request issued 0 3 SPRITE OSD interrupt 0 : No interrupt request issued request bit (SPR) 1 : Interrupt request issued 0 4 f(XIN)/4096 interrupt 0 : No interrupt request issued request bit (MSR) 1 : Interrupt request issued 5 Nothing is assigned. This bit is a write disable bit. 0 When this bit is read out, the value is “0.” 0 6 A-D conversion interrupt 0 : No interrupt request issued request bit (ADR) 1 : Interrupt request issued 7 Fix this bit to “0.” 0 RW R✽ R✽ R✽ R✽ R✽ R— R✽ RW ✽: “0” can be set by software, but “1” cannot be set. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 120 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Addresses 00FE16 Interrupt Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW 0 Timer 1 interrupt enable bit (TM1E) 1 Timer 2 interrupt enable bit (TM2E) 2 Timer 3 interrupt enable bit (TM3E) 3 Timer 4 interrupt enable bit (TM4E) 4 OSD interrupt enable bit (OSDE) 5 VSYNC interrupt enable bit (VSCE) 6 Multi-master I2C-BUS interface interrupt enable bit (IICE) 7 INT3 external interrupt enable bit (IT3E) Address 00FF16 Interrupt Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt control register 2 (ICON2) [Address 00FF16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW R— 0 INT1 external interrupt enable bit (IT1E) 1 INT2 external interrupt enable bit (IT2E) 2 Serial I/O interrupt enable bit (S1E) SPRITE OSD interrupt 3 enable bit (SPE) 4 f(XIN)/4096 interrupt enable bit (MSE) 5 Fix this bit to “0.” 6 A-D conversion interrupt 0 : Interrupt disabled enable bit (ADE) 1 : Interrupt enabled Nothing is assigned. This bit is a write disable 7 bit. When this bit is read out, the value is “0.” Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 121 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 021B16 ROM Correction Enable Register b7 b6 b5 b4 b3 b2 b1 b0 00000 ROM correction enable register (RCR) [Address 021B16] B 0 1 2 3 to 7 Name Vector 1 enable bit (RCR0) Vector 2 enable bit (RCR1) Vector 3 enable bit (RCR2) Fix these bits to “0.” Functions 0: Disabled 1: Enabled 0: Disabled 1: Enabled 0: Disabled 1: Enabled After reset R W 0 0 0 RW RW RW RW 0 Address 024016 Left Border Control Register b7 b6 b5 b4 b3 b2 b1 b0 Left border control register (LBR) [Address 024016] B 0 to 6 7 Name Control bits of left border (LBR0 to LBR6) Functions Left border position = Tdef4 + 4TOSC ✕ n + 1TOSC ✕ WH (n: setting value, Tdef4: 4TOSC, TOSC: OSD oscillation cycle, WH: value (0 to 3) of window horizontal position minute adjustment bit) After re set R W 0 R W Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is indeterminate. 0 R — Note: Set values fit for LBR ≤ RBR. Address 024116 Right Border Control Register b7 b6 b5 b4 b3 b2 b1 b0 Right border control register (RBR) [Address 024116] B 0 to 6 7 Name Control bits of left border (RBR0 to RBR6) Functions Right border position = Tdef4 + 4TOSC ✕ n + 1TOSC ✕WH (n: setting value, Tdef4: 4TOSC, TOSC: OSD oscillation cycle, WH: value (0 to 3) of window horizontal position minute adjustment bit) After re set R W 0 R W Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is indeterminate. 0 R — Note: Set values fit for LBR ≤ RBR. Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 122 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP Address 024516 Top Border Control Register b7 b6 b5 b4 b3 b2 b1 b0 Top border control register (TBR) [Address 024516] B Name Functions 0 Control bits of Top border position = Hdef + H ✕ n to top border (n: setting value, Hdef: 17H, H: HSYNC) 7 (TBR0 to TBR7) Notes 1: Set values except “0016” to TBR. 2: Set values fit for TBR ≤ BBR. After reset R W Indeterminate R W Address 024616 Bottom Border Control Register b7 b6 b5 b4 b3 b2 b1 b0 Bottom border control register (BBR) [Address 024616] B Name Functions 0 Control bits of Bottom border position = Hdef + H ✕ n to bottom border (n: setting value, Hdef: 17H, H: HSYNC) 7 (BBR0 to BBR7) Notes 1: Set values except “0016” to BBR. 2: Set values fit for TBR ≤ BBR. After reset R W Indeterminate R W Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 123 of 124 M37225M6/M8/MA/MC-XXXSP, M37225ECSP 19. PACKAGE OUTLINE 42P4B EIAJ Package Code SDIP42-P-600-1.78 MMP JEDEC Code – Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy Plastic 42pin 600mil SDIP 42 22 1 21 Symbol D e SEATING PLANE b1 b b2 A A1 A2 b b1 b2 c D E e e1 L Dimension in Millimeters Min Nom Max – – 5.5 0.51 – – – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 – 1.778 – – 15.24 – 3.0 – – 0° – 15° A Rev.1.00 Nov 01, 2000 REJ03B0136-0100Z page 124 of 124 A1 L A2 e1 E c REVISION HISTORY Rev. Date Page 1.00 Nov 01, 2000 – First edition issued M37225M6/M8/MA/MC–XXXSP, M37225ECSP Description Summary A-1 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. 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